SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Internal Look-Ahead Circuitry for Fast
Counting
D
Carry Output for N-Bit Cascading
D
Fully Synchronous Operation for Counting
description
This synchronous, presettable, 4-bit binary
counter has internal carry look-ahead circuitry
for use in high-speed counting designs.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that normally are associated with asynchronous (ripple-clock) counters. However,
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is synchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop outputs
to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. T ransitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74F163AN SN74F163AN
0°Cto70°C
SOIC D
Tube SN74F163AD
F163A
0°C
to
70°C
SOIC
–
D
Tape and reel SN74F163ADR
F163A
SSOP – DB Tape and reel SN74F163ADBR F163A
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D, DB, OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
state diagram
0
15
14
13
12
1234
5
6
7
891011
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
3R
G2
1, 3D
M1
1, 2T/C3
3R
G2
1, 3D
M1
1, 2T/C3
3R
G2
1, 3D
M1
1, 2T/C3
3R
G2
1, 3D
M1
1, 2T/C3
1
9
10
7
2
3
4
5
6
15
14
13
12
11
CLR
LOAD
ENT
ENP
CLK
A
B
C
D
RCO
QA
QB
QC
QD
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol, each flip-flop
3R
G2TE Q1
1, 3DD
M1LOAD
Q2
1, 2T/C3
R
CLK
Q1
Q2
logic diagram, each flip-flop (positive logic)
R
CLK
D
LOAD
TE
(Toggle
Enable) Q1
Q2
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequences
The following timing sequence is illustrated below:
1. Clear outputs to zero
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear Preset
Count Inhibit
12 13 14 15 0 1 2
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state –0.5 V to VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –1 mA
IOL Low-level output current 20 mA
TAOperating free-air temperature 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 V
VOH
VCC = 4.5 V, IOH = –1 mA 2.5 3.4
V
V
OH VCC = 4.75 V, IOH = –1 mA 2.7
V
VOL VCC = 4.5 V, IOL = 20 mA 0.3 0.5 V
IIVCC = 5.5 V, VI = 7 V 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 µA
ENP, CLK, A, B, C, D –0.6
IIL ENT, LOAD VCC = 5.5 V, VI = 0.5 V –1.2 mA
CLR –1.2
IOS§VCC = 5.5 V, VO = 0 –60 –150 mA
ICC VCC = 5.5 V 37 55 mA
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°CMIN MAX UNIT
MIN MAX
fclock Clock frequency 0 100 0 90 MHz
CLK high or low (loading) 5 5
twPulse duration
CLK (counting)
High 4 4 ns
CLK
(counting)
Low 6 7
Data before CLK↑High or low 5 5
LOAD and CLR before CLK↑
High 11 11.5
tsu Setup time
LOAD
an
d
CLR
b
e
f
ore
CLK↑
Low 8.5 9.5 ns
ENP and ENT before CLK↑
High 11 11.5
ENP
and
ENT
before
CLK↑
Low 5 5
Data after CLK↑High or low 2 2
th
Hold time
LOAD and CLR after CLK↑
High 2 2
ns
t
h
Hold
time
LOAD
an
d
CLR
a
ft
er
CLK↑
Low 0 0
ns
ENP and ENT after CLK↑High or low 0 0
switching characteristics (see Note 4)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 5 V,
CL = 50 PF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V TO 5.5 V,
CL = 50 PF,
RL = 500Ω,
TA = MIN TO MAX†UNIT
MIN TYP MAX MIN MAX
fmax 100 120 90 MHz
tPLH
CLK (LOAD high)
Any Q
2.7 5.1 7.5 2.7 8.5
ns
tPHL
CLK
(LOAD
hi
g
h)
A
ny
Q
2.7 7.1 10 2.7 11
ns
tPLH
CLK (LOAD low)
Any Q
3.2 5.6 8.5 3.2 9.5
ns
tPHL
CLK
(LOAD
l
ow
)
A
ny
Q
3.2 5.6 8.5 3.2 9.5
ns
tPLH
CLK
RCO
4.2 9.6 14 4.2 15
ns
tPHL
CLK
RCO
4.2 9.6 14 4.2 15
ns
tPLH
ENT
RCO
1.7 4.1 7.5 1.7 8.5
ns
tPHL
ENT
RCO
1.7 4.1 7.5 1.7 8.5
ns
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 4: Load circuits and waveforms are shown in Figure 1.
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈3.5 V
0 V
VOL + 0.3 V
≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
Open
7 V
Open
7 V
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤ 2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 7 V
500 Ω
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH – 0.3 V
500 Ω
500 Ω
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74F163AD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163ADE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163ADR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74F163AN3 OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74F163ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74F163ANSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74F163ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74F163ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74F163ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74F163ADR SOIC D 16 2500 333.2 345.9 28.6
SN74F163ANSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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