Order this data sheet by MTM10N12L/D MOTOROLA = SEMICONDUCTOR TECHNICAL DATA . 7 Designers Data Sheet MTM10N15L B a Power Field Effect Transistors MTP10N12L N-Channel Enhancement MTP10N 15L Mode Silicon Gate TMOS These Logic Level TMOS Power FETs are designed for high TMOS POWER FETs speed power switching applications such as switching regulators, ~ ~ LOGIC LEVEL converters, solenoid and relay drivers. 10 AMPERES e Low Drive Requirement to Interface Power Loads to Logic Level 'DS(on) = 0.3 OHM ICs or Microprocessors VGs(th) = 2 Volts max TMOoS 120 and 150 VOLTS Silicon Gate for Fast Switching Speeds Switching Times Specified at 100C @ Designers Data ipss, VpS(on)- VGS(th) and SOA Specified D at Elevated Temperature @ Rugged SOA is Power Dissipation Limited Source-to-Drain Diode Characterized for Use With Inductive Loads MAXIMUM RATINGS G . MTM10N12L | MTM10N15L : Rating Symbol | wrPiont2L | MTPIoNISL | UNit ; Drain-Source Voltage Voss 120 150 Vde Drain-Gate Voltage (Rgs = 1 MQ) VDGR 120 150 Vdc Gate-Source Voltage Ves +15 Vde Drain Current Continuous Ip 10 Adc Pulsed IDM 28 Total Power Dissipation @ Tc = 25C Pp 75 Watts Derate above 25C 0.6 wre Operating and Storage Temperature Range Ty. Tstg 65 to 150 c MTM10N12L THERMAL CHARACTERISTICS MTM10N15L Thermal Resistance / C/W CASE 1-04 Junction to Case ReJc 1.67 TO-204AA Junction to Ambient MTM10N12/15L ReJA 30 (TO-3) MTP10N12/15L 62.5 Maximum Lead Temp. for Soldering TL 275 a Purposes, 1/8 from case for 5 seconds ELECTRICAL CHARACTERISTICS (Tc = 25C unless otherwise noted) Characteristic Symbol | Min Max =| Unit | OFF CHARACTERISTICS Drain-Source Breakdown Voltage V(BR)DSS Vdc MTP10N12L (Veg = 0, Ip = 1 mA) MTM/MTPION12L 120 MTP10N15L MTM/MTP10N15L 150 _ CASE 221A-02 Zero Gate Voltage Drain Current Ipss pAdc TO-220AB (Vps = Rated Vpss. Ves = 9) _ i (Vps = Rated Vpss, Ves = 0, Ty = 125C) _ 50 (continued) Designer's Data for Worst Case Conditions The Designers Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves representing boundaries on device characteristics are given to facilitate worst case design. TMOS and Designer's are trademarks of Motorola Inc. (S) MOTOROLA MOTOROLA INC., 1986 DS3737ELECTRICAL CHARACTERISTICS continued (Tc = 25C unless otherwise noted) Characteristic Symbol Min Max Unit OFF CHARACTERISTICS (continued) Gate-Body Leakage Current, Forward IGSSF _ 100 nAdc (VG@sF = 15 Vde, Vps = 0) Gate Body Leakage Current, Reverse IGSSR - 100 nAdc (Vesr = 15 Vde, Vps = 0) ON CHARACTERISTICS Gate Threshold Voltage VGSith) Vde (Vps = VGs. Ip = 1 mA) 1 2 (Ty = 100C) 0.75 1.5 Static Drain-Source On-Resistance (Vgg = 5 Vde, ip = 5 Adc) 'DS(on)} _ 0.3 Ohm Drain-Source On-Voltage (Vgg = 5 V) - VbDS(on) Vdc (Ip = 10 Adc) 4 (Ip = 5 Adc, Ty = 700C) - 3.5 Forward Transconductance (Vps = 10 V, Ip = 5 A) OFS 4 _ mhos DYNAMIC CHARACTERISTICS Input Capacitance Vos = 25, Ves = 0, f = 1 MHz Ciss 1200 pF VG6s = 15 V,Vps = 0, f = 1 MHz _ 2800 Reverse Transfer Capacitance Vos = 25 V, Ves = 0, f = 1 MHz Crss _ 60 pF V6s = 15 V, Vps = 0, f = 1 MHz _ 2400 Output Capacitance Vos = 25V, Ves = 0, f = 1 MHz Coss _ 250 pF SWITCHING CHARACTERISTICS (Ty = 100C) Turn-On Delay Time tdion) _ 60 ns Rise Time (Vpp = 25 V, Ip = 7.5A, . tr _~ 135 Turn-Off Delay Time Ves = 5 V, Rgen = 50 ohms) tdloff) _ 135 Fall Time tf _ 135 Total Gate Charge (Vps = 0.8 Rated Vpss, Qg 14 (typ) 20 nc Gate-Source Charge Ip = 15 A, Vg@g = 5 Vdc} Ogs 7 (typ) Gate-Drain Charge See Figures 6 and 10. Qga 7 (typ) _ SOURCE DRAIN DIODE CHARACTERISTICS Forward On-Voltage (lg = Rated Ip, Veg = 0) Vsp 1.6 (typ) | _ | Vdc Forward Turn-On Time See Figures 14 and 15. ton Limited by stray inductance Reverse Recovery Time ter 150 (typ) | > | ns INTERNAL PACKAGE INDUCTANCE (TO-204) Internal Drain Inductance Lq 5 (Typ) _ nH (Measured from the contact screw on the header closer to the source pin and the center of the die) Internal Source Inductance Ls 12.5 (Typ) _ (Measured from the source pin, 0.25 from the package to the source bond pad) INTERNAL PACKAGE INDUCTANCE (TO-220) Internal Drain inductance Lg nH (Measured from the contact screw on tab to center of die) 3.5 (Typ) _ (Measured from the drain lead 0.25 from package to center of die) 4.5 (Typ) Internal Source Inductance Ls 7.5 (Typ) _ (Measured from the source lead 0.25 from package to source bond pad.) *Pulse Test: Pulse Width < 300 ps, Duty Cycle < 2%. MOTOROLA MTM10N12L MTM10N15L @ MTP10N12L @ MTP10N15LFORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain-to- source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limi- tations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction tem- perature of 150C. Limitations for repetitive pulses at var- ious case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, Transient Thermal Resistance-General Data and Its Use provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 12 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, Ipjq and the breakdown voltage, ViBR)DSS- The switching SOA shown in Figure 12 is applicable for both turn-on and turn-off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: TJ(max) Tc Rec 30 15 10 = Vgg = 10V = & IsiNGLE 5 Fa To = 25C 2 ce 3 3 = 'DS(on) Tee = = 15[ PACKAGE LIMIT - = & | THERMAL LIMIT & Ty = 150C 2 1 A 0.6 0.3 2 4 6 10 20 40 60 100 200 0 20 40 60 80 100 120 140 160 Vps, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Vps, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Figure 12. Maximum Rated Switching Biased Safe Operating Area Safe Operating Area OUTLINE DIMENSIONS CASE 1-04 CASE 221A-02 TO-204AA TO-220AB A (T0-3) roe |e +f w fe / D yo SEATING PLANE z : NOTES: 2, POSITIONAL TOLERANCE FOR HOLE Q: STYLE 3: PINT GATE $0.25 (0.010) ] w]v ] 2. SOURCE 3. POSITIONAL TOLERANCE FOR LEADS: CASE DRAIN 6 0.30(0.012) @[ wv @[ 0 @] 1. DIAMETER V AND SURFACE W ARE DATUMS. NOTES: PIN 1. GATE 1. DIMENSION H APPLIES TO ALL LEADS. 2. DIMENSION L APPLIES TO LEADS 1 AND 3. 3. DIMENSION 2 DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. 4, DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. MTM10N12L @ MTMI0N15L MTP10N12L MTP1ON15L MOTOROLArt}, TRANSIENT THERMAL RESISTANCE "DSton} ON RESISTANCE (NORMALIZED) = mp = Rh S co S > BR w KR = VBR(DSS) DRAIN-SOURCE BREAKDOWN VOLTAGE (VOLTS) (NORMALIZED) 0.9 ~ 50 0 50 100 150 50 0 50 100 160 Ty, JUNCTION TEMPERATURE (C) Ty, JUNCTION TEMPERATURE (C) Figure 7. On-Resistance Variation Figure 8. Breakdown Voltage Variation With Temperature With Temperature (NORMALIZED) 03 02 P; 0.1 : (Pk) Rescit) = rit} Rec t Rejc = 1.67CW MAX 0.05 D CURVES APPLY FOR POWER ye PULSE TRAIN SHOWN t READ TIME AT ty Tyo) Te = Piok) Resctt 0.02 DUTY CYCLE, D = typ lPK) ~ Te = Plpk) Reucit 0.01 001 002 005 01 02 06.1 2 5 0 ~20 50 100 ~~200 500 1000 t, TIME (ms) Figure 9. Thermal Response +18V Vop 9 mA F same mM. 47k 1 | 10 he anil V 15V = + re 1 T ote " +{ 2N3904 ap 0.1 He 2N3904 100k ernie || 47k 100 BEAD but Vin = 15 Vpk; PULSE WIDTH < 100 us, DUTY CYCLE = 10% Figure 10. Gate Charge Test Circuit MOTOROLA MTM10N12L @ MTM10N15L e MTP10N12L e MTP10N15LTYPICAL CHARACTERISTICS = = to = ay b Ip, ORAIN CURRENT (AMPS) S co Vsith). GATE THRESHOLD VOLTAGE (NORMALIZED) 3V o2- 0 2 4 6 8 10 50 0 50 100 150 Vps, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Ty, JUNCTION TEMPERATURE (C) Figure 1. On-Region Characteristics Figure 2. Gate-Threshold Voltage Variation With Temperature Ves t Vos 2500 = 2000 f Crss 2 = Cc = s & 3 1500 = = > S z = 1000 = S = 500 Crsg 0 0 2 4 6 10 15 oO 5 15 5 35 Vg, GATE-TO-SOURCE VOLTAGE (VOLTS) GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 3. Transfer Characteristics Figure 4. Capacitance Variation With Voltage Ty = 100C 25C fOS{on}. ORAIN-TO-SOURCE RESISTANCE (OHMS) Vgg, GATE-TO-SOURCE VOLTAGE (VOLTS) 0 3 6 9 12 15 0 4 8 12 16 20 Ip, DRAIN CURRENT (AMPS) , Qg, TOTAL GATE CHARGE (nC) Figure 5. On-Resistance Variation With Drain Current Figure 6. Gate Charge versus Gate-To-Source Voltage MTM10N12L @ MTM10N15L @ MTP10N12L MTP10N15L MOTOROLATMOS SOURCE-TO-DRAIN DIODE CHARACTERISTICS In the fabrication of a TMOS FET, a diode is formed across the source-to-drain terminals as shown in Figure 13. Reversal of the drain voltage will cause current flow in the reverse direction. This diode may be used in circuits BODY DIODE Figure 13. TMOS FET With Source-To-Drain Diode NOTE: DUT is Shown as an N-Channel TMOS but can also be a P-Channel when appropriately connected. DUT Driver is the same device as DUT Diode (or Com- plement for P-Channel DUT Diode) +15V 100 pF dt 1N914 Mt ~ ~ a Ry: DUTY CYCLE = CONTROL f = 25 kHz TO SET D-S DIODE CURRENT Is, ADJUST Ry AND/OR Vcc Ig, NORMALIZED SOURCE CURRENT MJE200 requiring external fast recovery diodes, therefore, typical characteristics of the on voltage, forward turn-on and reverse recovery times are given. 25% IRM(REC) IRMIREC) TIME Figure 14. Diode Switching Waveform +15V O Vcc K L = 100 pH, 30A (2,200 pH, 15.A INDUCTORS IN PARALLEL) J. W. MILLER: D7828 Figure 15. TMOS Diode Switching Test Circuit _ (AA) MOTOROLA MTM10N12L e MTM10N15L MTP10N12L e@ MTP10N15LThis page intentionally left blank.Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. a (S) MOTOROLA 20446 PRINTED IN USA (1994) MPS/POD S3737 MTM10N12L/D