© 2008 Microchip Technology Inc. DS21810F-page 1
MCP6271/1R/2/3/4/5
Features
• Gain Bandwidth Product: 2 MHz (typical)
• Supply Current: IQ = 170 µA (typical)
• Supply Voltage: 2.0V to 6.0V
• Rail-to-Rail Input/Outp ut
• Extended Temperature Range: –40°C to +125°C
• Available in Single, Dual and Quad Packages
• Parts with Chip Select (CS)
-Single (MCP6273)
-Dual (MCP6275)
Applications
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery Powered Systems
Available Tools
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circui t Designer & Simulator
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Description
The Microchip Technology Inc. MCP6271/1R/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 2 MHz
Gain Bandwidth Product (GBWP) and a 65° Phase
Margin. This family also op erates from a single supply
voltage as low as 2.0V, while drawing 1 70 µA (typical)
quiescent current. The MCP6271/1R/2/3/4/5 supports
rail-to-rail input and output swing, with a common mode
input voltage range of VDD +300mV to V
SS –300mV.
This family of op amps is designed with Microchip’s
advanced CMOS process.
The MCP6275 has a Chip Select input (CS) for dual op
amps in an 8-pin package and is manufactured by
cascading two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in low power mode.
The MCP6271/1R/2/3/4/5 family operates over the
Extended Temperature Range of –40°C to +125°C,
with a power supply range of 2.0V to 6.0V.
Package Types
VIN–
MCP6271
PDIP, SOIC, MSOP
VDD
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
VIN+
VSS
VOUT
+-
-+
-
+
VIN–
MCP6273
PDIP, SOIC, MSOP
VDD
1
2
3
4
8
7
6
5
-
+
NC
CS
NC
VIN+
VSS
VOUT
VINA–
MCP6272
PDIP, SOIC, MSOP
VOUTB
1
2
3
4
8
7
6
5VINB+
VDD
VOUTA
VINA+
VSS
VINB–
-
+-
+
VINA–
MCP6274
PDIP, SOIC, TSSOP
VIND–
1
2
3
4
14
13
12
11 VSS
VOUTD
VOUTA
VINA+
VDD
VIND+
5
6
7
10
9
8
-+-
+
+
--
+
VINB+VINC+
VOUTC
VINB–
VOUTB
VINC–
VINA–
MCP6275
PDIP, SOIC, MSOP
VOUTB
1
2
3
4
8
7
6
5CS
VDD
VOUTA/VINB+
VINA+
VSS
VINB–
VSS
MCP6273
SOT-23-6
CS
1
2
3
6
5
4
VDD
VOUT
VIN+V
IN–
-
+
VSS
MCP6271
SOT-23-5
1
2
3
5
4
VDD
VOUT
VIN+V
IN–-
+
VDD
MCP6271R
SOT-23-5
1
2
3
5
4
VSS
VOUT
VIN+V
IN–
170 µA, 2 MHz Rail-to-Rail Op Amp
MCP6271/1R/2/3/4/5
DS21810F-page 2 © 2008 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) ††.. VSS –1.0VtoV
DD +1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Junction Temperature (TJ) ..... ..................... ................+150°C
ESD Protection On All Pins (HBM/MM)................ ≥ 4 kV/400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2, RL=10kΩ to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset (Note 1)
Input Offset Voltage VOS –3.0 — +3.0 mV VCM = VSS
Input Offset Voltage
(Extended Temperature) VOS –5.0 — +5.0 mV TA = –40°C to +125°C, VCM = VSS
Input Offset Temperature Drift ΔVOS/ΔTA—±1.7—µV/°CT
A = –40°C to +125°C, VCM = VSS
Power Supply Rejection Ratio PSRR 70 90 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB— ±1.0 — pA Note 2
At Temperature IB— 50 200 pA TA= +85°C (Note 2)
At Temperature IB—2 5nAT
A= +125°C (Note 2)
Input Offset Current IOS — ±1.0 — pA Note 3
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF Note 3
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Voltage Range VCMR VSS −0.15 — VDD +0.15 V V
DD = 2.0V (Note 5)
VCMR VSS −0.30 — VDD +0.30 V V
DD = 5.5V (Note 5)
Common Mode Rejection Ratio CMRR 70 85 — dB VCM = –0.3V to 2.5V, VDD = 5V
(Note 6)
Common Mode Rejection Ratio CMRR 65 80 — dB VCM = –0.3V to 5.3V, VDD = 5V
(Note 6)
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V,
VCM =V
SS (Note 1)
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS +100mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to
VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
has a voltage range specified by VOH and VOL.
5: Set by design and characterization.
6: Does not apply to op amp B of the MCP6275.
7: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.
© 2008 Microchip Technology Inc. DS21810F-page 3
MCP6271/1R/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
FIGURE 1-1: Timing Diagram for the Chip
Select (CS) pin on the MCP6273 and MCP6275.
Output
Maximum Output Voltage Swing VOL, VOH VSS +15 — V
DD −15 mV 0.5V input overdrive (Note 4)
Output Short Circuit Current ISC —±25—mA
Power Supply
Supply Voltage VDD 2.0 — 6.0 V
Quiescent Current per Amplifier IQ100 170 240 µA IO = 0
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2, RL=10kΩ to VL, CL= 60 pF and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 2.0 — MHz
Phase Margin PM — 65 — ° G = +1 V/V
Slew Rate SR — 0.9 — V/µs
Noise
Input Noise Voltage Eni —4.6 — µVP-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —20 — nV/√Hz f = 1 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM =V
DD/2,
VOUT ≈VDD/2, VL = VDD/2, RL=10kΩ to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS +100mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to
VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
has a voltage range specified by VOH and VOL.
5: Set by design and characterization.
6: Does not apply to op amp B of the MCP6275.
7: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.
VIL
High-Z
tON
VIH
CS
tOFF
VOUT
-0.7 µA
High-Z
ISS
ICS
0.7 µA 0.7 µA
-0.7 µA
-170 µA
10 nA
(typical) (typical) (typical)
(typical) (typical)
(typical)
MCP6271/1R/2/3/4/5
DS21810F-page 4 © 2008 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
MCP6273/MCP6275 CHIP SELECT SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS =GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA–40 — +125 °C
Operating Temperature Range TA–40 — +125 °C Note
Storage Temperature Range TA–65 — +150 °C
Thermal Package Resist ances
Thermal Resistance, 5L-SOT-23 θJA —256—°C/W
Thermal Resistance, 6L-SOT-23 θJA —230—°C/W
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA —163—°C/W
Thermal Resistance, 8L-MSOP θJA —206—°C/W
Thermal Resistance, 14L-PDIP θJA —70 —°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note: The Junction Temperatu r e (TJ) must not exceed the Absolute Maximum specifi c ation of +150°C.
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND,
VCM =V
DD/2, VOUT ≈VDD/2, VL = VDD/2, RL=10kΩ to VDD/2, CL= 60 pF and CS is tied low.
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —0.01— µACS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8VDD —V
DD V
CS Input Current, High ICSH —0.7 2 µACS = VDD
GND Current per Amplifier ISS — –0.7 — µA CS = VDD
Amplifier Output Leakage — — 0.01 — µA CS = VDD
Dynamic Specifications (Note 1)
CS Low to Va lid Amplifier
Output, Turn on Time tON —410µsCS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output
High-Z tOFF —0.01— µsCS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST —0.6— VV
DD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (VOUTB).
© 2008 Microchip Technology Inc. DS21810F-page 5
MCP6271/1R/2/3/4/5
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
VDD
MCP627X
RGRF
RNVOUT
VIN
VDD/2
1µF
CLRL
VL
0.1 µF
VDD
MCP627X
RGRF
RNVOUT
VDD/2
VIN
1µF
CLRL
VL
0.1 µF
MCP6271/1R/2/3/4/5
DS21810F-page 6 © 2008 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL=10kΩ to VL, CL= 60 pF and CS is tied low.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Bias Curren t at
TA=+85°C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage, with VDD =2.0V.
FIGURE 2-4: Input Offset Voltage Drift.
FIGURE 2-5: Input Bias Current at
TA= +125°C.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage, with VDD =5.5V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In so me graphs or tables, the data presented may be outside the specifie d
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-3.0
-2.4
-1.8
-1.2
-0.6
0.0
0.6
1.2
1.8
2.4
3.0
Input Offset Voltage (mV)
Percentage of Occ urrences
832 Samples
VCM = VSS
0%
4%
8%
12%
16%
20%
24%
28%
32%
0 102030405060708090100
Input Bias Current (pA)
Percentage of Occurrences
422 Samples
TA = 85°C
-100
-50
0
50
100
150
200
250
300
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.0V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0%
2%
4%
6%
8%
10%
12%
14%
-10
-8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
832 Samples
VCM = VSS
TA = -40°C to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Input Bias Current (nA)
Percentage of Occurrences
422 Samp les
TA = +125°C
-100
-50
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
© 2008 Microchip Technology Inc. DS21810F-page 7
MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL=10kΩ to VL, CL= 60 pF and CS is tied low.
FIGURE 2-7: Common Mode Input
Voltage Range Lower Limit vs. Temperature.
FIGURE 2-8: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-9: CMRR, PSRR vs.
Frequency.
FIGURE 2-10: Common Mode Input
Voltage Range Uppe r Lim it vs. Te m pera tu re .
FIGURE 2-11: Input Bias, Input Offset
Currents vs. Temperature.
FIGURE 2-12: CMRR, PSRR vs.
Temperature.
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Common Mode Input Voltage
Range Limit (V)
Typical lower (VCM – VSS) limit
VDD = 5.5V
VDD = 2.0V
-100
-50
0
50
100
150
200
250
300
0.00.51.01.52.02.53.03.54.04.55.05.5
Output Volt age ( V )
Input Offset Voltage (µV)
VDD = 2.0V
VCM = VSS
Representative Part
VDD = 5.5V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
1 10k 100k 1M10010 1k
PSRR–
PSRR+
CMRR
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
-50-250 255075100125
Ambient Te mp era t ure (°C)
Common Mode Input Voltage
Range Limit (V)
Typical upper (VCM – VDD) limit
VDD
= 5.5
V
VDD = 2.0V
1
10
100
1,000
10,000
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Of f set Curren t s
(pA)
Input Bias Current
VCM = VDD
VDD = 5.5V
Input Offset Current
60
70
80
90
100
110
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
(VCM = VSS)
CMRR
MCP6271/1R/2/3/4/5
DS21810F-page 8 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL=10kΩ to VL, CL= 60 pF and CS is tied low.
FIGURE 2-13: Input Bias, Offset Currents
vs. Common Mode Input Voltag e, with
TA=+85°C.
FIGURE 2-14: Quiescent Current vs.
Supply Voltage.
FIGURE 2-15: Open-Loop Gain, Pha se vs.
Frequency.
FIGURE 2-16: Input Bias, Offset Currents
vs. Common Mode Input Voltage, with
TA= +125°C.
FIGURE 2-17: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-18: Gain Bandwidth Product,
Phase Margin vs. Temperature.
-25
-15
-5
5
15
25
35
45
55
0.00.51.01.52.02.53.03.54.04.55.05.5
Common Mode Input Voltage (V)
Input Bias, Offs et Currents
(pA)
TA = 85°C
VDD = 5.5V
Input Bi as Cu r r e n t
Input Offset Current
0
50
100
150
200
250
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Quiescent Current
(µA/amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Gain
Phase
0.1
1 10 100 1k 10k 100k 1M10M 100M
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Of f set Curren t s
(nA)
TA = 125°C
VDD = 5.5V
Input Bias Current
Input Of f set Cu rrent
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Ouput Voltage Headroom
(mV)
VOL – VSS VDD – VOH
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
50
55
60
65
70
75
80
Phase Margin (°)
PM, VDD
= 5.5
V
VDD
= 2.0
V
GBWP, VDD
= 5.5
V
VDD
= 2.0
V
© 2008 Microchip Technology Inc. DS21810F-page 9
MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL=10kΩ to VL, CL= 60 pF and CS is tied low.
FIGURE 2-19: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-20: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-21: Output Short Circuit Cur rent
vs. Supply Voltage.
FIGURE 2-22: Slew Rate vs. Temperature.
FIGURE 2-23: Input Noise Voltage Density
vs. Common Mode Input Voltage, with f = 1 kHz.
FIGURE 2-24: Channel-to-Channel
Separation vs. Frequency (MCP6272 and
MCP6274).
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Maximum Output Voltage
Swing (VP-P)
VDD = 2.0V
1k 10k 100k 1M
VDD = 5.5V
10M
10
100
1,000
1.E-
01 1.E+
00 1.E+
01 1.E+
02 1.E+
03 1.E+
04 1.E+
05 1.E+
06Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
0.1 10010 1k 100k10k 1M1
0
5
10
15
20
25
30
35
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Ouptut Short-Circuit Current
(mA)
TA
= +125°C
TA
= +85°C
TA
= +25°C
TA
= -40°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling Edge VDD = 5.5V
VDD = 2.0V
Rising Edge
0
5
10
15
20
25
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/¥Hz)
f = 1 kHz
VDD = 5.0V
100
110
120
130
140
1 10 100
Frequency (kHz)
Channel-to-Channel
Separation (dB)
MCP6271/1R/2/3/4/5
DS21810F-page 10 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL=10kΩ to VL, CL= 60 pF and CS is tied low.
FIGURE 2-25: Quiescent Current vs. Chip
Select (CS) Volt age, with VDD = 2.0V (MCP6273
and MCP6275 only).
FIGURE 2-26: Large Signal Non-inverting
Pulse Response.
FIGURE 2-27: Small Signal Non-inverting
Pulse Response.
FIGURE 2-28: Quiescent Current vs. Chip
Select (CS) V olt age, with VDD = 5.5V (MCP6273
and MCP6275 only).
FIGURE 2-29: Large Signal Inverting Pulse
Response.
FIGURE 2-30: Small Signal Inverting Pulse
Response.
0
50
100
150
200
250
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Chip Select Voltage (V)
Quiescent Cu rre nt
(µA/amplifier)
Hysteresis
Op Amp turns Off
Op Amp turns On
VDD = 2.0V
CS swept
High-to-Low CS swept
Low-to-High
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 µs/div)
Output Voltage (V)
G = +1 V/V
VDD = 5.0V
Time (2 µs/div)
Output Vol t age (10 mV/div)
G = +1 V/V
0
100
200
300
400
500
600
700
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Quiescent Current
(µA/amplifier)
Hysteresis
Op Amp
turns
On/Off
CS swept
Low-to-High
CS swept
High-to-Low
VDD = 5.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (5 µs/div)
Output Vol t ag e (V)
G = -1 V/V
VDD = 5.0V
Time (2 µs/div)
Output Voltage (10 mV/div)
G = -1 V/V
© 2008 Microchip Technology Inc. DS21810F-page 11
MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA= +25°C, VDD = +2.0V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL = VDD/2, RL=10kΩ to VL, CL= 60 pF and CS is tied low.
FIGURE 2-31: Chip Select (CS) to
Amplifier Output Response Time, with
VDD = 2.0V (MC P 62 7 3 and M C P627 5 on ly) .
FIGURE 2-32: Input Current vs. Input
Voltage.
FIGURE 2-33: Chip Select (CS) to
Amplifier Output Response Time, with
VDD = 5,5V (MCP6273 and MCP6275 only).
FIGURE 2-34: The MCP6271/1R/2/3/4/5
Show no Phase Reversal.
0.0
0.5
1.0
1.5
2.0
2.5
Time (5 µs/div)
Chip Select, Output Voltages
(V)
VOUT Output On
Output High-Z
VDD = 2.0V
G = +1 V/V
VIN = VSS
CS
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Time (5 µs/div)
Chip Select, Output Voltages
(V)
VOUT
Output OnOutput High-Z
VDD = 5.5V
G = +1 V/V
VIN = VSS
CS
-1
0
1
2
3
4
5
6
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2 V/V
VIN
VOUT
MCP6271/1R/2/3/4/5
DS21810F-page 12 © 2008 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
Description s of the pi ns are listed in Table 3-1 (single op amps) and Table 3-2 (d ual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
3.1 Analog Outputs
The output pins are low impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high
impedance CMOS inputs with low bias currents.
3.3 MCP6275’s VOUTA/VINB+ Pin
For the MCP6275 only, the output of op amp A is
connected directly to the non-inverting input of op amp
B; this is the VOUTA/VINB+ pin. This co nnection makes
it possible to provide a CS pin for duals in 8-pin
packages.
3.4 Chip Select Digital Input
This is a CMOS, Schmitt triggered input that places the
part into a low power mode of operation.
3.5 Power Supply Pins
The positive power supply (VDD) is 2.0V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
MCP6271 MCP6271R MCP6273
Symbol Description
PDIP, SOIC,
MSOP SOT-23-5 SOT-23-5 PDIP, SOIC,
MSOP SOT-23-6
24424V
IN– Inverting Input
33333V
IN+ Non-inverting Input
42542V
SS Negative Power Supply
61161V
OUT Analog Output
75276V
DD Positive Power Supply
——— 8 5CS
Chip Select
1,5,8 — — 1,5 — NC No Internal Connection
MCP6272 MCP6274 MCP6275 Symbol Description
11—V
OUTA Analog Output (op amp A)
222V
INA– Inverting Input (op amp A)
333V
INA+ Non-inverting Input (op amp A)
848 V
DD Positive Power Supply
55—V
INB+ Non-inverting Input (op amp B)
666V
INB– Inverting Input (op amp B)
777V
OUTB Analog Output (op amp B)
—8—V
OUTC Analog Output (op amp C)
—9—V
INC– Inverting Input (op amp C)
—10— V
INC+ Non-inverting Input (op amp C)
4114 V
SS Negative Power Supply
—12— V
IND+ Non-inverting Input (op amp D)
—13— V
IND– Inverting Input (op amp D)
—14— V
OUTD Analog Output (op amp D)
—— 1V
OUTA /V
INB+ Analog Output (op amp A)/Non-inverting Input (op amp B)
—— 5 CS
Chip Select
© 2008 Microchip Technology Inc. DS21810F-page 13
MCP6271/1R/2/3/4/5
4.0 APPLICATION INFORMATION
The MCP6271/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low cost, low power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
make the MCP6271/1R/2/3/4/5 ideal for battery
powered applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-34 shows an input voltage
exceeding both supplies with no phase inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damag e and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute Maxi-
mum Ratings † at the beginning of Section 1.0 “Elec-
trical Characteristics”). Figure 4-2 shows the
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-32. Applications that are high impedance may
need to limit the usable voltage range.
4.1.3 NORMAL OPERATIONS
The input stage of the MCP6271/1R/2/3/4/5 op amps
uses two differential CMOS input stages in parallel.
One operates at low common mode input voltage (VCM
and the other at high VCM. With this topology, the input
operates with VCM up to 0.3V past either supply rail
(see Figure 2-7 and Figure 2-10). The input offset volt-
age (VOS) is measured at VCM =V
SS –0.3V and
VDD + 0.3V to ensure proper operation.
The transition between the two input stage occurs
when VCM ≈VDD –1.1V (see Figure 2-3 and Figure 2-
6). For the best distorti on and gain linearity, with non-
inverting gains, avoid this region of operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6271/1R/2/3/4/5
op amps is VDD – 15 mV (minimum) and VSS +15mV
(maximum) when RL=10kΩ is connected to VDD/2
and VDD = 5.5V. Refer to Figure 2-17 for more informa-
tion.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1
MCP627X
R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
VOUT
R2>VSS – (minimum expected V2)
2mA
V2R2
D2
R3
MCP6271/1R/2/3/4/5
DS21810F-page 14 © 2008 Microchip Technology Inc.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produce s gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-3: Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., –1 V/V gives GN= +2 V/V).
FIGURE 4-4: Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6271/1R/2/3/4/5 SPICE
macro model are helpful.
4.4 MCP6273/5 Chip Select
The MCP6273 and MCP6275 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typical)
and flows through the CS pin to VSS. When this
happens, the amplifier output is put into a high
impedance state. By pulling CS low, the amplifier is
enabled. The CS pin has an internal 5 MΩ (typical) pull-
down resistor connected to VSS, so it will g o low if the
CS pin is left floating. Figure 1-1 shows the output volt-
age and supply current response to a CS pulse.
4.5 Cascaded Dual Op Amps
(MCP6275)
The MCP6275 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard d ual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select in put, which can
be connected to a microcontroller I/O line, puts the
device in low power mode. Refer to Section 4.4
“MCP6273/5 Chip Select (CS)”.
FIGURE 4-5: Cascaded Gain Amplifier.
The output of op amp A is loaded by the input
impedance of op amp B, which is typically
1013Ω⎟⎟6 pF, as specified in the DC specification table
(Refer to Section 4.3 “Capacitive Loads” for further
details regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However , since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD –20mV.
VIN
RISO VOUT
CL
–
+MCP627X
10
100
1,000
10 100 1,000 10,000
Normalized Load Capacitance; CL / GN (pF)
Recommended RISO (:)
GN = 1 V/V
GN = 2 V/V
GNt 4 V/V
AB
CS
2
3
5
6
7
VINA+
VOUTB
MCP6275
1
VINA–
VOUTA/VINB+VINB–
© 2008 Microchip Technology Inc. DS21810F-page 15
MCP6271/1R/2/3/4/5
4.6 Unused Amplifiers
An unused op amp in a quad package (MCP6274)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R1 and R2 produce a voltage
within its output voltage range (VOH, VOL). The op amp
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
FIGURE 4-6: Unused Op Amps.
4.7 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supp ly) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high frequency perfo rmance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6271/1R/2/3/4/5 family’s bias current at 25°C
(1 pA, typical).
The easiest way to reduce surface leaka ge is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is illustrated in
Figure 4-7.
FIGURE 4-7: Example Guard Ring Layout
for Inverting Gain.
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detect ors):
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases th e guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pi n (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
¼ MCP6274 (A)
VDD
¼ MCP6274 (B)
R1
R2
VDD
VDD
VREF
VREF VDD R2
R1R2
+
------------------
⋅=
Guard Rin g
VSS
VIN–V
IN+
MCP6271/1R/2/3/4/5
DS21810F-page 16 © 2008 Microchip Technology Inc.
4.9 Application Circuits
4.9.1 ACTIVE FULL-WAVE RECTIFIER
The MCP6271/1R/2/3/4/5 family of amplifiers can be
used in applications such as an Active Full-Wave
Rectifier or an Absolute Value circuit, as shown in
Figure 4-8. The amplifier and feedback loops in this
active voltage rectifier circuit eliminate the diode drop
problem that exists in a passive voltage rectifier. This
circuit behaves as a follower (the output follows the
input) as long as the input signal is more positive than
the reference voltage. If the input signal is more
negative than the reference voltage, however, the
circuit behaves as an inverting amplifier . Therefore, the
output voltage will always be above the reference
voltage, regardless of the input signal.
FIGURE 4-8: Active Full-wave Rectifier.
The design equations give a gain of ±1 from VIN to
VOUT, and produce rail-to-rail outputs.
4.9.2 LOSSY NON-INVERTING
INTEGRATOR
The non-inverting integrator shown in Figure 4-9 is
easy to build. It saves one op amp over the typical
Miller integrator plus inverting amplifier configuration.
The phase accuracy of this integrator depends on the
matching of the input and feedback resistor-capacitor
time constants. RF makes this a lossy integrator (it has
finite gain at DC), and makes this integrator stable by
itself.
FIGURE 4-9: Non-Inverting Integrator.
–
+
–
+
VIN
VOUT
VREF
VREF
R1
R3R4
R5
R2
Op Amp A
Op Amp B
D1
D2
VREF VREF
time time
Input Output
R5R2R4
2R3
------------=
R1R2R3
==
1/2
MCP6272
1/2
MCP6272
R4R3
<1 VD1
VREF VSS
–
----------------------------
–
⎝⎠
⎛⎞
+
_
C1
C2
R1
R2
VIN VOUT
RF
VOUT
VIN
------------- 1
sR
1C1
()
-------------------- f1
2πR1C11RFR2
⁄+()
---------------------------------------------------
≈,≈
MCP6271
RFR2
≈
R1C1R2||RF
()C2
=
C2
© 2008 Microchip Technology Inc. DS21810F-page 17
MCP6271/1R/2/3/4/5
4.9.3 CASCADED OP AMP
APPLICATIONS
The MCP6275 provides the flexibility of Low power
mode for dual op amps in an 8-pin package. The
MCP6275 eliminates the added cost and space in a
battery powered application by using two single op
amps with Chip Select (CS) lines or a 10-pin device
with one CS line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there a re severa l
applications where this op amp configuration with a CS
line becomes suitable. The circuits below show
possible applications for this device.
4.9.3.1 Load Isolat ion
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In
applications where op amp A is driving capacitive or
low resistive loads in the feedback loop (such as an
integrator or filter circuit) the op amp may not have
sufficient source current to drive the load. In this case,
op amp B can be used as a buffer.
FIGURE 4-10: Isolating the Load with a
Buffer.
4.9.3.2 Cascaded Gain
Figure 4-11 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of op amp
A and B, as shown below:
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain (e.g., a unity gain buffer).
FIGURE 4-11: Cascaded Gain Circuit
Configuration.
4.9.3.3 Difference Amplifier
Figure 4-12 shows op amp A configured as a difference
amplifier with Chip Select. In this configuration, it is
recommended that well matched resistors (e.g., 0.1%)
be used to increase the Common Mode Rejection Ratio
(CMRR). Op amp B can be u sed to provide ad ditional
gain and isolate the load from the difference amplifier.
FIGURE 4-12: Difference Amplifier Circ uit.
4.9.3.4 Inverting Integrator with Active
Compensation and Chip Select
Figure 4-13 uses an active compensator (op amp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity gain buffer to isolate the
integration capacitor C1 from op amp A and d rives the
capacitor with a low impedance source. Since both op
amps are matched very well, they provide a high quality
integrator.
FIGURE 4-13: Integrator Circuit with Active
Compensation.
A
CS
VOUTB
MCP6275
B
Load
VOUT VINGAGBVOSAGAGBVOSBGB
++=
Where:
GA= op amp A gain
GB= op amp B gain
VOSA = op amp A input offset voltage
VOSB = op amp B input offset voltage
A
CS
R4R3R2R1
VIN
VOUT
MCP6275
B
A
CS
R2R1R4R3
VOUT
MCP6275
VIN2
B
R2
R1
VIN1
A
CS
R1C1
VOUT
MCP6275
VIN B
MCP6271/1R/2/3/4/5
DS21810F-page 18 © 2008 Microchip Technology Inc.
4.9.3.5 Second Order MFB with an Extra
Pole-Zero Pair
Figure 4-14 is a second order multiple feedback low-
pass filter with Chip Select. Use the FilterLab® software
from Microchip Technology Inc. to determine the R and
C values for op amp A’s second order filter. Op amp B
can be used to add a pole-zero pair using C3, R 6 and
R7.
FIGURE 4-14: Second Order Multiple
Feedback Low-Pass Filter with an Extra Pole-
Zero Pair.
4.9.3.6 Second Order Sallen-Key with an
Extra Pole-Zero Pair
Figure 4-15 is a second order Sallen-Key low-pass
filter with Chip Select. Use the Filterlab® software from
Microchip to determine the R and C values for
op amp A’s second order filter. Op amp B can be used
to add a pole-zero pair using C3, R5 and R6.
FIGURE 4-15: Second Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
4.9.3.7 Capacitorless Second Order
Low-Pass filter with Chip Select
The low-pass filter shown in Figure 4-16 does not
require external capacitors and uses only three
external resistors; the op amp’s GBWP sets the corner
frequency . R1 and R2 are used to set the circuit gain. R3
is used to set the Q. To avoid gain peaking in the
frequency response, Q needs to be low (lower values
need to be selected for R3). Note that the amplifier
bandwidth varies greatly over temperature and
process. This configuration, however, provides a low
cost solution for applications with high bandwidth
requirements.
FIGURE 4-16: Capacitorless Second Order
Low-Pass Filter with Chip Select.
A
CS
R1
R6C3
VOUT
MCP6275
B
R5
R4
VDD
R7
C1
R3R2
VIN
A
CS
R5C3
VOUT
MCP6275
B
R6
R4R3
VIN
R2R1
C1
C2
A
CS
R3
R2
VOUT
MCP6275
B
VREF
R1
VIN
© 2008 Microchip Technology Inc. DS21810F-page 19
MCP6271/1R/2/3/4/5
5.0 DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6271/1R/2/3/4/5 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP6271/1R/2/
3/4/5 op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filte rlab, the
FilterLab d esign tool provides fu ll schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, whic h can be
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
5.4 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
•P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
•P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
ation Board
5.6 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended a s supplemental ref-
erence resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MCP6271/1R/2/3/4/5
DS21810F-page 20 © 2008 Microchip Technology Inc.
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
8-Lead MSOP Example:
XXXXXX
YWWNNN
6271E
644256
5-Lead SOT-23 (MCP6271 and MCP6271R)Example:
XXNN CG25
Device Code
MCP6271 CGNN
MCP6271R ETNN
Note: Applies to 5-Lead SOT-23
6-Lead SOT-23 (MCP6273)Example:
XXNN CK25
MCP6271
E/P^^256
0644
MCP6271
E/P256
0437
OR
MCP6271
E/SN0437
256
MCP6271E
SN^^0644
256
OR
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
© 2008 Microchip Technology Inc. DS21810F-page 21
MCP6271/1R/2/3/4/5
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6274) Example:
14-Lead TSSOP (MCP6274) Example:
14-Lead SOIC (150 mil) (MCP6274) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6274-E/P
0437256
6274EST
0437
256
XXXXXXXXXX MCP6274ESL
0437256
MCP6274
0644256
MCP6274
0644256
OR
E/P^^
OR
E/SL^^
3
e
3
e
MCP6271/1R/2/3/4/5
DS21810F-page 22 © 2008 Microchip Technology Inc.
/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU27>627@
1RWHV
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
/HDG3LWFK H %6&
2XWVLGH/HDG3LWFK H %6&
2YHUDOO+HLJKW $ ±
0ROGHG3DFNDJH7KLFNQHVV $ ±
6WDQGRII $ ±
2YHUDOO:LGWK ( ±
0ROGHG3DFNDJH:LGWK ( ±
2YHUDOO/HQJWK ' ±
)RRW/HQJWK / ±
)RRWSULQW / ±
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc. DS21810F-page 23
MCP6271/1R/2/3/4/5
/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU&+>627@
1RWHV
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2XWVLGH/HDG3LWFK H %6&
2YHUDOO+HLJKW $ ±
0ROGHG3DFNDJH7KLFNQHVV $ ±
6WDQGRII $ ±
2YHUDOO:LGWK ( ±
0ROGHG3DFNDJH:LGWK ( ±
2YHUDOO/HQJWK ' ±
)RRW/HQJWK / ±
)RRWSULQW / ±
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
b
E
4
N
E1
PIN1IDBY
LASER MARK
D
123
e
e1
A
A1
A2 c
L
L1
φ
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
MCP6271/1R/2/3/4/5
DS21810F-page 24 © 2008 Microchip Technology Inc.
/HDG3ODVWLF0LFUR6PDOO2XWOLQH3DFNDJH06>0623@
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK ( %6&
2YHUDOO/HQJWK ' %6&
)RRW/HQJWK /
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2
c
L1 L
φ
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc. DS21810F-page 25
MCP6271/1R/2/3/4/5
/HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV ,1&+(6
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
7RSWR6HDWLQJ3ODQH $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
%DVHWR6HDWLQJ3ODQH $ ± ±
6KRXOGHUWR6KRXOGHU:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
7LSWR6HDWLQJ3ODQH /
/HDG7KLFNQHVV F
8SSHU/HDG:LGWK E
/RZHU/HDG:LGWK E
2YHUDOO5RZ6SDFLQJ H% ± ±
N
E1
NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
MCP6271/1R/2/3/4/5
DS21810F-page 26 © 2008 Microchip Technology Inc.
/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $ ± ±
6WDQGRII
$ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK ( %6&
2YHUDOO/HQJWK ' %6&
&KDPIHURSWLRQDO K ±
)RRW/HQJWK / ±
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
0ROG'UDIW$QJOH7RS ±
0ROG'UDIW$QJOH%RWWRP ±
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc. DS21810F-page 27
MCP6271/1R/2/3/4/5
/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
MCP6271/1R/2/3/4/5
DS21810F-page 28 © 2008 Microchip Technology Inc.
/HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV ,1&+(6
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
7RSWR6HDWLQJ3ODQH $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
%DVHWR6HDWLQJ3ODQH $ ± ±
6KRXOGHUWR6KRXOGHU:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
7LSWR6HDWLQJ3ODQH /
/HDG7KLFNQHVV F
8SSHU/HDG:LGWK E
/RZHU/HDG:LGWK E
2YHUDOO5RZ6SDFLQJ H% ± ±
N
E1
D
NOTE 1
123
E
c
eB
A2
L
A
A1
b1
be
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc. DS21810F-page 29
MCP6271/1R/2/3/4/5
/HDG3ODVWLF6PDOO2XWOLQH6/±1DUURZPP%RG\>62,&@
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $ ± ±
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK ( %6&
2YHUDOO/HQJWK ' %6&
&KDPIHURSWLRQDO K ±
)RRW/HQJWK / ±
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
0ROG'UDIW$QJOH7RS ±
0ROG'UDIW$QJOH%RWWRP ±
NOTE 1
N
D
E
E1
123
b
e
A
A1
A2
L
L1
c
h
hα
β
φ
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
MCP6271/1R/2/3/4/5
DS21810F-page 30 © 2008 Microchip Technology Inc.
/HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH67±PP%RG\>76623@
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK (
0ROGHG3DFNDJH/HQJWK '
)RRW/HQJWK /
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
NOTE 1
D
N
E
E1
12
e
b
c
A
A1
A2
L1 L
φ
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
© 2008 Microchip Technology Inc. DS21810F-page 31
MCP6271/1R/2/3/4/5
APPENDIX A: REVISION HISTORY
Revision F (March 2008)
The following is the list of modificatio ns:
1. Increased maximum operating V DD.
2. Updated Section 5.0 “Design Tools”
3. Va rious cleanups thoughout document.
4. Updated package outline drawings in
Section 6.0 “Packaging Information”
Revision E (December 2006)
The following is the list of modificatio ns:
1. Updated specifications (Section 1.0 “Electrical
Characteristics”):
a) Clarified Absolute Maximum Analog Input
Voltage and Current specifications.
b) Clarified VCMR, VOL, VOH, and PM
specifications.
c) Corrected the typical Eni.
2. Added plots on Common Mode Input Range
behavior vs. temperature and supply voltage
(Section 2.0 “Typical Performance Curves”).
3. Added applications writeup on unused op amps
and corrected description of floating CS pin
behavior (Section 4.0 “Application Informa-
tion”).
4. Updated package information (Section 6.0
“Packaging Information”):
a) Corrected package markings.
b) Added disclaimer to package outline
drawings.
Revision D (December 2004)
The following is the list of modificatio ns:
1. Added SOT-23-5 packages for the MCP6271
and MCP6271R single op amps.
2. Added SOT-23-6 packages for the MCP6273
single op amp.
3. Added Section 3.0 “Pin Descriptions”.
4. Corrected application circuits
(Section 4.9 “Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected package marking information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: Revision History.
Revision C (June 2004)
• Undocumented Changes
Revision B (October 2003)
• Undocumented Changes
Revision A (June 2003)
• Original data sheet release.
MCP6271/1R/2/3/4/5
DS21810F-page 32 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21810F-page 33
MCP6271/1R/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6271: Single Op Amp
MCP6271T: Single Op Amp
(Tape and Reel)
(SOIC, MSOP, SOT-23-5)
MCP6271RT: Single Op Amp
(Tape and Reel) (SOT-23-5)
MCP6272: Dual Op Amp
MCP6272T: Dual Op Amp
(Tape and Reel) (SOIC, MSOP)
MCP6273: Single Op Amp with Chip Select
MCP6273T: Single Op Amp with Chip Select
(Tape and Reel)
(SOIC, MSOP, SOT-23-6)
MCP6274: Quad Op Amp
MCP6274T: Quad Op Amp
(Tape and Reel) (SOIC, TSSOP)
MCP6275: Dual Op Amp with Chip Select
MCP6275T: Dual Op Amp with Chip Select
(Tape and Reel) (SOIC, MSOP)
Temperature Range: E = -40°C to +125°C
Package: OT = Plastic Small Outline Transist or (SOT -23), 5-lead
(MCP6271, MCP6271R)
CH = Plastic Small Outline Transist or (SOT -23), 6-lead
(MCP6273)
MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lea d, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4 mm Body), 14-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6271-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6271-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6271-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6271T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
a) MCP6271RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
a) MCP6272-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6272-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6272-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6272T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
a) MCP6273-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6273-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6273-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6273T-E/CH: Extended Temperature,
6LD SOT-23 package.
a) MCP6274-E/P: Extended Temperature,
14LD PDIP package.
b) MCP6274T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC package.
c) MCP6274-E/SL: Extended Temperature,
14LD SOIC package.
d) MCP6274-E/ST: Extended Temperature,
14LD TSSOP package.
a) MCP6275-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6275-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6275-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6275T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
–
MCP6271/1R/2/3/4/5
DS21810F-page 34 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21810F-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICST ART, PRO MA TE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21810F-page 36 © 2008 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
01/02/08
