Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Product Features * * * * * * * * * * Available at 2, 2.40, 2.66, 2.80, and 3.06 GHz Dual processing server/workstation support Binary compatible with applications running on previous members of Intel's IA32 microprocessor line Intel(R) NetBurstTM micro-architecture Hyper-Threading Technology -- Hardware support for multithreaded applications 533 MHz Front Side Bus -- Bandwidth up to 4.3 GB/second Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency Hyper Pipelined Technology Advance Dynamic Execution -- Very deep out-of-order execution -- Enhanced branch prediction Level 1 Execution Trace Cache stores 12 K micro-ops and removes decoder latency from main execution loops -- Includes 8 KB Level 1 data cache * * * * * * 512 KB Advanced Transfer L2 Cache (on-die, full speed Level 2 cache) with 8-way associativity and Error Correcting Code (ECC) Enables system support of up to 64 GB of physical memory Streaming SIMD Extensions 2 (SSE2) -- 144 new instructions for double-precision floating point operations, media/video streaming, and secure transactions Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities -- System Management mode -- Multiple low-power states Advanced System Management Features -- Thermal Monitor -- Machine Check Architecture (MCA) The Intel(R) XeonTM Processor with 533 MHz Front Side Bus is designed for high-performance dual-processor workstation and server applications. Based on the Intel(R) NetBurstTM microarchitecture and the new Hyper-Threading Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The Intel Xeon processor with 533 MHz Front Side Bus is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP*, Windows* 2000, Linux*, and UNIX*. The Intel Xeon processor with 533 MHz Front Side Bus delivers compute power at unparalleled value and flexibility for powerful workstations, internet infrastructure, and departmental server applications. The Intel(R) NetBurstTM microarchitecture and Hyper-Threading Technology deliver outstanding performance and headroom for peak internet server workloads, resulting in faster response times, support for more users, and improved scalability. Document Number: 252135-003 March 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. *Other names and brands may be claimed as the property of others. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) XeonTM processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.MPEG is an international standard for video compression/ decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademark or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Copyright (c) Intel Corporation, 2002-2003 2 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Contents 1.0 Introduction......................................................................................................................... 7 1.1 1.2 1.3 2.0 Electrical Specifications.................................................................................................... 11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3.0 4.2 Processor Pin Assignments ................................................................................ 41 4.1.1 Pin Listing by Pin Name ......................................................................... 41 4.1.2 Pin Listing by Pin Number ...................................................................... 50 Signal Definitions................................................................................................. 60 Thermal Specifications ..................................................................................................... 69 5.1 5.2 6.0 Mechanical Specifications ................................................................................... 30 Processor Package Load Specifications ............................................................. 35 Insertion Specifications ....................................................................................... 36 Mass Specifications............................................................................................. 36 Materials.............................................................................................................. 36 Markings.............................................................................................................. 37 Pin-Out Diagram.................................................................................................. 38 Pin Listing and Signal Definitions ..................................................................................... 41 4.1 5.0 Front Side Bus and GTLREF .............................................................................. 11 Power and Ground Pins ...................................................................................... 11 Decoupling Guidelines ........................................................................................ 11 2.3.1 VCC Decoupling ..................................................................................... 12 2.3.2 Front Side Bus AGTL+ Decoupling ........................................................ 12 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking................................ 12 2.4.1 Bus Clock ............................................................................................... 13 PLL Filter ............................................................................................................. 13 2.5.1 Mixing Processors .................................................................................. 15 Voltage Identification .......................................................................................... 15 2.6.1 Mixing Processors of Different Voltages ................................................ 16 Reserved Or Unused Pins................................................................................... 17 Front Side Bus Signal Groups............................................................................. 17 Asynchronous GTL+ Signals............................................................................... 19 Maximum Ratings................................................................................................ 19 Processor DC Specifications............................................................................... 19 AGTL+ Front Side Bus Specifications ................................................................. 26 Mechanical Specifications ................................................................................................ 29 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4.0 Terminology........................................................................................................... 8 1.1.1 Processor Packaging Terminology........................................................... 8 State of Data ......................................................................................................... 9 References .......................................................................................................... 10 Thermal Specifications ........................................................................................ 70 Measurements for Thermal Specifications ......................................................... 72 5.2.1 Processor Case Temperature Measurement ......................................... 72 Features ........................................................................................................................... 73 6.1 6.2 Power-On Configuration Options ........................................................................ 73 Clock Control and Low Power States.................................................................. 73 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 3 6.3 7.0 Boxed Processor Specifications....................................................................................... 79 7.1 7.2 7.3 7.4 8.0 6.2.1 Normal State--State 1 ........................................................................... 73 6.2.2 AutoHALT Powerdown State--State 2 .................................................. 74 6.2.3 Stop-Grant State--State 3 ..................................................................... 74 6.2.4 HALT/Grant Snoop State--State 4 ........................................................ 75 6.2.5 Sleep State--State 5.............................................................................. 75 6.2.6 Bus Response During Low Power States .............................................. 76 Thermal Monitor .................................................................................................. 76 6.3.1 Thermal Diode........................................................................................ 77 Introduction ......................................................................................................... 79 Mechanical Specifications................................................................................... 80 7.2.1 Boxed Processor Heatsink Dimensions ................................................. 80 7.2.2 Boxed Processor Heatsink Weight......................................................... 80 7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports........... 80 Boxed Processor Requirements ......................................................................... 84 7.3.1 Intel(R) XeonTM Processor with 533 MHz Front Side Bus ........................ 84 7.3.2 1U Rack Mount Server Solution ............................................................. 88 Thermal Specifications........................................................................................ 90 7.4.1 Boxed Processor Cooling Requirements ............................................... 90 Debug Tools Specifications.............................................................................................. 91 8.1 Logic Analyzer Interface (LAI)............................................................................. 91 8.1.1 Mechanical Considerations .................................................................... 91 8.1.2 Electrical Considerations........................................................................ 91 1 2 3 Typical VCCIOPLL, VCCA and VSSA Power Distribution .................................. 14 Phase Lock Loop (PLL) Filter Requirements ...................................................... 14 Intel(R) XeonTM processor with 533 MHz Front Side Bus VoltageCurrent Projections (VID 1.5V)............................................................................ 22 Intel Xeon processor with 533 MHz Front Side Bus Voltage-Current Projections (VID 1.525V)..................................................................................... 23 Electrical Test Circuit .......................................................................................... 27 THERMTRIP# to VCC Timing ............................................................................. 27 FC-mPGA2 Processor Package Assembly Drawing........................................... 29 FC-mPGA Processor Package Top View: Component Placement Detail........... 30 Intel(R) XeonTM Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package Drawing ............................................................................ 31 FC-mPGA2 Processor Package Top View: Component Height Keep-in ............ 32 FC-mPGA2 Processor Package Cross Section View: Pin Side Component Keep-in ............................................................................................ 33 FC-mPGA2 Processor Package: Pin Detail ........................................................ 34 IHS Flatness and Tilt Drawing............................................................................. 35 Processor Top-Side Markings ............................................................................. 37 Processor Bottom-Side Markings........................................................................ 37 Processor Pin Out Diagram: Top View ............................................................... 38 Processor Pin Out Diagram: Bottom View .......................................................... 39 Processor with Thermal and Mechanical Components - Exploded View ............ 69 Processor Thermal Design Power vs Electrical Projections for VID = 1.500V... 70 Figures 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 20 21 22 23 24 25 26 27 28 29 30 31 Processor Thermal Design Power vs Electrical Projections for VID = 1.525V .... 71 Thermal Measurement Point for Processor TCASE............................................ 72 Stop Clock State Machine ................................................................................... 74 Mechanical Representation of the Boxed Processor Passive Heatsink.............. 79 Boxed Processor Retention Mechanism and Clip ............................................... 81 Boxed Processor Retention Mechanism that Ships with the Processor.............. 82 Multiple View Space Requirements for the Boxed Processor ............................. 83 Fan Connector Electrical Pin Sequence............................................................. 85 Processor Wind Tunnel General Dimensions ..................................................... 86 Processor Wind Tunnel Detailed Dimensions ..................................................... 87 Exploded View of the 1U Thermal Solution......................................................... 88 Assembled View of the 1U Thermal Solution ...................................................... 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Front Side Bus-to-Core Frequency Ratio ............................................................ 13 Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0].................... 13 Voltage Identification Definition ........................................................................... 16 Front Side Bus Signal Groups............................................................................. 18 Processor Absolute Maximum Ratings ............................................................... 19 Voltage and Current Specifications ..................................................................... 21 Front Side Bus Differential BCLK Specifications................................................. 23 AGTL+ Signal Group DC Specifications ............................................................. 24 TAP and PWRGOOD Signal Group DC Specifications....................................... 24 Asynchronous GTL+ Signal Group DC Specifications ........................................ 25 BSEL[1:0] and VID[4:0] DC Specifications.......................................................... 25 AGTL+ Bus Voltage Definitions........................................................................... 26 Miscellaneous Signals + Specifications .............................................................. 27 Dimensions for the Intel(R) XeonTM Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package.................................................................. 32 Package Dynamic and Static Load Specifications .............................................. 35 Processor Mass................................................................................................... 36 Processor Material Properties ............................................................................. 36 Pin Listing by Pin Name ...................................................................................... 41 Pin Listing by Pin Number ................................................................................... 50 Signal Definitions................................................................................................. 60 Processor Thermal Design Power....................................................................... 70 Power-On Configuration Option Pins .................................................................. 73 Thermal Diode Parameters ................................................................................. 77 Thermal Diode Interface...................................................................................... 78 Fan Cable Connector Requirements................................................................... 85 Fan Power and Signal Specifications.................................................................. 85 Tables 15 16 17 38 39 41 42 43 44 45 46 47 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 5 Revision History 6 Date of Release Revision No. November 2002 -001 Initial Release February 2003 -002 Added 3.06 GHz information. Edited definitions with current terminology. Added two TDP loadline figures in chapter 6. Edited figures 18 and 19. Added notes to signal definition tables for symmetric agents. Edited Chapter 8.0 Boxed Processor Specifications. March 2003 -003 Deleted Chapter 3 and Removed Section 2.13, 2.14 Added Table 13 Description Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 1.0 Introduction The Intel(R) XeonTM Processor with 533 MHz Front Side Bus is based on the Intel(R) NetBurstTM micro-architecture, which operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA-32 processors. While based on the Intel NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32 software. The Intel NetBurst micro-architecture features begin with innovative techniques that enhance processor execution such as Hyper Pipelined Technology, a Rapid Execution Engine, Advanced Dynamic Execution, enhanced Floating Point and Multimedia unit, and Streaming SIMD Extensions 2 (SSE2). The Hyper Pipelined Technology doubles the pipeline depth in the processor, allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in one half of the internal core clock period. The Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units have been improved by making the registers 128 bits wide and adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for doubleprecision floating point, SIMD integer, and memory management for improvements in video/ multimedia processing, secure transactions, and visual internet applications. Also part of the Intel NetBurst micro-architecture, the front side bus and caches on the Intel Xeon processor with 533 MHz Front Side Bus provide tremendous throughput for server and workstation workloads. The 533 MHz Front Side Bus provides a high-bandwidth pipeline to the system memory and I/O. It is a quad-pumped bus running off a 133 MHz Front Side Bus clock making 4.3 Gigabytes per second (4,300 Megabytes per second) data transfer rates possible. The Execution Trace Cache is a level 1 cache that stores approximately twelve thousand decoded microoperations, which removes the decoder latency from the main execution path and increases performance. The Advanced Transfer Cache is a 512 KB on-die level 2 cache running at the speed of the processor core providing increased bandwidth over previous micro-architectures. In addition to the Intel NetBurst micro-architecture, the Intel Xeon processor with 533 MHz Front Side Bus includes a groundbreaking new technology called Hyper-Threading technology, which enables multi-threaded software to execute tasks in parallel within the processor resulting in a more efficient, simultaneous use of processor resources. Server applications can realize increased performance from Hyper-Threading technology today, while workstation applications are expected to benefit from Hyper-Threading technology in the future through software and processor evolution. The combination of Intel NetBurst micro-architecture and Hyper-Threading technology delivers outstanding performance, throughput, and headroom for peak software workloads resulting in faster response times and improved scalability. The Intel Xeon processor with 533 MHz Front Side Bus is intended for high performance workstation and server systems with up to two processors on a single bus. The processor supports both uniand dual-processor designs. The Intel Xeon with 533 MHz Front Side Bus processors do not incorporate system managment devices (PIROM, OEM Scratchpad EEPROM, and thermal sensor), but offer direct access to the pins of an on-die thermal diode. These output pins can interface with a thermal sensor device that is placed on the baseboard. The Intel Xeon processor with 533 MHz Front Side Bus is packaged in a 604-pin flip chip micro-PGA2 (FC-mPGA2) package, and utilizes a surface mount ZIF socket with 604 pins. The FC-mPGA2 package contains an extra pin (located at location AE30) compared to the INTmPGA package. This additional pin serves as a keying mechanism to prevent the FC-mPGA2 package from being installed in the 603-pin socket since processors in the FC-mPGA2 package are Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 7 only supported in the 604-pin socket. Since the additional contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this location. Mechanical components used for attaching thermal solutions to the baseboard should have a high degree of commonality with the thermal solution components enabled for the Intel Xeon processor Heatsinks and retention mechanisms have been designed with manufacturability as a high priority. Hence, mechanical assembly can be completed from the top of the baseboard. The Intel Xeon processor with 533 MHz Front Side Bus uses a scalable front side bus protocol referred to as the "Front Side Bus" in this document. The processor front side bus utilizes a splittransaction, deferred reply protocol similar to that introduced by the Pentium(R) Pro processor Front Side Bus, but is not compatible with the Pentium Pro processor front side bus. The Intel Xeon processor with 533 MHz Front Side Bus is compatible with the Intel Xeon processor Front Side Bus. The front side bus uses Source-Synchronous Transfer (SST) of address and data to improve performance, and transfers data four times per bus clock (4X data transfer rate). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a `double-clocked' or 2X address bus. In addition, the Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 4.3 Gigabytes per second. Finally, the front side bus also introduces transactions that are used to deliver interrupts. Signals on the front side bus use Assisted GTL+ (AGTL+) level voltages which are fully described in the appropriate platform design guide (refer to Section 1.3). 1.1 Terminology A `#' symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the `#' symbol implies that the signal is inverted. For example, D[3:0] = `HLHL' refers to a hex `A', and D[3:0]# = `LHLH' also refers to a hex `A' (H= High logic level, L= Low logic level). Front Side Bus (FSB): The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: * 604-pin socket - The 604-pin socket contains an additional contact to accept the additional keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The 604-pin socket will also accept processors with the INT-mPGA package. Since the additional contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this location. Therefore, the additional keying pin will not require a baseboard via nor a surfacemount pad. See the mPGA604 Socket Design Guidelines for details regarding this socket. * Central Agent - The central agent is the host bridge to the processor and is typically known as the chipset. 8 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz * Flip Chip Ball Grid Array (FC-BGA) - Microprocessor packaging using "flip chip" design, where the processor is attached to the substrate face-down for better signal integrity, more efficient heat removal and lower inductance. * FC-mPGA2 - Packaging technology with the processor die mounted directly to a micro-Pin Grid Array substrate with an integrated heat spreader (IHS). * Front Side Bus - Front Side Bus (FSB) is the electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. * Intel(R) XeonTM processor with 512 KB L2 cache - The entire processor in its INT-mPGA package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and interposer. * Intel(R) XeonTM processor with 533 MHz Front Side Bus - The entire processor in its FCmPGA2 package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and interposer. * Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal solution to the processor. * Interposer - The structure on which the processor core package and I/O pins are mounted. * OEM - Original Equipment Manufacturer. * Processor core - The processor's execution engine. All AC timing and signal integrity specifications are to the pads of the processor core. * Retention mechanism - The support components that are mounted through the baseboard to the chassis to provide mechanical retention for the processor and heatsink assembly. * Symmetric Agent - A symmetric agent is a processor which shares the same I/O subsystem and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems. Intel(R) XeonTM (DP - Dual Processor) processors should only be used in SMP systems which have two or fewer symmetric agents. 1.2 State of Data The data contained in this document is subject to change. It is the best information that Intel is able to provide at the publication date of this document. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 9 1.3 References The reader of this specification should also be familiar with material and concepts presented in the following documents:. Intel Order Number1 Document AP-485, Intel(R) Processor Identification and the CPUID Instruction 241618 IA-32 Intel (R) Architecture Software Developer's Manual * Volume I: Basic Architecture 245470 * Volume II: Instruction Set Reference 245471 * Volume III: System Programming Guide TM 245472 (R) Intel (R) Xeon Processor with 512-KB L2 Cache and Intel E7505 Chipset Platform Design Guide http://developer.intel.com Intel(R) XeonTM Processor Thermal Design Guidelines 298348 603 -Pin Socket Design Guidelines 249672 mPGA604 Socket Design Guidelines 11299 Intel(R) XeonTM Processor Specification Update 249678 CK00 Clock Synthesizer/Driver Design Guidelines 249206 VRM 9.0 DC-DC Converter Design Guidelines 249205 VRM 9.1 DC-DC Converter Design Guidelines 298646 Dual Intel(R) Xeon Guidelines TM Processor Voltage Regulator Down (VRD) Design ITP700 Debug Port Design Guide 298644 249679 Intel(R) XeonTM Processor with 533 MHz Front Side Bus System Compatibility Guidelines Intel(R) XeonTM Processor with 533 MHz Front Side Bus Signal Integrity Models http://developer.intel.com Intel(R) XeonTM Processor with 533 MHz Front Side Bus Mechanical Models in ProE* Format http://developer.intel.com IIntel(R) XeonTM Processor with 533 MHz Front Side Bus Mechanical Models in IGES* Format http://developer.intel.com Intel(R) XeonTM Processor with 512-KB L2 Cache Front Side Bus Thermal Models (FloTherm* and ICEPAK* format) http://developer.intel.com Intel(R) XeonTM Processor with 533 MHz Front Side Bus Core Boundary Scan Descriptor Language (BSDL) Model http://developer.intel.com Wired for Management 2.0 Design Guide http://developer.intel.com Boxed Integration Notes http://support.intel.com/ support/processors/xeon NOTES: 1. Contact your Intel representative for the latest revision of documents without order numbers. 10 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 2.0 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Intel(R) XeonTM Processor with 533MHz Front Side Bus signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. The processor termination voltage level is VCC, the operating voltage of the processor core. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the processor front side bus. Because of the speed improvements to data and address busses, signal integrity and platform design methods become more critical than with previous processor families. Front side bus design guidelines are detailed in the appropriate platform design guide (refer to Section 1.3). The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See Table 12 for GTLREF specifications). Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination can be enabled to control reflections on the transmission line. For middle bus agents, on-die termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for details on ODTEN resistor termination requirements. Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard. See Table 4 for details regarding these signals. The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the front side bus, including trace lengths, is highly recommended when designing a system. Please refer to http://developer.intel.com to obtain the Intel(R) XeonTM Processor with 533 MHZ Front Side Bus Signal Integrity Models. 2.2 Power and Ground Pins For clean on-chip power distribution, the Intel Xeon processor with 533 MHz Front Side Bus has 190 VCC (power) and 189 VSS (ground) inputs. All VCC pins must be connected to the system power plane, while all VSS pins must be connected to the system ground plane. The processor VCC pins must be supplied the voltage determined by the processor VID (Voltage ID) pins. 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 11 Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines. 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM pins) to the 604-pin socket. Bulk decoupling may be provided on the voltage regulation module (VRM) to meet help meet the large current swing requirements. The remaining decoupling is provided on the baseboard. The power delivery path must be capable of delivering enough current while maintaining the required tolerances (defined in Table 6). For further information regarding power delivery, decoupling, and layout guidelines, refer to the appropriate platform design guidelines. 2.3.2 Front Side Bus AGTL+ Decoupling The Intel(R) XeonTM processor with 533MHz Front Side Bus integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines. 2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The maximum processor bus ratio multiplier will be set during manufacturing. The default setting will equal the maximum speed for the processor. The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. Clock multiplying within the processor is provided by the internal PLL, which requires a constant frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are provided in Table 7 and Table 13, respectively. These specifications must be met while also meeting signal integrity requirements as outlined in Chapter 3.0. The processor utilizes a differential clock. Details regarding BCLK[1:0] driver specifications are provided in the CK408 Clock Synthesizer/Driver Design Guidelines.. Table 1 contains the supported bus fraction ratios and their corresponding core frequencies. 12 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Intel(R) XeonTM Processor with 533 MHz Front Side Bus Table 1. Front Side Bus-to-Core Frequency Ratio Front Side Bus-to-Core Frequency Ratio 2.4.1 Core Frequency 1/15 2 GHz 1/18 2.40 GHz 1/20 2.66 GHz 1/21 2.80 GHz 1/23 3.06 GHz Bus Clock The front side bus frequency is set to the maximum supported by the individual processor. BSEL[1:0] are outputs used to select the front side bus frequency. Table 2 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. All front side bus agents must operate at the same frequency. Individual processors will only operate at their specified front side bus clock frequency, (100 MHz for present generation processors). The Intel(R) Xeon TM processor with a 533 MHz Front Side Bus is designed to run on a baseboard with a 133 MHz bus clock.. On these baseboards, BSEL[0:1] are considered `reserved' at the processor socket. . Table 2. Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0] BSEL1 2.5 BSEL0 Bus Clock Frequency L L 100 MHz L H 133 MHz H L Reserved H H Reserved PLL Filter VCCA and VCCIOPLL are power sources required by the processor PLL clock generator. This requirement is identical to that of the Intel Xeon processor with 512-KB L2 cache. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown in Figure 1. The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 1), is as follows: * * * * Datasheet < 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements) > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency 13 The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter refer to the appropriate platform design guidelines. Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution Trace < 0.02 VCC Processor interposer "pin" L1/L2 R-Socket R-Trace VCCA PLL C Baseboard via that connects filter to VCC plane Socket pin R-Socket Processor VSSA C R-Socket R-Trace VCCIOPLL L1/L2 Figure 2. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB -0.5 dB forbidden zone -28 dB forbidden zone -34 dB DC passband 14 1 Hz fpeak 1 MHz 66 MHz fcore high frequency band Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz NOTES: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 2.5.1 Mixing Processors Intel only supports those processor combinations operating with the same front side bus frequency, core frequency, VID settings, and cache sizes. Not all operating systems can support multiple processors with mixed frequencies. Intel does not support or validate operation of processors with different cache sizes. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported, and is outlined in the Intel(R) XeonTM Processor Specification Update. Additional details are provided in AP-485, the Intel Processor Identification and the CPUID Instruction application note. The Intel Xeon processor with 533 MHz Front Side Bus does not sample the pins IGNNE#, LINT[0]/INTR, LINT[1]/NMI, and A20M# to establish the core to front side bus ratio. Rather, the processor runs at its tested frequency at initial power-on. If the processor needs to run at a lower core frequency, as must be done when a higher speed processor is added to a system that contains a lower frequency processor, the system BIOS is able to effect the change in the core to front side bus ratio. 2.6 Voltage Identification The VID specification for the processor is defined in this datasheet, and is supported by power delivery solutions designed according to the Dual Intel(R) Xeon TM Processor Voltage Regulator Down (VRD) Design Guidelines, VRM 9.0 DC-DC Converter Design Guidelines, and VRM 9.1 DC-DC Converter Design Guidelines. The minimum voltage is provided in Table 6, and varies with processor frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator design can work with all supported processor frequencies. Note that the VID pins will drive valid and correct logic levels when the Intel(R) XeonTM processor with 533 MHz Front Side Bus is provided with a valid voltage applied to the SM_VCC pins. VID_VCC must be correct and stable prior to enabling the output of the VRM that supplies VCC. Similarly, the output of the VRM must be disabled before VID_VCC becomes invalid. Refer to Figure 17 for details. The processor uses five voltage identification pins, VID[4:0], to support automatic selection of processor voltages. Table 3 specifies the voltage level corresponding to the state of VID[4:0]. A `1' in this table refers to a high voltage and a `0' refers to low voltage level. If the processor socket is empty (VID[4:0] = 11111), or the VRD or VRM cannot supply the voltage that is requested, it must disable its voltage output. For further details, see the Dual Intel(R) XeonTM Processor Voltage Regulator Down (VRD) Design Guidelines, or VRM 9.0 DC-DC Converter Design Guidelines or the VRM 9.1 DC-DC Converter Design Guidelines. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 15 Table 3. Voltage Identification Definition Processor Pins 2.6.1 VID4 VID3 VID2 VID1 VID0 VCC_VID (V) 1 1 1 1 1 VRM output off 1 1 1 1 0 1.100 1 1 1 0 1 1.125 1 1 1 0 0 1.150 1 1 0 1 1 1.175 1 1 0 1 0 1.200 1 1 0 0 1 1.225 1 1 0 0 0 1.250 1 0 1 1 1 1.275 1 0 1 1 0 1.300 1 0 1 0 1 1.325 1 0 1 0 0 1.350 1 0 0 1 1 1.375 1 0 0 1 0 1.400 1 0 0 0 1 1.425 1 0 0 0 0 1.450 0 1 1 1 1 1.475 0 1 1 1 0 1.500 0 1 1 0 1 1.525 0 1 1 0 0 1.550 0 1 0 1 1 1.575 0 1 0 1 0 1.600 0 1 0 0 1 1.625 0 1 0 0 0 1.650 0 0 1 1 1 1.675 0 0 1 1 0 1.700 0 0 1 0 1 1.725 0 0 1 0 0 1.750 0 0 0 1 1 1.775 0 0 0 1 0 1.800 0 0 0 0 1 1.825 0 0 0 0 0 1.850 Mixing Processors of Different Voltages Mixing processors operating with different VID settings (voltages) is not supported and will not be validated by Intel. 16 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 2.7 Reserved Or Unused Pins All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to VCC, VSS, or to any other signal (including one another) can result in component malfunction or incompatibility with future processors. See Chapter 5.0 for a pin listing of the processor and for the location of all Reserved pins. For reliable operation, unused inputs or bidirectional signals should always be connected to an appropriate signal level. In a system-level design, on-die termination has been included on the processor to allow signal termination to be accomplished by the processor silicon. Most unused AGTL+ inputs should be left as no connects, as AGTL+ termination is provided on the processor silicon. However, see Table 4 for details on AGTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value for the on-die termination resistors (RTT). See Table 12. TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and all used outputs must be terminated on the baseboard. Unused outputs may be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design Guide. All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which matches the trace impedance within 10 . TESTHI[3:0] and TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if desired. However, utilization of boundary scan test will not be functional if these pins are connected together. TESTHI4 must always be pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for TESTHI[6:0] pins should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 , then a pull-up resistor value between 40 and 60 should be used. The TESTHI[6:0] termination recommendations provided in the Intel(R) XeonTM Processor Datasheet are also suitable for the Intel(R) XeonTM processor with 533 MHz Front Side Bus. However, Intel recommends new designs or designs undergoing design updates follow the trace impedance matching termination guidelines outlined in this section. 2.8 Front Side Bus Signal Groups In order to simplify the following discussion, the front side bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 17 rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous and asynchronous. Table 4. Front Side Bus Signal Groups Signal Group Signals 1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, BR[3:1]#3,4, DEFER#, RESET#4, RS[2:0]#, RSP#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#7, BNR#7, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7 Signals AGTL+ Source Synchronous I/O Synchronous to assoc. strobe Associated Strobe REQ[4:0]#,A[16:3]# 6 ADSTB0# A[35:17]# 5 ADSTB1# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3# AGTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# Asynchronous GTL+ Input 4 Asynchronous A20M#5, IGNNE# 5, INIT#6, LINT0/INTR5, LINT1/NMI5, SLP#, STPCLK# Asynchronous GTL+ Output 4 Asynchronous FERR#, IERR#, THERMTRIP#, PROCHOT# Front Side Bus Clock Clock BCLK1, BCLK0 TAP Input 2 Synchronous to TCK TCK, TDI, TMS, TRST# TAP Output 2 Synchronous to TCK TDO Power/Other Power/Other BSEL[1:0], COMP[1:0], GTLREF, ODTEN, Reserved, SKTOCC#, TESTHI[6:0],VID[4:0], VCC, VID_VCC8, VCCA, VCCIOPLL, VSSA, VSS, VCCSENSE, VSSSENSE, PWRGOOD NOTES: 1. Refer to Section 5.2 for signal descriptions. 2. These signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design Guide and corresponding Design Guide for termination requirements and further details. 3. The Intel(R) XeonTM processor with 533MHz Front Side Bus utilizes only BR0# and BR1#. BR2# and BR3# are not driven by the processor but must be terminated to VCC. For additional details regarding the BR[3:0]# signals, see Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines. 4. These signals do not have on-die termination. Refer to corresponding Platform Design Guidelines for termination requirements. 5. Note that Reset initialization function of these pins is now a software function on the Intel(R) XeonTM processor with 533MHz Front Side Bus. 6. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration options. See Section 7.1 for details. 7. These signals may be driven simultaneously by multiple agents (wired-or). 8. VID_Vcc is required for correct VID logic operation of the Intel(R) XeonTM processor with 533 MHz Front Side Bus. Refer to Figure 17 for details. 18 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 2.9 Asynchronous GTL+ Signals The Intel(R) XeonTM Processor with 533 MHz Front Side Bus does not utilize CMOS voltage levels on any signals that connect to the processor silicon. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the same DC requirements as AGTL+ signals, however the outputs are not driven high (during the logical 0to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous GTL+ signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them. See Table 10 for the DC specifications for the asynchronous GTL+ signal groups. 2.10 Maximum Ratings Table 5 lists the processor's maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. Table 5. Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes TSTORAGE Processor storage temperature -40 85 C 2 VCC Any processor supply voltage with respect to V SS -0.3 1.75 V 1 VinAGTL+ AGTL+ buffer DC input voltage with respect to V SS -0.1 1.75 V VinGTL+ Async GTL+ buffer DC input voltage with respect to Vss -0.1 1.75 V IVID Max VID pin current 5 mA 1. This rating applies to any pin of the processor. 2. Contact Intel for storage requirements in excess of one year. 2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal definitions. The voltage and current specifications for all versions of the processor are detailed in Table 6. For platform planning refer to Figure 3. Notice that the graphs include Thermal Design Power (TDP) associated with the maximum current levels. The DC specifications for the AGTL+ signals are listed in Table 8. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 19 Table 6 through Table 11 list the processor DC specifications and are valid only while meeting specifications for case temperature (TCASE as specified in Chapter 6.0), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. 20 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Table 6. Voltage and Current Specifications Symbol VCC VID Unit Notes1 1.353 1.461 1.5 V 2, 3, 4, 5,11, 12 1.344 1.456 1.5 V 2, 3, 4, 5,11, 12 1.452 1.5 V 2, 3, 4, 5,11, 12 1.331 1.450 1.5 V 2, 3, 4, 5,11, 12 3.06 GHz 1.352 1.467 1.525 V 2, 3, 4, 5,11, 12 All freq. 3.135 3.465 V 8 Core Freq Min 2 GHz VCC for Intel Xeon processor with 533 MHz Front Side Bus 2.40 GHz 2.66 GHz 1.334 2.80 GHz SMBus supply voltage SM_VCC Max Parameter Typ Refer to Figure 3 3.30 2 GHz 45.4 A 4, 5 2.40 GHz 51.4 A 4, 5 2.66 GHz 57.1 A 4, 5 2.80 GHz 59.1 A 4, 5 3.06 GHz 69.1 A 4, 5 ICC for PLL power pins All freq 60 mA 9 ICC_GTLREF ICC for GTLREF pins All freq 15 A 10 ISGnt/ISLP ICC Stop-Grant/Sleep All freq 25 A 6 ICC TCC active All freq 18.6 A 7 ICC for Intel Xeon processor with 533 MHz Front Side Bus ICC ICC_PLL ITCC NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processors. 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.6 and Table 3 for more information. 3. The voltage specification requirements are measured across vias on the platform for the VCC_SENSE and VSS_SENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 milliohm minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 4. The processor should not be subjected to any static Vcc level that exceeds the voltage vs current load-line for any given current loading (as shown in figure 3 for VID=1.500V and figure 4 for VID=1.525V). Moreover, Vcc should never exceed Vcc_VID. Failure to adhere to this specification can shorten the processor lifetime. 5. Vcc_max and Vcc_min are defined at a load of Icc_max. Icc_max is defined at Vcc_max 6. The current specified is also for AutoHALT State. 7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT#. 8. VID_VCC is required for correct operation of the processor VID logic. Refer to Figure 17 for details. 9. This specification applies to the PLL power pins VCCA and VCCIOPLL. See Section 2.5 for details. This parameter is based on design characterization and is not tested 10.This specification applies to each GTLREF pin. 11. The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. 12.Adherence to this loadline specification is required to ensure reliable processor operation. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 21 Figure 3. Intel(R) XeonTM processor with 533 MHz Front Side Bus Voltage-Current Projections (VID 1.5V) Maximum Processor Voltage (VDC) 1.51 1.50 1.49 1.48 1.47 1.46 1.45 1.44 0 10 20 30 40 50 60 70 Processor Current (A) 22 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 4. Intel Xeon processor with 533 MHz Front Side Bus Voltage-Current Projections (VID 1.525V) Table 7. Front Side Bus Differential BCLK Specifications Notes Symbol Parameter Min Typ Max Unit Figure VL Input Low Voltage -.150 0.000 N/A V 7 VH Input High Voltage 0.660 0.710 0.850 V 7 VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 7, 7 2,8 VCROSS(rel) Relative Crossing Point V 7, 7 2,3,8,9 VCROSS Range of Crossing Points N/A N/A 0.140 V 7, 7 2,10 VOV Overshoot N/A N/A VH + 0.3 V 7 4 5 0.250 + 0.5(VHavg - 0.710) N/A 0.550 + 0.5(VHavg - 0.710) VUS Undershoot -0.300 N/A N/A V 7 VRBM Ringback Margin 0.200 N/A N/A V 6 VTM Threshold Margin Vcross - 0.100 N/A Vcross + 0.100 V 6 1 NOTES:. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 23 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3. VHavg is the statistical average of the VH measured by the oscilloscope. 4. Overshoot is defined as the absolute value of the maximum voltage. 5. Undershoot is defined as the absolute value of the minimum voltage. 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes. 10.VCROSS is defined as the total variation of all crossing voltages as defined in note 2. Table 8. AGTL+ Signal Group DC Specifications Symbol Parameter Min Max Notes Unit 1,7 VIH Input High Voltage 1.10 * GTLREF VCC V 2, 4, 6 VIL Input Low Voltage 0.0 0.90 * GTLREF V 3, 6 VOH Output High Voltage N/A VCC V 4, 6 IOL Output Low Current N/A VCC / (0.50 * RTT_min + RON_min) mA 6 9 = 50 Pin Leakage High N/A 100 A ILO Pin Leakage Low N/A 500 A 8 RON Buffer On Resistance 7 11 5, 7 IHI NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 3. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 4. VIH and VON may experience excursions above V CC. However, input signal drivers must comply with the signal quality specifications in Chapter 3.0. 5. Refer to the Intel(R)XeonTM Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V characteristics. 6. The VCC referred to in these specifications refers to instantaneous V CC. 7. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with RTT enabled. 8. Leakage to VCC with pin held at 300 mV. 9. Leakage to VSS with pin held at VCC. Table 9. TAP and PWRGOOD Signal Group DC Specifications Symbol 24 Unit Notes 1, 2 Parameter Min Max VHYS TAP Input Hysteresis 200 300 VT+ TAP input low to high threshold voltage 0.5 * (VCC + VHYS_MIN) 0.5 * (VCC + VHYS_MAX) 5 VT- TAP input high to low threshold voltage 0.5 * (VCC - VHYS_MAX) 0.5 * (VCC - VHYS_MIN) 5 VOH Output High Voltage N/A VCC V 3, 5 IOL Output Low Current 40 mA 6, 7 IHI Pin Leakage High N/A 100 A 10 ILO Pin Leakage Low N/A 500 A 9 8 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz RON Buffer On Resistance 8.75 13.75 4 NOTES:. 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. All outputs are open drain 3. TAP signal group must meet the system signal quality specification in Chapter 3.0. 4. Refer to the Intel(R) XeonTM Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V characteristics. 5. The VCC referred to in these specifications refers to instantaneous VCC. 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 7. VOL_MAX of 0.300V is guaranteed when driving a test load. 8. VHYS represents the amount of hysteresis, nominally centered about 0.5*VCC, for all TAP inputs. 9. Leakage to VCC with Pin held at 300 mV. 10.Leakage to VSS with pin held at VCC. Table 10. Asynchronous GTL+ Signal Group DC Specifications Parameter Min Max Unit Notes1, 7 VIH Input High Voltage 1.10 * GTLREF VCC V 3, 5, 7 VIL Input Low Voltage 0.0 0.90 * GTLREF V 4, 6 VOH Output High Voltage N/A VCC V 2, 5, 7 IOL Output Low Current 50 mA 8,9 IHI Pin Leakage High N/A 100 A 11 ILO Pin Leakage Low N/A 500 A 10 RON Buffer On Resistance 7 11 6 Symbol NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. All outputs are open drain 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 5. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Chapter 3.0. 6. Refer to the Intel(R)XeonTMProcessor with 533 MHz Front Side Bus Signal Integrity Models for I/V characteristics. 7. The VCC referred to in these specifications refers to instantaneous VCC. 8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 9. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with RTT enabled. 10. Leakage to VCC with Pin held at 300 mV. 11. Leakage to VSS with pin held at VCC. NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. These parameters are based on design characterization and are not tested. Table 11. BSEL[1:0] and VID[4:0] DC Specifications Symbol Parameter Min Max Unit Notes 1 Ron (BSEL) Buffer On Resistance 9.2 14.3 2 Ron (VID) Buffer On Resistance 7.8 12.8 2 IHI Pin Leakage Hi N/A 100 A 3 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 25 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to Vss with pin held at 2.50V. 2.12 AGTL+ Front Side Bus Specifications Routing topologies are dependent on the number of processors supported and the chipset used in the design. Please refer to the appropriate platform design guidelines. In most cases, termination resistors are not required as these are integrated into the processor. See Table 4 for details on which AGTL+ signals do not include on-die termination.The termination resistors are enabled or disabled through the ODTEN pin. To enable termination, this pin should be pulled up to VCC through a resistor and to disable termination, this pin should be pulled down to VSS through a resistor. For optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 , then a value between 40 and 60 should be used. The processor's on-die termination must be enabled for the end agent only. Please refer to Table 12 for termination resistor values. For more details on platform design see the appropriate platform design guidelines. Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF. Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be generated on the baseboard using high precision voltage divider circuits. It is important that the baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on platform design see the appropriate platform design guidelines. Table 12. AGTL+ Bus Voltage Definitions Min Typ Max Units Notes 1 Bus Reference Voltage 2/3 * VCC - 2% 2/3 * VCC 2/3 * VCC + 2% V 2, 3, 6 Bus Reference Voltage 0.63*VCC - 2% 0.63*VCC 0.63*VCC + 2% V 2, 3, 6, RTT Termination Resistance 36 41 46 4 RTT New Design Termination Resistance 45 50 55 4, 9 COMP[1:0] COMP Resistance 42.77 43.2 43.63 5, 8 COMP[1:0] New Design COMP Resistance 49.55 50 50.45 5, 8, 9 Symbol GTLREF GTLREF New Design Parameter NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of VCC. 3. GTLREF is generated from VCC on the baseboard by a voltage divider of 1 percent resistors. Refer to the appropriate platform design guidelines for implementation details. 4. RTT is the on-die termination resistance measured from VCC to 1/3 VCC at the AGTL+ output driver. Refer to the Intel(R) XeonTM Processor with 533MHz Front Side Bus Signal Integrity Models for I/V characteristics. 5. COMP resistors are pull downs to VSS provided on the baseboard with 1% tolerance. See the appropriate platform design guidelines for implementation details. 6. The VCC referred to in these specifications refers to instantaneous V CC. 7. The COMP resistance value varies by platform. Refer to the appropriate platform design guideline for the recommended COMP resistance value. 26 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 8. The values for RTT and COMP noted as `New Designs' apply to designs that are optimized for the Intel(R) XeonTM processor with 533MHz Front Side Bus. Refer to the appropriate platform design guideline for the recommended COMP resistance value. 9. This specification applies to the Intel(R) XeonTMprocessor with 533MHz Front Side Bus when implemented in platforms that do not include forward compatibility with future processors. Table 13. Miscellaneous Signals + Specifications T# Parameter Min T39: THERMTRIP# to Vcc Removal Max Unit Figure 0.5 S 6 Notes Figure 5. Electrical Test Circuit Vtt Vtt Rload = 50 ohms Zo = 50 ohms, d=420mils, So=169ps/in L = 2.4nH C = 1.2pF AC Timings specified at pad. Figure 6. THERMTRIP# to VCC Timing THERMTRIP# Power Down Sequence T39 THERMTRIP# Vcc T39 < 0.5 seconds Note: THERMTRIP# is undefined when RESET is active Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 27 This page intentionally left blank. 28 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 3.0 Mechanical Specifications The Intel(R) XeonTM Processor with 533 MHz Front Side Bus uses the Flip Chip Micro-Pin Grid Array (FC-mPGA) package containing the processor die covered by an integrated heat spreader (IHS) Mechanical specifications for the processor are given in this section. See Section 1.1 for terminology definitions. Figure 7 provides a basic assembly drawing and includes the components which make up the entire processor. Package dimensions are provided in Table 14. The Intel(R) XeonTM processor with 533 MHz Front Side Bus utilizes a surface mount 604-pin zeroinsertion force (ZIF) socket for installation into the baseboard. See the 604-Pin Socket Design Guidelines for further details on the processor socket. For Figure 9 through Figure 13, the following notes apply: 1. Unless otherwise specified, the following drawings are dimensioned in millimeters. 2. All dimensions are not tested, but are guaranteed by design characterization. 3. Figures and drawings labelled as "Reference Dimensions" are provided for informational purposes only. Reference Dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. Reference Dimensions are NOT checked as part of the processor manufacturing process. Unless noted as such, dimensions in parentheses without tolerances are Reference Dimensions. 4. Drawings are not to scale. Figure 7. FC-mPGA2 Processor Package Assembly Drawing 1 2 3 Note: applies to Intel Xeon processor in the FC-mPGA2 package. 1. Integrated Heat Spreader (IHS) 2. Processor die 3. FC-mPGA2 package 4. Land side Capacitors 5. Package Pin Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 29 3.1 Mechanical Specifications Figure 8. FC-mPGA Processor Package Top View: Component Placement Detail Pin A1 30 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 9. Intel(R) XeonTM Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package Drawing Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 31 Table 14. Dimensions for the Intel(R) XeonTM Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package Symbol Min 42.40 30.90 3.42 1.95 18.80 37.85 A B E F G H J K L M N R T P Pin Tp 14.99 30.23 0.26 Milimeters Nominal 42.50 31.00 3.60 2.03 19.05 38.10 6.35 12.70 15.24 30.48 6.35 1.27 12.70 0.31 Notes Max 42.60 31.10 3.78 2.11 19.30 38.35 Nominal Component Keepin Nominal Component Keepin 15.49 30.73 Nominal Component Keepin Nominal 0.36 0.25 Pin Diameter Figure 10 details the keep-in zone for components mounted to the top side of the processor interposer. The components include the EEPROM, thermal sensor, resistors and capacitors. Figure 10. FC-mPGA2 Processor Package Top View: Component Height Keep-in 1.61 COMPONENT KEEPOUT CROSS HATCHED AREA 2.27 mm MAX ALLOWABLE COMPONENT HEIGHT 7.5 15.5 7.5 1.61 15.5 32 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 11 details the keep-in specification for pin-side components. The processor may contain pin side capacitors mounted to the processor package. These capacitors will be exposed within the opening of the interposer cavity. Figure 11. FC-mPGA2 Processor Package Cross Section View: Pin Side Component Keep-in IHS 1.5 mm Component Keepin FC-mPGA2P 12.7 mm Component Keepin Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 33 Figure 12. FC-mPGA2 Processor Package: Pin Detail 1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni. 2. 0.254 Diametric true position, pin to pin. 34 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 13 details the flatness and tilt specifications for the IHS of the Intel Xeon processor with 533 MHz Front Side Bus, respectively. Tilt is measured with the reference datum set to the bottom of the processor interposer. Figure 13. IHS Flatness and Tilt Drawing 0.080 3.2 Processor Package Load Specifications Table 15 provides dynamic and static load specifications for the processor IHS. These mechanical load limits should not be exceeded during heat sink assembly, mechanical stress testing, or standard drop and shipping conditions. The heat sink attach solutions must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heat sink-toprocessor thermal interface. It is not recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions. Table 15. Package Dynamic and Static Load Specifications Parameter Static Dynamic Max Unit Unit 50 lbf 1, 2, 3 lbf 1, 2, 4, 5 50 + 1 lb * 50G input * 1.8 (AF) = 140 NOTES: 1. This specification applies to a uniform compressed load. 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. 3. These parameters are based on design characterization and not tested. 4. Dynamic loading specifications are defined assuming a maximum duration of 11ms. 5. The heatsink weight is assumed to be one pound. Shock input to the system during shock testing is assumed to be 50 G's. AF is the amplification factor. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 35 3.3 Insertion Specifications The processor can be inserted and removed 15 times from a 604-pin socket meeting the mPGA604 Socket Design Guidelines document. Note that this specification is based on design characterization and is not tested. 3.4 Mass Specifications Table 16 specifies the processors mass. This includes all components which make up the entire processor product. Table 16. Processor Mass Processor Mass (grams) Intel(R) XeonTM Processor with 533 MHz Front Side Bus 3.5 25 Materials The processor is assembled from several components. The basic material properties are described in Table 17. Table 17. Processor Material Properties Component Integrated Heat Spreader FC-BGA Interposer Interposer pins 36 Material Nickel plated copper BT Resin FR4 Kovar with Gold over nickel Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 3.6 Markings The following section details the processor top-side laser markings. It is provided to aid in the identification of the processor. Figure 14. Processor Top-Side Markings Dynamic Laser Mark Area with 2D Matrix Group A Line1 Group A Line2 Group B Line1 Group B Line2 2D Matrix encodes ATPO number and Serial number Pin A1 NOTE: 1. Character size for laser markings is: height 0.050" (1.27mm), width 0.032" (0.81mm). 2. All characters will be in upper case. Figure 15. Processor Bottom-Side Markings Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 37 3.7 Pin-Out Diagram This section provides two view of the processor pin grid. Figure 16 and Figure 17 detail the coordinates of the processor pins. Figure 16. Processor Pin Out Diagram: Top View COMMON CLOCK 1 3 COMMON CLOCK ADDRESS 5 7 9 11 13 15 17 19 21 23 Async / JTAG 25 27 29 31 A A B B C D C D E F G G H J K L M N P R T H J K L M N P R T U V W Y AA AB AC AD AE U V W Y AA AB AC AD AE 2 4 6 8 10 12 14 16 18 20 22 DATA CLOCKS = Signal = Power = Ground 38 Vcc/Vss Vcc/Vss E F 24 26 28 SMBus = SM_VCC = GTLREF = Reserved = Mechanical Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Processor Pin Out Diagram: Bottom View Async / JTAG 31 29 27 COMMON CLOCK 25 23 21 COMMON CLOCK ADDRESS 19 17 15 13 11 9 7 5 3 1 A A B C B C D D E F G Vcc/Vss E F G H J K L M N P R T H J K L M N P R T U V W Y AA AB AC AD Vcc/Vss Figure 17. U V W Y AA AB AC AD AE AE 28 SMBus 26 24 22 20 18 16 14 12 10 DATA = Signal = Power = Ground 8 6 4 2 CLOCKS = SM_VCC = GTLREF = Reserved Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz = Mechanical 39 This page intentionally left blank. 40 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Intel(R) XeonTM Processor with 533MHz Front Side Bus 4.0 Pin Listing and Signal Definitions 4.1 Processor Pin Assignments Section 2.8 contains the front side bus signal groups in Table 4 for the Intel(R) XeonTM Processor with 533 MHz Front Side Bus. This section provides a sorted pin list in Table 38 and Table 39. Table 38 is a listing of all processor pins ordered alphabetically by pin name. Table 39 is a listing of all processor pins ordered by pin number. 4.1.1 Pin Listing by Pin Name Table 38. Pin Listing by Pin Name Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction A3# A22 Source Sync Input/Output A4# A20 Source Sync Input/Output A5# B18 Source Sync Input/Output A6# C18 Source Sync Input/Output A7# A19 Source Sync Input/Output A8# C17 Source Sync Input/Output A9# D17 Source Sync Input/Output A10# A13 Source Sync Input/Output A11# B16 Source Sync Input/Output A12# B14 Source Sync Input/Output A13# B13 Source Sync Input/Output A14# A12 Source Sync Input/Output A15# C15 Source Sync Input/Output A16# C14 Source Sync Input/Output A17# D16 Source Sync Input/Output A18# D15 Source Sync Input/Output A19# F15 Source Sync Input/Output A20# A10 Source Sync Input/Output A21# B10 Source Sync Input/Output A22# B11 Source Sync Input/Output A23# C12 Source Sync Input/Output A24# E14 Source Sync Input/Output A25# D13 Source Sync Input/Output A26# A9 Source Sync Input/Output A27# Datasheet B8 Source Sync Input/Output Pin Name Pin No. Signal Buffer Type Direction A28# E13 Source Sync Input/Output A29# D12 Source Sync Input/Output A30# C11 Source Sync Input/Output A31# B7 Source Sync Input/Output A32# A6 Source Sync Input/Output A33# A7 Source Sync Input/Output A34# C9 Source Sync Input/Output A35# C8 Source Sync Input/Output A20M# F27 Async GTL+ Input ADS# D19 Common Clk Input/Output ADSTB0# F17 Source Sync Input/Output ADSTB1# F14 Source Sync Input/Output AP0# E10 Common Clk Input/Output AP1# D9 Common Clk Input/Output BCLK0 Y4 Sys Bus Clk Input BCLK1 W5 Sys Bus Clk Input BINIT# F11 Common Clk Input/Output BNR# F20 Common Clk Input/Output BPM0# F6 Common Clk Input/Output BPM1# F8 Common Clk Input/Output BPM2# E7 Common Clk Input/Output BPM3# F5 Common Clk Input/Output BPM4# E8 Common Clk Input/Output BPM5# E4 Common Clk Input/Output BPRI# D23 Common Clk Input BR0# D20 Common Clk Input/Output 41 Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction Pin No. Signal Buffer Type Direction BR1# F12 Common Clk Input D32# AB16 Source Sync Input/Output BR2# 1 E11 Common Clk Input D33# AA16 Source Sync Input/Output 1 D10 Common Clk Input D34# AC17 Source Sync Input/Output Power/Other Output2 D35# AE13 Source Sync Input/Output 2 BR3# BSEL0 42 Pin Name AA3 BSEL1 AB3 Power/Other Output D36# AD18 Source Sync Input/Output COMP0 AD16 Power/Other Input D37# AB15 Source Sync Input/Output COMP1 E16 Power/Other Input D38# AD13 Source Sync Input/Output D0# Y26 Source Sync Input/Output D39# AD14 Source Sync Input/Output D1# AA27 Source Sync Input/Output D40# AD11 Source Sync Input/Output D2# Y24 Source Sync Input/Output D41# AC12 Source Sync Input/Output D3# AA25 Source Sync Input/Output D42# AE10 Source Sync Input/Output D4# AD27 Source Sync Input/Output D43# AC11 Source Sync Input/Output D5# Y23 Source Sync Input/Output D44# AE9 Source Sync Input/Output D6# AA24 Source Sync Input/Output D45# AD10 Source Sync Input/Output D7# AB26 Source Sync Input/Output D46# AD8 Source Sync Input/Output D8# AB25 Source Sync Input/Output D47# AC9 Source Sync Input/Output D9# AB23 Source Sync Input/Output D48# AA13 Source Sync Input/Output D10# AA22 Source Sync Input/Output D49# AA14 Source Sync Input/Output D11# AA21 Source Sync Input/Output D50# AC14 Source Sync Input/Output D12# AB20 Source Sync Input/Output D51# AB12 Source Sync Input/Output D13# AB22 Source Sync Input/Output D52# AB13 Source Sync Input/Output D14# AB19 Source Sync Input/Output D53# AA11 Source Sync Input/Output D15# AA19 Source Sync Input/Output D54# AA10 Source Sync Input/Output D16# AE26 Source Sync Input/Output D55# AB10 Source Sync Input/Output D17# AC26 Source Sync Input/Output D56# AC8 Source Sync Input/Output D18# AD25 Source Sync Input/Output D57# AD7 Source Sync Input/Output D19# AE25 Source Sync Input/Output D58# AE7 Source Sync Input/Output D20# AC24 Source Sync Input/Output D59# AC6 Source Sync Input/Output D21# AD24 Source Sync Input/Output D60# AC5 Source Sync Input/Output D22# AE23 Source Sync Input/Output D61# AA8 Source Sync Input/Output D23# AC23 Source Sync Input/Output D62# Y9 Source Sync Input/Output D24# AA18 Source Sync Input/Output D63# AB6 Source Sync Input/Output D25# AC20 Source Sync Input/Output DBSY# F18 Common Clk Input/Output D26# AC21 Source Sync Input/Output DEFER# C23 Common Clk Input D27# AE22 Source Sync Input/Output DBI0# AC27 Source Sync Input/Output D28# AE20 Source Sync Input/Output DBI1# AD22 Source Sync Input/Output D29# AD21 Source Sync Input/Output DBI2# AE12 Source Sync Input/Output D30# AD19 Source Sync Input/Output DBI3# AB9 Source Sync Input/Output D31# AB17 Source Sync Input/Output DP0# AC18 Common Clk Input/Output Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 1 38. Pin Listing by Pin Name Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No. Signal Buffer Type Direction DP1# AE19 Common Clk Input/Output Reserved B1 Reserved Reserved DP2# AC15 Common Clk Input/Output Reserved C5 Reserved Reserved DP3# AE17 Common Clk Input/Output Reserved D25 Reserved Reserved DRDY# E18 Common Clk Input/Output Reserved W3 Reserved Reserved DSTBN0# Y21 Source Sync Input/Output Reserved Y3 Reserved Reserved DSTBN1# Y18 Source Sync Input/Output THERMDA Y27 Anode Pin Output DSTBN2# Y15 Source Sync Input/Output THERMDC Y28 Cathode Pin Output DSTBN3# Y12 Source Sync Input/Output Reserved AC1 Reserved Reserved DSTBP0# Y20 Source Sync Input/Output Reserved AD1 Reserved Reserved DSTBP1# Y17 Source Sync Input/Output SMB_PRT AE4 Ground VSS DSTBP2# Y14 Source Sync Input/Output Reserved AE15 Reserved Reserved DSTBP3# Y11 Source Sync Input/Output Reserved AE16 Reserved Reserved FERR# E27 Async GTL+ Output RESET# Y8 Common Clk Input GTLREF W23 Power/Other Input RS0# E21 Common Clk Input GTLREF W9 Power/Other Input RS1# D22 Common Clk Input GTLREF F23 Power/Other Input RS2# F21 Common Clk Input GTLREF F9 Power/Other Input RSP# C6 Common Clk Input HIT# E22 Common Clk Input/Output SKTOCC# A3 Power/Other Output HITM# A23 Common Clk Input/Output SLP# AE6 Async GTL+ Input IERR# E5 Async GTL+ Output NC AD28 Reserved IGNNE# C26 Async GTL+ Input NC AC28 Reserved INIT# D6 Async GTL+ Input NC AC29 Reserved LINT0 B24 Async GTL+ Input NC AA29 Reserved LINT1 G23 Async GTL+ Input NC AB29 Reserved LOCK# A17 Common Clk Input/Output NC AB28 Reserved MCERR# D7 Common Clk Input/Output NC AA28 Reserved ODTEN B5 Power/Other Input NC Y29 Reserved PROCHOT# B25 Async GTL+ Output NC AE28 Reserved PWRGOOD AB7 Async GTL+ Input NC AE29 Reserved REQ0# B19 Source Sync Input/Output NC AD29 Reserved REQ1# B21 Source Sync Input/Output SMI# C27 Async GTL+ Input REQ2# C21 Source Sync Input/Output STPCLK# D4 Async GTL+ Input REQ3# C20 Source Sync Input/Output TCK E24 TAP Input REQ4# B22 Source Sync Input/Output TDI C24 TAP Input Reserved A1 Reserved Reserved TDO E25 TAP Output Reserved A4 Reserved Reserved TESTHI0 W6 Power/Other Input Reserved A15 Reserved Reserved TESTHI1 W7 Power/Other Input Reserved A16 Reserved Reserved TESTHI2 W8 Power/Other Input Reserved A26 Reserved Reserved TESTHI3 Y6 Power/Other Input Datasheet 43 Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name Pin Name Table 38. Pin Listing by Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No. Signal Buffer Type TESTHI4 AA7 Power/Other Input VCC E26 Power/Other TESTHI5 AD5 Power/Other Input VCC E28 Power/Other TESTHI6 AE5 Power/Other Input VCC E30 Power/Other THERMTRIP# F26 Async GTL+ Output VCC F1 Power/Other 44 TMS A25 TAP Input VCC F4 Power/Other TRDY# E19 Common Clk Input VCC F10 Power/Other TRST# F24 TAP Input VCC F16 Power/Other VCC A2 Power/Other VCC F22 Power/Other VCC A8 Power/Other VCC F29 Power/Other VCC A14 Power/Other VCC F31 Power/Other VCC A18 Power/Other VCC G2 Power/Other VCC A24 Power/Other VCC G4 Power/Other VCC A28 Power/Other VCC G6 Power/Other VCC A30 Power/Other VCC G8 Power/Other VCC B4 Power/Other VCC G24 Power/Other VCC B6 Power/Other VCC G26 Power/Other VCC B12 Power/Other VCC G28 Power/Other VCC B20 Power/Other VCC G30 Power/Other VCC B26 Power/Other VCC H1 Power/Other VCC B29 Power/Other VCC H3 Power/Other VCC B31 Power/Other VCC H5 Power/Other VCC C2 Power/Other VCC H7 Power/Other VCC C4 Power/Other VCC H9 Power/Other VCC C10 Power/Other VCC H23 Power/Other VCC C16 Power/Other VCC H25 Power/Other VCC C22 Power/Other VCC H27 Power/Other VCC C28 Power/Other VCC H29 Power/Other VCC C30 Power/Other VCC H31 Power/Other VCC D1 Power/Other VCC J2 Power/Other VCC D8 Power/Other VCC J4 Power/Other VCC D14 Power/Other VCC J6 Power/Other VCC D18 Power/Other VCC J8 Power/Other VCC D24 Power/Other VCC J24 Power/Other VCC D29 Power/Other VCC J26 Power/Other VCC D31 Power/Other VCC J28 Power/Other VCC E2 Power/Other VCC J30 Power/Other VCC E6 Power/Other VCC K1 Power/Other VCC E12 Power/Other VCC K3 Power/Other VCC E20 Power/Other VCC K5 Power/Other Direction Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VCC K7 VCC VCC VCC Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Power/Other VCC P24 Power/Other K9 Power/Other VCC P26 Power/Other K23 Power/Other VCC P28 Power/Other K25 Power/Other VCC P30 Power/Other VCC K27 Power/Other VCC R1 Power/Other VCC K29 Power/Other VCC R3 Power/Other VCC K31 Power/Other VCC R5 Power/Other VCC L2 Power/Other VCC R7 Power/Other VCC L4 Power/Other VCC R9 Power/Other VCC L6 Power/Other VCC R23 Power/Other VCC L8 Power/Other VCC R25 Power/Other VCC L24 Power/Other VCC R27 Power/Other VCC L26 Power/Other VCC R29 Power/Other VCC L28 Power/Other VCC R31 Power/Other VCC L30 Power/Other VCC T2 Power/Other VCC M1 Power/Other VCC T4 Power/Other VCC M3 Power/Other VCC T6 Power/Other VCC M5 Power/Other VCC T8 Power/Other VCC M7 Power/Other VCC T24 Power/Other VCC M9 Power/Other VCC T26 Power/Other VCC M23 Power/Other VCC T28 Power/Other VCC M25 Power/Other VCC T30 Power/Other VCC M27 Power/Other VCC U1 Power/Other VCC M29 Power/Other VCC U3 Power/Other VCC M31 Power/Other VCC U5 Power/Other VCC N1 Power/Other VCC U7 Power/Other VCC N3 Power/Other VCC U9 Power/Other VCC N5 Power/Other VCC U23 Power/Other VCC N7 Power/Other VCC U25 Power/Other VCC N9 Power/Other VCC U27 Power/Other VCC N23 Power/Other VCC U29 Power/Other VCC N25 Power/Other VCC U31 Power/Other VCC N27 Power/Other VCC V2 Power/Other VCC N29 Power/Other VCC V4 Power/Other VCC N31 Power/Other VCC V6 Power/Other VCC P2 Power/Other VCC V8 Power/Other VCC P4 Power/Other VCC V24 Power/Other VCC P6 Power/Other VCC V26 Power/Other VCC P8 Power/Other VCC V28 Power/Other Datasheet Direction Direction 45 Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VCC V30 VCC W1 VCC 46 Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Power/Other VCC AE18 Power/Other Power/Other VCC AE24 Power/Other W25 Power/Other VCCA AB4 Power/Other Input VCC W27 Power/Other VCCIOPLL AD4 Power/Other Input VCC W29 Power/Other VCCSENSE B27 Power/Other Output VCC W31 Power/Other VID0 F3 Power/Other Output VCC Y10 Power/Other VID1 E3 Power/Other Output VCC Y16 Power/Other VID2 D3 Power/Other Output VCC Y2 Power/Other VID3 C3 Power/Other Output VCC Y22 Power/Other VID4 B3 Power/Other Output VCC Y30 Power/Other VSS A5 Power/Other VCC AA1 Power/Other VSS A11 Power/Other VCC AA4 Power/Other VSS A21 Power/Other VCC AA6 Power/Other VSS A27 Power/Other VCC AA12 Power/Other VSS A29 Power/Other VCC AA20 Power/Other VSS A31 Power/Other VCC AA26 Power/Other VSS B2 Power/Other VCC AA31 Power/Other VSS B9 Power/Other VCC AB2 Power/Other VSS B15 Power/Other VCC AB8 Power/Other VSS B17 Power/Other VCC AB14 Power/Other VSS B23 Power/Other VCC AB18 Power/Other VSS B28 Power/Other VCC AB24 Power/Other VSS B30 Power/Other VCC AB30 Power/Other VSS C1 Power/Other VCC AC3 Power/Other VSS C7 Power/Other VCC AC4 Power/Other VSS C13 Power/Other VCC AC10 Power/Other VSS C19 Power/Other VCC AC16 Power/Other VSS C25 Power/Other VCC AC22 Power/Other VSS C29 Power/Other VCC AC31 Power/Other VSS C31 Power/Other VCC AD2 Power/Other VSS D2 Power/Other VCC AD6 Power/Other VSS D5 Power/Other VCC AD12 Power/Other VSS D11 Power/Other VCC AD20 Power/Other VSS D21 Power/Other VCC AD26 Power/Other VSS D27 Power/Other VCC AD30 Power/Other VSS D28 Power/Other VCC AE3 Power/Other VSS D30 Power/Other VCC AE8 Power/Other VSS E1 Power/Other VCC AE14 Power/Other VSS E9 Power/Other Direction Direction Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VSS E15 VSS VSS Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Power/Other VSS K2 Power/Other E17 Power/Other VSS K4 Power/Other E23 Power/Other VSS K6 Power/Other VSS E29 Power/Other VSS K8 Power/Other VSS E31 Power/Other VSS K24 Power/Other VSS F2 Power/Other VSS K26 Power/Other VSS F7 Power/Other VSS K28 Power/Other VSS F13 Power/Other VSS K30 Power/Other VSS F19 Power/Other VSS L1 Power/Other VSS F25 Power/Other VSS L3 Power/Other VSS F28 Power/Other VSS L5 Power/Other VSS F30 Power/Other VSS L7 Power/Other VSS G1 Power/Other VSS L9 Power/Other VSS G3 Power/Other VSS L23 Power/Other VSS G5 Power/Other VSS L25 Power/Other VSS G7 Power/Other VSS L27 Power/Other VSS G9 Power/Other VSS L29 Power/Other VSS G25 Power/Other VSS L31 Power/Other VSS G27 Power/Other VSS M2 Power/Other VSS G29 Power/Other VSS M4 Power/Other VSS G31 Power/Other VSS M6 Power/Other VSS H2 Power/Other VSS M8 Power/Other VSS H4 Power/Other VSS M24 Power/Other VSS H6 Power/Other VSS M26 Power/Other VSS H8 Power/Other VSS M28 Power/Other VSS H24 Power/Other VSS M30 Power/Other VSS H26 Power/Other VSS N2 Power/Other VSS H28 Power/Other VSS N4 Power/Other VSS H30 Power/Other VSS N6 Power/Other VSS J1 Power/Other VSS N8 Power/Other VSS J3 Power/Other VSS N24 Power/Other VSS J5 Power/Other VSS N26 Power/Other VSS J7 Power/Other VSS N28 Power/Other VSS J9 Power/Other VSS N30 Power/Other VSS J23 Power/Other VSS P1 Power/Other VSS J25 Power/Other VSS P3 Power/Other VSS J27 Power/Other VSS P5 Power/Other VSS J29 Power/Other VSS P7 Power/Other VSS J31 Power/Other VSS P9 Power/Other Datasheet Direction Direction 47 Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VSS P23 VSS P25 VSS 48 Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Power/Other VSS V29 Power/Other Power/Other VSS V31 Power/Other P27 Power/Other VSS W2 Power/Other VSS P29 Power/Other VSS W4 Power/Other VSS P31 Power/Other VSS W24 Power/Other VSS R2 Power/Other VSS W26 Power/Other VSS R4 Power/Other VSS W28 Power/Other VSS R6 Power/Other VSS W30 Power/Other VSS R8 Power/Other VSS Y1 Power/Other VSS R24 Power/Other VSS Y5 Power/Other VSS R26 Power/Other VSS Y7 Power/Other VSS R28 Power/Other VSS Y13 Power/Other VSS R30 Power/Other VSS Y19 Power/Other VSS T1 Power/Other VSS Y25 Power/Other VSS T3 Power/Other VSS Y31 Power/Other VSS T5 Power/Other VSS AA2 Power/Other VSS T7 Power/Other VSS AA9 Power/Other VSS T9 Power/Other VSS AA15 Power/Other VSS T23 Power/Other VSS AA17 Power/Other VSS T25 Power/Other VSS AA23 Power/Other VSS T27 Power/Other VSS AA30 Power/Other VSS T29 Power/Other VSS AB1 Power/Other VSS T31 Power/Other VSS AB5 Power/Other VSS U2 Power/Other VSS AB11 Power/Other VSS U4 Power/Other VSS AB21 Power/Other VSS U6 Power/Other VSS AB27 Power/Other VSS U8 Power/Other VSS AB31 Power/Other VSS U24 Power/Other VSS AC2 Power/Other VSS U26 Power/Other VSS AC7 Power/Other VSS U28 Power/Other VSS AC13 Power/Other VSS U30 Power/Other VSS AC19 Power/Other VSS V1 Power/Other VSS AC25 Power/Other VSS V3 Power/Other VSS AC30 Power/Other VSS V5 Power/Other VSS AD3 Power/Other VSS V7 Power/Other VSS AD9 Power/Other VSS V9 Power/Other VSS AD15 Power/Other VSS V23 Power/Other VSS AD17 Power/Other VSS V25 Power/Other VSS AD23 Power/Other VSS V27 Power/Other VSS AD31 Power/Other Direction Direction Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 38. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VSS AE2 Power/Other VSS AE11 Power/Other VSS AE21 Power/Other VSS AE27 Power/Other VSSA AA5 Power/Other Datasheet Table 38. Pin Listing by Pin Name Direction Pin Name Pin No. Signal Buffer Type Direction VSSSENSE D26 Power/Other Output 1. In systems utilizing the Intel Xeon processor, the system designer must pull-up these signals to the processor VCC 2. Baseboard treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 133 MHz. Input 49 Intel(R) XeonTM Processor with 533MHz Front Side Bus 4.1.2 Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Pin No. 50 Pin Name Signal Buffer Type A1 Reserved Reserved A2 VCC Power/Other A3 SKTOCC# Power/Other A4 Reserved Reserved A5 VSS Power/Other A6 A32# Source Sync A7 A33# Source Sync A8 VCC Power/Other A9 A26# Source Sync Pin Name Signal Buffer Type B2 VSS Power/Other B3 VID4 Power/Other B4 VCC Power/Other Output B5 OTDEN Power/Other Reserved B6 VCC Power/Other B7 A31# Source Sync Input/Output Input/Output B8 A27# Source Sync Input/Output Input/Output B9 VSS Power/Other B10 A21# Source Sync Input/Output Input/Output B11 A22# Source Sync Input/Output Input/Output B12 VCC Power/Other B13 A13# Source Sync Input/Output A12# Source Sync Input/Output Direction Reserved Pin No. A10 A20# Source Sync A11 VSS Power/Other A12 A14# Source Sync Input/Output B14 A13 A10# Source Sync Input/Output B15 VSS Power/Other B16 A11# Source Sync VSS Power/Other Direction Output Input Input/Output A14 VCC Power/Other A15 Reserved Reserved Reserved B17 A16 Reserved Reserved Reserved B18 A5# Source Sync Input/Output Input/Output B19 REQ0# Common Clk Input/Output B20 VCC Power/Other Input/Output B21 REQ1# Common Clk Input/Output Input/Output B22 REQ4# Common Clk Input/Output B23 VSS Power/Other A17 LOCK# Common Clk A18 VCC Power/Other A19 A7# Source Sync A20 A4# Source Sync A21 VSS Power/Other A22 A3# Source Sync A23 HITM# Common Clk A24 VCC Power/Other A25 TMS TAP Input/Output B24 LINT0 Async GTL+ Input Input/Output B25 PROCHOT# Power/Other Output B26 VCC Power/Other Input B27 VCCSENSE Power/Other Reserved B28 VSS Power/Other A26 Reserved Reserved A27 VSS Power/Other B29 VCC Power/Other A28 VCC Power/Other B30 VSS Power/Other A29 VSS Power/Other B31 VCC Power/Other VSS Power/Other A30 VCC Power/Other C1 A31 VSS Power/Other C2 VCC Power/Other B1 Reserved Reserved C3 VID3 Power/Other Reserved Output Output Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type C4 VCC Power/Other C5 Reserved Reserved C6 RSP# Common Clk C7 VSS Power/Other C8 A35# Source Sync C9 A34# Source Sync C10 VCC Power/Other Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction D12 A29# Source Sync Input/Output Reserved D13 A25# Source Sync Input/Output Input D14 VCC Power/Other D15 A18# Source Sync Input/Output Input/Output D16 A17# Source Sync Input/Output Input/Output D17 A9# Source Sync Input/Output D18 VCC Power/Other D19 ADS# Common Clk Input/Output D20 BR0# Common Clk Input/Output Direction C11 A30# Source Sync Input/Output C12 A23# Source Sync Input/Output C13 VSS Power/Other C14 A16# Source Sync Input/Output D21 VSS Power/Other C15 A15# Source Sync Input/Output D22 RS1# Common Clk Input C16 VCC Power/Other D23 BPRI# Common Clk Input C17 A8# Source Sync Input/Output D24 VCC Power/Other C18 A6# Source Sync Input/Output D25 Reserved Reserved Reserved C19 VSS Power/Other D26 VSSSENSE Power/Other Output C20 REQ3# Common Clk Input/Output D27 VSS Power/Other C21 REQ2# Common Clk Input/Output D28 VSS Power/Other C22 VCC Power/Other D29 VCC Power/Other C23 DEFER# Common Clk Input D30 VSS Power/Other C24 TDI TAP Input D31 VCC Power/Other C25 VSS Power/Other Input E1 VSS Power/Other C26 IGNNE# Async GTL+ Input E2 VCC Power/Other C27 SMI# Async GTL+ Input E3 VID1 Power/Other Output C28 VCC Power/Other E4 BPM5# Common Clk Input/Output C29 VSS Power/Other E5 IERR# Common Clk Output C30 VCC Power/Other E6 VCC Power/Other C31 VSS Power/Other E7 BPM2# Common Clk Input/Output D1 VCC Power/Other E8 BPM4# Common Clk Input/Output D2 VSS Power/Other E9 VSS Power/Other D3 VID2 Power/Other Output E10 AP0# D4 STPCLK# Async GTL+ Input D5 VSS Power/Other E12 VCC Power/Other D6 INIT# Async GTL+ Input E13 A28# Source Sync Input/Output D7 MCERR# Common Clk Input/Output E14 A24# Source Sync Input/Output D8 VCC Power/Other E15 VSS Power/Other D9 AP1# Common Clk Input/Output E16 COMP1 Power/Other D10 BR3# 1 Common Clk Input E17 VSS Power/Other D11 VSS Power/Other E18 DRDY# Common Clk Datasheet E11 BR2# 1 Common Clk Input/Output Common Clk Input Input Input/Output 51 Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 39. Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction Pin No. Pin Name Signal Buffer Type Direction E19 TRDY# Common Clk Input F27 A20M# Async GTL+ Input E20 VCC Power/Other F28 VSS Power/Other E21 RS0# Common Clk Input F29 VCC Power/Other E22 HIT# Common Clk Input/Output F30 VSS Power/Other E23 VSS Power/Other F31 VCC Power/Other E24 TCK TAP Input G1 VSS Power/Other E25 TDO TAP Output G2 VCC Power/Other E26 VCC Power/Other G3 VSS Power/Other E27 FERR# Async GTL+ G4 VCC Power/Other E28 VCC Power/Other G5 VSS Power/Other E29 VSS Power/Other G6 VCC Power/Other E30 VCC Power/Other G7 VSS Power/Other E31 VSS Power/Other G8 VCC Power/Other F1 VCC Power/Other G9 VSS Power/Other F2 VSS Power/Other G23 LINT1 Async GTL+ F3 VID0 Power/Other G24 VCC Power/Other F4 VCC Power/Other G25 VSS Power/Other 52 Output Output F5 BPM3# Common Clk Input/Output G26 VCC Power/Other F6 BPM0# Common Clk Input/Output G27 VSS Power/Other F7 VSS Power/Other G28 VCC Power/Other F8 BPM1# Common Clk Input/Output G29 VSS Power/Other F9 GTLREF Power/Other Input G30 VCC Power/Other F10 VCC Power/Other G31 VSS Power/Other F11 BINIT# Common Clk Input/Output H1 VCC Power/Other F12 BR1# Common Clk Input H2 VSS Power/Other F13 VSS Power/Other H3 VCC Power/Other F14 ADSTB1# Source Sync Input/Output H4 VSS Power/Other F15 A19# Source Sync Input/Output H5 VCC Power/Other F16 VCC Power/Other H6 VSS Power/Other F17 ADSTB0# Source Sync Input/Output H7 VCC Power/Other F18 DBSY# Common Clk Input/Output H8 VSS Power/Other F19 VSS Power/Other H9 VCC Power/Other F20 BNR# Common Clk Input/Output H23 VCC Power/Other Input H24 VSS Power/Other H25 VCC Power/Other Power/Other F21 RS2# Common Clk F22 VCC Power/Other F23 GTLREF Power/Other Input H26 VSS F24 TRST# TAP Input H27 VCC Power/Other F25 VSS Power/Other H28 VSS Power/Other F26 THERMTRIP # Async GTL+ H29 VCC Power/Other Output Input Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type H30 VSS H31 J1 J2 Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Power/Other L2 VCC Power/Other VCC Power/Other L3 VSS Power/Other VSS Power/Other L4 VCC Power/Other VCC Power/Other L5 VSS Power/Other J3 VSS Power/Other L6 VCC Power/Other J4 VCC Power/Other L7 VSS Power/Other J5 VSS Power/Other L8 VCC Power/Other J6 VCC Power/Other L9 VSS Power/Other J7 VSS Power/Other L23 VSS Power/Other J8 VCC Power/Other L24 VCC Power/Other J9 VSS Power/Other L25 VSS Power/Other Direction J23 VSS Power/Other L26 VCC Power/Other J24 VCC Power/Other L27 VSS Power/Other J25 VSS Power/Other L28 VCC Power/Other J26 VCC Power/Other L29 VSS Power/Other J27 VSS Power/Other L30 VCC Power/Other J28 VCC Power/Other L31 VSS Power/Other J29 VSS Power/Other M1 VCC Power/Other J30 VCC Power/Other M2 VSS Power/Other J31 VSS Power/Other M3 VCC Power/Other K1 VCC Power/Other M4 VSS Power/Other K2 VSS Power/Other M5 VCC Power/Other K3 VCC Power/Other M6 VSS Power/Other K4 VSS Power/Other M7 VCC Power/Other K5 VCC Power/Other M8 VSS Power/Other K6 VSS Power/Other M9 VCC Power/Other K7 VCC Power/Other M23 VCC Power/Other K8 VSS Power/Other M24 VSS Power/Other K9 VCC Power/Other M25 VCC Power/Other K23 VCC Power/Other M26 VSS Power/Other K24 VSS Power/Other M27 VCC Power/Other K25 VCC Power/Other M28 VSS Power/Other K26 VSS Power/Other M29 VCC Power/Other K27 VCC Power/Other M30 VSS Power/Other K28 VSS Power/Other M31 VCC Power/Other K29 VCC Power/Other N1 VCC Power/Other K30 VSS Power/Other N2 VSS Power/Other K31 VCC Power/Other N3 VCC Power/Other L1 VSS Power/Other N4 VSS Power/Other Datasheet Direction 53 Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type N5 VCC Power/Other N6 VSS N7 VCC N8 VSS 54 Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type R8 VSS Power/Other Power/Other R9 VCC Power/Other Power/Other R23 VCC Power/Other Power/Other R24 VSS Power/Other Direction N9 VCC Power/Other R25 VCC Power/Other N23 VCC Power/Other R26 VSS Power/Other N24 VSS Power/Other R27 VCC Power/Other N25 VCC Power/Other R28 VSS Power/Other N26 VSS Power/Other R29 VCC Power/Other N27 VCC Power/Other R30 VSS Power/Other N28 VSS Power/Other R31 VCC Power/Other N29 VCC Power/Other T1 VSS Power/Other N30 VSS Power/Other T2 VCC Power/Other N31 VCC Power/Other T3 VSS Power/Other P1 VSS Power/Other T4 VCC Power/Other P2 VCC Power/Other T5 VSS Power/Other P3 VSS Power/Other T6 VCC Power/Other P4 VCC Power/Other T7 VSS Power/Other P5 VSS Power/Other T8 VCC Power/Other P6 VCC Power/Other T9 VSS Power/Other P7 VSS Power/Other T23 VSS Power/Other P8 VCC Power/Other T24 VCC Power/Other P9 VSS Power/Other T25 VSS Power/Other P23 VSS Power/Other T26 VCC Power/Other P24 VCC Power/Other T27 VSS Power/Other P25 VSS Power/Other T28 VCC Power/Other P26 VCC Power/Other T29 VSS Power/Other P27 VSS Power/Other T30 VCC Power/Other P28 VCC Power/Other T31 VSS Power/Other P29 VSS Power/Other U1 VCC Power/Other P30 VCC Power/Other U2 VSS Power/Other P31 VSS Power/Other U3 VCC Power/Other R1 VCC Power/Other U4 VSS Power/Other R2 VSS Power/Other U5 VCC Power/Other R3 VCC Power/Other U6 VSS Power/Other R4 VSS Power/Other U7 VCC Power/Other R5 VCC Power/Other U8 VSS Power/Other R6 VSS Power/Other U9 VCC Power/Other R7 VCC Power/Other U23 VCC Power/Other Direction Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type U24 VSS U25 U26 U27 Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Power/Other W27 VCC Power/Other VCC Power/Other W28 VSS Power/Other VSS Power/Other W29 VCC Power/Other VCC Power/Other W30 VSS Power/Other Direction Direction U28 VSS Power/Other W31 VCC Power/Other U29 VCC Power/Other Y1 VSS Power/Other U30 VSS Power/Other Y2 VCC Power/Other U31 VCC Power/Other Y3 Reserved Reserved Reserved V1 VSS Power/Other Y4 BCLK0 Sys Bus Clk Input V2 VCC Power/Other Y5 VSS Power/Other V3 VSS Power/Other Y6 TESTHI3 Power/Other V4 VCC Power/Other Y7 VSS Power/Other V5 VSS Power/Other Y8 RESET# Common Clk Input V6 VCC Power/Other Y9 D62# Source Sync Input/Output V7 VSS Power/Other Y10 VCC Power/Other V8 VCC Power/Other Y11 DSTBP3# Source Sync Input/Output V9 VSS Power/Other Y12 DSTBN3# Source Sync Input/Output V23 VSS Power/Other Y13 VSS Power/Other V24 VCC Power/Other Y14 DSTBP2# Source Sync Input/Output V25 VSS Power/Other Y15 DSTBN2# Source Sync Input/Output V26 VCC Power/Other Y16 VCC Power/Other V27 VSS Power/Other Y17 DSTBP1# Source Sync Input/Output V28 VCC Power/Other Y18 DSTBN1# Source Sync Input/Output V29 VSS Power/Other Y19 VSS Power/Other V30 VCC Power/Other Y20 DSTBP0# Source Sync Input/Output V31 VSS Power/Other Y21 DSTBN0# Source Sync Input/Output W1 VCC Power/Other Y22 VCC Power/Other W2 VSS Power/Other Y23 D5# Source Sync Input/Output W3 Reserved Reserved Y24 D2# Source Sync Input/Output W4 VSS Power/Other Y25 VSS Power/Other Reserved Input W5 BCLK1 Sys Bus Clk Input Y26 D0# Source Sync Input/Output W6 TESTHI0 Power/Other Input Y27 THERMDA Anode Pin Output W7 TESTHI1 Power/Other Input Y28 THERMDC Cathode Pin Output W8 TESTHI2 Power/Other Input Y29 NC Reserved W9 GTLREF Power/Other Input Y30 VCC Power/Other W23 GTLREF Power/Other Input Y31 VSS Power/Other W24 VSS Power/Other AA1 VCC Power/Other W25 VCC Power/Other AA2 VSS Power/Other W26 VSS Power/Other AA3 BSEL0 Power/Other Datasheet Output2 55 Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type AA4 VCC Power/Other AA5 VSSA Power/Other AA6 VCC Power/Other AA7 TESTHI4 Power/Other AA8 D61# Source Sync AA9 VSS Power/Other AA10 D54# Source Sync 56 Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction AB12 D51# Source Sync Input/Output AB13 D52# Source Sync Input/Output AB14 VCC Power/Other Input AB15 D37# Source Sync Input/Output Input/Output AB16 D32# Source Sync Input/Output AB17 D31# Source Sync Input/Output Input/Output AB18 VCC Power/Other Input/Output AB19 D14# Source Sync Input/Output AB20 D12# Source Sync Input/Output Direction Input AA11 D53# Source Sync AA12 VCC Power/Other AA13 D48# Source Sync Input/Output AB21 VSS Power/Other AA14 D49# Source Sync Input/Output AB22 D13# Source Sync Input/Output AB23 D9# Source Sync Input/Output AB24 VCC Power/Other AB25 D8# Source Sync Input/Output Input/Output AA15 VSS Power/Other AA16 D33# Source Sync AA17 VSS Power/Other AA18 D24# Source Sync Input/Output AB26 D7# Source Sync AA19 D15# Source Sync Input/Output AB27 VSS Power/Other AA20 VCC Power/Other AB28 NC Reserved Input/Output AA21 D11# Source Sync Input/Output AB29 NC Reserved AA22 D10# Source Sync Input/Output AB30 VCC Power/Other AA23 VSS Power/Other AB31 VSS Power/Other AA24 D6# Source Sync Input/Output AC1 Reserved Reserved AA25 D3# Source Sync Input/Output AC2 VSS Power/Other AA26 VCC Power/Other AC3 VCC Power/Other AA27 D1# Source Sync AC4 VCC Power/Other AA28 NC Reserved AC5 D60# Source Sync Input/Output AA29 NC Reserved AC6 D59# Source Sync Input/Output AA30 VSS Power/Other AC7 VSS Power/Other AA31 VCC Power/Other AC8 D56# Source Sync Input/Output AB1 VSS Power/Other AC9 D47# Source Sync Input/Output AB2 VCC Power/Other AC10 VCC Power/Other Input/Output AB3 BSEL1 Power/Other Output AB4 VCCA Power/Other Input AB5 VSS Power/Other AB6 D63# Source Sync AB7 PWRGOOD Power/Other AB8 VCC Power/Other 2 Input Reserved AC11 D43# Source Sync Input/Output AC12 D41# Source Sync Input/Output AC13 VSS Power/Other AC14 D50# Source Sync Input/Output AC15 DP2# Common Clk Input/Output AC16 VCC Power/Other AB9 DBI3# Source Sync Input/Output AC17 D34# Source Sync Input/Output AB10 D55# Source Sync Input/Output AC18 DP0# Common Clk Input/Output AB11 VSS Power/Other AC19 VSS Power/Other Datasheet Intel(R) XeonTM Processor with 533MHz Front Side Bus Table 39. Pin Listing by Pin Number Table 39. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction Pin No. Pin Name Signal Buffer Type Direction AC20 D25# Source Sync Input/Output AD27 D4# Source Sync Input/Output AC21 D26# Source Sync Input/Output AD28 NC Reserved AC22 VCC Power/Other AD29 NC Reserved AC23 D23# Source Sync Input/Output AD30 VCC Power/Other AC24 D20# Source Sync Input/Output AD31 VSS Power/Other AC25 VSS Power/Other AE2 VSS Power/Other AC26 D17# Source Sync Input/Output AE3 VCC Power/Other AC27 DBI0# Source Sync Input/Output AE4 SMD_PRT Ground Output AC28 NC Reserved AE5 TESTHI6 Power/Other Input AC29 NC Reserved AE6 SLP# Async GTL+ Input AC30 VSS Power/Other AE7 D58# Source Sync Input/Output AC31 VCC Power/Other AD1 Reserved Reserved AD2 VCC Power/Other AD3 VSS Power/Other AE11 VSS Power/Other AD4 VCCIOPLL Power/Other Input AE12 DBI2# Source Sync Input/Output AD5 TESTHI5 Power/Other Input AE13 D35# Source Sync Input/Output Reserved AE8 VCC Power/Other AE9 D44# Source Sync Input/Output AE10 D42# Source Sync Input/Output AD6 VCC Power/Other AE14 VCC Power/Other AD7 D57# Source Sync Input/Output AE15 Reserved Reserved Reserved AD8 D46# Source Sync Input/Output AE16 Reserved Reserved Reserved Input/Output AD9 VSS Power/Other AE17 DP3# Common Clk AD10 D45# Source Sync Input/Output AE18 VCC Power/Other AD11 D40# Source Sync Input/Output AE19 DP1# Common Clk Input/Output Input/Output AD12 VCC Power/Other AE20 D28# Source Sync AD13 D38# Source Sync Input/Output AE21 VSS Power/Other AD14 D39# Source Sync Input/Output AE22 D27# Source Sync Input/Output AD15 VSS Power/Other AE23 D22# Source Sync Input/Output AD16 COMP0 Power/Other AD17 VSS Power/Other AD18 D36# Source Sync AD19 D30# Source Sync AD20 VCC Power/Other AD21 D29# Source Sync Input/Output AD22 DBI1# Source Sync Input/Output AD23 VSS Power/Other AD24 D21# Source Sync Input/Output AD25 D18# Source Sync Input/Output AD26 VCC Power/Other Datasheet AE24 VCC Power/Other AE25 D19# Source Sync Input/Output Input/Output AE26 D16# Source Sync Input/Output Input/Output AE27 VSS Power/Other AE28 VID_VCC Power/Other AE29 VID_VCC Power/Other AE30 Mechanical Key Input 1. In systems utilizing the Intel Xeon processor, the system designer must pull-up these signals to the processor VCC. 2. Baseboards treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 133 MHz. 57 This page intentionally left blank. 58 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz This page intentionally left blank. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 59 4.2 Signal Definitions Table 41. Signal Definitions (Sheet 1 of 9) Name Type Description Notes 36 A[35:3]# I/O A[35:3]# (Address) define a 2 byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In subphase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the front side bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. 4 On the active-to-inactive transition of RESET#, the processors sample a subset of the A[35:3]# pins to determine their power-on configuration. See Section 6.1. A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1 MByte boundary. Assertion of A20M# is only supported in real mode. 3 A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on all front side bus agents. ADSTB[1:0]# I/O Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edge. 4 4 AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all front side bus agents. The following table defines the coverage model of these signals. AP[1:0]# BCLK[1:0] I/O I Request Signals Subphase 1 Subphase 2 A[35:24]# AP0# AP1# A[23:3]# AP1# AP0# REQ[4:0]# AP1# AP0# The differential pair BCLK (Bus Clock) determines the bus frequency. All processor front side bus agents must receive these signals to drive their outputs and latch their inputs. 4 4 All external timing parameters are specified with respect to the rising edge of BCLK0 crossing the falling edge of BCLK1. 60 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Table 41. Signal Definitions (Sheet 2 of 9) Name Type Description Notes BINIT# (Bus Initialization) may be observed and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information. BINIT# I/O If BINIT# observation is enabled during power-on configuration (see Section 6.1) and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ 4 and transaction tracking state machines upon observation of BINIT# assertion. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the front side bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BNR# I/O Since multiple agents might need to request a bus stall at the same time, BNR# is a wire-OR signal which must connect the appropriate pins of all processor front side bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled on specific clock edges. 4 BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all front side bus agents. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM[5:0]# I/O BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processors. 3 BPM[5:4]# must be bussed to all bus agents. These signals do not have on-die termination and must be terminated at the end agent. See the appropriate platform design guidelines for additional information. BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor front side bus. It must connect the appropriate pins of all processor front side bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 4 61 Table 41. Signal Definitions (Sheet 3 of 9) Name Type Description Notes BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. BR2# and BR3# must not be utilized in a dual processor platform design. The table below gives the rotating interconnect between the processor and bus signals for dual processor systems. BR[1:0]# Signals Rotating Interconnect, dual processor system BR0# BR[1:3]#1 I/O I Bus Signal Agent 0 Pins Agent 1 Pins BREQ0# BR0# BR1# BREQ1# BR1# BR0# During power-up configuration, the central agent must assert the BR0# bus signal. All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent ID. All agents then configure their pins to match the appropriate bus signal protocol as shown below. 1,4 BR[1:0]# Signal Agent IDs BR[1:0]# Signals Rotating Interconnect, dual processor system Agent ID BR0# 0 BR1# 1 During power-on configuration, the central agent must assert the BR0# bus signal. All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition of RESET#. The pin which the agent samples asserted determines it's agent ID. These signals do not have on-die termination and must be terminated at the end agent. See the appropriate platform design guidelines for additional information. These output signals are used to select the front side bus frequency. A BSEL[1:0] = "00" will select a 100 MHz bus clock frequency. The frequency is determined by the processor(s), chipset, and frequency synthesizer capabilities. All front side bus agents must operate at the same frequency. Individual processors will only operate at their specified front side bus (FSB) frequency. BSEL[1:0] O On baseboards which support operation only at 100 MHz bus clocks these signals can be ignored. On baseboards employing the use of these signals, a 1 K pull-up resistor be used. See Table 2 "Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]" on page 13 for output values. COMP[1:0] 62 I COMP[1:0] must be terminated to VSS on the baseboard using precision resistors. These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate platform design guidelines and Table 12 for implementation details. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Table 41. Signal Definitions (Sheet 4 of 9) Name Type Description Notes D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor front side bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to strobes and DBI#. D[63:0]# I/O Data Group DSTBN/ DSTBP DBI# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 4 Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within a 16-bit group, change logic level in the next cycle. DBI[3:0] Assignment To Data Bus DBI[3:0]# I/O Bus Signal Data Bus Signals DBI0# D[15:0]# DBI1# D[31:16]# DBI2# D[47:32]# DBI3# D[63:48]# 4 I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor front side bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor front side bus agents. 4 DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the appropriate pins of all processor front side bus agents. 4 DP[3:0]# I/O DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the 4 appropriate pins of all processor front side bus agents. DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor front side bus agents. 4 DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#. 4 DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. 4 DBSY# Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 63 Table 41. Signal Definitions (Sheet 5 of 9) Name FERR#/PBE# Type O Description FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/ PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/ PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Notes 3 This signal does not have on-die termination and must be terminated at the end agent. See the appropriate Platform Design Guideline for additional information. GTLREF I HIT# I/O HITM# I/O IERR# O GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3Vcc. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any front side bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. Since multiple agents may deliver snoop results at the same time, HIT# and HITM# are wire-OR signals which must connect the appropriate pins of all processor front side bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, HIT# and HITM# are activated on specific clock edges and sampled on specific clock edges. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor front side bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. 4 3 This signal does not have on-die termination and must be terminated at the end agent. See the appropriate Platform Design Guideline for additional information. IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. 3 IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O write bus transaction. INIT# I INIT# (Initialization), when asserted, resets integer registers inside all processors without affecting their internal caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor front side bus agents. 3 If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). 64 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Table 41. Signal Definitions (Sheet 6 of 9) Name LINT[1:0] Type Description I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side bus agents. When the APIC functionality is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Notes 3 Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# Mechanical Key I/O Inert LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor front side bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor front side bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock. 4 Mechanical Key to prevent compatibility with 603-pin socket. MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor front side bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: * Enabled or disabled. * Asserted, if configured, for internal errors along with IERR#. MCERR# I/O * Asserted, if configured, by the request initiator of a bus transaction after it observes an error. * Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the IA-32 Software Developer's Manual, Volume 3: System Programming Guide. Since multiple agents may drive this signal at the same time, MCERR# is a wire-OR signal which must connect the appropriate pins of all processor front side bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, MCERR# is activated on specific clock edges and sampled on specific clock edges. ODTEN PROCHOT# I O ODTEN (On-die termination enable) should be connected to VCC to enable on-die termination for end bus agents. For middle bus agents, pull this signal down via a resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die termination will be active, regardless of other states of the bus. PROCHOT# (processor hot) indicates that the processor Thermal Control Circuit (TCC) has been activated. Under most conditions, PROCHOT# will go active when the processor's thermal sensor detects that the processor has reached its maximum safe operating temperature. See Section 6.3 for more details. These signals do not have on-die termination and must be terminated at the end agent. See the appropriate Platform Design Guideline for additional information. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 65 Table 41. Signal Definitions (Sheet 7 of 9) Name PWRGOOD Type I Description PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. "Clean" implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. Figure 6 illustrates the relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 13, and be followed by a 1 mS RESET# pulse. Notes 3 The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor front side bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking of these signals. 4 Asserting the RESET# signal resets all processors to known states and invalidates their internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all front side bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10ms. RESET# I A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1. 4 This signal does not have on-die termination and must be terminated at the end agent. See the appropriate Platform Design Guideline for additional information. RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor front side bus agents. RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor front side bus agents. RSP# I SKTOCC# O SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that the processor is present. SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. SMB_PRT I Pin is grounded on processor packages that do not contain SMBUS components (PIROM, Scratch EEPROM, and thermal sensor). It is floating on processor packages that contain the SMBus components. 66 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. 4 4 3 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Table 41. Signal Definitions (Sheet 8 of 9) Name Type Description Notes SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state SMI# I and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. 3 If SMI# is asserted during the deassertion of RESET# the processor will tri-state its outputs. STPCLK# I STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the front side bus and APIC units. The processor continues to snoop bus transactions and 3 service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. I All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which matches the trace impedance within a range of 10 ohms. TESTHI[3:0] and TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if desired. However, utilization of boundary scan test will not be functional if these pins are connected together. TESTHI4 must always be pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for TESTHI[6:0] pins should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 , then a value between 40 and 60 should be used. The TESTHI[6:0] termination recommendations provided in the Intel(R) XeonTM processor datasheet are still suitable for the Intel(R) XeonTM processor with 533 MHz Front Side Bus. However, Intel recommends new designs or designs undergoing design updates follow the trace impedance matching termination guidelines given in this section. TESTHI[6:0] THERMTRIP# O Activation of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135 C. To properly protect the processor, power must be removed upon THERMTRIP# becoming active. See Figure 6 for the appropriate power down sequence and timing requirement. In parallel, the processor will attempt to reduce its temperature by shutting off internal clocks and stopping all program execution. Once activated, THERMTRIP# remains latched and the processor will be stopped until RESET# is asserted. A RESET# pulse will reset the processor and execution will begin at the boot vector. If the temperature has not dropped below the trip level, the processor will assert THERMTRIP# and return to the shutdown state. The processor releases THERMTRIP# when RESET# is activated even if the processor is still too hot. 2 This signal do not have on-die termination and must be terminated at the end agent. See the appropriate platform design guidelines for additional information. THERMDA O Thermal Diode Anode. THERMDC O Thermal Diode Cathode. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 67 Table 41. Signal Definitions (Sheet 9 of 9) Name Type Description Notes TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TMS I TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all front side bus agents. TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. See the appropriate Platform Design Guideline for additional information. VCCA I VCCA provides isolated power for the analog portion of the internal PLL's. Use a discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to provide clean power to the PLL. The tolerance and total ESR for the filter is important. Refer to the appropriate platform design guidelines for complete implementation details. VCCIOPLL I VCCIOPLL provides isolated power for digital portion of the internal PLL's. Follow the guidelines for VCCA (Section 2.5), and refer to the appropriate platform design guidelines for complete implementation details. O The Vccsense and Vsssense pins are the points for which processor minimum and maximum voltage requirements are specified. Uniprocessor designs may utilize these pins for voltage sensing for the processor's voltage regulator. However, multiprocessor designs must not connect these pins to sense logic, but rather utilize them for power delivery validation. VID[4:0] O VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages (VCC). Unlike previous processor generations, these pins are driven by processor logic. Hence the voltage supply for these pins (SM_VCC) must be valid before the VRM supplying Vcc to the processor is enabled. Conversely, the VRM output must be disabled prior to the voltage supply for these pins becomes invalid. The VID pins are needed to support processor voltage specification variations. See Table 3 for definitions of these pins. The power supply must supply the voltage that is requested by these pins, or disable itself. VID_VCC . I Voltage for VID and BSEL logic VSSA I VSSA provides an isolated, internal ground for internal PLL's. Do not connect directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a discrete filter circuit. VCCSENSE VSSSENSE This signal does not have on-die termination and must be terminated at the end agent.See the appropriate platform design guidelines for additional information. NOTES: 1. Intel Xeon processors only support BR0# and BR1#. However, the Intel Xeon processors must terminate BR2# and BR3# to the processor VCC. 2. For this pin on Intel(R) XeonTM processors, the maximum number of symmetric agents is one. Maximum number of Central Agents is zero. 3. For this pin on Intel(R) XeonTM processors, the maximum number of symmetric agents is two. Maximum number of Central Agents is zero. 4. For this pin on Intel(R) XeonTM processors, the maximum number of symmetric agents is two. Maximum number of Central Agents is one. 68 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 5.0 Thermal Specifications This chapter provides the thermal specifications necessary for designing a thermal solution for the Intel(R) XeonTM Processor with 533 MHz Front Side Bus. Thermal solutions should include heatsinks that attach to the integrated heat spreader (IHS). The IHS provides a common interface intended to be compatible with many heatsink designs. Thermal specifications are based on the temperature of the IHS top, referred to as the case temperature, or TCASE. Thermal solutions should be designed to maintain the processor within TCASE specifications. For information on performing TCASE measurements, refer to the Intel(R) XeonTM Processor Thermal Design Guidelines. See Figure 18 for an exploded view of the processor package and thermal solution assembly. Note: The processor is either shipped alone or with a heatsink (boxed processor only). All other components shown in Figure 18 must be purchased separately. Figure 18. Processor with Thermal and Mechanical Components - Exploded View 60 4 P in Note: This is a graphical representation. For specifications, see each component's respective documentation listed in Section 1.3. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 69 5.1 Thermal Specifications Table 42 specifies the thermal design power dissipation envelope for the Intel(R) XeonTM processor with 533 MHz Front Side Bus. The processor power listed in Table 42 is described in thermal design power. Analysis indicates that real applications are unlikely to cause the processor to consume the maximum possible power consumption. Intel recommends that system thermal designs utilize the Thermal Design Power indicated in Table 42. Thermal Design Power recommendations are chosen through characterization of server and workstation applications on the processor. The Thermal Monitor feature is intended to protect the processor from overheating on any high power code that exceeds the recommendations in this table. For more details on the Thermal Monitor feature, refer to Section 6.3. In all cases, the Thermal Monitor feature must be enabled for the processor to be operating within specification. Table 42 also lists the minimum and maximum processor TCASE temperature specifications. A thermal solution should be designed to ensure the temperature of the processor never exceeds these specifications. Table 42. Processor Thermal Design Power Core Frequency Thermal Design Power1 (W) Maximum Power (W) Minimum TCASE (C) Maximum TCASE (C) Notes 2 GHz 58 66 5 70 2,3 2.40 GHz 65 75 5 74 2,3 2.66 GHz 72 83 5 74 2,3 2.80 GHz 74 86 5 75 2,3 3.06 GHz 85 101 5 73 2,3 NOTE: 1. Intel recommends that thermal solutions be designed utilizing the Thermal Design Power values. Refer to the Intel(R) XeonTM Processor Thermal Design Guidelines. 2. TDP values are specified at the point on Vcc_max loadline corresponding to Icc_TDP. 3. Systems must be designed to ensure that the processor is not subjected to any static Vcc and Icc combination wherein Vcc exceeds Vcc_max at specified Icc. Please refer to the loadline specifications in Chapter 2.0. Figure 19. Processor Thermal Design Power vs Electrical Projections for VID = 1.500V 70 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 20. Processor Thermal Design Power vs Electrical Projections for VID = 1.525V Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 71 5.2 Measurements for Thermal Specifications 5.2.1 Processor Case Temperature Measurement The minimum and maximum case temperatures (TCASE) for processors are specified in Table 42 of the previous section. These temperature specifications are meant to ensure correct and reliable operation of the processor. Figure 21 illustrates the thermal measurement point for TCASE. This point is at the geometric center of the integrated heat spreader (IHS). Figure 21. Thermal Measurement Point for Processor TCASE Note: Figure is not to scale, and is for reference only 72 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 6.0 Features 6.1 Power-On Configuration Options The Intel(R) XeonTM Processor with 533 MHz Front Side Bus has several configuration options that are determined by the state of specific processor pins at the active-to-inactive transition of the processor RESET# signal. These configuration options cannot be changed except by another reset. Both power on and software induced resets reconfigure the processor(s). Table 43. Power-On Configuration Option Pins Configuration Option Pin1 Output tri state SMI# Execute BIST (Built-In Self Test) INIT# In Order Queue de-pipelining (set IOQ depth to 1) A7# Disable MCERR# observation A9# Disable BINIT# observation A10# APIC cluster ID (0-3) A[12:11]# Disable bus parking A15# Disable Hyper-Threading Technology Symmetric agent arbitration ID Notes 2 A31# BR[3:0]# 3 NOTES: 1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option. 2. The Intel(R) XeonTM processor with 533 MHz Front Side Bus does not support this feature, therefore platforms utilizing this processor should not use these configuration pins. 3. Intel Xeon processor with 533 MHz Front Side Bus utilize only BR0# and BR1# signals. 2-way platforms must not utilize BR2# and BR3# signals. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 22 for a visual representation of the processor low power states. Due to the inability of processors to recognize bus transactions during the Sleep state, multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the other processor in the Normal or Stop-Grant state. 6.2.1 Normal State--State 1 This is the normal operating state for the processor. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 73 6.2.2 AutoHALT Powerdown State--State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# will cause the processor to immediately initialize itself. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. Figure 22. Stop Clock State Machine HALT Instruction and HALT Bus Cycle Generated 2. Auto HALT Power Down State BCLK running Snoops and interrupts allowed INIT#, BINIT#, INTR, NMI, RESET# ST PC LK #A ss ert ed Snoop Event Occurs Snoop Event Serviced 4. HALT/Grant Snoop State BCLK running Service snoops to caches 1. Normal State Normal execution STPCLK# Asserted . STPCLK# De-asserted ST PC LK #D e-a ss ert ed Snoop Event Occurs Snoop Event Serviced 3. Stop Grant State BCLK running Snoops and interrupts allowed SLP# Asserted SLP# De-asserted 5. Sleep State BCLK running No snoops or interrupts allowed 6.2.3 Stop-Grant State--State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop Grant state. Both logical processors of the Intel(R) XeonTM processor with 533 MHz Front Side Bus must be in the Stop Grant state before the deassertion of STPCLK#. 74 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the front side bus should be driven to the inactive state. BINIT# will be recognized while the processor is in Stop-Grant state. If STPCLK# is still asserted at the completion of the BINIT# bus initialization, the processor will remain in Stop-Grant mode. If the STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor will return to Normal state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should only be deasserted one or more bus clocks after the deassertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the front side bus (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with the assertion of the SLP# signal. While in the Stop-Grant state, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. 6.2.4 HALT/Grant Snoop State--State 4 The processor will respond to snoop transactions on the front side bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the front side bus has been serviced (whether by the processor or another agent on the front side bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate. 6.2.5 Sleep State--State 5 The Sleep state is a very low power state in which each processor maintains its context, maintains the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT states. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the front side bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 75 Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous front side bus event occurs. The SLP# pin should only be asserted when the processor (and all logical processors within the physical processor) is in the Stop-Grant state. SLP# assertions while the processors are not in the Stop-Grant state is out of specification and may result in illegal operation. 6.2.6 Bus Response During Low Power States While in AutoHALT Power Down and Stop-Grant states, the processor will process a front side bus snoop. When the processor is in Sleep state, the processor will not process interrupts or snoop transactions. 6.3 Thermal Monitor Thermal Monitor is a feature of the processor that allows system designers to lower the cost of thermal solutions, without compromising system integrity or reliability. By using a factory-tuned, precision on-die temperature sensor, and a fast acting thermal control circuit (TCC), the processor, without the aid of any additional software or hardware, can control the processors' die temperature within factory specifications under typical real-world operating conditions. Thermal Monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications, instead of being designed to the much higher maximum processor power envelopes. Thermal Monitor controls the processor temperature by modulating (starting and stopping) the internal processor core clocks. The processor clocks are modulated when the thermal control circuit (TCC) is activated. Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode. Automatic mode must be enabled via BIOS, which is required for the processor to operate within specifications. Once automatic mode is enabled, the TCC will activate only when the internal die temperature is very near the temperature limits of the processor. When the TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks will be modulated by maintaining a duty cycle within a range of 30% - 50%. Clocks will not be off or on more than 3.0 ms when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. Once the temperature has returned to a non-critical level, and the hysteresis timer has expired, modulation ceases and the TCC goes inactive. Processor performance will be decreased by ~50% when the TCC is active (assuming a duty cycle that varies from 30%-50%), however, with a properly designed and characterized thermal solution the TCC most likely will only be activated briefly during the most power intensive applications while at maximum chassis ambient temperature. For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers or interrupt handling routines. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor Control Register is written to a "1" the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed anywhere within a range of 30% to 50%; however in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used at the same time 76 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Automatic mode is enabled, however, if TCC is enabled via On-Demand mode at the same time automatic mode is enabled AND a high temperature condition exists, the fixed duty cycle of the automatic mode will override the duty cycle selected by the On-Demand mode. An external signal, PROCHOT# (processor hot) is asserted at any time the TCC is active (either in Automatic or On-Demand mode). Bus snooping and interrupt latching are also active while the TCC is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible. In an MP system, Thermal Monitor must be configured identically for each processor within the system. Besides the thermal sensor and thermal control circuit, the Thermal Monitor feature also includes one ACPI register, one performance counter register, three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT# (i.e. upon the activation/deactivation of TCC). Refer to Volume 3 of the IA32 Intel Architecture Software Developer's for specific register and programming details. If automatic mode is disabled the processor will be operating out of specification and cannot be guaranteed to provide reliable results. Regardless of enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 C. At this point the front side bus signal THERMTRIP# will go active and stay active until the processor has cooled down and RESET# has been initiated. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within the timeframe defined in Figure 6. 6.3.1 Thermal Diode The processor incorporates an on-die thermal diode. A thermal sensor located on the baseboard may be used to monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 44 and Table 45 provide the diode parameter and interface specifications.This thermal diode is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. Table 44. Thermal Diode Parameters Symbol Parameter Min IFW Forward Bias Current 5 n Diode Ideality Factor 1.0011 RT Series Resistance Typ 1.0021 Max Unit Notes 300 uA 1 1.0030 3.64 2,3,4 W 2,3,5 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized at 75C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVD/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 77 board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT*(N-1)*IFWmin]/[(nk/ q)*ln N] Where Terror = sensor temperature error, N = sensor current ration, k = Boltzmann Constant, q = electronic charge. Table 45. Thermal Diode Interface 78 Pin Name Pin Number Pin Description THERMDA Y27 diode anode THERMDC Y28 diode cathode Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 7.0 Boxed Processor Specifications 7.1 Introduction The Intel(R) XeonTM Processor with 533 MHz Front Side Bus is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The boxed processor is supplied with an unattached passive heatsink. It will also contain an optional active duct solution, called Processor Wind Tunnel (PWT), to provide adequate airflow across the heatsink. If the chassis or baseboard used contains an alternate cooling solution that has been thermally validated, the PWT may be discarded. This chapter documents baseboard and platform requirements for the cooling solution that is supplied with the boxed processor. This chapter is particularly important for OEM's that manufacture baseboards and chassis for integrators. Figure 23 shows a mechanical representation of a boxed processor heatsink. Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designer's responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platform and chassis. Figure 23. Mechanical Representation of the Boxed Processor Passive Heatsink Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 79 7.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive heatsink and the PWT. Proper clearance is required around the heatsink to ensure proper installation of the processor and unimpeded airflow for proper cooling. 7.2.1 Boxed Processor Heatsink Dimensions The boxed processor is shipped with an unattached passive heatsink. Clearance is required around the heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled heatsink are shown in Figure 26 (Multiple Views). The airflow requirements for the boxed processor heatsink must also be taken into consideration when designing new baseboards and chassis. The airflow requirements are detailed in the Thermal Specifications, Section 7.4. 7.2.2 Boxed Processor Heatsink Weight The boxed processor heatsink weighs no more than 450 grams. See Chapter 3.0 and Chapter 5.0 of this document along with the Intel(R) XeonTM Processor Family Thermal Design Guidelines for details on the processor weight and heatsink requirements. 7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports The boxed processor requires processor retention solution to secure the processor, the baseboard, and the chassis. The retention solution contains one retention mechanisms and two retention clips per processor. The boxed processor ships with retention mechanism, cooling solution retention clips, and direct chassis attach screws.Baseboards and chassis designed for use by system integrators should include holes that are in proper alignment with each other to support the boxed processor. Refer to the Server System Infrastructure Specification (SSI-EEB) at http://www.ssiforum.org for details on the hole locations. Please refer to the "Boxed integration notes" at http://support.intel.com/support/processors/xeon for retention mechanism installation instructions. Retention mechanism clips must interface with the boxed processor heatsink area shown in Detail A in Figure 26. The retention mechanism that ships with the boxed processor is different than the reference solution from Intel. Please refer to Figure 24 below, which contains the dimensions for the reference solution. Please refer to Figure 25 for the retention mechanism that ships with the boxed processor. 80 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 24. Boxed Processor Retention Mechanism and Clip Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 81 Figure 25. Boxed Processor Retention Mechanism that Ships with the Processor 82 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 26. Multiple View Space Requirements for the Boxed Processor Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 83 7.3 Boxed Processor Requirements 7.3.1 Intel(R) XeonTM Processor with 533 MHz Front Side Bus 7.3.1.1 Processor Wind Tunnel The boxed processor ships with an active duct cooling solution called the Processor Wind Tunnel, or PWT. This is an optional cooling solution that is designed to meet the thermal requirements of a diverse combination of baseboards and chassis. It ships with the processor in order to reduce the burden on the chassis manufacturer to provide adequate airflow across the processor heatsink. Manufacturers may elect to use their own cooling solution. Note: Although Intel will be testing a select number of baseboard and chassis combinations for thermal compliance, this is in no way a comprehensive test. It is ultimately the system integrator's responsibility to test that their solution meets all of the requirements specified in this document. The PWT is meant to assist in processor cooling, but additional cooling techniques may be required in order to ensure that the entire system meets the thermal requirements. See Figure 28 and Figure 29 for the Processor Wind Tunnel dimensions. 7.3.1.2 Fan Power Supply The Processor Wind Tunnel includes a fan, which requires a constant +12V power supply. A fan power cable is shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinouts are shown in Figure 27 and the fan cable connector requirements are detailed in Table 46. Platforms must provide a matched power header to support the boxed processor. Table 47 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, an open-collector output, that pulses at a rate of two pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the baseboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the baseboard itself. The baseboard power header should be positioned within 7 inches from the centre of the processor socket. 84 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 27. Fan Connector Electrical Pin Sequence Table 46. Fan Cable Connector Requirements Item Specification Fan connector must be a straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. - Match with a straight pin, friction lock header on the mainboard. - Manufacturer and part number or equivalent: o AMP : Fan connector: 643815-3, header: 640456-3 o Walden / Molex : Fan connector: 22-01-3037, header: 22-23-2031 - Pin 1: Ground; black wire. - Pin 2: Power, +12 V; yellow wire. - Pin 3: Signal, Open collector tachometer output signal requirement: 2 pulses per revolution; green wire. The fan cable connector must reach a mating mainboard connector at any point within a radius of 110 mm (4.33") measured from the central datum planes of the enabled assembly (datum planes A, B & C on Drawing AXXXXX). Fan power cable must be routed in such a way to prevent it from contacting the fan impellor and it must be positioned in a consistent location from unit to unit. - Connector Type Pin Out (See Figure Above) Fan cable length (Drawing 747887): Fan cable routing Table 47. Fan Power and Signal Specifications Description Min Typ Max Unit +12V: 12 Vot Fan Power Supply 6.0 12.0 13.2 V 1.5 A IC: Fan Current Draw SENSE Frequency 2 Pulses per fan revolution Notes 1 1. Baseboard should pull this pin up to V CC with a resistor. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 85 Figure 28. Processor Wind Tunnel General Dimensions 86 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 29. Processor Wind Tunnel Detailed Dimensions Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 87 7.3.1.3 Fan The Processor Wind Tunnel includes a 25mm fan for use with processors <= 2.8 GHz, or a 38mm fan for use with processors running at 3 GHz and above. The 38mm fan provides the high performance required to meet the demanding thermal requirements of processors running at 3 GHz and above. The 38mm fan provides local fan speed control. There is a temperature diode on the fan that measures the inlet temperature to the fan and adjusts the speed accordingly. The benefit is that system manufacturers can pass acoustical requirements while still being able to pass thermal requirements at maximum ambient temperature. 7.3.2 1U Rack Mount Server Solution The 1U solution contains a passive heatsink and a foam pad, in addition to the retention solution included with the other options. Because of the small form factor, the 1U heatsink is not as efficient at dissipating heat as the general-purpose heatsink. In order to ensure maximum thermal efficiency, the foam pad must be attached to the top of the 1U heatsink, blocking airflow between the heatsink and the chassis cover. This will force air through the heatsink fins instead of allowing it to bypass over the top. See Figure 30 and Figure 31 for more detail on installation. Figure 30. Exploded View of the 1U Thermal Solution 88 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz Figure 31. Assembled View of the 1U Thermal Solution Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 89 7.4 Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor will be directly cooled with a passive heatsink. For the passive heatsink to effectively cool the boxed processor, it is critical that sufficient, unimpeded, cool air flow over the heatsink of every processor in the system. Meeting the processor's temperature specification is a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is found in Chapter 5.0. It is important that system integrators perform thermal tests to verify that the boxed processor is kept below its maximum temperature specification in a specific baseboard and chassis. At an absolute minimum, the boxed processor heatsink will require 500 Linear Feet per Minute (LFM) of cool air flowing over the heatsink. The airflow must be directed from the outside of the chassis directly over the processor heatsinks in a direction passing from one retention mechanism to the other. It also should flow from the front to the back of the chassis. Directing air over the passive heatsink of the boxed Intel(R) XeonTM Processor with 533 MHz Front Side Bus can be done with auxiliary chassis fans, fan ducts, or other techniques. It is also recommended that the ambient air temperature outside of the chassis be kept at or below 35 C. The air passing directly over the processor heatsink should not be preheated by other system components (such as another processor), and should be kept at or below 45 C. Again, meeting the processor's temperature specification is the responsibility of the system integrator. The processor temperature specification is found in Chapter 5.0. 90 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 8.0 Debug Tools Specifications The Debug Port design information has been moved. This includes all information necessary to develop a Debug Port on this platform, including electrical specifications, mechanical requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700 Debug Port Design Guide for the design of your platform. 8.1 Logic Analyzer Interface (LAI) Intel(R) is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture front side bus signals. There are two sets of considerations to keep in mind when designing a system that can make use of an LAI: mechanical and electrical. 8.1.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI. 8.1.2 Electrical Considerations The LAI will also affect the electrical performance of the front side bus; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide. Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz 91 This page intentionally left blank. 92 Intel(R) XeonTM Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz