Xeon Processor 533Mhz - Intel

Intel® Xeon ™ Processor with 533 MHz

Front Side Bus at 2 GHz to 3.06 GHz

Product Features

•Available at 2, 2.40, 2.66, 2.80, and 3.06 GHz

•Dual processing server/workstation support

•Binary compatible with applications running on

previous members of Intel’s IA32

microprocessor line

•Intel® NetBurst™ micro-architecture

•Hyper-Threading Technology

—Hardware support for multithreaded

applications

•533 MHz Front Side Bus

—Bandwidth up to 4.3 GB/second

•Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor core

frequency

•Hyper Pipelined Technology

•Advance Dynamic Execution

—Very deep out-of-order execution

—Enhanced branch prediction

•Level 1 Execution Trace Cache stores 12 K

micro-ops and removes decoder latency from

main execution loops

—Includes 8 KB Level 1 data cache

•512 KB Advanced Transfer L2 Cache (on-die,

full speed Level 2 cache) with 8-way

associativity and Error Correcting Code (ECC)

•Enables system support of up to 64 GB of

physical memory

•Streaming SIMD Extensions 2 (SSE2)

—144 new instructions for double-precision

floating point operations, media/video

streaming, and secure transactions

•Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D

performance

•Power Management capabilities

—System Management mode

—Multiple low-power states

•Advanced System Management Features

—Thermal Monitor

—Machine Check Architecture (MCA)

Document Num ber: 252135-003

March 2003

The Intel Xeon processo r with 533 MHz Front

Side Bus d elivers compute power at unpa ralleled

value and flexibility for powerful workstations,

intern et inf rastructure, and departm e ntal server

applicat ions. The Intel® NetBurst™ micro-

archite cture and Hyper-Threading Technol ogy

deli ve r out standi ng performa nc e a nd headroom

for peak internet server workloads, res ulting in

fast er resp onse time s, suppor t for more users, a nd

improved scalability.

The Intel® Xeon™ Process or wit h 533 MHz F ront Side Bus is des igned for high-perform a nc e

dual-processor workstation and server applications. Based on the Intel® Ne tBurst™ micro-

archite cture and the new Hyper -Threading Technol ogy, it is binary compatible with previous

Inte l Arch itec tur e (I A- 32) pr oces sor s. The Int el Xe on pr oce ssor wi th 53 3 MHz Front Sid e Bus

scalab le to two proces s ors in a multiprocess or system providing exceptional perfo rm ance for

applic a tion s running on adva nc e d oper a ting sys t ems suc h a s Windows XP*, Windows* 2000,

Linux*, and UNIX*.

2Intel® Xeon™ Proc essor w i th 533 MHz Front Side B us at 2 GHz to 3.06 GHz

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CON DITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABI LITY WHA TSOEVER, AND INTEL DISC LAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDI NG LIABIL ITY OR WA RRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRI NGEME NT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLE CT UAL PROPE RTY RIGHT. Intel products are not intended for use in medical , life saving, life sustaining applicat ions.

Intel may make cha nges to speci ficatio ns and prod uct descript io ns at any time, without noti ce.

*Other names and bra nds may be claimed as the proper ty of others.

Designer s mus t not rely on the absen ce or charact erist ic s of any featu res or instruc tions m ark ed "res erved" or "undefined. " In tel reserves these for

future definition and shall have no responsi bi lity wha tsoeve r for conflicts or incompat ibiliti es arising from f utu re chang es to them .

The Intel® Xeon™ processor may contain design defects or errors known as errata which may cause the product to deviate from

published speci f icatio ns. Current characterized errata are available on request.MP EG is an internationa l standard for video com pre ssi on/

decompressi on pr omo ted by ISO. Implem entatio ns of MP EG CO DECs , or MPEG enab led platforms may require licenses from var ious ent ities,

including Intel Corporation.

Contact your local Intel sale s office or your distributor to obtain the latest specificat ion s and befo re placing your product order.

Copies of documents which have an ordering numb er and are referenc ed in this docume nt, or other Intel literature may be obtained by callin g 1-800-

548-4725 or by visiting Intel’s websi te at http://www.intel.com.

Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetB urs t are trademark or regis tered tradem ar ks of Intel Corporation or its s u bsidia ries in the

United States and other count ries.

Copyrigh t © Intel Corpor ation , 2002-2003

Intel® Xeon™ Processor wi th 533 MH z Front  Si de Bus at 2 GHz to  3.06 GHz 3
Contents
0 Introduction.........................................................................................................................7
1 Terminology...........................................................................................................8
1. 1 Pro ce sso r Packa gin g  Termin olo gy..... ... ....... ... ....... ... ....... ... ....... ... ....... ... .8
2 State of Data .........................................................................................................9
3 References..........................................................................................................10
0 Electrical Specificati o ns. .... ...... .... ...... .... ............. ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ..11
1 Front Side Bus and GTLREF ..............................................................................11
2 Power and Ground Pins......................................................................................11
3 Decoupl in g Guidel in es ...... ... ....... ... ....... ... ....... ... ....... ... ....... ... .............. ... ....... ... ..11
3.1 VCC Decoupling.....................................................................................12
3. 2 Front Si de Bus AGTL+ Dec oup li ng....... .... ...... .... ...... .... ...... .... ............. ..12
4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking................................12
4. 1 Bus Clock.................... ... ....... ... ....... ... ....... ... ............. .... ...... .... ...... .... .....13
5 PLL Filter.............................................................................................................13
5.1 Mixing Processors..................................................................................15
6  Voltage Identification..........................................................................................15
6.1 Mixing Processors of Different Voltages ................................................16
7 Reserved Or Unused Pins...................................................................................17
8 Front Side Bus Signal Groups.............................................................................17
9 Asynchronous GTL+ Signals ...............................................................................19
10 Maximum Ratin gs. ............. ... .............. ... ....... ... ....... ... ....... ... ............. .... ...... .... .....19
11 Processor DC Specifications...............................................................................19
12 AGTL+ Front  Side Bus Speci fica tio n s.......... ... ....... ... ....... ... ....... ... ....... ... ....... ... ..26
0 Mechanical Specifications................................................................................................29
1 Mechanical Specifications...................................................................................30
2 Processor Package Load Specifications.............................................................35
3 Insertion Specifications .......................................................................................36
4 Mass Specifications.............................................................................................36
5 Materials..............................................................................................................36
6 Markings..............................................................................................................37
7 Pin-Out Diagram..................................................................................................38
0 Pin Listing and Signal Definitions.....................................................................................41
1 Processor Pin Assignments ................................................................................41
1.1 Pin Listing by Pin Name .........................................................................41
1.2 Pin Listing by Pin Number......................................................................50
2 Signal Definitions.................................................................................................60
0 Thermal Specifications.....................................................................................................69
1 Thermal Specifications........................................................................................70
2  Measurements for Thermal Specifications.........................................................72
2.1 Processor Case Temperature Measurement .........................................72
0 Features...........................................................................................................................73
1 Power-On Configuration Options ........................................................................73
2 Clock Control and Low Power States..................................................................73

4Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
2.1 Normal State—State 1...........................................................................73
2.2 AutoHALT Pow erd ow n State—State 2 .............. .... ...... .... ...... .... ...... .... ..74
2.3 Stop-Grant State—State 3 .....................................................................74
2.4 HALT/Grant Snoop State—State 4........................................................7 5
2.5 Sleep State—State 5..............................................................................7 5
2 .6 Bus Response Durin g Low Power  Stat es.... ... ....... ... ....... ... ....... ... .........76
3 Thermal Monito r................... ... ....... ... .............. ... ....... ... ....... ... ....... ... ............. .... ..76
3.1 Thermal Diode........................................................................................7 7
0 Boxed Processor Specifications.......................................................................................79
1 Introduction .........................................................................................................79
2 Mechanical Specifications...................................................................................80
2.1 Boxed Processor Heatsink Dimensions.................................................8 0
2.2 Boxed Processor Heatsink Weight.........................................................80
2.3 Boxed Proce sso r Rete nt ion  Mechan ism and Heat sin k Sup port s...........80
3 Boxed Process or Requirements ................. .... ...... .... ...... .... ...... .... ...... .... ...... .... ..84
3.1 Intel ® Xeon™ Proce sso r  with 533 MHz Front Side Bus........ .... ...... .... ..84
3.2 1U Rack Mount Server Solution.............................................................88
4 Thermal Speci fi cati o ns................... ... ....... ... ....... ... ....... ... .............. ... ....... ... ....... ..90
4.1 Boxed Processor Cooling Requirements...............................................90
0 Debug Tools Specifications..............................................................................................91
1 Logic Analyzer Interface (LAI).............................................................................9 1
1 .1 Mechanical Co nsi der at i ons................ ... ....... ... ....... ... ....... ... ....... ... ....... ..91
1.2 Electrical Considerations........................................................................91
Figures
Typica l VCCI OPL L, VCCA and VSSA Power  Distr ib ut ion.. ...... .... ............. ... ......14
Pha se Lock  Loop (PLL) Fil ter  Requ ire ments............ ... ....... ... ....... ... ....... ... ....... ..14
Intel® Xeon™ processor with  533 MHz  Fr ont Side Bus V ol t age-
Current Projections (VID 1.5V)............................................................................2 2
In t el  Xeon  proce ssor  with 53 3 M Hz Front Side B us Vol tage- Curr ent
Pro jec tio ns (VI D 1.52 5V)............. ... ....... ... ....... ... ............. .... ...... .... ...... .... ...... .... ..23
Electrical Test  Ci rcuit .... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ......27
THERMTRIP# to VCC Timing.............................................................................27
FC-mPGA2 Processor Package Assembly Drawing ...........................................29
FC-mPGA Processor Package Top View: Component Placement Detail...........30
Intel® Xeon™ Processor with 533 MHz Front Side Bus in the
FC-mPGA2 Package Drawing ............................................................................31
FC-mPGA2 Processor Package Top View: Component Height Keep-in............32
FC-mPGA2 Processor Package Cross Section View: Pin Side
Compone nt Ke ep-in................ .... ...... .... ...... .... ...... .... ...... .... ............. ... ....... ... ......33
FC-mPGA2 Processor Package: Pin Detail........................................................34
IHS Flatness and Tilt Drawing.............................................................................3 5
Pro cesso r Top -S ide Mark ing s..... ...... .... ...... .... ...... .... ............. ... ....... ... ....... ... ......37
Pro cesso r Bot to m-Sid e  Marking s.......... ... ....... ... ............. .... ...... .... ...... .... ...... .... ..37
Pro cesso r Pin Out Dia gra m:  Top View .... ............. .... ...... .... ...... .... ...... .... ............38
Pro cesso r Pin Out Diagr a m: Botto m View.. .... ...... .... ...... .... ...... .... ............. ... ......39
Processor with Thermal and Mechanical Components - Exploded View............69
Proc essor T herm al Design Power vs Electri cal Pr oj ecti ons for VID = 1.500V...70

Intel® Xeon™ Processor wi th 533 MH z Front  Si de Bus at 2 GHz to  3.06 GHz 5
Processo r T hermal Design Power vs Electrical Pro j ectio ns for VID = 1 .525V....71
Thermal Measurement Point for Processor TCASE............................................72
Sto p Clo ck Sta te  Machine.... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ... ....... ..74
Mechanical Representation of the Boxed Processor Passive Heatsink..............79
Boxed Processor Retention Mechanism and Clip...............................................81
Boxed Processor Retention Mechanism that Ships with the Processor..............82
Multiple View Space Requirements for the Boxed Processor.............................83
Fan Connector Electrical Pin Sequence.............................................................85
Processor Wind Tunnel General Dimensions .....................................................86
Processor Wind Tunnel Detailed Dimensions.....................................................87
Exploded View of the 1U Thermal Solution.........................................................88
Assembled View of the 1U Thermal Solution......................................................89
Tables
Front Side Bus-to-Core Frequency Ratio............................................................13
Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]....................13
Voltage Identification Definition...........................................................................16
Front Side Bus Signal Groups.............................................................................18
Pro ce ss or  Absolu te Maxi mum Ratin gs ........ ...... .... ...... .... ...... .... ............. ... ....... ..19
Voltage and Current Specifications.....................................................................21
Front Side Bus Differential BCLK Specifications.................................................23
AGTL+ Signal Group DC Specifications .............................................................24
TAP and PWRGOOD Signal Group DC Specifications.......................................24
Asynchronous GTL+ Signal Group DC Specifications........................................25
BSEL[1:0] and VID[4:0] DC Specifications..........................................................25
AGTL+ Bus Voltage Definitions...........................................................................26
Miscellaneous Signals + Specifications ..............................................................27
Di m ensio ns for th e In tel® X eon™ Process or wit h 533 MHz  F ront
Side Bus in the FC-mPGA2 Package..................................................................32
Package Dynamic and Static Load Specifications..............................................35
Processor Mass...................................................................................................36
Processor Material Properties.............................................................................36
Pin Listing by Pin Name......................................................................................41
Pin Listing by Pin Number...................................................................................50
Signal Definitions.................................................................................................60
Processor Thermal Design Power.......................................................................70
Power-On Configuration Option Pins..................................................................73
Thermal Diode Parameters.................................................................................77
Thermal Diode Interface......................................................................................78
F an Cable Conn e cto r Requirements..... ....... ... ............. .... ...... .... ...... .... ...... .... .....85
Fan Power and Signal Specifications..................................................................85

6Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Revision History

Date of Release Revision

No. Description

November 2002 -001 Initial Release

February 2003 -002

Added 3.06 GHz information.

Edited definitions with current terminology.

Added two TDP loadline figures in chapter 6.

Edited figures 18 and 19.

Added notes to signal definition tables for symmetric agents.

Edited Chapter 8.0 Boxed Processor Specifications.

March 2003 -003 Deleted Chapter 3 and Removed Section 2.13, 2.14

Added Table 13

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 7

1.0 Introduction

The Intel® Xeon™ Processor with 533 MHz Front Side Bus is based on the Intel® NetBurst™

micro-architecture, which operates at significantly higher clock speeds and delivers performance

levels that are significantly higher than previous generations of IA-32 processors. While based on

the Intel NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32

software.

The Intel NetBurst micro-architecture features begin with innovative techniques that enhance

processor execution such as Hyper Pipelined Technology, a Rapid Execution Engine, Advanced

Dynamic Execution, enhanced Floating Point and Multimedia unit, and Streaming SIMD

Ex te nsions 2 (SSE2). T he Hype r Pipe lined Technology doubles the pi pe line depth in th e processor,

allow ing the processor to reach much hig her cor e fr equencies. The Rapid Execution Engine allows

the two integer ALUs in the processor to run at twice the core frequency, which allows many

integ er instr uctions to execute in one half of the inter nal core cl ock period. The Advanced D ynamic

Execution improves speculative execution and branch prediction internal to the processor. The

floating poin t and multi-media unit s have been improve d by maki ng the registers 128 bits w i de and

adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-

precision floating point, SIMD integer, and memory management for improvements in video/

multimedia processing, secure transactions, and visual internet applications.

Also part of the Intel NetBurst micro-architecture, the front side bus and caches on the Intel Xeon

pro ces sor w ith 533 MHz Fr ont Side Bus pr ovide trem endo us thr ou ghp ut for server and works tat ion

workloads. The 533 MHz Front Side Bus provides a high-bandwidth pipeline to the system

memory and I/O. It is a quad-pumped bus running off a 133 MHz Front Side Bus clock making

4.3 Gigabyt e s per sec ond (4,300 Megabytes per seco nd) da ta tran sfer rates possible. The Ex e c ution

Trace Cache is a level 1 cache that stores approximately twelve thousand decoded micro-

operations, which removes the decoder latency from the main execution path and increases

performance. The Advanced Transfer Cache is a 512 KB on-die level 2 cache running at the speed

of the processor core providing increased bandwidth over previous micro-architectures.

In addition to the Intel NetBurst micro-architecture, the Intel Xeon processor with 533 MHz Front

Side Bus includes a groundbreaking new technology called Hyper-Threading technology, which

enabl es multi- thread ed software to execut e tasks in p arallel w ithin th e process or resulting in a more

efficient, simultaneous use of processor resources. Server applications can realize increased

perfor mance from Hyp er-Threading technology today, while work st ation applications are exp ected

to benefit from Hyper-Threading technology in the future through software and processor

evolution. The combination of Intel NetBurst micro-architecture and Hyper-Threading technology

delivers outstanding performance, throughput, and headroom for peak software workloads

resulting in fa ster res ponse t imes and im proved scalability.

The Intel Xeon pr ocessor wi th 533 MHz Front S ide Bus i s intende d for high performa nc e worksta-

tion and server s ys tems wit h up to two processors on a s ingle bu s. The processor supports both uni-

and dual-processor de signs. The Intel Xeon with 5 33 MHz Front Side Bus processors do not i nc or-

porate system managment devices (PIROM, OEM Scratchpad EEPROM, and thermal sensor), but

offer direct access to the pins of an on-die thermal diode. These output pins can interface with a

thermal sensor device that is placed on the baseboard. The Intel Xeon processor with 533 MHz

Front Side Bus is packaged in a 604-pin flip chip micro-PGA2 (FC-mPGA2) package, and utilizes

a surface mount ZIF socket wit h 604 pins.

The FC-mPGA2 package contains an extra pin (located at location AE30) compared to the INT-

mPGA package. This additional pin serves as a keying mechanism to prevent the FC-mPGA2

packag e fr om being instal led in the 603-p in socket since processors in the FC-mPGA2 package are

8Intel ® Xe on™ Pr oces so r with 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

only s upported in the 604-pin s ocket. S ince the additional contact for pin AE30 is electrically inert,

the 604-pin so cket will not have a solder ball at this location.

Mechanical components used for attaching thermal solutions to the baseboard should have a high

deg ree of commonalit y with the thermal so lution components enabled for the Intel Xeon pr oc e ssor

Heatsinks and retention mechanisms have been designed with manufacturability as a high priority.

Hence, mechanical assembly can be comp leted from the top of the baseboard.

The Intel Xeon processor with 533 MHz Front Side Bus uses a scalable front side bus protocol

referred to as the “Front Side Bus” in this document. The processor front side bus utilizes a split-

transaction, deferred reply protocol similar to that introduced by the Pentium® Pro processor Front

Side Bus, but is not compatible with the Pentium Pro processor front side bus. The Intel Xeon

processor with 533 MHz Front Side Bus is compatible with the Intel Xeon processor Front Side

Bus. The front side bus uses Source-Synchronous Transfer (SST) of address and data to improve

performance, an d transfers d a ta four times per bus clock (4X data transfer rate). Along with the 4X

data bus, the address bus can deliver addresses two times per bus clock and is referred to as a

‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.

Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 4.3

Gigabytes per second. Finally, the front side bus also introduces transactions that are used to

del i ve r inte rrupts.

Signals on the front side bus use Assisted GTL+ (AGTL+) level voltages which are fully described

in the a ppropriate platform des i gn gui de (ref e r to Se c ti o n 1.3).

1.1 Terminology

A ‘#’ sym bol after a signal name r efers to an active low signal, indicating a s ignal is in the assert ed

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Front Side Bus (FSB): The electrical interface that connects the processor to the chipset. Also

referred to as the processor system bus or the system bus. All memory and I/O transactions as well

as interrupt messages pass be tween th e process or and chipset ov e r the FSB.

1.1.1 Processor Packaging Terminology

Com m only use d t erms are ex pl ained here for clarific ation:

•604-pin socket - The 604-pin socket contains an additional contact to accept the additional

keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The

604-pin socket will also accept processors with the INT-mPGA package. Since the additional

contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this

location. Therefore, the additional keying pin will not require a baseboard via nor a surface-

mount pad. See the mPGA604 Socket Design Guidelines for details regarding this sock et.

•Ce ntral Agen t - The central agent is the ho st bridg e to the p rocess or and is typicall y known as

the chipset.

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 9

•F li p Chip B a ll Gr id A r ray (F C-BGA) - Microprocessor packaging using “flip chip” design,

where the processor is attached to the substrate face-down for better signal integrity, more

eff icient heat removal and lower ind uctance.

•FC-mPGA2 - Packaging technology with the processor die mounted directly to a micro-Pin

Grid Array substrate with an integrated heat spreader (IHS).

•Fr o nt Si de B us - Front Side Bus (FSB) is the electrica l inte rface tha t connects the proc esso r to

the ch ipset . A lso ref erred t o a s t h e p roce sso r system b u s o r th e sy st em bu s. All m e mory an d

I/O transactions as well as interrupt messages pass between the processor and chipset over the

FSB.

•Intel® Xeon™ processor with 512 KB L2 cache - The entire processor in its INT-mPGA

package, including processor core in its FC-BGA p ackage, integrated heat spreader (IHS), and

interposer.

•Intel® Xeon™ processor with 533 MHz Front Side Bus - The entire processor in its FC-

mPGA2 package, including processor core in its FC-BGA package, integrated heat spreader

(IHS), a n d interposer.

•Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal

solution to the processor.

•Interposer - The structure on whi ch the processor core package and I/O pin s are mount ed.

•OEM - Original Equipment Manufacturer.

•Processor core - The processor’s execution engine. All AC timing and signal integrity

specifications are to the pads of the pr ocess or core.

•Retention mechanism - The support components that are mounted through the baseboard to

the chassis to pro vide mechanical ret ention for the processor and heatsink as sembly.

•Symmetric Agent - A symmetric agent is a processor which shares the same I/O subsystem

and memory array, and runs the same operating system as another processor in a system.

Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems.

Intel® Xeon™ (DP - Dual Processor) processors should only be used in SMP systems which

have tw o or fewe r symme tric agents.

1.2 State of Data

The data contained in this d ocument is s ubject to change. I t is the best information that Intel is able

to provide a t the publicat ion date of this document.

10 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

1.3 References

The reader of this specification should also be familiar with material and concepts presented in the

following docume nts:.

NOTES:

1. Contact your Intel representative for the latest revision of documents without order numbers.

Document Intel Order Number1

AP-485, Intel® Processor Identification and the CPUID Instruction 241618

IA-32 Intel ® Architecture Software Developer's Manual

• Volume I: Basic Architecture

• Volume II: Instruction Set Reference

• Volume III: System Programm ing Guide

245470

245471

245472

Intel ® XeonTMProcessor with 512-KB L2 Cache and Intel® E7505 Chipset

Platform Design Guide http://developer.intel.com

Intel® Xeon™ Processor Thermal Design Guidelines 298348

603 -Pin Socket Design Guidelines 249672

mPGA604 Socket Design Guidelines 11299

Intel® Xeon™ Processor Specification Update 249678

CK00 Clock Synthesizer/Driver Design Guidelines 249206

VRM 9.0 DC-DC Converter Design Guidelines 249205

VRM 9.1 DC-DC Converter Design Guidelines 298646

Dual Intel® XeonTM Processor Voltage Regulator Down (VRD) Design

Guidelines 298644

ITP700 Debug Port Design Guide 249679

Intel® Xeon™ Processor with 533 MHz Front Side Bus System Compatibility

Guidelines

Intel® Xeon™ Processor with 533 MHz Front Side Bus Signal Integrity

Models http://developer.intel.com

Intel® Xe on™ Proc essor with 533 M Hz Fro nt Side Bus Mecha nical Models in

ProE* Format http://developer.intel.com

IIntel® Xeon™ Processor with 533 MHz Front Side Bus Mechanical Models

in IGES* Format http://developer.intel.com

Intel® Xeon™ Processor with 512-KB L2 Cache Front Side Bus Thermal

Models (FloTherm* and ICEPAK* format) http://developer.intel.com

Intel® Xeon™ Processor with 533 MHz Front Side Bus Core Boundary Scan

Descriptor Language (BSDL) Model http://developer.intel.com

Wired for Management 2.0 Design Guide http://developer.intel.com

Boxed Integr ation Notes http://support.intel.com/

support/processors/xeon

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 11

2.0 Electrical Specifications

2.1 Front Side Bus and GTLREF

Most Intel® Xeon™ Processor with 533MHz Front Side Bus signals use Assisted Gunning

Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved

noise margins and reduced ringing through low voltage swings and controlled edge rates. The

pro cessor term inat ion volt age leve l is VCC, the operating voltage of the processor core. Th e use of a

termination voltage that is determined by the processor core allows better voltage scaling on the

processor front side bus. Because of the speed improvements to data and address busses, signal

integrity and platform design methods become more critical than with previous processor families.

Front side bus design guidelines are detailed in the appropriate platform design guide (refer to

Sec tion 1.3).

The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to

deter mi ne if a signal is a logical 0 or a logical 1. GTLREF must be generate d on the bas eboard (See

Ta b le 1 2 for GTLREF specifications). Termination resistors are provided on the processor silicon

and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable

featu re and can be enabled or disabled via the ODTEN pin. For end bus agents , on-die termination

can be enabled to control reflections on the transmission line. For middle bus agents, on-die

termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating

the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to S ecti on 2.12 for

details on ODTEN resistor termination requirements.

Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard.

See Table 4 for details re garding these signals.

The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+

signals are based on flight tim e a s opposed to ca pacitive der atings. Analog signal simulation of the

front side bus, including trace lengths, is highly recommended when designing a system. Please

ref e r to http://developer.intel.com to obtain the Intel® Xeon™ Processor with 533 MHZ Front Side

Bu s Signal Integrity Mode ls.

2.2 Power and Ground Pins

For clean on-chip power distribution, the Intel X eon pr oc ess or wit h 5 3 3 M Hz Fr ont Sid e B us ha s

190 VCC (p owe r) and 189 VSS (gr ound) input s. All VCC pins m ust be connect e d to the system power

plane, while all VSS pins must be connected to the system ground plane. The processor VCC pins

must be supplied the voltage determined by the proces s or VID (Voltage ID) pins.

2.3 Decou p ling Gui delin es

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large average current swings between low and full power states. This may cause

voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.

Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting

changes in current demand by the component, such as coming out of an idle condition. Similarly,

they act as a storage well for current when entering an idle condition from a running condition.

12 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Care must be taken in the baseboard design to ensure that the voltage provided to the processor

remains within the specifications listed in Table 6. Failur e to do so can result in timin g violat ion s or

reduced lifetime of the component. For further information and guidelines, refer to the appropriate

pla tform de sign guidelines.

2.3.1 VCC Decoupling

Regulato r solutions need to provide bulk capacitance with a low Eff ective Series Resistance (ESR)

and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM

pins) to the 604-pin socket. Bulk decoupling may be provided on the voltage regulation module

(VRM) to meet help meet the large current swing requirements. The remaining decoupling is

provided on the baseboard. The power delivery path must be capable of delivering enough current

while maintaining the required tolerances (defined in Ta b le 6 ). For further information regarding

power delivery, decoupling, and layout guidelines, refer to the appropriate platform design

guidelines.

2.3.2 Front Side Bus AGTL+ Decoupling

The Intel® Xe on™ processo r with 533MHz Front Side B us integrates signa l ter minati on on the die

as well as part of the required high frequency decoupling capacitance on the processor package.

However, additional high frequency capacitance must be added to the baseboard to properly

deco uple the re turn c urrents from the front side bus. Bul k de c oupli ng must als o be provi de d by the

baseb oar d fo r prop er AGTL+ bu s opera tion. Decou pli ng g uid elin es are de scr ibe d in th e a ppr opria t e

pla tform de sign guidelines.

2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor core frequency is a multiple of the

BCLK[1:0] frequency. The maximum processor bus ratio multiplier will be set during

manufactu ring. T he de fault setting will equal the maximu m spe e d for the proce ssor.

The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The

processor core frequency is configured during reset by using values stored internally during

manufacturing. The stored value sets the highest bus fraction at which the particular processor can

operate.

Clock mu ltiply ing within the process or is provided by the internal PLL, which requires a cons tant

frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC

specifications for the BCLK[1:0] inp uts are provid ed in Table 7 and Table 13, respectively. These

specifications must be met while also meeting signal integrity requirements as outlined in Chapter

3.0. The proces s or utilizes a differential clock. Details regarding BCLK[1:0] driver speci fications

are provided in the CK408 Clock Synthesizer/Driver Design Guidelines.. Table 1 contains the sup-

ported b us frac tion r a tios an d their corre sponding cor e frequenci e s.

Intel® Xeon™ Processor with 533 MH z Front Side Bus

Datasheet 13

Ta b le 1. Front Side Bus-to-Core Frequency Ratio

2.4.1 Bus Clock

The front side bus frequency is set to the maximum supported by the individual processor.

BSEL[1:0] are outputs used to select the front side bus frequency. Table 2 defines the possible

combinations of the signals and the frequency associated with each combination. The frequency is

determined by the processor(s), chipset, and clock synthesizer. All front side bus agents must

operate at the same frequency. Individual processors will only operate at their specified front side

bus clock frequency, (100 MHz for pre sent ge neration p rocessors) .

The Intel® Xeon TM processor with a 533 MHz Front Side Bus is designed to run on a baseboard

with a 133 MHz bus clock.. On these baseboards, BSEL[0:1] are considered ‘reserved’ at the

proces so r sock et. .

Table 2. Front Side Bus Clock Freq uenc y Select Truth Table for BSEL[ 1:0 ]

2.5 PLL Filter

VCCA and VCCIOPLL are power sources required by the processor PLL clock generator. This

requirement is identical to that of the Intel Xeon processor with 512-KB L2 cache. Since these

PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is

detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e.

maximum frequency). To prevent this degradation, these supplies must be low pass filtered from

VCC. A typical fi lter topology is shown in Figure 1.

The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or

CIO in Figure 1), is as follows:

•< 0.2 dB gain in pass band

•< 0.5 dB at t e nu a ti on in pa s s ba n d < 1 Hz (s e e DC dr o p in ne xt s et of req ui reme nt s )

•> 34 dB att e nuatio n from 1 MHz to 66MHz

•> 28 dB attenuation fr om 66 MHz to co re frequency

Front Side Bus-to-Core

Frequency Ratio Core Frequency

1/15 2 GHz

1/18 2.40 GHz

1/20 2.66 GHz

1/21 2.80 GHz

1/23 3.06 GHz

BSEL1 BSEL0 Bus Cloc k Frequency

L L 100 MHz

L H 133 MHz

HLReserved

HHReserved

14 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

The filter requirements are illustrated in Figure 2. For recommendations on implem enting the filter

re fe r to th e appropriate platform design guidelines.

Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution

VCC

VCCA

VSSA

VCCIOPLL

L1/L2

Processor

PLL

R-Socket

R-Trace

R-Socket

R-Trace

Processor interposer "pin"

Baseboard via that connect s

filter to VCC plane

Trace

< 0.02 Ω

Socket pin

Figure 2. Phase Lock Loop (PLL) Filter Requirements

0 dB

-28 dB

-34 dB

0.2 dB

forbidden

zone

-0.5 dB

forbidden

zone

1 MHz 66 MHz

fcore

fpeak

1 HzDC

passband high fre q ue n c y

band

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 15

NOTES:

1. Diagram not to scale.

2. No specifications for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

2.5.1 Mixing Processors

Intel only supports those processor combinations operating with the same front side bus frequency,

core frequency, VID settings, and cache sizes. Not all operating systems can support multiple

processors with mixed frequencies. Intel does not support or validate operation of processors with

different cache sizes. Mixing processors of different steppings but the same model (as per CPUID

instruction) is supported, and is outlined in the Intel® Xeon™ Processor Specification Update.

Additional details are provided in AP-485, the Intel Processor Identification and the CPUID

Instruction application note.

The Intel Xeon processor with 533 MHz Front Side Bus does not sample the pins IGNNE#,

LI NT[0] / INTR, LINT[1]/NMI, and A20M# to establish the core to front side bus rat i o. Rather, the

processor runs at its tested frequency at initial power-on. If the processor needs to run at a lower

core fr equency, as must be done when a h igher speed processor is add ed to a system that contains a

lower f requenc y processor, the syste m BIOS is able to ef fec t the chang e in the cor e to f ront side bus

ratio.

2.6 Voltage Iden tif ica tion

The VID specification for the processor is defined in this datasheet, and is supported by power

delivery solutions designed according to the Dual Intel® Xeon TM Processor Voltage Regulator

Down (VRD) Design Guidelines, VRM 9.0 DC-DC Converter Design Guidelines, and VRM 9.1

DC-DC Converter Design Guidelines. The minimum voltage is provided in Table 6, and varies

with processor frequency. This allows processors running at a higher frequency to have a relaxed

minimum voltage specification. The specifications have been set such that one voltage regulator

de sign can work with all supported proces sor frequ e nc ies.

Note that the VID pins will drive valid and correct logic levels when the Intel® Xeon™ processor

with 533 MHz Front Side Bus is provided with a valid voltage applied to the SM_VCC pins.

VID_VCC must be correct and stable prior to enabling the output o f the VRM that supplies

VCC. Similarly, the output of the VRM must be disabled before VID_VCC becomes invalid.

Refer to Figure 17 for det ail s .

The processor uses five voltage identification pins, VID[4:0], to support automatic selection of

processor voltages. Table 3 specifies the voltage level corresponding to the state o f VID[4:0]. A ‘1’

in this table refers to a high voltage and a ‘0’ refers to low voltage level. If the processor socket is

empt y (V ID [4:0] = 1 11 1 1) , or the VR D or VR M canno t suppl y the vo lta ge that is reque st ed, it must

disable its voltage output. For further details, see the Dual Intel® XeonTM Processor Voltage

Regulator Down (VRD) Design Guidelines, or VRM 9.0 DC-DC Converter Design Guidelines or

the VRM 9.1 DC-DC Conv e rter Des i gn Guide l ines.

16 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

2.6.1 Mixing Processors of Different Voltages

Mixing proc e ssors operating with differe nt VID setti ngs (vo lta ges) is not supported and will not be

val ida ted by I ntel.

Table 3. Voltage Identification Definition

Processor Pins

VID4 VID3 VID2 VID1 VID0 VCC_VID (V)

1 1 1 1 1 VRM output off

111101.100

111011.125

111001.150

110111.175

110101.200

110011.225

110001.250

101111.275

101101.300

101011.325

101001.350

100111.375

100101.400

100011.425

100001.450

011111.475

011101.500

011011.525

011001.550

010111.575

010101.600

010011.625

010001.650

001111.675

001101.700

001011.725

001001.750

000111.775

000101.800

000011.825

000001.850

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 17

2.7 Reserved Or Unused Pins

All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to

VCC, VSS, or to any other signal (including one another) can result in component malfunction or

incom patibility with future processors. See Chapter 5.0 for a pin listing of the processor and for the

location of all Reserved pins.

For reliable operation, unused inputs or bidirectional signals should always be connected to an

appropriate signal level. In a system-level design, on-die termination has been included on the

processor to allow signal termination to be accomplished by the processor silicon. Most unused

AGTL+ inputs should be left as no connects, as AGTL+ termination is provided on the processor

silicon. However, see Table 4 for details on AGTL+ signals that do not include on-die termination.

Unus e d active high inputs should be connect e d through a re sistor to grou nd (VSS). Unused outputs

can be left unconnected, however this may interfere with some TAP functions, complicate debug

probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional

signals to power or ground. When tying any signal to power or ground, a resistor will also allow for

system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value

for the on-die termination resistors (RTT). See Table 12.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

te rmination. Inputs and all used outputs must be ter minat e d on the base board . Unused outputs may

be te rminated o n the baseboard or left unconnect e d. Note that le a ving unused out puts unterminated

may interfere with some TAP functions, complicate debug probing, and prevent boundary scan

testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design

Guide.

All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which

matches the trace impedance within ±10 Ω. TESTHI[3:0] and TESTHI[6:5] may all be tied

together and pulled up to VCC with a single resistor if desired. However, utilization of boundary

scan test will not be functional if these pins are connected together. TESTHI4 must always be

pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up

resistor values used for TESTHI[6:0] pins should have a resistance value within 20 percent of the

impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 Ω,

then a pull-up resistor value between 40 and 60 Ω should be used. The TESTHI[6:0] termination

recommendations provided in the Intel® XeonTM Processor Datasheet are also suitable for the

Intel® Xeon™ processor with 533 MHz Front Side Bus. However, Intel recommends new designs

or designs undergoing design updates follow the trace impedance matching termination guidelines

outlined in this section.

2.8 Front Side Bus Signal Group s

In order to simplify the following discussion, the front side bus signals have been combined into

groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as

a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as

well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+

output group as well as the AGTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of

tim ing paramet ers. One set is fo r common clock sig nals whos e timings are specifi ed with respect to

rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source

synchronous signals which are relative to their respective strobe lines (data and address) as well as

18 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can

become active at any time during the clock cycle. Tab le 4 identifies which signals are common

clock, source synchronous and asynchronous.

NOTES:

1. Refer to Section 5.2 for signal descriptions.

2. T hese signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design Guide and

corresponding Design Guide for termination requirements and further details.

3. The Intel® Xeon™ process or with 533MHz Front Side Bus utili zes only BR0# and BR1#. BR2# and BR3# are

not driven by the processor but must be terminated to VCC. For additional details regarding the BR[3:0]#

signals, see Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines.

4. These signals do not have on-die termination. Refer to corresponding Platform Design Guidelines for

termination requirements.

5. Note that Reset initialization function of these pins is now a software function on the Intel® Xeon™

processor with 533MHz Front Side Bus.

6. T he value of these pins during the active-to-inactive edge of RESET# to determine processor configuration

options. See Section 7.1 for details.

7. These signals may be driven simultaneously by multiple agents (wired-or).

8. VID_Vcc is required for correct VID logic operation of the Intel® Xeon™ processor with 533 MHz Front Side

Bus. Refer to Figure 17 for details.

Table 4. Front Side Bus Signal Groups

Signal Group Ty pe Signals 1

AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, BR [3:1]#3,4, DEFER#, RESET#4,

RS[2:0]#, RSP#, TRDY#

AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#7, BNR#7,

BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#,

DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7

AGTL+ Source Synchronous

I/O Synchronous to assoc.

strobe

AGTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Asynchronous GTL+ Input 4Asynchronous A20M#5, IGNNE#5, INIT#6, LINT0/INTR5,

LINT1/NMI5, SLP # , STPCLK#

Asynchronous GTL+ Output 4Asynchronous FERR#, IERR#, THERM TRIP#, PROCHOT#

Front Side Bus Clock Clock BCLK1, BCLK0

TAP Input 2Synchronous to TCK TCK, TDI, TMS, TRST#

TAP Output 2Synchronous to TCK TDO

Power/Other Power/Other BSEL[1:0], COMP[1:0], GTLREF, ODTEN,

Reserved, SKTOCC#, TESTHI[6:0],VID[4:0],

VCC, VID_VCC8, VCCA, VCCIOPLL, VSSA, VSS,

VCCSENSE, VSSSENSE, PWRGOOD

Signals Associated Strobe

REQ[4:0]#,A[16:3]#6ADSTB0#

A[35:17]#5ADSTB1#

D[1 5:0 ]# , DBI0# DSTBP0 #, DSTBN0#

D[31:16]#, DBI1# DSTBP1#, DSTBN1#

D[47:32]#, DBI2# DSTBP2#, DSTBN2#

D[63:48]#, DBI3# DSTBP3#, DSTBN3#

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 19

2.9 Asynchronous GTL+ Signals

The Intel® Xeon™ Processor with 533 MHz Front Side Bus does not utilize CMOS voltage levels

on any signals that connect to the processor silicon. As a result, legacy input signals such as

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SLP#, and STPCLK# utilize GTL+ input

buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, THERMTRIP# and

PROCHOT# utilize GTL+ output bu ffers. A ll of these a synchronous GTL+ signals follow the sa me

DC re quirements as AGTL+ signals, howe ver the outputs are not drive n high (during the logical 0-

to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous

GTL+ signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all

of the asynchronous GTL+ s ignals are required to be asserted for at least two BCLKs in order for

the processor to recognize them. See Table 10 for the DC specifications for the asynchronous

GTL+ signal gr oups.

2.10 Maximum Ratings

Table 5 lists the processor’s maximum environmental stress ratings. Functional operation at the

absolute maximum and minimum is neither implied nor guaranteed. The processor should not

receive a clock while subjected to these conditions. Functional operating parameters are listed in

the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.

Furthermore, although the processor contains protective circuitry to resist damage from static

electric discharge, one should always take precautions to avoid high static voltages or electric

fields.

1. This rating applies to any pin of the processor.

2. Contact Intel for storage requirements in excess of one year.

2.11 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless

noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal

definitions. The voltage and current specifications for all versions of the processor are detailed in

Ta b le 6. For platform planning refer to Figure 3. Notice that the graphs include Thermal Design

Power (TDP) associated with the maximum current levels. The DC specifications for the AGTL+

signals are listed in Table 8.

Table 5. Processor Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

TSTORAGE Processor storage temperature -40 85 °C 2

VCC Any processor supply voltage with

respect to VSS -0.3 1.75 V 1

VinAGTL+ AGTL+ buffer DC input voltage with

respect to VSS -0.1 1.75 V

VinGTL+ Async GTL+ bu ffer DC i nput volt age

with respect to Vss -0.1 1.75 V

IVID Max VID pin current 5 mA

20 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Table 6 through Table 11 list the processor DC specifications and are valid only while meeting

specifications for case temperature (TCASE as specified in Chapter 6. 0), clo c k frequency, an d input

volta ges. Care shoul d be ta ken to re a d al l note s as sociat ed with each parameter.

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 21

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processors.

2. These voltages are targets only. A variable voltage source should exist on systems in the event that a

different voltage is required. See Section 2.6 and Table 3 for more information.

3. The voltage specification requirements are measured across vias on the platform for the VCC_SENSE and

VSS_SENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe

capacitance, and 1 milliohm minimum impedance. The maximum length of ground wire on the probe should

be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

4. The processor should not be subje cted to an y st atic Vc c lev el that ex ceeds the volt age v s curr ent l oad-line for

any given current loading (as shown in figure 3 for VID=1.500V and figure 4 for VID=1.525V). Moreover, Vcc

should never exceed Vcc_VID. Failure to adhere to this specification can shorten the processor lifetime.

5. Vcc_max and Vcc_min are defined at a load of Icc_max. Icc_max is defined at Vcc_max



6. The current specified is also for AutoHALT State.

7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as

indicated by the assertion of PROCHOT#.

8. VID_VCC is required for correct operation of the processor VID logic. Refer to Figure 17 for details.

9. This specification applies to the PLL power pins VCCA and VCCIOPLL. See Section 2.5 for details. This

parameter is based on design characterization and is not tested

10.This specification applies to each GTLREF pin.

11.The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage

regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins.

12.Adherence to this loadline specification is required to ensure reliable processor operation.

Table 6. Voltage and Current Specifications

Symbol Parameter Core Freq M in Typ Max VID Unit Notes1

VCC VCC for Intel Xeon

processor with 533

MHz Front Side Bus

2 GHz

2.40 GHz

2.66 GHz

2.80 GHz

3.06 GHz

1.353

1.344

1.334

1.331

1.352

Refer to

Figure 3

1.461

1.456

1.452

1.450

1.467

1.5

1.525

2, 3, 4, 5,11, 12

SM_VCC SMBus supply

voltage All freq. 3.135 3.30 3.465 V 8

ICC ICC for Intel Xeon

processor with 533

MHz Front Side Bus

2 GHz

2.40 GHz

2.66 GHz

2.80 GHz

3.06 GHz

45.4

51.4

57.1

59.1

69.1

4, 5

ICC_PLL ICC for PLL power

pins All freq 60 mA 9

ICC_GTLREF ICC for GTLREF pins All freq 15 µA 10

ISGnt/ISLP ICC Stop-Grant/Sleep All freq 25 A 6

ITCC ICC TCC active All freq 18.6 A 7

22 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Figure 3. Intel® Xeon™ processor with 533 MHz Front Side Bus Voltage-Current

Projections (VID 1.5V)

1.44

1.45

1.46

1.47

1.48

1.49

1.50

1.51

0 10203040506070

Proce sso r Current ( A)

Maximum Processor

Voltage (VDC)

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 23

Figure 4. Intel Xeon processor with 533 MHz Front Side Bus Voltage-Current

Projections (VID 1.525V)

NOTES:.

Table 7. Front Side Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

VLInput Low

Voltage -.150 0.000 N/A V 7

VHInput High

Voltage 0.660 0.710 0.850 V 7

VCROSS(abs) Absolute

Crossing Point 0.250 N/A 0.550 V 7, 7 2,8

VCROSS(rel) Relative

Crossing Point 0.250 +

0.5(VHavg - 0.710) N/A 0.550 +

0.5(VHavg - 0.710) V7, 7 2,3,8,9

∆VCROSS Range of

Crossing Points N/A N/A 0.140 V 7, 7 2,10

VOV Overshoot N/A N/A VH + 0.3 V 74

VUS Undershoot -0.300 N/A N/A V 75

VRBM Ringback Margin 0.200 N/A N/A V 6

VTM Threshold Margin Vcross - 0.100 N/A Vcross + 0.100 V 6

24 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the

falling edge of BCLK1.

3. VHavg is the statistical average of the VH measured by the oscilloscope.

4. Overshoot is defined as the absolute value of the maximum voltage.

5. Undershoot is defined as the absolute value of the minimum voltage.

6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback

and the maximum Falling Edge Ringback.

7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential

receiver switches. It includes input threshold hysteresis.

8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.

10.∆VCROSS is defined as the total variation of all crossing voltages as defined in note 2.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

3. VIL is defined as the maxi mum vol tage l evel a t a r eceiv ing agent tha t wil l be interpreted as a logi cal l ow value.

4. VIH and VON may experience excursions above VCC. However, input signal drivers must comply with the

signal quality specifications in Chapter 3.0.

5. Refer to the Intel®Xeon™ Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V

characteristics.

6. The VCC referred to in these specifications refers to instantaneous VCC.

7. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with RTT enabled.

8. Leakage to VCC with pin held at 300 mV.

9. Leakage to VSS with pin held at VCC.

Table 9. TAP and PWRGOOD Signal Group DC Specifications

Table 8. AGTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

1,7

VIH Input High Voltage 1.10 * GTLREF VCC V2, 4, 6

VIL Input Low Voltage 0.0 0.90 * GTLREF V 3, 6

VOH Output High Voltage N/A VCC V4, 6

IOL Output Low Current N/A VCC /

(0.50 * RTT_min + RON_min)

= 50 mA 6

IHI Pin Leakage High N/A 100 µA 9

ILO Pin Leakage Low N/A 500 µA 8

RON Buffer On Resistance 7 11 Ω5, 7

Symbol Parameter Min Max Unit Notes 1, 2

VHYS TAP Input Hysteresis 200 300 8

VT+ TAP input low to high

threshold voltage 0.5 * (VCC + VHYS_MIN) 0.5 * (VCC + VHYS_MAX)5

VT- TAP input high to low

threshold voltage 0.5 * (VCC - VHYS_MAX) 0.5 * (VCC - VHYS_MIN)5

VOH Output High Voltage N/A VCC V3, 5

IOL Output Low Current 40 mA 6, 7

IHI Pin Leakage High N/A 100 µA 10

ILO Pin Leakage Low N/A 500 µA 9

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 25

NOTES:.

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. All outputs are open drain

3. TAP signal group must meet the system signal quality specification in Chapter 3.0.

4. Refer to the Intel® Xeon™ Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V

characteristics.

5. The VCC referred to in these specifications refers to instantaneous VCC.

6. The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

7. VOL_MAX of 0.300V is guaranteed when driving a test load.

8. VHYS represents the amount of hysteresis, nominally centered about 0.5*VCC, for all TAP inputs.

9. Leakage to VCC with Pin held at 300 mV.

10.Leakage to VSS with pin held at VCC.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. All outputs are open drain

3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

4. VIL is defi ned as the m aximum voltage lev el at a rece iving a gent that w ill be inter preted as a logic al low value .

5. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the

signal quality specifications in Chapter 3.0.

6. Refer to the Intel®Xeon™Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V

characteristics.

7. The VCC referred to in these specifications refers to instantaneous VCC.

8. The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

9. VOL_MAX of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with RTT enabled.

10. Leakage to VCC with Pin held at 300 mV.

11 .Leakage to VSS with pin held at VCC.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. These parameters are based on design characterization and are not tested.

Table 11 . BSEL[1:0] and VID[4:0] DC Specifications

RON Buffer On Resistance 8.75 13.75 Ω4

Table 10. Asynchronous GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1, 7

VIH Input High Voltage 1.10 * GTLREF VCC V 3, 5, 7

VIL Input Low Voltage 0.0 0.90 * GTLREF V 4, 6

VOH Output High Voltage N/A VCC V 2, 5, 7

IOL Output Low Current 50 mA 8,9

IHI Pin Leakage High N/A 100 µA 11

ILO Pin Leakage Low N/A 500 µ A 10

RON Buffer On Resistance 7 11 Ω6

Symbol Parameter Min Max Unit Notes1

Ron (BSEL) Buffer On

Resistance 9.2 14.3 Ω2

Ron

(VID) Buffer On

Resistance 7.8 12.8 Ω2

IHI Pin Leakage Hi N/A 100 µA 3

26 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are not tested and are based on design simulations.

3. Leakage to Vss with pin held at 2.50V.

2.12 AGTL+ Front Side Bus Specifications

Routing topologies are dependent on the number of processors supported and the chipset used in

the design. Please refer to the appropriate platform design guidelines. In most cases, termination

resistors are not required as these are integrated into the processor. See Table 4 for details on which

AGTL+ signals do not in c lude on-die te rminat ion.The te rmination resist ors are enabled or disabl e d

through the ODTEN pin. To enable termination, this pin should be pulled up to VCC through a

resistor and to disable termination, this pin should be pulled down to VSS through a resistor. For

optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should

have a resistance value within 20 percent of the impedance of the baseboard transmission line

traces. For example, if the trace impedance is 50 Ω, then a value between 40 and 60 Ω should be

used. The processor’s on-die termination must be enabled for the end agent only. Please refer to

Ta bl e 1 2 for termination resistor values. For more details on platform design see the appropriate

pla tform de sign guidelines.

Valid high and low levels are determined by the input buffers via comparing with a reference

voltage called GTLREF.

Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be

generated on the baseboard using high precision voltage divider circuits. It is important that the

baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for

the AGTL+ signal group traces is known and well-controlled. For more details on platform design

see the appropr iate platform de si gn guidelines .

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. T he tolerances for this specification have been stated generically to enable system designer to calculate the

minimum values across the range of VCC.

3. GTLREF is generated from VCC on the baseboard by a voltage divider of 1 percent resistors. Refer to the

appropriate platform design guidelines for implementation details.

4. RTT is the on-die termination resistance measured from VCC to 1/3 V CC at the AGTL+ output driver. Refer to

the Intel® Xeon™ Processor with 533MHz Front Side Bus Signal Integrity Models for I/V characteristics.

5. COMP resistors are pull downs to VSS provided on the baseboard with 1% tolerance. See the appropriate

platform design guidelines for implementation details.

6. The VCC referred to in these specifications refers to instantaneous VCC.

7. The COMP resistance value varies by platform. Refer to the appropriate platform design guideline for the

recommended COMP resistance value.

Table 12. AGTL+ Bus Voltage Definitions

Symbol Parameter Min Typ M ax Units Notes 1

GTLREF Bus Reference Voltage 2/3 * VCC - 2% 2/3 * VCC 2/3 * VCC + 2% V 2, 3, 6

GTLREF

New Design Bus Reference Voltage 0.63*VCC - 2% 0.63*VCC 0.63*VCC + 2% V 2, 3, 6,

RTT Termination Resistance 36 41 46 Ω4

RTT

New

Design Termination Resistance 45 50 55 Ω4, 9

COMP[1:0] COMP Resistance 42.77 43.2 43.63 Ω5, 8

COMP[1:0]

New

Design COMP Resistance 49.55 50 50.45 Ω5, 8, 9

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 27

8. The values for RTT and COMP noted as ‘New Designs’ apply to designs that are optimized for the Intel®

Xeon™ processor with 533MHz Front Side Bus. Refer to the appropriate platform design guideline for the

recommended COMP resistance value.

9. This specification applies to the Intel® Xeon™processor with 533MHz Front Side Bus when implemented in

platforms that do not include forward compatibility with future processors.

Table 13. Miscellaneous Signals + Specifications

Figure 6. THERMTRIP# to VCC Timing

T# Parameter Min Max Unit Figure Notes

T39: THERMTRIP# to Vcc Removal 0.5 S 6

Figure 5. Electrical Test Circuit

Vtt Vtt

Rload = 50 ohms

C = 1.2 pF

L = 2.4nH

AC Timings

specified at pad.

Zo = 50 ohms, d=420mils, So=169ps/in

THERMTRIP# Power Down Sequence

T39 < 0.5 seconds

Note: THERMTRIP# is undefined when RESET is active

THERMTRIP#

Vcc

T39

28 Int el ® Xeon™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3.06 GHz

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Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 29

3.0 Mechanical Specifications

The Intel® Xeon™ Processor with 533 MHz Front Side Bus uses the Flip Chip Micro-Pin Grid

Array (FC-mPGA) package containing the processor die covered by an integrated heat spreader

(IHS) Mechanical specifications for the processor are given in this section. See Section 1.1 for

terminology definitions. Figure 7 provides a basic assembly drawing and includes the components

which mak e up th e entire processor. Package dimensions are provided in Table 14.

Th e Intel® Xeon™ proce ssor w ith 533 MHz Front Side Bus utili z e s a sur face m ount 60 4-pin z e ro-

insertion force (ZIF) socket for installation into the baseboard. See the 604-Pin Socket Design

Guidelines for furth e r details on the processor socket.

For Figure 9 through Figu re 13, the following notes apply:

1. Unless otherwise spe cified, the foll owing dra wings are dimensione d in millimet e rs.

2. All dimensions are not tes ted, but are guaranteed by design characterization.

3. Figures and drawings labelled as “Reference Dimensions” are provided for informational

purposes only. Reference Dimensions are extracted from the mechanical design database and

are nominal dimensions with no tolerance information applied. Reference Dimensions are

NOT checked as part of the processor manufacturing process. Unless noted as such,

dimens ions in parent he ses without toleranc e s are Re fe rence Dimensions.

4. Drawings are not to scale.

Note: applies t o Intel Xeon processor in the FC-mPG A2 package.

1. Integr ated Heat Spreader (IHS )

2. Processor die

3. FC-mPGA2 package

4. Land side Capacitors

5. Package Pin

Figu r e 7. FC-mPGA 2 P r o cess o r P ackage Ass embl y Drawi n g

123

30 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

3.1 Mechanical Specifications

Figure 8. FC-mPGA Proce sso r Packa ge Top View: Component Placement Detail

Pin A1

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 31

Fig ur e 9. In tel ® X eo n™ Processor with 533 MHz Fro nt Sid e Bus in the FC-mPGA2 Pack age

Drawing

32 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Figure 10 details the keep-in zone for components mounted to the top side of the processor

interposer. The components inclu de the EEPROM, thermal sensor, resistors and capacitors.

Table 14. Dimensions for the Intel® Xeon™ Processor with 533 MHz Front Side

Bus in the F C-m PGA2 Pack ag e

Symbol Notes

Min Nominal Max

A 42.40 42.50 42.60

B 30.90 31.00 31.10

E 3.42 3.60 3.78

F 1.95 2.03 2.11

G 18.80 19.05 19.30

H 37.85 38.10 38.35

J 6. 35 Nomi nal Component K eepi n

K 12. 70 Nom inal Com ponent K eepi n

L 14.99 15.24 15.49

M 30.23 30.48 30.73

N 6. 35 Nomi nal Component K eepi n

R 1.27 Nominal

T12.70

P 0.26 0.31 0.36 Pin Diameter

P in Tp 0. 25

Milimeters

Figure 10. FC-mPGA 2 Proc essor P ackage Top View: Component Height Keep- i n

15.5 7.5

1.61

15.5

7.5 1.61

COMPONENT KEEPOUT

CROSS HATCHED AREA

2.27 mm MAX ALLOWABL

COMPONENT HEIGHT

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 33

Figure 11 details the ke e p-i n specif ic ation for pin-side co mponents. The processor may conta i n pin

side capacitors mounted to the processor package. These capacitors will be exposed within the

opening of the interposer cavity.

Figure 11. FC-mPGA2 Processor Package C ross Section View: Pin Side Compon ent Keep-in

12.7 mm

Component Keepin

1.5 mm

Compon

ent

Keepin

IHS

FC-mPGA2P

34 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Fig ur e 12. FC -mPGA2 Pr o cess o r P ackage: Pin Detail

1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni.

2. 0.254 Diametric true position, pin to pin.

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 35

Figur e 13 details the flatness and tilt specification s for the IHS of the Int el Xeon proces s or with

533 MHz Fron t Side Bus , r e s pectiv ely. T ilt is measured w ith the reference datum set to the bottom

of the processor interposer.

3.2 Proces sor Packa ge Load Specifi catio ns

Table 15 provides dynamic and static load specifications for the processor IHS. These mechanical

load limits should not be exceeded during heat sink assembly, mechanical stress testing, or

standard drop and shipping conditions. The heat sink attach solutions must not induce continuous

stress onto the processor with the exception of a uniform load to maintain the heat sink-to-

proces sor thermal in terface. It is not recommende d to use any porti on of the processor interpo ser as

a mechanical reference or load b earing surface for ther m al solutions .

NOTES:

1. This specification applies to a uniform compressed load.

2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and

processor interface.

3. These parameters are based on design characterization and not tested.

4. Dynamic loading specifications are defined assuming a maximum duration of 11ms.

5. The heatsink weight i s assumed to be one pound. Shock input to the sys tem during shoc k testing is assume d

to be 50 G’s. AF is the amplification factor.

Figure 13. IHS Flatne ss and Tilt Drawing

0.080

Ta b le 15 . Pack ag e Dynamic and Static L o ad Speci fi cati o ns

Parameter Max Unit Unit

Static 50 lbf 1, 2, 3

Dynamic 50 + 1 lb * 50G input * 1.8 (AF)

= 140 lbf 1, 2, 4, 5

36 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

3.3 Insertion Specifications

The processor can be inserted and removed 15 times from a 604-pin socket meeting the mPGA604

Socket Design Guidelines document. Note that this specification is based on design

characterization and is not tested.

3.4 Mass Specifications

Table 16 specifies the processors mass. This includes all components which make up the entire

proce ssor produ c t.

3.5 Materials

The processor is assembled from several components. The basic material properties are described

in Table 17.

Table 16. Processo r Mass

Processor Mass (grams)

Intel® Xeon™ Processor with 533 MHz Front Side

Bus 25

Ta b l e 17. P r ocess o r M aterial Pro perties

Component Material

Integrated Heat Spreader Nickel plated copper

FC-BGA BT Resin

Interposer FR4

Interposer pins Kovar with Gold over nickel

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 37

3.6 Markings

The following section details the processor top-side laser markings. It is provided to aid in the

ident ification of the pro ces so r.

NOTE:

1. Character size for laser markings is: height 0.050" (1.27mm), width 0.032" (0.81mm).

2. All characters will be in upper case.

Figure 15. P roce sso r Bot tom-Side Markings

Figure 14. Proces sor Top-Side Marki ngs

Group A Line1

Group A Li ne 2

Group B Line1

Group B Line2

Pin A1

Dynamic Laser

Mark Area with 2D Matrix

2D Ma trix en co d es ATP O

number and Serial number

Group A Line1

Group A Li ne 2

Group B Line1

Group B Line2

Group A Line1

Group A Li ne 2

Group B Line1

Group B Line2

Pin A1Pin A1

Dynamic Laser

Mark Area with 2D Matrix

2D Ma trix en co d es ATP O

number and Serial number

38 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

3.7 Pin-Out Diagr am

This section provides two view of the processor pin grid. Figure 16 and Figure 17 detail

the coordinate s of the proces sor pins.

Figure 16. Proces sor Pi n Out D iagram: Top View

Vcc/Vss

ADDRESS

DATA

Vcc/Vss

CLOCKS SMBus

COMMON

CLOCK

COMMON

CLOCK

Async /

JTAG

= Signal

= Po w e r

= Ground = Reserved

3 5 7 9 11 13 15 17 19 21 23 25 27 29 311

= G TLREF

= SM _V CC

2 4 6 8 10 12 14 16 18 20 22 24 26 28

= M e chanical

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 39

Figure 17. P roce ssor Pin Out Diagram : Bottom View

Vcc/Vss

= Signal

= Power

= Ground = Reserved

= GTLREF

= SM_VCC

AD AD

ADDRESS

DATA CLOCKSSMBus

COMMON

CLOCK

COMMON

CLOCK

Async /

JTAG

35791113151719212325272931 1

246810121416182022242628

= Mechanical

40 Int el ® Xeon™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3.06 GHz

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Intel® Xeon™ P roce ss or with 53 3MH z Front Side Bus

Datasheet 41

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

A3# A22 Source Sync Input/Output

A4# A20 Source Sync Input/Output

A5# B18 Source Sync Input/Output

A6# C18 Source Sync Input/Output

A7# A19 Source Sync Input/Output

A8# C17 Source Sync Input/Output

A9# D17 Source Sync Input/Output

A10# A13 Source Sync Input/Output

A11# B16 Source Sync Input/Output

A12# B14 Source Sync Input/Output

A13# B13 Source Sync Input/Output

A14# A12 Source Sync Input/Output

A15# C15 Source Sync Input/Output

A16# C14 Source Sync Input/Output

A17# D16 Source Sync Input/Output

A18# D15 Source Sync Input/Output

A19# F15 Source Sync Input/Output

A20# A10 Source Sync Input/Output

A21# B10 Source Sync Input/Output

A22# B11 Source Sync Input/Output

A23# C12 Source Sync Input/Output

A24# E14 Source Sync Input/Output

A25# D13 Source Sync Input/Output

A26# A9 Source Sync Input/Output

A27# B8 Source Sync Input/Output

A28# E13 Source Sync Input/Output

A29# D12 Source Sy nc Input/Output

A30# C11 S our ce Sync Input/Output

A31# B7 Sour ce Sync Input/Output

A32# A6 Sour ce Sync Input/Output

A33# A7 Sour ce Sync Input/Output

A34# C9 Source Sy nc Input/Output

A35# C8 Source Sy nc Input/Output

A20M# F27 As ync GTL+ Input

ADS# D19 Common Clk Input/Output

ADSTB0# F17 Source Sy nc Input/Output

ADSTB1# F14 Source Sy nc Input/Output

AP0# E10 Common Clk Input/Output

AP1# D9 Commo n Clk Input/Output

BCLK0 Y4 Sys Bus Clk Input

BCLK1 W5 Sys Bus Clk Input

BINIT# F11 Co mm o n Clk Input/Output

BNR# F20 Comm on Clk Input/Output

BPM0# F6 Common Clk Input/Output

BPM1# F8 Common Clk Input/Output

BPM2# E7 Common Clk Input/Output

BPM3# F5 Common Clk Input/Output

BPM4# E8 Common Clk Input/Output

BPM5# E4 Common Clk Input/Output

BPRI# D23 Common Clk Input

BR0# D20 Comm o n Clk Input/Output

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

4.0 Pin Listing and Signal Definitions

4.1 Processor Pin Assignment s

Sec tion 2.8 c ontains the fro nt side bus signal gro ups in Table 4 fo r t he In tel ® Xeon™ Processor with

533 MHz Front Side Bus. This se c tion p rovides a sor te d pi n list in Table 38 and Table 39. Table 38 is

a li sting of all pro cess or pi ns or der ed alph abet ica lly by pin na me. Table 39 is a lis ting of al l proces sor

pins ordered by pin number.

4.1.1 P in Listing by Pin Name

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

42 Datasheet

BR1# F12 Common Clk Input

BR2# 1E11 Common Clk Input

BR3# 1D10 Common Clk Input

BSEL0 AA3 Power/Other Output2

BSEL1 AB3 Power/Other Output2

COMP0 AD16 Power/Other Input

COMP1 E16 Power/Other Input

D0# Y26 Source Sync Input/Output

D1# AA27 Source Sync Input/Output

D2# Y24 Source Sync Input/Output

D3# AA25 Source Sync Input/Output

D4# AD27 Source Sync Input/Output

D5# Y23 Source Sync Input/Output

D6# AA24 Source Sync Input/Output

D7# AB26 Source Sync Input/Output

D8# AB25 Source Sync Input/Output

D9# AB23 Source Sync Input/Output

D10# AA22 Source Sync Input/Output

D11# AA21 Source Sync Input/Output

D12# AB20 Source Sync Input/Output

D13# AB22 Source Sync Input/Output

D14# AB19 Source Sync Input/Output

D15# AA19 Source Sync Input/Output

D16# AE26 Source Sync Input/Output

D17# AC26 Source Sync Input/Output

D18# AD25 Source Sync Input/Output

D19# AE25 Source Sync Input/Output

D20# AC24 Source Sync Input/Output

D21# AD24 Source Sync Input/Output

D22# AE23 Source Sync Input/Output

D23# AC23 Source Sync Input/Output

D24# AA18 Source Sync Input/Output

D25# AC20 Source Sync Input/Output

D26# AC21 Source Sync Input/Output

D27# AE22 Source Sync Input/Output

D28# AE20 Source Sync Input/Output

D29# AD21 Source Sync Input/Output

D30# AD19 Source Sync Input/Output

D31# AB17 Source Sync Input/Output

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

D32# AB16 Source Sync Input/Output

D33# AA16 Source Sync Input/Output

D34# AC17 Source Sync Input/Output

D35# AE13 Source Sync Input/Output

D36# AD18 Source Sync Input/Output

D37# AB15 Source Sync Input/Output

D38# AD13 Source Sync Input/Output

D39# AD14 Source Sync Input/Output

D40# AD11 Source Sync Input/Output

D41# AC12 Source Sync Input/Output

D42# AE10 Source Sync Input/Output

D43# AC11 Source Sync Input/Output

D44# AE9 Source Sync Input/Output

D45# AD10 Source Sync Input/Output

D46# AD8 Source Sync Input/Output

D47# AC9 Source Sync Input/Output

D48# AA13 Source Sync Input/Output

D49# AA14 Source Sync Input/Output

D50# AC14 Source Sync Input/Output

D51# AB12 Source Sync Input/Output

D52# AB13 Source Sync Input/Output

D53# AA11 S our ce Sync Input/Output

D54# AA10 Source Sync Input/Output

D55# AB10 Source Sync Input/Output

D56# AC8 Source Sync Input/Output

D57# AD7 Source Sync Input/Output

D58# AE7 Source Sync Input/Output

D59# AC6 Source Sync Input/Output

D60# AC5 Source Sync Input/Output

D61# AA8 Source Sync Input/Output

D62# Y9 Source Sync Input/Output

D63# AB6 Source Sync Input/Output

DBSY# F18 Common Clk Input/Output

DEFER# C23 Commo n Clk Input

DBI0# AC27 Source Sync Input/Output

DBI1# AD22 Source Sync Input/Output

DBI2# AE12 Source Sync Input/Output

DBI3# AB9 Source Sync Input/Output

DP0# AC18 Commo n Clk Input/Output

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel® X eon™ Processor with 5 33MHz Front Side Bus

Datasheet 43

DP1# AE19 Common Clk Input/Output

DP2# AC15 Common Clk Input/Output

DP3# AE17 Common Clk Input/Output

DRDY# E18 Common Clk Input/Output

DSTBN0# Y21 Source Sync Input/Output

DSTBN1# Y18 Source Sync Input/Output

DSTBN2# Y15 Source Sync Input/Output

DSTBN3# Y12 Source Sync Input/Output

DSTBP0# Y20 Source Sync Input/Output

DSTBP1# Y17 Source Sync Input/Output

DSTBP2# Y14 Source Sync Input/Output

DSTBP3# Y11 Source Sync Input/Output

FERR# E27 Async GTL+ Output

GTLREF W23 Power/Other Input

GTLREF W9 Power/Other Input

GTLREF F23 Power/Other Input

GTLREF F9 Power/Other Input

HIT# E22 Common Clk Input/Output

HITM# A23 Common Clk Input/Output

IERR# E5 Async GTL+ Output

IGNNE# C26 Asy nc GTL+ Input

INIT# D6 Async GTL+ Input

LINT0 B24 Async GTL+ Input

LINT1 G23 Async GTL+ Input

LOCK# A17 Common Clk Input/Output

MCERR# D7 Common Clk Input/Output

ODTEN B5 Power/Other Input

PROCHOT# B25 Async GTL+ Output

PWRGOOD AB7 Async GTL+ Input

REQ0# B19 Source Sync Input/Output

REQ1# B21 Source Sync Input/Output

REQ2# C21 Source Sync Input/Output

REQ3# C20 Source Sync Input/Output

REQ4# B22 Source Sync Input/Output

Reserved A1 Reserved Reserved

Reserved A4 Reserved Reserved

Reserved A15 Reserved Reserved

Reserved A16 Reserved Reserved

Reserved A26 Reserved Reserved

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

Reserved B1 Reserved Reserved

Reserved C5 Reserved Reserved

Reserved D25 Reserved Reserved

Reserved W3 Reserved Reserved

Reserved Y3 Reserved Reserved

THERMDA Y27 Anode Pin Output

THERMDC Y28 Cathode Pin Output

Reserved AC1 Reserved Reserved

Reserved AD1 Reserved Reserved

SMB_PRT AE4 Ground VSS

Reserved AE15 Reserved Reserved

Reserved AE16 Reserved Reserved

RESET# Y8 Co mm o n Clk Input

RS0# E21 Common Clk Input

RS1# D22 Comm o n Clk Input

RS2# F21 Common Clk Input

RSP# C6 Commo n Clk Input

SKTOCC# A3 Power/Other Output

SLP# AE6 As ync GTL+ Input

NC AD28 Reserved

NC AC28 Reserved

NC AC29 Reserved

NC AA29 Reserved

NC AB29 Reserved

NC AB28 Reserved

NC AA28 Reserved

NC Y29 Reserved

NC AE28 Reserved

NC AE29 Reserved

NC AD29 Reserved

SMI# C27 Async GTL+ Input

STPCLK# D4 Async GTL+ Input

TCK E24 TAP Input

TDI C24 TAP Input

TDO E25 TAP Output

TESTHI0 W6 Power/Other Input

TESTHI1 W7 Power/Other Input

TESTHI2 W8 Power/Other Input

TESTHI3 Y6 Power/Other Input

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

44 Datasheet

TESTHI4 AA7 Power/Other Input

TESTHI5 AD5 Power/Other Input

TESTHI6 AE5 Power/Other Input

THERMTRIP# F26 Async GTL+ Output

TMS A25 TAP Input

TRDY# E19 Common Clk Input

TRST# F24 TAP Input

VCC A2 Power/Other

VCC A8 Power/Other

VCC A14 Power/Other

VCC A18 Power/Other

VCC A24 Power/Other

VCC A28 Power/Other

VCC A30 Power/Other

VCC B4 Power/Other

VCC B6 Power/Other

VCC B12 Power/Other

VCC B20 Power/Other

VCC B26 Power/Other

VCC B29 Power/Other

VCC B31 Power/Other

VCC C2 Power/Other

VCC C4 Power/Other

VCC C10 Power/Other

VCC C16 Power/Other

VCC C22 Power/Other

VCC C28 Power/Other

VCC C30 Power/Other

VCC D1 Power/Other

VCC D8 Power/Other

VCC D14 Power/Other

VCC D18 Power/Other

VCC D24 Power/Other

VCC D29 Power/Other

VCC D31 Power/Other

VCC E2 Power/Other

VCC E6 Power/Other

VCC E12 Power/Other

VCC E20 Power/Other

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

VCC E26 Power/Other

VCC E28 Power/Other

VCC E30 Power/Other

VCC F1 Power/Other

VCC F4 Power/Other

VCC F10 Power/Other

VCC F16 Power/Other

VCC F22 Power/Other

VCC F29 Power/Other

VCC F31 Power/Other

VCC G2 Power/Other

VCC G4 Power/Other

VCC G6 Power/Other

VCC G8 Power/Other

VCC G24 Power/Other

VCC G26 Power/Other

VCC G28 Power/Other

VCC G30 Power/Other

VCC H1 Power/Other

VCC H3 Power/Other

VCC H5 Power/Other

VCC H7 Power/Other

VCC H9 Power/Other

VCC H23 Power/Other

VCC H25 Power/Other

VCC H27 Power/Other

VCC H29 Power/Other

VCC H31 Power/Other

VCC J2 Power/Other

VCC J4 Power/Other

VCC J6 Power/Other

VCC J8 Power/Other

VCC J24 Power/Other

VCC J26 Power/Other

VCC J28 Power/Other

VCC J30 Power/Other

VCC K1 Power/Other

VCC K3 Power/Other

VCC K5 Power/Other

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel® X eon™ Processor with 5 33MHz Front Side Bus

Datasheet 45

VCC K7 Power/Other

VCC K9 Power/Other

VCC K23 Power/Other

VCC K25 Power/Other

VCC K27 Power/Other

VCC K29 Power/Other

VCC K31 Power/Other

VCC L2 Power/Other

VCC L4 Power/Other

VCC L6 Power/Other

VCC L8 Power/Other

VCC L24 Power/Other

VCC L26 Power/Other

VCC L28 Power/Other

VCC L30 Power/Other

VCC M1 Power/Other

VCC M3 Power/Other

VCC M5 Power/Other

VCC M7 Power/Other

VCC M9 Power/Other

VCC M23 Power/Other

VCC M25 Power/Other

VCC M27 Power/Other

VCC M29 Power/Other

VCC M31 Power/Other

VCC N1 Power/Other

VCC N3 Power/Other

VCC N5 Power/Other

VCC N7 Power/Other

VCC N9 Power/Other

VCC N23 Power/Other

VCC N25 Power/Other

VCC N27 Power/Other

VCC N29 Power/Other

VCC N31 Power/Other

VCC P2 Power/Other

VCC P4 Power/Other

VCC P6 Power/Other

VCC P8 Power/Other

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

VCC P24 Power/Other

VCC P26 Power/Other

VCC P28 Power/Other

VCC P30 Power/Other

VCC R1 Power/Other

VCC R3 Power/Other

VCC R5 Power/Other

VCC R7 Power/Other

VCC R9 Power/Other

VCC R23 Power/Other

VCC R25 Power/Other

VCC R27 Power/Other

VCC R29 Power/Other

VCC R31 Power/Other

VCC T2 Power/Other

VCC T4 Power/Other

VCC T6 Power/Other

VCC T8 Power/Other

VCC T24 Power/Other

VCC T26 Power/Other

VCC T28 Power/Other

VCC T30 Power/Other

VCC U1 Power/Other

VCC U3 Power/Other

VCC U5 Power/Other

VCC U7 Power/Other

VCC U9 Power/Other

VCC U23 Power/Other

VCC U25 Power/Other

VCC U27 Power/Other

VCC U29 Power/Other

VCC U31 Power/Other

VCC V2 Power/Other

VCC V4 Power/Other

VCC V6 Power/Other

VCC V8 Power/Other

VCC V24 Power/Other

VCC V26 Power/Other

VCC V28 Power/Other

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

46 Datasheet

VCC V30 Power/Other

VCC W1 Power/Other

VCC W25 Power/Other

VCC W27 Power/Other

VCC W29 Power/Other

VCC W31 Power/Other

VCC Y10 Power/Other

VCC Y16 Power/Other

VCC Y2 Power/Other

VCC Y22 Power/Other

VCC Y30 Power/Other

VCC AA1 Power/Other

VCC AA4 Power/Other

VCC AA6 Power/Other

VCC AA12 Power/Other

VCC AA20 Power/Other

VCC AA26 Power/Other

VCC AA31 Power/Other

VCC AB2 Power/Other

VCC AB8 Power/Other

VCC AB14 Power/Other

VCC AB18 Power/Other

VCC AB24 Power/Other

VCC AB30 Power/Other

VCC AC3 Power/Other

VCC AC4 Power/Other

VCC AC10 Power/Other

VCC AC16 Power/Other

VCC AC22 Power/Other

VCC AC31 Power/Other

VCC AD2 Power/Other

VCC AD6 Power/Other

VCC AD12 Power/Other

VCC AD20 Power/Other

VCC AD26 Power/Other

VCC AD30 Power/Other

VCC AE3 Power/Other

VCC AE8 Power/Other

VCC AE14 Power/Other

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

VCC AE18 Power/Other

VCC AE24 Power/Other

VCCA AB4 Power/Other Input

VCCIOPLL AD4 Power/Other Input

VCCSENSE B27 Power/Other Output

VID0 F3 Power/Other Output

VID1 E3 Power/Other Output

VID2 D3 Power/Other Output

VID3 C3 Power/Other Output

VID4 B3 Power/Other Output

VSS A5 Power/Other

VSS A11 Power/Other

VSS A21 Power/Other

VSS A27 Power/Other

VSS A29 Power/Other

VSS A31 Power/Other

VSS B2 Power/Other

VSS B9 Power/Other

VSS B15 Power/Other

VSS B17 Power/Other

VSS B23 Power/Other

VSS B28 Power/Other

VSS B30 Power/Other

VSS C1 Power/Other

VSS C7 Power/Other

VSS C13 Power/Other

VSS C19 Power/Other

VSS C25 Power/Other

VSS C29 Power/Other

VSS C31 Power/Other

VSS D2 Power/Other

VSS D5 Power/Other

VSS D11 Power/Other

VSS D21 Power/Other

VSS D27 Power/Other

VSS D28 Power/Other

VSS D30 Power/Other

VSS E1 Power/Other

VSS E9 Power/Other

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel® X eon™ Processor with 5 33MHz Front Side Bus

Datasheet 47

VSS E15 Power/Other

VSS E17 Power/Other

VSS E23 Power/Other

VSS E29 Power/Other

VSS E31 Power/Other

VSS F2 Power/Other

VSS F7 Power/Other

VSS F13 Power/Other

VSS F19 Power/Other

VSS F25 Power/Other

VSS F28 Power/Other

VSS F30 Power/Other

VSS G1 Power/Other

VSS G3 Power/Other

VSS G5 Power/Other

VSS G7 Power/Other

VSS G9 Power/Other

VSS G25 Power/Other

VSS G27 Power/Other

VSS G29 Power/Other

VSS G31 Power/Other

VSS H2 Power/Other

VSS H4 Power/Other

VSS H6 Power/Other

VSS H8 Power/Other

VSS H24 Power/Other

VSS H26 Power/Other

VSS H28 Power/Other

VSS H30 Power/Other

VSS J1 Power/Other

VSS J3 Power/Other

VSS J5 Power/Other

VSS J7 Power/Other

VSS J9 Power/Other

VSS J23 Power/Other

VSS J25 Power/Other

VSS J27 Power/Other

VSS J29 Power/Other

VSS J31 Power/Other

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

VSS K2 Power/Other

VSS K4 Power/Other

VSS K6 Power/Other

VSS K8 Power/Other

VSS K24 Power/Other

VSS K26 Power/Other

VSS K28 Power/Other

VSS K30 Power/Other

VSS L1 Power/Other

VSS L3 Power/Other

VSS L5 Power/Other

VSS L7 Power/Other

VSS L9 Power/Other

VSS L23 Power/Other

VSS L25 Power/Other

VSS L27 Power/Other

VSS L29 Power/Other

VSS L31 Power/Other

VSS M2 Power/Other

VSS M4 Power/Other

VSS M6 Power/Other

VSS M8 Power/Other

VSS M24 Power/Other

VSS M26 Power/Other

VSS M28 Power/Other

VSS M30 Power/Other

VSS N2 Power/Other

VSS N4 Power/Other

VSS N6 Power/Other

VSS N8 Power/Other

VSS N24 Power/Other

VSS N26 Power/Other

VSS N28 Power/Other

VSS N30 Power/Other

VSS P1 Power/Other

VSS P3 Power/Other

VSS P5 Power/Other

VSS P7 Power/Other

VSS P9 Power/Other

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

48 Datasheet

VSS P23 Power/Other

VSS P25 Power/Other

VSS P27 Power/Other

VSS P29 Power/Other

VSS P31 Power/Other

VSS R2 Power/Other

VSS R4 Power/Other

VSS R6 Power/Other

VSS R8 Power/Other

VSS R24 Power/Other

VSS R26 Power/Other

VSS R28 Power/Other

VSS R30 Power/Other

VSS T1 Power/Other

VSS T3 Power/Other

VSS T5 Power/Other

VSS T7 Power/Other

VSS T9 Power/Other

VSS T23 Power/Other

VSS T25 Power/Other

VSS T27 Power/Other

VSS T29 Power/Other

VSS T31 Power/Other

VSS U2 Power/Other

VSS U4 Power/Other

VSS U6 Power/Other

VSS U8 Power/Other

VSS U24 Power/Other

VSS U26 Power/Other

VSS U28 Power/Other

VSS U30 Power/Other

VSS V1 Power/Other

VSS V3 Power/Other

VSS V5 Power/Other

VSS V7 Power/Other

VSS V9 Power/Other

VSS V23 Power/Other

VSS V25 Power/Other

VSS V27 Power/Other

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

VSS V29 Power/Other

VSS V31 Power/Other

VSS W2 Power/Other

VSS W4 Power/Other

VSS W24 Power/Other

VSS W26 Power/Other

VSS W28 Power/Other

VSS W30 Power/Other

VSS Y1 Power/Other

VSS Y5 Power/Other

VSS Y7 Power/Other

VSS Y13 Power/Other

VSS Y19 Power/Other

VSS Y25 Power/Other

VSS Y31 Power/Other

VSS AA2 Power/Other

VSS AA9 Power/Other

VSS AA15 Power/Other

VSS AA17 Power/Other

VSS AA23 Power/Other

VSS AA30 Power/Other

VSS AB1 Power/Other

VSS AB5 Power/Other

VSS AB11 Power/Other

VSS AB21 Power/Other

VSS AB27 Power/Other

VSS AB31 Power/Other

VSS AC2 Power/Other

VSS AC7 Power/Other

VSS AC13 Power/Other

VSS AC19 Power/Other

VSS AC25 Power/Other

VSS AC30 Power/Other

VSS AD3 Power/Other

VSS AD9 Power/Other

VSS AD15 Power/Other

VSS AD17 Power/Other

VSS AD23 Power/Other

VSS AD31 Power/Other

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel® Xeon™ Processor with 5 33MH z Front Si de Bus

Datasheet 49

1. In systems utilizing the Intel Xeon processor, the system

designer must pull-up these signals to the processor VCC

2. Baseboard treating AA3 and AB3 as Reserved will operate

correctly with a bus clock of 133 MHz.

VSS AE2 Power/Other

VSS AE11 Power/Other

VSS AE21 Power/Other

VSS AE27 Power/Other

VSSA AA5 Power/Other Input

Table 38. Pin Listing by Pin Name

Pin Nam e Pin No. Signal

Buffe r Type Direction

VSSSENSE D26 Power/Other Output

Table 38. Pin Li sting by Pin Name

Pin Name Pin No. Signal

Buffer Type Direction

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

50 Datasheet

4.1.2 Pin Listing by Pin Number

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

A1 Reserved Reserved Reserved

A2 VCC Power/Other

A3 SKTOCC# Power/Other Output

A4 Reserved Reserved Reserved

A5 VSS Power/Other

A6 A32# Source Sync Input/Output

A7 A33# Source Sync Input/Output

A8 VCC Power/Other

A9 A26# Source Sync Input/Output

A10 A20# Source Sync Input/Output

A11 VSS Power/Other

A12 A14# Source Sync Input/Output

A13 A10# Source Sync Input/Output

A14 VCC Power/Other

A15 Reserved Reserved Reserved

A16 Reserved Reserved Reserved

A17 LOCK# Com m on Clk Input/Output

A18 VCC Power/Other

A19 A7# Source Sync Input/Output

A20 A4# Source Sync Input/Output

A21 VSS Power/Other

A22 A3# Source Sync Input/Output

A23 HITM# Common Clk Input/Output

A24 VCC Power/Other

A25 TMS TAP Input

A26 Reserved Reserved Reserved

A27 VSS Power/Other

A28 VCC Power/Other

A29 VSS Power/Other

A30 VCC Power/Other

A31 VSS Power/Other

B1 Reserved Reserved Reserved

B2 VSS Power/Other

B3 VID4 Power/Other Output

B4 VCC Power/Other

B5 OTDEN Power/Other Input

B6 VCC Power/Other

B7 A31# Source Sync Input/Output

B8 A27# Source Sync Input/Output

B9 VSS Power/Other

B10 A21# Source Sync Input/Output

B11 A22# Source Sync Input/Output

B12 VCC Power/Other

B13 A13# Source Sync Input/Output

B14 A12# Source Sync Input/Output

B15 VSS Power/Other

B16 A11# Source Sync Input/Output

B17 VSS Power/Other

B18 A5# S ource Sync Input/Output

B19 REQ0# Common Clk Input/Output

B20 VCC Power/Other

B21 REQ1# Common Clk Input/Output

B22 REQ4# Common Clk Input/Output

B23 VSS Power/Other

B24 LINT0 Async GTL+ Input

B25 PROCHOT# Power/Other Output

B26 VCC Power/Other

B27 VCCSENSE Power/Other Output

B28 VSS Power/Other

B29 VCC Power/Other

B30 VSS Power/Other

B31 VCC Power/Other

C1 VSS Power/Other

C2 VCC Power/Other

C3 VID3 Power/Other Output

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

Intel® Xeon™ Processor with 5 33MH z Front Si de Bus

Datasheet 51

C4 VCC Power/Other

C5 Reserved Reserved Reserved

C6 RSP# Common Clk Input

C7 VSS Power/Other

C8 A35# Source Sync Input/Output

C9 A34# Source Sync Input/Output

C10 VCC Power/Other

C11 A30# Source Sync Input/Output

C12 A23# Source Sync Input/Output

C13 VSS Power/Other

C14 A16# Source Sync Input/Output

C15 A15# Source Sync Input/Output

C16 VCC Power/Other

C17 A8# Source Sync Input/Output

C18 A6# Source Sync Input/Output

C19 VSS Power/Other

C20 REQ3# Comm on Clk Input/Output

C21 REQ2# Comm on Clk Input/Output

C22 VCC Power/Other

C23 DEFER# Com m on Clk Input

C24 TDI TAP Input

C25 VSS Power/Other Input

C26 IGNNE# Async GTL+ Input

C27 SMI# Async GTL+ Input

C28 VCC Power/Other

C29 VSS Power/Other

C30 VCC Power/Other

C31 VSS Power/Other

D1 VCC Power/Other

D2 VSS Power/Other

D3 VID2 Power/Other Output

D4 STPCLK# Async GTL+ Input

D5 VSS Power/Other

D6 INIT# Async GTL+ Input

D7 MCERR# Comm on Clk Input/Output

D8 VCC Power/Other

D9 AP1# Comm on Clk Input/Output

D10 BR3# 1Comm on Clk Input

D11 VSS Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

D12 A29# Source Sync Input/Output

D13 A25# Source Sync Input/Output

D14 VCC Power/Other

D15 A18# Source Sync Input/Output

D16 A17# Source Sync Input/Output

D17 A9# Source Sync Input/Output

D18 VCC Power/Other

D19 ADS# Common

Clk Input/Output

D20 BR0# Common

Clk Input/Output

D21 VSS Power/Other

D22 RS1# Common Clk Input

D23 BPRI# Common Clk Input

D24 VCC Power/Other

D25 Reserved Reserved Reserved

D26 VSSSENSE Power/Other Output

D27 VSS Power/Other

D28 VSS Power/Other

D29 VCC Power/Other

D30 VSS Power/Other

D31 VCC Power/Other

E1 VSS Power/Other

E2 VCC Power/Other

E3 VID1 Power/Other Output

E4 BPM5# Common Clk Input/Output

E5 IERR# Common Clk Output

E6 VCC Power/Other

E7 BPM2# Common Clk Input/Output

E8 BPM4# Common Clk Input/Output

E9 VSS Power/Other

E10 AP0# Common Clk Input/Output

E11 BR2# 1Common Clk Input

E12 VCC Power/Other

E13 A28# Source Sync Input/Output

E14 A24# Source Sync Input/Output

E15 VSS Power/Other

E16 COMP1 Power/Other Input

E17 VSS Power/Other

E18 DRDY# Common Clk Input/Output

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

52 Datasheet

E19 TRDY# Com m on Clk Input

E20 VCC Power/Other

E21 RS0# Com m on Clk Input

E22 HIT# Comm on Clk Input/Output

E23 VSS Power/Other

E24 TCK TAP Input

E25 TDO TAP Output

E26 VCC Power/Other

E27 FERR# Async GTL+ Output

E28 VCC Power/Other

E29 VSS Power/Other

E30 VCC Power/Other

E31 VSS Power/Other

F1 VCC Power/Other

F2 VSS Power/Other

F3 VID0 Power/Other Output

F4 VCC Power/Other

F5 BPM3# Com m on Clk Input/Output

F6 BPM0# Com m on Clk Input/Output

F7 VSS Power/Other

F8 BPM1# Com m on Clk Input/Output

F9 GTLREF Power/Other Input

F10 VCC Power/Other

F11 BINIT# Comm on Clk Input/Output

F12 BR1# Comm on Clk Input

F13 VSS Power/Other

F14 ADSTB1# Source Sync Input/Output

F15 A19# Source Sync Input/Output

F16 VCC Power/Other

F17 ADSTB0# Source Sync Input/Output

F18 DBSY# Comm on Clk Input/Output

F19 VSS Power/Other

F20 BNR# Comm on Clk Input/Output

F21 RS2# Comm on Clk Input

F22 VCC Power/Other

F23 GTLREF Power/Other Input

F24 TRST# TAP Input

F25 VSS Power/Other

F26 THERMTRIP

#Async GTL+ Output

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

F27 A20M# Async GTL+ Input

F28 VSS Power/Other

F29 VCC Power/Other

F30 VSS Power/Other

F31 VCC Power/Other

G1 VSS Power/Other

G2 VCC Power/Other

G3 VSS Power/Other

G4 VCC Power/Other

G5 VSS Power/Other

G6 VCC Power/Other

G7 VSS Power/Other

G8 VCC Power/Other

G9 VSS Power/Other

G23 LINT1 Async GTL+ Input

G24 VCC Power/Other

G25 VSS Power/Other

G26 VCC Power/Other

G27 VSS Power/Other

G28 VCC Power/Other

G29 VSS Power/Other

G30 VCC Power/Other

G31 VSS Power/Other

H1 VCC Power/Other

H2 VSS Power/Other

H3 VCC Power/Other

H4 VSS Power/Other

H5 VCC Power/Other

H6 VSS Power/Other

H7 VCC Power/Other

H8 VSS Power/Other

H9 VCC Power/Other

H23 VCC Power/Other

H24 VSS Power/Other

H25 VCC Power/Other

H26 VSS Power/Other

H27 VCC Power/Other

H28 VSS Power/Other

H29 VCC Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

Intel® Xeon™ Processor with 5 33MH z Front Si de Bus

Datasheet 53

H30 VSS Power/Other

H31 VCC Power/Other

J1 VSS Power/Other

J2 VCC Power/Other

J3 VSS Power/Other

J4 VCC Power/Other

J5 VSS Power/Other

J6 VCC Power/Other

J7 VSS Power/Other

J8 VCC Power/Other

J9 VSS Power/Other

J23 VSS Power/Other

J24 VCC Power/Other

J25 VSS Power/Other

J26 VCC Power/Other

J27 VSS Power/Other

J28 VCC Power/Other

J29 VSS Power/Other

J30 VCC Power/Other

J31 VSS Power/Other

K1 VCC Power/Other

K2 VSS Power/Other

K3 VCC Power/Other

K4 VSS Power/Other

K5 VCC Power/Other

K6 VSS Power/Other

K7 VCC Power/Other

K8 VSS Power/Other

K9 VCC Power/Other

K23 VCC Power/Other

K24 VSS Power/Other

K25 VCC Power/Other

K26 VSS Power/Other

K27 VCC Power/Other

K28 VSS Power/Other

K29 VCC Power/Other

K30 VSS Power/Other

K31 VCC Power/Other

L1 VSS Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

L2 VCC Power/Other

L3 VSS Power/Other

L4 VCC Power/Other

L5 VSS Power/Other

L6 VCC Power/Other

L7 VSS Power/Other

L8 VCC Power/Other

L9 VSS Power/Other

L23 VSS Power/Other

L24 VCC Power/Other

L25 VSS Power/Other

L26 VCC Power/Other

L27 VSS Power/Other

L28 VCC Power/Other

L29 VSS Power/Other

L30 VCC Power/Other

L31 VSS Power/Other

M1 VCC Power/Other

M2 VSS Power/Other

M3 VCC Power/Other

M4 VSS Power/Other

M5 VCC Power/Other

M6 VSS Power/Other

M7 VCC Power/Other

M8 VSS Power/Other

M9 VCC Power/Other

M23 VCC Power/Other

M24 VSS Power/Other

M25 VCC Power/Other

M26 VSS Power/Other

M27 VCC Power/Other

M28 VSS Power/Other

M29 VCC Power/Other

M30 VSS Power/Other

M31 VCC Power/Other

N1 VCC Power/Other

N2 VSS Power/Other

N3 VCC Power/Other

N4 VSS Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

54 Datasheet

N5 VCC Power/Other

N6 VSS Power/Other

N7 VCC Power/Other

N8 VSS Power/Other

N9 VCC Power/Other

N23 VCC Power/Other

N24 VSS Power/Other

N25 VCC Power/Other

N26 VSS Power/Other

N27 VCC Power/Other

N28 VSS Power/Other

N29 VCC Power/Other

N30 VSS Power/Other

N31 VCC Power/Other

P1 VSS Power/Other

P2 VCC Power/Other

P3 VSS Power/Other

P4 VCC Power/Other

P5 VSS Power/Other

P6 VCC Power/Other

P7 VSS Power/Other

P8 VCC Power/Other

P9 VSS Power/Other

P23 VSS Power/Other

P24 VCC Power/Other

P25 VSS Power/Other

P26 VCC Power/Other

P27 VSS Power/Other

P28 VCC Power/Other

P29 VSS Power/Other

P30 VCC Power/Other

P31 VSS Power/Other

R1 VCC Power/Other

R2 VSS Power/Other

R3 VCC Power/Other

R4 VSS Power/Other

R5 VCC Power/Other

R6 VSS Power/Other

R7 VCC Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

R8 VSS Power/Other

R9 VCC Power/Other

R23 VCC Power/Other

R24 VSS Power/Other

R25 VCC Power/Other

R26 VSS Power/Other

R27 VCC Power/Other

R28 VSS Power/Other

R29 VCC Power/Other

R30 VSS Power/Other

R31 VCC Power/Other

T1 VSS Power/Other

T2 VCC Power/Other

T3 VSS Power/Other

T4 VCC Power/Other

T5 VSS Power/Other

T6 VCC Power/Other

T7 VSS Power/Other

T8 VCC Power/Other

T9 VSS Power/Other

T23 VSS Power/Other

T24 VCC Power/Other

T25 VSS Power/Other

T26 VCC Power/Other

T27 VSS Power/Other

T28 VCC Power/Other

T29 VSS Power/Other

T30 VCC Power/Other

T31 VSS Power/Other

U1 VCC Power/Other

U2 VSS Power/Other

U3 VCC Power/Other

U4 VSS Power/Other

U5 VCC Power/Other

U6 VSS Power/Other

U7 VCC Power/Other

U8 VSS Power/Other

U9 VCC Power/Other

U23 VCC Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

Intel® Xeon™ Processor with 5 33MH z Front Si de Bus

Datasheet 55

U24 VSS Power/Other

U25 VCC Power/Other

U26 VSS Power/Other

U27 VCC Power/Other

U28 VSS Power/Other

U29 VCC Power/Other

U30 VSS Power/Other

U31 VCC Power/Other

V1 VSS Power/Other

V2 VCC Power/Other

V3 VSS Power/Other

V4 VCC Power/Other

V5 VSS Power/Other

V6 VCC Power/Other

V7 VSS Power/Other

V8 VCC Power/Other

V9 VSS Power/Other

V23 VSS Power/Other

V24 VCC Power/Other

V25 VSS Power/Other

V26 VCC Power/Other

V27 VSS Power/Other

V28 VCC Power/Other

V29 VSS Power/Other

V30 VCC Power/Other

V31 VSS Power/Other

W1 VCC Power/Other

W2 VSS Power/Other

W3 Reserved Reserved Reserved

W4 VSS Power/Other

W5 BCLK1 Sys Bus Clk Input

W6 TESTHI0 Power/Other Input

W7 TESTHI1 Power/Other Input

W8 TESTHI2 Power/Other Input

W9 GTLREF Power/Other Input

W23 GTLREF Power/Other Input

W24 VSS Power/Other

W25 VCC Power/Other

W26 VSS Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

W27 VCC Power/Other

W28 VSS Power/Other

W29 VCC Power/Other

W30 VSS Power/Other

W31 VCC Power/Other

Y1 VSS Power/Other

Y2 VCC Power/Other

Y3 Reserved Reserved Reserved

Y4 BCLK0 Sys Bus Clk Input

Y5 VSS Power/Other

Y6 TESTHI3 Power/Other Input

Y7 VSS Power/Other

Y8 RESET# Common Clk Input

Y9 D62# Source Sync Input/Output

Y10 VCC Power/Other

Y11 DSTBP3# Source Sync Input/Output

Y12 DSTBN3# Source Sync Input/Output

Y13 VSS Power/Other

Y14 DSTBP2# Source Sync Input/Output

Y15 DSTBN2# Source Sync Input/Output

Y16 VCC Power/Other

Y17 DSTBP1# Source Sync Input/Output

Y18 DSTBN1# Source Sync Input/Output

Y19 VSS Power/Other

Y20 DSTBP0# Source Sync Input/Output

Y21 DSTBN0# Source Sync Input/Output

Y22 VCC Power/Other

Y23 D5# Source Sync Input/Output

Y24 D2# Source Sync Input/Output

Y25 VSS Power/Other

Y26 D0# Source Sync Input/Output

Y27 THERMDA Anode Pin Output

Y28 THERMDC Cathode Pin Output

Y29 NC Reserved

Y30 VCC Power/Other

Y31 VSS Power/Other

AA1 VCC Power/Other

AA2 VSS Power/Other

AA3 BSEL0 Power/Other Output2

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

Intel ® Xeon™ Processor with 53 3MH z Front Side Bus

56 Datasheet

AA4 VCC Power/Other

AA5 VSSA Power/Other Input

AA6 VCC Power/Other

AA7 TESTHI4 Power/Other Input

AA8 D61# Source Sync Input/Output

AA9 VSS Power/Other

AA10 D54# Source Sync Input/Output

AA11 D53# Source Sync Input/Output

AA12 VCC Power/Other

AA13 D48# Source Sync Input/Output

AA14 D49# Source Sync Input/Output

AA15 VSS Power/Other

AA16 D33# Source Sync Input/Output

AA17 VSS Power/Other

AA18 D24# Source Sync Input/Output

AA19 D15# Source Sync Input/Output

AA20 VCC Power/Other

AA21 D 11# Source Sync Input/Output

AA22 D10# Source Sync Input/Output

AA23 VSS Power/Other

AA24 D6# Source Sync Input/Output

AA25 D3# Source Sync Input/Output

AA26 VCC Power/Other

AA27 D1# Source Sync Input/Output

AA28 NC Reserved

AA29 NC Reserved

AA30 VSS Power/Other

AA31 VCC Power/Other

AB1 VSS Power/Other

AB2 VCC Power/Other

AB3 BSEL1 Power/Other Output2

AB4 VCCA Power/Other Input

AB5 VSS Power/Other

AB6 D63# Source Sync

AB7 PWRGOOD Power/Other Input

AB8 VCC Power/Other

AB9 DBI3# Source Sync Input/Output

AB10 D55# Source Sync Input/Output

AB11 VSS Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

AB12 D51# Source Sync Input/Output

AB13 D52# Source Sync Input/Output

AB14 VCC Power/Other

AB15 D37# Source Sync Input/Output

AB16 D32# Source Sync Input/Output

AB17 D31# Source Sync Input/Output

AB18 VCC Power/Other

AB19 D14# Source Sync Input/Output

AB20 D12# Source Sync Input/Output

AB21 VSS Power/Other

AB22 D13# Source Sync Input/Output

AB23 D9# Source Sync Input/Output

AB24 VCC Power/Other

AB25 D8# Source Sync Input/Output

AB26 D7# Source Sync Input/Output

AB27 VSS Power/Other

AB28 NC Reserved

AB29 NC Reserved

AB30 VCC Power/Other

AB31 VSS Power/Other

AC1 Reserved Reserved Reserved

AC2 VSS Power/Other

AC3 VCC Power/Other

AC4 VCC Power/Other

AC5 D60# Source Sync Input/Output

AC6 D59# Source Sync Input/Output

AC7 VSS Power/Other

AC8 D56# Source Sync Input/Output

AC9 D47# Source Sync Input/Output

AC10 VCC Power/Other

AC11 D43# S ource Sync Input/Output

AC12 D41# Source Sync Input/Output

AC13 VSS Power/Other

AC14 D50# Source Sync Input/Output

AC15 DP2# Common Clk Input/Output

AC16 VCC Power/Other

AC17 D34# Source Sync Input/Output

AC18 DP0# Common Clk Input/Output

AC19 VSS Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

Intel® Xeon™ Processor with 5 33MH z Front Si de Bus

Datasheet 57

1. In systems utilizing the Intel Xeon processor, the system

designer must pull-up these signals to the processor VCC.

2. Baseboards treating AA3 and AB3 as Reserved will operate

correctly with a bus clock of 133 MHz.

AC20 D25# Source Sync Input/Output

AC21 D26# Source Sync Input/Output

AC22 VCC Power/Other

AC23 D23# Source Sync Input/Output

AC24 D20# Source Sync Input/Output

AC25 VSS Power/Other

AC26 D17# Source Sync Input/Output

AC27 DBI0# Source Sync Input/Output

AC28 NC Reserved

AC29 NC Reserved

AC30 VSS Power/Other

AC31 VCC Power/Other

AD1 Reserved Reserved Reserved

AD2 VCC Power/Other

AD3 VSS Power/Other

AD4 VCCIOPLL Power/Other Input

AD5 TESTHI5 Power/Other Input

AD6 VCC Power/Other

AD7 D57# Source Sync Input/Output

AD8 D46# Source Sync Input/Output

AD9 VSS Power/Other

AD10 D45# Source Sync Input/Output

AD11 D40# Source Sync Input/Output

AD12 VCC Power/Other

AD13 D38# Source Sync Input/Output

AD14 D39# Source Sync Input/Output

AD15 VSS Power/Other

AD16 COMP0 Power/Other Input

AD17 VSS Power/Other

AD18 D36# Source Sync Input/Output

AD19 D30# Source Sync Input/Output

AD20 VCC Power/Other

AD21 D29# Source Sync Input/Output

AD22 DBI1# Source Sync Input/Output

AD23 VSS Power/Other

AD24 D21# Source Sync Input/Output

AD25 D18# Source Sync Input/Output

AD26 VCC Power/Other

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buff er Type Direction

AD27 D4# Source Sync Input/Output

AD28 NC Reserved

AD29 NC Reserved

AD30 VCC Power/Other

AD31 VSS Power/Other

AE2 VSS Power/Other

AE3 VCC Power/Other

AE4 SMD_PRT Ground Output

AE5 TESTHI6 Power/Other Input

AE6 SLP# Async GTL+ Input

AE7 D58# Source Sync Input/Output

AE8 VCC Power/Other

AE9 D44# Source Sync Input/Output

AE10 D42# Source Sync Input/Output

AE11 VSS Power/Other

AE12 DBI2# Source Sync Input/Output

AE13 D35# Source Sync Input/Output

AE14 VCC Power/Other

AE15 Reserved Reserved Reserved

AE16 Reserved Reserved Reserved

AE17 DP3# Common Clk Input/Output

AE18 VCC Power/Other

AE19 DP1# Common Clk Input/Output

AE20 D28# Source Sync Input/Output

AE21 VSS Power/Other

AE22 D27# Source Sync Input/Output

AE23 D22# Source Sync Input/Output

AE24 VCC Power/Other

AE25 D19# Source Sync Input/Output

AE26 D16# Source Sync Input/Output

AE27 VSS Power/Other

AE28 VID_VCC Power/Other

AE29 VID_VCC Power/Other

AE30 Mechanical

Key

Table 39. Pin Listing by Pin Number

Pin No. Pin Name Signal

Buffer Type Direction

58 Int el ® Xeon™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3.06 GHz

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Int el ® Xeon™ Pr oces so r with 533 MHz Fr ont Side B us at 2 GH z t o 3.06 GHz 59

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60 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

4.2 Signal Definition s

Table 41. Signal Definitions (Sheet 1 of 9)

Name Type Description Notes

A[35:3]# I/O

A[35:3]# (Addr ess) defi ne a 236 byte physical m emory addr ess spa ce. In sub-phas e

1 of the address phase, these pins transmit the address of a transaction. In sub-

phase 2, these pins transmit transaction type information. These signals must

connect the appropriate pins of all agents on the front side bus. A[35:3]# are

protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and

are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset of

the A[35:3]# pins to determine their power-on configuration. See Section 6.1.

A20M# I

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit

20 (A20#) before looking up a line in any internal cache and before driving a read/

write transaction on the bus. Asserting A20M# emulates the 8086 processor’s

address wrap-around at the 1 MByte boundary. Assertion of A20M# is only

supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

ADS# I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin

parity checking, protocol checking, address decode, internal snoop, or deferred

reply ID match operations associated with the new transaction. This signal must

connect the appropriate pins on all front side bus agents.

ADSTB[1:0]# I/O Address strobes are used to latch A[35:3]# and REQ[4:0]# on their ri sing and falli ng

edge. 4

AP[1:0]# I/O

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,

A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is

high if an even number of covered signals are low and low if an odd number of

covered signals are low. This allows parity to be high when all the covered signals

are high. AP[1:0]# should connect the appropriate pins of all front side bus agents.

The following table defines the coverage model of these signals.

BCLK[1:0] I

The differential pair BCLK (Bus Clock) determines the bus frequency. All processor

front side bus agents must receive these signals to drive their outputs and latch

their inputs.

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing the falling edge of BCLK1.

Request Signals Subphase 1 Subphase 2

A[35:24]# AP0# AP1#

A[23:3]# AP1# AP0#

REQ[4:0]# AP1# AP0#

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 61

BINIT# I/O

BINIT# (Bus Initialization) may be observed and driven by all processor front side

bus agents and if used, must connect the appropriate pins of all such agents. If the

BINIT# driver is enabled during po wer on confi gur ation, BINIT# i s asserted to s ignal

any bus condition that prevents reliable future information.

If BINIT# observation is enabled during power-on configuration (see Section 6.1)

and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity

and bus request arbitration state machines. The bus agents do not reset their IOQ

and transaction tracking state machines upon observation of BINIT# assertion.

Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for

the front side bus and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is disabled during power-on configuration, a central agent

may handle an assertion of BINIT# as appropriate to the error handling architecture

of the system.

BNR# I/O

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is

unable to accept new bus transactions. During a bus stall, the current bus owner

cannot issue any new transactions.

Since multiple agents might need to request a bus stall at the same time, BNR# is a

wire-OR signal which must connect the appropriate pins of all processor front side

bus agents. In order to avoid wire-OR glitches associated with simultaneous edge

transitio ns driven by multi ple driver s , BNR# is activated on speci fic clock edges and

sampled on specific clock edges.

BPM[5:0]# I/O

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.

They are outputs from the processor which indicate the status of breakpoints and

programmable counters used for monitoring processor performance. BPM[5:0]#

should connect the appropriate pins of all front side bus agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a

processor output used by debug tools to determine processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is

used by debug tools to request debug operation of the processors.

BPM[5:4]# must be bussed to all bus agents.

These signals do not have on-die termination and must be t erminated at the

end agent. See the appropriate platform design guidelines for additional

information.

BPRI# I

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

front side bus. It must connect the appropriate pins of all processor front side bus

agents. Observing BPRI# active (as asserted by the priority agent) causes all other

agents to stop issuing new requests, unless such requests are part of an ongoing

locked operation. The priority agent keeps BPRI# asserted until all of its requests

are completed, then releases the bus by deasserting BPRI#.

Ta b le 41 . Signal Defin itions (Sheet 2 of 9)

Name Type Description Notes

62 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

BR0#

BR[1:3]#1I/O

BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The

BREQ[3:0]# signals are interconnected in a rotating manner to individual processor

pins. BR2# and BR3# must not be utilized in a dual processor platform design. The

table below gives the rotating interconnect between the processor and bus signals

for dual processor systems.

During power-on configuration, the central agent must assert the BR0# bus signal.

All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition

of RESET#. The pin which the agent samples asserted determines it’s agent ID.

These signals do not have o n-die termination and must be terminated at the

end agent. See the appropriate platform design guidelines for additional

information.

1,4

BSEL[1:0] O

These output signals are used to select the front side bus frequency. A BSEL[1:0] =

“00” will select a 100 MHz bus clock frequency. The frequency is determined by the

processor(s), chipset, and frequency synthesizer capabilities. All front side bus

agents must operate at the same frequency. Individual processors will only operate

at their specified front side bus (FSB) frequency.

On baseboards which support operation only at 100 MH z bus clocks these signals

can be ignored. On baseboards employing the use of these signals, a 1 KΩ pull-up

resistor be used.

See Table 2 “Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]” on

page 13 for output values.

COMP[1:0] I COMP[1:0] must be terminated to VSS on the baseboard using precision resistors.

These inputs configur e the AGTL+ drivers of the process or. Refer to the appropri ate

platform design guidelines and Table 12 for implementation details.

Table 41. Signal Definitions (Sheet 3 of 9)

Name Type Description Notes

BR[1:0]# Signals Rotating Interconnect, dual processor system

During power-up configuration, the central agent must assert the BR0# bus signa

All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition o

RESET#. The pin on which the agent samples an active level determines its age

ID. All agents then configure their pins to match the appropriate bus signal proto

col

as shown below.

Bus Signal Agent 0 Pins Agent 1 Pins

BREQ0# BR0# BR1#

BREQ1# BR1# BR0#

BR[1:0 ]# Signal Ag e n t IDs

BR[1:0]# Signals Rotating

Interconnect, dual processor system Agent ID

BR0# 0

BR1# 1

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 63

D[63:0]# I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor front side bus agents, and must connect the appropriate

pins on all such agents. The data driver asserts DRDY# to indicate a valid data

transfer.

D[63:0]# are quad-pumped signals, and will thus be driven four times in a common

clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and

DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP#

and one DSTBN#. The follo wing table shows the grouping of dat a si gnals to strobes

and DBI#.

Furthermore, the DBI# pins determine the polarity of the data signals. Each group

of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active,

the corresponding data group is inverted and therefore sampled active high.

DBI[3:0]# I/O

DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals.

The DBI[3:0]# signals are activated when the data on the data bus is inverted. The

bus agent will invert the data bus signals if more than half the bits, within a 16-bit

group, change logic level in the next cycle.

DBSY# I/O

DBSY# (Data Bus Bus y) is as ser ted by the agent respons ible for dri ving data on the

processor front side bus to indicate that the data bus is in use. The data bus is

released after DB SY# is deasserted. This signal must connect the appropriate pins

on all processor front side bus agents.

DEFER# I

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility

of the addressed memory or I/O agent. This signal must connect the appropriate

pins of all processor front side bus agents.

DP[3:0]# I/O DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are

driven by the agent responsible for driving D[63:0]#, and must connect the

appropriate pins of all processor front side bus agents. 4

DRDY# I/O

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

indicating val id data on the dat a bus . In a multi -common clock data tr ans fer, D RDY#

may be deasserted to insert idle clocks. This signal must connect the appropriate

pins of all processor front side bus agents. 4

DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#. 4

DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. 4

Ta b le 41 . Signal Defin itions (Sheet 4 of 9)

Name Type Description Notes

Data Gr oup DSTBN/

DSTBP DBI#

D[15:0]# 0 0

D[31:16]# 1 1

D[47:32]# 2 2

D[63:48]# 3 3

DBI[3:0] Assignment To Data Bus

Bus Signal Data Bus Signals

DBI0# D[15:0]#

DBI1# D[31:16]#

DBI2# D[47:32]#

DBI3# D[63:48]#

64 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

FERR#/PBE# O

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and

its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/

PBE# indicates a floating-point error and will be asserted when the processor

detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/

PBE# is similar to the ERROR# signal on the Intel 387 coproces sor, and is inclu ded

for compatibility with systems using MS-DOS*-type floating-point error reporting.

When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the

processor has a pending break event waiting for service. The assertion of FERR#/

PBE# indicates that the processor should be returned to the Normal state. For

additional information on the pending break event functionality, including the

identification of support of the feature and enable/disable information, refer to

volume 3 of the Intel Architecture Software Developer’s Manual and the Intel

Processor Identification and the CPUID Instruction application note.

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

GTLREF I GTLREF determines the signal reference level for AGTL+ input pins. GTLREF

should be set at 2/3Vcc. GTLREF is used by the AGTL+ receivers to determine if a

signal is a logical 0 or a logical 1.

HIT#

HITM# I/O

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any front side bus agent may assert both HIT# and HITM# together to

indicate that it requires a snoop stall, which can be continued by reasserting HIT#

and HITM# together.

Since multiple agents may deliver snoop results at the same time, HIT# and HITM#

are wire-OR signals which must connect the appropriate pins of all processor front

side bus agents. In order to avoid wire-OR glitches associated with simultaneous

edge transitions driven by multiple drivers, HIT# and HITM# are activated on

specific clock edges and sampled on specific clock edges.

IERR# O

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

processor front side bus. This transaction may optionally be converted to an

external error signal (e.g., NMI) by system core logic. The processor will keep

IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

IGNNE# I

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is deasserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

INIT# I

INIT# (Initialization), when asserted, resets integer registers inside all processors

without affecting their internal caches or floating-point registers. Each processor

then begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal and must connect the appropriate pins

of all processor front side bus agents.

If INIT# is sampled active on the active to inactive transition of RESET#, then the

processor executes its Built-in Self-Test (BIST).

Table 41. Signal Definitions (Sheet 5 of 9)

Name Type Description Notes

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 65

LINT[1:0] I

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side

bus agents. When the APIC functionality is disabled, the LINT0 signal becomes

INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a

nonmaskable interrupt. INTR and NMI are backward compatible with the signals of

those names on the Pentium processor. Both signals are asynchronous.

Both of these signals must be software configured via BIOS programming of the

APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC

is enabled by default after Re set, operation of these pins as LINT[1:0] is the default

configuration.

LOCK# I/O

LOCK# indicates to the system that a transaction must occur atomically. This signal

must connect the appropriate pins of all processor front side bus agents. For a

locked sequence of transactions, LOCK# is asserted from the beginning of the first

transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the processor

front side bus, it will wait until it observes LOCK# deasserted. This enables

symmetric agent s to r et ain owner ship of the pr ocess or front side bus thr oughout the

bus locked operation and ensure the atomicity of lock.

Mechanical

Key Inert Mechanical Key to prevent compatibility with 603-pin socket.

MCERR# I/O

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error

without a bus protocol violation. It may be driven by all processor front side bus

agents.

MCERR# assertion conditions are configurable at a system level. Assertion options

are defined by the following options:

• Enabled or disabled.

• Asserted, if configured, for internal errors along with IERR#.

• Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

• Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32 Software

Developer ’s Manual, Volume 3: System Programming Guide.

Since multiple agents m ay drive this si gnal at the same tim e, MCERR# i s a wire-OR

signal which must connect the appropriate pins of all processor front side bus

agents. In order to avoid wire-OR glitches associated with simultaneous edge

transitions driven by multiple drivers, MCERR# is activated on specific clock edges

and sampled on specific clock edges.

ODTEN I ODTEN (On-die termination enable) should be connected to VCC to enable on-die

termination for end bus agents. For middle bus agents, pull this signal down via a

resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die

termination will be active, regardless of other states of the bus.

PROCHOT# O

PROCHOT# (processor hot) indicates that the processor Thermal Control Circuit

(TCC) has been activated. Under most conditions, PROCHOT# will go active when

the processor’s thermal sensor detects that the processor has reached its

maximum safe operating temperature. See Section 6.3 for more details.

These signals do not have on-die termination and must be t erminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

Ta b le 41 . Signal Defin itions (Sheet 6 of 9)

Name Type Description Notes

66 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

PWRGOOD I

PWRGOOD (Power Good) is an input. The processor requires this signal to be a

clean indication that all processor clocks and power supplies are stable and within

their specifications. “Clean” implies that the signal will remain low (capable of

sinking leakage current), without glitches, from the time that the power supplies are

turned on until they come within specification. The signal must then transition

monotonically to a high state. Figure 6 illustrates the relationship of PWRGOOD to

the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and

power must again be stable before a subsequent rising edge of PWRGOOD. It

must also meet the minimum pulse width specification in Table 13, and be followed

by a 1 mS RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

REQ[4:0]# I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor

front side bus agents. They are asserted by the current bus owner to define the

currently active transaction type. These signals are source synchronous to

ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking

of these signals.

RESET# I

Asserting the RESET# signal resets all processors to known states and invalidates

their internal caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least one millisecond after VCC and BCLK

have reached their proper specifications. On observing active RESET#, all front

side bus agents will deassert their outputs within two clocks. RESET# must not be

kept asserted for more than 10ms.

A number of bus signals are sampled at the active-to-inactive transition of RESET#

for power-on configuration. These configuration options are described in the

Secti on 6.1.

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of all processor front side bus agents. 4

RSP# I

RSP# (Response Parity) is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#, the signals for

which RSP# provides parity protection. It must connect to the appropriate pins of all

processor front side bus agents.

A correct parity signal is high if an even number of covered signals are low and low

if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also

high, since this indicates it is not being driven by any agent guaranteeing correct

parity.

SKTOCC# O SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate

that the processor is present.

SLP# I

SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the

Sleep st ate. During Sleep st ate, t he processor stop s providi ng inter nal cloc k signal s

to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in

this state will not recognize snoops or interrupts. The processor will recognize only

assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK

input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state

and returns to Stop-Grant state, restarting its internal clock signals to the bus and

processor core units.

SMB_PRT I Pin is grounded on processor packages that do not contain SMBUS components

(PIROM, Scratch EEPROM , and thermal sensor). It is floating on processor

packages that contain the SMBus components.

Table 41. Signal Definitions (Sheet 7 of 9)

Name Type Description Notes

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 67

SMI# I

SMI# (System Management Interrupt) is asserted asynchronously by system logic.

On accepting a System Management Interrupt, processors save the current state

and enter System Management Mode (SMM). An SMI Acknowledge transaction is

issued, and the processor begins program execution from the SMM handler.

If SMI# is asserted during the deassertion of RESET# the processor will tri-state its

outputs.

STPCLK# I

STPCLK# (Stop Clock), when asserted, causes processors to enter a low power

S top-G rant state. The process or i ssues a Stop-G rant Acknow ledge transac tion, and

stops providing internal clock signals to all processor core units except the front

side bus and APIC units. The processor continues to snoop bus transactions and

service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the

processor restarts its internal clock to all units and resumes execution. The

assertion of STPCLK# has no effect on the bus clock; STPCLK# is an

asynchronous input.

TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known

as the Test Access Port).

TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO O T DO (Test D ata Out) transfers serial test data out of the processor. TDO provides

the serial output needed for JTAG specification support.

TESTHI[6:0] I

All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor

which matches the trace impedance within a range of ±10 ohms. TESTHI[3:0] and

TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if

desired. However, utilization of boundary scan test will not be functional if these

pins are connected together. TESTHI4 must always be pulled up independently

from the other TESTHI pins. For optimum noise margin, all pull-up resistor values

used for TESTHI[6:0] pins should have a resistance value within ±20 percent of the

impedance of the baseboard transmission line traces. For example, if the trace

impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used. The

TESTHI[6:0] termination recommendations provided in the Intel® XeonTM

processor d atas heet are stil l suitable for the Intel® X eonTM proc essor w ith 533 M Hz

Front Side Bus. However, Intel recommends new designs or designs undergoing

design updates follow the trace impedance matching termination guidelines given

in this section.

THERMTRIP# O

Activation of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a level beyond which permanent silicon damage may

occur. Measurement of the temperature is accomplished through an internal

thermal sensor which is configured to trip at approximately 135 °C. To properly

protect the processor, power must be removed upon THERMTRIP# becoming

active. See Figure 6 for the appropriate power down sequence and timing

requirement. In parallel, the processor will attempt to reduce its temperature by

shutting off internal clocks and stopping all program execution. Once activated,

THERMTRIP# remains latched and the processor will be stopped until RESET# is

asserted. A RESET# pulse will reset the processor and execution will begin at the

boot vector. If the temperature has not dropped below the trip level, the processor

will assert THERMTR IP# and return to the shutdown state. The processor releases

THERMTRIP# when RESET# is activated even if the processor is still too hot.

This signal do not have on-die termination and must be terminated at the end

agent. See the appropriate platform design guidelines for additional

information.

THERMDA O Thermal Diode Anode.

THERMDC O Thermal Diode Cathode.

Ta b le 41 . Signal Defin itions (Sheet 8 of 9)

Name Type Description Notes

68 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

NOTES:

1. Intel Xeon processors onl y support B R0# and BR1#. However, the Intel Xeon processors must terminate B R2# and BR3# to the

processor VCC.

2. For this pin on Intel® Xeon™ processors, the maximum number of symmetric agents is one. Maximum number of Central

Agents is zero.

3. For this pin on Intel® Xeon™ processors, the maximum number of symmetric agents is two. Maximum number of Central

Agents is zero.

4. For this pin on Intel® Xeon™ processors, the maximum number of symmetric agents is two. Maximum number of Central

Agents is one.

TMS I

TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

This signal does not have on-die termination and must be terminated at the

end agent.See the appropriate platform design guidelines for additional

information.

TRDY# I TRDY # (Target Ready) is asser ted by the target to indicate that it is read y to r eceiv e

a write or implic it writeba ck dat a tr ansfer. TRDY# must conne ct the appropr iate pin s

of all front side bus agents.

TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven

low during power on Reset. See the appropriate Platform Design Guideline for

additional information.

VCCA I

VCCA provides isolated power for the analog portion of the internal PLL’s. Use a

discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to

provide clean power to the PLL. The tolerance and total ESR for the filter is

important. Refer to the appropriate platform design guidelines for complete

implementation details.

VCCIOPLL IVCCIOPLL provides isolated power for digital portion of the internal PLL’s. Follow the

guidelines for VCCA (Section 2.5), and refer to the appropriate platform design

guidelines for complete implementation details.

VCCSENSE

VSSSENSE O

The Vccsense and Vsssense pins are the points for which processor minimum and

maximum voltage requirements are specified. Uniprocessor designs may utilize

these pins for voltage sensing for the processor's voltage regulator. How ever, multi-

processor designs must not connect these pins to sense logic, but rather utilize

them for power delivery validation.

VID[4:0] O

VID[4:0] (Voltage ID) pins can be used to support automatic selection of power

supply voltages (VCC). Unlike previous processor generations, these pins are

driven by processor logic. Hence the voltage supply for these pins (SM_VCC) must

be valid before the VRM supplying Vcc to the processor is enabled. Conversely, the

VRM output must be disabled prior to the voltage supply for these pins becomes

invalid. The VID pins are needed to support processor voltage specification

variations. See Table 3 for definitions of these pins. The power supply must supply

the voltage that is requested by these pins, or disable itself.

VID_VCC . I Voltage for VID and BSEL logic

VSSA IVSSA provides an isolated, internal ground for internal PLL’s. Do not connect

directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a

discrete filter circuit.

Table 41. Signal Definitions (Sheet 9 of 9)

Name Type Description Notes

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 69

5.0 Thermal Specifications

This chapter provides the thermal specifications necessary for designing a thermal solution for the

Intel® Xeon™ Processor with 533 MHz Front Side Bus. Thermal solutions should include

heatsinks that attach to the integrated heat spreader (IHS). The IHS provides a common interface

intended to be compatible with many heatsink designs. Thermal specifications are based on the

temperature of the IHS top, referred to as the case temperature, or TCASE. Thermal solutions should

be designed to maintain the processor within TCASE specifications. For information on performing

TCASE measurem ents, refe r to the Intel® Xeon™ Processor Thermal Design Guidelines. See Figure

18 for an explo ded vi ew of the processor package and thermal solu tion assembly.

Note: The processor is either shipped alone or with a heatsink (boxed processor only). All other

compone nts shown in Figure 18 mu st be purchased separately.

Note: This is a graphical representation. For specifications, see each component’s respective

documentation li st ed in Section 1.3.

Figure 18. Processor with Thermal and Mechanical Component s - Exploded View

604 Pin

70 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

5.1 Thermal Specifications

Tab le 42 specifies the thermal design power dissipation envelope for the Intel® Xeon™ processor

with 533 MHz Front Side Bus. The processor power listed in Table 42 is described in thermal

design power. Analysis indicates that real applications are unlikely to cause the processor to

consume the maximum possible power consumption. Intel recommends that system thermal

designs utilize the Thermal Design Power indicated in Table 42. Thermal Design Power

recommendations are chosen through characterization of server and workstation applications on

the processor.

The Thermal Monitor feature is intended to protect the processor from overheating on any high

power code that exceeds the recommendations in this table. For more details on the Thermal

Moni t or feature, re fer to Sectio n 6.3. In all cases, the Thermal Monitor feature must be enabled for

the processor to be operating within specification. Ta b le 42 also lists the minimum and maximum

processor TCASE temperature specifications. A thermal solution should be designed to ensure the

temperature of the processo r nev er exceeds these spec ifications.

NOTE:

1. Intel recommends that the rmal solutions be designed utiliz ing t he Thermal Des ign Pow er valu es. R efer to the

Intel® Xeon™ Processor Thermal Design Guidelines.

2. TDP values are specified at the point on Vcc_max loadline corresponding to Icc_TDP.

3. Systems must be designed to ensure that the processor is not subjected to any static Vcc and Icc

combination wherein Vcc exceeds Vcc_max at specified Icc. Please refer to the loadline specifications in

Chapter 2.0.

Figure 19. Pro ces s or Thermal Design Power vs Electrical Projections for VID = 1.500V

Table 42. Processor Thermal Design Power

Core Frequency Thermal Design

Power1

(W)

Maximum Power

(W) Minimum TCASE

(°C) Maximum TCASE

(°C) Notes

2GHz 58 66 5 70 2,3

2.40 GHz 65 75 5 74 2,3

2.66 GHz 72 83 5 74 2,3

2.80 GHz 74 86 5 75 2,3

3.06 GHz 85 101 5 73 2,3

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 71

Figure 20. Proces sor Thermal Design Power vs Electrical Projections for VID = 1.525V

72 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

5.2 Measurement s for Thermal Specifications

5.2.1 Processor Case Temperature Measurement

The minimum and maximum case temperatures (TCASE) for processors are specified in Table 42 of

the previous section. These temperature specifications are meant to ensure correct and reliable

operation of the processor. Figure 21 illustrates the thermal measurement point for TCASE. This

point is at th e geometric center of th e integrated heat spreader (IHS).

Figure 21. Thermal Measurement Point for Process or TCASE

Note: Figure is not to scale, and is for reference only

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 73

6.0 Features

6.1 Power-On Configuration Options

The Intel® Xeon™ Processor with 533 MHz Front Side Bus has several configuration options that

are determined by the state of specific processor pins at the active-to-inactive transition of the

proces sor RESET# signal. These configur ation options cannot be changed except by another reset.

Both power on a nd softwar e induced resets re c onfigure t he processor(s).

NOTES:

1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option.

2. The Intel® Xeon™ processor with 533 MHz Front Side Bus does not support this feature, therefore platforms

utilizing this processor should not use these configuration pins.

3. Intel Xeon processor with 533 MH z Front S ide Bus util ize onl y B R0# and BR1# signal s. 2- way plat for ms mus t

not utilize BR2# and BR3# signals.

6.2 Clock Control and Low Power States

The processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power

consumption by stopping the clock to internal sections of the processor, depending on each

particular state. See Figure 22 f or a vis ual r epresentation of the processor low power states.

Due to the inability of processors to recognize bus transactions during the Sleep state,

multiprocessor systems are not allow ed to simultaneously have one processor in Sleep state and the

other processor in th e Normal or Stop-Grant state.

6.2.1 Normal State—State 1

This is the nor m al operating state for the processor.

Tabl e 43. Power-On Configuration Opt io n Pins

Configuration Option Pin1Notes

Output tri state SMI#

Execute BIST (Built-In Self Test) INIT#

In Order Queue de-pipelining (set IOQ depth to 1) A7#

Disable MCERR# observation A9#

Disable BINIT# observation A10#

APIC cluster ID (0-3) A[12:11]# 2

Disable bus parking A15#

Disable Hyper-Threading Technology A31#

Symmetric agent arbitration ID BR[3:0]# 3

74 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

6.2.2 AutoHALT Powerdown State—St ate 2

AutoHALT is a low power state entered when the processor executes the HALT instruction. The

processor will transition to the Normal state upon the occurrence of BINIT#, INIT#, LINT[1:0]

(NMI, INTR), or an interr upt delivered over the front side bus. RESE T# will caus e the processor to

immediately initialize its e lf.

The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.

When the system deasserts the STPCLK# interrupt, the processor will return execution to the

HALT state.

6.2.3 Stop-Grant State—State 3

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks

after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once

the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop

Grant state. Both logical processors of the Intel® Xeon™ processor with 533 MHz Front Side Bus

must be in the Stop Grant state before the deassertion of STPC LK#.

Figure 22. Stop Clock State Machine

2. Auto HALT Power Down

State

BCLK running

Snoops and interrupts allow ed

1. Normal State

Normal execution

4. HALT/Grant S noo p S ta te

BCLK running

Service snoops to caches

3. Stop Grant State

BCLK running

Snoops and interrupts allowed

5. Sleep State

BCLK running

No snoops or interrupts

allowed

HALT Instruction and

HALT Bus Cycle Generated

Snoop

Event

Occurs

Snoop

Event

Serviced

INIT# , BIN IT #, INTR, N MI,

RESET#

STPCLK#

Asserted STPCLK#

De-asserted

STPCLK# Asserted

STPCLK# De-asserted

SLP#

Asserted SLP#

De-asserted

Snoop Event Occurs

Snoop Event Serviced

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 75

Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven

(allowing the level to return to VCC) for minimum power drawn by the termination resistors in this

state. In addition, all other input pins on the front side bus should be driv en to the inac tive state.

BINIT# will be recognized while the processor is in Stop-Grant state. If STPCLK# is still asserted

at the com ple tion of the BINI T# bus initi aliza tion , the pr ocess or wil l remain in S top- Gr ant mo de. If

the STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor will

return to Normal state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the

STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should

onl y be de a s se rte d one or mo re bu s clock s aft er the de a ss e r ti on of SL P # .

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the

front side bus (see Se c tion 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with

the assertion of the SLP# signal.

While in the Stop-Grant state, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and

only serviced when the processor returns to the Normal state. Only one occurrence of each event

will be recognized upon retur n to the Normal state.

6.2.4 HALT/Grant Snoop State—State 4

The processor will respond to snoop transactions on the front side bus while in Stop-Grant state or

in AutoHA LT Power Down s tate. Durin g a snoop trans action, the pr ocesso r enters th e HALT/Grant

Snoop state. The processor will stay in this state until the snoop on the front side bus has been

serviced (whether by the processor or another agent on the front side bus). After the snoop is

serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as

appropriate.

6.2.5 Sleep S tate—State 5

The Sleep state is a very low power state in which each processor maintains its context, maintains

the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be

entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing

the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT

states.

Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will

cause unpredic t a ble behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching

interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)

are allowed on the front side bus while the processor is in Sleep state. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in

the RESET# pin specification, then the processor will reset itself, ignoring the transition through

Stop-Grant state. If RESET# is dr iven active while the processor is in the Sleep s tate, th e SLP# and

STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the

processor correctl y execu tes the reset sequence.

76 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous front side bus

event occurs. The SLP# pin should only be asserted when the processor (and all logical processors

within the physical processor) is in the Stop-Grant state. SLP# assertions while the processors are

not in the S top-Gra nt sta te is out of specification and may result in ille ga l oper a tion.

6.2.6 Bus Response During Low Power States

While in Aut oHALT Power Down and S top -Grant stat es, th e processor will process a front s ide bus

snoop.

When the processor is in Sleep state, the processor will not process interrupts or snoop

transactions.

6.3 Thermal Monitor

Thermal Monitor is a feature of the processor that allows system designers to lower the cost of

thermal solutions, without compromising system integrity or reliability. By using a factory-tuned,

precision on-die temperature sensor, and a fast acting thermal control circuit (TCC), the processor,

without the aid of an y a dditi ona l software or ha rdware, can control the processors’ die tempera ture

within factory specifications under typical real-world operating conditions. Thermal Monitor thus

allows the processor and system thermal solutions to be designed much closer to the power

envelopes of real applications, instead of being designed to the much higher maximum processor

power envelopes.

Thermal Monitor controls the processor temperature by modulating (starting and stopping) the

internal processor core clocks. The processor clocks are modulated when the thermal control

circuit (TCC) is activated. Thermal Monitor uses two modes to activate the TCC: Automatic mode

and On-Demand mode. Auto matic m ode m ust be e nabl ed vi a BIO S, whic h is requ ired for t he

processor to operate within specifications. Once automatic mode is enabled, the TCC will

activate only when th e internal die temperature is very near the temperatu re limits of the processor.

When the TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks

will be modulated by maintaining a duty cycle wi thin a r a nge of 30% - 50%. Cl oc ks will not be off

or on more than 3.0 ms when the TCC is active. Cycle times are processor speed dependent and

will decrease as processor core frequencies increase. A small amount of hysteresis has been

included to prevent rapid active/inactive transitions of the TCC when the processor temperature is

near the trip point. Once the temperature has returned to a non-critical level, and the hysteresis

timer has expired, modulation ceases and the TCC goes inactive. Processor performance will be

decreased by ~50% when the TCC is active (assuming a duty cycle that varies from 30%-50%),

however, with a properly designed and characterized thermal solution the TCC most likely will

only be activated briefly during the most power intensive applications while at maximum chassis

ambient tem per ature.

For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic

mode does not requi re a ny additional hardware, s oftw a re drive rs or int e rrupt ha ndlin g routi ne s.

The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor

Control Register is written to a “1” the TCC will be activated immediately, independent of the

processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the

clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control

however in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to

87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used at the same time

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 77

Automatic mode is enabled, however, if TCC is enabled via On-Demand mode at the same time

automatic mode is enabled AND a high temperature condition exists, the fixed duty cycle of the

automatic mode will overr ide the duty cycle selected by the On-Demand mode.

An exter nal signal , PR OCHOT# (processor hot) is asse rted at any time the TCC is active (either in

Automatic or On-Demand mode). Bus snooping and interrupt latching are also active while the

TCC is active. The temperature at which the thermal control circuit activates is not user

configurable and is not software visible. In an MP system, Thermal Monitor must be configured

ident ically for each proces s or within the sys tem .

Besides the thermal sensor and thermal control circuit, the Thermal Monitor feature also includes

one ACPI regi ster , on e performance co unter regist er , three model specific registe rs (MSR), an d one

I/O pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor

feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or de-

assertion of PROCHOT# (i.e. upon the activation/deactivation of TCC). Refer to Volume 3 of the

IA32 Intel Architecture Software Developer’s f or spec ific registe r and pr ogramming de ta ils.

If automatic mode is disabled the processor will be operating out of specification and cannot be

guaranteed to provide reliable results. Regardless of enabling of the automatic or On-Demand

modes, in the event of a catastrophic cooling failure, the processor will automatically shut down

when the silicon has reached a temperature of approximately 135 °C. At this point the front side

bus signal THERMTRIP# will go active and stay active until the processor has cooled down and

RESET# has been initiated. THERMTRIP# activation is independent of processor activity and

does not generate any bus cycles.If THERMTRIP# is asserted, processor core voltage (VCC) mus t

be rem oved wit hin the timeframe defin e d in Fi g ur e 6.

6.3.1 Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the baseboard

may be used to monitor the die temper ature o f the pro cessor for ther mal manag ement/l ong ter m die

te mpera ture change pur poses. Table 44 and Table 45 provide the diode par a meter and inter face

specifica tions.Thi s thermal diode i s se parate from t he Thermal Monitor’s thermal sensor a nd

ca nnot be used to predic t the behavior of the Ther mal Monitor.

Ta b l e 44. T herma l D iode P arameters

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized at 75°C.

3. Not 100% tested. Specified by design characterization.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

equation:

IFW=Is *(e(qVD/nkT) -1)

Where IS = saturation cu rrent, q = electr onic cha rge, VD = voltage across the diod e, k = Boltzmann Constant,

and T = absolute temperature (Kelvin).

5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction

temperature. RT as defined includes the pins of the processor but does not include any socket resistance or

Symbol Parameter Min Typ Max Unit Notes

IFW Forwar d Bias

Current 5 300 uA 1

nDiode Ideality

Factor 1.0011 1.0021 1.0030 2,3,4

RTSeries

Resistance 3.64 W 2,3,5

78 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

board trace resis tanc e between the socket and the ex ternal r emote diod e thermal sensor. RT can be used by

remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.

Another application is that a temperature offset can be manually calculated and programmed into an offset

q)*ln N]

Where Terror = sensor temperature error, N = sensor current ration, k = Boltzmann Constant, q = electronic

charge.

Ta b l e 45. Therm al Diod e I n ter fa c e

Pin Nam e Pin Numbe r Pin Description

THERMDA Y27 diode anode

THERMDC Y28 diode cathode

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 79

7.0 Boxed Processor Specification s

7.1 Introduction

The Intel® Xeon™ Processor with 533 MHz Front Side Bus is also offered as an Intel boxed

processor. Intel boxed processors are intended for system integrators who build systems from

components available through distribution channels. The boxed processor is supplied with an

unattached passive heatsink. It will also contain an optional active duct solution, called Processor

Wind Tunnel (PWT), to provide adequate airflow across the heatsink. If the chassis or baseboard

used contains an alternate cooling solution that has been thermally validated, the PWT may be

discarded. This chapter documents baseboard and platform requirements for the cooling solution

that is supplied with the boxed processor. This chapter is particularly important for OEM's that

manufacture baseboards and chassis for integrators. Figure 23 shows a mechanical representation

of a boxed processor heatsink.

Note: Drawing s in this section ref lect only the specifications on the Intel boxed processor pro duct. These

dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system

designer's responsibility to consider their proprietary cooling solution when designing to the

required keep-out zone on th eir system platfor m an d chassis .

Figure 23. Mechanical Representation of the Boxed Processor Passive Heatsink

80 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

7.2 Mechanical Specifications

This section documents the mechanical specifications of the boxed processor passive heatsink and

the PWT.

Proper clearance is required around the heatsink to ensure proper installation of the processor and

unimpeded airflow fo r prop e r cooling.

7.2.1 Boxed Processor Heat si nk Dimensions

The boxed processor is shipped with an unattached passive heatsink. Clearance is required around

the heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and

dimensions for the boxed processor with assembled heatsink are shown in Figure 26 (Multiple

Views). The airflow requirements for the boxed processor heatsink must also be taken into

consideration when designing new baseboards and chassis. The airflow requirements are detailed

in the Thermal Specifications, Se c ti o n 7.4.

7.2.2 Boxed Processor Heatsink Weight

The boxed proc essor heatsink weighs no more than 45 0 grams. See Chapte r 3.0 and Chapte r 5. 0 of

this document along with the Intel® XeonTM Processor Family Thermal Design Guidelines for

det a ils on the processor weight and he a tsink requirements.

7.2.3 Boxed Processor Retention Mechanism and Heatsink Support s

The boxed proc essor re quires proces sor retention solution to secu re the process or, the basebo a rd,

and the chassis. The retention solution contains one retention mechanism s and tw o retention clips

per processor. The boxed pr ocessor s hips with retention mechanis m, cooling so lution retention

clips, and dir ect chassis attach screws.Baseboards and chassis designed for use by system integra-

tors should includ e hole s that a re in prope r alig nment with each other to support the box e d proces-

sor. Refer to the Server System Infrast ructure Specification (SSI-EEB) at http://www.ssif orum.org

for deta ils on the ho le location s . P lease refer to the “Boxed integration notes ” at http://su p-

port.intel.com/support/processors/xeon for retention mechanism instal lation instruct ions. Retention

mechanis m clips must int erface with the boxed proce ssor heatsi nk area shown in Detail A in Figure

26.

The retention mechanism that ships with the boxed process or is different than the reference solu-

tion from Intel. Please refer to Figure 24 bel ow, which contai ns the di mensions for t he reference

solution. Please refer to Figure 25 for the rete ntion mechanism that ships with the boxed pro ces s or.

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Figure 24. Boxed Processor Retention Mechanism and Clip

82 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Figure 25. Boxed Processor Retention Mechanism that Ships with the Processor

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Figure 26. Multiple View Space Requirements for the Boxed Processor

84 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

7.3 Boxed Processor Requirements

7.3.1 Intel® Xeon™ Processor with 533 MHz Front Side Bus

7.3.1.1 Processor Wind Tunnel

The boxed processor ships with an active duct cooling solution called the Processor Win d Tunnel,

or PWT. This is an optional cooling solution that is designed to meet the thermal requirements of a

diverse combination of baseboards and chassis. It ships with the processor in order to reduce the

burden on the chassis manufacturer to provide adequate airflow across the processor heatsink.

Manufa cturers may e le ct to us e their own cooling solution.

Note: Although Intel will be testing a select number of baseboard and chassis combinations for thermal

compliance, this is in no way a comprehensive test. It is ultimately the system integrator’s

responsibility to test that their solution meets all of the requirements specified in this document.

The PWT is meant t o assis t in pro cess or cool ing , but add iti onal coo lin g tech niques may be r equir ed

in order to ensure that the entire sys tem meets the thermal re quirements.

See Figur e 28 and Figure 29 for the Processor Wind Tunnel dimensions.

7.3.1.2 Fan Power Supply

The Processor Wind Tunnel includes a fan, which requires a constant +12V power supply. A fan

power cable is shipped with the boxed processor to draw power from a power header on the

baseboard. The power cable connector and pinouts are shown in Figure 27 and the fan cable

connector requirements are detailed in Ta b l e 4 6 . Platforms must provide a matched power header

to s u ppo rt t h e box e d proc e s sor. Ta bl e 47 contains specifications for the input and output signals at

the fa n heatsi nk con nec tor. The fan hea t sink ou tpu ts a SENSE si gna l, an op en-c olle cto r outpu t, th at

pulses at a rate of two pulses per fan revolution. A baseboard pull-up resistor provides VOH to

match the baseboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE

signal is optional. If the SENSE signal is not us e d, pin 3 of the con ne c tor should be tie d to GND.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the platform

documentation, or on the baseboard itself. The baseboard power header should be positioned

within 7 inch es from th e centr e of the proces s or socket.

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 85

1. Baseboard should pull this pin up to VCC w ith a resistor.

Figure 27. Fan Connector Electrical Pin Sequence

Table 46. Fan Cable Connector Requirements

Table 47. Fan Power and Signal Specifications

Description Min Typ Max Unit Notes

+12V: 12 Vot Fan Power Supply 6.0 12.0 13.2 V

IC: Fan Current Draw 1.5 A

SENSE Frequency 2 Pulses per fan

revolution 1

Item Specification

Connector Type

− Fa n c o nnector must be a str a i ght squ are pin, 3-pin t e rmi na l

housing wi t h pol arizi ng ribs and fri ction lo ck i n g ramp.

− M atch with a straight pin, fric tion lock header on th e

mainboard.

− M anuf acturer and part number or e quivalent:

o AMP†: Fan conn ect or: 643815- 3, he ader : 640 456-3

o Walden† / Molex†: Fan connector: 22-01-3037,

header: 22-23-2031

Pin O ut

(See Figure

Above)

− Pin 1: Ground; black wire.

− Pin 2: Power, +12 V; yellow wire.

− Pin 3: Signal, Open collec tor tachomete r output s i gna l

requirement: 2 pulses per revolution; green wire.

Fa n c a bl e length

(Drawing

747887):

Th e fan cable con nector mus t rea ch a matin g mainboard

conn ector at any poi n t wit hi n a ra di us of 110 mm (4.33”)

m easu red f rom the central da tu m plan es of the enabled

assem bly (datum planes A, B & C on Drawing AXXXXX).

Fa n c a bl e

routing

Fan po wer cab l e must be rout ed in su ch a w ay to prevent it from

cont acti ng t he fan i mpellor and it mus t be positione d i n a

consistent location from unit to unit.

86 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

Figure 28. Processor Wind Tunnel General Dimensions

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 87

Figure 29. Processor Wind Tunnel Detailed Dimensions

88 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

7.3.1.3 Fan

The Pr oc essor Wi nd Tunnel includ e s a 25mm fan for use with proces sors < = 2.8 GHz , or a 38mm

fan for use with processor s running at 3 GHz a nd a bove. T he 38mm fan provides the high

performanc e requir ed to meet the demand ing ther mal requi rement s of processors running at 3 GHz

and above. The 38mm fan prov ide s local fan speed control. There is a tempera ture diode on the fan

that meas ures the inlet temperatu re to the fan and adjusts th e s peed accordingly. The benefit is that

system manufacturers can pass acoustical requirements while still being able to pass thermal

requirem ents at maximum ambient tem per ature.

7.3.2 1U Rack Mount Server Solution

The 1U solution c ontains a pas sive heatsink an d a foam pa d, in addi tion to th e re tention solu tion

includ ed with the ot her op tions . Becau se of th e sm all fo rm facto r , the 1U heats ink is not as ef fi cient

at diss ipating heat as the g eneral- purp ose heats ink. In o rder to en sure max imum the rmal ef ficien cy,

the foam pad must be attac hed to the top of the 1U heatsink, blo cking airfl ow between the heat sink

and the chassis cover. This will force air through the heatsink fi ns instead of allowing it to by pas s

ove r the top. Se e Fig ur e 30 and Figu re 31 for more detail on ins tallation.

Figure 30. Exploded View of the 1U Thermal Solution

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Figure 31. Assembled View of the 1U Thermal Solution

90 Intel ® Xe on™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3. 06 GHz

7.4 Thermal Specifications

This section describes the cooling requirements of the heatsink solution utilized by the boxed

processor.

7.4.1 Boxed Processor Cooling Requirements

The boxed processor will be directly cooled with a passive heatsink. For the passive heatsink to

effectively cool the boxed processor, it is critical that sufficient, unimpeded, cool air flow over the

heatsink of every processor in the system. Meeting the processor’s temperature specification is a

function of the thermal design of the entire system, and ultimately the responsibility of the system

integrator. The processor temperature specification is found in Chapter 5.0. It is important that

system integrators perform thermal tests to verify that the boxed processor is kept below its

maximum temper ature specific ation in a specific baseboar d and chassis.

At an absolute minimum, the boxed processor heatsink will require 500 Linear Feet per Minute

(LFM) of cool air flowing over the heatsink. The airflow must be directed from the outside of the

chassis directly over the processor heatsinks in a direction passing from one retention mechanism

to the other. It also should flow from the front to the back of the chassis. Directing air over the

passive heatsink of the boxed Intel® Xeon™ Processor with 533 MHz Front Side Bus can be done

with auxiliary chassis fans, fan ducts, or other techniques.

It is also recommended that the ambient air temperature outside of the chassis be kept at or below

35 °C. The air pas sing direc tly over the proces sor heats in k shou ld not be prehea ted by oth er system

components (such as another processor), and should be kept at or below 45 °C. Again, meeting the

processor's temperature specification is the responsibility of the system integrator. The processor

temperature specification is found in Chapter 5.0.

Intel ® Xe on™ Pr oces so r with 533 MHz Front Si de B us at 2 GHz to 3.06 GHz 91

8.0 Debug Tools Specifications

The Debug Port design information has been moved. This includes all information necessary to

develop a Debug Port on this platform, including electrical specifications, mechanical

requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700

Debug Port Design Guide for the des i gn of your platform.

8.1 Logic Analyzer Interface (LAI)

Intel® is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for

use in debuggin g system s. Tektronix * a nd Ag ile nt* should be c ontacted t o ge t spec ific inform a tion

about their logic analyzer interfaces. The following information is general in nature. Specific

inf ormation must be obtai ned from the logic analyzer vendor.

Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture

front side bus signals. There are two sets of considerations to keep in mind when designing a

syst em that can m ake use of an LAI: mec hanical and electrical.

8.1.1 Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI pins plug into the

socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI

egresses the system to allow an electrical connection between the processor and a logic analyzer.

The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable

egress restrictions, should be obtained from the logic analyzer vendor. System designers must

make sure that the keepout volume remains unobstructed inside the system. Note that it is possible

that the keepout volume reserved for the LAI may differ from the space normally occupied by the

processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as

par t of the L AI .

8.1.2 Electrical Considerations

The LAI will also affect the electrical performance of the front side bus; therefore, it is critical to

obtain electrical load models from each of the logic analyzers to be able to run system level

simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for

electrical specif ications and load models for the LAI solution they provide.

92 Int el ® Xeon™ Pr oces sor wi th 533 MH z Fron t S i de Bus at 2 GHz to 3.06 GHz

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