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LP3963/LP3966 3A Fast Ultra Low Dropout Linear Regulators

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1FEATURES DESCRIPTION

The LP3963/LP3966 series of fast ultra low-dropout

2• Ultra Low Dropout Voltage linear regulators operate from a +2.5V to +7.0V input

• Low Ground Pin Current supply. Wide range of preset output voltage options

• Load Regulation of 0.06% are available. These ultra low dropout linear

regulators respond very quickly to step changes in

• 15µA Quiescent Current in Shutdown Mode load which makes them suitable for low voltage

• Specified Output Current of 3A DC microprocessor applications. The LP3963/LP3966 are

• Available in DDPAK/TO-263 and TO-220 developed on a CMOS process which allows low

Packages quiescent current operation independent of output

load current. This CMOS process also allows the

• Output Voltage Accuracy ± 1.5% LP3963/LP3966 to operate under extremely low

• Error Flag Indicates Output Status (LP3963) dropout conditions.

• Sense Option Improves Load Regulation Dropout Voltage: Ultra low dropout voltage; typically

(LP3966) 80mV at 300mA load current and 800mV at 3A load

• Minimum Output Capacitor Requirements current.

• Overtemperature/Overcurrent Protection Ground Pin Current: Typically 6mA at 3A load

•−40°C to +125°C Junction Temperature Range current.

Shutdown Mode: Typically 15µA quiescent current

APPLICATIONS when the shutdown pin is pulled low.

• Microprocessor Power Supplies Error Flag: Error flag goes low when the output

• GTL, GTL+, BTL, and SSTL Bus Terminators voltage drops 10% below nominal value (for LP3963).

• Power Supplies for DSPs SENSE: Sense pin improves regulation at remote

• SCSI Terminator loads. (For LP3966)

• Post Regulators Precision Output Voltage: Multiple output voltage

• High Efficiency Linear Regulators options are available ranging from 1.2V to 5.0V and

adjustable (LP3966), with a specified accuracy of

• Battery Chargers ±1.5% at room temperature, and ±3.0% over all

• Other Battery Powered Applications conditions (varying line, load, and temperature).

Typical Application Circuits

*SD and ERROR pins must be pulled high through a 10kΩpull-up resistor. Connect the ERROR pin to ground if this

function is not used. See Application Hints for more information.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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*SD and ERROR pins must be pulled high through a 10kΩpull-up resistor. Connect the ERROR pin to ground if this

function is not used. See Application Hints for more information.

Block DiagramLP3963

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Block DiagramLP3966

Block DiagramLP3966-ADJ

Connection Diagram

Figure 1. Top View Figure 2. Top View

TO-220-5 Package DDPAK/TO-263-5 Package

Bent, Staggered Leads

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Pin Descriptions for TO-220-5 and DDPAK/TO-263-5 Packages

LP3963 LP3966

Pin # Name Function Name Function

1 SD Shutdown SD Shutdown

2 VIN Input Supply VIN Input Supply

3 GND Ground GND Ground

4 VOUT Output Voltage VOUT Output Voltage

5 ERROR ERROR Flag SENSE/ADJ Remote Sense Pin/Output

Adjust Pin

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings (1)(2)

Storage Temperature Range −65°C to +150°C

Lead Temperature (Soldering, 5 sec.) 260°C

ESD Rating (3) 2 kV

Power Dissipation (4) Internally Limited

Input Supply Voltage (Survival) −0.3V to +7.5V

Shutdown Input Voltage (Survival) −0.3V to VIN+0.3V

Output Voltage (Survival) (5) (6) −0.3V to +7.5V

IOUT (Survival) Short Circuit Protected

Maximum Voltage for ERROR Pin VIN+0.3V

Maximum Voltage for SENSE Pin VOUT+0.3V

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which

the device is intended to be functional, but does not specify performance limits. For ensured specifications and test conditions, see

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.

(4) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be

derated at θjA = 50°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the DDPAK/TO-263

surface-mount package must be derated at θjA = 60°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. See Application Hints.

(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to

ground.

(6) The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will

get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can

typically withstand 200mA of DC current and 1Amp of peak current.

Operating Ratings

Input Supply Voltage (Operating), (1) 2.5V to 7.0V

Shutdown Input Voltage (Operating) −0.3V to VIN+0.3V

Maximum Operating Current (DC) 3A

Operating Junction Temp. Range −40°C to +125°C

(1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5V, whichever is greater.

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Electrical Characteristics

LP3963/LP3966

Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: VIN = VO(NOM) + 1.5V, IL= 10 mA, COUT =33µF, VSD = VIN-0.3V.

Symbol Parameter Conditions Typ (1) LP3963/6 (2) Units

Min Max

Output Voltage Tolerance(3) VOUT +1.5V < VIN< 7.0V -1.5 +1.5

VO0 %

10 mA < IL< 3A -3.0 +3.0

Adjust Pin Voltage (ADJ version) 10 mA ≤IL≤3A 1.198 1.234

VADJ 1.216 V

VOUT +1.5V ≤VIN≤7.0V 1.180 1.253

ΔVOL Output Voltage Line Regulation VOUT +1.5V < VIN < 7.0V 0.02 %

(3) 0.06

ΔVO/ΔIOUT Output Voltage Load Regulation 10 mA < IL< 3A 0.06 %

(3) 0.01

VIN - VOUT IL= 300 mA 80 100

120

Dropout Voltage (4) mV

IL= 3A 800 1000

1200

IL= 300 mA 5 9

Ground Pin Current In Normal

IGND mA

Operation Mode IL= 3A 6 14

IGND Ground Pin Current In Shutdown VSD ≤0.2V 15 25 µA

Mode (5) 75

IO(PK) Peak Output Current See (6) 4.5 4 A

3.5

SHORT CIRCUIT PROTECTION

ISC Short Circuit Current 5.5 A

OVER TEMPERATURE PROTECTION

Tsh(t) Shutdown Threshold 165 °C

Tsh(h) Thermal Shutdown Hysteresis 10 °C

SHUTDOWN INPUT

Output = High VIN VIN–0.3

VSDT Shutdown Threshold V

Output = Low 0 0.2

TdOFF Turn-off delay IL= 3A 20 µs

TdON Turn-on delay IL= 3A 25 µs

ISD SD Input Current VSD = VIN 1 nA

ERROR FLAG

VTThreshold See (7) 10 5 16 %

VTH Threshold Hysteresis See (7) 52 8 %

VEF(Sat) Error Flag Saturation Isink = 100µA 0.02 0.1 V

Td Flag Reset Delay 1 µs

(1) Typical numbers are at 25°C and represent the most likely parametric norm.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).

(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.

Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line

and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the

output voltage tolerance specification.

(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.

Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is

nothing but the input to output differential, since the minimum input voltage is 2.5V.

(5) This specification has been tested for −40°C ≤TJ≤85°C since the temperature rise of the device is negligible under shutdown

conditions.

(6) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be

derated at θjA = 50°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the DDPAK/TO-263

surface-mount package must be derated at θjA = 60°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. See Application Hints.

(7) Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. See Application Hints.

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Electrical Characteristics

LP3963/LP3966 (continued)

Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: VIN = VO(NOM) + 1.5V, IL= 10 mA, COUT =33µF, VSD = VIN-0.3V.

Symbol Parameter Conditions Typ (1) LP3963/6 (2) Units

Min Max

Ilk Error Flag Pin Leakage Current 1 nA

Imax Error Flag Pin Sink Current VError =0.5V 1 mA

AC PARAMETERS

VIN = VOUT + 1.5V 60

COUT = 100uF

VOUT = 3.3V

PSRR Ripple Rejection dB

VIN = VOUT + 0.3V 40

COUT = 100uF

VOUT = 3.3V

ρn(l/f Output Noise Density f = 120Hz 0.8 µV

BW = 10Hz – 100kHz 150

enOutput Noise Voltage (rms) µV (rms)

BW = 300Hz – 300kHz 100

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Typical Performance Characteristics

Unless otherwise specified, VIN = VO(NOM) + 1.5V, VOUT= 2.5V, COUT = 33µF, IOUT = 10mA, CIN = 68µF, VSD = VIN, and TA=

25°C.

Drop-Out Voltage

Drop-Out Voltage Vs

Vs Temperature (IL= 100mA, 1A, VOUT = 2.5V, Dropout at 50mV

Temperature for Different Load Currents Down)

Figure 3. Figure 4.

Ground Pin Current Ground Pin Current

Vs Vs

Input Voltage (VSD=VIN) Input Voltage (VSD=100mV)

Figure 5. Figure 6.

Ground Current Ground Current

Vs Vs

Temperature (VSD=VIN) Temperature (VSD=0V)

Figure 7. Figure 8.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VIN = VO(NOM) + 1.5V, VOUT= 2.5V, COUT = 33µF, IOUT = 10mA, CIN = 68µF, VSD = VIN, and TA=

25°C. Ground Pin Current Input Voltage

Vs Vs

Shutdown Pin Voltage Output Voltage

Figure 9. Figure 10.

Output Noise Density, VOUT= 2.5V Output Noise Density, VOUT= 5V

Figure 11. Figure 12.

Ripple Rejection

Load Transient Response Frequency

Figure 13. Figure 14.

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Typical Performance Characteristics (continued)

Unless otherwise specified, VIN = VO(NOM) + 1.5V, VOUT= 2.5V, COUT = 33µF, IOUT = 10mA, CIN = 68µF, VSD = VIN, and TA=

25°C.

δVOUT

Temperature Noise Density VIN = 3.5V, VOUT = 2.5V, IL= 10 mA

Figure 15. Figure 16.

Line Transient Response Line Transient Response

Figure 17. Figure 18.

Line Transient Response (IOUT = 3.0A) Line Transient Response (IOUT = 3.0A)

Figure 19. Figure 20.

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APPLICATION HINTS

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are required to assure stability. these capacitors must be

correctly selected for proper performance.

INPUT CAPACITOR: The LP3963/6 requires a low source impedance to maintain regulator stability because the

internal bias circuitry is connected directly to VIN. The input capacitor must be located less than 1 cm from the

LP3963/6 device and connected directly to the input and ground pins using traces which have no other currents

flowing through them (see PCB LAYOUT).

The minimum allowable input capacitance for a given application depends on the type of the capacitor and ESR

(equivalent series resistance). A lower ESR capacitor allows the use of less capacitance, while higher ESR types

(like aluminum electrolytics) require more capacitance.

The lowest value of input capacitance that can be used for stable full-load operation is 68 µF (assuming it is a

ceramic or low-ESR Tantalum with ESR less than 100 mΩ).

To determine the minimum input capacitance amount and ESR value, an approximation which should be used is:

CIN ESR (mΩ) / CIN (µF) ≤1.5

This shows that input capacitors with higher ESR values can be used if sufficient total capacitance is provided.

Capacitor types (aluminum, ceramic, and tantalum) can be mixed in parallel, but the total equivalent input

capacitance/ESR must be defined as above to assure stable operation.

IMPORTANT: The input capacitor must maintain its ESR and capacitance in the "stable range" over the entire

temperature range of the application to assure stability (see CAPACITOR CHARACTERISTICS).

OUTPUT CAPACITOR: An output capacitor is also required for loop stability. It must be located less than 1 cm

from the LP3963/6 device and connected directly to the output and ground pins using traces which have no other

currents flowing through them (see PCB LAYOUT).

The minimum value of the output capacitance that can be used for stable full-load operation is 33 µF, but it may

be increased without limit. The output capacitor's ESR is critical because it forms a zero to provide phase lead

which is required for loop stability. The ESR must fall within the specified range:

0.2Ω ≤ COUT ESR ≤5Ω

The lower limit of 200 mΩmeans that ceramic capacitors are not suitable for use as LP3963/6 output capacitors

(but can be used on the input). Some ceramic capacitance can be used on the output if the total equivalent ESR

is in the stable range: when using a 100 µF Tantalum as the output capacitor, approximately 3 µF of ceramic

capacitance can be applied before stability becomes marginal.

IMPORTANT: The output capacitor must meet the requirements for minimum amount of capacitance and also

have an appropriate ESR value over the full temperature range of the application to assure stability (see

CAPACITOR CHARACTERISTICS).

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and variation with temperature must be taken into consideration

when selecting a capacitor so that the minimum required amount of capacitance is provided over the full

operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation

with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also

typically have large temperature variation of capacitance value.

Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics,

as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors.

Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so

severe they may not be feasible for some applications (see CAPACITOR CHARACTERISTICS).

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CAPACITOR CHARACTERISTICS

CERAMIC: For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly

than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR

(typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a

function of voltage and temperature.

Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or

Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V

also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of

the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically

maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of

course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.

TANTALUM: Solid Tantalum capacitors are recommended for use on the output because their typical ESR is

very close to the ideal value required for loop compensation. They also work well as input capacitors if selected

to meet the ESR requirements previously listed.

Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value

that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X

going from the high to low temperature limits.

The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if

the ESR of the capacitor is near the upper limit of the stability range at room temperature).

ALUMINUM: This capacitor type offers the most capacitance for the money. The disadvantages are that they are

larger in physical size, not widely available in surface mount, and have poor AC performance (especially at

higher frequencies) due to higher ESR and ESL.

Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also

varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X

when going from 25°C down to −40°C.

It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which

indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance

specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP396X. Derating must be

applied to the manufacturer's ESR specification, since it is typically only valid at room temperature.

Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating

temperature where ESR is maximum.

PCB LAYOUT

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.

The input and output capacitors must be directly connected to the input, output, and ground pins of the LP3963/6

using traces which do not have other currents flowing in them Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the VIN, VOUT, and ground

pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its

capacitors have a "single point ground".

It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane

were used at the ground points of the LP3963/6 IC and the input and output capacitors. This was caused by

varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single

point ground technique for the regulator and it's capacitors fixed the problem.

Since high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor

leads to these pins so there is no voltage drop in series with the input and output capacitors.

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RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit's

performance because of the small dimensions of the geometries inside the device. In applications where circuit

sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must

be taken to ensure that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the LP396X regulator (such as applications where the input

source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the

input pin of the LP396X.

If a load is connected to the LP396X output which switches at high speed (such as a clock), the high-frequency

current pulses required by the load must be supplied by the capacitors on the LP396X output. Since the

bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above

that frequency. The means the effective output impedance of the LP396X at frequencies above 100 kHz is

determined only by the output capacitor(s).

In applications where the load is switching at high speed, the output of the LP396X may need RF isolation from

the load. It is recommended that some inductance be placed between the LP396X output capacitor and the load,

and good RF bypass capacitors be placed directly across the load.

PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces.

Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At

MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the

ground plane.

In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not

radiate directly into adjacent layers which carry analog power and ground.

OUTPUT ADJUSTMENT

An adjustable output device has output voltage range of 1.216V to 5.1V. To obtain a desired output voltage, the

following equation can be used with R1 always a 10kΩresistor.

For output stability, CFmust be between 68pF and 100pF.

TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW

As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating

voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may

momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V

are not affected by this behavior.

OUTPUT NOISE

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at

a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a

function of frequency.

Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually

several decades of frequencies.

Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and

total output noise is measured in µV(rms).

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The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a

low frequency component and a high frequency component, which depend strongly on the silicon area and

quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the

current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a

smaller package. Increasing the current drawn by the internal reference increases the total supply current

(ground pin current). Using an optimized trade-off of ground pin current and die size, LP3963/LP3966 achieves

low noise performance and low quiescent current operation.

The total output noise specification for LP3963/LP3966 is presented in the Electrical Characteristics table. The

Output noise density at different frequencies is represented by a curve under typical performance characteristics.

SHORT-CIRCUIT PROTECTION

The LP3963 and LP3966 is short circuit protected and in the event of a peak over-current condition, the short-

circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts

down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the

thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the POWER

DISSIPATION/HEATSINKING for power dissipation calculations.

ERROR FLAG OPERATION

The LP3963/LP3966 produces a logic low signal at the Error Flag pin when the output drops out of regulation

due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing

diagram in Figure 21 shows the relationship between the ERROR flag and the output voltage. In this example,

the input voltage is changed to demonstrate the functionality of the Error Flag.

The internal Error flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high

through a pull up resistor. Although the ERROR flag pin can sink current of 1mA, this current is energy drain

from the input supply. Hence, the value of the pull up resistor should be in the range of 10kΩto 1MΩ.The

ERROR pin must be connected to ground if this function is not used. It should also be noted that when the

shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown

mode.

Figure 21. Error Flag Operation

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SENSE PIN

In applications where the regulator output is not very close to the load, LP3966 can provide better remote load

regulation using the SENSE pin. Figure 22 depicts the advantage of the SENSE option. LP3963 regulates the

voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the

drop across the trace resistance. For example, in the case of a 3.3V output, if the trace resistance is 100mΩ, the

voltage at the remote load will be 3V with 3A of load current, ILOAD. The LP3966 regulates the voltage at the

sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in

Figure 22. If the sense option pin is not required, the sense pin must be connected to the VOUT pin.

Figure 22. Improving remote load regulation using LP3966

SHUTDOWN OPERATION

A CMOS Logic level signal at the shutdown (SD) pin will turn-off the regulator. Pin SD must be actively

terminated through a 10kΩpull-up resistor for a proper operation. If this pin is driven from a source that actively

pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be

tied to Vin if not used.

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within

2% of the nominal output voltage. The LP3963/LP3966 use an internal MOSFET with an Rds(on) of 240mΩ

(typically). For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal

MOSFET.

REVERSE CURRENT PATH

The internal MOSFET in LP3963 and LP3966 has an inherent parasitic diode. During normal operation, the input

voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is

pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets

forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to

200mA continuous and 1A peak.

POWER DISSIPATION/HEATSINKING

LP3963 and LP3966 can deliver a continuous current of 3A over the full operating temperature range. A heatsink

may be required depending on the maximum power dissipation and maximum ambient temperature of the

application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

PD= (VIN−VOUT)IOUT+ (VIN)IGND

where IGND is the operating ground current of the device (specified under Electrical Characteristics).

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The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the

application, and the maximum allowable junction temperature (TJmax):

TRmax = TJmax−TAmax

The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the

formula:

θJA = TRmax / PD

LP3963 and LP3966 are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on

amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥

60 °C/W for TO-220 package and ≥60 °C/W for DDPAK/TO-263 package no heatsink is needed since the

package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these

limits, a heat sink is required.

HEATSINKING TO-220 PACKAGE

The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on

a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for

DDPAK/TO-263 package.

The heatsink to be used in the application should have a heatsink to ambient thermal resistance,

θHA≤ θJA − θCH − θJC.

In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal

resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for

θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value

is unknown, 2°C/W can be assumed.

HEATSINKING DDPAK/TO-263 PACKAGE

The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are

soldered to the copper plane for heat sinking. Figure 23 shows a curve for the θJA of DDPAK/TO-263 package for

different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area

for heat sinking.

Figure 23. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package

As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The

minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.

Figure 24 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient

temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.

Product Folder Links: LP3963 LP3966

LP3963, LP3966

SNVS067H –APRIL 2000–REVISED APRIL 2013

www.ti.com

Figure 24. Maximum power dissipation vs ambient temperature for DDPAK/TO-263 package

Product Folder Links: LP3963 LP3966

LP3963, LP3966

www.ti.com

SNVS067H –APRIL 2000–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision G (April 2013) to Revision H Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 15

Product Folder Links: LP3963 LP3966

PACKAGE OPTION ADDENDUM

www.ti.com 19-Nov-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3963ES-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3963ES

-2.5

LP3963ES-3.3 NRND DDPAK/

TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3963ES

-3.3

LP3963ES-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3963ES

-3.3

LP3963ESX-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3963ES

-2.5

LP3963ESX-3.3 NRND DDPAK/

TO-263 KTT 5 500 TBD Call TI Call TI -40 to 125 LP3963ES

-3.3

LP3963ESX-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3963ES

-3.3

LP3966ES-1.8 NRND DDPAK/

TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3966ES

-1.8

LP3966ES-1.8/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-1.8

LP3966ES-2.5 NRND DDPAK/

TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3966ES

-2.5

LP3966ES-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-2.5

LP3966ES-3.3 NRND DDPAK/

TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3966ES

-3.3

LP3966ES-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-3.3

LP3966ES-ADJ NRND DDPAK/

TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3966ES

-ADJ

LP3966ES-ADJ/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-ADJ

LP3966ESX-1.8 NRND DDPAK/

TO-263 KTT 5 500 TBD Call TI Call TI -40 to 125 LP3966ES

-1.8

LP3966ESX-1.8/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-1.8

LP3966ESX-2.5 NRND DDPAK/

TO-263 KTT 5 500 TBD Call TI Call TI -40 to 125 LP3966ES

-2.5

PACKAGE OPTION ADDENDUM

www.ti.com 19-Nov-2018

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3966ESX-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-2.5

LP3966ESX-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-3.3

LP3966ESX-ADJ/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3966ES

-ADJ

LP3966ET-ADJ NRND TO-220 NDH 5 45 TBD Call TI Call TI -40 to 125 LP3966ET

-ADJ

LP3966ET-ADJ/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3966ET

-ADJ

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 19-Nov-2018

Addendum-Page 3

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3963ESX-2.5/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3963ESX-3.3 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3963ESX-3.3/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3966ESX-1.8 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3966ESX-1.8/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3966ESX-2.5 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3966ESX-2.5/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3966ESX-3.3/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3966ESX-ADJ/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3963ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3963ESX-3.3 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3963ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3966ESX-1.8 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3966ESX-1.8/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3966ESX-2.5 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3966ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3966ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3966ESX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 2

MECHANICAL DATA

NDH0005D

www.ti.com

MECHANICAL DATA

KTT0005B

www.ti.com

BOTTOM SIDE OF PACKAGE

TS5B (Rev D)

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