R1
R2
D1
D2
RIN1-
RIN1+
RIN2+
RIN2-
DOUT2-
DOUT2+
DOUT1+
DOUT1-
ROUT1
ROUT2
DIN2
DIN1
AND EN
EN
EN
GND
VDD
EN
RIN1-
RIN1+
RIN2+
RIN2-
DOUT2-
DOUT2+
DOUT1+
DOUT1-
ROUT1
ROUT2
DIN2
DIN1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DS90LV049Q
www.ti.com
SNLS300D –MAY 2008–REVISED APRIL 2013
DS90LV049Q Automotive LVDS Dual Line Driver and Receiver Pair
Check for Samples: DS90LV049Q
1FEATURES DESCRIPTION
The DS90LV049Q is a dual CMOS flow-through
2• AECQ-100 Grade 1 differential line driver-receiver pair designed for
• Up to 400 Mbps Switching Rates applications requiring ultra low power dissipation,
• Flow-Through Pinout Simplifies PCB Layout exceptional noise immunity, and high data
throughput. The device is designed to support data
• 50 ps Typical Driver Channel-to-Channel Skew rates in excess of 400 Mbps utilizing Low Voltage
• 50 ps Typical Receiver Channel-to-Channel Differential Signaling (LVDS) technology.
Skew The DS90LV049Q drivers accept LVTTL/LVCMOS
• 3.3 V Single Power Supply Design signals and translate them to LVDS signals. The
• TRI-STATE Output Control receivers accept LVDS signals and translate them to
• Internal Fail-Safe Biasing of Receiver Inputs 3 V CMOS signals. The LVDS input buffers have
internal failsafe biasing that places the outputs to a
• Low Power Dissipation (70 mW at 3.3 V Static) known H (high) state for floating receiver inputs. In
• High Impedance on LVDS Outputs on Power addition, the DS90LV049Q supports a TRI-STATE
Down function for a low idle power state when the device is
• Conforms to TIA/EIA-644-A LVDS Standard not in use.
• Available in Low Profile 16 Pin TSSOP The EN and EN inputs are ANDed together and
Package control the TRI-STATE outputs. The enables are
common to all four gates.
Connection Diagram Functional Diagram
Figure 1. TSSOP Package
See Package Number PW0016A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS90LV049Q
SNLS300D –MAY 2008–REVISED APRIL 2013
www.ti.com
Truth Table
EN EN LVDS Out LVCMOS Out
L or Open L or Open OFF OFF
H L or Open ON ON
L or Open H OFF OFF
H H OFF OFF
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VDD)−0.3 V to +4 V
LVCMOS Input Voltage (DIN)−0.3 V to (VDD + 0.3 V)
LVDS Input Voltage (RIN+, RIN-)−0.3 V to +3.9 V
Enable Input Voltage (EN, EN) −0.3 V to (VDD + 0.3 V)
LVCMOS Output Voltage (ROUT)−0.3 V to (VDD + 0.3 V)
LVDS Output Voltage (DOUT+, DOUT-)−0.3 V to +3.9 V
LVCMOS Output Short Circuit Current (ROUT) 100 mA
LVDS Output Short Circuit Current (DOUT+, DOUT−) 24 mA
LVDS Output Short Circuit Current Duration (DOUT+, DOUT−) Continuous
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Junction Temperature +135°C
Maximum Package Power Dissipation @ +25°C
PW0016A Package 1146 mW
Derate PW0016A Package 10.4 mW/°C above +25°C
Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θJA 96.0°C/W
θJC 30.0°C/W
ESD Rating
HBM (3) ≥8 kV
MM (4) ≥250 V
CDM (5) ≥1250 V
(1) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions Min Typ Max Units
Supply Voltage (VDD) +3.0 +3.3 +3.6 V
Operating Free Air Temperature (TA)−40 +25 +125 °C
2Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q
DS90LV049Q
www.ti.com
SNLS300D –MAY 2008–REVISED APRIL 2013
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (1)(2)(3)
Parameter Test Conditions Pin Min Typ Max Units
LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)
VIH Input High Voltage 2.0 VDD V
VIL Input Low Voltage GND 0.8 V
DIN
IIH Input High Current VIN = VDD EN −10 1 +10 μA
EN
IIL Input Low Current VIN = GND −10 −0.1 +10 μA
VCL Input Clamp Voltage ICL =−18 mA −1.5 −0.6 V
LVDS Output DC Specifications (Driver Outputs)
| VOD | Differential Output Voltage 250 350 450 mV
ΔVOD Change in Magnitude of VOD for 1 35 |mV|
Complementary Output States RL= 100 Ω
(Figure 2)
VOS Offset Voltage 1.125 1.23 1.375 V
ΔVOS Change in Magnitude of VOS for 1 25 |mV|
Complementary Output States
IOS Output Short Circuit Current (4) ENABLED, −5.8 −9.0 mA
DOUT−
DIN = VDD, DOUT+ = 0 V or DOUT+
DIN = GND, DOUT−= 0 V
IOSD Differential Output Short Circuit −5.8 −9.0 mA
ENABLED, VOD = 0 V
Current (4)
IOFF Power-off Leakage VOUT = 0 V or 3.6 V −20 ±1 +20 μA
VDD = 0 V or Open
IOZ Output TRI-STATE Current EN = 0 V and EN = VDD −10 ±1 +10 μA
VOUT = 0 V or VDD
LVDS Input DC Specifications (Receiver Inputs)
VTH Differential Input High Threshold −15 35 mV
VCM = 1.2 V, 0.05 V, 2.35 V
VTL Differential Input Low Threshold -100 −15 mV
VCMR Common-Mode Voltage Range VID = 100 mV, VDD=3.3 V 0.05 3 V
RIN+
VDD=3.6 V RIN- −12 ±4 +12 μA
VIN =0 V or 2.8 V
IIN Input Current VDD=0 V −10 ±1 +10 μA
VIN =0 V or 2.8 V or 3.6 V
LVCMOS Output DC Specifications (Receiver Outputs)
VOH Output High Voltage IOH = -0.4 mA, VID= 200 mV 2.7 3.3 V
VOL Output Low Voltage IOL = 2 mA, VID = 200 mV ROUT 0.05 0.25 V
IOZ Output TRI-STATE Current Disabled, VOUT =0 V or VDD -10 ±1 +10 μA
General DC Specifications
IDD Power Supply Current (5) EN = 3.3 V 21 35 mA
VDD
IDDZ TRI-State Supply Current EN = 0 V 15 25 mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VTH, VTL, VOD and ΔVOD.
(2) All typical values are given for: VDD = +3.3 V, TA= +25°C.
(3) The DS90LV049Q drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to
their outputs. The typical range of the resistor values is 90 Ωto 110 Ω.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
(5) Both driver and receiver inputs are static. All LVDS outputs have 100 Ωload. All LVCMOS outputs are floating. None of the outputs
have any lumped capacitive load.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS90LV049Q
DS90LV049Q
SNLS300D –MAY 2008–REVISED APRIL 2013
www.ti.com
Switching Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (1)(2)
Parameter Test Conditions Min Typ Max Units
LVDS Outputs (Driver Outputs)
tPHLD Differential Propagation Delay High to Low 0.7 2 ns
tPLHD Differential Propagation Delay Low to High 0.7 2 ns
tSKD1 Differential Pulse Skew |tPHLD −tPLHD|(3) (4) 0 0.05 0.4 ns
RL= 100 Ω
tSKD2 Differential Channel-to-Channel Skew (3) (5) 0 0.05 0.5 ns
(Figure 3 and Figure 4)
tSKD3 Differential Part-to-Part Skew (3) (6) 0 1.0 ns
tTLH Rise Time (3) 0.2 0.4 1 ns
tTHL Fall Time (3) 0.2 0.4 1 ns
tPHZ Disable Time High to Z 1.5 3 ns
tPLZ Disable Time Low to Z 1.5 3 ns
RL= 100 Ω
(Figure 5 and Figure 6)
tPZH Enable Time Z to High 1 3 6 ns
tPZL Enable Time Z to Low 1 3 6 ns
fMAX Maximum Operating Frequency (7) 250 MHz
LVCMOS Outputs (Receiver Outputs)
tPHL Propagation Delay High to Low 0.5 2 3.5 ns
tPLH Propagation Delay Low to High 0.5 2 3.5 ns
tSK1 Pulse Skew |tPHL −tPLH|(8) 0 0.05 0.4 ns
tSK2 Channel-to-Channel Skew (9) (Figure 7 and Figure 8) 0 0.05 0.5 ns
tSK3 Part-to-Part Skew (10) 0 1.0 ns
tTLH Rise Time(3) 0.3 0.9 1.4 ns
tTHL Fall Time(3) 0.3 0.75 1.4 ns
tPHZ Disable Time High to Z 3 5.6 8 ns
tPLZ Disable Time Low to Z 3 5.4 8 ns
(Figure 9 and Figure 10)
tPZH Enable Time Z to High 2.5 4.6 7 ns
tPZL Enable Time Z to Low 2.5 4.6 7 ns
fMAX Maximum Operating Frequency (11) 250 MHz
(1) All typical values are given for: VDD = +3.3 V, TA= +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50 Ω, tr≤1 ns, and tf≤1 ns.
(3) These parameters are ensured by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage, temperature) ranges.
(4) tSKD1 or differential pulse skew is defined as |tPHLD −tPLHD|. It is the magnitude difference in the differential propagation delays between
the positive going edge and the negative going edge of the same driver channel.
(5) tSKD2 or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two
driver channels on the same device.
(6) tSKD3 or differential part-to-part skew is defined as |tPLHD Max −tPLHD Min| or |tPHLD Max −tPHLD Min|. It is the difference between the
minimum and maximum specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of
each other within the operating temperature range.
(7) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, VOD >
250 mV, all channels switching.
(8) tSK1 or pulse skew is defined as |tPHL −tPLH|. It is the magnitude difference in the propagation delays between the positive going edge
and the negative going edge of the same receiver channel.
(9) tSK2 or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the
same device.
(10) tSK3 or part-to-part skew is defined as |tPLH Max −tPLH Min| or |tPHL Max −tPHL Min|. It is the difference between the minimum and maximum
specified propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating
temperature range.
(11) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V . Output Criteria: duty cycle =
45%/55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching.
4Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q
Transmission Line
Transmission Line
DC Block
DC Block
Signal
Generator Transmission Line D
50 :
50 :
50 :
Oscilloscope
Z0 = 50 :
C = 15 pF Distributed
Z0 = 50 :
C = 15 pF Distributed
DIN
DOUT+
DOUT-
Power
Supply VDD EN
100 :
SMU
SMU
SMU D
DIN
DOUT+
DOUT-
Power
Supply VDD EN
100 :
DS90LV049Q
www.ti.com
SNLS300D –MAY 2008–REVISED APRIL 2013
Parameter Measurement Information
Figure 2. Driver VOD and VOS Test Circuit
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS90LV049Q
Transmission Line
Power
Supply
R
950 :50 :
Oscilloscope
Z0 = 50 :
C = 15 pF Distributed
EN
ROUT
Power
Supply
Transmission Line
100 :
Z0 = 50 :
C = 15 pF Distributed RIN+
Signal
Generator Transmission Line
RIN-
VDD
Transmission Line
Transmission Line
Signal
Generator Transmission Line
D
50 :
50 :
50 :
Oscilloscope
Z0 = 50 :
C = 15 pF Distributed
Z0 = 50 :
C = 15 pF Distributed
EN
DOUT+
DOUT-
3.3 V DIN
VDD
100 :
2.4 V
1 k:
1 k:
950 :
950 :
Power Supplies
2.4 V
DS90LV049Q
SNLS300D –MAY 2008–REVISED APRIL 2013
www.ti.com
Parameter Measurement Information (continued)
Figure 5. Driver TRI-STATE Delay Test Circuit
Figure 6. Driver TRI-STATE Delay Waveform
Figure 7. Receiver Propagation Delay and Transition Time Test Circuit
6Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q
Transmission Line
Signal
Generator Transmission Line
R
50 :
950 :
50 :
Oscilloscope
Z0 = 50 :
C = 15 pF Distributed
Z0 = 50 :
C = 15 pF Distributed
EN
ROUT
1.4 V 100 :
RIN+
1.0 V RIN-
VDD
Power Supplies
2.5 V 1 k:
DS90LV049Q
www.ti.com
SNLS300D –MAY 2008–REVISED APRIL 2013
Parameter Measurement Information (continued)
Figure 8. Receiver Propagation Delay and Transition Time Waveforms
Figure 9. Receiver TRI-STATE Delay Test Circuit
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DS90LV049Q
EN
EN
1.5 V
3 V
0 V
tPLZ
tPHZ
0.5 V
0.5 V
1.5 V 1.5 V
1.5 V
tPZL
tPZH
VDD / 2
VOL
VDD / 2
VOH
50%
50%
OUT
OUT
0 V
3 V
DS90LV049Q
SNLS300D –MAY 2008–REVISED APRIL 2013
www.ti.com
Parameter Measurement Information (continued)
Figure 10. Receiver TRI-STATE Delay Waveforms
Typical Application
Figure 11. Point-to-Point Application
APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes: LVDS Owner's Manual (lit #550062-003), AN-805 (SNOA233), AN-808 (SNLA028), AN-903 (SNLA034),
AN-916 (SNLA219, AN-971(SNLA165), AN-977 (SNLA166).
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 11. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100 Ω. A termination resistor of 100 Ω(selected to match the media), and is located as close to
the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into
a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be taken into account.
The TRI-STATE function allows the device outputs to be disabled, thus obtaining an even lower power state
when the transmission of data is not required.
8Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q
DS90LV049Q
www.ti.com
SNLS300D –MAY 2008–REVISED APRIL 2013
The DS90LV049Q has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1 μF and 0.001 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple
vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or greater solid
tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply
and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (that is,
cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they
leave the IC (stubs should be < 10 mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than
traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
TERMINATION
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90 Ωand 130 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs should be minimized. The distance between the termination resistor and the receiver
should be < 10 mm (12 mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DS90LV049Q
DS90LV049Q
SNLS300D –MAY 2008–REVISED APRIL 2013
www.ti.com
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100 Ω. They should not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple
coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling
effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is
rejected by the receiver.
FAIL-SAFE FEATURE
An LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating receiver inputs.
The DS90LV049Q has two receivers, and if an application requires a single receiver, the unused receiver inputs
should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by
internal high value pull up and pull down current sources to set the output to a HIGH state. This internal circuitry
will ensure a HIGH, stable output state for open inputs.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pull up and pull down resistors should be in the 5 kΩto 15 kΩrange to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
For more information on failsafe biasing of LVDS interfaces, please refer to AN-1194 (SNLA051).
PIN DESCRIPTIONS
Pin No. Name Description
10, 11 DIN Driver input pins, LVCMOS levels. There is a pull-down current source present.
6, 7 DOUT+ Non-inverting driver output pins, LVDS levels.
5, 8 DOUT−Inverting driver output pins, LVDS levels.
2, 3 RIN+ Non-inverting receiver input pins, LVDS levels. There is a pull-up current source present.
1, 4 RIN- Inverting receiver input pins, LVDS levels. There is a pull-down current source present.
14, 15 ROUT Receiver output pins, LVCMOS levels.
9, 16 EN, EN Enable and Disable pins. There are pull-down current sources present at both pins.
12 VDD Power supply pin.
13 GND Ground pin.
10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q
40 60 80 100 120 140 160
Resistor Load - RL [:]
0.25
0.30
0.35
0.40
0.45
Differential Output Voltage - VOD [V]
VDD = 3.3 V
TA = 25o C
DS90LV049Q
www.ti.com
SNLS300D –MAY 2008–REVISED APRIL 2013
Typical Performance Curves
Differential Output Voltage Power Supply Current
vs vs
Load Resistor Frequency
Figure 12. Figure 13.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DS90LV049Q
DS90LV049Q
SNLS300D –MAY 2008–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90LV049QMT/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 90LV049
QMT
DS90LV049QMTX/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 90LV049
QMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90LV049QMTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90LV049QMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated