4-269
File Number
2314.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRFD110
1A, 100V, 0.600 Ohm, N-Channel Power
MOSFET
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17441.
Features
1A, 100V
•r
DS(ON) = 0.600
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
HEXDIP
Ordering Information
PART NUMBER PACKAGE BRAND
IRFD110 HEXDIP IRFD110
NOTE: When ordering, use the entire part number. G
D
S
SOURCE
GATE
DRAIN
Data Sheet July 1999
4-270
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
IRFD110 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID1.0 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 8.0 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D1.0 W
Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.008 W/oC
Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 19 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T
STG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 9) 100 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 1.0 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 0.8A, VGS = 10V (Figures 7, 8) - 0.5 0.6
Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = 0.8A (Figure 11) 0.8 1.2 - S
Turn-On Delay Time td(ON) VDD = 0.5 x Rated BVDSS, ID 1.0A,
RG = 9.1Ω, RL = 50
MOSFET Switching Times are Essentially
Independent of Operating Temperature
-1020ns
Rise Time tr-1525ns
Turn-Off Delay Time td(OFF) -1525ns
Fall Time tf-1020ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID 1.0A, VDS = 0.8 x Rated BVDSS,
Ig(REF) = 1.5mA (Figure 13)
Gate Charge is Essentially Independent of
Operating Temperature
- 5.0 7.0 nC
Gate to Source Charge Qgs - 2.0 - nC
Gate to Drain “Miller” Charge Qgd - 3.0 - nC
Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1MHz
(Figure 10) - 135 - pF
Output Capacitance COSS -80-pF
Reverse Transfer Capacitance CRSS -20-pF
Internal Drain Inductance LDMeasured from the Drain
Lead, 2mm (0.08in) from
Package to Center of Die
Modified MOSFET
Symbol Showing the
Internal Device’s
Inductances
- 4.0 - nH
Internal Source Inductance LSMeasured from the Source
Lead, 2mm (0.08in) from
Header to Source Bonding
Pad
- 6.0 - nH
Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 120 oC/W
LS
LD
G
D
S
IRFD110
4-271
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Diode
- - 1.0 A
Pulse Source to Drain Current (Note 4) ISDM - - 8.0 A
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 1.0A, V GS = 0V (Figure 12) - - 2.5 V
Reverse Recovery Time trr TJ = 150oC, ISD = 1.0A, dISD/dt = 100A/µs - 100 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = 1.0A, dISD/dt = 100A/µs - 0.2 - µC
NOTES:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. VDD = 25V, starting TJ= 25oC, L = 28.5mH, RG= 25Ω, peak IAS = 1.0A.
4. Repetitive rating: pulse width limited by maximum junction temperature.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. OUTPUT CHARACTERISTICS
G
D
S
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 TA, AMBIENT TEMPERATURE (oC)
50 75 10025 150
1.0
0.8
0.6
0
0.4
ID, DRAIN CURRENT (A)
0.2
125
VDS, DRAIN TO SOURCE VOLTAGE (V)
1
ID, DRAIN CURRENT (A)
100
0.1
101
0.01
1ms
10ms
100ms
100µs
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
DC
10
TJ = MAX RATED
ID, DRAIN CURRENT (A)
010203040
1
2
3
4
5
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
0VGS = 4V
VGS = 5V
VGS = 7V
PULSE DURATION = 80µs
VGS = 10V
VGS = 8V
VGS = 6V
VGS = 9V DUTY CYCLE = 0.5% MAX
IRFD110
4-272
FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
ID, DRAIN CURRENT (A)
01 2 3 4
1
2
3
4
5
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
VGS = 9V
VGS = 4V
VGS = 5V
VGS = 7V
VGS = 10V
VGS = 8V
VGS = 6V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
5
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
4
3
2
08642010
1
TJ = 25oC
TJ = 125oC
TJ = -55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS > ID(ON) x rDS(ON)MAX
0
1.0
2.0
246
rDS(ON), DRAIN TO SOURCE
ID, DRAIN CURRENT (A) 80
0.5
1.5
VGS = 10V
VGS = 20V
ON RESISTANCE ()
DUTY CYCLE = 0.5% MAX
2µs PULSE TEST
NORMALIZED DRAIN TO SOURCE
2.5
1.5
1.0
0.5
0
-60 -20 40
TJ, JUNCTION TEMPERATURE (oC) 120 140
2.0
80 100
60200-40
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 0.8A
1.25
0.95
0.85
0.75
-60 -20 20
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
60 100 140
1.05
1.15
-40 0 40 80 120
ID = 250µA500
100
0020 50
C, CAPACITANCE (pF)
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
400
200
10 30
CISS
COSS
CRSS
40
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
IRFD110
4-273
FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
01234
0.8
1.5
2.4
3.2
4.0
5
0
TJ = -55oC
TJ = 25oC
TJ = 125oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
00.6 1.0 1.4 1.60.2
0.1
1.0
2
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
10
0.4 1.2
TJ = 25oC
TJ = 150oC
5
5
2
1.8 2.00.8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
QG, GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
04610
5
15
20 ID = 1A
10
028
VDS = 80V
VDS = 50V
VDS = 20V
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
IRFD110
4-274
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
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FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
VGS
RL
RG
DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50k
VDS
S
DUT
D
G
Ig(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
Ig(REF)
0
IRFD110