M16C/6NK - Renesas Technology / Hitachi Semiconductor

Rev.1.10 Jul 01, 2005 page 1 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0058-0110

Rev.1.10

Jul 01, 2005

Under development

This document is under development and its contents are subject to change

Specifications written in this manual are believed to be accurate, but are not

guaranteed to be entirely free of error. Specifications in this manual may be

changed for functional or performance improvements. Please make sure your

manual is the latest edition.

1. Overview

The M16C/6N Group (M16C/6NK, M16C/6NM) of single-chip microcomputers are built using the

high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in

100-pin and 128-pin plastic molded LQFP. These single-chip microcomputers operate using sophisticated

instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable

of executing instructions at high speed. Being equipped with two CAN (Controller Area Network) modules in

M16C/6N Group (M16C/6NK, M16C/6NM), the microcomputer is suited to car audio and industrial control

systems. The CAN modules comply with the 2.0B specification. In addition, this microcomputer contains a

multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control

of various OA and communication equipment which requires high-speed arithmetic/logic operations.

1.1 Applications

Car audio and industrial control systems, other

Rev.1.10 Jul 01, 2005 page 2 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

1.2 Performance Outline

Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NK, M16C/6NM).

Table 1.1 Performance Outline of M16C/6N Group (100-pin Version: M16C/6NK)

Item Performance

Normal-ver. T/V-ver.

CPU Number of Basic Instructions 91 instructions

Minimum Instruction 41.7ns (f(BCLK) = 24MHz, 50.0ns (f(BCLK) = 20MHz,

Execution Time

1/1 prescaler, without software wait) 1/1 prescaler, without software wait)

Operation Mode Single-chip mode

Address Space 1 Mbyte

Memory Capacity See Table 1.3 Product List

Peripheral Port Input/Output: 87 pins, Input: 1 pin

Function Multifunction Timer Timer A: 16 bits ✕ 5 channels

Timer B: 16 bits ✕ 6 channels

Three-phase motor control circuit

Serial I/O 3 channels

Clock synchronous, UART, I2C-bus (1), IEBus (2)

2 channels

Clock synchronous

A/D Converter 10-bit A/D converter: 1 circuit, 26 channels

D/A Converter 8 bits ✕ 2 channels

DMAC 2 channels

CRC Calculation Circuit CRC-CCITT

CAN Module 2 channels with 2.0B specification

Watchdog Timer 15 bits ✕ 1 channel (with prescaler)

Interrupt Internal: 32 sources, External: 9 sources

Software: 4 sources, Priority level: 7 levels

Clock Generating Circuit 4 circuits

• Main clock oscillation circuit (*)

• Sub clock oscillation circuit (*)

• On-chip oscillator

• PLL frequency synthesizer

(*) Equipped with a built-in feedback resistor

Oscillation Stop Detection Main clock oscillation stop and re-oscillation detection function

Function

Electrical Supply Voltage

VCC = 3.0 to 5.5V (f(BCLK) = 24MHz, VCC = 4.2 to 5.5V (f(BCLK) = 20MHz,

Characteristics

1/1 prescaler, without software wait) 1/1 prescaler, without software wait)

Power Mask ROM 21mA (f(BCLK) = 24MHz, -

Consumption PLL operation, no division)

Flash Memory

23mA (f(BCLK) = 24MHz, 21mA (f(BCLK) = 20MHz,

PLL operation, no division) PLL operation, no division)

Mask ROM 3µA

(f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)

Flash Memory

0.8µA (Stop mode, Topr = 25°C)

Flash Memory Program/Erase Supply Voltage

3.0 ± 0.3V or 5.0 ± 0.5V 5.0 ± 0.5V

Version

Program and Erase Endurance

100 times

I/O I/O Withstand Voltage 5.0V

Characteristics

Output Current 5mA

Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C

V version: -40 to 125°C

(option)

Device Configuration CMOS high performance silicon gate

Package 100-pin plastic mold LQFP

NOTES:

1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

option: All options are on request basis.

Rev.1.10 Jul 01, 2005 page 3 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NM)

Item Performance

Normal-ver. T/V-ver.

CPU Number of Basic Instructions 91 instructions

Minimum Instruction 41.7ns (f(BCLK) = 24MHz, 50.0ns (f(BCLK) = 20MHz,

Execution Time

1/1 prescaler, without software wait) 1/1 prescaler, without software wait)

Operation Mode Single-chip mode

Address Space 1 Mbyte

Memory Capacity See Table 1.3 Product List

Peripheral Port Input/Output: 113 pins, Input: 1 pin

Function Multifunction Timer Timer A: 16 bits ✕ 5 channels

Timer B: 16 bits ✕ 6 channels

Three-phase motor control circuit

Serial I/O 3 channels

Clock synchronous, UART, I2C-bus (1), IEBus (2)

4 channels

Clock synchronous

A/D Converter 10-bit A/D converter: 1 circuit, 26 channels

D/A Converter 8 bits ✕ 2 channels

DMAC 2 channels

CRC Calculation Circuit CRC-CCITT

CAN Module 2 channels with 2.0B specification

Watchdog Timer 15 bits ✕ 1 channel (with prescaler)

Interrupt Internal: 34 sources, External: 12 sources

Software: 4 sources, Priority level: 7 levels

Clock Generating Circuit 4 circuits

• Main clock oscillation circuit (*)

• Sub clock oscillation circuit (*)

• On-chip oscillator

• PLL frequency synthesizer

(*) Equipped with a built-in feedback resistor

Oscillation Stop Detection Main clock oscillation stop and re-oscillation detection function

Function

Electrical Supply Voltage

VCC = 3.0 to 5.5V (f(BCLK) = 24MHz, VCC = 4.2 to 5.5V (f(BCLK) = 20MHz,

Characteristics

1/1 prescaler, without software wait) 1/1 prescaler, without software wait)

Power Mask ROM 21mA (f(BCLK) = 24MHz, -

Consumption PLL operation, no division)

Flash Memory

23mA (f(BCLK) = 24MHz, 21mA (f(BCLK) = 20MHz,

PLL operation, no division) PLL operation, no division)

Mask ROM 3µA

(f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)

Flash Memory

0.8µA (Stop mode, Topr = 25°C)

Flash Memory Program/Erase Supply Voltage

3.0 ± 0.3V or 5.0 ± 0.5V 5.0 ± 0.5V

Version

Program and Erase Endurance

100 times

I/O I/O Withstand Voltage 5.0V

Characteristics

Output Current 5mA

Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C

V version: -40 to 125°C

(option)

Device Configuration CMOS high performance silicon gate

Package 128-pin plastic mold LQFP

NOTES:

1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

option: All options are on request basis.

Rev.1.10 Jul 01, 2005 page 4 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

1.3 Block Diagram

Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NK, M16C/6NM).

Figure 1.1 Block Diagram

NOTES:

1: ROM size depends on microcomputer type.

2: RAM size depends on microcomputer type.

3: Ports P11 to P14 are only in the 128-pin version.

4: 8 bits ✕ 2 channels in the 100-pin version.

Port P11

(3)

Port P14

(3)

Port P12

(3)

Port P13

(3)

Timer (16 bits)

Output (timer A): 5

Input (timer B): 6

Three-phase motor

control circuit

Internal peripheral functions

Watchdog timer

(15 bits)

A/D converter

(10 bits ✕ 8 channels

Expandable up to 26 channels)

UART or

Clock synchronous serial I/O

(3 channels)

System clock generating circuit

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator

Port P0

Port P1

Port P2

8 8 8 8

Port P6

8788

Port P10

Port P9

Port P8_5

Port P8

Port P7

Port P5Port P4Port P3

CRC arithmetic circuit (CCITT)

(Polynomial: X

+1)

Clock synchronous serial I/O

(8 bits ✕ 4 channels)

(4)

CAN module

(2 channels)

DMAC

(2 channels)

D/A converter

(8 bits ✕ 2 channels)

MemoryM16C/60 series CPU core

R0H R0L

R1H R1L

Multiplier

INTB

USP

ISP

FLG

ROM

(1)

RAM

(2)

Rev.1.10 Jul 01, 2005 page 5 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

1.4 Product List

Table 1.3 lists the M16C/6N Group (M16C/6NK, M16C/6NM) products and Figure 1.2 shows the type numbers,

memory sizes and packages.

Table 1.3 Product List As of Jul. 2005

Type No.

M30 6N K

M G T

XXX GP

Package type:

GP: Package PLQP0100KB-A, PLQP0128KB-A

ROM No.

Omitted on flash memory version

Characteristics

(no): Normal-ver.

T : T-ver. (Automotive 85°C version)

V : V-ver. (Automotive 125°C version)

ROM capacity:

E : 192 Kbytes

G: 256 Kbytes

H : 384 Kbytes

J : 512 Kbytes

Memory type:

M : Mask ROM version

F : Flash memory version

Shows the number of CAN module, pin count, etc.

6N Group

M16C Family

Type No. ROM Capacity RAM Capacity Package Type Remarks

M306NKFHGP 384 K + 4 Kbytes 31 Kbytes PLQP0100KB-A Flash Normal-ver.

M306NMFHGP PLQP0128KB-A memory

M306NKFJGP (D) 512 K + 4 Kbytes 31 Kbytes PLQP0100KB-A version

M306NMFJGP PLQP0128KB-A

M306NKFHTGP (D) 384 K + 4 Kbytes 31 Kbytes PLQP0100KB-A T-ver.

M306NMFHTGP (D) PLQP0128KB-A

M306NKFJTGP (D) 512 K + 4 Kbytes 31 Kbytes PLQP0100KB-A

M306NMFJTGP (D) PLQP0128KB-A

M306NKFHVGP (D) 384 K + 4 Kbytes 31 Kbytes PLQP0100KB-A V-ver.

M306NMFHVGP (D) PLQP0128KB-A

M306NKFJVGP (D) 512 K + 4 Kbytes 31 Kbytes PLQP0100KB-A

M306NMFJVGP (D) PLQP0128KB-A

M306NKME-XXXGP 192 Kbytes 16 Kbytes PLQP0100KB-A Mask Normal-ver.

M306NMME-XXXGP PLQP0128KB-A ROM

M306NKMG-XXXGP 256 Kbytes 20 Kbytes PLQP0100KB-A version

M306NMMG-XXXGP PLQP0128KB-A

(D): Under development

Figure 1.2 Type No., Memory Size, and Package

Rev.1.10 Jul 01, 2005 page 6 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

PIN CONFIGURATION (top view)

Figure 1.3 Pin Configuration (Top View) (1)

1.5 Pin Configuration

Figures 1.3 and 1.4 show the pin configuration (top view).

1 2 3 4 5 6 7 8 9 10111213141516171819202122232425

515253545556

57585960616263646566676869707172737475

100

P0_0/AN0_0

P0_1/AN0_1

P0_2/AN0_2

P0_3/AN0_3

P0_4/AN0_4

P0_5/AN0_5

P0_6/AN0_6

P0_7/AN0_7

P1_0

P1_1

P1_2

P1_3

P1_4

VREF

AVSS

VCC1

XIN

XOUT

VSS

RESET

CNVSS

P8_7/XCIN

P8_6/XCOUT

BYTE P2_0/AN2_0

P2_1/AN2_1

P2_2/AN2_2

P2_3/AN2_3

P2_4/AN2_4

P2_5/AN2_5

P2_6/AN2_6

P2_7/AN2_7

P3_0

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

P4_0

P4_1

P4_2

P4_3

P7_4/TA2OUT/W/(CLK4)

P7_6/TA3OUT/CTX1

P5_6

P7_7/TA3IN/CRX1

P5_5

P5_4

P5_3

P5_2

VCC2

VSS

P5_7/CLKOUT

P4_5

P4_6

P4_7

AVCC

P6_3/TXD0/SDA0

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P6_1/CLK0

P6_2/RXD0/SCL0

P10_0/AN0

P10_1/AN1

P10_2/AN2

P10_3/AN3

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

P9_5/ANEX0/CRX0/CLK4

P9_6/ANEX1/CTX0/SOUT4

(1)

P9_1/TB1IN/SIN3

P9_2/TB2IN/SOUT3

P8_0/TA4OUT/U/(SIN4)

P6_0/CTS0/RTS0

P6_4/CTS1/RTS1/CTS0/CLKS1

P8_2/INT0

P8_3/INT1

P8_5/NMI

P9_7/ADTRG/SIN4

P4_4

P5_0

P5_1

P9_0/TB0IN/CLK3

P8_4/INT2/ZP

P7_2/CLK2/TA1OUT/V

P7_1/RXD2/SCL2/TA0IN/TB5IN

(1)

P7_0/TXD2/SDA2/TA0OUT

P7_5/TA2IN/W/(SOUT4)

P7_3/CTS2/RTS2/TA1IN/V

P1_5/INT3

P1_6/INT4

P1_7/INT5

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P8_1/TA4IN/U

M16C/6N Group

(M16C/6NK)

Package: PLQP0100KB-A

NOTE:

1. P7_1 and P9_1 are N channel open-drain pins.

Rev.1.10 Jul 01, 2005 page 7 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

PIN CONFIGURATION (top view)

Figure 1.4 Pin Configuration (Top View) (2)

737475767778798081828384858687888990919293949596979899

100101102

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128 39

104

105

106

107

108

31 32 33 34 35 36 37

66676869707172

103

P5_7/CLKOUT

P9_5/ANEX0/CRX0/CLK4

P9_6/ANEX1/CTX0/SOUT4

P14_1

P14_0

P13_7/INT8

P13_6/INT7

P13_5/INT6

P13_4

P1_3

P1_4

P1_5/INT3

P1_6/INT4

P1_7/INT5

P11_3

P11_2/SOUT5

P11_1/SIN5

P11_0/CLK5

VCC1

VSS

P13_0

P13_1

P13_2

P13_3

P12_5

P12_6

P12_7

P11_4

P11_5/CLK6

P11_6/SOUT6

P11_7/SIN6

M16C/6N Group

(M16C/6NM)

21 22 23 24 25 26 27 28 29 3011 12 13 14 15 16 17 18 19 2012345678910

P1_1

P1_2

P2_0/AN2_0

P2_1/AN2_1

P2_2/AN2_2

P2_3/AN2_3

P2_4/AN2_4

P2_5/AN2_5

P2_6/AN2_6

P2_7/AN2_7

P3_0

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

P4_0

P4_1

P4_2

P4_3

P4_4

P12_0

P12_1

P12_2

P12_3

P12_4

P4_5

P4_6

P4_7

VCC2

VSS

P5_6

P5_5

P5_4

P5_3

P5_2

P6_3/TXD0/SDA0

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P6_1/CLK0

P6_2/RXD0/SCL0

P6_0/CTS0/RTS0

P6_4/CTS1/RTS1/CTS0/CLKS1

P5_0

P5_1

P7_2/CLK2/TA1OUT/V

(1) P7_1/RXD2/SCL2/TA0IN/TB5IN

P7_0/TXD2/SDA2/TA0OUT

VCC1

P7_4/TA2OUT/W/(CLK4)

P7_6/TA3OUT/CTX1

P7_7/TA3IN/CRX1

P8_0/TA4OUT/U/(SIN4)

P8_2/INT0

P8_3/INT1

P8_5/NMI

P8_4/INT2/ZP

P7_5/TA2IN/W/(SOUT4)

P7_3/CTS2/RTS2/TA1IN/V

P8_1/TA4IN/U

XIN

XOUT

VSS

RESET

CNVSS

P8_7/XCIN

P8_6/XCOUT

BYTE

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

(1)

P9_1/TB1IN/SIN3

P9_2/TB2IN/SOUT3

P9_0/TB0IN/CLK3

P9_7/ADTRG/SIN4

P0_0/AN0_0

P0_1/AN0_1

P0_2/AN0_2

P0_3/AN0_3

P0_4/AN0_4

P0_5/AN0_5

P0_6/AN0_6

P0_7/AN0_7

P1_0

VREF

AVSS

AVCC

P10_0/AN0

P10_1/AN1

P10_2/AN2

P10_3/AN3

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

Package: PLQP0128KB-ANOTE:

1. P7_1 and P9_1 are N channel open-drain pins.

Rev.1.10 Jul 01, 2005 page 8 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

1.6 Pin Description

Tables 1.4 and 1.5 list the pin descriptions.

Table 1.4 Pin Description (100-pin and 128-pin Versions) (1)

I/O

VCC1, VCC2,

VSS

AVCC, AVSS

_____________

RESET

CNVSS

BYTE

XIN

XOUT

XCIN

XCOUT

CLKOUT

________ ________

INT0 to INT8 (3)

________

NMI

______ ______

KI0 to KI3

TA0OUT to TA4OUT

TA0IN to TA4IN

TB0IN to TB5IN

___ ___ ____

U, U, V, V, W, W

__________ __________

CTS0 to CTS2

__________ __________

RTS0 to RTS2

CLK0 to CLK6 (3)

RXD0 to RXD2

SIN3 to SIN6 (3)

TXD0 to TXD2

SOUT3 to SOUT6 (3)

CLKS1

SDA0 to SDA2

SCL0 to SCL2

Power supply

input

Analog power

supply input

Reset input

CNVSS

External data

bus width

select input

Main clock

input

Main clock

output

Sub clock

input

Sub clock

output

Clock output

______

INT interrupt input

_______

NMI interrupt

input

Key input

interrupt input

Timer A

Timer B

Three-phase motor

control output

Serial I/O

I2C mode

Apply 3.0 to 5.5V to the VCC1 and VCC2 pins and 0V to the

VSS pin. The VCC apply condition is that VCC2 = VCC1 (1).

Applies the power supply for the A/D converter. Connect the

AVCC pin to VCC1. Connect the AVSS pin to VSS.

The microcomputer is in a reset state when applying “L” to the

this pin.

Connect this pin to VSS.

I/O pins for the main clock oscillation circuit. Connect a ceramic

resonator or crystal oscillator between XIN and XOUT (2).

To use the external clock, input the clock from XIN and leave

XOUT open.

I/O pins for a sub clock oscillation circuit. Connect a crystal

oscillator between XCIN and XCOUT (2).

To use the external clock, input the clock from XCIN and leave

XCOUT open.

The clock of the same cycle as fC, f8, or f32 is output.

______

Input pins for the INT interrupt.

_______

Input pin for the NMI interrupt.

Input pins for the key input interrupt.

These are timer A0 to timer A4 I/O pins.

These are timer A0 to timer A4 input pins.

Input pin for the Z-phase.

These are timer B0 to timer B5 input pins.

These are Three-phase motor control output pins.

These are send control input pins.

These are receive control output pins.

These are transfer clock I/O pins.

These are serial data input pins.

These are serial data output pins.

This is output pin for transfer clock output from multiple pins function.

These are serial data I/O pins.

These are transfer clock I/O pins. (except SCL2 for the

N-channel open drain output.)

Signal Name Pin Name I/O Type Description

I: Input O: Output I/O: Input/Output

NOTES:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2. Ask the oscillator maker the oscillation characteristic.

________ ________

3. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version.

Rev.1.10 Jul 01, 2005 page 9 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview

Under development

This document is under development and its contents are subject to change.

Table 1.5 Pin Description (100-pin and 128-pin Versions) (2)

Applies the reference voltage for the A/D converter and D/A

converter.

Analog input pins for the A/D converter.

This is an A/D trigger input pin.

This is the extended analog input pin for the A/D converter,

and is the output in external op-amp connection mode.

This is the extended analog input pin for the A/D converter.

These are the output pins for the D/A converter.

These are the input pins for the CAN module.

These are the output pins for the CAN module.

8-bit I/O ports in CMOS, having a direction register to select

an input or output.

Each pin is set as an input port or output port. An input port

can be set for a pull-up or for no pull-up in 4-bit unit by

program.

(except P7_1 and P9_1 for the N-channel open drain output.)

_______

Input pin for the NMI interrupt.

Pin states can be read by the P8_5 bit in the P8 register.

Reference

voltage input

A/D converter

D/A converter

CAN module

I/O port

Input port

VREF

AN0 to AN7

AN0_0 to AN0_7

AN2_0 to AN2_7

_____________

ADTRG

ANEX0

ANEX1

DA0, DA1

CRX0, CRX1

CTX0, CTX1

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_7

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_4

P8_6, P8_7

P9_0 to P9_7

P10_0 to P10_7

P11_0 to P11_7 (1)

P12_0 to P12_7 (1)

P13_0 to P13_7 (1)

P14_0, P14_1 (1)

P8_5

I/O

Signal Name Pin Name I/O Type Description

I: Input O: Output I/O: Input/Output

NOTE:

1. Ports P11 to P14 are only in the 128-pin version.

Rev.1.10 Jul 01, 2005 page 10 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU)

Under development

This document is under development and its contents are subject to change.

Figure 2.1 CPU Registers

2.1 Data Registers (R0, R1, R2, and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit

data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The A0 register consists of 16 bits, and is used for address register indirect addressing and address

same as A0.

In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

USP

ISP

b15 b0

Static Base Register

User Stack Pointer

Interrupt Stack Pointer

b19 b15

INTBLINTBH

The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.

Interrupt Table Register

b19

Program Counter

R0H (R0's high bits) R0L (R0's low bits)

R1H (R1's high bits) R1L (R1's low bits)

b31 b15 b8 b7 b0

Data Registers

(1)

Address Registers

(1)

Frame Base Registers

(1)

NOTE:

1. These registers comprise a register bank. There are two register banks.

b15 b0

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Area

Processor Interrupt Priority Level

Reserved Area

b15 b0

FLG Flag Register

IPL U I O B S Z D C

b7b8

Rev.1.10 Jul 01, 2005 page 11 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU)

Under development

This document is under development and its contents are subject to change.

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Select Flag (B Flag)

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is

set to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0” ; USP is selected when the U flag is “1”.

The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software

interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level

0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt request is enabled.

2.8.10 Reserved Area

When white to this bit, write “0”. When read, its content is indeterminate.

Rev.1.10 Jul 01, 2005 page 12 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 3. Memory

Under development

This document is under development and its contents are subject to change.

3. Memory

Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NK, M16C/6NM). The address space

extends the 1 Mbyte from address 00000h to FFFFFh.

The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a

512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.

As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is

mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.

The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the

start address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a

31-Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh. In addition to storing data, the

internal RAM also stores the stack used when calling subroutines and when interrupts are generated.

The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are

located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be

used by users.

The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by

the JMPS or JSRS instruction. For details, refer to M16C/60 and M16C/20 Series Software Manual.

Figure 3.1 Memory Map

00000h

YYYYY

FFFFFh

00400h

0FFFFh

10000h

0F000h

XXXXX

Internal ROM

(data area)

(1)

Internal ROM

(program area)

(3)

SFR

Internal RAM

Reserved area

FFE00h

FFFDCh

FFFFFh

NOTES:

1. As for the flash memory version, 4-Kbyte space (block A) exists.

2. Shown here is a memory map for the case where the PM13 bit in the PM1 register is "1".

If the PM13 bit is set to "0", 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.

3. When using the masked ROM version, write nothing to internal ROM area.

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Oscillation stop and re-oscillation

detection / watchdog timer

Reset

Special page

vector table

DBC

NMI

Address XXXXX

Capacity

Internal RAM

20 Kbytes

31 Kbytes

053FF

16 Kbytes 043FF

07FFF

Address YYYYY

Capacity

Internal ROM

(1)

384 Kbytes A0000

256 Kbytes C0000

192 Kbytes D0000

512 Kbytes 80000

Reserved area

Rev.1.10 Jul 01, 2005 page 13 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

4. Special Function Register (SFR)

SFR (Special Function Register) is the control register of peripheral functions.

Tables 4.1 to 4.16 list the SFR information.

Table 4.1 SFR Information (1)

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

Processor Mode Register 0

Processor Mode Register 1

System Clock Control Register 0

System Clock Control Register 1

Address Match Interrupt Enable Register

Protect Register

Oscillation Stop Detection Register (1)

Watchdog Timer Start Register

Watchdog Timer Control Register

Address Match Interrupt Register 0

Address Match Interrupt Register 1

PLL Control Register 0

Processor Mode Register 2

DMA0 Source Pointer

DMA0 Destination Pointer

DMA0 Transfer Counter

DMA0 Control Register

DMA1 Source Pointer

DMA1 Destination Pointer

DMA1 Transfer Counter

DMA1 Control Register

PM0

PM1

CM0

CM1

AIER

PRCR

CM2

WDTS

WDC

RMAD0

RMAD1

PLC0

PM2

SAR0

DAR0

TCR0

DM0CON

SAR1

DAR1

TCR1

DM1CON

X: Undefined

NOTES:

1. The CM20, CM21, and CM27 bits in the CM2 register do not change at oscillation stop detection reset.

2. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

00h

00001000b

01001000b

00100000b

XXXXXX00b

XX000000b

0X000000b

XXh

00XXXXXXb

00h

X0h

00h

X0h

0001X010b

XXX00000b

XXh

00000X00b

XXh

00000X00b

Rev.1.10 Jul 01, 2005 page 14 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.2 SFR Information (2)

XXXXX000b

XX00X000b

XXXXX000b

XX00X000b

XXXXX000b

XX00X000b

XXXXX000b

XX00X000b

XXXXX000b

XX00X000b

XXh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

C01WKIC

C0RECIC

C0TRMIC

INT3IC

TB5IC

S5IC

TB4IC

U1BCNIC

TB3IC

U0BCNIC

C1RECIC

S4IC

INT5IC

C1TRMIC

S3IC

INT4IC

U2BCNIC

DM0IC

DM1IC

C01ERRIC

ADIC

KUPIC

S2TIC

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

INT7IC

TA3IC

INT6IC

TA4IC

TB0IC

S6IC

TB1IC

INT8IC

TB2IC

INT0IC

INT1IC

INT2IC

Address Register Symbol After Reset

CAN0/1 Wake-up Interrupt Control Register

CAN0 Successful Reception Interrupt Control Register

CAN0 Successful Transmission Interrupt Control Register

INT3 Interrupt Control Register

Timer B5 Interrupt Control Register

SI/O5 Interrupt Control Register (1)

Timer B4 Interrupt Control Register

UART1 Bus Collision Detection Interrupt Control Register

Timer B3 Interrupt Control Register

UART0 Bus Collision Detection Interrupt Control Register

CAN1 Successful Reception Interrupt Control Register

SI/O4 Interrupt Control Register

INT5 Interrupt Control Register

CAN1 Successful Transmission Interrupt Control Register

SI/O3 Interrupt Control Register

INT4 Interrupt Control Register

UART2 Bus Collision Detection Interrupt Control Register

DMA0 Interrupt Control Register

DMA1 Interrupt Control Register

CAN0/1 Error Interrupt Control Register

A/D Conversion Interrupt Control Register

Key Input Interrupt Control Register

UART2 Transmit Interrupt Control Register

UART2 Receive Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer A0 Interrupt Control Register

Timer A1 Interrupt Control Register

Timer A2 Interrupt Control Register

INT7 Interrupt Control Register (1)

Timer A3 Interrupt Control Register

INT6 Interrupt Control Register (1)

Timer A4 Interrupt Control Register

Timer B0 Interrupt Control Register

SI/O6 Interrupt Control Register (1)

Timer B1 Interrupt Control Register

INT8 Interrupt Control Register (1)

Timer B2 Interrupt Control Register

INT0 Interrupt Control Register

INT1 Interrupt Control Register

INT2 Interrupt Control Register

CAN0 Message Box 0: Identifier / DLC

CAN0 Message Box 0: Data Field

CAN0 Message Box 0: Time Stamp

CAN0 Message Box 1: Identifier / DLC

CAN0 Message Box 1: Data Field

CAN0 Message Box 1: Time Stamp

X: Undefined

NOTES:

1. These registers exist only in the 128-pin version.

2. The blank area is reserved and cannot be accessed by users.

Rev.1.10 Jul 01, 2005 page 15 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.3 SFR Information (3)

X: Undefined

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h

00A1h

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

CAN0 Message Box 2: Identifier / DLC

CAN0 Message Box 2: Data Field

CAN0 Message Box 2: Time Stamp

CAN0 Message Box 3: Identifier / DLC

CAN0 Message Box 3: Data Field

CAN0 Message Box 3: Time Stamp

CAN0 Message Box 4: Identifier / DLC

CAN0 Message Box 4: Data Field

CAN0 Message Box 4: Time Stamp

CAN0 Message Box 5: Identifier / DLC

CAN0 Message Box 5: Data Field

CAN0 Message Box 5: Time Stamp

Address Register Symbol After Reset

XXh

Rev.1.10 Jul 01, 2005 page 16 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.4 SFR Information (4)

X: Undefined

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

CAN0 Message Box 6: Identifier / DLC

CAN0 Message Box 6: Data Field

CAN0 Message Box 6: Time Stamp

CAN0 Message Box 7: Identifier / DLC

CAN0 Message Box 7: Data Field

CAN0 Message Box 7: Time Stamp

CAN0 Message Box 8: Identifier / DLC

CAN0 Message Box 8: Data Field

CAN0 Message Box 8: Time Stamp

CAN0 Message Box 9: Identifier / DLC

CAN0 Message Box 9: Data Field

CAN0 Message Box 9: Time Stamp

Address Register Symbol After Reset

XXh

Rev.1.10 Jul 01, 2005 page 17 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.5 SFR Information (5)

X: Undefined

0100h

0101h

0102h

0103h

0104h

0105h

0106h

0107h

0108h

0109h

010Ah

010Bh

010Ch

010Dh

010Eh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h

0119h

011Ah

011Bh

011Ch

011Dh

011Eh

011Fh

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

CAN0 Message Box 10: Identifier / DLC

CAN0 Message Box 10: Data Field

CAN0 Message Box 10: Time Stamp

CAN0 Message Box 11: Identifier / DLC

CAN0 Message Box 11: Data Field

CAN0 Message Box 11: Time Stamp

CAN0 Message Box 12: Identifier / DLC

CAN0 Message Box 12: Data Field

CAN0 Message Box 12: Time Stamp

CAN0 Message Box 13: Identifier / DLC

CAN0 Message Box 13: Data Field

CAN0 Message Box 13: Time Stamp

Address Register Symbol After Reset

XXh

Rev.1.10 Jul 01, 2005 page 18 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.6 SFR Information (6)

X: Undefined

NOTE:

1. The blank areas are reserved and cannot be accessed by users.

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

CAN0 Message Box 14: Identifier /DLC

CAN0 Message Box 14: Data Field

CAN0 Message Box 14: Time Stamp

CAN0 Message Box 15: Identifier /DLC

CAN0 Message Box 15: Data Field

CAN0 Message Box 15: Time Stamp

CAN0 Global Mask Register

CAN0 Local Mask A Register

CAN0 Local Mask B Register

Address Register Symbol After Reset

XXh

C0GMR

C0LMAR

C0LMBR

Rev.1.10 Jul 01, 2005 page 19 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.7 SFR Information (7)

X: Undefined

NOTES:

1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version.

2. The blank areas are reserved and cannot be accessed by users.

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

Flash Memory Control Register 1 (1)

Flash Memory Control Register 0 (1)

Address Match Interrupt Register 2

Address Match Interrupt Enable Register 2

Address Match Interrupt Register 3

FMR1

FMR0

RMAD2

AIER2

RMAD3

Address Register Symbol After Reset

0X00XX0Xb

00000001b

00h

X0h

XXXXXX00b

00h

X0h

Rev.1.10 Jul 01, 2005 page 20 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.8 SFR Information (8)

Timer B3, B4, B5 Count Start Flag

Timer A1-1 Register

Timer A2-1 Register

Timer A4-1 Register

Three-Phase PWM Control Register 0

Three-Phase PWM Control Register 1

Three-Phase Output Buffer Register 0

Three-Phase Output Buffer Register 1

Dead Time Timer

Timer B2 Interrupt Occurrence Frequency Set Counter

Interrupt Cause Select Register 2

Timer B3 Register

Timer B4 Register

Timer B5 Register

SI/O6 Transmit/Receive Register (1)

SI/O6 Control Register (1)

SI/O6 Bit Rate Generator (1)

SI/O3, 4, 5, 6 Transmit/Receive Register (2)

Timer B3 Mode Register

Timer B4 Mode Register

Timer B5 Mode Register

Interrupt Cause Select Register 0

Interrupt Cause Select Register 1

SI/O3 Transmit/Receive Register

SI/O3 Control Register

SI/O3 Bit Rate Generator

SI/O4 Transmit/Receive Register

SI/O4 Control Register

SI/O4 Bit Rate Generator

SI/O5 Transmit/Receive Register (1)

SI/O5 Control Register (1)

SI/O5 Bit Rate Generator (1)

UART0 Special Mode Register 4

UART0 Special Mode Register 3

UART0 Special Mode Register 2

UART0 Special Mode Register

UART1 Special Mode Register 4

UART1 Special Mode Register 3

UART1 Special Mode Register 2

UART1 Special Mode Register

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Generator

UART2 Transmit Buffer Register

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

Address Register Symbol After Reset

TBSR

TA11

TA21

TA41

INVC0

INVC1

IDB0

IDB1

DTT

ICTB2

IFSR2

TB3

TB4

TB5

S6TRR

S6C

S6BRG

S3456TRR

TB3MR

TB4MR

TB5MR

IFSR0

IFSR1

S3TRR

S3C

S3BRG

S4TRR

S4C

S4BRG

S5TRR

S5C

S5BRG

U0SMR4

U0SMR3

U0SMR2

U0SMR

U1SMR4

U1SMR3

U1SMR2

U1SMR

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

U2BRG

U2TB

U2C0

U2C1

U2RB

000XXXXXb

XXh

00h

XXh

X0000000b

XXh

01000000b

XXh

XXXX0000b

00XX0000b

00h

XXh

01000000b

XXh

01000000b

XXh

01000000b

XXh

00h

000X0X0Xb

X0000000b

00h

000X0X0Xb

X0000000b

00h

000X0X0Xb

X0000000b

00h

XXh

00001000b

00000010b

XXh

X: Undefined

NOTES:

1. These registers exist only in the 128-pin version.

2. The S5TRF and S6TRF bits in the S3456TRR register are used in the 128-pin version.

3. The blank areas are reserved and cannot be accessed by users.

Rev.1.10 Jul 01, 2005 page 21 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

X: Undefined

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

0208h

0209h

020Ah

020Bh

020Ch

020Dh

020Eh

020Fh

0210h

0211h

0212h

0213h

0214h

0215h

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

021Dh

021Eh

021Fh

0220h

0221h

0222h

0223h

0224h

0225h

0226h

0227h

0228h

0229h

022Ah

022Bh

022Ch

022Dh

022Eh

022Fh

0230h

0231h

0232h

0233h

0234h

0235h

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

023Fh

CAN0 Message Control Register 0

CAN0 Message Control Register 1

CAN0 Message Control Register 2

CAN0 Message Control Register 3

CAN0 Message Control Register 4

CAN0 Message Control Register 5

CAN0 Message Control Register 6

CAN0 Message Control Register 7

CAN0 Message Control Register 8

CAN0 Message Control Register 9

CAN0 Message Control Register 10

CAN0 Message Control Register 11

CAN0 Message Control Register 12

CAN0 Message Control Register 13

CAN0 Message Control Register 14

CAN0 Message Control Register 15

CAN0 Control Register

CAN0 Status Register

CAN0 Slot Status Register

CAN0 Interrupt Control Register

CAN0 Extended ID Register

CAN0 Configuration Register

CAN0 Receive Error Count Register

CAN0 Transmit Error Count Register

CAN0 Time Stamp Register

CAN1 Message Control Register 0

CAN1 Message Control Register 1

CAN1 Message Control Register 2

CAN1 Message Control Register 3

CAN1 Message Control Register 4

CAN1 Message Control Register 5

CAN1 Message Control Register 6

CAN1 Message Control Register 7

CAN1 Message Control Register 8

CAN1 Message Control Register 9

CAN1 Message Control Register 10

CAN1 Message Control Register 11

CAN1 Message Control Register 12

CAN1 Message Control Register 13

CAN1 Message Control Register 14

CAN1 Message Control Register 15

CAN1 Control Register

CAN1 Status Register

CAN1 Slot Status Register

CAN1 Interrupt Control Register

CAN1 Extended ID Register

CAN1 Configuration Register

CAN1 Receive Error Count Register

CAN1 Transmit Error Count Register

CAN1 Time Stamp Register

C0MCTL0

C0MCTL1

C0MCTL2

C0MCTL3

C0MCTL4

C0MCTL5

C0MCTL6

C0MCTL7

C0MCTL8

C0MCTL9

C0MCTL10

C0MCTL11

C0MCTL12

C0MCTL13

C0MCTL14

C0MCTL15

C0CTLR

C0STR

C0SSTR

C0ICR

C0IDR

C0CONR

C0RECR

C0TECR

C0TSR

C1MCTL0

C1MCTL1

C1MCTL2

C1MCTL3

C1MCTL4

C1MCTL5

C1MCTL6

C1MCTL7

C1MCTL8

C1MCTL9

C1MCTL10

C1MCTL11

C1MCTL12

C1MCTL13

C1MCTL14

C1MCTL15

C1CTLR

C1STR

C1SSTR

C1ICR

C1IDR

C1CONR

C1RECR

C1TECR

C1TSR

Address Register Symbol After Reset

00h

X0000001b

XX0X0000b

00h

X0000001b

00h

XXh

00h

X0000001b

XX0X0000b

00h

X0000001b

00h

XXh

00h

Table 4.9 SFR Information (9)

Rev.1.10 Jul 01, 2005 page 22 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

X: Undefined

NOTE:

1. The blank areas are reserved and cannot be accessed by users.

XXh

00h

XXh

CAN0 Acceptance Filter Support Register

CAN1 Acceptance Filter Support Register

Peripheral Clock Select Register

CAN0/1 Clock Select Register

CAN1 Message Box 0: Identifier / DLC

CAN1 Message Box 0: Data Field

CAN1 Message Box 0:Time Stamp

CAN1 Message Box 1: Identifier / DLC

CAN1 Message Box 1: Data Field

CAN1 Message Box 1:Time Stamp

0240h

0241h

0242h

0243h

0244h

0245h

0246h

0247h

0248h

0249h

024Ah

024Bh

024Ch

024Dh

024Eh

024Fh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

025Fh

0260h

0261h

0262h

0263h

0264h

0265h

0266h

0267h

0268h

0269h

026Ah

026Bh

026Ch

026Dh

026Eh

026Fh

0270h

0271h

0272h

0273h

0274h

0275h

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

027Dh

027Eh

027Fh

C0AFS

C1AFS

PCLKR

CCLKR

Address Register Symbol After Reset

Table 4.10 SFR Information (10)

Rev.1.10 Jul 01, 2005 page 23 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.11 SFR Information (11)

X: Undefined

0280h

0281h

0282h

0283h

0284h

0285h

0286h

0287h

0288h

0289h

028Ah

028Bh

028Ch

028Dh

028Eh

028Fh

0290h

0291h

0292h

0293h

0294h

0295h

0296h

0297h

0298h

0299h

029Ah

029Bh

029Ch

029Dh

029Eh

029Fh

02A0h

02A1h

02A2h

02A3h

02A4h

02A5h

02A6h

02A7h

02A8h

02A9h

02AAh

02ABh

02ACh

02ADh

02AEh

02AFh

02B0h

02B1h

02B2h

02B3h

02B4h

02B5h

02B6h

02B7h

02B8h

02B9h

02BAh

02BBh

02BCh

02BDh

02BEh

02BFh

CAN1 Message Box 2: Identifier / DLC

CAN1 Message Box 2: Data Field

CAN1 Message Box 2: Time Stamp

CAN1 Message Box 3: Identifier / DLC

CAN1 Message Box 3: Data Field

CAN1 Message Box 3: Time Stamp

CAN1 Message Box 4: Identifier / DLC

CAN1 Message Box 4: Data Field

CAN1 Message Box 4: Time Stamp

CAN1 Message Box 5: Identifier / DLC

CAN1 Message Box 5: Data Field

CAN1 Message Box 5: Time Stamp

Address Register Symbol After Reset

XXh

Rev.1.10 Jul 01, 2005 page 24 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.12 SFR Information (12)

X: Undefined

02C0h

02C1h

02C2h

02C3h

02C4h

02C5h

02C6h

02C7h

02C8h

02C9h

02CAh

02CBh

02CCh

02CDh

02CEh

02CFh

02D0h

02D1h

02D2h

02D3h

02D4h

02D5h

02D6h

02D7h

02D8h

02D9h

02DAh

02DBh

02DCh

02DDh

02DEh

02DFh

02E0h

02E1h

02E2h

02E3h

02E4h

02E5h

02E6h

02E7h

02E8h

02E9h

02EAh

02EBh

02ECh

02EDh

02EEh

02EFh

02F0h

02F1h

02F2h

02F3h

02F4h

02F5h

02F6h

02F7h

02F8h

02F9h

02FAh

02FBh

02FCh

02FDh

02FEh

02FFh

CAN1 Message Box 6: Identifier / DLC

CAN1 Message Box 6: Data Field

CAN1 Message Box 6: Time Stamp

CAN1 Message Box 7: Identifier / DLC

CAN1 Message Box 7: Data Field

CAN1 Message Box 7: Time Stamp

CAN1 Message Box 8: Identifier / DLC

CAN1 Message Box 8: Data Field

CAN1 Message Box 8: Time Stamp

CAN1 Message Box 9: Identifier / DLC

CAN1 Message Box 9: Data Field

CAN1 Message Box 9: Time Stamp

Address Register Symbol After Reset

XXh

Rev.1.10 Jul 01, 2005 page 25 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.13 SFR Information (13)

X: Undefined

0300h

0301h

0302h

0303h

0304h

0305h

0306h

0307h

0308h

0309h

030Ah

030Bh

030Ch

030Dh

030Eh

030Fh

0310h

0311h

0312h

0313h

0314h

0315h

0316h

0317h

0318h

0319h

031Ah

031Bh

031Ch

031Dh

031Eh

031Fh

0320h

0321h

0322h

0323h

0324h

0325h

0326h

0327h

0328h

0329h

032Ah

032Bh

032Ch

032Dh

032Eh

032Fh

0330h

0331h

0332h

0333h

0334h

0335h

0336h

0337h

0338h

0339h

033Ah

033Bh

033Ch

033Dh

033Eh

033Fh

CAN1 Message Box 10: Identifier / DLC

CAN1 Message Box 10: Data Field

CAN1 Message Box 10: Time Stamp

CAN1 Message Box 11: Identifier / DLC

CAN1 Message Box 11: Data Field

CAN1 Message Box 11: Time Stamp

CAN1 Message Box 12: Identifier / DLC

CAN1 Message Box 12: Data Field

CAN1 Message Box 12: Time Stamp

CAN1 Message Box 13: Identifier / DLC

CAN1 Message Box 13: Data Field

CAN1 Message Box 13: Time Stamp

Address Register Symbol After Reset

XXh

Rev.1.10 Jul 01, 2005 page 26 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

Table 4.14 SFR Information (14)

X: Undefined

NOTE:

1. The blank areas are reserved and cannot be accessed by users.

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

034Ah

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

035Ch

035Dh

035Eh

035Fh

0360h

0361h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch

037Dh

037Eh

037Fh

CAN1 Message Box 14: Identifier / DLC

CAN1 Message Box 14: Data Field

CAN1 Message Box 14: Time Stamp

CAN1 Message Box 15: Identifier / DLC

CAN1 Message Box 15: Data Field

CAN1 Message Box 15: Time Stamp

CAN1 Global Mask Register

CAN1 Local Mask A Register

CAN1 Local Mask B Register

Address Register Symbol After Reset

XXh

C1GMR

C1LMAR

C1LMBR

Rev.1.10 Jul 01, 2005 page 27 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

X: Undefined

NOTES:

1. The TA2P to TA4P bits in the UDF register are set to "0" after reset. However, the contents in these bits are indeterminate when read.

2. The blank areas are reserved and cannot be accessed by users.

0380h

0381h

0382h

0383h

0384h

0385h

0386h

0387h

0388h

0389h

038Ah

038Bh

038Ch

038Dh

038Eh

038Fh

0390h

0391h

0392h

0393h

0394h

0395h

0396h

0397h

0398h

0399h

039Ah

039Bh

039Ch

039Dh

039Eh

039Fh

03A0h

03A1h

03A2h

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh

03BDh

03BEh

03BFh

Count Start Flag

Clock Prescaler Reset Flag

One-Shot Start Flag

Trigger Select Register

Up/Down Flag

Timer A0 Register

Timer A1 Register

Timer A2 Register

Timer A3 Register

Timer A4 Register

Timer B0 Register

Timer B1 Register

Timer B2 Register

Timer A0 Mode Register

Timer A1 Mode Register

Timer A2 Mode Register

Timer A3 Mode Register

Timer A4 Mode Register

Timer B0 Mode Register

Timer B1 Mode Register

Timer B2 Mode Register

Timer B2 Special Mode Register

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Generator

UART0 Transmit Buffer Register

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Generator

UART1 Transmit Buffer Register

UART1 Transmit/Receive Control Register 0

UART1 Transmit/Receive Control Register 1

UART1 Receive Buffer Register

UART Transmit/Receive Control Register 2

DMA0 Request Cause Select Register

DMA1 Request Cause Select Register

CRC Data Register

CRC Input Register

TABSR

CPSRF

ONSF

TRGSR

UDF

TA0

TA1

TA2

TA3

TA4

TB0

TB1

TB2

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

U0MR

U0BRG

U0TB

U0C0

U0C1

U0RB

U1MR

U1BRG

U1TB

U1C0

U1C1

U1RB

UCON

DM0SL

DM1SL

CRCD

CRCIN

Address Register Symbol After Reset

00h

0XXXXXXXb

00h

XXh

00h

00XX0000b

XXXXXX00b

00h

XXh

00001000b

00XX0010b

XXh

00h

XXh

00001000b

00XX0010b

XXh

X0000000b

00h

XXh

(1)

Table 4.15 SFR Information (15)

Rev.1.10 Jul 01, 2005 page 28 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR)

Under development

This document is under development and its contents are subject to change.

X: Undefined

NOTES:

1. These registers exist only in the128-pin version.

2. The blank areas are reserved and cannot be accessed by users.

03C0h

03C1h

03C2h

03C3h

03C4h

03C5h

03C6h

03C7h

03C8h

03C9h

03CAh

03CBh

03CCh

03CDh

03CEh

03CFh

03D0h

03D1h

03D2h

03D3h

03D4h

03D5h

03D6h

03D7h

03D8h

03D9h

03DAh

03DBh

03DCh

03DDh

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

03EAh

03EBh

03ECh

03EDh

03EEh

03EFh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

03FEh

03FFh

A/D Register 0

A/D Register 1

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

A/D Control Register 2

A/D Control Register 0

A/D Control Register 1

D/A Register 0

D/A Register 1

D/A Control Register

Port P14 Control Register

(1)

Pull-Up Control Register 3

(1)

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

Port P3 Register

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

Port P5 Register

Port P4 Direction Register

Port P5 Direction Register

Port P6 Register

Port P7 Register

Port P6 Direction Register

Port P7 Direction Register

Port P8 Register

Port P9 Register

Port P8 Direction Register

Port P9 Direction Register

Port P10 Register

Port P11 Register

(1)

Port P10 Direction Register

Port P11 Direction Register

(1)

Port P12 Register

(1)

Port P13 Register

(1)

Port P12 Direction Register

(1)

Port P13 Direction Register

(1)

Pull-up Control Register 0

Pull-up Control Register 1

Pull-up Control Register 2

Port Control Register

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ADCON2

ADCON0

ADCON1

DA0

DA1

DACON

PC14

PUR3

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

P10

P11

PD10

PD11

P12

P13

PD12

PD13

PUR0

PUR1

PUR2

PCR

Address Register Symbol After Reset

XXh

00h

00000XXXb

00h

XX00XXXXb

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00X00000b

00h

XXh

00h

XXh

00h

Table 4.16 SFR Information (16)

Rev.1.10 Jul 01, 2005 page 29 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

5. Electrical Characteristics

Table 5.1 Absolute Maximum Ratings

NOTE:

1. Ports P11 to P14 are only in the 128-pin version.

VCC

AVCC

Topr

Tstg

°C

Unit

Supply Voltage (VCC1 = VCC2)

Analog Supply Voltage

Input

Voltage

Output

Voltage

Power Dissipation

Operating Ambient When the Microcomputer is Operating

Temperature Flash Program Erase

Storage Temperature

Symbol Parameter

_____________

RESET, CNVSS, BYTE,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,

P9_0, P9_2 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1, VREF, XIN

P7_1, P9_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_0, P14_1, XOUT

P7_1, P9_1

Rated Value

–0.3 to 6.5

–0.3 to VCC+0.3

–0.3 to 6.5

–0.3 to VCC+0.3

–0.3 to 6.5

700

–40 to 85

0 to 60

–65 to 150

Condition

VCC = AVCC

Topr = 25°C

Rev.1.10 Jul 01, 2005 page 30 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

Table 5.2 Recommended Operating Conditions (1) (1)

Supply Voltage (VCC1 = VCC2)

Analog Supply Voltage

Supply Voltage

Analog Supply Voltage

HIGH Input

Voltage

LOW Input

Voltage

HIGH Peak

Output Current

HIGH Average

Output Current

LOW Peak

Output Current

LOW Average

Output Current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

_____________

P14_0, P14_1, XIN, RESET, CNVSS, BYTE

P7_1, P9_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

_____________

P14_0, P14_1, XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to

P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0

to P13_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to

P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0

to P13_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

5.0

VCC

3.0

0.8VCC

5.5

VCC

6.5

0.2VCC

–10.0

–5.0

10.0

5.0

VCC

AVCC

VSS

AVSS

VIH

VIL

IOH(peak)

IOH(avg)

IOL(peak)

IOL(avg)

ParameterSymbol Typ.Min.

Standard Unit

Max.

NOTES:

1. Referenced to VCC = 3.0 to 5.5V at Topr = –40 to 85°C unless otherwise specified.

2. The mean output current is the mean value within 100 ms.

3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max.

The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12 and P13 must be 80mA max.

The total IOH(peak) for ports P0, P1, and P2 must be –40mA max.

The total IOH(peak) for ports P3, P4, P5, P12 and P13 must be –40mA max.

The total IOH(peak) for ports P6, P7 and P8_0 to P8_4 must be –40mA max.

The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be –40mA max.

4. P11 to P14 are only in the 128-pin version.

Rev.1.10 Jul 01, 2005 page 31 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

Table 5.3 Recommended Operating Conditions (2) (1)

Main Clock Input Oscillation No Wait Mask ROM Version VCC = 3.0 to 5.5V

Frequency (2) (3) (4)

Flash Memory Version

Sub Clock Oscillation Frequency

On-chip Oscillation Frequency

PLL Clock Oscillation Frequency

CPU Operation Clock

VCC = 3.0 to 5.5V

PLL Frequency Synthesizer Stabilization Wait Time

Power Supply Ripple Allowable Frequency (VCC)

Power Supply Ripple Allowable Amplitude Voltage VCC = 5V

VCC = 3V

Power Supply Ripple Rising/Falling Gradient VCC = 5V

VCC = 3V

32.768

MHz

kHz

MHz

kHz

V/ms

0.5

0.3

f(XIN)

f(XCIN)

f(Ring)

f(PLL)

f(BCLK)

tsu(PLL)

f(ripple)

VP-P(ripple)

VCC(|∆V/∆T|)

ParameterSymbol Typ.Min.

Standard Unit

Max.

NOTES:

1. Referenced to VCC = 3.0 to 5.5V at Topr = –40 to 85°C unless

otherwise specified.

2. Relationship between main clock oscillation frequency and supply

voltage is shown right.

3. Execute program/erase of flash memory by VCC = 3.3 ± 0.3 V or

VCC = 5.0 ± 0.5 V.

4. When using 16MHz and over, use PLL clock. PLL clock oscillation

frequency which can be used is 16MHz, 20MHz or 24MHz.

0.0

16.0

5.53.0

VCC [V] (main clock: no division)

Main clock input oscillation frequency

f(XIN) operating maximum frequency [MHz]

f(ripple)

Power Supply Ripple Allowable

Frequency (VCC)

VP-P(ripple)

Power Supply Ripple Allowable

Amplitude Voltage

Figure 5.1 Timing of Voltage Fluctuation

(ripple)

P-P(ripple)

VCC

Rev.1.10 Jul 01, 2005 page 32 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

Table 5.4 Electrical Characteristics (1) (1)

-2.0

-0.3

3.0

0.2

2.0

2.5

1.6

1.5

HIGH Output

Voltage

HIGH Output

Voltage

HIGH Output

Voltage

HIGH Output

Voltage

LOW Output

Voltage

LOW Output

Voltage

LOW Output

Voltage

LOW Output

Voltage

Hysteresis

HIGH Input

Current

LOW Input

Current

Pull-up

Resistance

Feedback Resistance

RAM Retention Voltage

VOH

VOL

VT+-VT-

IIH

IIL

RPULLUP

RfXIN

RfXCIN

VRAM

IOH = –5mA

IOH = –200µA

IOH = –1mA

IOH = –0.5mA

With no load applied

IOL = 5mA

IOL = 200µA

IOL = 1mA

IOL = 0.5mA

With no load applied

VI = 5V

VI = 0V

At stop mode

µA

kΩ

MΩ

Measuring Condition

Standard

Min. Unit

VCC

2.0

0.45

2.0

1.0

2.5

0.8

5.0

–5.0

170

Parameter

Symbol

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

_________ _________

TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT8,

________ ______________ __________ __________

NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2,

SDA0 to SDA2, CLK0 to CLK6, TA0OUT to TA4OUT,

______ ______

KI0 to KI3, RXD0 to RXD2, SIN3 to SIN6

_____________

RESET

XIN

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_0, P14_1

XIN

XCIN

Typ. Max.

NOTES:

1. Referenced to VCC = 3.0 to 5.5V, VSS = 0V at Topr = –40 to 85°C, f(BCLK) = 24MHz unless otherwise specified.

________ ________

2. P11 to P14, INT6 to INT8, CLK5, CLK6, SIN5 and SIN6 are only in the 128-pin version.

Rev.1.10 Jul 01, 2005 page 33 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

Table 5.5 Electrical Characteristics (2) (1)

Mask ROM f(BCLK) = 24MHz,

PLL operation,

No division

On-chip oscillation,

No division

Flash Memory f(BCLK) = 24MHz,

PLL operation,

No division

On-chip oscillation,

No division

Flash Memory f(BCLK) = 10MHz,

Program VCC = 5V

Flash Memory f(BCLK) = 10MHz,

Erase VCC = 5V

Mask ROM f(BCLK) = 32kHz,

Low power dissipation

mode, ROM (2)

Flash Memory f(BCLK) = 32kHz,

Low power dissipation

mode, RAM (2)

f(BCLK) = 32kHz,

Low power dissipation

mode,

Flash memory (2)

Mask ROM On-chip oscillation,

Flash Memory Wait mode

f(BCLK) = 32kHz,

Wait mode (3),

Oscillation capacity High

f(BCLK) = 32kHz,

Wait mode (3),

Oscillation capacity Low

Stop mode,

Topr = 25°C

NOTES:

1. Referenced to VCC = 3.0 to 5.5V, VSS = 0V at Topr = –40 to 85°C, f(BCLK) = 24MHz unless otherwise specified.

2. This indicates the memory in which the program to be executed exists.

3. With one timer operated using fC32.

1.8

420

8.5

3.0

0.8

Power Supply

Current

(VCC

= 3.0 to 5.5V)

ICC mA

µA

Measuring Condition Standard

Min. Unit

3.0

ParameterSymbol

Output pins are open

and other pins are VSS.

Typ. Max.

Rev.1.10 Jul 01, 2005 page 34 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

Table 5.6 A/D Conversion Characteristics (1)

±3

±7

±5

±7

±2

±3

±7

±5

±7

±2

±1

±3

VCC

VREF

Bit

LSB

kΩ

µs

3.3

2.8

0.3

2.0

VREF = VCC

VREF

= VCC

= 5V

VREF

= VCC

= 3.3V

VREF = AVCC = VCC = 3.3V

VREF

= VCC

= 5V

VREF

= VCC

= 3.3V

VREF = AVCC = VCC = 3.3V

VREF = VCC

VREF = VCC = 5V, φAD = 10MHz

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

Resolution

Integral 10 bits

Nonlinearity

Error

8 bits

Absolute 10 bits

Accuracy

8 bits

Differential Nonlinearity Error

Offset Error

Gain Error

Resistor Ladder

10-bit Conversion Time,

Sample & Hold function Available

8-bit Conversion time,

Sample & Hold function Available

Sampling Time

Reference Voltage

Analog Input Voltage

–

INL

–

DNL

–

RLADDER

tCONV

tSAMP

VREF

VIA

Symbol Parameter Min.

Standard Unit

Measuring Condition Max.

Typ.

(NOTE 2)

1.0

1.5

Bits

µs

kΩ

Resolution

Absolute Accuracy

Setup Time

Output Resistance

Reference Power Supply Input Current

–

tsu

IVREF

Symbol Parameter Min.

Standard Unit

Measuring Condition

Max.Typ.

NOTES:

1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5V, VSS = AVSS = 0V, –40 to 85°C unless otherwise specified.

2. φAD frequency must be 10MHz or less.

3. When sample & hold function is disabled, φAD frequency must be 250kHz or more in addition to a limit of NOTE 2.

When sample & hold function is enabled, φAD frequency must be 1MHz or more in addition to a limit of NOTE 2.

Table 5.7 D/A conversion Characteristics (1)

NOTES:

1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5V, VSS = AVSS = 0V, –40 to 85°C unless otherwise specified.

2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to “00h”.

The resistor ladder of the A/D converter is not included. Also, the current IVREF always flows even though VREF

may have been set to be unconnected by the ADCON1 register.

Rev.1.10 Jul 01, 2005 page 35 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

150

µs

Time for Internal Power Supply Stabilization During Powering-On

STOP Release Time

Low Power Dissipation Mode Wait Mode Release Time

td(P-R)

td(R-S)

td(W-S)

Symbol Parameter Min.

Standard Unit

Measuring

Condition Max.

Typ.

VCC = 3.0 to 5.5V

Table 5.10 Power Supply Circuit Timing Characteristics

CPU clock

VCC

td(P-R)

Time for Internal Power Supply

Stabilization During Powering-On

td(R-S)

STOP Release Time

td(W-S)

Low Power Dissipation Mode

Wait Mode Release Time

CPU clock

td(W-S)

td(R-S)

(b)

(a)

Interrupt for

(a) Stop mode release

(b) Wait mode release

Figure 5.2 Power Supply Circuit Timing Diagram

NOTES:

1. Referenced to VCC = 4.5 to 5.5V, 3.0 to 3.6V, Topr = 0 to 60°C unless otherwise specified.

2. n denotes the number of blocks to erase.

Table 5.9 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics

(at Topr = 0 to 60°C)

200

4 ✕ n (2)

200

µs

Word Program Time

Block Erase Time

Erase All Unlocked Blocks Time

Lock Bit Program Time

Flash Memory Circuit Stabilization Wait Time

Parameter Min.

Standard Unit

Max.Typ.

1 ✕ n (2)

Symbol

tps

VCC = 3.3 ± 0.3V or 5.0 ± 0.5V

Flash Read Operation VoltageFlash Program, Erase Voltage

VCC = 3.0 to 5.5V

Table 5.8 Flash Memory Version Electrical Characteristics (1)

Rev.1.10 Jul 01, 2005 page 36 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

External Clock Input Cycle Time

External Clock Input HIGH Pulse Width

External Clock Input LOW Pulse Width

External Clock Rise Time

External Clock Fall Time

Symbol Parameter Min.

Standard Unit

Max.

62.5

tw(H)

tw(L)

Timing Requirements

(Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified)

Table 5.11 External Clock Input (XIN Input)

TAiIN Input Cycle Time

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

100

Table 5.13 Timer A Input (Gating Input in Timer Mode)

tc(TA)

tw(TAH)

tw(TAL)

Table 5.14 Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 5.15 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 5.16 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

TAiIN Input Cycle Time

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TA)

tw(TAH)

tw(TAL)

TAiIN Input Cycle Time

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

200

100

tc(TA)

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

100

tw(TAH)

tw(TAL)

TAiOUT Input Cycle Time

TAiOUT Input HIGH Pulse Width

TAiOUT Input LOW Pulse Width

TAiOUT Input Setup Time

TAiOUT Input Hold Time

Symbol Parameter Min.

Standard Unit

Max.

2000

1000

400

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

Table 5.17 Timer A Input (Two-phase Pulse Input in Event Counter Mode)

TAiIN Input Cycle Time

TAiOUT Input Setup Time

TAiIN Input Setup Time

Symbol Parameter Min.

Standard Unit

Max.

800

200

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

Table 5.12 Timer A Input (Counter Input in Event Counter Mode)

Rev.1.10 Jul 01, 2005 page 37 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

TBiIN Input Cycle Time (counted on one edge)

TBiIN Input HIGH Pulse Width (counted on one edge)

TBiIN Input LOW Pulse Width (counted on one edge)

TBiIN Input Cycle Time (counted on both edges)

TBiIN Input HIGH Pulse Width (counted on both edges)

TBiIN Input LOW Pulse Width (counted on both edges)

Symbol Parameter Min.

Standard Unit

Max.

100

200

Table 5.19 Timer B Input (Pulse Period Measurement Mode)

tc(TB)

tw(TBH)

tw(TBL)

tc(TB)

tw(TBH)

tw(TBL)

Timing Requirements

(Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified)

Table 5.18 Timer B Input (Counter Input in Event Counter Mode)

Table 5.20 Timer B Input (Pulse Width Measurement Mode)

Table 5.21 A/D Trigger Input

Table 5.22 Serial I/O

TBiIN Input Cycle Time

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TB)

tw(TBH)

tw(TBL)

TBiIN Input Cycle Time

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TB)

tw(TBH)

tw(TBL)

_____________

ADTRG Input Cycle Time (trigger able minimum)

_____________

ADTRG Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

1000

125

tC(AD)

tw(ADL)

CLKi Input Cycle Time

CLKi Input HIGH Pulse Width

CLKi Input LOW Pulse Width

TXDi Output Delay Time

TXDi Hold Time

RXDi Input Setup Time

RXDi Input Hold Time

Symbol Parameter Min.

Standard Unit

Max.

200

100

tc(CK)

tw(CKH)

tw(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

_______

Table 5.23 External Interrupt INTi Input

_______

INTi Input HIGH Pulse Width

_______

INTi Input LOW Pulse Width

Symbol Parameter Min.

Standard Unit

Max.

250

tw(INH)

tw(INL)

Rev.1.10 Jul 01, 2005 page 38 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) 5. Electric Characteristics

Under development

This document is under development and its contents are subject to change.

Figure 5.3 Timing Diagram

tsu(D—C)

CLKi

TXDi

RXDi

tc(CK)

tw(CKH)

tw(CKL)

tw(INL)

tw(INH)

td(C—Q) th(C—D)

th(C—Q)

INTi input

tc(TB)

tw(TBH)

tw(TBL)

tc(AD)

tw(ADL)

ADTRG input

TBiIN input

Two-phase pulse input in event counter mode

su(TAOUT—TAIN)

su(TAIN—TAOUT)

C(TA)

su(TAIN—TAOUT)

TAiIN input

TAiOUT input

tc(TA)

tw(TAH)

tw(TAL)

tc(UP)

tw(UPH)

tw(UPL)

TAiIN input

TAiOUT input

During event counter mode

TAiIN input

(When count on falling edge

is selected)

TAiIN input

(When count on rising edge

is selected)

TAiOUT input

(Up/down input)

h(TIN—UP)

su(UP—TIN)

trtr

tw(H) tw(L)

XIN input

Rev.1.10 Jul 01, 2005 page 39 of 39

REJ03B0058-0110

M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions

Under development

This document is under development and its contents are subject to change.

Appendix 1. Package Dimensions

Terminal cross section

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Index mark

125

100

Detail F

y0.08

e0.5

L 0.35 0.5 0.65

0.05 0.1 0.15

A1.7

15.8 16.0 16.2

1.4

E 13.914.014.1

D 13.914.014.1

Reference

Symbol

Dimension in Millimeters

Min Nom Max

0.15 0.20 0.25

0.09 0.145 0.20

0.08

1.0

0.18

0.125

1.0

Previous CodeJEITA Package Code RENESAS Code

PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV

MASS[Typ.]

0.6gP-LQFP100-14x14-0.50

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

DetailF

Index mark

138

65102

103

128

y 0.10

e0.5

L 0.35 0.5 0.65

0.05 0.125 0.2

A1.7

15.8 16.0 16.2

21.8 22.0 22.2

1.4

E 13.9 14.0 14.1

D 19.9 20.0 20.1

Reference

Symbol

Dimension in Millimeters

Min Nom Max

0.17 0.22 0.27

0.09 0.145 0.20

0.10

0.75

0.20

0.125

1.0

P-LQFP128-14x20-0.50 0.9g

MASS[Typ.]

128P6Q-APLQP0128KB-A

RENESAS CodeJEITA Package Code Previous Code

Terminal cross section

REVISION HISTORY M16C/6N Group (M16C/6NK, M16C/6NM) Data Sheet

Rev. Date Description

Page Summary

A-1

1.00

Jul. 20, 2004

1.01

Nov. 01, 2004

1.10

Jul. 01, 2005

–First edition issued

–Revised edition issued

* Revised parts and revised contents are as follows (except for expressional change).

30 Table 5.2 Recommended Operating Conditions (1)

•IOH(peak): Unit is revised from “V” to “mA”.

31 Table 5.3 Recommended Operating Conditions (2)

•NOTE 3: “VCC = 3.0 ± 0.3 V” is revised to “VCC = 3.3 ± 0.3 V”.

32 Table 5.4 IIH, IIL: “P3_3” is revised to “P3_7” in Parameter.

35 Table 5.9: VCC = 3.0 ± 0.3 V” is revised to “VCC = 3.3 ± 0.3 V” in Flash Program, Erase

Voltage.

–Revised edition issued

* The contents of product are revised. (T/V-ver. is added.)

* Revised parts and revised contents are as follows (except for expressional change).

2 Table 1.1 Performance outline of M16C/6N Group (100-pin Version: M16C/6NM)

• Performance outline of T/V-ver. is added.

3 Table 1.2 Performance outline of M16C/6N Group (128-pin Version: M16C/6NN)

• Performance outline of T/V-ver. is added.

5 Table 1.3 Product List is revised. (T/V-ver. is added.)

Figure 1.2 Type No., Memory Size, and Package: “Characteristics” is added.

13 FIgure 4.1 SFR Information (1): The value of After Reset in CM2 Register is revised.

19 Figure 4.7 SFR Information (7): NOTE 1 is revised.

32 Table 21.4 Electrical Characteristics (1)

• Measuring Condition of VOL is revised from “LOL = –200µA” to “LOL = 200µA”.

33 Table 21.5 Electrical Characteristics (2): Mask ROM (5th item)

• “f(XCIN)” is changed to “(f(BCLK)).

34 Table 21.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.

Keep safety first in your circuit designs!

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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary

circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

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