HOTLink Design Considerations - Cypress Semiconductor

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Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

November 1993 - Revised May 17, 1995

HOTLink™ Design Considerations

Application Note Overview

The HOTLink™ family of da ta co mmunications products pro-

vides a simple and low-cost solution to high-speed data trans-

mission. While these products are easy to use, th e methods

used to connec t them to high-speed serial interfaces are often

not intuitive. This document provides a basic lev el of explana-

tion of the parallel and serial interface characteristics, and

provides some cook book solutions for interfacing them to dif-

ferent types of parts and media.

Primary Topics

The primary topics covered in this application note are

• HOTLink Overview

• HOTLink Serial Signal Characteristics

• Terminating HOTLink Seri al Signals

• Inter facing to HOTLink

• Serial Link Support Com ponents

HOTLink Overview

HOTLink Features

• Fibre Channel compliant

• IBM ESCON™ compliant

• ATM Compatible

• 8B/10B-coded or 10-bit unencoded

• 160- to 330-Mbps data rate

• TTL synchronous I/O

• No external PLL components

• Triple ECL 100K serial outputs

• Dual ECL 100K seri al inputs

• L ow power : 350 m W (Tx), 6 50 mW (Rx)

• Compatible with fiber-o ptic modules, coaxial cable, and

twisted- p air media

• Built-In Self-Test

• Single +5V supply

• 28-pin SOIC/PLCC/LCC

• 0.8µ BiCMOS

Functional Description

The CY7B923 HOTLink Transmitter and CY7B933 HOTLink

Receiver are point-to-point communications building blocks

that transfer data over high-speed serial links (fiber-optic,

coax, and twist ed/ parallel- p air) at 160- to 3 30-Mbit s/second.

Figure 1

illustrates typical connections to host systems or

controllers.

Eight bits of user data or protocol information are loaded into

the HOTLink T ransmitter and are encoded. Serial data is shift-

ed out of the three differential positive ECL (PECL) serial

ports at the bit-rate (which is ten times the byte-rate).

The HOTLink Rece iver ac cepts the serial bit stream at its dif-

ferential line receiver inputs, and using a completely integrat-

ed phase-locked-loop (PLL) clock synchronizer recovers the

timing infor mati on ne cessary for data reconstruction. The bit

stream is deserialized, decoded, and checked for transmis-

sion errors. The recovered byte is presented in parallel to the

re ceiving host along with the synchronized byte-rate clock.

The 8B/10B encoder/decoder (Reference 1, 2) can be dis-

abled in systems that already encode or scramble the tran s-

mitted data. Signals are available to create a seamless inter-

face with both asynchronous FIFOs (i.e., Cypress’s

CY7C42X) and clocked FIFOs (i.e. , Cypr ess’s CY7C44X). A

built-in self-test pattern g enerator and checker allow s testing

of the tr ansmitter, receiver, and the co nnecting link as a part

of a system diagnostic check.

HOTLink devices are ideal for a v ariety of applications where

a parallel interface can be replaced with a high-speed

point-to-point serial link. Applications include interconnecting

workstations, servers, mass storage, and video transmission

equipment.

Figure 1. HOTLink System Connections

Host

Host Se ria l Link

HOTLink Design Considerations

CY7B923 HOT Link Tran smitter Description

The function of the HOTLink Transmitter is to convert

byte-rate parallel data into a high speed serial data stream. A

logic block diagram of the tr ansmit ter is shown in

Figure 2

Input Register

The Input register holds the data to be processed by the HOT-

Link Transmitter and allows the input timing to be ma de con-

sistent with standard FIFOs. The Input register is clocked by

CKW (clock write) and loaded with i nformation on the D0–7,

SC/D (special character/data select), and SVS (send violation

symbol) pins. Two enable inputs (ENA and ENN) allow the

user to choose when data is to be sent. Asserting ENA (en-

able, active LOW) c auses the inputs to be loaded on the rising

edge of CKW. If ENN (enable next, acti ve LOW) is asserted

when CKW rises, the data present on the inputs on the

rising edge of CKW will be loaded into the input register.

These two inpu ts allow proper t iming and function for compat-

ibility with either asynchronou s FIFOs or clocked FIFOs w ith-

out external logic.

In BIST mode, t h e Input register becomes the signature pat-

tern generator by logically converting the parallel input regis-

ter into a linear feedbac k shift register (LFSR). When enabled,

this LFSR generates a 511-byte sequence that includes all

Data and Special Character codes, including the explicit vio-

lation symbols. This patt ern provides a predictable but pseu-

do-random sequence that can be matched to an identical

LFSR in the HOTLink Receiver. For additional information see

the Cypress Semiconductor application note “HOTLink

Built -In Self- Test.”

Encoder

The Encoder transforms the input data held by the Input reg-

ister into a form more suitable for transmission on a serial

interface lin k. The code used is specified by AN SI X3T11 Fi-

bre Channel (Reference 3) and the IBM ESCON channel

(Reference 4) (code tables are available in the CY7B923/

CY7B933 data sheet). The eight D0–7 data inputs are convert-

ed to e ither a Data symbol or a Special Character , depen ding

upon the state of the SC/D input. I f SC/D is HIGH, the data

inputs represent a control code and are encoded using the

Special Character code tables. If SC/D is LOW, th e dat a in-

puts are converted u si ng the Data code ta ble. If a byte-time

passes with the inputs disabled, the Encoder will output a

Special Ch aracter Com ma (K28.5 or SYNC) to mai ntain lin k

synchronizatio n. The SVS input forces the transmis sion of a

specified Violation symbol to allow the user to check error

handling logic in the system controller.

The 8B/10B coding function of the Encoder can be bypassed

for systems t hat include an external coder or scrambler func-

tion as part of the controller. This bypass capability is con-

trolled by s etting the MODE select pin HIGH. When in bypass

mode, Da–j (note that bit order is specified by the Fibre Chan-

nel 8B/10B code) become the ten inputs to the Shifter, with

Da being the first bit to be shifted out.

Shifter

The Shifter acce pts p ara llel data from the Encoder once e ach

byte-time and shifts it to the serial interface output buffers

using a PLL multiplied bit-clock that runs at 10 times the

byte-clock (CKW) rate. Timing for the parallel transfer is con-

trolled by the counter included in the Cl ock Generator, and is

not affected by signal levels or timing at the input pin s.

OutA, OutB, OutC

The serial interface ECL output buffers (100K signal levels

referenced to +5V) are the drivers for the serial media. The y

are all connected to the Shifter and contain the same serial

data. Two of the output pairs (OUTA± and OUTB±) are con-

trolled b y the FOTO input and can be disabled by the sys tem

controller to force a logical zero (i.e., “light off”) at the outputs.

The third outp ut pair (OUTC±) is not affected by FOTO and

will supply a continuous data stream suitable for loop-back

testing of the subsystem.

OUTA± and OUTB± will respo nd to FOTO input changes with-

in a few bit times. However, since FOTO is not synchronized

with the transmitter data stream, the outputs will be forced of f

or turned on at arbitrary points in a transmitted byte. This

function is intended to augment an external laser safety con-

troller and as an aid for Receiver P LL testing.

In wire-based systems, control of th e outputs may not be re-

quired, and FOTO can be strapped LOW. The three output

pairs are int ended to add system and architectural flexibili ty

by offering identical s erial bit streams with separate interfaces

for redundant connections or for multiple destinations. Un-

needed outputs can be left open or wired to VCC to disable

and power down the unused output circuitr y.

Clock Generator

The clock generator is an embedded phase-locked loop (PLL)

that takes a byte-rate referenc e c lock (CKW) and multiplies it

by ten to create a bit-rate clock for driving the serial shifter.

The byte-rate refer ence com es from CKW, the rising edge of

which clocks data into the Input register. This clock must be

a crystal-referenced pulse stream that has a frequency be-

tween the minimum and m aximum specified for the HOTLink

Transmitter/Receiver pair. Signals controlled by this block

form the bit-cl ock and the t iming sig nals that control int ernal

data transfers betwe en the Input register and the Shif ter.

The read pulse (RP) is derived from the feedback counter

used in the PLL multipli er. It i s a b yte-rate p ulse stream wi th

the proper phase and pulse widths to allow transfer of data

from an asynchronous FIFO. Pulse width is independent of

CKW duty cycle, since proper phase and duty cycle is main-

tained by the PLL. The RP pulse stream will insure correct

data transfers between asynchronous FIFOs and the trans-

mitter input latch with no external logic.

Figure 2. C Y7B923 Transmitter Logic Block Diagram

D0–7

(Db–h)SC/D (Da)

SVS (Dj)

OUTA

OUTB

OUTC

FOTO

CKW

Clock

Generator

ENAENNRP

Test

Logic

MODE

BISTEN

ENAB

Input Register

Encoder

Shifter

HOTLink Design Considerations

Test Logic

Test logic includes the initialization and control for the built-in

self-test (BIST) generator, the multiplexer for Test mode clock

distrib ution, and contr ol logic t o properly select the data en-

coding. Test logic is discuss ed in more detail in the CY7B923/

CY7B933 HOTLink data sheet.

CY7B933 HOT Link Receiv er Description

The function of the HOTLink Receiver is to convert a

high-speed serial data stre am into byt e-rate parallel data. A

logic block diagram of the receiver is shown in

Figure 3.

Serial Data Inputs

The HOTLink Receiver has two differential line receivers

(INA± and INB±) that can be se lected as inputs for the serial

data stream. INA± or INB± is s elected with the A/B input. INA±

is s elected when A /B is HIGH and INB± is selec ted when A/B

is LOW. The threshold of A/B is compatible with ECL 100K

signals. TTL logic elements c an be us ed to select the INA± or

INB± inputs by a dding a resistor vo ltage divid er to a TTL driv-

er connected to A/B (s ee

Figure 35

). The differential sensitiv-

ity of INA± and INB± will accommodate wire interconnect with

filtering losses or transmission line attenuation greater than

20 dB (VDIF y 50 mV). These inputs can alternatively be di-

rectly connected to fiber-optic interface modules (any ECL

logic family, not limited to ECL 100K) with up to 1.2V of differ-

ential signal. The common-mode tolerance accommodates a

wide range of signal termination voltages. The highest HIGH

input that can be tolerated is VIN = VCC, and the lowest LOW

input that can be interpreted correctly is VIN = GND+2.0V.

ECL-TTL Translator

The function of the INB(INB+) input and the SI(INB–) input is

determined by the connection on the SO output pin. If the

ECL/TTL translator function is not re quired, the SO output is

wired to VCC. A sensor circuit detects this connection and

causes the i npu ts t o be come I NB± (a dif ferential line-receiver

for serial-dat a input). If the ECL/TTL translator function is re-

quired, the SO output is conne cted t o a no rmal TTL load (typ-

ically one or more TTL inputs, but no pull-up resistor) and the

inpu ts become INB (single-ended ECL 100K-level serial-data

input) and SI (single-ended ECL 100K-level status input).

This positive-referenced ECL-to-TTL translator is provided to

eliminate external logic between an ECL carrier-detect or link

status signal and a TTL input in the control logic. The input

threshold is compatible with ECL 100K-levels (+5V refer-

enced).

Clock Sync

The Clock Synchronizer function is perform ed by an embed-

ded phase -locke d loop (PLL) that tracks the frequency of the

incoming serial bit-stream and aligns the phase of its internal

bit-rate clock to the serial d ata transitions. This block contains

the logic to transfer the data from the Shifter to the Decode

regis ter once every byte. The counter that controls this trans -

fer is initialized by the Framer logic. CKR is a buffered output

derived fr om t he bit co unter used to control Decode register

and Output register transfers.

Clock output logic is designed such that when reframing

causes the counter sequence to be interrupted, the period

and pulsewidth of CKR will never be less than normal. Re-

framing may stretch the period of CKR by up to 90%, and

either CKR pulsewidth HIGH or pulsewidth LOW may be

stretched, depending on when reframe occurs.

The REFCLK input provides a byte-rate reference frequency

to improve PLL acquisition time and limit unlock ed frequen cy

excursions of CKR when no data is pr esent at the serial in-

puts. The frequency of REFCLK is required to be within

±0.1% of the f requenc y o f th e clo ck tha t drive s the t ran smitter

CKW pin.

Framer

Framer logic checks the incoming bit stream for the pattern

that determines the byte boundaries. This combinatorial logic

filter looks for the ANSI Fibre Channel symbol defined as a

Special Character Comma (K28.5) ( Reference 3). When it is

found, the free-running bit-counter in the Clock Sync block is

synchronously reset to its initial stat e, thus framing the data

on the correct byte boundaries.

Random errors that occur in the serial da ta can corrupt some

data pattern s into a bit patt ern identical to a K28.5, and thus

cause an erroneous data-framing error. The RF input pre-

vents this by inhibiting reframing during times when normal

message data is present. When RF is held LOW , the HOTLink

Receiver deseriali zes the incomin g data without trying to re-

frame the data to incoming patterns. When RF rises, RDY is

inhibited until a K28.5 has been detected, after which RDY

resumes its normal function. While RF is HIGH, it is possible

that an error could cause misframing, after which all data will

be corrupted. Likewise, a K28.7 followed by D11.x, D20.x, or

an SVS (C0.7) followed by D11.x will cause erroneous fram-

ing. These sequences must be avoided while RF is HIGH.

If RF remains HIGH for greater than 20 48 bytes, t he framer

switches to double-byte framing , requiring two K28.5 Special

Characters within five bytes.

Shifter

The Shifter accepts serial data from one of the Serial Data

input pairs one bit at a time, as clocked by the Clock Sync

logic. Data is examined by the Framer on each bit, and is

transferr ed to t h e De code r e gister once per byte.

Decode Register

The Decode register accepts data from the Shifter once per

byte as determi n ed by the logic in the Clock Sync block. It is

Figure 3. CY7B933 Receiver Logic Block Di agram

A/B

INA+

REFCLK

MODE

BISTEN

ECL

TTL

Test

Logic

Clock

Sync

CKR RDY SC/D (Qa)

RVS (Qj)

Q0–7

(Qb – h)

Ou tput Reg iste r

Decoder

Decoder Register

Shifter

Framer

Data

INA–

INB+

INB–(SI)

HOTLink Design Considerations

prese nted to the Decoder and held u ntil i t is t ransferred to the

output latch .

Decoder

Parallel data is trans formed from ANSI Fibre Channel 8B/10B

codes (Reference 3) ba ck to “raw d ata” in the Decoder. This

block us es t he standard d ecoder pattern s fo und in the Valid

Data Characters and V alid Special Character Codes and Se-

quences (code tables are available in the CY7B923/

CY7B933 data sheet). Data patterns are signaled by a LOW

on the SC/D output and Special Character patterns are sig-

naled by a HIGH on the SC/D output. Unused patterns or

disparity errors are signaled as errors by a HIGH on the RVS

(Received Violation Symbol) output and by specific Special

Character codes.

Output Register

The Output register holds the recovered data (Q0–7, SC/D,

and RVS) and aligns it with the recovered byte clock (CKR).

This synchronization insures pr oper timing to match a FIFO

interface or other logic that require s glitch free and specified

output behavior. Outputs change synchronously with the ris-

ing edge of CKR.

In BIST mode, this register becomes the signature pattern

generator a nd c hecke r by logically convert in g itself into a Lin-

ear-Feedback Shift-Register (LFSR) pattern generator. When

enabled, this LFSR generates a 511-byte sequence that in-

cludes all Data and Special Character codes, including the

explicit violation symbols . This pattern provides a predictable

but pseudo-random sequence that can be matched to an

identical LFSR in the transmitter. When synchronized, it

checks each byte in the Decod er wit h each byte gene rated by

the LFSR and indicates errors using R VS. Patterns generated

by the LFSR are compared after being buffered to the output

pins and then fed back to the comparators, allowing test of the

entire receive function.

In BI ST mode, the LFSR is initiali zed by the f irst oc currence

of the transmitter BIST loop start code D0.0 (D0.0 is sent only

once per BIST loop). Once the BIS T loop has been started,

RVS will be HIGH for pattern mismatches between the re-

ceived sequence and the internally generated sequence.

Code rule violatio ns or running disparity er rors th at oc cur a s

part of the BIST lo op do not cause an error i ndicat ion. RDY

puls es high once per BIST loop and can be use d to check test

pattern progress. The receiver BIST checker can be reiniti al-

ized by leavin g and re-enter ing BIS T mode.

Test Logic

Test logic includes the initialization and control for the built-in

self-te st (BIST) checker, the multiplexer for Test m ode clock

distribution, and control logic for the decoder. Test logic is

discussed in more detail in the CY7B923/CY7B933 HOTLink

data sheet .

HOTLink Serial Signal Characteristics

The serial in terfaces on the HOTLink Transmitter and Receiv-

er are based on the standard for high-speed digital logic

called emitter-coupled-logic or ECL. This form of logic has

been used commercially in integrated circ uits since the early

1960s, and pr ior to th at it was i mplemented in discrete form.

ECL is a non-saturating form of digital logic. ECL gets its

name f rom how the emi tt ers of a differential amplifier in the

circuit are connected. The main features of this logic family

are ve ry hig h speed , low noise, and the ability to drive low-im-

pedance transmission lines.

In the past, many engineers have avoided ECL as a logic

family because it was different from the TLL-compatible fam-

ilies with which they were more familiar. Proper use of ECL

requires the understanding and application of transmission

lines, line termination, and power supply b ypass ing. Because

of the faster speeds present in the newer TTL compatible fam-

ilies, these same disciplines a re now required fo r TTL circuits

as well.

ECL Signal Level Reference

The primary differences between ECL and other logic families

are the signal levels used to represent the HIGH and LOW

logic level s.

In the TTL and CMOS l ogic families, a LOW is usually some

level close to VSS, and a HIGH is usually som e level close to

VCC. The ground or reference point for these measurements

is usua lly the VSS point, with VCC set to +5V from that ground

reference.

In standard ECL this changes significantly. Instead of having

the ground reference at VSS, it is placed at VCC. This means

that both HIGH and LOW logic levels exist at potentials th at

are negative with respect to ground. Standard ECL is speci-

fied a s operat ing with a negative su pply ( –4.5V to –5.2V for

VEE). Since ground is only a reference point, it is also possible

to operate ECL with a positive supply. When used in this mode

ECL is usually referred to as PECL which means Positive

ECL.

ECL Basic Switch

Internally, ECL gates (or switches) operate using a current

source whose current is directed through one of two paths

back to VCC. A schematic of this basic ECL switch is shown

Figure 4

(Reference 5).

In this ECL switch, the state of the switch is determined by the

voltage drop across R1 a nd R2. T he output signal swing is se t

by the size o f these resistors and the magn itude of the current

passed through them.

The base of Q2 is biased at a fixed voltage called VBB. This

voltage determines at what level of VIN on Q1 that the majority

of the current flowing in the switch changes from R1 to R2. If

VIN is set to the same voltage as VBB, the current divides

equally between R1 and R2. In creasing VIN b y 125 mV above

VBB causes essentially all the current to be run through Q1

Figure 4. Basic ECL Switch

R1 R2

Q1 Q2

VIN VBB

VCC

VEE

VC2

VC1

HOTLink Design Considerations

(and hence R1). Lowering VIN to 125 mV below V BB causes

essentially all the cu rrent to flow through Q2. This mean s that

an input swin g of as li ttle as 250 mV can cause the ECL gate

to switch completely from a 0 to a 1. To provide noise immu-

nity and allow operation over a wide variety of condi tions, the

actual signal swing specified for ECL signals is around

800 mV.

Emitter-Follower

The switch shown in

Figure 4

can react very quickly but, be-

cause of its high-value resistor pull-ups (R1 and R2), its

switching delay varies di rectly with load capacitance. To allow

larger loads to be driven, and to make the output voltages

compatible with the input of subsequent gates, additional

transistors are added in an emitter- follower co nfigurati on a s

illustrated in

Figure 5

These emitter-foll ower transistors have a very low on imped-

ance (5–7Ω). This allows ECL gates to drive transmission

lines having impedances as low as 50Ω, and ca n supply loa d

currents of up to 50 mA.

The emitter-follower transistors have an u ncommitted emitter

as their output. This allows the transistor to source, but not

sink, current. This is effectively the op posit e of an open-col-

lector output in a TTL part. To allow the output to function

correctly, it requires a load that operates as a pull-down.

ECL Signal Levels

ECL signals op erate over a very narrow and tightly controlled

range. These signal levels ar e referenced from the VCC pi ns

of the parts.

Figure 6

shows the relationships of the different

output and input levels for ECL gates. The names of these

levels are detailed in

Table 1

ECL Output Signal Levels

ECL outputs are all referenc ed from VCC. A typical ECL driver

has an output-HIGH level (VOH) of VCC – 0.85V and an out-

put-LOW level (VOL) of VCC – 1. 7V. These typical values are

seldom specified for parts because a good design must be

done using the range limits for thes e sign als as l isted i n

Table

. Actual values for the se l evels vary by individual part type

and ECL family.

ECL Input Signal Levels

ECL Inputs are also referenced fr om VCC. A typical ECL re-

ceiver has an input-HIGH (VIH) threshold of VCC – 1.1V and

an input-LOW (VIL) threshold of VCC – 1.47V. These differ-

ences between the output and input HIGH and LOW values

translate directly into the usable noise margin (VNH and VNL)

of a syst em.

Viewing ECL Signals

Proper viewing of ECL signals requires use of an oscilloscope

and probe s with suf ficient ba ndwidth to see th e important fea-

tures of the w aveforms. Depending on the speed of the sig-

nals being viewed, different s cope and probe characteristics

are required.

Oscilloscope Bandwi dth

Oscilloscope bandwidth is not a simple number; it is base d on

the combined bandwidths of mul tiple pieces of the measure-

ment system. These can include the oscilloscope, the sc ope

probe amplifier, the probe itself, and possibly other compo-

nents.

The calculation for bandwidth is based on an inverse

sum-of-squares as shown in

Equation 1

Eq. 1

Figure 5. Buffered ECL Switch

VEE

VBB

VIN

CC1

VCC2

Figure 6. ECL Signal Levels

Table 1. ECL Signal Level N ames

Name Description

VOHH Highest Output HIGH Voltage

VOHL Lowest Output HIGH Voltage

VOLH Highest Output LOW Voltage

VOLL Lowest Output LOW Volt ag e

VIH Lowest Input HIGH Volta ge Thre shold

VIL Highest Input LOW Voltage Thre shold

VNH High Input Noise Margin (VOHL–VIH)

VNL Low Input Noise Margin (VOLH–VIL)

Output Voltage

Level Limits Input Voltage

Sense Levels

VOHH

VOHL VNH

VNL

VIH

VIL

VOLL

VOLH

bw 1

bw1

-----------





bw2

-----------





----------------------------------------------------=

HOTLink Design Considerations

Thus a scope with a 1-GHz bandwidth probe using a 1-GH z

bandwidth amplifier would only have a usable bandwidth of

700 MHz.

The current ANSI Fibre Channel standard specifies the mini-

mum system bandwidth for testing as 1 .8 times the baud rate.

For testing with the HOTLink parts (330 Mbaud), this trans-

lates to a minimum system bandwidth of 600 MHz. This is

translated into a viewable rise time using

Equation 2

(Refer-

ence 6).

Eq. 2

This means that the oscilloscope and probes, having a

600 MHz bandwidth, can display signals with rise-times no

faster than 600 ps, with out having more th an 3 dB of attenu-

ation.

Note: Various scope manufacturers use different conventions

to specify bandwidth for their equipment; i.e., specified band-

width is not necessari ly where the displayed waveforms are

3 dB down in amplitude.

Scope Probes

Scope probes are available with many different characteris-

tics. The three main types are referred to as pa ssive high-im-

pedance, active high-impedance, and passive low-imped-

ance.

Passive high -impedance probes usually range from as low as

10-kΩ to 10-MΩ load impedance. This number i dentifies the

loading effect of the probe when attached to a circuit. The

best feature of high-impedance probes is that their imped-

ance is usually much la rger that those of the circuit under test

and thus do not present any appreciable DC load t o the mea-

sured signal when present.

Passive high-impedance probes do suffer one major draw-

back: significant capacitive loading. Most high-impedance

probe s present from 5 pF t o 20 pF of capac itance at the probe

tip. This capacitance affects measurements in two ways; it

slows down the circuit being m easured, and it degrades t he

rise-time of the pro b e. The u pper bandwidth limi t for passive

high-impedance probes is around 40 0 MHz.

Active high-impedance probes combine a high bandwidth

amplifier with the probe to improve the overall bandwidth of

the system. These probes usually exhibit load imped ances o f

10 kΩ to 1 0 MΩ but have lo ad capacitances of less than 3 pF.

This type of probe has a typical upper bandwidth limit of

around 1 GHz.

Care should be taken when using active probes as the man-

ufacturers specified bandwidth may not be where th e signal

measured is 3 dB down. To achieve the higher bandwidths

some active probes have non-linear responses to equalize

the probe response. When presented with edge rates or fre-

quency components beyond the specified probe bandwidth,

the probe and scope may actually display a distorted wave-

form having more high-frequency components present than

are actually in t he measured signal.

Passive low-impedance (resistive divider) probes are used for

the highest frequency work. These probes are available in

load impedances from 50Ω to 5 kΩ, and present load capac-

itances of 1 pF or less. A typical upper bandwidth limit for

these probes is around 3 GHz. Unlike the high-impedance

probes, low-impedance probes are designed to connec t to a

50Ω tra nsmission line system and do not require compensa-

tion. The probe itself is an extension of the 50 Ω transmission

line present in the scope, and contains a precision resis-

tive-divider at t he probe tip.

The main drawback of passive low-im pedance probes is the

load imped ance they present to the circuit. The rule of thumb

for probes is that the probe impedance needs to be an order

of magnitude greater than the impedances present around it

to avoid any appreciable distortion. To get around this the

probe is of ten designe d as part of the s ystem under test, such

that its impedance is factored into the design. When the probe

is not prese nt it may be necess a ry to change compo nent val-

ues or confi gurations to compensate for the absence of the

probe (Reference 7).

Table 2

shows a summary of typical oscilloscope probe char-

acteristics. For proper viewing of HOTLink ECL signals, an

oscilloscope should have a minimum system bandwidth of

600 MHz. In most cases this will require use of low-imped-

ance probes.

Probe Grounding

As wit h any measure ment, a goo d ground is mandato ry . What

is often misunderstood is just what

a good ground. At the

frequencies used with HOTLink, a long looping ground lead

is abo ut as good as no ground at all. Three factors come into

play: the reflections caused by the scope probe, and the

ground inductance and parasitic capacitance limiting the

probe’s bandwidth. A simple rule of thumb f or ground leads is

that they exhibit about 1 nH of inductance for eac h millimeter

of length. As the length of the probe’s ground lead increases ,

the probe’s r esonance point decreases.

o view a signal with minimal distorti on, the probe’s resonant

frequency must remain above the highest frequency signal

component of interest. The graph in

Figure 7

shows how a

scope probe’s resonant frequency varies for different lengths

of ground loop inductance and tip capaci tance. This graph is

based on

Equation 3

with the diagram of a low-impedance

probe shown in

Figure 8

Eq. 3

From this graph it is quite apparent that a ground lead of only

10 mm cuts the resonan t f requ ency of the probe by 75%. For

signal viewing at HOTLink serial data rates it is usually ne c-

essa ry to use coaxial scope-tip sockets soldered directly to a

circui t board, or some other probe type that probes for signal

and ground without a loose ground lead (Reference 8).

tr0.35

-----------=

Table 2. Typical Probe Characteristics

Probe Type Z Cload BW (MHz)

Passive High-Z 10 k–

10 MΩ5–20 pF 400

Active High-Z 10 k–

10 MΩ3 pF 1000

Passive Low-Z 50–5 kΩ1 pF 3000

ω2π

------------==

HOTLink Design Considerations

Probing From V

The normal mode for probing ECL is to use VCC as the ground

reference. In this mode the signal being viewed is below

ground and is relatively close to the ground refere nce. If the

overall circuit design uses TTL parts in a mix with the negative

referenced ECL, the TTL signals will all exist above ground. If

the ECL parts are operated in a PECL mode where they share

a common VCC supply with other TTL or CMOS parts, all

probing should be done from TTL ground, which is the VEE

side of the ECL parts.

Probing From V

When VEE is used as the scope ground, other issues may

come i nto play. In this mode the ECL signal is now p ositione d

almost 4V above the reference point. While many s copes are

able to pe rform a DC of fset to make the ECL signal viewable,

some do this at the e xpense of sensitivity. In other words, a

signal that is viewable at 100 mV/div when offset less than 2V ,

may only be viewable at 500 mV/div when o ffset by 4 V. Sinc e

the total signal swing for ECL signals is only 8 00 m V, it m ay

be difficult to see a detai led representatio n of the waveform

at this resolution.

Another pr oblem with measuring f rom V EE is that all the ref-

erences in the ECL part are regulated from VCC, not VEE. Th is

mean s that any amplitude chan ges or ripple i n the power sup-

ply are now added int o the displayed waveform.

One way around the offset problem is to AC co uple the signal

into the scop e. Some scopes offer this as a front panel set-up

selection, while others require the addition of a wide-band-

width DC-blocking capacitor in line with the scope probe. Ei-

ther of these will remove all DC components from the signal

under test, and allow the signal to be displayed at the maxi-

mum resolution of t h e oscilloscope.

Wide-bandwidth capacitors designed for this function are

available from most test equipment manufacturers for use

with existing probes and scope amplifiers. Some common ca -

pacitor types for SMA connector probes are the Tektronix

015-1-13-00 and Hewlett-Packard 11742A. For BNC connec-

tored probes the Hewlett-Packard 10240B is also available.

Sample ECL Waveforms

ECL signals, when properly biased, terminated, and by-

passed, are very clean and stable. Any noticeable overshoot

on signals is usually caused by reflections from improperly

terminated transmission lines or improper probing.

Figure 9

shows wh at a pristine single-ended ECL waveform should re-

semble when viewed on a scope.

Both the rising and falling edges are quite symmetrical and

approximate an RC charge/discharge curve. The

peak-to-peak range of the transition covers approximately

800 mV and is centere d around VCC – 1.3V. This signal was

measured using a 500Ω, 1.5-GHz bandwidth low-impedance

probe, on a scope having 1-GHz bandwidth. This signal was

measured with VCC as the prob e ground. The probe load im-

pedance (500Ω) was combined with other bias resistors to

present a 50Ω to VCC – 2V load on the signal.

With incorrect termination, a waveform such as that illustrated

Figure 10

can result. Here t h e spike in the middle of a low

area may cross the recei ver V IH threshold and cause the re-

ceiver to start t o switch.

Figure 7. Scope Probe Resonant Frequency

Figure 8. Scope Probe Tip Schematic

0.1

1.0

10.0

0 5 10 15 20 25 30

1pF

3pF

10pF

Ground Len

(

)

Resonant Frequency (GHz)

C: Parasitic Tip Capacitance

L: G round Loop Inductance

50Ω

450Ω

Figure 9. Good ECL Waveform,

Single-Ended vs. VCC Ground

Ch. 2 = 2 00 .0 mV/di v Offset = –1 .32 0V

Timeb ase = 1.0 0 ns/d iv

Rise Time = 830 ps Fall Time = 880 ps

HOTLink Design Considerations

ECL Logic Families

Just as the TTL compatible world has its 7400, 74LS, 74H,

74S, 74AS, 74ALS, etc. logic families that have evolved over

time, so does ECL. The most common families still in use are

referred t o as 10K (e.g. , SL10104), 10KH (e.g., MC10H11 6),

and 100K (e .g., F10015 0 ). These ECL families differ in terms

of speed, signal levels, noise margin s, and temperatur e and

voltage stability.

10K ECL

The 10K ECL family has been around since 1971. It provides

propagation delays of 2 ns with slow 3.5-ns edge rates

(10%–90%). The voltage swings and switching thr esholds of

this logic family are relatively insensitive to variations in the

power supply voltage but are affected by operating tempera-

ture (–30°C to +85°C). The VBB bias network is fixed at

VCC – 1.29V, and is compensated for voltage and tempera-

ture. In the basic 10K ECL switch the cu rrent so urce is unreg-

ulated and consists of a single resistor between VEE and the

tied emi tters of the differ ential ampl ifier. The tra nsfer curves

of a simple 10K gate are illustrated in

Figure 11

and detail how

this family is sensitive to temperature variations in both inputs

and outputs (Reference 19).

10KH ECL

To improve system speeds, t he 10KH ECL family was intro-

duced in 1981. It reduced propagation delays to 1 ns while

edge rates were set to 1.8 ns. Because the thresholds and

voltage swings remain the same in 10KH as in 10K, thes e two

ECL families are fully compatible with each other. The tem-

perature and voltage compensated VBB reference network

from 10K parts was replaced with a fully compensated and

regulated supply. To improve the VOL l evels t h e resistor cur -

rent source was replaced with a regulated current source.

This allowed the collector resistors in the ECL switch to be

matched and have similar switching characteristics. The

transfer curves of a sim ple 10KH gate (see

Figure 12

) i llus-

trate how this fam ily im proves noise margins over 10K ECL,

yet remains sensitive to temperature variations. The 10KH

family also is specified to operate over a narrower t empera-

ture range (0°C to 75°C) than 10K ECL (Reference 19).

100K ECL

The 100K ECL family is a fa ster and ea sier t o use ECL logic

family . Introduced in 1973, this family improved o n the i nternal

structures to provide 750-ps propagation delays and 1-ns

edge rates. In addition to speed improvements, the 100K ECL

family was the first to introduce full compensation. This

means that all the critical structures in the parts are now com-

pens a ted fo r variation s in voltage and temperature. This min-

imizes differences in propagation delays from one stage to

the next that limit the maximum operating rate of a system.

This stability is illust rated in the tr ansf er curv es in

Figure 13

(Reference 5).

Figure 10. Bad ECL Waveform

Ch. 1 = 200.0 mV/div Offset = –1.332V

Timebase = 2.00 ns/div Delay = 0.00000s

Figure 11. 10K ECL Tra nsfer Functions

Figure 12. 10KH ECL Tra nsfer Functio ns

VEE= –5.2V °10%, Rt=50Ω to –2V

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

–2.0 –1.8 –1.6 –1.4 –1.2 –1.0 –0.8 –0.6

VIN (Vol ts)

25°C

–30°C

85°C

–30°C

25°C

85°C

VEE= –5.2V ±5%, Rt=50Ω to –2V

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

–2.0 –1.8 –1.6 –1.4 –1.2 –1.0 –0.8 –0.6

VIN (Vol ts)

75°C

25°C

0°C75°C

25°C0°C

HOTLink Design Considerations

In the 100K ECL family the operating temperature range is

expanded to 0°C to 85°C but the nominal operating voltage

changes from –5.2V to –4.5V.

HOTLink ECL Outputs

All ECL outputs of the HOTLink Transmitter are ECL

100K-level compatible. This means that these outputs meet

or e xceed all voltage, current, and edge r ates specifi cations

of 1 00K ECL and w ill interoperate w ith other 100K ECL parts.

This signal level compatibility is required by the ANSI Fibre

Channel standard (Reference 3).

The HOTLink ECL outputs actually are substantially better

than the 100K ECL specification, allowing operation with

5V±10% supplies over the full –55°C to +125°C temperature

range. This allows the HOTLink parts to be used in a TTL,

PECL, or ECL environment.

The HOTLink Transmitter has six ECL outputs configured as

three differential pairs: OUTA±, OUTB±, and OUTC± (see

Figure 2

). These different ial outputs may be used to commu-

nicate wi th ECL compatible r eceivers in either single-ended

(str ongl y discouraged) or differential (pref erred) modes.

HOTLink Transmitter Sin gle-Ended Connections

A single-ended connect ion is u sed most often for logic func-

tions. In this type of a connection, a single output of a driver

is attached to a single i n put of a receiver. The receivin g ele-

ment is thus dependent on the driver and interconnect for

maintaining the input signal in the narrow voltage bands spec-

ified for a valid logic 1 or 0.

Figure 14

illustrates th e basic components of a single-ended

connection. The driver different ial pair outputs are biased to

allow them to switch. The receiver, a s wi th all ECL gates, is

based on a differential amplifier . In the case of a single-ended

receiver, the second input int o th e differ e ntial amplifier is not

prese nt at an external pin on the chip, but is instead connect-

ed internally to a VBB referen ce voltage. As the signal present

on IN+ goes either a bove or below the internal threshold set

by VBB, the receiver will switch.

Whil e conn ections of this type are perfectly fine for logic func-

tions, they should be avoided for a communications link. In a

single-ended environment, any signal level differences

(caused by temperature, logic family , transients, power supply

noise, etc.) directly af fect the receive d sign al t iming. In a logic

function t his timing variation limit s a design both in determin-

ing how fast the system may operate, and in how much noise

margin is present.

In a communications link these variations in timi ng translate

dire ctly into jitter in the serial d ata stream. Jitter affects a se-

rial link by limiting not only how fast the link c an operate (data

rate) but also how far the data can be s ent. J itte r is discussed

in detail later in this docum ent .

The only expected single-ended connection on a HOTLink

Transmitter is for a local loopback function to a HOTLink Re-

ceiver (when the INB– input is not available for a differential

connection because it has been used as an ECL-to-TTL

translator). In this connection it is expected that the transmit-

ter and receiver are in relatively close proximity, such tha t th e

connection between them is more on the order of a lo gic con-

nection than a communications link. The small amount of jitter

caused by the sin gle-ended connection will be far below the

jitter susceptibility of the HOTLink Receiver.

HOTLink Transmitter Differenti al Connections

A d iffer en tia l connection is the preferred attachment for HOT-

Link Transmitter serial outputs. In a differential connection

both outputs a of a driver are connected to the true and com-

plement inputs of an ECL-compatible receiver. When con-

nected in this fashion the majority of the interconnect depen-

dencies are r emoved. The main advantages of a differential

connection are insensitivity to the logic family, operating tem-

perature, and power supply variations. In addition, the con-

nection is now immune to most common-mode noise.

Figure 15

illustrates the basic components of a differential

connectio n. T he driver differential pair outputs are biased to

allow them to switch. Now both true and complement inputs

of the receiver differential amplifier are available at external

pins and are connected to the complementary o utputs of the

driver.

Figure 13. 100K ECL Transfer Functions

VEE=–4.5V ±7%, Rt=50Ω to –2V

TC=0°C to 85°C

VIN (V olts)

–1.8 –1.6 –1.4 –1.2 –1.0 –0.8 –0.6–2.0

–2.0

–1.8

–1.6

–1.4

–1.2

–1.0

–0.8

–0.6

Figure 14. Single-Ended Connection

Driver Receiver

OUT+

OUT–

VBB

Threshold Bias

Generator

VEE

IN+ +

–

HOTLink Design Considerations

Some ECL differential receivers may also provide an external

VBB reference. This reference is provided for those cases

where a driver is connected single-ended to one of the differ-

ential receiver inputs. The other receiver input must then be

connec ted to the VBB reference to allow the receiver to switch.

With a tru e differential connection thi s VBB output should re-

main open.

The main concerns in a differential connection are signal

skew and crosstalk. Sk ew is the difference in ar rival time of

the OUT+ and OUT– signals at th e receiver. Crosstalk is t he

coupling of energy between these same two sig nals.

As the amoun t of signal skew present in a differential connec-

tion is increased, the effective signal rise and fall times at the

differential receiver also increase. In systems with large

amou nts of signal skew, it is possible fo r short pulses to never

be detected by the r e ceiver.

The main cause for signal skew is asymmetric routi ng of the

true and complement signals b etween the driver and the re-

ceiver. A 1-inch difference in routing length is equal to about

150 ps of signal sk ew. This problem is corrected by maintain-

ing matched signal runs between the HOTLink Transmitter

and the ECL differential receiver.

The main cause for crosstalk is long parallel signal runs. The

adjacent lines act as coupling transformers and transfer en-

ergy from one to another . One cure for this is to limit the le ngth

of the connection by pl acing the ECL differential receiver a s

close to the HOTLink Transmitter as poss ib le . Oth e r possibil-

ities are to route the two signals on opposite sides of a circuit

board with an interposed power plane to act as a shield. If

routing is to remain on t he s ame plane, the crosstalk affects

can be minimized by horizontally separating the two sig nal s

as far as p ossible or by routing a ground t race (with many vias

to attach the gro und trace to the ground pla ne) between the

two signals.

HOTLink ECL Inputs

The ECL inputs on the HOTLink Receiver are also ECL

100K-level compatible. Similar to the transmitter , these inputs

have also b een en hance d to o perate o ver a wider range than

standard 100K ECL.

The differential INA± and INB± inputs offer improved mini-

mum sensitivity of 50 mV, compared to 150 mV for the few

100K ECL di ff erential receivers available. These inputs may

be connected directly t o eit her power rail wit hout damage to

the part, or changing the internal thresholds of other sections

of the receiver. These same differential inputs also operate

with a 3V common-mode rejection range (VCC down to

VCC – 3V) that is twice the 1.5V range of standard 100K ECL

differential receivers (VCC – 0.5V down to VCC – 2V).

Note: While differential outputs are quite common on ECL

parts, true differential inputs are rare. The most common us-

age for differential inputs is on line receivers and clock drivers.

The common-mode ra nge on some parts with differential in-

puts is quite limited and should not be expected to operate

over e ven a narrow range unless exp licitly stated in the man-

ufacturer’s data sheet.

The INA± inputs of the HOTLink Receiver sh ould always be

connected to a differential signal source. Since there is no

VBB reference output on the receiver there is no way to prop-

erly bias the second input of the differential receiver.

The INB± inputs may be configured to operate either as a

differe ntial r e ceiver (in which case it should be connected to

a differential signal source) or as two single-ende d rece iv ers .

When operated as two s ingle-ended receivers (as configured

using the SO pin) the INB+ input operates as a 100K ECL

single-ended rece iver for serial data, while the INB–(SI) input

operates as a 100K ECL single-ended receiver for an

ECL-to-TTL level translator. The VBB reference for these sig-

nals is availabl e only inside the HOTLink Receiver and is not

brought to an external pin. Signals connected to these sin-

gle-ended in puts must now ensure operation within the 100K

threshold levels.

Mixing ECL Logic Families

It is often de si rable to use ECL parts of different f amilies to-

gether in the sam e design. This can be done if cert ain rules

are followed. The main r easons for these rules are the vari-

ability in signali ng levels in ECL 10K family part s.

Figure 16

shows a DC-level comparison for 100K ECL outputs driving

single-ended 10K ECL inputs.

In this configuration there is only 20 mV of margin between

the 100K VOHL and the 10K VIH at t he upper e nd of t he tem-

perature range. With 10K parts driving other 10K parts (as-

suming a common operating temperature) this is not a prob-

lem as the internal VBB r efe renc e in eac h p art follows a similar

temperature shift. If the case temperature of the receiving

10K part can be kept below 35°C (100-mV margin), it can

safely be used with 100K ECL parts for logic functions.

While the VOLH specification appears to also have a noise

margin problem, it does not. What occurs here is a conditi on

where the receiver may be operated outside its linear reg ion ;

i.e., 1s and 0s will be detected properly but the timing re-

sponse may not match the manufacturer’ s data sheet.

Figure 17

shows the opposite configuration with 10K ECL

logic driving either a single-ended 100K ECL receiver or a

HOTLink Receiver. Here there are no ti ght margin areas be-

tween in put and output thresholds. This means that 10K ECL

parts can safely be used to drive 100K ECL inputs over their

full temperature range.

Figure 15. Different ial C onnectio n

Driver Receiver

OUT+

OUT–

VBB

Threshold Bias

Generator

VCC

VEE

IN+ +–

VBB

IN–

HOTLink Design Considerations

Figure 16. 100K ECL Drivi ng 10K ECL

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

–55–45 –35–25–15 –5 5 15 25 35 45 55 65 75 85 95 105115 125

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

10K Input

Range 100K Output

Range HOTLink Output

Range

Low Real

Margin

Low Data

Sheet Margin Logic 0

Levels

Logic 1

Levels

Case Temperature (°C)

Figure 17. 10K ECL Driving 1 0 0K EC L

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

–55–45–35–25–15 –5 5 15 25 35 45 55 65 75 85 95 105115125

AAAA

AAA

AAAA

AAA

AAAA

10K Output

Range 100K Input

Range HOTLink Input

Range

Logic 0

Levels

Logic 1

Levels

Case Temperature (°C)

Vcc (0)

–3.0

HOTLink Design Considerations

Figure 17

also highlights the enhanced input range for the

HOTLink Receiver. Unli ke the narrow input range present on

standard ECL families, the ECL inputs on the HOTLink Re-

ceiver maintain normal operation over the entire VCC to

VCC – 3V range.

Single-Ended Connections

Both of these comparisons are b ased on single- ended con-

nections, w here only a single ECL output is used to drive the

receiving internally referenced single-ended gate. In these

cases, the other input to the receiving different ial amplif ier i s

connected internally to a VBB reference. This type of connec-

tion should not be used t o drive the INA± or INB± differential

inputs of the HOTLink Receiver.

Differential Connections

One of the biggest ad vantages of ECL is the abil ity to com-

municate in a differential mode. This mode is relatively rare

on logic parts (most commonly used f or clock d rivers and l ine

receivers), as it requires both the driving and receiving parts

to ha ve both true and c omplement outputs and inpu ts respec-

tively. When connected in this manner, the receiving part is

no longer comparing the input signal to its VBB reference, but

instead compares the true and complement inputs to each

other.

When used i n this mode there is no problem using 100K ECL

with 10K ECL at any temperatur e. Because an ECL receiver

only requires around 250 mV of

difference

to fully switch, and

the difference between the outputs of a differe ntial driver re-

mains near 800 mV, any differential connection has a mini-

mum of twice the noise margin of a single-ended connection.

This ty pe of connectio n is also immune to minor differences

in the reference voltages between parts. Because the con-

nection is differential, any c ommon-mode v oltages present on

the received signals (due to power supply differences, AC

coupling, ground shift, etc.) within the common-m ode ra nge

are canceled out in t he receiving differ ential am plifier. Some

ECL parts wi th dif ferential inputs can ac cept up to 1V of com-

mon-mode offset on the received signal without degradation

of performance. The enhanced 100K ECL compatible inputs

of the HOTLink Rece iver can acc ept inputs between VCC and

VCC – 3V, offering a commo n-mode range of 3V.

HOTLink Transmitter Connections

Unlike conventional negative-referenced ECL, the

high-speed outputs on the HOTLink Transmitter are imple-

mented in 100K positive -referenc ed ECL (PECL). This al lows

the TTL and ECL interfaces on the t ransmitter to o perate from

a common +5V power supply.

The HOTLink Transmitter has three differential output sec-

tions: OUTA±, OUTB±, and O UTC±. In a ddition t o operati ng

as 100K ECL-compatible signals, these outputs have been

enhanced with additional features.

Power Saving Mode

A standard ECL output structure uses a constant current

source at the base of a differential amplifier (see

Figure 5

). In

these standard parts, this current so urce is enabled and dis-

sipating power even when the outputs are not used.

The HOTLink T ransmitter ECL outputs, while still operating as

true 100K ECL outputs, incorporate some additional struc-

tures (see

Figure 18

) to save power when the outputs are not

used. The differential amplifier (D1) under normal conditions

will direct the IS current from the current source through its

internal transistors. As this current is switched, the output

driver transistors (Q1 and Q2) change their operation point

and the amount of current they source (a properly biased ECL

output sources current in both 1 and 0 states; i.e., it does not

turn off). Each output driver (Q1 and Q2) contains a high val-

ue pull-up resistor (RO+ and RO–) and a voltage comparator

(C1 a n d C2).

When both voltage co mparators of a HOTLink d ifferential out-

put detect a voltage above a 100K ECL output-high level

(VTH), the current source (IS) for that differential output pair is

disabled. This results in a current savings of around 5 mA

(25 mΩ) for each unused output pair.

FOTO Control of OUTA ± and OUTB±

The HOTLink transmitter OUTA± and OUTB± differential out-

puts have an additional control input not present in the

OUTC± o utput pair. While the OUTC± outputs are a lways e n-

abled to follow th e serial data stream generate d in th e HOT-

Link Transmitter shift er, the OUTA± and OUTB± outputs are

not. These outputs are also controlled by a TTL-level input

called FOTO (fiber-optic transmitter-off). While OUTA± and

OUTB± are disabled, the OUTC± pair remains active and can

be used for a local loopback source.

This FO TO signal is u sed to force the differenti al outputs of

the OUTA± and OUTB± drivers to a state where a logical 0 is

being driven. This state corresponds to a condition on optica l

modules where no light is transmitted. While not r equired for

LED-based optical modules, this ca pability is required for la-

ser-based links (see ANSI Z136.1 and Z136.2, F. D.A regula-

tion 21 CFR subchapter J, and I EC 825) (References 9, 10,

11, 12, 13).

ECL Output Biasing

ECL outputs have specific loading requirements to insure

proper operation. Becau se of the o pen-emitter s tructu re of an

ECL output, it can source current b ut cannot sink current. To

allow the output to switch, some form of pull-down is required

on the output. This pull-down usually takes the form of a re-

sistive load; eith er to VEE or VCC –2V.

Most ECL outputs ar e specified for driving load impedances

as low as 50Ω. Because an ECL output does not swing

rail-to-rail, this load is usually specified at VCC –2V, a point

Figure 18. HOTLink Tra nsm itter ECL Output

D1 Q2

Q1 OUT+

OUT–

VEE

VCC

VTH

RO+

RO–

HOTLink Design Considerations

slightly below the ECL VOL. At this point, when the ECL gate

is driving a logic-0 level signal, a small current is running

through the load resistor to ke ep t he out put tra nsist or in t he

active regio n. T yp ical currents sourced when driving a logic-1

(IOH) and logic-0 (IOL) are calculated using

Equations

4 and

5 respectivel y, where RT is the effective load impedance and

VTT is the effecti ve bias voltage.

Eq. 4

Eq. 5

These IOH and IOL values are the basis for the timing and

signal le vels in the HOTLink data sheet. For other values of

IOH and IOL, t he tra nsmitter will exhibit slightly different c har-

acter isti cs. These current flows can be achieved in many

ways. T he four m ost common methods are

• Shunt bias to VTT bias voltage

• Shunt bias to VEE bias voltage

• Thévenin bias to VTT bias voltage

• Y-bias to VTT bias voltage

Sh unt Bias to V

In shunt bias, as illustrated in

Figure 19

, a single resistor is

used as a pull-down load on an ECL output to some bias

voltage . When biased to VTT, a single 50Ω res i stor (R T) from

the ECL outp ut to VTT is all that is necessary. This requires

an add itional power supply to provide the (VCC – 2V) VTT-lev-

el. This terminati on type dissip at es the le ast average-power

(13 mΩ) of any output load type. It is often used in large ECL

systems, in systems where overall power dissipation is a ma-

jor concern, or where there is enou gh ECL present to warrant

its design and implementation.

Sh unt Bias to V

ECL outputs may also be biased to the VEE supply as illus-

trated in

F igure 20

. Here a load resistance (RT) of near 270Ω

is connected to the VEE supply to provide a similar current

load for the ECL output driver. This value is determined by

taking the average current flow for both a 1 and a 0 at the

midway point (VBB) in the output swing. The calculation for

this is shown in

Equation 6

Eq. 6

Unlike the shunt b ias t o V TT, this bias arrangement dissipates

a significant amount of power in both the 1 and 0 states

(47 mΩ average). This bias type (due to mismatched RC

charge and discharge rates) exhibits a faster falling edge than

rising edge. Because of this, its use is usually limited to logic

functions, and is discoura ged f or serial links and for biasing

differential output pairs. This is discu ssed in detail later in this

document.

Thévenin Bias to V

In a Théven in bias network, a pair of resistors (R1 and R2) is

used to create a load whose Thévenin equivalent matches

that of a single resistor attached to a specific bias voltage

(VTT). For ECL this voltage is usually VCC – 2V. These r esis-

tors are connected a s illustrated in

Figure 21

. The values of

R1 and R2 are solved using

Equations 7

and 8.

Eq. 7

Eq. 8

Solving for 50Ω an d VCC – 2V yields values o f 8 2Ω a nd 120Ω

for a 5V system. While this combination does provide a similar

dynamic load to the shunt bias to VTT, it dissipates nearly an

order of magnitude more power (138 mΩ) than its shunt to

VTT equivalent.

The capacitor s hown in

Figure 21

is needed to allow R1 and

R2 to provide the proper load for AC sig nal s. In a T hévenin

equivalent circuit, the power supply is assumed to be a short

circuit. While this may be accurate for DC or very low frequen-

cy AC signals, the power supply appears as a near infinite

impedance at RF frequencies. The bypass capacitor across

R1 and R2 is used to create an AC short. This capacitor mus t

be sized to operate as a short near the frequencies in use.

For HOTLink-based systems this capacitor should probably

be in the ra nge of 300 pF t o 0.01 µF.

Figure 19. Shunt Bias to VTT

Figure 20. Shunt Bias to VEE

–

--------------------------- 0.9–()2.0–()–

50Ω

-------------------------------------- 22

== =

–

--------------------------- 1.7–()2.0–()–

50Ω

-------------------------------------- 6

== =

VEE

Figure 21. T hévenin Bias Equivalent

–

----------------

--------------------------- 51.3–

22 6+

----------------

----------------- 264Ω===

–

---------------------------=

------------------------=

VEE

VTT

HOTLink Design Considerations

Y-Bias to V

Unlike the three pre viously described terminations, t he, Y-bi-

as can only be used with differenti al outputs. In this co nfigu-

ration the active ECL output (logic 1) is used to source c urrent

for a voltage divider , while the inactive ECL output (logic 0) is

pulled down to the bias voltage created by this divider . A sche-

matic of this bias network is ill ustrated in

Figure 22

Here RT is the desired load impedance, usually 50Ω to

VCC – 2V for ECL sy stems. RL is determined by summing the

currents of a logic 1 and a logic 0 (as shown in

Equations 4

and 5), and calculating the resistance ne cessary to drop the

remaining voltage. This calculation is shown in

Equation 9

and solved for a 50Ω RT.

Eq. 9

This type of bias provides a significant power savings over a

Thévenin bias because only a single pull-down resistor is

used to dissipate p ower for two outputs. F or a 50Ω e quivalent

load the power dissipation is only 110 mΩ for two outputs

(55 mΩ for one). Just as with the Thévenin bias, a capacitor

is necessary to create an AC short.

Matched Loading

Just as the differential amplifier in an ECL switch directs cur-

rent flow, so do the emitter-follower output transistors. As

these transistors are turned on an off, large amounts of cur-

rent are switched through the driver’s VCC package pins . Be-

cause of the inductance present in these pins, trans ients can

be induced in the internal VCC supply.

Fortunately the effects of this lead-inducta nce only manifest

themselves when the current through the VCC supply pin

changes

. If the current is kept stable, no transients are in-

duced. Due to the differential configuration of many ECL out-

puts, it is possible to keep this current stable by having

matched loads on the true and complement outputs of the

differential driver . This means that if a design uses one or both

outputs of a d ifferential driver , they both sho uld drive loads of

the same magnitude.

Figure 23

shows a differential output driver connected to a

load including the package inductance present on the VCC

power pin. As the differential driver change s state, the overall

current th rou gh L1 remains the same (assuming that both R T

loads are the same value).

If one of the two RT load resistors is removed, some very

undesirable things start to happen. The first is that the exter-

nal power supply must now re act to a dynamic rather than a

static need for current. This increases the amount of pow-

er-supply bypassing that is need ed next to the ECL driver VCC

pin. The seco nd is a variation in the internal and external VCC

supplies caused by the dynamic current flow. This effect is

illustr ate d in the following approximati on.

For a single ECL output the current differ ence from a logic 1

to a logic 0 ( into a 50 Ω to VCC – 2V loa d) is 16 mA (see

Equa-

tions 4

and

). From the ECL 100K family data sheets we

know that signal transition times may be under 500 ps. By

assuming the rise and fall portions of the signal are related to

a tria ngular wave form, this transition may be roughly convert-

ed to a fundamental frequency using

Equation 10

Eq. 10

The Fourier series for a triangu lar waveform is listed in

Equa-

tion 11

. This illustrates that most of the energy content is

present at the fundamental frequency with much smaller

compon ents present a t the hig her o dd harmonics. To simplify

the following calculations only the fundamental frequency is

assumed to be present (Reference 24).

Eq. 11

If a package pin inductance of 4 nH is assumed (typical for

many surface mount components),

Equation 12

can be us e d

to determine the impedance of the pac kage at th is freque ncy.

Eq. 12

Using Ohm’s Law we can now convert this change in current

into an internal voltage change, as illustrated in

Equation 13

Figure 22. Y-Bias Network

VEE

VCC

VTT

+–

LOW

-------------------------------------------- 3

---------------- 107Ω===

Figure 23. Loaded Differe ntial Driver

External VCC Su pply

IT=I1+I2

Leadframe

and

Bondwire

Inductance

Internal VCC Bus

Differential Output Driver

Externa l Loads

RTVTT

--------------- 1

2 500E12–

------------------------------- 1

GHz

== =

------- ω0

--- 3ω0

cos 1

------ ω0

cos …+++cos





2π

2π1E9

×4E9–

×25Ω== =

HOTLink Design Considerations

Eq. 13

This temporary difference between the intern al V CC and the

external VCC supply is the same phenomenon known in a TTL

environment as ground bounce.

All of this, of course, is based on the assumption that the

output will be able to switch at this speed (500 ps) and provide

the specified current (16 mA) when presented with a high-im-

pedance sou rce. Wha t actually occ urs is that the output edge

slows down to match the current transfer permitted by the

on-resistance of t he output driver transistor and the package

reactance.

Most ECL parts use a couple of different techniques to com-

bat this problem. Both are quite simple to implement. The first

is t o use a se parate pac kage pin t o provide power to the emit-

ter-follower output transistors. This prevents any VCC shift

caused by the output drivers from affecting the se nsitive dif -

ferential amplifiers and voltage references present in other

parts of the device.

The second method is to maintain a balanced load on the

differential output drivers. Since the rising and falling edge

rates of ECL are very symmetrical, DI1 = DI2. Because these

changes in output current are symmetrical, DIT ≅ 0. From

Equation

13 we know that any induced DV is directly propor-

tional to DI; thus as DI goes t o 0, so does DV.

AC Charact eristics of Output Drivers

In an ECL driver, the time it takes for the signal to rise is

largely determined by its internal resistors and parasitic ca-

pacitors (Cint a nd Rint in

Figure 24

), since the emitter-follower

can supply large currents to charge the load capacitance. The

DC voltage to which the output rises is determined by the

emitter-follower transistor characteristics and the internal

driver resistor (Rint) value. However, the AC voltage (over-

shoot, ringing, etc.) is determined primari ly by the lo ad char-

acteristics. A capacitive load (along with th e induc tance foun d

in the package, printe d circui t traces, and other load compo-

nents) causes the output to rise significantly beyond the an-

ticipated DC output level, since the emitter-follower cannot

supply any compensati ng current at t he top of its transit ion.

Unlike the output rise time, the fall time is primarily deter-

mined by the time constants of the load capacitance and

pull-down circuit. The output LOW voltage (VOL), is deter-

mined by Rint, IS, and the characteristics of the emitter-follow-

er transistor. In a properly designed system the load circuit

has time constants comparable t o (or shorter than) the inter-

nal fall time, such that the emitter-follower can s ource a small

amount of current during the entire time it is switching from

HIGH to LOW . If this is not true, the emitter-follower transistor

will be shut off for part of the transition time, and the output

will foll ow the t ime constant of the load.

Figure 25

illustrates the effects of two different load or bias

circuits. The assumption in both of these e xamples is that the

load circuit controls the fall time of the signal, and that the

pull-down current is being supplied by a resistor to a VT of

eith er VCC – 2V or VEE (+3V or ground for a PECL environ-

ment). I n the dashed curve, the standard ECL load of 50Ω to

VCC – 2V is used , causing an outpu t current of approximately

20 m A when the output is HIGH, and 5 mA wh en the o utp ut

is LOW. Thi s load (or i ts equivalent) ca n be created using all

of the previously described bia s networks except shunt bias

to VEE (shown in the solid curv e).

VIX

×16

25Ω× 400

== =

Figure 24. ECL Output Driver with Loading

Rint

Cint

RLCL

Figure 25. Falling Edge Rate Comparison for Bias to VTT and VEE

Vth

2V2V

VOL Determined by ECL Driver

RL=50Ω, V bias=3V

RL=300Ω, Vbias=0V

TRC into

0V Term

TRC into 3V

Term

HOTLink Design Considerations

The same amount of pull-down current can be realized wi th a

single resistor (RL in

Figure 24

) in a shunt bias to VEE config-

uration. To get a comparable output current (and assure com-

parable voltages at the output) the pull-down resistor would

be chosen to sink approximately the average of I OH and IOL

when connected t o a voltage midway between VOH and VOL

(see

Equation 6

). The IOH and IOL currents listed here would

yield a pull-down resistor of around 300Ω. This type of bias is

perfectly correct and adequate for ECL logic circuits where

the mismatch between r ise and fall times is absorbed into the

normal logic delays and set-up times. In a data tran smission

system the effects of this type of output bias can be unpre-

dictable and will often degrade performance.

Figures 25

and

illustr ate the difference in output fall time

assuming a constant load c apacitance, with the only variation

being the bias resistor and voltage. The 50Ω load resistor

(dashed line) follows an RC discharge curve which ends at

VCC – 2V. For normal loading this

soft

edge rate more clos ely

matches the rise time of the output as controlled by the emit-

ter- foll ow er, and is less affected by variations in load capaci-

tance and reflection currents.

The 300Ω load resistor (solid line) follows an RC discharge

curve which would normally end at VEE (ground). While this

appears to have a crisper edge rate, it will be more s everely

affected by load capacitance variation and tra nsmis si on line

reflection curr ents that must be a c commodated.

Figure 26

shows that with either pull-down the total voltage

swing is th e same a nd is determ ined by the internal voltage

swing of the driver , a s buffered by the emitter-follower transis-

tor. While the RC curve for the 30 0Ω pull-down continues to

VEE, the emitter-follower is turned on and sourcing c urrent at

the VOL point and does not allow the output to continue farther

down the curve.

In either configuration the signal delays match, since both

falling edges cross the mid-swing l ine at the same time, bu t

the rise and fall tim es are different. T hese rise and fall ti m e s

determine the higher frequency spectral components of the

waveform. Differences in these spectral components affect

the termination efficiency and waveform dis tortion caused by

cable attenuation (Reference 14).

Transmission Line Termination

While often confused with ECL output biasing, termi nation of

transmission lines is something quite different. Because of

the reactive characteristics of transmission line termination,

the resistors used for termination m ay often be used as part

of the output bias network, but they perform different func-

tions.

Due to the high swit chin g speeds of ECL, most of the inter-

connect bet ween parts c annot be treated as simpl e connec-

tions. They must instead be treated as transmission lines. The

distance between parts, in conjunction with the signal loading

and rise and fall times, is us ed to determine at what point the

interconnect must be treated as a transmission line. The gen-

eral assumption is that short lines do not require termination,

while long ones do. The determination of what is a long line

is made using

Equation 14

(Reference 5).

Eq. 14

The values for this equation for microstrip construction on

G10/FR4 type board would be

•

max – maximum unterm inated line length

• Tr – source 20% to 80% rise time

•C

– load capacitance (2 p F assumed for a load)

•δ – delay per unit length (0.148-ns/inch)

•C

– capacitance per inch

Running this calcul ation for various impedance and rise-tim e

combinations yields the lengths listed in

Table 3.

Lengths be-

yond those listed h ere requir e terminati on.

Figure 26. Expanded Detail of Falling Edge Rate Comparison

Vth

VOL Determined by ECL Driver

RL=50Ω, Vbias=3V

RL=300Ω, Vbias=0V

Trise

Tpd+

Tpd–

Tfall1

Tfall2

max 1

---

--------





------





-----------–=

HOTLink Design Considerations

The lengths listed in

Table 3

assume digital switching charac-

teristics. The HOTLink ECL serial signals are, for the most

part, analog in nature. This effectively shortens the maximum

unterminated length. For HOTLink serial signals, any ECL

trace greater than one inch in l ength should be terminat ed.

The objective of transmission line termination is to prevent

reflection of power from the destination back to the source.

This is accomplished by terminating a transmission line in its

characteristic impedance (ZO). The two basic types of line

termination are referred to as series and parallel termination.

The actual amount of the source signal reflected is based on

how well th e line impedance matches the destination imped-

ance. This determines how much voltage is reflected back

into the transmission line. This ratio of reflected voltage to

incident voltage is called the reflection co efficient r (rho) and

is shown in

Equation 15

(Reference 5).

Eq. 15

Series Ter minatio n

Series termination (sometimes referred to as source termina-

tion) requires that the load be high-impedance to properly

operate. This type of line termination is not recommende d for

use with HOTLink because of the reactive nature of all parts

at th e high f requenc ies pres ent on the HOTLink ECL signals.

Parallel Termination

In parallel termination the desired characteristic is to termi-

na te the

end

of the line (rather than the source) in its charac-

teristic impedance. This results in a reflection coefficient of

zero; i.e., no signal is reflected. This type of termination is

implemented the same as shunt bias networks.

Figures 27

and 28 show the two equivalen t forms of parallel termination.

Parallel termination offers the advantages of allowing distrib-

uted loads on the transmission line, and of having the termi-

nation net work also operate as the bias network.

In the single-resistor form of parallel termination illustrated in

Figure 27

, the RT resisto r is sized to match the ZO impeda nce

of the tra nsmission line. This terminati on form has the same

advantage as the single resistor shunt bias because it dissi-

pates less overall power than the Thévenin equivalent termi-

nation. It also h as the s ame drawbac k of requiring a separate

power supply.

In a Th évenin equivalent termination (illustrated in

Figure 28

)

two resistors (R1 and R2) are used to form an equivalent cir-

cuit to that in

Figure 27

Table 4

lists the R1 and R2 resistor

values for a number of common transmission line impedanc-

es. Th is table assumes operation with a 5V source and a ter-

mination voltage of VCC – 2V, and selects the nearest stan-

dard 1% resistor value when an exact match is not avail abl e.

These values are calculated u sing the same

Equations 7

and

8 as used for calcu lating a Théven in bias network (Reference

15).

Terminating HOTLink Transmitter ECL Signals

The HOTLink CY7B923 transmitter has three different ECL

differe ntial o utp ut pairs named OUTA±, OUTB± and OUTC±

(see

Figure 2

). How (or if) these outputs are terminated is

dependent on what the outp ut i s used for.

Table 3. 100K ECL Maximum Unterminated Line Length

(in inches) , Microstrip Construction

Line Lengt h (in inches)

0.5 ns 1 ns 1.5 ns

50Ω1.38 3.06 4.74

62Ω1.32 2.99 4.67

75Ω1.25 2.91 4.59

90Ω1.18 2.82 4.50

100Ω1.14 2.76 4.44

Figure 27. Parallel Termination to VTT

----- ρ

–

--------------------==

V1 VT

VTT

Figure 28. Thévenin Equivalent Parallel

Table 4. Thévenin Bias Resistor Val ues

ZOR1 R2

50Ω82.5 124

70Ω118 174

75Ω124 187

80Ω133 200

90Ω150 226

100Ω165 249

120Ω200 301

150Ω249 374

V1 VT

Vcc

VEE

HOTLink Design Considerations

OUTC±

The OUTC± outputs of the HOTLink Transmitter are not con-

trolled by the transmitter FOTO signal and are thus always

enabled t o drive serial data. While fully capable of driving ei-

ther optical modules or copper ca ble s, it is expected that the

most common usage of this differential output will be as a

loca l loo pback t o a HOTLin k CY7B9 33 Receiver INB± inputs.

This signal may be conne cted to the HOTLink Rece iver e ither

differentially or single-ended. When connected differentially,

the OUTC+ output is connected to the INB+ input, and the

OUTC– output is connected to the INB– input. When c onnect-

ed single-ended, the OUTC+ o utput is conne cte d to the INB+

input.

Note: For the INB+ input to be used di ff erentiall y, t he SI/SO

ECL-to-TTL t ranslator (mapped throug h the INB– input) must

be disab led . This is done by connecting the SO output d irectly

to VCC.

Once the connection is made, the type o f te rmination required

is determined by the distanc e between the HOTLink Transmit-

ter and the HOTLink Receiver. If the distance is kept short

enough (under one inch) (Reference 5) no termi nation is re-

quired and th e output only n eeds t o be biased. This can be

done with a single pull- down resistor t o VEE. While this t y pe

of termination does induce some jitter into the serial data

stream (due to mismatched rise a nd fall times), the amount is

well within the receiver limits.

If the distance is greater than one inch, the line should be

terminated (Reference 5). To do this correctly requires deter-

mination of th e characteristic im pedance of the board traces

used to connect t he source and destination. Please see the

Cypress Semicon ductor application note “ Driving Copper Ca-

bles wit h HOTLink” for informati on on how t o determine the

char acteristi c impedance of various types of transmission

lines (Reference 16).

For local connections that do not travel through external trans-

mission media (i.e., coax, twisted-pair , optical fiber , etc.) par-

allel termination may be used. The important consideration

here is that both the OUTC+ and OUTC– outputs must be

terminated/biased into the same size of load to maintain a

current balance inside the HOTLink Tra nsmitter.

If neither of the OUTC± ou tputs are used , both outputs sh ould

be lef t open or pulled up to VCC to disable the current source

for the differential driver (see

Figure 18

OUTA± and OUTB±

The OUTA± and OUTB± outputs of the HOTLink Transmitter

are both contr olled by the FO TO signal w hi ch is re quir ed to

meet laser safety regulations for communications links ( Ref-

erences 9, 10, 11, 12, 13). Other than this special enable

signal, these outputs operate the same as the OUTC± out-

puts.

Driving Optical Module s

When connecting to optical modules, it is best to drive the

optical module data inputs differentially. This provides the

highest noise immunity f or t he system, and the lowest signal

jitter. When used with

de facto

standard optical modules this

becomes mandatory becau se the op tical modules have a dif-

ferential data input, yet do not provide a VBB supply to bias

the other input of the differential amplifier of the optical trans-

mi tter. Becau se this in terface is intend ed for driving s ome ex-

ternal segment of optical cable, series termination (which

uses shunt bias to VEE and increases jitter) should not be

used . Since the HOTLink parts will most probab ly be the only

ECL parts in the system, the recommended termination is a

Thévenin or Y-ter mination.

Both the T hévenin and Y-terminations provid e the bias nec-

essa ry fo r the ECL signal to switch, an d the i m pedance nec-

essa ry to te rminate a transmission line. One of these types of

termination/bias should be used even when the distance from

the HOTLink Transmitter to the optical transmitter is short.

This is necessary to maintain symmetrical rise and fall times

for the OUTx± differential outputs.

PECL Optical M odules

Interfacing to optical modules in PECL mode is quite simple,

requiring only a few passive parts. The schematic in

Figure

illustrates the connections and parts necessary for this

type of connection.

One of the k ey items often missed in this t ype of connection

is proper bypassing of the termination/bias networks. The

theory behin d a Thévenin network is that the power supply is

considered as a short for AC. While this may be true for near

DC applications, the base frequencies and harmon ic present

in the HOTLink Transmitter output are far beyond any frequen-

cy the power su pply itself co uld pass.

To make the power supply a short, a capacitor must be placed

across the Théveni n pair. The size of the ca pacitor is deter-

mined by the frequen cy of ope ration of the serial link. A good

rule-of-thumb is to pick the largest value capacitor whose se-

ries re sonant frequency is 30% above the highest baseban d

frequency of the baud rate of the serial data (Reference 17).

Since the data is sent using an NRZ modulation (non-re-

turn-to-zero), the highest baseband frequency is one half the

serial bit-rate (Reference 18).

Another important characteristic is the dielectric type of the

capacitor. For this type of analog operation, a good high fre-

quency RF type capacitor must be specified. This means

specifying either NP0 or C0G type capacitors.

Standard EC L Optical Modules

Those optical modules with the case connected to VCC are

designed for use in a negative DC supply system. These

types o f modules may also be dr iven by a HOTLink T rans mit-

ter.

Figure 29. HOTLink Transmitter -to-PECL Optical Module

CY7B923

330 pF

130 130

DXN

Optical

Driver

HOTLink Design Considerations

By far th e simplest method is to c onnect the modu le the same

as a PECL module, with the e xception of the Case pins . Here,

instead of attaching the Case pins to ground (VEE), they are

attached to VCC. If the case is metallic in nature, care must

then be exercised such that it does not come into direct con-

tact with ground.

If the optical module is to be used below ground, it must be

AC coupled to the HOTL ink T rans mitter . This type of connec-

tion is illustrated in

Figure 30.

The HOTLink T ransmitter outputs are biased the same as for

a PECL optical module. AC coupling capacitors are u sed to

connect the HOTLink Transmitter positive-referenced ECL

outputs to the negative-referenced ECL inputs of the optical

module. These coupling capacitors actually operate as a

bandpass filter, centered around their series resonant fre-

quency. To pass additional low- or high-frequency compo-

nents, additional capacitors s hould be placed in parallel with

the coupling capacitors.

Capacitively coupled signa ls require DC restoration and, if the

connection length warrants, transmission line termination. DC

restoration is necessary t o place the signal swings in the input

range of the ECL receiver. Unlike ECL outputs, which are bi-

ased to a level slightly below their VOL(min)-level (VCC – 2V),

AC coupled ECL inputs need to be bias ed to the center of the

receiver input ra nge. This is the same as the VBB reference

point of VCC – 1.3V. In

Figure 30

, this refere nce point is cre-

ated from a resistive divider network, and bypassed with a

0.01-µF capacitor to provide the dynamic current response

needed for the differential inputs.

While many optical modules or ECL gates generate a

VBB-level, this output

must not

be used to bias this reference

point because it cannot provide sufficient dynamic current.

Th e VBB output of an optical module, or other ECL g ate, is an

unbuffered tap of the internal VBB reference. While fully capa-

ble of delivering the few mA of current necessary to drive an

input, it cannot tolerate the transient currents present at the

end of a low-i mpedance transmission line. Because the VBB

source is unbuffered, this also means that any external tran-

sie nts applied to it will move th e VBB reference

inside

the re-

ceiv e r, with unpredictable consequences.

While it is possible to create a VBB power amplifier (by using

multiple ECL buffers in paral lel) to create a bu ff ered form of

VBB, such amplifiers should not be used with HOTLink. They

are prone to oscillation and ringing. Such amplifiers should

also not b e used for DC restoration (as needed here) beca use

the VBB amplifier is not quite DC stable; i.e. its output usually

contains a low-level (10–50 mV) oscillation whose frequency

is set by the delay through the part. This low-level noise is no t

a problem for logic applicati ons, but for analog applications

causes increased jitter on the biased signals.

In this example, the VEE for the optical module is set to –5.2V.

This is a common supply voltage for ECL circuits. If a different

supp ly voltage is used , the values in the resistive divider must

be changed to maintain the VBB reference point at

VCC – 1.3V.

One drawback of this circuit is the inability to react to a DC

state in the data stream. If the HOTLink Transmitter is set to

transmit all 1s or all 0s (e.g., FOTO is set to disable transmit-

ting), the optical module inputs will both return to a V BB-level.

At this level the optical module’s output will proba bly oscillate

due to the high gain present in the optical module’s

ECL-to-optical translator. In this AC coupled configuration

(wh en o perated with laser-based optical drivers) it is neces-

sary to use some method other t han FOTO to meet the laser

safety restrictions (Ref erences 9, 10, 11, 12, 13).

Driving Copper Media

The ANSI Fibre Channel Standard currently identifies both

coaxial cable and shielded twisted- pair as supported copper

media types. The HOTLink Transmitter easily interfaces to

these and many other types of copper media, and allows

communicating on them at distanc es well beyond the lengths

called out in the ANSI Standa rd (Reference 3).

Numerous charact eristics d etermine how far a signal can be

transmitted on copper media. The most important of these

are:

• Voltage amplitude of the signal fed into the cable

• Jit ter a nd ringing on the source signal

• Attenuation characteri stics of the cable

• Length of the cable

• W hat (if any) equalization is used in the syst em

• Receiver loading and sensitivity

Coupling to the cable (transmission line if on a backplane)

may be done in multiple ways, depending on the media type

and distances involved.

Direct Coupled

For those instances where the signal never leaves the same

chas sis (or ev en the same bo ard) it is possible to directly cou-

ple to the media. Here the media is effectively the circuit board

traces, runs of twisted-pair, twinax, or dual coax. The main

criteria her e is that th ere mu st be no chance for a significant

VCC reference differen ce (transient or DC) between the HOT-

Link Tr ansmitter and HOTLink R eceiver, including any com-

mon-mode induced noise. For the HOTLink Receiver, this

maximum difference is around 1V. Under these conditions the

HOTLink Transm itter and Receiver may be connected as il-

lustrated in

Figure 31.

Figure 30. HOTLink T ransmitter-to-Negative-Referenced

ECL Optical Module

CY7B923

330 pF +5V

OUTA+

OUTA–

130

1000 pF

500

1500 –1.3V

(VBB)

0.01µF

–5.2V

Optical

Driver

DXN

HOTLink Design Considerations

While

Figure 31

shows a 50Ω transmission line, the actual

impedan ce can be higher tha n this. For other impeda nce val-

ues it is n ecessary to change the Thévenin termination net-

works.

When sent through twin coaxial cables (as shown in

Figure

) or two separate trans mission lines , care must be taken to

make sure that both lines are electrically the same length. Any

dif ference i n length c auses one o f the two t ransmitted signals

to arrive at the receiver input either leading or lagging the

other. This difference manifests itself as jitter in the receiver.

If twisted-pair or twinax is used instead, both the OUTA+ and

OUTA– signals combine to form a single signal sent down a

balanced tra nsmission line.

Capacitor Coupled

For configurations where it is possible to have significant

ground or reference differences, some form of AC coupling

becomes necessary. If the signals remain in a well protected

environment (minimal EMI/ESD exposure) this AC coupling

can be performed with capacitors. When this is done , bias/ter-

mination networks are required at both ends of the cable. A

schematic detailing this type of connection is shown in

Figure

Good low-loss RF-grade capacitors should be used for this

applic ation. These parts are available in many different c a se

types and voltage ratings. The capacitors used must be able

to withstand not just the voltage of the signals sent, but of any

DC difference between the transmitter an d receiver and the

maximum ESD ex pected. A typical 1000- pF 50-ΩV C0G ca-

pacitor would be available in an 0805 surface mount case size

(0.08″L x 0.05″Ω x 0.02″H). For on-board applications a

50-ΩV rating shou ld be suf ficient. While capacitors with much

higher break down voltages are available, both cost and space

make their use prohibitive. This same 1 000-pF C0G capacitor

at 5-kV breakdown is almost a half cubic inch in size (Refer-

ence 15).

This type of coupling is very similar to that used to drive an

optical module that is not at the same reference as the HOT-

Link Transmitter. Since the HOTLink Receiver and an optical

module both operate with ECL 100K-level compatible inputs,

this should be expected.

In this configuration, the receiver referenc e point is se t slightly

differe nt from that for a st andard ECL receiver. Part of this is

due to th e HOTLink Rece iv er being designed for operation at

+5V rather than –5.2V or –4.5V. The other is that the HOTLink

Receiver has a wider common-mode range than standard

100K ECL parts. To allow operation over the widest ran ge of

signal conditions the VBB bias netw ork on t he receive end of

the transmission line is set to the center of the HOTLink Re-

ceiver 3V comm o n-mode range at V CC –1.5V.

This capacitively coupled interface is not recommended for

cabling syst ems that leave a cabinet or extend for more than

a few feet. This is primarily due to

• Limited voltage breakdown under ESD situations of the

coupling capacitors

• ESD susceptibility of the receiver due to transients induced

in the cable

• Limited common-m ode r ejection at the receiver end

Addition of a second set of cou pling capacitors at the receive

end may improve some of these characteristics, but it will not

remove them.

Transformer Coupled

The preferred copper attachment method is to transformer

coup le to the media. Trans formers have multiple advantages

in c opper-b ased interfaces. They provide

• Hi gh primar y-to- secondary isolation

• Comm on-mode cancellati on

• Balanced-to-unbalanced conversion

The transformer is similar to a capacitor in that it also has

passband characteristics, limiting both low and high frequen-

cy operation. Proper selection of a coupling transformer al-

lo ws pass ing of the f requencies ne cess ary for HOTLink serial

communications. A schematic detailing a transformer cou-

pled interface is shown in

Figure 33

This transformer-coupled configuration has many similarities

to the capacitively coup led interface. It still provides DC isola-

tion between the HOTLink Tr ansmitter and Receiver, and re-

quire s the VBB bias and terminat ion network at t he receiver.

Figure 31. Di rect- Coupled, Copper Int erface

Figure 32. Capacitive-Coupl ed, Copper Interface

CY7B923

OUTA+

OUTA–

130

CY7B933

330 pF

INA+

INA–

ZO = 50Ω

CY7B923

OUTA+

OUTA–

130

330 pF

1000 pF

3.5V

(VBB)

0.01µF

CY7B93

1500

INA+

INA–

649

ZO = 50Ω

Figure 33. Tran sformer-Coupled, Copper Interface

CY7B933

CY7B923

OUTA+

OUTA– 270

ZO=150Ω

649

1500

3.5V

(VBB)

INA+

INA–

HOTLink Design Considerations

The connection at the HOTLink Transmitter is quite different

now. The output bias network is now a simple pull-down to

VEE. While this causes the transmitter outputs to have asym-

metric rise and fall time s, it d oes not add to the system jitter.

Instead, the true and complement outputs combine in the

transformer to provide a single signal with symmetrical rise

and fa ll times. This bias arrangement also the has the ad van-

tage of delivering the enti re tran smitter output volta ge swing

into the transformer , rather than part into the transformer and

part into th e bias network.

The configuration shown in

Figure 33

uses only a single

transformer and either 150Ω twinax or twisted-pair as the

transmission line. This can be done becaus e the transmission

system remains balanced from end to end. Here the primar y

func tions of the transformer are to provide isolation and com-

mon-mode cancellation.

In a single t ransformer configuration th e tra nsf ormer s hould

be placed a t the source end of the cable. Unlike the HOTLink

differential receiver , which has a full 3V common-mode range,

an ECL output (when sourcing a zero or LOW-level) will re-

spond to high-going signals picked up on the transmission

line.

Figure 34

a second transformer is added to the transmis-

sion system at the receiver end of the cable. This configura-

tion allows use of either balanced or unbalanced (coaxial)

transmission lines. The configuration shown here is a 75Ω

coaxial cable system. Here the first transformer is used for

balanced-to-unbalanced conver sion, while the second trans-

former provides unbalanced-to-balanced conversion.

HOTLink Receiver ECL Inputs

The HOTLink Receiver has five 100K ECL (PECL) compatible

inputs: INA+, INA–, I NB+, INB–(SI), and A/ B (see

Figure 3

The A/B input i s used to select which serial data input (I NA±

or INB±) is fed t o the receiver PLL and shifter.

The INA± differential input is normally used for the primary

receive d data input. Th is input is o nly functional as a dif feren-

tial rece iver. To use i t as a single-ended receive r, a VBB refer-

ence would have to be attached to one of the INA± inputs.

Since the HOTLink Receiver does not provide a VBB output,

this must come from either an external ECL gate o r a resistive

divider. Becau se neither of th ese source s can be gu aranteed

to be at the exact internal VBB reference of th e HOTLink Re-

ceiver (and will thus introduce jitter into the system), operation

of INA+ in sin gle-end ed mode is not recommend ed. Also, op-

eration in single-ended mode gen erally take s tw ice the signal

swing (100 mV for HOTLink) for a receiver to properly detect

data.

The INB± differential input i s expected t o be used as the local

loopback receiver. It is capable of being operated as a differ-

ential receiver, or as two single-ended receivers.

To operat e the INB± inputs as a differential receiver it is ne c-

essa ry to hav e the SO output either directly connec ted to VCC

or pulled up to VCC through a resistor (minimum of

VCC – 250 mV). This pin, while normally used as an output,

has a voltage comparator on the output to both disable it and

to o per ate the INB± inputs as a differential pair. When used

as a differential receiver the INB± inputs o perate th e same as

the INA± inputs.

If the SO pin is instead allowe d to remain in the s tan dard TTL

output range (below VCC – 850 mV), it is enabled as a

TTL-level driver, and is the o utput end of an ECL-to-TTL level

translator. In this mode the HOTLink Receiver INB+ input is a

single-ended ECL receiver for serial data, while the INB– in-

put becomes the input end of the ECL-to-TTL translator. The

expected use of this translator is for converting an ECL carri-

er-detect signal to TTL levels.

ECL Input Levels

Unlike standard 100K ECL logic, the HOTLink ECL inputs a re

designed to operate, not only over the full 100K ECL voltage

and temperature range, but substantially b eyond as well.

Normally 100K ECL inputs should never be raised above

VCC – 700 mV. If this occurs, the input transistor saturates

and can damage other internal structures in the gate. Be-

caus e the HOTL ink Re ceiver is designed f or use in a commu-

nications environment, its input structures are more robust

and can be taken all the way up to VCC with no degradation

in performance. This provides a common-mode operating

ra nge more than twice that of standard ECL.

The HOTLink ECL Receivers also provide higher gain than

that available from standard 100K ECL. The receiver is able

to fully detect 1 s a nd 0s with as litt le a s 50 m V of differential

signal at the inputs. Those few 100K ECL parts capable of

differ ential operat ion usually specify this at 150–200 m V.

The HOTL ink ECL inpu ts are also robust on the VIL(min) side.

When o perated in differential mode these inputs provide full

functio nal ity down to VCC – 3V, yielding a full 3V com-

mon-mode operating range. For single-ended operations

these s ame inputs can be take n a ll the way to VEE (ground or

0V).

Controlling A/B from TTL

While the A/B path select on the HOTLink Receiver is a PECL

input, it can be controlled from a TTL driver with as few as two

re sistors. Contr olling a traditi onal PECL in put from TTL nor-

mally requires a third resistor to limit the high state to the

specified VIH(max). Only a two resistor divider is neede d with

the HOTLink Receiver (as illustrated in

Figure 35

) because it

can tolerate a full VCC-level on its ECL inputs.

HOTLink Receiver Biasing

Unlike ECL outputs, which always require an output bias to

create the output-low level, ECL inputs instead require levels

within their input range to allow them to switch. When the

HOTLink Receiver is directly connected to the bia sed outp ut

of either a 10K, 10KH, or 100K ECL driver (see

Figures 16

and

, these conditions are satisfied.

Figure 34. Dual Transformer-Co uple d, Copper Interface

CY7B923

OUTA+

OUTA– 270

ZO=75ΩCY7B933

INA+

INA–

37.4

649

1500

3.5V

(VBB)

0.01 µF

HOTLink Design Considerations

PECL Optical Modules

Connecting a PECL optical module to the HOTLink Receiver

is the same as connecting two ECL parts together. This is

connection i s illustrated in

Figure 36

A bias network i s requ ired on the ou tput of the optical module

to allow it t o switch. A Thévenin or Y-bias netw ork should be

used on the high-speed serial lines (RO and NRO as illustrat-

ed in

Figure 36

) to keep induced jitter to a minimum. The

signal- or carrier-detect o utp ut (SIG O) of the module is con-

sidered a logic level signal and only requires a pull-down type

of biasing to allow the output to switch.

I f the distan ce be tween the opti cal module and the HOTLi n k

Receiver is short (see

Table 3

) then the bias network may be

placed anywhere between the optical module and the HOT-

Link Receiver. If this distance is long, then the interconnect

traces must be treated as a transmission line and the bias

network must be moved to the receiver to also act as line

termination. If t he transmission line imp edance is other than

50Ω, then different values of resistors are necessary (see

Equations 7

and 8

and

Table 4

Standard ECL Optical Modules

Optical modules with the Case pins connected to VCC are

designed for use in a negative DC supply system. These

types of modules may also drive a HOTLink Receiver.

By far the simplest method is to connect the module the same

as a PECL module, w ith th e exception of the Case pins. Here,

instead of attaching the Case pins to ground (V EE), they are

attached to VCC. If the case is metallic in nature, care must

then be exercised such that it does not come into direct con-

tact with ground.

If the optica l module is us ed belo w ground it must be AC cou-

pled to the HOTLink Receiver. A schematic detailing t his type

of connection i s shown in

Figure 37

From a parts count standpoint this type of connection should

be avoided if at all possible. Just as with the HOTLink tra ns-

mitter-to-nega tive referenced ECL optical modules, this inter-

face requires biasing on both sides of the AC coupling capac-

itors.

Because the signal det ect output of the optical module is not

an AC signal, capacitive coupling cannot be used t o feed this

signal into the HOTLink Receiver INB– input. The simplest

thin g to do here is to use an external ECL-to-TTL translator

(a s illustrated in

Figure 37

.) to c onvert the signal-detect out-

put to a positive referenced TTL environment.

The INA± differential inputs must be biased to near the mid-

point of the common-mode range of the HOTLink Receiver.

The two 50Ω resistors tied to this synthesized reference p oint

are sized to properly termin at e the transmissio n line imped-

ance of the interconnect.

Receiving from Copper Media

The direct-coupled, capacitor- c oupled, and tr an sformer-c ou-

pled configurations for copper interconnec t are c overed in the

HOTLink transmitter-to-copper interface section o f this docu-

ment, wi th schematics of these connections illustrated in

Fig-

ures 31

through

Signal-Detect for C opper Inter face

When interfacing to optical modules, the generati on of a car-

rier- or signal-detect function is a simple connection to an

ECL output. With a copper interface, this signal-detect func-

tion must be built from other components.

The key to a good signal-detect implementation is to create

one that accurately detects the p resence or absen ce o f a val-

id data stream, yet does not load or distort the received signal.

A sampl e carrier-detect circuit is shown in

Figure 38.

This circuit uses a reference divider-network similar to that in

Figure 37

, e xcept that a n additional voltage re ference point is

created. This new reference point sets a threshold for re-

ceived amplitude at which the signa l detect circuit will start to

respond. For this example, this reference point is set to

100 mV above the carrier detect receiver VBB reference point.

This 100-mV offset is also necessary to prevent the 10H11 6

amplifiers fro m os cillating when no signal is present.

A 10H116 was selected here for numerous reas ons. It i s small

(20-pin PLCC), fast (1 ns), and does not have 50-kΩ

pull-down resistors built into its input structures. While t hese

pull-down resistors (present on most ECL parts) are very

handy for logi c design, they have a significant impact when

used for fast analog applicat ions as done here.

T wo s ections of the 10H116 are us ed as rece ived signal level

comparators. One looks for logic-1 levels while the other look

for logic-0 levels. The output of these two comparators are

wire-O Red together and feed an RC network. Th e c apacitor

in this network is charg ed when either of the comparators is

Figure 35. TTL-to-HOTLink PECL Interface

Figure 36. PECL Optical Module-to-HOTLink Receiver

TTL

270

PECL

HOTLink

VCC

CY7B933

330 pF

INA+

INA–

INB+

INB–(SI)

130

270

Optical

Receiver

NRO

SIGO

From

Transmitter OUTC+

HOTLink Design Considerations

turned on, and discharges through a bleeder resistor when

neither comparator is on.

The third section of the 10H116 also operates as a compara-

tor, evaluating the voltage level on the RC network. Because

the level on this capacitor changes so slowly, and ECL oper-

ates a s an analog amplifier, p ositive feedback was added to

cause the comparator to switch fast er and to full ECL levels.

The amount of hysteresis is set by the feedback resistor. For

slow changing sig nal s of this type, a minim um of 150 mV of

hysteresis is recommended.

Figure 37. Negati v e-Referenced Optical Module-to-HOTLink Receiver

Figure 38. Copper Interface Si gnal Detect Circuit

33 0 pF

Optical

Receiver

NRO

SIGO

1000 pF

VCC–1.5V

(VBB)

+5V

649

1500

+5V

0.01 µF

50 CY7B933

INA+

INA–

Carrier

Detect

–5.2V

10H125

VBB

GND

–5.2V

130

270

To Copper

Media

VCC

470

VBB

1.5K

100

10H116

270

10H116

270 2.2K

From Local

Transmitter

10H116

270

150

348

CY7B933

INA+

INA–

INB+

INB–(SI)

HOTLink Design Considerations

Copper Signal Characteristics

Communication on copper-based media is very similar to

communication on optical fiber. Both suffer from increasing

signal degradation with increasing media length.

The transmitted signal is composed of multiple frequency

components, and requires a fairly wide bandwidth media to

propa gate those signal compon ents. A large part of the band-

width requirement is determined by the 8B/10B code and

NRZ modulation used in HOTLink for communication.

NRZ Modulation

NRZ is an acronym for non-return-to-zero. This is o ne of the

most basic types of data encoding whereby a signal is HIGH

for a 1 and LOW for a 0. The upper waveform in

Fi gure 39

illustrates an NRZ data stream. Other forms of modulation

(Manche ster , Bipha se, etc.) are used i n data communications

that encode clock information a s part of the 1s and 0s. With

an NRZ data stream, a phase-locked-loop is necessary to

recover the bit-clock to allow data to be captured (Reference

18).

8B/10B Code Dependencies

A phase- locked-loop (PLL) requires transitio ns meeting spe-

cific criter ia t o allow i t to r ecover a clock. If binary data were

sent serially using only an NRZ modulation, long periods

could exist w here no transiti ons are sent. During these peri-

ods (if they are long enough) the receiving PLL can drift such

that it is no longer able to properly recover the data sent.

8B/10B encoding is used to ensure that sufficient transit ions

are present in the NRZ data stream such that the receiving

PLL remains synchronized to the data.

The 8B/10B code is a run-length limited code. This means

that there are limits to the m aximum and minimum l ength of

a continuous sequence of 1s or 0s in the data stream. The

code operates by converting an 8-bit data byte (with uncon-

trolled transitions) into a 10-bit transmission character (with

controlled transitions). The 8B/10B code is referred to as a 1:5

code because the minim um number of consecutive 1s or 0 s

is one, whi le the maximum number is five (References 1, 2).

T ranslating these code limits into frequencies gives the b ase-

band limit s of the code. For example, w ith a s erial bit-rate of

300 MHz, a pattern sent with the maximum number of con-

secutive 1s a nd 0s (five high, five low) would be equivalent to

a 30-MHz square wave. Using the highest rate of al ternating

bits of 0 and 1 gives a frequency of 150 MHz.

As far as signal prop agation goes, these numbers only refer

to a sinusoidal frequency . Since square waves are used at the

source, there are many additional higher-frequency harmon-

ics present. To propagate a reasonable signal it is recom-

mended that the system bandwidth also include at a minimum

the 3rd harmonic of the highest baseband frequency, and

preferably through the 5th har monic.

For o ur previously described example operatin g at a bit-rate

of 300 MHz, the necessary system bandwidth would be

Eq. 16

Eq. 17

Transmissi on Line Ef fects On Serial Data

In a per fect world a p er fect squar e wave could be launched

down a perfect transmission line and it would come out the

end looking the same as it went in. Unfortunately, the laws of

physics make such a transmission line impossible.

Instead, transmission lines have significant amounts o f para-

sitic capacitance, inductance, resistance, and the termina-

tions are reactive in nature. This m eans th at a lossy sy st em

exists. The c able attenuation characteristics o f c opper cables

are such that the higher frequencies have greater losses than

the lower frequencies ( s ee

Figure 77

for some sample cable

attenuation curves).

When data is sent through such a lossy medium, distortion

occu rs. The higher frequency spec tral components are signif-

icantly reduced in a mplitude, while the lower frequency spec -

tral componen ts are reduced by a less er amount. In addition,

the higher frequency spectral components propagate faster

than the lower f req uency componen ts. The square waves fed

into the cable come out looking like RC charge/discharge

curves.

These frequency-selective losses are equivalent to a time

constant. For very short transmission line s (or very slow data

rates) thi s time constant is short enough that transmitted 1s

and 0s can completely charge or discharge the transmission

line for each bit sent. The input and output sig nal wavef orms

for a transmission line of this type are illustrated in

Figure 39

Because the line can fully charge or discharge on even the

fastest possible transition, the time to reach the receiver

threshold is always the same. This allows t he data out of the

receiver to look just like the data sent into the transmission

line.

Figure 39. Short Time Constant Transmi ssion Line Response

T r ansmission

Line Outp ut

Waveform

NRZ Input

Data

Re ceive r

Threshold

MAX

×()

MIN

–=

3150

MHz

×()30

MHz

–420

MHz

HOTLink Design Considerations

As a transmission line is lengthened, its time constant in-

creases. When th e time cons tant is large enough tha t the line

can no longer be fully charged and dischar ged in a single bit

time, the received data edges become time displaced from

their desired positions. Since coding theory refers to each

transmitted 0 and 1 as a symbol, this type of distortion is

called

intersymbol interference

or ISI. For communications

systems, distortion of this type i s called data-dependent jitter

(DDJ).

Input and output waveforms for a long time c onstant transmis-

sion line are shown in

Figure 40

. The receiver output is added

to illustrate th e edge displacement. As the transmission line

becomes increasingly longer it is even possible for some sin-

gle-bit transitions to not be detected at all by the receiver

(base d on the data pattern sent) because they fail to cross the

receive r threshold. This may be correcte d through use of fre-

quency compensation circuits at either the source (precom-

pensation) or destination (equalization) ends of the transmis-

sion line.

8B/10B Code Running Disparity

The 8B/10B code attempts to limit the maximum distance

(voltage) from the receiver threshold that a transmitted signal

can reach, by con trolling the DC signal co ntent of the charac-

ters sent and t he m aximum separations between 1s and 0s

used to represent each character. To do this the 8B /10B code

provides two 10-bit sequences to represent each 8-bit data

value. The difference between thes e patterns is th e ratio of 1s

to 0s. To determine which of the two values to send, the HOT-

Link T ransmitter c ounts the number of 1s and 0s use d to sen d

each 10-bit transmission character (when operated wit h the

encoder enabled). If the net result is more 1s than 0s (referred

to as positive running disparity), the following data byte is en-

coded using the fo rm with more 0s than 1s. If the net result is

more 0s than 1s (referred to as negative running disparity),

the following data byte is encoded using the form with more

1s than 0s. The goal of this is to maintain as near as possible

a net v alue of DC over time for the serial data sent to minimize

baseline wander.

Baseline Wander

Methods of data encoding that are not DC balanced (i.e.,

4B/5B as used with FDDI) suffer from a characteristic known

as baseline wander. This is a side effect of an AC coupled

sy st em attem pting to propagate a signal that contains a DC

component.

Baseline wander is a ( relatively) long-term, low-freque ncy ef-

fect, generated when the average DC-level of a transmitted

signal varies with the data sent. This DC component is lost

because the transmission system is AC coupled. At the re-

ceiving end of the cable this appears as data that does not

remain centered around the receiver threshold. This effect is

illustrated in

Figure 41

If the receiver was actually presented with perfectly square

pulses (with transitions that always crossed the receiver

threshold) then baseline wander would not be a problem. Un-

fortunately, what ar e a ct ually sent and re ceived are more in

the form of trapezoids with measurable rise and fall times. The

farther a signal drifts from being centered around the receiver

threshold, the more that the threshold crossings are time dis-

placed. This time displacement is also known as jitter.

Jitter

Jitter is a high-frequency deviation from the ideal timing of an

event. Many different aspects of a serial link can affect the

total jitter present in the link. Those based on real and repeat-

able direct measurements are referr ed to as

deterministic jit-

ter

. Other effects, which are not directly repeatable and are

more probabilistic in nature, are called

random jitter

Det erminist ic jitter its elf m ay be br oken into two major com-

ponen ts: those based on the accu racy of th e duty cycle of the

information, and those based on the interaction of the 1s and

0s due to the limited bandwidth of the transmission s ystem.

The jitter that affe cts adjacent edges and duty cycle is called

duty cycle distortion (DCD) . The jitter b ased on th e data pat-

terns sent is calle d data-dependent jitter (DDJ).

Figure 40. L ong Time Constant Transmi ssio n Line Response

Leading-Edge

Jitter

Traili ng-Edge

Jitter

Line Receiver

Output Timing

Tra nsmission

Line Output

Waveform

NRZ Input

Data

Receiver

Threshold

Figure 41. Baseline Wander Example

Fixed

Receiver

Threshold

HOTLink Design Considerations

Data-Dependent Jitt er Characteristics

Data-depen dent jitter (DDJ) is a measurement of intersymbol

interference based on the maximum timing deviations caused

by a worst-case data pattern. DDJ is affected by many envi-

ronmental characteristics, in addition to the code used. Thes e

include the length of th e cable, the attenua tion characteristics

of the c able, the in tegrity o f the signal laun ched in to the cable,

and how well the cable is terminated. Be caus e of the f requen-

cy selective attenuation prese nt in coppe r c abl es, DDJ i s on e

of the main limiting factors on how far a recoverable signal

may be sent.

To measure DDJ for a specific configuration, data patterns

having specific characteristics need to be repeatedly

launched into the cable. These patterns must present the

worst-case transition characteristics b ased on the code used

for sending data. This is usually described in terms of sequen-

tial combinations of long and short 0s and 1s.

A long 0 or 1 is specified as the longest continuous LOW or

HIGH that can be sent. For the 8B/10B code this is f ive bits in

leng th. The short 0 or 1 is the s hortest LOW or HIGH that can

be sent. For the 8B/10B code this is one bit in length. The

sequences used for testing are diagrammed in

Figure 42

A design feature of the HOTL ink T ransmitter is that when nei-

ther data enable is active (ENA and ENN both HIGH), the pa rt

repeatedly s ends out the K28.5 SYNC code. T he 10-bit pat-

tern of this code is 0011111010. Since the transmitter also

tracks disparity, this patt ern is invert ed o n e very other byte.

This al ternating pattern contains the necessary combinations

of long and short 0s a nd 1s for performi n g a proper eye pat-

tern test.

The opening of the “eye” (see

Figure 43

) relative to the width

of a bit cell is a good measure of link integrity. As this window

gets smaller, it becomes more difficult for the HOTLink Re-

ceiver PLL to determine wh er e to sample each bit cell (Ref-

erence 5).

The maximum variation, from early to late, of when the re-

ceived signal crosses the receiver threshold is equal to the

amount of jitter present . This jitter is usually expressed as a

perc entage relative to t he wi dth of a bit cell window. T his re-

lationship i s shown i n

Equation 18

Eq. 18

The oscilloscope illustration in

Figure 44

is an actual DDJ

measurement based on a 100 foot (30.4 m) segment of RG59

cable. The jitter measured in this configuration is approxi-

mately 600 ps.

Dut y-C ycle Distor tion Jitter Characteri sti cs

In most cases duty-cycle distortion (DCD) is caused by the

components used to make a link, rather than the data sent

across the link. I t ma nifests itself as either di fferences in the

rise and fall times or differences in period for bits sent as a 0

compared to bits sent as a 1. This is measured by sending a

pattern down a communications link that does not exhibit DDJ

and using an averaging mode on the oscilloscope to filter out

any random jitter (RJ) that m ay be present.

Figure 42. Eye Pattern Generation Waveforms

Superimposed

Data Patterns

Generate Eye

Patterns

Source

Destination

Bit Rate

Clock

Long 0

Short 1

Long 1

Short 0

Figure 43. Eye Diagram

Figure 44. DDJ Measurement

Threshold Crossing Variation

Bit Cell Window

Eye Opening

Jitter Bit

TIME

VAR

–

Bit

TIME

-------------------------------------------- 100%×=

Ch. 2 = 100.0 mV/div Timebase = 500 ps/div

HOTLink Design Considerations

The HOTLink Transmitter has a built-in DCD pattern genera-

tor that is acti vated by placing the tra nsmi tter in BIS T mode

(BISTEN LOW) while both ENA and ENN remain HIGH. In

this mode the transmitter sends out an alternating 1-0 pattern

(D10.2 or D21.5). As all pulses in a square wave are the

same, this pattern d oes not generate any D DJ. An example

meas urement of DCD for an optica l link is shown i n

Figure 45.

When viewed from the receiver threshold (center horizontal

line) in

Figure 45

, the timing for a logic 1 is seen to be slightly

shorter than that of a logic 0. This difference in time is the

DCD jitter pr esent in t he link.

Random Jitter Characteristics

Random jitter (RJ) is that por tion of ji tter th at is not re petitive

in nature and is caused by external or internal noise in a sys-

tem (thermal noise, EMI, etc.). It is measured by using a data

pattern free of DD J (i.e., the same patt ern used to measure

DCD) relative to the transmitter clock. Now, averaging is

turned off but infinite persistence is enabled. This captures

the maximum variation of a transition relative to the clock. An

example measurement of RJ for an optical link is illustrated

Figure 46.

In this measurement the amount of random jit ter present is

measured by how wide the trace is as it crosses the threshold.

This particular optical link has approximately 200 ps of ran-

dom jitter present. This measurement was made using a

250-Mbit/second data pattern (4-ns/bit).

Equation 18

yields

an RJ of 5% for this link example.

When making measurements of this kind, the tolerances of

the signal sources and accuracy of the test equipment must

also be taken into account. If t he trigger source contains 50

ps of jit ter , and th e s cope t rigger accu racy is ±5 0 ps, then the

actual jitter present may be substantially less than that mea-

sured.

Frequency Char acteristics of 8B/10B Data

Most digital design engineers are used to viewing si gnals in

the time domain using an oscilloscope. This instrument pro-

vides inform ation about how a signal looks referenced to the

passage of time. The waveforms in

Figure 47

illustrate the

HOTLink Transmitter CKW clock on the upper trace and one

of the ECL data outp ut signals on the lower trace. The indi-

vidual bit cells may be seen as the eye be tween the r ising and

falling output e dges.

In the 8B/10B code, data is sent as a non-return-to-zero

(NRZ) waveform. In this waveform the clocking information is

contained in the edges, while the data is contained in the

interval between the edges. While an oscilloscope-type dis-

play allows us to see what the output looks like in terms of

voltage, rise time, period, etc., it does not present any fre-

quency-specific information. To properly design filters, cou-

plers, or transmission systems, it is necessary to know the

frequency characteristics of the sign als. This information can

only be examined thro ugh use of a spectrum analyzer.

A s pectrum analyzer could easily b e called a fre quency do-

main oscilloscope. A conventional spectrum analyzer oper-

Figure 45. DCD Measurement

Ti mebase = 1.00 ns/div Ch. 1 = 200.0 mV/div

Figure 46. RJ Measurement

Figure 47. HOTLi nk Transmitter Serial Data

Ti m eb ase = 2 00 p s/ div Ch. 1 = 1 00 .0 mV/d i v

Ch. 1 = 2.00 0 V/div Offset = 2. 40 0V

Ch. 2 = 2 00 .0 m V/d i v Offset = 0.000V

Timebase = 1.00 ns/di v Delay = 0 .0 0000 s

HOTLink Design Considerations

ates as a swept frequenc y, superheterodyne rec eiver that dis-

play s a signal’ s amplitud e versus its frequenc y. I t operates by

sweeping a narrow-band tuned filter across a specified sec-

tion of the electromagnetic spectrum, and measuring (and

displaying) the rms voltage of the signal at each frequency.

This swept filter technique shows the specific frequen cy com-

ponents that make up a complex signal, b ut does not prov ide

any phase related information ( Reference 22).

The spectrum analyzer output in

Figure 48

illustrates the

spectral characteristics of the HOTLink T ransmitter serial out-

puts when sending the 511-byte BIST patt ern. The data pat-

terns sent in the BIST loop are similar to those sent during

normal communications traf fic. This figure was made using a

30-MHz byte-rate clock (300-MHz bit-rate data). The enve-

lope shows a relatively even distri bution of power below the

bit-rate of the data, and significant amounts o f ene rgy present

in the information out to 1 GHz. This illustrates how neces-

sary it is to have a true wideband transmission system to

propagate the signals.

Figure 49

also shows a large dip in the energy distribution

below 30 MHz. This confirms that the 8B/10B code used h a s

no true DC component.

Figure 49

illustrates th e spectral characteri stic s for the high-

est frequency data pattern that can be sent, a continuous

0101 (D21.5 character) patt ern. With the 30-MH z byte-clock

used here this pattern is equivalent to a 150-MHz square

wave. Unlike

F igure 48

, most of the energy here is loca ted at

the fund amental base frequency of 150 MHz, and at odd h ar-

monics of that frequency. Other frequency components

present in the signal are at least 30 dB down from the data

being sent. These components are either generated by other

parts of the HOTLink circuitry as it clocks, encodes, shifts,

etc., the users data, or from external sources such as pow-

er-supply switching noise.

Figure 50

shows the spectral characteristics for the lowest

legal frequency pattern that can be sent, a continuous

0000011111 (K28.7) pattern. This pattern ends up being an

exact match in period to the source clock (30 MHz) with a

fixed 50% duty cy cle. Here, the largest a mounts of ene rgy are

present at 30 MHz and all odd harmonics above that. The

smal ler frequency components present at the even harmon-

ics are again due to the internal operation of the HOTLink

Transmitter and external system noise. If this figure is com-

pared to

Figure 49

, many of these even harmonic compo-

nents can be seen to have almost exactly the same level in

both figures.

To verify that these spectral characteristics have some resem-

blance to theory, these same two source waveforms were

generated mathematically and analyzed using an FFT (fast

Fourier transform) algorithm. This transform analyzes a

source wavef orm and computes its f requency components.

Because the input waveforms are not true square waves, time

constant curves based on a natural logarithm were used to

synthesize the r ising and falling edges. These rising and fall-

ing e dge equations are listed in

Equa tions 19

and

respec -

tively.

Eq. 19

Eq. 20

In these equations, T represents the time constant for rise and

fall time. For the waveforms generated here, a T of 400 ps was

used .

Figure 51

illustrates the signal generated with these

equations for a 150-MHz clock rate (300-Mbit/second

bit-rate). This is equivalent to the data pattern gene rated b y a

D21.5 character.

Figure 48. BIST Pattern Spectral Characteristics

300 600 900

Reference Level of -10 dBm

Frequency (MHz)

10 dB/Division

Figure 49. 0101 (D21.5) Pattern Spectral Characteristics

Figure 50. 0000011111 (K28.7) Patt ern

Spectral Characteristics

300 600 900

Reference Level of -10 dBm

Fre

uenc

(

MHz

)

10 dB/Division

300 600 900

Reference Level of -10 dBm

Frequency (MHz)

10 dB/Division

–

⁄()

–=

–

⁄()

HOTLink Design Considerations

Running a 4096 point FFT on this waveform yields the spec-

tral components illustrated in

Figure 52

. The v ertical axis here

is plotte d o n a log scale to m atc h up with the sp ectrum ana-

lyzer outputs. This plot illustrate s that the energy of a square

wave having a symmetrical rise and fall is lo cated at the odd

harmonics.

An FFT is based on numeric analysis rather than a physical

measurement and will calculate signal components with an

amplitude of zero. Because Log(0) is equal to –∞, a calculated

FFT does no t have a noise f loor. To plot its results in a usable

form requires the addition of an artificial noise floor to present

the points of interest on a reasonable scale. To allow a better

compariso n,

Figures 52

and

use a noise floor similar to

that measured in the spectrum analyzer charts.

Unlike a spectrum analyzer, which only displays the magni-

tude of the spectral compone nts, an FFT of a waveform yields

both magnitude and phase in re ctangular form as a complex

number. To plot this informat ion for comparison with a spec-

trum analyzer plot requires conversion to polar notation of

magnitude and phase. This calculation of the magnitude por-

tion is done using

Equation 21

(Reference 24).

Eq. 21

This same FFT analysis was performed on the synthesized

K28.7 pattern illustrated in

Figure 53

. This wave form uses the

same 400-ps time constant as

Figure 51

. The FFT based

spectral plot for this wa veform is illu strated in

Figure 54. Be-

cause

it uses the same value for a t ime co nstant , thi s wave-

form has the same rise and fall times as the D21.5 pattern in

Figure 51

. As with the plot for the D21.5 pattern, all of the

energy is contained i n the odd harmonics.

The spectral plots for both the D2 1.5 and K28.7 synthesized

patterns contain slightly more energy in the higher frequency

harmonics than the actual measured signals. This is primarily

due to the sharp knee present when the synthesized wave-

form changes between rising and fall ing. This knee is much

ro under in t he actual signal.

Components

The selection of support components for a HOTLink commu-

nications environment should not be taken lightly . The correct

parts allow construction of a high-bandwidth, low error-rate

system.

Several p arts can be measured as key in a HOTLink system.

These parts are

• Clock Oscillator

• Bypass/Coupling Capacitors

• Fiber -Optic Emit ters

• Fiber -Opti c Detectors

• Pulse Transformer s

• Fiber -Opti c Cable

• Copper Cables

• Ci rcuit B o ard

Figure 51. Synthesized D21.5 Wavefor m

Figure 52. FFT Spectrum of Synthesized D21.5 Patt ern

300 600 900

Frequency (MHz)

D21.1 Pattern

Magnitude Re

Figure 53. Synthesized K28.7 Waveform

Fig ure 54. FFT Spectrum of Synthesized K28.7 Pattern

300 600 900

Fre

uenc

(

MHz

)

K28.7 Pattern

HOTLink Design Considerations

Clock Oscillators

The HOTLink T ransmitter and Receiver are designed to oper-

ate from a very stable clock s ource. To achieve the necessary

frequency accura cy and stability i t is necessary for this clock

source to be based on a quartz crystal.

The current ANSI Fibre Channel stan dard calls out a frequen-

cy accuracy of ±100 ppm for both source and destination (AN-

SI FC-PH 4.1 Section 6.1.2 Table 8, and Section 8 Table 9) to

allow relia ble communications. Clock oscillators with this ini-

tial accuracy are available from multiple sources

(Reference 3).

What must also be considered is lifetime stability. Most oscil-

lator manufacturers can easily de liver product that mee ts the

±100-ppm rating right out of the box, but this limit must be met

over the l ife of t he product, and is affected by the operating

env ironment. The two most critical parameters are referred to

aging

and

temperature

stability.

Aging refers to how an oscillator’s output frequency varies

over time (assuming other environmental factors remain con-

stant). This is usually expressed in ppm/year. For most com-

mon “AT” cut crystals, t he typical aging is 5 ppm/year for t he

first year and 3 ppm/year t h ereafter (5 ppm=.0005%).

A crystal’s resonant frequency also varie s with temperature.

How much it varies is based both on how the crystal is cut,

and ov er how wide a tempe rature range it is used. The stabil-

ity over temperature is a non-linear function and is usually

expressed as some peak-to-peak frequency change over a

temperature range. The process for measuring a nd specify-

ing temperature stability is called out in MIL-O-55310. Tem-

perature stability may easily exceed the initial accuracy s pec-

ification. R atings of ±100 ppm for temperature alone are not

uncommon.

Figure 55

shows a typical t ransfer curve of crys-

tal frequency vs. temperature.

This curve can be rotated on the +25°C axis point by cutting

the crystal differently. This can be used to create an o scillator

that is more stable over a narrow temperature range (say 0°C

to +50°C), yet is much more unstable out side of this range.

Temperature stability and initial accuracy are often combined

in a vendor’s specification; i.e., ±100 ppm at 0°C to 70°C.

These n umbers do n ot tak e in to acco unt the aging c haracter-

istic of stability.

Modified o s cillat ors are avail abl e th at allow for a wi d er oper-

ating environment while maintaining a high stability. These

are referred to as either TCXO (temperature compensated

crystal oscillator) or OCXO (oven controlled crystal oscilla-

tor).

The TCXO is us ually built by a dding a va ractor diode in series

with the crystal. A special thermistor network across the diode

causes the o scillator to maintain a ver y stable operating fre-

quenc y. Because o f the desired stabili ty of a TCXO (±2 ppm),

a better grade of crystal is used to provide better aging char-

acteristics ( ±1 ppm/y ear ). Oscill ators of this type are usually

larger in size (and higher in cost) than the sta ndard 4/14-pin

DIP footprint of standard clock oscillators.

The OCXO provides the highest -accura cy oscillators. T hese

are built by placing a standard oscillator into a tempera-

ture-controlled environment. Rather than have to both heat

and cool the crystal, the operating t emperature is set to the

upper end of the oscillator’s range. Crystals are a lso cut such

that a nearly flat area of temperature r esponse is located at

the operating temperature of the oven. The nor mal operating

temp erature of crystal ovens is in t he 60°C to 100°C range.

Oven-controlled oscillators are g enerally quite large, expen-

sive, and dissipate l arge amounts of power. They also have a

significant warm-up period, requiring from 15 to 30 minutes

after power on to a c hieve their s pecified stability (Refer ence

23).

HOTLink Oscil lator Requirements

Unlike the ANSI requirement for ±100-ppm stability for

end-to-end communication, the HOTLink family of parts will

operate with a substantially wider rang e of reference freque n-

cies between the HOTLink Transmitter and Receiver. The

specification of 0.1% end-to-end frequency tolera nce allows

operation with oscillator sources operating at up to ±500-ppm

tolerance. This allows even the lowest c ost oscillators to be

used with HOTLink.

Bypass Capacitors

At the frequencies that the HOTLink Transmitter and Receiver

operate, the proper usage of power-supply bypassing be-

comes quite critical. Strategically sized and placed capacitors

are used both to provide an AC path between VCC and ground

(VEE), and to source current when the power supply cannot

respond quickly enough due to the parasitics of the power

distributi on system.

The base of any power distributing system is the circuit board.

Due to the very high frequencies developed in a HOT-

Link-based communications link, it is strongly advised to use

full power a nd gr ound planes, rather than attempt ing to dis-

tribute power and ground on the same layers used for signal

distribution. These power layers should be made with a min-

imum of 1-ounce copper.

To properl y bypass the HOTLink Tra nsmitter a nd Receiver it

is necessary to know which VCC pins are assigned to which

portions of the logic inside the part.

HOTLink Transmitter Power Pins

The pin configuration for the HOTLink Transmitter is illustrated

Figure 56

. The transmitter has three pins as signed as VCC

and two assigned as ground. All three of these VCC power

pins are connecte d internally a nd

must

be connected exter-

nally to the same power rail. The curr ent flow from t h e sli ght

voltage variations that would exist if different external VCC

supplies were used could damage the part .

Figure 5 5. Oscil lat or Temperat ure St abili ty

+40

+20

–20

–40

–50 –25 0+25 +50 +75 +100

Temperature (5°C)

HOTLink Design Considerations

Pin 4 of the HOTLink Transmitter is named VCCN or Noisy

VCC. This pin provides power to the ECL emitter-follower out-

put transistors. This pin is not usually a noise source if the

ECL outputs are loaded in a balanced fashion. If these sam e

outputs are operated single-ended with unbalanced loads,

then a varyin g amount of current will flow through this pin as

the outputs switch. To keep board noise to a minimum it is

advised that, if an output is used, both outputs of the d ifferen-

tial driver be loaded the same.

Pin 9 of the t ransmitter is named VCCQ or Quiet VCC. Th is pin

provides power to the CMOS logic core of the part and the

TTL compatible input buffers. This includes the 8B/10B en-

coder and the counters and state machines used to control

the flow of data through the part. Because t he dynamic cur-

rent draw through this pin should not be very large, the prima-

ry bypassing concern should be for higher frequency signal

components present in the internal logic.

Pin 22 of the transmitter is also named VCCQ or Quiet VCC.

This pin is probably the most critical of all the pins on the

transmitter as it provides power to the analog core. This in-

clud es the charge pumps and compa rators used w ith the PL L

clock m ultiplier.

HOTLink Receiver Power Pins

The pin configuration for the HOTLink Re ceiver is illustrated

Figure 57

. The receiver has three pins assigned as VCC

and three assigned as ground. All three of these power pins

are connec ted internally and

must

b e conn ected ex ternally to

the same power rail. The current flow from t h e slight voltage

variations that would exist if different external VCC supplies

were used could dam age the part.

Pin 9 of the HOTLink Receiver is named VCCN or Noisy VCC.

This pin provides power to the TTL-compatible output buf fers.

Because th ere is no way to maintain a constant current load

on these outputs (a s can be done w ith the HOTLink T ransmit-

ter ECL outputs) there will always be significant dyna mic c u r-

rent flow through this pin as the part operates.

Pin 21 of the receiver is named VCCQ or Quiet V CC. This pin

provides p ower to the core CMOS logic i n the receiver. This

include s the 10B/8B decoder and th e c ounters a nd state ma-

chines used to contr ol the flow of data through the part. Be-

cause the dynamic current dr aw through this pin s hould n ot

be very large, the primary bypassing concern should be for

higher frequency signal components present in the internal

logic.

Pin 24 o f the receiver is also named VCCQ or Quiet VCC. This

pin is probably the most crit ical of all the pins on the receiver

as it provides power to the analog core. This includes the

charge pumps and comparators used with the PLL and the

input differential amplifiers for the high-speed serial data

streams.

Bypass Capacitor Types

For the purposes of power supply bypassing, capacitors are

used to store charge, and deliver that charge to a nearby de-

vice when necessary. While many stil l believe t hat ch arge is

store d on the plate s of a capacitor, it is not. Charge i s stored

in the dielectric (Reference 21).

There are two primary types of chip capacitors used for power

supply bypassing; they are identified as either high-K or low-K

capacitors. These capacitor types differ primarily in their di-

electric material.

The K referred to here is the dielectric constant for the mate-

rial used as a dielectric in the capacitor. High-K dielectrics for

bypass-type capacitors are usually based on t itanates of bar-

ium, c alcium, strontium or magnesium. This material provides

dielectric constants in the range of 1200 to 12,000. These

high-K dielectrics allow construction of physically small ca-

pacitors that provide a large amount of capacitance per unit

area. The generally available range of high-K capacitors is

from 200 pF to 0.1 µF. Thes e high-K capacitors hav e temper-

ature characteristi cs of type X7R, Z5U, or Y5V.

Both high- K and low-K diel ectrics are used for power supply

bypassing. High-K dielectrics are us ually not used for temper-

ature-critical or high-frequency operations because of their

thermal and frequency dependent characteristics.

One of the biggest problems with using these high-K dielectric

capacitors is sensitivity to temperature. Per the graphs in

Fig-

ures 58

and

, these typ es of parts can change their capac-

itance values by over 80% over the operating temperature

range of most commercial or industrial applications. (The

Figure 5 6. CY7B923 HOTLink Transmitter

Pin Configur ation

43 12 28 2726

12 13 1514 16 17 18

PLCC

Top View

FOTO

ENN

ENA

VCCQ

CKW

GND

SC/D (Da)

BISTEN

GND

MODE

VCCQ

SVS (Dj)

(Dh) D7

7B923

Figure 5 7. CY7B933 HOTLink Receiver Pin C o nfiguration

SC/D (Qa)

43 12 28 27 26

1213 1514 16 17 18

PLCC

Top View

REFCLK

VCCQ

CKR

VCCQ

GND

RDY

GND

VCCN

RVS (Qj)

(Qh) Q 7

7B933

HOTLink Design Considerations

temperature characteristics for Y5V are similar to Z5U except

that the peak capacitance occurs around 20°C lower in tem-

perature.)

A second problem is that these titanate-based dielectrics ex-

hibit ferroelectric properties; i.e., they do not respond linearly

to an AC signal. The effect is similar to a hysteresis loop in

magnetics. This makes these dielectrics a poor choice when

a distortion-free analog response is required.

When used for high-frequency (RF) or communications-link

type applications, high-K dielectrics have other drawbacks.

Capacitors b ased on these dielectric types are also ve ry sen-

sitive to operating voltag e and frequency.

Figure 60

illustrates the voltage sensitivity of high-K dielec-

trics . Here the capacitance loss can exceed 7 0% with as little

as 25V applied to the part . This parameter may become crit-

ical if capacit ors are used as part of a DC block in a commu-

nications li nk.

Figure 61

illustrates one of th e effects of operating frequency

on capacitance. As the operating frequency increases, the

high-K dielectr ics exhibit less and less capacitance. If these

high-K dielectrics are to be used at an RF frequ ency, a capac -

itance correction factor must be applied to determine t he ac-

tual capacitance present in the circuit (Refere nce 26).

Low-K dielectrics are generally based o n e ithe r titanium-diox-

ide ceramic, alumina, or porcelain. These materials provide

dielectric constants in the range of 9 to 30. Because of the

low-K, these materials are only used for making s mall-valued

capacitors in the range of 1 pF to 10,000 pF. These low-K

capacitors ar e usually identif ied as ha ving NP0 or C0G type

temperature characteristics, and are often referred to as

RF-g rade capa citors because of the ir high-Q and low diss ipa-

tion factors.

Low-K dielectric capacitors are very stable over temperature.

Per

Figure 62

, these parts change in capacitance less than

0.5% over the full military temperature range of –55°C to

125°C. Because of this temperature stability , low-K capacitors

are preferred for many analog applications where fix ed tim e

constants and resonant frequencies are necessary.

Figure 58. Capacitance vs. Temperature for Y5V and Z5U

Dielectrics

Figure 59. Capacit ance vs. Te m perature for X7R

Dielectrics

–40

–80

–60 –40 –20 0 20 40 60 80 100

Temperature in °C

Y5V

Z5U

Temperature in °C140120100806040200–20–40–60

–4

–8

–12

–16

–20

Figure 60. Capacitance vs. DC Volt age

Figure 61. Capacitance vs. Frequency

+10

–10

–20

–30

–40

–50

-60

–70

–80

–90

0 5 10 15 20 25 30 35 40 45 50

Volts DC Applied

NP0

X7R

Z5U

Y5V

–5

–10

–15

–20 1kHz 10kHz 100kHz 1MHz 10MHz100MHz

Frequency

NP0

X7R

Y5V

Z5U

HOTLink Design Considerations

No capacitor provides a

pure

capacitance; i.e., there are other

parasitic resistive and inductive components present in the

comple x impedanc e of a ca pacitor ov er frequen cy as i llustrat-

ed in

Figure 63

(References 15, 1 6, 17, 21). T hese parasitic

components of a capacitor are due to t he materials used in,

and mechanical construction of, the physical capacitor. Be-

cause of these parasitics, a capacitor cannot be treated as

having ever-decreasing impedance with increasing frequen-

cy. At some freque ncy the capac itor passe s through its series

resonant point and must then be treated as an i nductor.

A general rule o f thumb is that as the c apacitance decreases,

the series re sonant frequency increases. This relationship is

illustrated i n

Figure 64

. At t his series r e sonant point, the ca-

pacitive and inductive reactance components cancel each

other out, leaving only the Ef fective Series Resistance (ESR).

For most common bypass capacit ors, the ESR is well under

1Ω. When selecting parts for high-frequency operation, the

smaller case sizes (0805 or 0603) are preferred beca use they

have smaller in ductive parasitics.

Resistors

Figure 65

shows a first order model of a real world resistor.

Because of the pa rasitic L and C present, a resistor does not

have a constant impedance over frequency. The actual

amount of change in impedance from a pure resistance is

based primarily on the construction of, mater ials in, and DC

resistance value of t h e component.

For high frequency or RF designs, most low-value (<1 kΩ)

composite (non wire-wound) resistors may be assumed to

operate at or near their DC resistance. As the DC r esist ance

of the part increases, its impedance at higher frequencies

decreases.

Fi gur e 66

shows this relationship for typical car-

bon fi lm resistors. This change in impeda nce is refe rred to as

the Boella Effect and is caused by the distributed shunt ca-

pacitance present in the conducting carbon par ticles (Refer-

ence 21).

This shows that low-value carbon film resistors have reason-

able impedance characteristics for RF applications, but for

higher values a different type of re sistor must be used.

For higher resistance values at RF frequencies, metal film

resistors should be used. Because these types of resistors

are not formed from particulate material, the distributed ca-

pacitance is reduced. These types of resistors are manufac-

tured by vacuum sputtering of thin films of mixed metals onto

Figure 62. Capacitance vs. Temperature for NP0/C0G

Dielectrics

Figure 63. Capacitor Equivalent Model

Temp eratu re in °C

Tolerance

–55 –40 –20 0 20 40 60 80 100 125

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

Figure 64. Capacitor Impedan ce vs. Frequency

Figure 65. Fir st Order Resistor Model

Figure 66. Carbon Film Resistor

Frequency Characteristics

101

10–1

10–3

10–4

10–5 100 µF10 µF

10 0 pF

11010

21031041051061071081091010

Fr equency (Hz)

Z (oh m s)

10–2

Frequency (MHz) 400100

1.0

0.1

0.01

100

300Ω

1 kΩ

3.3 kΩ

10 kΩ

33 kΩ

100 kΩ

330 kΩ

1 MΩ

HOTLink Design Considerations

a ceramic substrate. Because there are no individual particles

of metal, the capacitance is much lower.

Care must also be used when selecting metal film resistors

as some of these have significant induc tive parasitics. These

inductive parasitic s are often caused by the method of laser

trim used to adjust the value of the resistor. Those resistors

created using two straight cuts, one from either side, are gen-

erally more inductive than those trimmed using a single

straight or L shaped cut.

Metal film resistors shou ld b e used for resistors in the analog

data path. This includes the transmission line termination and

line bias resistors at both the source and destination ends of

the serial link.

Fiber-Optic Emi tters (Driver s)

A fiber-optic emitter is an electro-optical conve rter that c hang-

es an el ectrical stimulus into light. A simplified block diagram

of a fiber-optic emitter is shown in

Figure 67

. The input buffer

is an ECL differential line receiver. While some emitters do

provide a VBB output to allow single-ended operation, its use

is strongly discouraged. The ECL receiver controls a

high -current amplifier . The amplifier drives its current through

an LED or s emiconductor laser to generate a shaped optical

output in response to the ECL signal i nput. A micro-lens as-

sembly (usually a small sphere of glass) is used to co uple and

direct the light int o a port for an optical fiber. B ecause of the

small core size of the optical fiber , the lens and fiber recepta-

cle are aligned by the fiber-optic emitter manufacturer (Refer-

ence 27).

Fiber-optic emitters are available in may different case styles,

wavelengths, launch m odes, data rates, etc. When selecti ng

an emitter, the main concerns are

• Optical Re ceiver characteristi cs

• O p er a ting da ta rate

• Cable plant characteristics

Most of these areas deal with interoperability of data commu-

nica tions links. If a shortwave laser is used as an emitter, the

optical receive r must be designe d to operate w ith the specific

data rates and spectral properties of that shortwave laser.

While it would be nice i f a more m ix-and-match combinati on

of LED, shortwave laser, and longwave laser emitter s could

be used, existing receivers do not allow this. If a 1300-nm

LED-driver is use d, an optical receiver designed for 1300-nm

LED reception must be u sed to properly d etect the signals. In

addition the optical receiver must be designed to support the

data rate used in the link.

Opti cal emitter assemblie s are available from multiple sourc-

es, including AMP/Lytel, Siemens Optical, Hewlett-Packard,

Sumitomo Electr ic, AT&T, and other s.

ANSI Fibre Channel Requirements

The current ANSI Fibre Channel standar d calls out four opti-

cal interface technology options for use at the 25-MByte/sec -

ond data rate supported by HOTLink. The ANSI designators

for these technology options are (Reference 3)

• 25–SM–LL–L

• 25–SM–LL–I

• 25–M5–SL–I

• 25–M6–LE–I

These designators are interpreted as four fields. The first field

identifies the data r ate used (25 MBytes/second).

The second field ident ifies the media used. SM specif ies sin-

gle-mode fiber , M5 spec ifie s 50-µm core multimode fiber , and

M6 specifie s 62.5-µm core multimo de fiber.

The third field identifies the transmitter type. LL specifies a

1300-nm longwave laser, SL specifies a 780-nm shortwave

laser, a nd LE specifies a 1300-nm LED-driver.

The last field identifies the distance class of the link. L speci-

fies long distance (2m–10 km), and I specifies intermediate

distance ( 2m–1.5 km).

HOTLink will correctly operate with all these different link

types. However, it is up to the user t o select th e proper com-

bination of emitt er and detector for each class.

For those users intending to implement laser-based optical

links, there are a number of federal and i nternati onal safety

certifications required before any such link can be put into

public use. These safety requirements (ANSI Z136.1 and

Z136.2, F.D.A. regulation 21 CFR s ubcha pter J, and IEC 82 5)

are called out in the ANSI Fibre Channel s tandard (Referenc-

es 9, 10, 11, 12, 13). No such certification r equirements are

necessary for LED based links.

Power Distribution Requirements for Optical Drivers

The LED or laser used to drive the optical link is probably the

larges t noise ge nerating item in an opt ical link. When the op-

tical driver is turned on (sending 1s), currents of 50 mA to 100

mA are forced through the LED or laser. While current steer-

ing is often used to minimi ze dynamic current requir ement s,

significant high-frequency noise is still generated. M ost opti-

cal modules attempt to remedy part of this situation by pro-

viding multiple VCC and VEE pin s on their package and inc lud -

ing some power s upply b ypass ca pacitance inside the optical

module. This does take care of some of the p roblem, but does

not correct all of it .

While bypass capacitors are still necessary to provide dy-

namic current, additional power isolation and filtering is re-

quired to separate the high noise of the optical transmitter

from the highly sensit ive optical receiver, and from the serial-

izer/deserializer operations of the HOTLink Transmitter and

Receiver . V endor’s recommend ations for this include a 10-µF

solid Tantalum capacitor l ocated near the optical transmitter,

and a 0.1-µF decoupling capaci tor directly connected to the

optical tra nsmi tter VCC pins (Reference 27).

Isolation is provided by se parating the VCC or power plane for

the transmitter from the rest of the surr ounding power plane,

through an indu ctive path. This i s do ne by placing a gap in the

Figure 67. Fiber -Opt ic Emitter Module Block Diagram

Differential

ECL Input

ECL Amp

LED or

Laser Driver

Light-Emitting Diode or

Semiconductor Laser

SC or ST Fiber

Connector

Light Coupling

Optics

HOTLink Design Considerations

VCC plane around most of the transmitter VCC pins with a

single limited connecting point. If the transmitter packag e only

has one or two VCC pins, these may be treated individually by

bringing in power through a small inductor or surface trace.

For a low-noise environment this inductor may be constructed

as part of th e circuit board using a 15-mil-wide trace approx-

imately 10 mm in length (approximately 5 nH) . The specified

by passing sh ould occur after this inductive trace, right next to

the optical transmitter . The net result is to implement a π-filter

using the circuit board and capacitors for the different filter

elements. This is il lustrated schematically in

Figure 68

An example slotted power plane used to implement the induc-

tive element in the π-filter is shown in

Figure 69

. This illustra-

tion details an actual power plane layout for an optical module.

The bla ck ar eas indicate the absence of copper. The slot in

the center of the figure is used to separate the power for the

optical transmitter from the optical receiver. The s haded line

on the right h and side indicat es a surface layer trace (induc-

tor) used to separate power for the optical module from the

remainder of t h e design.

Fiber-Optic Detectors (R eceivers)

A fiber-optic detec tor is an opto-electric conve rter that chang-

es a light stimulus into an electrical signal. A simplifie d block

diagram of a fiber-optic detector is illustrated in

Figure 70

Ligh t enters the module through an optical fiber and is guided

by the connector housing. A coupling lens focuses all avail-

able opti cal en ergy onto th e activ e region of a light sensitive

diod e. The presence or absen ce of light affects the amount of

current flow through the diode . This small current flow is then

amplified by a transimpedance amplifier which then feeds an

ECL differential driver. Many f iber-optic detectors also contain

additio nal circuitry such as signal-detect (Referenc e 27).

Fiber-optic receivers are generally available from the same

vendors as fiber-optic emitters. As with fiber-optic emitters,

the optical receive r must match the c haracteristics of the light

dri ven into th e optical fiber.

Unlike the optical emit ter where there are multiple technolo-

gies used for l ight generation, all opti cal receivers are based

on the response of a PIN (positive-intrinsic-negative) photo

diode. These photodiodes are based on eit h er silicon or gal-

lium arsinide technology. The outpu t of the PIN photodiode is

a small (<1 µA) change in current in response to received

light. A fiber-optic detector module feeds the output of this PIN

photodiode into a transimpedance amplifier. The function of

this am plifi er is to convert this small change in current into a

large change (E C L 100K-level) in voltage.

For many optical receivers, it is possible to operate them

above their stated maximum data rate. What is given up is

re ceiver se nsitivit y; i.e., many 200-Mbit/second o ptical m od-

ules will operate at the ANSI Fibre Channel data

266-Mbit/second dat a rate, but wit h a 3-dB or greater loss of

sensitivity. This loss may be converted direct ly into a shorter

usable distance on the fiber-optic media.

Because the optical receiver has ECL outputs, care should be

taken to maintain a balanced load on any differential outputs

to minimize current transients. While some optical receiver

outputs (i.e., signal-detect on endfire modules) may be sin-

gle-ended, they usually do not change very often and should

not affect data integrity when they do.

Power Distribution Requirements for Opti cal Receivers

The power filtering of the optical receiver is quite critical as

the transimpedance amplifier must responding to very low

current variations. This filtering problem is usually compound-

ed by the placement of the high-noise generating optical

transmitt er, directly adjacent to the optical re ceiver.

Depending on the type of receiver, it may be implemented

with one or many VCC p ins . For those made with a single VCC

connection, this pin should be isolated through a π-network

or other network that implements an inductive leg to block RF

on the power lead.

For those optical receiver mod ules that use multiple VCC pins,

these pins are usually kept separate internal to the module,

and feed different sections of the logic. For those VCC pins

that supply power to the ECL output emitter-followers and the

ECL differential amplifiers, all that is necessary is a good

0.1-µF d ecoupling capacitor next to the VCC power pins. An

Figure 68. Optical Module Power π-Filter

Figure 69. Fiber-Optic Module Sl otted Power Plane

Board

Power In

Slotted Power

Plane Inductor Optical

Module

Power

Bul k an d

High-

Frequency

Bypass

Capacitors

Bulk and

High-

Frequency

Bypass

Capacitors

XMTR

RCVR

Figure 70. Fiber -Opt ic Detector Module Block Diagram

Differential

ECL Output

ECL Amp

Transimpedance

Amplifier SC or ST Fiber

Connector

Light Coupling

Optics

PIN Photodetector

HOTLink Design Considerations

inductive-based filter is recommended for the VCC pin that

provides p ower to bias the PI N photodiode and th e transim-

pedance amplifier to limit the external noise input from the

system supply.

Just as with the tra nsmi tter this inductiv e filter can b e i mple-

mented either as a notched or slotted power plane, or by us-

ing a surf a ce trace to act as an induct or. When implemented

in this fash ion th e capacitor plac ed at the op tical receiver end

of t he inductor should be 0.1 µF.

Optical Modules

Thanks to the effor ts of a group of optical component manu-

facturers (AMP/Lytel, Siemens Optical, Hewlett-Packard, and

Sumitomo Electric), a

de facto

standard footprint has been

developed for optical modules. While originally developed f or

the FDDI market, optical modules with speeds suitable for

Fibre Channel and ATM are also available. This footprint

specifies the mechanical dimensions and signal names of two

dif ferent package styles, yet allows a common board layout to

accept both. The dimensions and pin num bering of this fo ot-

print are illustrated in

Figure 71

The two module t ypes supported b y this footprint are call ed

DIP and endfire. The DIP modules utilize pins 1–32, while the

endfire modules only use pins 33–41 (for signals) and pins 1

and 32 for package mounting. These two mounti ng pins are

also larger in diameter than the other pins on the package.

These optical modules (DIP and endfire) share several sig-

nals. For compatibility with both module types, only the small-

er set of signals present on the endfire module type should

be used. A complete listing of the signals present in the stan-

dard footprint is found in

Table 5

. The signals present on the

optical module are

• SD – Signal Detect

• TD – Tr ansmit Data

• RD – Receive Data

• Case – Outer Case of Module

•V

CC – Positive Supply Voltage

•V

EE – Negative Supply Vol tage

•V

BB – ECL Base Threshold Volta ge

The VBB a nd SD– signals are only present on th e DIP foot-

pr int package and thus should not be used in designs that

wish to suppor t interchangeable module types.

Care must be used when connecting to the pin s marked as

Case. These pins are not specified as being isolated, t ied to

VEE, or tied to VCC. As s uch, each manufacturer is allowed to

connect them as they wish.

Isolated Case pins may be connected either to VCC or VEE.

Usually this connection is made to whichever power rail is

identified as ground in the system. When used with the HOT-

Link T ransmitter , these types of modules are us ually operated

in PECL mode wit h the Case pins connected to VEE.

When the case i s connected to the VCC pins, the part is de-

signed for operation in a stand ard ECL (negative-referenced)

system. Modules of this type may still be used with HOTLink,

but some care must be taken in how they are interfaced.

Figure 71. Standard Optical Module Footprint

Table 5. Standard Optical Module Pinout

DIP Pin Assignments

Pin Signal Pin Signal

1 C ase 2 No Pin

3Case4V

EE 6 +SD

7 –SD 8 Case

9Case10RD

11 +RD 12 VCC

13 VCC 14 VCC

15 Case 16 Case

17 Case 18 Case

19 VCC 20 VCC

21 Case 22 +TD

23 –TD 24 Case

25 Case 26 VBB

27 Case 28 Case

29 VEE 30 VEE

31 No Pin 32 Case

Endfire Pin Assig nme nts

Pin Signal Pin Signal

33 VEE 34 +RD

35 –RD 36 +SD

37 VCC 38 VCC

39 –TD 40 +TD

41 VEE

HOTLink Design Considerations

Pulse Transformers

A pu lse transformer is a magnetic device used to couple elec-

trical energy from one stage to another with minimal distor-

tion. This coupling occurs through magnetic induction. How

well this couplin g o ccurs is based on the construct ion of t he

transformer and the materials used for the core an d windings.

Core Materials

There are thre e basic types of core materi als used for trans-

formers: metal, powdered iron, and ferrites. Metal cores con-

sis t of p ieces o f low conduc tivity metal having some magnetic

prope rties; usually soft iron or steel. This metal core is usually

made from multiple strips or laminations of material to limit

eddy currents in the core. Metal cores have a practical upper

f re quency limi t of about 50 kHz.

Powdered iron cores use metal powder fused together by an

insu lating binder . Because o f the smaller size of the magnetic

particles, the upper frequency for powdered iron cores ex-

tends to near 1 MHz.

Ferrites are a magnetic form of ceramic. Depending on the

type of ferrite and construction of the core, transformer s with

ferrite-based cores are available with operating frequencies

of near 1 GHz. This is the core material that must be used for

transformers used with HOTLink.

ANSI Fibre Channel Specifications

The current ANSI Fibre Chann el standa rd, section 7.1, states

that the recommended interface to all types of copper media

is via transformer coupling. The primary benefits of transform-

er coupling are ground isolation, common-mode rejection,

and the ability to drive both bala nced and u nbalanced trans-

mission lines with th e same interface (Reference 3).

Just as with optical interfaces, the ANSI standard calls out

multiple copper technology options for use at the

25-MByte/second data rate supported by HOTLink. The ANSI

designators for these technol ogy options are

• 25–TV–EL–S

• 25–MI–EL–S

• 25–TP–EL–S

These designators are interpreted as four fields. The first field

identifies the data rate used (25-MBytes/second).

The second field ide ntifies the media used. TV specifies 75Ω

video grade coaxial cable, MI specifies a 75Ω miniature co-

axial cable, and TP specifies shielded twisted-pair.

The third field identifies the transmitter type. The EL identifier

is used for all electrical classes.

The last f ield identifie s the distance class of the l ink. S spec-

ifies short dist ances (<75m).

While these are the only electrical class es that ANSI supports

for Fibre Channel, many other impedances an d distanc es w ill

function with the HOTLink Transmit ter and Receiver.

The typical transformer electrical characteristics to support

thes e interface combinations are called out in the ANSI Fibre

Channel standard in Section 7.1, Table 10 (Reference 3).

Pulse transformers suitable for coupling HOTLink to copper

based cables are available from Pulse Engineering, Mini-Cir-

cuits, Premier Magnetics Inc., Valor, and others.

Fiber -Optic Cables

Opti cal media generally falls into tw o cat egorie s: multimode

and single-mode. The usage of each type is dictated by the

spectral ch aracterist ics and l aunch mode of the light into the

fiber.

Single-Mode Fiber

Single-mode fiber is most often used with optical drivers that

are both spectrally pure (i.e., a laser) and coherent in their

output (well collimated, longwave laser). Fibers of this type

have a very small core section to limit the modes of propag a-

tion of the transmitted light, and an index of refraction de-

signed to only allow light to remain in the core that strikes the

cladding at a very low critical angle. Its main propagatio n of

light is by refraction (bending) of light that travels down the

center of the core. I n addition, a smal l number of tight turns

of the fib er are usually pla ced near the optical tra nsmitter to

act as a filter for any of the h igher-order modes of propagation

that may be launched into the fiber. These turns change the

incidence angle of the higher-order modes between the core

and the cladding of th e fi ber, causing light at these modes to

leave the core. A diagram of a single-mode fib er is shown in

Figure 72

(Reference 18).

Single-mode fibers are available in different core diameters

for use with different optical sources. The fiber type called out

for single-mode propag ation in the ANSI Fibre Channel stan-

dard is 125-µm fiber diameter with a 9- µm core. With this core

diameter, the fiber is limited to use with 1300-nm sources

(Reference 3).

Multimode Fi ber

Multimode fiber is usually used with optical drivers that are

not sp ec trally pure (i.e., LED) or not c ohe rent in their outp ut

(i.e., shortwave lasers). The lensing system used to couple

the optical driver’s light output to the fiber is not designed for

collimation, but to couple the maximum amount o f light. This

type of fiber allows propagation of light both by refraction and

by reflection.

Two distinct classes of multimode fiber are in use today:

step-index and graded-index. In a step-index fiber, the prima-

ry mode of light propagation is through total internal reflec-

tion. Light that enters the core on one end is continuously

reflected at the c ore/cladding interfa ce until it exits th e cable

at th e other end. A diagr am of multi mode step-index fib er is

shown in

Figure 73

Figure 72. Single-Mode Fib er Propagation

Cladding

Core

Light

Source

S ingle-Mode Fiber

HOTLink Design Considerations

In a graded-index fiber, light is propagated through refraction

rather than reflection. The fiber core is constructed of multiple

concentric layers of glass. Th e index of re fraction in each lay-

er is slightly different, getting lower as you move out from the

center of the core. Because light travels faster in a lower index

of refraction, the higher-order modes of propag ation that trav-

el the farthest arrive in phase wit h the low- order modes that

remain near the center of the core. A diagram of a multimode

grade d-index fiber is shown in

Figure 74

(Reference 1 8).

The step-index form of multim ode fiber is n ot n or mally used

for data communications because its propagation character-

istics limit the usable distance of a link. The ANSI Fibre Chan-

nel standard currently onl y supports graded-index fibers with

core diameters of 50 µm or 62.5 µm, both with a cladding

diameter of 125 µm (Reference 3).

Optical Pulse Dispersion

In a step-index fiber , light that t ravels straight through the core

covers a shorter distance and arrives at the end of the fiber

before light t hat r ep eatedly bounces off the core/cladding in-

terface. This difference in delay through the fiber causes a

narrow pulse launched into the fiber to widen as it travels

down the fiber. Because this pulse widening or dispersion is

c aused by the different modes of propagation, this phenome-

na is known as modal dispersion.

When used with an LED driver, an additional source of dis-

persion comes into play. Unlike free space where all wave-

lengths of light propagate at the same rate, an optical fiber

propagates different wavelengths at different rates. This caus-

es any l ight pulse that is no t spectrally pure (i.e., all the same

wavelength) to widen as it travels down the f iber. Pulse wid-

ening caused b y wavelength is called chromatic dispersion.

With multimode fiber one of the main limits to usable distance

is the pulse spreading caused by light dispersion within the

fiber . As the transmitted 1s (pulses of light) get wider through

dispersion, they interact with adjacent transmitted 0s (ab-

sence of light). The ef fect of dispersion is illustrated in

Figure

(Refere nce 18).

With single-mode fiber , dispersion is usually not a limiting fac-

tor. Here the amount of attenuation over distance is the main

limiting factor.

ANSI Fibre Channel Optical Fibre Requirem ents

Fiber-optic cables are available with many different optical

and mechanical characteristics. International organizations

have set standards for optical cable plants to al low manufac-

tures to sta ndardize on some cable t ypes.

The standards body that created the standards used for opti-

cal cable plants is called EIA/TIA (Electronic Industry Associ-

ation/Telecommunications Industry Association). The gov-

erning document for all optical fiber types is EIA/TIA

492BAAA. This includes single-mode and both core diame-

ters of multimode fiber.

The ANSI Fibre Channel sta ndard has also selected a com-

mon fiber-optic connector type f or use wi th all types of o ptica l

fiber media. This connector type was developed by NTT in

Japan and is known as an SC-type optical fi ber c o nnector. A

diagram of a simplex SC connector is shown in

Figure 76

These simplex connectors may be joined together using a

plastic clip to form a du plex connector. In the duplex configu-

ration the center-line spacing of the optical fibers is 0.5 inch.

Simplex and duplex cable assemblies are available from AMP,

FOCS Inc., Alcoa Fujikura Ltd., Belden, and many others.

Copper Cables

There are three primary types of copper media available for

distance data tran smis sion: shielded twisted-pair (STP), twi-

naxial cable, and coaxial cable. Each of these cable types has

specific advantages and characteristics.

Figure 73. Multimode Step-Index Fiber Propagation

Figure 74. Multimode Graded-Index Fiber Propagation

Light

Source

Cladding

Core

Multimode Step-Index Fiber

Light

Source

Cladding

Core

Multimode Graded-Index Fiber

Figure 75. Pul se Dispersion

Single-Mode Fiber

Multimode Graded-Index Fiber

Multimode Step-Index Fiber

nput

Signal

utput

Signal

HOTLink Design Considerations

Shielded Tw isted Pair

Shielded twisted-pair (STP) cables are used for many

low-cost LAN ins tallations. One of the most common o f thes e

is the IBM Type-1 and Type-6 cables used for IEEE 802.5

token ring networks. For use with the ANSI Fibre Channel, the

standard calls out Type-1 and Type-2 150Ω STP cables as

defined in EIA/TI A 568 (References 3, 11, 20).

STP cables are constructed of two insulated conductors twist-

ed together at a specific number of twists per foot, with an

overall sh ield and jacket. They a re available w ith characteris-

tic impedances of from 78Ω to 20 0Ω. With this type of cable

the transmission remains fully differential from source to des-

tination. The shield is only used to preve nt radiation and con-

trol susceptibility . Cables of this type are effective for long dis-

tances at low data rates, and short distances for high data

rates. T he main limit ing factor for c able s of t his type is t heir

attenuation at high f requencies . In many cases , cables of this

type are so poor above 50 MHz that attenuation is not even

specified at these f requenc ies. In some ve ndors’ data, shield-

ed twisted-pair c ables ar e also referr ed to as twinax (Refer -

ence 20).

Twin axial Cable

Twinaxial c able is a shielded form of t win-l ead. Twinaxial ca-

bles consist of two par allel insulated conductors, maint ain ed

at a fixed spacing with an ov er all shield. Cables of this con-

struction are often used for television re ception lead-in cable.

As w ith STP cables, twinax ial cables maintain a fully dif feren-

tial transmission system f rom t ransmitter to receiver. Twinax-

ial cables can have lower attenuation of high frequency sig-

nals than STP cables and c an be used for longer distances.

Unshielded twin-lead, while ha ving excelle nt high-fre quency

characteristics, is not generally usable for data communica-

tions due to the radiated emissions of the cable, and the im-

pedance changes that occur as the unshielded cable is rout-

ed near metallic objects.

Twinax cables are available in impedances from 125Ω to

300Ω and velociti es of 70% to 80% (Reference 20).

Coaxial Cable

Coaxial cable is used for the longest distances. They consist

of a single center conductor surrounded by a dielectric spac-

er, surrounded by a concentric shield. Unlike either STP or

twinax, coaxial cables are an unbalanced transmission line;

i.e., the signal is transmitted and received as a signal relative

to a ground or shield, rather than a signal relative to another

signal.

In a coaxial cable the outer conductor a cts both as part of the

transmission lin e t o propagate the signal, and as a shield to

prevent radiation of the t ransmitted signal and susceptibility

from out side signals.

Coaxial cables are available in impedances from 50Ω to 125Ω

and velocities of 66% to 90% . The main element that affects

the velocity of propagation is the dielectric type used between

the center conductor and the shield. Solid polyethylene is a

common dielectric at the 66% velocity. The fastest speeds

usua lly res ort t o foamed Teflon o r partial air core.

Table 6

lists

some common coaxial cable types and characteristics (Ref-

erence 20).

One thing that cannot be seen from this t able are the cable’s

attenuation characteristics versus frequency. This is one of

the characterist ics that determines just how far a usable sig-

nal can be sent. The cables listed in

Table 6

are plotted for

atten uation in

Figure 77

ANSI Fibre Channel Copper Cable Requirements

The ANSI cable plant requires copper cables with specific

operating characteristics. These characteristics are called out

in Section 9 and Annex F of th e Fibre Channel PC-PH stan-

dard (Reference 3).

Realizing these req ui rements means that the cable must be

made with specific construction. For coaxial cable s the VP of

70% to 82% requires a foam dielectric.

The minimum necessary shield coverage for braid is 95%.

This is necessary because of th e high frequencies carried by

the cables. With shield coverage lower than this, the signal

leakage through the braid can allow not only significant signa l

radiation, but an impedance mismatch due to signa l propaga -

tion down the outer surface of the braid. For best effective-

ness, a 100% foil shield should be used in addition to the braid

shield.

To meet flammability requirements, the National Electrical

Code now req uires that almost all installations use eithe r CL2

or CL2P (plenum rated) jacket mat erial (Reference 25).

Cables meeting all of these requirements are available fro m

multiple vendors.

The ANSI standard also al lows use of shielded twiste d pa ir or

twinaxial type cables. These cables all require a shield to

meet EMI/EM C requirements. Unshielded twisted p air (use d

for many networks) should not be used. This is primar ily due

to radiated emissions rather than susceptibilit y.

Figure 76. SC Simplex Fiber-Optic Connector

Table 6. Common Coaxial Cable Types

RG/U Ty pe Belden

Type ZONominal

O.D. VP

RG58A/U 8259 50 .193″66%

RG179B/U 83264 75 .1″70%

RG6/U 1223A 75 .290″83%

RG59/U 9259 75 .242″78%

RG11/U 87292 75 .348″82%

RG62A/U 9268 93 .242″84%

RG63 9857 125 .405″84%

HOTLink Design Considerations

Copper Cable Connectors

There are three primary connector types called out for use

with c opper cables: BNC and TNC for coaxial cables (illustrat-

ed in

Figure 78

) and a 9-pin D-sub (illustrated in

Figure 7 9

)

for twi ste d-p air/ twinax cables.

For coaxial cables, the BNC connectors are used on the

transmitting end of the cable while the TNC connectors are

used on the receiver end of the cable. This dual connector

configuration allows a duplex cable to be connected without

having to identify one cable from the other. With these con-

nectors the male end is always on the cable while the female

end is used at th e board bulkhead.

For twisted-pair or twinaxial type cables a 9-pin D-sub con-

nector is used. This connector is required to have a metal

shell because the shields of both the transmit and receive

pairs are terminat ed to the shell of the connector . As with the

coaxial connectors the cable gets the male connector while

the board or bulkhead gets the female connector.

The STP cable is wired in a crossover fashion where the

transmit pins at one end of the cabl e (as illustrat ed in

Figure

) are connected to the receive pins at the other end of the

cable. The cable shields for both p airs are tied together a nd

connected to the D-sub connector shell at each end.

Figure 77. Coaxial Cable Attenuation Characteristics

0.1

1.0

10.0

1 10 100 1000

Sinusoidal Frequency (MHz)

RG11/U RG63

RG62A/U

RG58A/U

RG6/U

RG179B/U

RG59/U

Attenuation (dB/100 feet)

Figure 78. /BNC Cable Connectors

Figure 79. STP Cable C onnector and Connector Pinout

Threaded

Neil-Councilman

Connector (TNC)

Bayonet

Neil-Councilman

Connector (BNC)

HOTLink Design Considerations

Bec ause of the low cu rrent used in these cables, the connec-

tions are considered to be dry circuits. To prevent contact ox-

idation fro m degrading the link over tim e the conta cts are re-

quired to be gold or palladium plated (Reference 28).

Conclusion

The HOTLink family of communications products provide de-

signers with a simple yet elegant method of reliably moving

large quantities of data a t very high speeds f rom on e place t o

another . The se parts a re capa ble of communicating over cop-

per or optical media at distances well in excess of industry

standards. Their BiCMOS implementation, along with their

integrated powe r savin g features, combine to offer one of the

lowest-power, high-speed serial communications link stan-

dards available.

HOTL ink is a tradema r k of Cypress Sem icon du ctor.

IBM is a re gi stere d tra dema rk of In te rnatio na l Business M achi nes Corp oration.

ESCON is a trade mark o f In terna tio nal Busin e ss Mach ines s Corp orati on .

Figure 80. STP Cable Connections

+XMIT 1

–XMIT 6

+RCVR 5

–RCVR 9

SHELL

1 +XMIT

6 –XMIT

5 +RCV

9 –RCV

SHELL

Cable Shield

HOTLink Design Considerations

of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze

its products for use as critical components in life-support sy stems where a malfunc tion or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

References

1. A. X. Widmer and P. A. Fran azek,

A DC-Balanced, Parti-

tioned-Block, 8B/10B T ransmission Code

, IBM J ournal of

Research a nd Development, 27, No. 5: 440-451, Sep tem-

ber 1983

2. U.S. Patent 4,486,739, Peter A. Franaszek and Albert X

Widmer,

Byte Oriented DC Balanced (0,4) 8B/10B Parti-

tioned Block Transmission Code

, December 4, 1984

Fibre Channel Physical Standard, ANS X3.230-1994

American National Standards Institute, 1994

Enterpri se Syst em Architecture/390 ESCON I/O

SA22-7 202, IBM Corporation, 1990

F100K ECL Logic Databook and Design Guide

, National

Semiconductor, 1990

6. Lawren ce B. Levit and Marco L. Vincelli,

Characterize

High-spee d Digital Circuits: A Job For Wideband Scopes

Lecr oy C orp., EDN June 10, 1993

The ABC’s of Probes

, Tektr onix Pub 60W-6053-3

Product Overview

, Cascade Microtech, Product Over -

view, 1992

Safe Use of Lasers ANS Z136.1-1993

, American National

Standard s Institute, 1993

10.

Laser Safety in Optical Communication Systems ANS

Z136.2

, Americ an National St a ndards Instit ute

11.

Commercial Building Telecommunications Wiring St an-

dard EIA/TIA-568

, Electronics I n dustries Associa-

tion/Telecommunications Industries Associat ion

12.F.D.A. Regulation 21, Code of Federal Regulations

13.

IEC825

, International Electrotechnical Committee

14.Scott, Paul, Cypress Semiconductor,

Draft Paper - HOT-

Link On Wire

, May 1992

15.

1990-91 Resistor/C apacitor Data Book

, Philips Compo-

nents, 1990

16.

System Design Considerations When Using Cypress

CMOS Circuits

, Cypr ess Semiconductor Applic ations

Handbook, 1993

17.W hite, D onal d R.J.,

Elect rical Filters, Synthesis, Design

and Applications

, Second Edition, 198 0

18.Sterling, Donald J.Jr .,

T echnician’s Guide T o Fiber Optics

Second Edi tion, 1 9 93

19.Blood Jr., William R.,

MECL System Design HandBook,

Fourth Editio n, 1988

20.

Belden Wire and Cable

, Cooper Industri es, 1990

21.Botos, Bo b, Hewlett Packard,

Designers Guide to RCL

Measurements

, June 1979

22.

Hewlett-P ackard Test and Measurement Catalog

Hewlett-Packard Corp., 1992

23.

Crystal Oscillator Handbook a nd Catalog,

Vectron Labo-

ratories, Inc., 1992

24.Ramierez, Robert W.,

The FFT, Fundamentals and Con-

cepts

, Tektronix, Inc. 1985

25.

National Electrica l Code

, National Fire Protec tion Associ-

ation

26.

1990-91 Resistor/C apacitor Data Book

, Philips Compo-

nents, 1990

27.

Application Note 65074, Fiber-Opt ic Transmitter and Re-

ceiver

, AMP I ncorporate d, 1992

28.J. H. Whitl ey, AMP Inc.,

Co nta cts a n d Dry Circuits

, AMP

Symposium paper, October 1963