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General Description
The MAX5165 contains four 1-to-8 multiplexers and 32
sample/hold amplifiers. A single analog input connects
to all four internal 1-to-8 multiplexers. The sample/hold
amplifiers are organized into four octal sample/holds
with independent TTL/CMOS-compatible track/hold
enables for each octal set. Additional 3-bit TTL/CMOS-
compatible address logic selects the 1-to-8 multiplexer
channel. Clamping diodes on each output allow clamp-
ing between two external reference voltages. The
MAX5165 is available with an output impedance of
50Ω, 500Ω, or 1kΩ, allowing output filtering.
The MAX5165 operates with +10V and -5V supplies and
a separate +5V digital logic supply. Manufactured with
a proprietary BiCMOS process, it provides high accura-
cy, fast acquisition time, low droop rate, and a low hold
step. The device acquires 8V step input signals to
0.01% accuracy in 2.5µs. Transitions from sample
mode to hold mode result in only a 0.5mV error. While
in hold mode, the output voltage slowly droops at a rate
of 1mV/sec. The MAX5165 is available in a 48-pin TQFP
package.
Applications
Automatic Test Equipment (ATE)
Industrial Process Controls
Arbitrary Function Generators
Avionics Equipment
Features
♦32-Channel Sample/Hold
♦Output Clamping
♦0.01% Accuracy of Acquired Signal
♦0.01% Linearity Error
♦Fast Acquisition Time: 2.5µs
♦Low Droop Rate: 1mV/sec
♦Low Hold Step: 0.25mV
♦Wide Output Voltage Range: +7V to -4V
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
________________________________________________________________ Maxim Integrated Products 1
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
VDD
OUT15
OUT14
OUT13
OUT12
OUT11
A2
M0
M1
M2
M3
VL
DGND
VSS
AGND
IN
CH
CL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
A1
A0
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
TQFP
MAX5165
19-1469; Rev 0; 7/99
PART
MAX5165LCCM
MAX5165MCCM
MAX5165NCCM 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-
PACKAGE
48 TQFP
48 TQFP
48 TQFP
Pin Configuration
Ordering Information
ROUT
(Ω)
50
500
1k
MAX5165LECM
MAX5165MECM
MAX5165NECM -40°C to +85°C
-40°C to +85°C
-40°C to +85°C 48 TQFP
48 TQFP
48 TQFP
50
500
1k
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +10V, VSS = -5V, VL = +5V ±5%, AGND = DGND, RL= 5kΩ, CL= 50pF, TA= TMIN to TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND.......................................................-0.3V to +11.0V
VSS to AGND .........................................................-6.0V to +0.3V
VDD to VSS ......................................................................+15.75V
VL to DGND...........................................................-0.3V to +6.0V
VL to AGND ...........................................................-0.3V to +6.0V
DGND to AGND.....................................................-0.3V to +2.0V
IN to AGND.................................................................VSS to VDD
A_, M_ to DGND ....................................................-0.3V to +6.0V
CH, CL to AGND .................................................-6.0V to +11.0V
Maximum Current into Output Pin ....................................±10mA
Maximum Current into A_, M_ ..........................................±20mA
Continuous Power Dissipation (TA= +70°C)
48-pin TQFP (derate 12.5mW/°C above +70°C).........1000mW
Operating Temperature Ranges
MAX5165_CCM ...................................................0°C to +70°C
MAX5165_ECM.................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Maximum Current into CH, CL, PIN..................................±80mA
Figure 2 (Note 1)
Figure 2 (Note 1)
Figure 2 (Note 1)
IN = AGND
To ±1mV of final value, Figure 2 (Note 1)
-4V < VIN < +7V, RL= ∞
TA= +25°C, 100mV step to ±1mV, RL= ∞,
Figure 2 (Note 2)
8V step to 0.08%, RL= ∞, Figure 2 (Note 2)
IN = AGND, TA= +25°C
IN = AGND, TA= +25°C
+15°C ≤TA≤+65°C (Note 1)
RL= ∞, CL= 250pF
CONDITIONS
ns150tDH
Data Hold Time
ns200tPW
Inhibit Pulse Width
ns200tAP
Aperture Delay
µs12tH
Hold-Mode Settling Time
µs
1
tAQ
2.5 4
Acquisition Time
VVSS VDD
VCL
Output Clamp Low
VVSS VDD
VCH
Output Clamp High
mA2ISINK
Output Sink Current
mA2ISOURCE
Output Source Current
Ω
700 1000 1300
ROUT_
DC Output Impedance
mV0.25 1.00VHS
Hold Step
%0.01 0.08Linearity Error
350 500 650
35 50 65
pF10 20CIN
Input Capacitance
mV/sec140∆VOUT_
Droop Rate
mV-30 -5 30
µV/°C20 40
VOS
Offset Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
8V step with 500ns
rising edge
(Note 1)
dB
-72 -76
Analog Crosstalk
MAX5165L
MAX5165M
MAX5165N
RL= ∞V
VSS + VDD -
0.75 2.4
VOUT_
Output Voltage Range
MAX5165L, CL= 250pF
MAX5165M, CL= 10nF
MAX5165N, CL= 10nF
Figure 2 (Note 1) ns50tDS
Data Setup Time
ANALOG SECTION
TIMING PERFORMANCE
-72 -76
-72 -76
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -5V, VL = +5V ±5%, AGND = DGND, RL= 5kΩ, CL= 50pF, TA= TMIN to TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
Note 1: Guaranteed by design.
Note 2: Only one M_ input may be asserted low at a time, so only one channel is selected (see Single vs. Simultaneous Sampling).
Note 3: Do not exceed the absolute maximum rating for VDD to VSS of +15.75V (see Absolute Maximum Ratings).
For both VDD and VSS in sample mode,
VIN = 0
A0–A3 = 0.8V or 2V;
M0, M1, M2 = 0.8V or 2V
A0–A3 = DGND or VL;
M0, M1, M2 = DGND or VCC
RL= ∞
RL= ∞
(Note 3)
(Note 3)
A_ = DGND or VL, M_ = DGND or VL
CONDITIONS
dB-60 -75PSRRPower-Supply Rejection Ratio
mA5IL
Digital Logic Supply Current
mA0.5IL
Digital Logic Supply Current
mA36ISS
Negative Analog Supply Current
mA36IDD
Positive Analog Supply Current
V4.75 5 5.25VL
Digital Logic Supply Voltage
V-4.75 -5.0 -5.45VSS
Negative Analog Supply Voltage
V9.5 10 10.5VDD
Positive Analog Supply Voltage
V0.8VIL
Input Voltage Low
V2.0VIH
Input Voltage High
µA-1 +1II
Input Current
UNITSMIN TYP MAXSYMBOLPARAMETER
DIGITAL INPUTS
POWER SUPPLIES
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = +10V, VSS = -5V, VL= +5V, IN = GND, RL= ∞, CL= 0, AGND = DGND, VCH = VDD, VCL = VSS, TA= +25°C, unless other-
wise noted.)
0
4
2
10
8
6
16
14
12
18
-40 0 20-20 406080100
DROOP RATE vs. TEMPERATURE
MAX5165-01
TEMPERATURE (°C)
DROOP RATE (mV/sec)
1k 10k
0
-10
-20
-30
-40
-60
-50
-70
-80
-90
110100
POWER-SUPPLY REJECTION RATIO
(HOLD MODE)
MAX5165-02
FREQUENCY (kHz)
PSRR (dB)
-SUPPLY +SUPPLY
1k 10k
0
-10
-20
-30
-40
-60
-50
-70
-80
-90
1 10 100
POWER-SUPPLY REJECTION RATIO
(SAMPLE MODE)
MAX5165-03
FREQUENCY (kHz)
PSRR (dB)
-SUPPLY
+SUPPLY
0
25
50
75
-40 20 40-20 0 60 80 100
HOLD STEP vs. TEMPERATURE
MAX5165-04
TEMPERATURE (°C)
HOLD STEP (µV)
0
20
10
50
40
30
60
70
90
80
100
-5.0 -3.0 -1.0 1.0 3.0 5.0 7.0
HOLD STEP vs. INPUT VOLTAGE
MAX5165-07
INPUT VOLTAGE (V)
HOLD STEP (µV)
-5.0
-4.0
-4.5
-3.0
-3.5
-2.5
-2.0
-40 20 40-20 0 60 80 100
OFFSET VOLTAGE vs. TEMPERATURE
MAX5165-05
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)
1.00
1.10
1.05
1.20
1.15
1.30
1.25
1.35
1.45
1.40
1.50
-5.0 -2.0 -0.5 1.0-3.5 2.5 4.0 5.5 8.57.0 10.0
DROOP RATE vs. INPUT VOLTAGE
MAX5165-06
INPUT VOLTAGE (V)
DROOP RATE (mV/sec)
-4.5
-4.3
-4.4
-4.0
-4.1
-4.2
-3.9
-3.8
-3.6
-3.7
-3.5
-5.0 -3.0 -1.0 1.0 3.0 5.0 7.0
OFFSET VOLTAGE vs. INPUT VOLTAGE
MAX5165-08
INPUT VOLTAGE (V)
OFFSET VOLTAGE (mV)
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
_______________________________________________________________________________________ 5
3-TO-8
DECODER AND0
1-TO-8 MULTIPLEXER
AND7
EN
88
IN
1-TO-8 MULTIPLEXER
EN
IN
1-TO-8 MULTIPLEXER
EN
IN
1-TO-8 MULTIPLEXER
EN
IN
VCC
VDD
VL
AGND
DGND
IN
M3
M2
M1
M0
A2
A1
A0
SAMPLE-AND-HOLD
SAMPLE-AND-HOLD
SAMPLE-AND-HOLD
SAMPLE-AND-HOLD
OUTPUT CLAMPING
D0
CH
CL
OUT0
OUT7
OUT8
OUT15
OUT16
OUT23
OUT24
OUT31
D0
D31 D31
8
8
8
MAX5165
Figure 1. Functional Diagram
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
6 _______________________________________________________________________________________
_______________Detailed Description
The MAX5165 connects a single analog input to the
inputs of four internal 1-to-8 analog multiplexers. Each
multiplexer channel connects to a buffered sample/hold
circuit and a series output resistor, creating a single-
input device with 32 sample/hold output channels.
Three multiplexer channel-address inputs and four
mode-select inputs (one for each multiplexer) control
channel selection and sample/hold functions (Figure 1
and Tables 1, 2).
Digital Interface
Three address pins and 3-to-8 address decoder logic
select the channel for all four internal analog multiplex-
ers. The mode-select inputs (M3–M0) independently
control the sample/hold functions for each multiplexer
(Tables 1, 2).
Sample/Hold
The MAX5165 contains 32 buffered sample/hold cir-
cuits with internal hold capacitors. Internal hold capaci-
tors minimize leakage current, dielectric absorption,
feedthrough, and required board space. The value of
the hold capacitor affects acquisition time and droop
rate. Lower capacitance allows faster acquisition times
but increases the droop rate. Higher values increase
hold time and acquisition time. The hold capacitor used
in the MAX5165 provides fast 2.5µs (typ) acquisition
time while maintaining a low 1mV/sec (typ) droop rate,
making the sample/hold ideal for high-speed sampling.
Pin Description
NAME FUNCTION
1, 47, 48 A2, A0, A1
Address Inputs. The input of a 3-to-8 decoder, which controls channel selection for all four 1-to-8
multiplexers simultaneously. Selects which output channels are connected to the input during
sample mode (Tables 1, 2).
2–5 M0–M3
Mode-Selection/Multiplexer-Enable Inputs 0 to 3. Independent controls for each of the four 1-to-8
multiplexers. A logic low enables sample mode by connecting the selected channel (via address
inputs A2, A1, A0) to IN. A logic high selects hold mode (Tables 1, 2).
PIN
6VL Positive Digital Logic Power-Supply Input
7DGND Digital Ground
8 VSS Negative Analog Power-Supply Input
9AGND Analog Ground
10 IN Analog Input. Connects to the input of all four internal 1-to-8 multiplexers.
11 CH Clamp High Input. Clamps VOUT to (VCH + 0.7V).
12 CL Clamp Low Input. Clamps VOUT to (VCL - 0.7V).
13 N.C. No Connection. Not internally connected.
14–29 OUT0–OUT15 Sample/Hold Outputs 0 to 15
30 VDD Positive Analog Power-Supply Input
31–46 OUT16–OUT31 Sample/Hold Outputs 16 to 31
Sample Mode
Driving M3–M0 low (one at a time) selects sample
mode (Tables 1, 2). During sample mode, the selected
multiplexer channel connects to IN, allowing the hold
capacitor to acquire the input signal. To guarantee an
accurate sample, maintain sample mode for at least
4µs. The output of the S/H amplifier tracks the input
after 4µs. Only the addressed channel on the selected
multiplexer samples the input; all other channels remain
in hold mode.
Hold Mode
Driving M3–M0 high selects hold mode. Hold mode dis-
ables the multiplexer and disconnects all eight chan-
nels on the 1-to-8 multiplexer from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/sec
droop rate (towards VDD).
Hold Step
When switching between sample mode and hold mode,
the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capaci-
tor. The MAX5165 limits the hold step to 0.25mV (typ).
An output capacitor to ground can be used to filter out
this small hold-step error.
Output
The MAX5165 contains an output buffer for each multi-
plexer channel (32 total), so the hold capacitor sees a
high-impedance input, reducing the droop rate. The
capacitor droops at a 1mV/sec (typ) rate while in hold
mode. The buffer also provides a low output imped-
ance; however, the device contains output resistors in
series with the buffer output (Figure 1) for selected out-
put filtering. To provide greater design flexibility, the
MAX5165 is available with an ROof 50Ω, 500Ω, or 1kΩ.
Note: Output loads increase the analog supply cur-
rent (IDD and ISS). Excessive loading of the output(s)
damages the device by consuming more power than the
device will dissipate (see Absolute Maximum Ratings).
The resistor-divider formed by the output resistor (ROUT)
and load impedance (RL) scales the sampled voltage
(VSAMP). Determine the output voltage (VOUT_) as follows:
Voltage Gain = AV= RL / (RL+ ROUT)
VOUT_ = VSAMP ·AV
The maximum output voltage range depends on the
analog supply voltages available, and the scaling factor
used:
(VSS + 0.75V) ·AV≤VOUT_ ≤(VDD - 2.4V) ·AV
when RL= ∞, then AV= 1 and this equation becomes:
(VSS + 0.75V) ≤VOUT ≤(VDD - 2.4V)
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
_______________________________________________________________________________________ 7
0
0
Table 1. Output Selection
Table 2. Mode Selection
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
ADDRESS
0
1
0
1
OUT2
OUT3
OUT6
OUT0
OUT7
OUT1
OUT4
OUT5
OUT10
OUT11
OUT14
OUT8
OUT15
OUT9
OUT12
OUT13
OUT18
OUT19
OUT22
OUT16
OUT23
OUT17
OUT20
OUT21
OUTPUT SELECTED
OUT26
OUT27
OUT30
OUT24
OUT31
OUT25
OUT28
OUT29
A2 A1 A0 MUX0 MUX1 MUX2 MUX3
0 = Logic Low, 1 = Logic High
0
1
Sample mode enabled on selected
analog multiplexer and channel
(Table 1).
Hold mode enabled on selected
analog multiplexer and channel
(Table 1).
MODE-SELECT
INPUTS (M3–M0) ACTION
0 = Logic Low, 1 = Logic High
* Only one M_ input asserted low; all others must be logic high
to meet the timing specification (see Single vs. Simultaneous
Sampling section).
MAX5165
Output Clamp
The MAX5165 clamps the output between two external-
ly applied reference voltages. Internal diodes connect
all outputs to the clamping voltages, restricting the out-
put voltage to:
VCH + 0.7V ≤VOUT_ ≤VCL - 0.7V
When the clamping voltage exceeds the maximum out-
put voltage, the maximum output voltage will be the lim-
iting factor. To disable output clamping, connect CH to
VDD and CLto VSS to set the clamping voltages beyond
the maximum output voltage range. The clamping
diodes allow the MAX5165 to be used with other
devices requiring restricted input voltages.
Timing Definitions
Acquisition time (tAQ) is the amount of time the
MAX5165 must remain in sample mode for the hold
capacitor to acquire an accurate sample. The hold-
mode settling time (tH) is the amount of time necessary
for the output voltage to settle to its final value. Aperture
delay (tAP) is the time interval required to disconnect
the input from the hold capacitor. The inhibit pulse
width (tPW) is the amount of time the MAX5165 must
remain in hold mode while the address is changed. The
data setup time (tDS) is the amount of time an address
must be maintained before the address becomes valid.
The data hold time (tDH) is the amount of time that an
address must be maintained after mode select has
gone from low to high (Figure 2).
__________Applications Information
Control-Line Reduction
The MAX5165 contains four separate 1-to-8 multiplex-
ers and individual mode selectors for each multiplexer.
Configure the device to sample only one channel at a
time or up to four channels (with the same address, see
Table 1) simultaneously. When sampling one channel
at a time, use an external 2-to-4 decoder (with active-
low outputs) to reduce the number of digital control
lines from seven to five (Figure 3).
Single vs. Simultaneous Sampling
Individually control the four mode/multiplexer-select
pins to simultaneously sample on four channels, the
same channel for each multiplexer (Figure 4). Each
mode-select pin controls sampling on one of the 1-to-8
multiplexers, while the 3-bit address selects one of the
eight channels on all the multiplexers (Tables 1, 2).
Setting any combination of the mode-select pins low
enables sampling on the addressed channels for the
selected multiplexers.
Simultaneously sampling two or more channels reduces
offset voltage but increases acquisition time. Multiply
the single-channel acquisition time by the number of
channels sampling.
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
8 _______________________________________________________________________________________
MODE
SELECT
ADDRESS
(A0–A2)
OUTPUT
INPUT
tPW
tAQ
tDH
tH
tAP
HOLD STEP
tDS
Figure 2. Timing Performance
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
_______________________________________________________________________________________ 9
1/16 MAX5165
ADDRESS
DECODER
MODE SELECTOR
DECODER
CHANNEL
ADDRESS
M0
A0–A2
2
OUT8
OUT0
AGND
AGND
M1
M2
M3
IN
INPUT
SIGNAL
533
Figure 3. Control-Line Reduction
1/16 MAX5165
ADDRESS
DECODER
MODE/MULTIPLEXER
SELECTION
INPUT
SIGNAL
ADDRESS
M0
A0–A2
OUT8
OUT0
AGND
AGND
M1
M2
M3
IN
33
Figure 4. Simultaneous Sampling
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
10 ______________________________________________________________________________________
1/16 MAX5165
ADDRESS
DECODER
MODE SELECTOR
DECODER
DIGITAL
INPUTS
ADDRESS
DAC
M0
A0–A2
2
OUT8
OUT0
AGND
AGND
M1
M2
M3
IN
533
Figure 5. Multiplexing a DAC
Chip Information
TRANSISTOR COUNT: 5077
Multiplexed DAC
Figure 5 shows a typical demultiplexer application.
Different digital codes are converted by the digital-to-
analog converter (DAC) and then stored on 32 different
channels of the MAX5165. The 100mV/sec (max) droop
rate requires refreshing the hold capacitors every
100ms before the voltage drops by 1/2LSB for an 8-bit
DAC with a 5V full-scale voltage.
Powering the MAX5165
The MAX5165 does not require a special power-up
sequence to avoid latchup. The device requires three
separate supply voltages for operation; however, when
one or two of the voltages are not available, DC-DC
charge-pump (switched-capacitor) converters provide
a simple, efficient solution. The MAX860 provides volt-
age doubling or inversion, ideal for conversions from
+5V to +10V or from +5V to -5V. The MAX860 also
functions as a voltage divider to provide conversion
from +10V to +5V.
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
______________________________________________________________________________________ 11
Package Information
TQFPPO.EPS
MAX5165
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
NOTES
