S3C9004/P9004/C9014/P9014 PRODUCT OVERVIEW
1-1
1 PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87RI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM87RI microcontrollers have
an external interface that provides access to external memory and other peripheral devices.
S3C9004/P9004/C9014/P9014 MICROCONTROLLER
The S3C9004/P9004/C9014/P9014 single-chip 8-bit microcontroller is fabricated using an advanced CMOS
process. It is built around the powerful SAM87RI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9004/P9004/C9014/P9014 has 4 K
bytes of program memory on-chip.
Using the SAM87RI design approach, the following peripherals were integrated with the SAM87RI core:
—Five configurable I/O ports (32 pins)
—12 bit-programmable pins for external interrupts
—8-bit timer/counter with three operating modes
The S3C9004/P9004/C9014/P9014 is a versatile microcontroller that can be used in a wide range of general
purpose applications. It is especially suitable for use as a keyboard controller and is available in a 40-pin DIP and
a 44-pin QFP package.
OTP
The S3C9004/C9014 microcontroller is also available in OTP (One Time Programmable) version,
S3P9004/P9014. S3P9004/P9014 microcontroller has an on-chip 8-Kbyte one-time-programmable EPROM
instead of masked ROM. The S3P9004/P9014 is comparable to S3C9004/C9014, both in function and in pin
configuration.
PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014
1-2
FEATURES
CPU
•SAM87RI CPU core
Memory
•4-Kbyte internal program memory (ROM)
•208-byte internal register file
•8-Kbyte external program memory
•8-Kbyte external data memory
Instruction Set
•41 instructions
•IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
•1.5 µs at 4 MHz fOSC
Interrupts
•14 interrupt sources with one vector, Each
source has its pending bit
•One level, one vector interrupt structure
Oscillation Circuit Options
•4 MHz RC oscillator with on chip capacitor for
S3C9004/P9004 ( –10% RC accuracy at VDD ±
5% and Ta = 0°C–70°C, using 1% external
precision resistor)
•RC oscillator for S3C9004/P9004
•Crystal/ceramic oscillator for S3C9014/P9014
General I/O
•Five ports (32 pins total)
•Three bit-programmable ports (20 pins total)
•Two bit-programmable ports with external
interrupts (12 pins total)
Timer/Counter
•One 8-bit basic timer for watchdog function and
programmable oscillation stabilization interval
generation function
•One 8-bit timer/counter with PWM mode
Operating Temperature Range
•– 40°C to + 85°C
Operating Voltage Range
•4.5 V to 5.5 V for S3C9004/P9004
•2.7 V to 5.5 V for S3C9014/P9014
Package Types
•40-pin DIP
S3C9004/P9004/C9014/P9014 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
PORT
PORT
SAM87RI CPU
P0.0-P0.4/A8-A12,
P0.5-P0.7
4-KB ROM
RESET
P3.0
P3.1
P3.2
P3.3/CLO
EA (TEST)
MAIN
OSC
208-BYTE
REGISTER
FILE
PORT
P4.0/INT
P4.1/INT/T0CLK
P4.2/INT
P4.3/INT/T0OUT
Timer 0
PORT PORT
P2.0-P2.7/INT,
AS, DS, R/W, DM
P1.0-P1.7/
AD0-AD7
XIN
XOUT
SAM87RI BUS
Basic
Timer
I/O PORT AND
INTERRUPT CONTROL
VDD
VSS1 VDD
VSS1
Figure 1-1. Block Diagram
PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014
1-4
PIN ASSIGNMENTS
P3.0
INT/P4.0
T0CLK/INT/P4.1
INT/P4.2
T0OUT/INT/P4.3
AS/INT/P2.0
DS/INT/P2.1
R/W/INT/P2.4
DM/INT/P2.3
INT/P2.4
INT/P2.5
INT/P2.6
INT/P2.7
NC
VSS1
AD7/P1.7
AD6/P1.6
AD5/P1.5
AD4/P1.4
AD3/P1.3
40-DIP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P3.1
P3.2
P3.3/CLO
VDD
P0.0/A8
P0.1/A9
P0.2/A10
P0.3/A11
P0.4/A12
P0.5
P0.6
P0.7
XIN
RESET
EA
P1.0/AD0
P1.1/AD1
P1.2/AD2
XOUT
VSS2
S3C9004/P9004
S3C9014/P9014
Figure 1-2. Pin Assignment Diagram (40-Pin DIP Package)
S3C9004/P9004/C9014/P9014 PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C9004/P9004/C9014/P9014 Pin Descriptions
Pin
Names Pin
Type Pin
Description Circuit
Number Pin
Numbers Share
Pins
P0.0-P0.7 I/O Bit-programmable I/O port for Schmitt trigger
input or open-drain output. Port0 can also be
configured as external interface address lines A8-
A12.
C36-29 A8-A12
P1.0-P1.7 I/O Bit-programmable I/O port for Schmitt trigger
input, push-pull, or open-drain output. Port1 can
alternatively be used as external interface
address/data lines AD0-AD7.
C23-16 AD0-AD7
P2.0-P2.7 I/O Bit-programmable I/O port for Schmitt trigger
input or push-pull output. Port2 can be
individually configured as external interrupt
inputs. Especially, P2.0-2.3 can be configured for
external bus control signal.
D6-13 INT, AS,
DS, R/W,
DM
P3.0-P3.3 I/O Same general characteristics as Port1. Port3 are
designed for to drive LED directly. P3.3 can be
used to system clock output (CLO) port.
C1, 40-38 P3.3/CLO
P4.0-P4.3 I/O Bit-programmable I/O port. Input mode or n-
channel open-drain output mode is software
assignable. Port4 can be individually configured
as external interrupt inputs. Pull-up resistors are
also software assignable. Especially, P4.1 can be
used T0CLK input and P4.3 also T0OUT for
Timer 0.
D2-5 INT,
T0CLK,
T0OUT
XIN, XOUT –System clock input and output pin (for RC
oscillator, crystal/ceramic oscillator, or external
clock source)
–27, 28 –
INT IExternal interrupt for bit-programmable port2 and
port4 pins when set to input mode. –2-13 PORT2/
PORT4
RESET IRESET signal input pin. Schmitt trigger input with
internal pull-up resistor. A26 –
EA IExternal Memory Access (EA) pin with 2 modes:
0V = Normal Operation Mode
5V = ROMLESS Operation Mode
(Must be connected to VSS during normal
operation mode)
B24 –
VDD –Power input pin – 37 –
VSS1, VSS2 –Vss1 is a ground power for CPU core.
Vss2 is a ground power for I/O and OSC block –15, 25 –
NC –No connection
(This pin would be better connecting to VSS)– 14 –
PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014
1-6
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the S3C9004/P9004/C9014/P9014
Circuit Number Circuit Type S3C9004/P9004/C9014/P9014 Assignments
AIRESET signal input
BIEA input
CI/O Ports 0, 1, and 3
DI/O Ports 2 and 4
VDD
PULL-UP
RESISTOR
IN Noise
Filter
Figure 1-3. Pin Circuit Type A (RESETRESET)
IN
0 V = Internal ROM Access
5 V = External ROM Access
Figure 1-4. Pin Circuit Type B (EA)
VDD
OPEN
DRAIN
OUTPUT
DISABLE
INPUT
DATA MUX D0
D1
MODE INPUT DATA
INPUT
OUTPUT D0
D1
I/O
OUTPUT
DATA
VSS
Figure 1-5. Pin Circuit Type C (Ports 0, 1, and 3)
S3C9004/P9004/C9014/P9014 PRODUCT OVERVIEW
1-7
VDD
OPEN
DRAIN
OUTPUT
DISABLE
INPUT
DATA
MODE INPUT DATA
INPUT
OUTPUT D0
D1
I/O
OUTPUT
DATA
VSS
PULL-UP
ENABLE
VDD
PULL-UP
RESISTOR
MUX D0
D1
Figure 1-6. Pin Circuit Type D (Ports 2 and 4)
PRODUCT OVERVIEW S3C9004/P9004/C9014/P9014
1-8
APPLICATION CIRCUIT
KEYBOARD
MATRIX
0
1
2
3
15
0
1
2
3
7
5V
H
O
S
T
5V
CLK
DATA
XIN
XOUT
VSS1 VSS2
VDD
PORT 3
PORT 0PORT 1PORT 2
EA
RESET
S3C9004
S3P9004
PORT 4
ROSC
Figure 1-7. Keyboard Control Application Circuit Diagram
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-1
12 ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9004/P9004/C9014/P9014 electrical characteristics are presented in tables and
graphs:
—Absolute maximum ratings
—D.C. electrical characteristics
—I/O capacitance
—A.C. electrical characteristics
—Input timing for RESET
—Input timing for external interrupts (ports 2 and 4, RESET, and EA)
—Oscillator characteristics
—Oscillation stabilization time
—Clock timing measurement points at XIN
—Data retention supply voltage in Stop mode
—Stop mode release timing when initiated by a reset
—Stop mode release timing when initiated by an external interrupt
—External Memory timing characteristics (8 MHz)
—External Memory Read and Write timing
—Characteristic curves
ELECTRICAL DATA S3C9004/P9004/C9014/P9014
12-2
Table 12-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter Symbol Conditions Rating Unit
Supply Voltage VDD –– 0.3 to + 6.5 V
Input Voltage VIN All input ports – 0.3 to VDD + 0.3 V
Output Voltage VOAll output ports – 0.3 to VDD + 0.3 V
Output Current IOH One I/O pin active – 18 mA
High All I/O pins active – 60
Output Current IOL One I/O pin active + 25 mA
Low Total pin current for ports 3 + 100
Total pin current for ports 0, 1, 2, 4 + 100
Operating
Temperature TA– – 40 to + 85 °C
Storage
Temperature TSTG –– 65 to + 150 °C
Table 12-2. D.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V (1))
Parameter Symbol Conditions Min Typ Max Unit
Input High
Voltage VIH1 All inputs except VIH2 0.8 VDD –VDD V
VIH2 XIN VDD – 0.5 VDD
Input Low Voltage VIL1 All inputs except VIL2 –0.2 VDD V
VIL2 XIN 0.4
Output High
Voltage VOH IOH = – 200 µA
All outputs except P4.1,
P4.3, and port0
VDD – 1.0 – – V
Output Low
Voltage VOL IOL = 2 mA
All outputs except port3 – – 0.4 V
Output Low
Current IOL VOL= 3 V
Port3 only 8 15 23 mA
Input High
Leakage Current ILIH1 VIN = VDD
All inputs except ILIH2, P4.0
and P4.1
––3µA
ILIH2 VIN = VDD
XIN, XOUT
20
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-3
Table 12-2. D.C. Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V (1))
Parameter Symbol Conditions Min Typ Max Unit
Input Low
Leakage Current ILIL1 VIN = 0 V
All inputs except ILIL2, P4.0 and
P4.1
– – – 3 µA
ILIL2 VIN = 0 V
XOUT, XIN
– 20
Output High
Leakage Current ILOH VOUT = VDD
All outputs – – 3 µA
Output Low
Leakage Current ILOL VOUT = 0 V
All outputs – – – 3 µA
Pull-up Resistors RL1 VIN = 0 V; Port 2 only 30 60 90 KΩ
RL2 VIN = 0 V; Port 4 only 1.82.8 4.0
RL3 VIN = 0 V; RESET only 50 90 150
Supply Current (2) IDD1 Normal operation mode
4 MHz CPU clock –4.5 10 mA
IDD2 Idle mode; 4 MHz oscillator 0.9 3mA
IDD3 Stop mode 0.5 5µA
NOTES:
1. The operating voltage range of S3C9014/P9014 is from 2.7 V to 5.5 V according to oscillation frequency.
2.Supply current does not include current drawn through internal pull-up resistors or external output current loads.
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-5
Table 12-3. Input/Output Capacitance
(TA = – 40°C to + 85°C, VDD = 0 V)
Parameter Symbol Conditions Min Typ Max Unit
Input
Capacitance CIN f = 1 MHz; unmeasured pins
are connected to VSS – – 10 pF
Output
Capacitance COUT
I/O Capacitance CIO
Table 12-4. A.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Unit
Interrupt Input
High, Low Width tINTH, tINTL P2 and P4 – 200 – ns
RESET Input
Low Width tRSL RESET –1,000 –
RESET
tRSL
0.2 VDD
Figure 12-1. Input Timing for RESETRESET
ELECTRICAL DATA S3C9004/P9004/C9014/P9014
12-6
tINTL tINTH
0.8 VDD
0.2 VDD
Figure 12-2. Input Timing Measurement Points for Port 2, Port 4, and RESETRESET
Table 12-5. Oscillator Characteristics
(TA = – 40°C + 85°C, VDD = 4.5 V to 5.5 V)
Oscillator Clock Circuit Test Condition Min Typ Max Unit
RC Oscillator (with
Internal Capacitor;
for S3C9004/P9004)RXIN
XOUT
VDD = 4.75 to 5.25 V
TA = 0°C + 70°C
Tolerance: ± 10% (note)
–4–MHz
Crystal/Ceramic
Oscillator
(for S3C9014/P9014)
C2
XIN
XOUT
C1
Crystal/Ceramic
oscillation frequency 1.0 –8.0
NOTE:The S3C9004/P9004 provides an internal capacitor to accommodate an RC oscillator configuration. A 1%
precision resistor must be used to achieve an oscillation frequency with an acceptable tolerance.
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-7
CPU CLOCK
1 MHz
SUPPLY VOLTAGE (V)
2 MHz
3 MHz
4 MHz
6 MHz
8 MHz
2 3 4 5 6 71 2.7 3.5 5.5
Figure 12-3. Operating Voltage Range (S3C9014/P9014)
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-9
Table 12-6. Oscillation Stabilization Time
(TA = – 40°C + 85°C, VDD = 4.5 V to 5.5 V)
Oscillator Test Condition Min Typ Max Unit
Main Crystal fOSC = 4 MHz – – 10 ms
Main Ceramic (Oscillation stabilization occurs when VDD is equal to
the minimum oscillator voltage range.)
Oscillator
Stabilization Wait
Time
tWAIT stop mode release time by a reset –216 /
fOSC
–
tWAIT stop mode release time by an interrupt –(note) –
NOTE:The oscillator stabilization wait time, tWAIT, is determined by the setting in the basic timer control register, BTCON.
XIN
tXL tXH
1 / fOSC
VDD – 0.5 V
0.4 V
Figure 12-4. Clock Timing Measurement Points at XIN
Table 12-7. Data Retention Supply Voltage in Stop Mode
(TA = – 40°C + 85°C)
Parameter Symbol Conditions Min Typ Max Unit
Data Retention
Supply Voltage VDDDR Stop mode 2.0 – 6 V
Data Retention
Supply Current IDDDR Stop mode; VDDDR = 2.0 V ––5µA
ELECTRICAL DATA S3C9004/P9004/C9014/P9014
12-10
tWAIT
VDD
RESET
EXECUTION OF
STOP INSTRUCTION
VDDDR
DATA RETENTION
MODE
STOP MODE
INTERNAL RESET
OPERATION IDLE MODE
(BASIC TIMER
ACTIVE)
0.8 VDD
0.2 VDD
NORMAL
OPERATING
MODE
~
~
~
~
Figure 12-5. Stop Mode Release Timing When Initiated by a Reset
tWAIT
VDD
EXTERNAL
INTERRUPT
EXECUTION OF
STOP INSTRUCTION
VDDDR
DATA RETENTION
MODE
STOP MODE
IDLE MODE
(BASIC TIMER
ACTIVE)
0.8 VDD
0.2 VDD
NORMAL
OPERATING
MODE
~
~~
~
Figure 12-6. Stop Mode Release Timing When Initiated by an External Interrupt
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-11
Table 12-8. External Memory Timing Characteristics (4 MHz)
(TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V)
Number Symbol Parameter Normal Timing (ns)
Min Max
1tdA (AS) Address valid to AS ↑ delay 10 –
2tdAS (A) AS ↑ to address float delay 35 –
3tdAS (DR) AS ↑ to read data required valid – 140
4twAS AS Low width 88 –
5tdA (DS) Address float to DS ↓0 –
6a twDS (read) DS (read) Low width 314 –
6b twDS (write) DS (write) Low width 164 –
7tdDS (DR) DS ↓ to read data required valid – 80
8thDS (DR) Read data to DS ↑ hold time 0 –
9tdDS (A) DS ↑ to address active delay 20 –
10 tdDS (AS) DS ↑ to AS ↓ delay 30 –
11 tdDO (DS) Write data valid to DS (write) ↓ delay 10 –
12 tdRW (AS) R/W valid to AS ↑ delay 20 –
13 tdDS (DW) DS ↑ to write data not valid delay 20 –
NOTES:
1. All times are in nano seconds (ns) and assume an 4 MHz input frequency.
2. Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7.
ELECTRICAL DATA S3C9004/P9004/C9014/P9014
12-12
PORT0
(P2.3)
PORT1
(P2.0)
(P2.1)
12
3
1 2 11
4
5
7
6
8
10
9
13
A0−A7 D0−D7 OUT D0−D7IN OUT
R/ (P2.2)
W
DM
AS
DS
A8−A12, DM
Figure 12-7. External Memory Read and Write Timing
(See Table 12-8 for a description of each timing point.)
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-13
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements. They do
not, however, represent guaranteed operating values.
IDD1
(mA)
1
0
VDD (V)
2
3
4
5
6
7
3.0 3.5 4.0 4.5 5.0 5.5 6.0
fOSC = 10 MHz
~
~
2.5
fOSC = 8 MHz
fOSC = 5 MHz
fOSC = 2 MHz
fOSC = 1 MHz
(TA = 25 C)
Figure 12-8. IDD1 vs. VDD
ELECTRICAL DATA S3C9004/P9004/C9014/P9014
12-14
IDD2
(µA)
200
0
VDD (V)
400
600
800
1000
1200
1400
3.0 3.5 4.0 4.5 5.0 5.5 6.0
~
~
2.5
fOSC = 10 MHz
fOSC = 5,8 MHz
fOSC = 2 MHz
fOSC = 1 MHz
(TA = 25 C)
Figure 12-9. IDD2 vs. VDD
S3C9004/P9004/C9014/P9014 ELECTRICAL DATA
12-15
IDD3
(nA)
400
0
VDD (V)
450
500
550
600
650
750
3.0 3.5 4.0 4.5 5.0 5.5 6.0
~
~
2.5
fOSC = 5 MHz
(TA = 25 C)
700
Figure 12-10. IDD3 vs. VDD
VOH (V)
0
-1
IOH (mA)
1
2
3
4
5
2 3 4 5 6 7 81
6
0 9 10 11 12
VDD = 5.0VVDD = 4.5V VDD = 5.5V
Figure 12-11. IOH vs. VOH
ELECTRICAL DATA S3C9004/P9004/C9014/P9014
12-16
VOL (V)
IOL (mA)
1
2
3
4
5
2 3 4 5 6 7 81
6
0 10 12 14 17
VDD = 4.5V
7
9 11 13 15 16
VDD = 5.5VVDD = 5.0V
Figure 12-12. VOL vs. IOL (Port 0, 1, 2, and 4)
VOL (V)
IOL (mA)
1
2
3
4
5
2 3 4 5 6 7 81
6
0 10 12 14 17
VDD = 4.5V
7
9 11 13 15 16
VDD = 5.5V
VDD = 5.0V
Figure 12-13. VOL vs. IOL (Port 3)
S3C9004/P9004/C9014/P9014 MECHANICAL DATA
13-1
13 MECHANICAL DATA
OVERVIEW
The S3C9004/P9004/C9014/P9014 is currently available in a 40-pin DIP package.
NOTE: Dimensions are in millimeters.
0-15 °
15.24
0.25 +0.1
– 0.05
0.51MIN 3.95 ± 0.2
3.30 ± 0.3 5.08MAX
52.42 ± 0.2
52.82 MAX
1.27 ± 0.1
0.46 ± 0.1
(2.00) 2.54
13.85 ± 0.2
#1 #20
#40 #21
40-DIP-600B
Figure 13-1. 40-Pin DIP Package Mechanical Data (40-DIP-600B)
MECHANICAL DATA S3C9004/P9004/C9014/P9014
13-2
NOTES
