LP3875-ADJ
IN OUT
ADJ
GND
CIN
COUT
INPUT OUTPUT
1.5 A
R1
R2
CFF
SD
SD
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3875-ADJ
SNVS247E –SEPTEMBER 2003–REVISED AUGUST 2016
LP3875-ADJ 1.5-A Fast Ultra-Low-Dropout LDOs
1
1 Features
1• Input Voltage Range: 2.5 V to 7 V
• Ultra Low Dropout Voltage
• Low Ground Pin Current
• Load Regulation of 0.06%
• 10-nA Quiescent Current in Shutdown Mode
• Specified Output Current of 1.5-A DC
• Minimum Output Capacitor Requirements
• Overtemperature/Overcurrent Protection
•−40°C to +125°C Junction Temperature Range
• Available in DDPAK/TO-263 and SOT-223
Packages
2 Applications
• Microprocessor Power Supplies
• GTL, GTL+, BTL, and SSTL Bus Terminators
• Power Supplies for DSPs
• SCSI Terminator
• Post Regulators
• High Efficiency Linear Regulators
• Battery Chargers
• Other Battery-Powered Applications
3 Description
The LP3875-ADJ fast ultra-low-dropout LDO operates
from a 2.5-V to 7-V input supply. This ultra-low-
dropout LDO responds very quickly to step changes
in load, which makes it suitable for low-voltage
microprocessor applications. The LP3875-ADJ is
developed on a CMOS process, which allows low
quiescent-current operation independent of output
load current. This CMOS process also allows the
LP3875-ADJ to operate under extremely low dropout
conditions.
• Dropout Voltage: Ultra-low-dropout voltage;
typically 38 mV at 150-mA load current and 380
mV at 1.5-A load current.
• Ground Pin Current: Typically 6 mA at 1.5-A load
current.
• Shutdown Mode: Typically 10-nA quiescent
current when the SD pin is pulled low.
• Adjustable Output Voltage: The output voltage
may be programmed via two external resistors.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LP3875-ADJ SOT-223 (5) 6.50 mm × 3.56 mm
TO-263 (5) 10.16 mm × 8.42 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
Simplified Schematic
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description.............................................. 8
7.1 Overview................................................................... 8
7.2 Functional Block Diagram......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
8 Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application.................................................... 9
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Examples................................................... 15
11 Device and Documentation Support................. 17
11.1 Related Documentation ....................................... 17
11.2 Receiving Notification of Documentation Updates 17
11.3 Community Resources.......................................... 17
11.4 Trademarks........................................................... 17
11.5 Electrostatic Discharge Caution............................ 17
11.6 Glossary................................................................ 17
12 Mechanical, Packaging, and Orderable
Information........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2013) to Revision E Page
• Added Device Information table, Pin Configuration and Functions section, ESD Ratings and Thermal Information
tables, Feature Description section, Device Functional Modes,Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
• Changed "Linear Regulator" in title and text of page 1 to "LDO"........................................................................................... 1
• Deleted all information re: TO-220 package, which is obsolete. ........................................................................................... 1
• Changed all VIN and VOUT pin names to IN and OUT in drawings and text........................................................................ 1
• Deleted "(survival)" from Abs Max rows ................................................................................................................................ 4
• Changed Changed RθJA values: SOT-223 package from "90°C/W" to "65.2°C/W, DDPAK/TO-263 package from
"60°C/W" to "40.3°C/W".......................................................................................................................................................... 4
• Added updated Thermal Values table and footnotes............................................................................................................. 4
• Deleted all "Heatsinking" subsections as they have out-of-date information; added Power Dissipation and Estimating
Junction Temperature .......................................................................................................................................................... 12
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Semiconductor data sheet to TI format.................................................................................... 15
1
2
3
4
5
IN
OUT
ADJ
GND
SD
IN
OUT
ADJ
SD
GND
1
2
3
4
5
Thermal Tab
is GND
3
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5 Pin Configuration and Functions
KTT Package
5-Pin DDPAK/TO-263
Top View
NDC Package
5-Pin SOT-223
Top View
Pin Functions
PIN
I/O DESCRIPTION
NAME NUMBER
DDPAK/TO-263 SOT-223
ADJ 5 4 O The ADJ pin is used to set the regulated output voltage by
connecting it to the external resistors R1 and R2.
GND 3 5 — Ground
IN 2 2 I Input supply
OUT 4 3 O Output voltage
SD 1 1 I Shutdown
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
(4) The output PMOS structure contains a diode between the IN and OUT pins. This diode is normally reverse biased. This diode will get
forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically
withstand 200 mA of DC current and 1 A of peak current.
(5) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heat sink values (if a
heat sink is used). If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal
shutdown.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
IN pin to GND pin voltage −0.3 7.5 V
Shutdown (SD) pin to GND pin voltage −0.3 7.5 V
OUT pin to GND pin voltage(3),(4) −0.3 6 V
IOUT Short-circuit protected
Power dissipation(5) Internally limited
Storage temperature, Tstg −65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5 V, whichever is greater.
6.3 Recommended Operating Conditions MIN MAX UNIT
VIN supply voltage(1) 2.5 7 V
Shutdown (SD) voltage −0.3 7 V
Maximum operating current (DC) IOUT 1.5 A
Junction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
6.4 Thermal Information
THERMAL METRIC(1) LP3875-ADJ
UNITNDC (SOT-223) KTT (TO-263)
5 PINS 5 PINS
RθJA(2) Junction-to-ambient thermal resistance, High K 65.2 40.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.2 43.4 °C/W
RθJB Junction-to-board thermal resistance 9.9 23.1 °C/W
ψJT Junction-to-top characterization parameter 3.4 11.5 °C/W
ψJB Junction-to-board characterization parameter 9.7 22 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a 1 °C/W
5
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(1) Limits are specified by testing, design, or statistical correlation.
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.
Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line
and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the
output voltage tolerance specification.
(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.
Dropout voltage specification applies only to output voltages of 2.5 V and above. For output voltages below 2.5 V, the dropout voltage is
nothing but the input to output differential, because the minimum input voltage is 2.5 V.
6.5 Electrical Characteristics
Unless otherwise specified: TJ= 25°C, VIN = VO(NOM) + 1 V, IL= 10 mA, COUT = 10 µF, VSD = 2 V.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VADJ ADJ pin voltage
VOUT + 1 V ≤VIN ≤7 V
10 mA ≤IL≤1.5 A 1.198 1.216 1.234 V
VOUT + 1 V ≤VIN ≤7 V
10 mA ≤IL≤1.5 A
–40°C to 125°C 1.180 1.216 1.253 V
IADJ ADJ pin input current
VOUT + 1 V ≤VIN ≤7 V
10 mA ≤IL≤1.5 A 10 nA
VOUT + 1 V ≤VIN ≤7 V
10 mA ≤IL≤1.5 A
–40°C to 125°C 100 nA
ΔVOL Output voltage line regulation(3) VOUT + 1 V ≤VIN ≤7 V 0.02%
VOUT + 1 V ≤VIN ≤7 V, –40°C ≤TJ≤125°C 0.06%
ΔVO/
ΔIOUT
Output voltage load regulation(3) 10 mA ≤IL≤1.5 A 0.06%
10 mA ≤IL≤1.5 A, –40°C ≤TJ≤125°C 0.12%
VIN –
VOUT Dropout voltage(4)
IL= 150 mA 38 50
mV
IL= 150 mA, –40°C ≤TJ≤125°C 60
IL= 1.5 A 380 450
IL= 1.5 A, –40°C ≤TJ≤125°C 550
IGND Ground pin current in normal
operation mode
IL= 150 mA 5 9
mA
IL= 150 mA,–40°C ≤TJ≤125°C 10
IL= 1.5 A 6 14
IL= 1.5 A, –40°C ≤TJ≤125°C 15
IGND Ground pin current in shutdown
mode VSD ≤0.3 V 0.01 10 µA
–40°C ≤TJ≤85°C 50
IO(PK) Peak output current VOUT ≥VO(NOM) – 4% 1.8 A
SHORT CIRCUIT PROTECTION
ISC Short-circuit current 3.2 A
6
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Electrical Characteristics (continued)
Unless otherwise specified: TJ= 25°C, VIN = VO(NOM) + 1 V, IL= 10 mA, COUT = 10 µF, VSD = 2 V.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
SHUTDOWN INPUT
VSDT Shutdown threshold
Output = high VIN
V
Output = high, –40°C ≤TJ≤125°C 2
Output = low 0
Output = low, –40°C ≤TJ≤125°C 0.3
Td(OFF) Turnoff delay IL= 1.5 A 20 µs
Td(ON) Turnon delay IL= 1.5 A 25 µs
ISD SD input current VSD = VIN 1 nA
AC PARAMETERS
PSRR Ripple rejection
VIN = VOUT + 1 V, COUT = 10 µF
VOUT = 3.3 V, ƒ = 120 Hz 73 dB
VIN = VOUT + 0.5 V, COUT = 10 µF
VOUT = 3.3 V, ƒ = 120 Hz 57
ρn(l/f) Output noise density f = 120 Hz 0.8 µV
enOutput noise voltage BW = 10 Hz – 100 kHz, VOUT = 2.5 V 150 µVRMS
BW = 300 Hz – 300 kH, VOUT = 2.5 V 100
-40 -20 0 20 40 60 80 100 125
JUNCTION TEMPERATURE (oC)
0
0.5
1
1.5
2
2.5
3
'VOUT/V CHANGE IN VIN (mV)
SHUTDOWN IQ (PA)
TEMPERATURE (oC)
-40 -20 0 20 40 60 80 100 125
0.001
0.01
0.1
1
10
-40 -20 0 20 40 60 80 100 125
JUNCTION TEMPERATURE (oC)
0
0.5
1
1.5
2
2.5
3
DC LOAD REGULATION (mV/A)
1.8 2.3 2.8 3.3 3.8 4.3 4.8
OUTPUT VOLTAGE (V)
0
1
2
3
4
5
6
GROUND PIN CURRENT (mA)
0 0.5 11.5
0
100
200
300
400
500
600
OUTPUT LOAD CURRENT (A)
DROPOUT VOLTAGE (mV)
25oC
-40oC
125oC
7
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6.6 Typical Characteristics
Unless otherwise specified: TJ= 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VO(NOM) + 1 V,
IL= 10 mA
Figure 1. Dropout Voltage vs Output Load Current
IL= 1.5 A
Figure 2. Ground Current vs Output Voltage
Figure 3. Shutdown IQvs Junction Temperature Figure 4. DC Load Regulation vs Junction Temperature
Figure 5. DC Line Regulation vs Temperature Figure 6. Noise vs Frequency
8
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7 Detailed Description
7.1 Overview
The LP3875-ADJ linear regulators is designed to provide an ultra-low-dropout voltage with excellent transient
response and load/line regulation. For battery-powered always-on type applications, the very low quiescent
current of the LP3875-ADJ in shutdown mode helps reduce battery drain.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Shutdown (SD)
The LM3875-ADJ device has a shutdown feature that turns the device off and reduces the quiescent current to
10 nA (typical).
7.3.2 Short-Circuit Protection
The LP3875-ADJ is short-circuit protected and, in the event of a peak overcurrent condition, the short-circuit
control loop rapidly drives the output PMOS pass element off. Once the power pass element shuts down, the
control loop rapidly cycles the output on and off until the average power dissipation causes the thermal shutdown
circuit to respond to servo the on/off cycling to a lower frequency. Refer to Power Dissipation for power
dissipation calculations.
7.3.3 Dropout Voltage
The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within
2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and
the RDS(ON) of the internal MOSFET.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
A CMOS logic low level signal at the shutdown (SD) pin turns off the regulator. The SD pin must be actively
terminated through a 10-kΩpullup resistor for a proper operation. If this pin is driven from a source that actively
pulls high and low (such as a CMOS rail-to-rail comparator), the pullup resistor is not required. This pin must be
tied to VIN if not used.
7.4.2 Active Mode
When voltage at SD pin of the LP3875-ADJ device is at logic high level, the device is in normal mode of
operation.
LP3875-ADJ
IN OUT
ADJ
GND
CIN
COUT
INPUT OUTPUT
1.5 A
R1
R2
CFF
SD
SD
R1
OUT = 1.216 (1 + )
R2
Vu
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10 µF
10 µF
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP3875-ADJ device is an LDO linear regulator designed to provide high load current of up to 1.5 A, low
dropout voltage, and low quiescent current in shutdown mode. Figure 7 shows the typical application circuit for
this device.
8.1.1 Reverse Current Path
The internal MOSFET in the LP3875-ADJ an inherent parasitic diode. During normal operation, the input voltage
is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above
the input in an application, then current flows from the output to the input as the parasitic diode gets forward
biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200-
mA continuous and 1-A peak.
8.2 Typical Application
Figure 7. LP3875-ADJ Typical Application Circuit
8.2.1 Design Requirements
For typical linear regulator LDO applications, use the parameters listed in Table 1:
Table 1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 2.5 V to 7 V
Output voltage 1.8 V
Output current 1.5 A
Output capacitor 10 µF
Input capacitor 10 µF
Output capacitor ESR range 100 mΩto 4 Ω
COUT ESR (:)
LOAD CURRENT (A)
STABLE REGION
COUT > 10 PF
012
.001
.01
0.1
1.0
10
10
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8.2.2 Detailed Design Procedure
8.2.2.1 External Capacitors
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
• Input Capacitor: An input capacitor of at least 10 µF is required. Ceramic, tantalum, or electrolytic capacitors
may be used, and capacitance may be increased without limit.
• Output Capacitor: An output capacitor is required for loop stability. It must be located less than 1 cm from the
device and connected directly to the output and ground pins using traces which have no other currents
flowing through them (see Layout).
The minimum value of output capacitance that can be used for stable full-load operation is 10 µF, but it may be
increased without limit. The output capacitor must have an equivalent series resistance (ESR) value as shown in
Figure 8. TI recommends tantalum capacitors for the output capacitor.
Figure 8. ESR Curve
8.2.2.2 CFF (Feed Forward Capacitor)
The capacitor CFF is required to add phase lead and help improve loop compensation. The correct amount of
capacitance depends on the value selected for R1 (see Figure 7). Select a capacitor such that the zero
frequency as given by the equation shown below is approximately 45 kHz:
Fz = 45,000 = 1 / ( 2 × π× R1 × CFF ) (1)
Use a good-quality ceramic with X5R or X7R dielectric for the CFF capacitor.
8.2.2.3 Selecting a Capacitor
Capacitance tolerance and variation with temperature must be considered when selecting a capacitor so that the
minimum required amount of capacitance is provided over the full operating temperature range. In general, a
good tantalum capacitor shows very little capacitance variation with temperature, but a ceramic capacitor may
not be as good (depending on dielectric type). Aluminum electrolytics also typically have large temperature
variation of capacitance value.
Equally important to consider is how the ESR of a capacitor changes with temperature: this is not an issue with
ceramics, as their ESR is extremely low. However, it is very important in tantalum and aluminum electrolytic
capacitors. Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic
capacitors is so severe they may not be feasible for some applications (see Capacitor Characteristics).
8.2.2.4 Capacitor Characteristics
8.2.2.4.1 Ceramic
For values of capacitance in the 10-µF to 100-µF range, ceramics are usually larger and more costly than
tantalum capacitors but give superior AC performance for bypassing high frequency noise because of very low
ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics
as a function of voltage and temperature.
11
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Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or
Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V
also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of
the temperature range.
If ceramic capacitors are used, TI recommends X7R and X5R dielectric ceramic capacitors as they typically
maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of
course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.
8.2.2.4.2 Tantalum
TI recommends using solid tantalum capacitors on the output because their typical ESR is very close to the ideal
value required for loop compensation. They also work well as input capacitors if selected to meet the ESR
requirements previously listed.
Tantalums also have good temperature stability: a good-quality tantalum typically shows a capacitance value that
varies less than 10-15% across the full temperature range of −40°C to +125°C. ESR varies only about 2× going
from the high to low temperature limits.
The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if
the ESR of the capacitor is near the upper limit of the stability range at room temperature).
8.2.2.4.3 Aluminum
Aluminium capacitors offer the most capacitance for the money. The disadvantages are that they are larger in
physical size, not widely available in surface mount, and have poor AC performance (especially at higher
frequencies) due to higher ESR and equivalent series inductance (ESL).
Compared by size, the ESR of an aluminum electrolytic is higher than either tantalum or ceramic, and it also
varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50×
when going from 25°C down to −40°C.
Also note that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates
they have poor high-frequency performance. Use only aluminum electrolytics that have an impedance specified
at a higher frequency (from 20 kHz to 100 kHz) for the LP3875-ADJ. Derating must be applied to the
manufacturer's ESR specification, because it is typically only valid at room temperature.
Any applications using aluminum electrolytics must be thoroughly tested at the lowest ambient operating
temperature where ESR is maximum.
8.2.2.5 Setting The Output Voltage
The output voltage is set using the resistors R1 and R2 (see Figure 7). The output is also dependent on the
reference voltage (typically 1.216 V) which is measured at the ADJ pin. The output voltage is given by the
equation:
VOUT = VADJ × ( 1 + R1 / R2) (2)
This equation does not include errors due to the bias current flowing in the ADJ pin which is typically about 10
nA. This error term is negligible for most applications. If R1 is > 100kΩ, a small error may be introduced by the
ADJ bias current.
The tolerance of the external resistors used contributes a significant error to the output voltage accuracy, with 1%
resistors typically adding a total error of approximately 1.4% to the output voltage (this error is in addition to the
tolerance of the reference voltage at VADJ).
8.2.2.6 Turnon Characteristics for Output Voltages Programmed to 2 V or Less
As VIN increases during start-up, the regulator output will track the input until VIN reaches the minimum operating
voltage (typically about 2.2 V). For output voltages programmed to 2 V or less, the regulator output may
momentarily exceed its programmed output voltage during start-up. Outputs programmed to voltages above 2 V
are not affected by this behavior.
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8.2.2.7 RFI/EMI Susceptibility
Radio frequency interference (RFI) and electromagnetic interference (EMI) can degrade the performance of any
device because of the small dimensions of the geometries inside the device. In applications where circuit sources
are present which generate signals with significant high frequency energy content (> 1 MHz), care must be taken
to ensure that this does not affect the device regulator.
If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes
from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the
device.
If a load is connected to the device output which switches at high speed (such as a clock), the high-frequency
current pulses required by the load must be supplied by the capacitors on the device output. Because the
bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above
that frequency. This means the effective output impedance of the device at frequencies above 100 kHz is
determined only by the output capacitors.
In applications where the load is switching at high speed, the output of the device may need RF isolation from
the load. TI recommends that some inductance be placed between the output capacitor and the load, and good
RF bypass capacitors be placed directly across the load.
PCB layout is also critical in high noise environments, because RFI/EMI is easily radiated directly into PC traces.
Noisy circuitry should be isolated from clean circuits where possible, and grounded through a separate path. At
MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the
ground plane.
In multilayer PCB applications, care must be taken in layout so that noisy power and ground planes do not
radiate directly into adjacent layers which carry analog power and ground.
8.2.2.8 Output Noise
Noise is specified in two ways:
• Spot Noise (or Output Noise Density): the RMS sum of all noise sources, measured at the regulator output, at
a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a
function of frequency.
• Total Output Noise (or Broad-Band Noise): the RMS sum of spot noise over a specified bandwidth, usually
several decades of frequencies.
Attention must be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and total
output noise is measured in µV(RMS).
The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a
low frequency component and a high frequency component, which depend strongly on the silicon area and
quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the
current drawn by the internal reference. Increasing the area decreases the chance of fitting the die into a smaller
package. Increasing the current drawn by the internal reference increases the total supply current (GND pin
current). Using an optimized trade-off of the GND pin current and die size, the LP3875-ADJ achieves low noise
performance and low quiescent-current operation.
The total output noise specification for LP3875-ADJ is presented in the Electrical Characteristics. The output
noise density at different frequencies is represented by a curve under Typical Characteristics.
8.2.2.9 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 3.
PD(MAX) = (VIN(MAX) – VOUT)×IOUT (3)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher
voltage drops result in better dynamic (that is, PSRR and transient) performance.
13
LP3875-ADJ
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On the TO-263 (KTT) package, the primary conduction path for heat is through the thermal tab into the PCB. In
this package, the die is connected directly to the thermal pad and the heat generated in the die (junction) has a
direct path through the large thermal tab into the PCB copper area.
In the SOT-223 (NDC) package, the primary conduction path for heat is through the GND Tab (pin 5) into the
PCB. While the die (junction) is connected directly to the GND tab metal, this thermal path is longer and has a
higher thermal resistance value than the TO-263.
To ensure the best thermal performance, place as large of a copper area directly under the thermal tab as is
possible, and connect the thermal tab, through multiple thermal vias, to an internal ground plane with an
appropriate amount of copper PCB area.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 4 or Equation 5:
TJ(MAX) = TA(MAX) + (RθJA × PD(MAX)) (4)
PD(MAX) = (TJ(MAX) – TA(MAX)) / RθJA (5)
Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-
spreading area, and is to be used only as a relative measure of package thermal performance. For a well-
designed thermal layout layout for the TO-263 (KTT) , RθJA is actually the sum of the package junction-to-case
(bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a
heat sink.
8.2.2.10 Estimating Junction Temperature
The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction
temperatures of surface mount devices on a typical PCB board application. These characteristics are not true
thermal resistance values, but rather package specific thermal characteristics that offer practical and relative
means of estimating junction temperatures. These psi metrics are determined to be significantly independent of
copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are
used in accordance with Equation 6 or Equation 7.
TJ(MAX) = TTOP + (ΨJT × PD(MAX))
where
• PD(MAX) is explained in Equation 5
• TTOP is the temperature measured at the center-top of the device package. (6)
TJ(MAX) = TBOARD + (ΨJB × PD(MAX))
where
• PD(MAX) is explained in Equation 5.
• TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the
package edge. (7)
For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal
Metrics; for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics; and for more
information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the Thermal Characteristics of
Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available at www.ti.com.
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
VOUT
100mV/DIV
ILOAD
1A/DIV
TIME (50Ps/DIV)
MAGNITUDE
14
LP3875-ADJ
SNVS247E –SEPTEMBER 2003–REVISED AUGUST 2016
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8.2.3 Application Curves
Unless otherwise specified: TJ= 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VO(NOM) + 1 V,
IL= 10 mA
CIN = COUT = 10 µF, Oscon
Figure 9. Load Transient Response
CIN = COUT = 100 µF, Oscon
Figure 10. Load Transient Response
CIN = COUT = 100 µF, POSCAP
Figure 11. Load Transient Response
CIN = COUT = 10 µF, Tantalum
Figure 12. Load Transient Response
CIN = COUT = 100 µF, Tantalum
Figure 13. Load Transient Response
GND
CFF
R1
R2
SD
Thermal
Vias
COUT
CIN
1
2
3
4
5
IN
GND
OUT
ADJ
SD
VIN
VOUT
GND
15
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9 Power Supply Recommendations
The LP3875-ADJ device is designed to operate from an input supply voltage range of 2.5 V to 7 V. The input
supply must be well regulated and free of spurious noise. To ensure that the LP3875-ADJ output voltage is well
regulated, the input supply must be at least VOUT + 0.5 V, or 2.5 V, whichever is higher. A minimum capacitor
value of 10 μF is required to be within 1 cm of the IN pin.
10 Layout
10.1 Layout Guidelines
Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.
The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the regulator using
traces which do not have other currents flowing in them (Kelvin connect).
The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND
pins. Connect the GND pin to the external circuit ground so that the regulator and its capacitors have a single-
point ground.
Note that stability problems have been seen in applications where vias to an internal ground plane were used at
the ground points of the device and the input and output capacitors. This was caused by varying ground
potentials at these nodes resulting from current flowing through the ground plane. Using a single-point ground
technique for the regulator and its capacitors solved the problem.
Because high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor
leads to these pins so there is no voltage drop in series with the input and output capacitors.
10.2 Layout Examples
Figure 14. Layout Example for DDPAK/TO-263 Package
xxx
xxx
1
2
3
4
5
IN
OUT
ADJ
GND
VIN
VOUT
GND COUT
CFF
R1
R2
CIN
SD
SD
Thermal
Vias
16
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SNVS247E –SEPTEMBER 2003–REVISED AUGUST 2016
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Layout Examples (continued)
Figure 15. Layout Example for SOT-223 Package
17
LP3875-ADJ
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11 Device and Documentation Support
11.1 Related Documentation
For additional information, see the following:
•Semiconductor and IC Package Thermal Metrics
•Using New Thermal Metrics
•Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jul-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP3875EMP-ADJ/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHSB
LP3875EMPX-ADJ/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHSB
LP3875ES-ADJ NRND DDPAK/
TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3875ES
ADJ
LP3875ES-ADJ/NOPB ACTIVE DDPAK/
TO-263 KTT 5 45 Pb-Free (RoHS
Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3875ES
ADJ
LP3875ESX-ADJ/NOPB ACTIVE DDPAK/
TO-263 KTT 5 500 Pb-Free (RoHS
Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3875ES
ADJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jul-2016
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP3875EMP-ADJ/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3
LP3875EMPX-ADJ/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3
LP3875ESX-ADJ/NOPB DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3875EMP-ADJ/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0
LP3875EMPX-ADJ/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0
LP3875ESX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Jul-2016
Pack Materials-Page 2
MECHANICAL DATA
NDC0005A
www.ti.com
MECHANICAL DATA
KTT0005B
www.ti.com
BOTTOM SIDE OF PACKAGE
TS5B (Rev D)
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