2014-2017 Microchip Technology Inc. DS20005339C-page 1
MCP8025/6
Features
• AEC-Q100 Grade 0 Qualified
• Quiescent Current:
- Sleep Mode: 5 µA Typical
- Standby Mode: < 200 µA
• LIN Transceiver Interface (MCP8025):
- Compliant with LIN Bus Specifications 1.3,
2.2 and SAE J2602
- Supports baud rates up to 20K baud
- Internal pull-up resistor and diode
- Protected against ground shorts
- Protected against loss of ground
- Automatic thermal shutdown
- LIN Bus dominant time-out
• Three Half-Bridge Drivers Configured to Drive
External High-Side NMOS and Low-Side NMOS
MOSFETs:
- Independent input control for high-side
NMOS and low-side NMOS MOSFETs
- Peak output current: 0.5A @ 12V
- Shoot-through protection
- Overcurrent and short-circuit protection
• Adjustable Output Buck Regulator (750 mW)
• Fixed Output Linear Regulators:
- 5V@30mA
- 12V @ 30 mA
• Operational Amplifiers:
- one in MCP8025
- three in MCP8026
• Overcurrent Comparator with DAC Reference
• Phase Comparator with Multiplexer (MCP8025)
• Neutral Simulator (MCP8025)
• Level Translators (MCP8026)
• Input Voltage Range: 6V to 40V
• Operational Voltage Range:
-6Vto19V (MCP8025)
- 6V to 28V (MCP8026)
• Buck Regulator Undervoltage Lockout: 4.0V
• Undervoltage Lockout (UVLO): 5.5V (except Buck)
• Overvoltage Lockout (OVLO)
- 20V (MCP8025)
- 32V (MCP8026)
• Transient (100 ms) Voltage Tolerance: 48V
• Extended Temperature Range (TA): -40 to +150°C
• Thermal Shutdown
Applications
• Automotive Fuel, Water, Ventilation Motors
• Home Appliances
• Permanent Magnet Synchronous Motor (PMSM)
Control
• Hobby Aircraft, Boats, Vehicles
Description
The MCP8025/6 devices are 3-phase brushless DC
(BLDC) power modules containing three integrated
half-bridge drivers capable of driving three external
NMOS/NMOS transistor pairs. The three half-bridge
drivers are capable of delivering a peak output current
of 0.5A at 12V for driving high-side and low-side NMOS
MOSFET transistors. The drivers have shoot-through,
overcurrent and short-circuit protection. A Sleep mode
has been added to achieve a typical “key-off” quiescent
current of 5 µA.
The MCP8025 device integrates a comparator, a buck
voltage regulator, two LDO regulators, power
monitoring comparators, an overtemperature sensor, a
LIN transceiver, a zero-crossing detector, a neutral
simulator and an operational amplifier for motor current
monitoring. The phase comparator and multiplexer
allow for hardware commutation detection. The neutral
simulator allows commutation detection without a
neutral tap in the motor. The buck converter is capable
of delivering 750 mW of power for powering a
companion microcontroller. The buck regulator may be
disabled if not used. The on-board 5V and 12V
low-dropout voltage regulators are capable of
delivering 30 mA of current.
The MCP8026 replaces the LIN transceiver, neutral
simulator and zero-crossing detector in MCP8025 with
two level shifters and two additional op amps.
The MCP8025/6 operation is specified over a
temperature range of -40°C to +150°C.
Package options include 40-lead 5x5 QFN and 48-lead
7x7 TQFP with Exposed Pad (EP).
3-Phase Brushless DC (BLDC) Motor Gate Driver
with Power Module, Sleep Mode, and LIN Transceiver
MCP8025/6
DS20005339C-page 2 2014-2017 Microchip Technology Inc.
Package Types – MCP8025
* Includes Exposed Thermal Pad (EP), see Table 3-1.
2
3
4
5
PWM2H 1
FAULTn/TXE
7
8
9
10
6
12
13
14
15
11
17
18
19
20
16
29
28
27
26
30
24
23
22
21
25
39
38
37
36
40
34
33
32
31
35
+12V
LX
VDD
+5V
CAP2
PWM1L
PWM2L
PWM3H
PWM3L
DE2
CAP1
ZC_OUT
MUX2
MUX1
RX
LIN_BUS
LSC
I_SENSE1+
I_SENSE1-
LSB
LSA
PGND
CE
PWM1H
TX
COMP_REF
VBA
ILIMIT_OUT
I_OUT1
PHA
PHB
PHC
HSC
HSB
HSA
VBB
VBC
FB
(41)
EP
5 mm x 5 mm QFN-40
2
3
4
5
PWM1L
7 mm x 7 mm TQFP-48
1
FAULTn/TXE
7
8
9
10
6
13
14
15
17
18
19
20
16
29
28
27
26
30
25
43
42
41
40
44
38
39
+12V
VDD
VDD
+5V
CAP2
PWM2L
PWM3H
PWM3L
DE2
CAP1
ZC_OUT
MUX2
MUX1
RX
LIN_BUS
LSB
I_SENSE1+
I_SENSE1-
LSA
PGND
PGND
NC
PWM1H
TX
COMP_REF
VBA
ILIMIT_OUT
I_OUT1
PHA
PHB
PHC
HSC
HSB
HSA
VBB
VBC
FB
11
LSC
21
22
31
32
33
PGND
45
46
47
48 PWM2H
CE
NC
+
12
3724
23
34
35
36
PGND
PGND
PGND
LX
(49)
EP
2014-2017 Microchip Technology Inc. DS20005339C-page 3
MCP8025/6
Package Types – MCP8026
* Includes Exposed Thermal Pad (EP), see Table 3-2.
22
21
2
3
4
5
PWM2H
5 mm x 5 mm QFN-40
1
ISENSE3-
7
8
9
10
6
12
13
14
15
11
17
18
19
20
16
29
28
27
26
30
24
23
25
39
38
37
36
40
34
33
32
31
35
+12V
VDD
+5V
CAP2
PWM1L
PWM2L
PWM3H
PWM3L
DE2
CAP1
ISENSE2-
IOUT2
ISENSE3+
LV_OUT1
HV_IN1
LSC
I_SENSE1+
I_SENSE1-
LSB
LSA
PGND
CE
PWM1H
IOUT3
ISENSE2+
VBA
ILIMIT_OUT
I_OUT1
PHA
PHB
PHC
HSC
HSB
HSA
VBB
VBC
FB
LX
(41)
EP
2
3
4
5
PWM1L
7 mm x 7 mm TQFP-48
1
7
8
9
10
6
13
14
15
16
18
19
20
21
17
32
31
30
29
33
27
26
28
43
42
41
40
44
38
39
+12V
+5V
CAP1
LX
PWM2L
PWM3H
PWM3L
DE2
FB
LSB
I_SENSE1+
I_SENSE1-
LSA
PGND
PGND
PWM1H
ISENSE2+
VBA
ILIMIT_OUT
I_OUT1
PHA
PHB
PHC
HSC
HSB
HSA
VBB
VBC
CAP2
11
LSC
22
23
34
35
36
VDD
45
46
47
48 PWM2H
ISENSE3-
IOUT2
ISENSE3+
LV_OUT1
HV_IN1
LV_OUT2
IOUT3
ISENSE2-
HV_IN2
CE
+
37
25
24
12
PGND
PGND
PGND
PGND
VDD
(49)
EP
MCP8025/6
DS20005339C-page 4 2014-2017 Microchip Technology Inc.
Functional Block Diagram – MCP8025
LIN
XCVR
CE
FAULTn/TXE
RX
TX
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
LIN_BUS
MUX
+
-
PHA
PHB
PHC
PGND
ZC_OUT COMP_REF
NEUTRAL_SIM
MUX1
MUX2
MOTOR CONTROL UNIT
COMMUNICATION PORT BIAS GENERATOR
+12V
HSA
HSB
HSC
LSA
LSB
LSC
VBA
VBB
VBC
GATE
CONTROL
LOGIC
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
VDD
I_OUT1
+
-
+
-
ILIMIT_OUT
I_SENSE1+
I_SENSE1-
DRIVER
FAULT
VDD
I
I
I/O
I/O
O
I
II
I
IO
PHASE DETECT
ILIMIT_REF
LDO
BUCK SMPS
SUPERVISOR
LDO
CHARGE PUMP
DE2
VDD
+5V
LX
FB
+12V
CAP2
CAP1
SIM Select
2014-2017 Microchip Technology Inc. DS20005339C-page 5
MCP8025/6
Functional Block Diagram – MCP8026
GATE
CONTROL
LOGIC
CE
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
HV_IN1
I_OUT1
+
-
+
-
PHA
PHB
PHC
PGND
ILIMIT_OUT
MOTOR CONTROL UNIT
COMMUNICATION PORT BIAS GENERATOR
+12V
HSA
HSB
HSC
I_SENSE1+
LSA
LSB
LSC
I_SENSE1-
VBA
VBB
VBC
LV_OUT1
LEVEL
TRANSLATOR
VDD
+
-
+
-
I_SENSE2+
I_SENSE2-
I_SENSE3+
I_SENSE3-
I_OUT2
I_OUT3
DRIVER
FAULT
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
LDO
BUCK SMPS
SUPERVISOR
LDO
CHARGE PUMP
DE2
VDD
+5V
LX
FB
+12V
CAP2
CAP1
ILIMIT_REF
HV_IN2
LV_OUT2 O
I
MCP8025/6
DS20005339C-page 6 2014-2017 Microchip Technology Inc.
Typical Application Circuit – MCP8025
2014-2017 Microchip Technology Inc. DS20005339C-page 7
MCP8025/6
Typical Application Circuit – MCP8026
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MCP8025/6
DS20005339C-page 8 2014-2017 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Input Voltage, VDD.............................(GND – 0.3V) to +46.0V
Input Voltage, < 100 ms Transient ...............................+48.0V
Internal Power Dissipation ...........................Internally-Limited
Operating Ambient Temperature Range .......-40°C to +150°C
Operating Junction Temperature (Note 1)....-40°C to +160°C
Transient Junction Temperature (Note 2)................... +170°C
Storage Temperature (Note 1)......................-55°C to +150°C
Digital I/O .......................................................... -0.3V to 5.5V
LV Analog I/O .................................................... -0.3V to 5.5V
VBx ...................................................(GND – 0.3V) to +46.0V
PHx, HSx ..........................................(GND – 5.5V) to +46.0V
ESD and Latch-Up Protection:
VDD, LIN_BUS/HV_IN1  8 kV HBM and 750V CDM
All other pins ..................... 2 kV HBM and 750V CDM
Latch-up protection – all pins .............................. > 100 mA
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
Note 1: The maximum allowable power dissipation
is a function of ambient temperature, the
maximum allowable junction temperature
and the thermal resistance from junction to
air (i.e., TA, TJ, JA). Exceeding the maxi-
mum allowable power dissipation may
cause the device operating junction tem-
perature to exceed the maximum 160°C
rating. Sustained junction temperatures
above 150°C can impact the device reliabil-
ity and ROM data retention.
2: Transient junction temperatures should not
exceed one second in duration. Sustained
junction temperatures above 170°C may
impact the device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
POWER SUPPLY INPUT
Input Operating Voltage VDD 6.0 — 19.0 V Operating (MCP8025)
6.0 — 28.0 Operating (MCP8026)
6.0 — 40.0 Shutdown
4.0 — 32.0 Buck Operating Range
Transient Maximum Voltage VDDmax — — 48.0 V < 100 ms
Input Current (MCP8025) IDD —— — µAV
DD >13V
— 5 15 Sleep mode
— 175 — Standby, CE = 0V, TJ=-45°C
— 175 — Standby, CE = 0V, TJ=+25°C
— 195 300 Standby, CE = 0V, TJ= +150°C
— 940 — Active, CE > VDIG_HI_TH
— 1150 — Active, VDD =6V, T
J= +25°C
Input Current (MCP8026) IDD —— — µAV
DD >13V
— 5 15 Sleep mode
— 120 — Standby, CE = 0V, TJ=-45°C
— 120 — Standby, CE = 0V, TJ=+25°C
— 144 300 Standby, CE = 0V, TJ= +150°C
— 950 — Active, CE > VDIG_HI_TH
— 1090 — Active, VDD =6V, T
J= +25°C
Digital Input/Output DIGITALI/O 0—5.5 V
Digital Open-Drain Drive
Strength
DIGITALIOL —1 —mAVDS <50mV
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
2014-2017 Microchip Technology Inc. DS20005339C-page 9
MCP8025/6
Digital Input Rising Threshold VDIG_HI_TH 1.26 — — V
Digital Input Falling Threshold VDIG_LO_TH — — 0.54 V
Digital Input Hysteresis VDIG_HYS — 500 — mV
Digital Input Current IDIG — 30 100 µA VDIG =3.0V
—0.2 — VDIG =0V
Analog Low-Voltage Input ANALOGVIN 0—5.5 VExcludes LIN and high-voltage
pins
Analog Low-Voltage Output ANALOGVOUT 0—V
OUT5 V Excludes LIN and high-voltage
pins
BIAS GENERATOR
+12V Regulated Charge Pump
Charge Pump Current ICP 20 — — mA VDD =9.0V
Charge Pump Start CPSTART 11.0 11.5 — V VDD falling
Charge Pump Stop CPSTOP — 12.0 12.5 V VDD rising
Charge Pump Frequency
(50% charging/
50% discharging)
CPFSW — 76.80 — kHz VDD =9.0V
—0 — V
DD = 13V (stopped)
Charge Pump Switch
Resistance
CPRDSON —14 — RDSON sum of high side and
low side
Output Voltage VOUT12 —12 — VV
DD 7.5V, CPUMP = 100 nF
IOUT =20mA
—9 — V
DD =5.1V, C
PUMP = 260 nF
IOUT =15mA
Output Voltage Tolerance |TOLVOUT12|— — 4.0 %I
OUT =1mA
Output Current IOUT 30 — — mA Average current
Output Current Limit ILIMIT 40 50 — mA Average current
Output Voltage Temperature
Coefficient
TCVOUT12 — 50 — ppm/°C
Line Regulation |VOUT/
(VOUT xVDD)
|
— 0.1 0.5 %/V 13V < VDD <19V
IOUT =20mA
Load Regulation |VOUT/VOUT|— 0.2 0.5 %I
OUT = 0.1 mA to 15 mA
Power Supply Rejection Ratio PSRR — 60 — dB f = 1 kHz
IOUT =10mA
+5V Linear Regulator
Output Voltage VOUT5 —5 — VV
DD =V
OUT5 +1V
IOUT =1mA
Output Voltage Tolerance |TOLVOUT5|— — 4.0 %
Output Current IOUT 30 — — mA Average current
Output Current Limit ILIMIT 40 50 — mA Average current
Output Voltage Temperature
Coefficient
|TCVOUT5| — 50 — ppm/°C
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
MCP8025/6
DS20005339C-page 10 2014-2017 Microchip Technology Inc.
Line Regulation |VOUT/
(VOUT xVDD)
|
— 0.1 0.5 %/V 6V < VDD <19V
IOUT =20mA
Load Regulation |VOUT/VOUT|— 0.2 0.5 %I
OUT = 0.1 mA to 15 mA
Dropout Voltage VDD –V
OUT5 — 180 350 mV IOUT =20mA
measurement taken when
output voltage drops 2% from
no-load value
Power Supply Rejection Ratio PSRR — 60 — dB f = 1 kHz
IOUT =10mA
Buck Regulator
Feedback Voltage VFB 1.19 1.25 1.31 V
Feedback Voltage Tolerance TOLVFB—— 5.0 %I
FB =1µA
Feedback Voltage Line
Regulation
VFB/VFB)/
VDD|
— 0.1 0.5 %/V VDD = 6V to 28V
Feedback Voltage Load
Regulation
VFB/VFB|—0.1 0.5 %I
OUT = 5 mA to 150 mA
Feedback Input Bias Current IFB -100 — +100 nA Sink/Source
Feedback Voltage
to Shut Down Buck Regulator
VBUCK_DIS 2.5 — 5.5 V VDD >6V
Switching Frequency fSW — 461 — kHz
Duty Cycle Range DCMAX 3—96 %
PMOS Switch On Resistance RDSON —0.6 — TJ= 25°C
PMOS Switch Current Limit IP(MAX) —2.5 — A
Ground Current –
PWM Mode
IGND — 1.5 2.5 mA Switching
Quiescent Current –
PFM Mode
IQ— 150 200 µA IOUT =0mA
Output Voltage Adjust Range VOUT 2.0 — 5.0 V
Output Current IOUT 150 — — mA 5V, VDD – VOUT >0.5V
250 — — 3V, VDD – VOUT > 0.5V
Output Power POUT — 750 — mW P = IOUT xV
OUT
2.5A peak current
Voltage Supervisor
Buck Input Undervoltage Lock-
out – Start-Up
UVLOBK_STRT —4.3 4.5 VV
DD rising
Buck Input Undervoltage Lock-
out – Shutdown
UVLOBK_STOP 3.8 4.0 — V VDD falling
Buck Input Undervoltage
Lockout Hysteresis
UVLOBK_HYS —0.3 — V
5V LDO Undervoltage Fault
Inactive
UVLO5VLDO_INACT —4.5 — VV
OUT5 rising
5V LDO Undervoltage Fault
Active
UVLO5VLDO_ACT —4.0 — VV
OUT5 falling
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
2014-2017 Microchip Technology Inc. DS20005339C-page 11
MCP8025/6
5V LDO Undervoltage Fault
Hysteresis
UVLO5VLDO_HYS —0.5 — V
Input Undervoltage Lockout –
Start-Up
UVLOSTRT — 6.0 6.25 V VDD rising
Input Undervoltage Lockout –
Shutdown
UVLOSTOP 5.1 5.5 — V VDD falling
Input Undervoltage Lockout
Hysteresis
UVLOHYS 0.20 0.45 0.70 V
Input Overvoltage Lockout –
Driver Disabled (MCP8025) DOVLOSTOP — 20.0 20.5 V VDD rising
Input Overvoltage Lockout –
Driver Enabled (MCP8025) DOVLOSTRT 18.75 19.5 — V VDD falling
Input Overvoltage Lockout
Hysteresis (MCP8025) DOVLOHYS 0.15 0.5 0.75 V
Input Overvoltage Lockout
– All Functions Disabled
AOVLOSTOP — 32.0 33.0 V VDD rising
Input Overvoltage Lockout
– All Functions Enabled
AOVLOSTRT 29.0 30.0 — V VDD falling
Input Overvoltage Lockout
Hysteresis
AOVLOHYS 1.0 2.0 3.0 V
Temperature Supervisor
Thermal Warning Temperature TWARN —72 —%T
SD Rising temperature (115°C)
Thermal Warning Hysteresis TWARN — 15 — °C Falling temperature
Thermal Shutdown Temperature TSD 160 170 — °C Rising temperature
Thermal Shutdown Hysteresis TSD — 25 — °C Falling temperature
MOTOR CONTROL UNIT
Output Drivers
PWMH/L Input Pull-Down RPULLDN —47 — k
Output Driver Source Current ISOURCE 0.3 — — A VDD = 12V, HS[A:C], LS[A:C]
Output Driver Sink Current ISINK 0.3 — — A VDD = 12V, HS[A:C], LS[A:C]
Output Driver Source
Resistance
RDSON —17 — IOUT =10mA, V
DD = 12V
HS[A:C], LS[A:C]
Output Driver Sink
Resistance
RDSON —17 — IOUT =10mA, V
DD = 12V
HS[A:C], LS[A:C]
Output Driver Blanking tBLANK 500 — 4000 ns Configurable
Output Driver UVLO Threshold DUVLO 7.2 8.0 — V Config Register 0 bit 3 = 0
Output Driver UVLO Minimum
Duration
tDUVLO tBLANK
+ 700
—t
BLANK
+ 1400
ns Fault latched after tDUVLO
Output Driver HS Drive
Voltage
VHS 8.0 12 13.5 V With respect to the phase pin
-5.5 — — With respect to ground
Output Driver LS Drive Voltage VLS 8.0 12 13.5 V With respect to ground
Output Driver Bootstrap
Voltage
VBOOTSTRAP — — — V With respect to ground
— — 44 Continuous
— — 48 < 100 ms
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
MCP8025/6
DS20005339C-page 12 2014-2017 Microchip Technology Inc.
Output Driver Phase Pin
Voltage
VPHASE — — — V With respect to ground
-5.5 — 44 Continuous
-5.5 — 48 < 100 ms
Output Driver Short-Circuit
Protection Threshold
High Side (VDD –V
PHx)
Low Side (VPHx –P
GND)
DSC_THR — — — V Set In Register CFG0
—0.250 — 00 (Default)
—0.500 — 01
—0.750 — 10
—1.000 — 11
Output Driver Short-Circuit
Detected Propagation Delay
TSC_DLY —— — nsC
LOAD = 1000 pF, VDD =12V
— 430 — Detection after blanking
— 10 — Detection during blanking,
value is delay after blanking
Output Driver OVLO Turn-Off
Delay
TOVLO_DLY 35 —µsDetection synchronized with
internal clock (Note 2)
Power-Up or Sleep to Standby tPOWER — — — ms CE High-Low-High
Transition < 100 µs (Fault
Clearing)
—10 — MCP8025
—5 — MCP8026
Standby to Motor Operational tMOTOR — 5 — µs CE High-Low-High
Transition < 0.9 ms (Fault
Clearing)
— — 5 ms Standby state to Operational
state (MCP8025) (Note 2)
— — 10 ms Standby state to Operational
state (MCP8026) (Note 2)
Fault to Driver Output Turn-Off TFAULT_OFF —— — µsC
LOAD = 1000 pF, VDD =12V
Time after fault occurs
— 1 — UVLO, OCP faults
— 10 — All other faults
CE Low to Driver Output
Turn-Off
TDEL_OFF — 100 250 ns CLOAD = 1000 pF, VDD =12V
Time after CE = Low (Note 2)
CE Low to Standby State tSTANDBY —1 —msTime after CE = Low
SLEEP bit = 0
CE Low to Sleep State tSLEEP — 1 — ms Time after CE = Low
SLEEP bit = 1
CE Fault Clearing Pulse tFAULT_CLR 1 — 900 µs CE High-Low-High Transition
Time (Note 2)
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
2014-2017 Microchip Technology Inc. DS20005339C-page 13
MCP8025/6
Current Sense Amplifier
Input Offset Voltage VOS -3.0 — +3.0 mV VCM =0V
TA= -40°C to +150°C
Input Offset Temperature Drift VOS/TA—±2.0 —µV/°CV
CM =0V
Input Bias Current IB-1 — +1 µA
Common Mode Input Range VCMR -0.3 — 3.5 V
Common Mode Rejection Ratio CMRR — 80 — dB Freq = 1 kHz
IOUT =10µA
Maximum Output Voltage
Swing
VOL, VOH 0.05 — 4.5 V IOUT = 200 µA
Slew Rate SR — ±7 — V/µs Symmetrical
Gain Bandwidth Product GBWP — 10.0 — MHz
Current Comparator Hysteresis CCHYS —10 — mV
Current Comparator Common
Mode Input Range
VCC_CMR 1.0 — 4.5 V
Current Limit DAC
Resolution — 8 — bits
Output Voltage Range VOL, VOH 0.991 — 4.503 V IOUT =1mA
Output Voltage VDAC —— — V
CFG1 Code x
13.77 mV/bit + 0.991V
— 0.991 — Code 00H
— 1.872 — Code 40H
— 4.503 — Code FFH
Input to Output Delay TDELAY —50 — µs
Integral Nonlinearity INL -0.5 — +0.5 %FSR %Full Scale Range (Note 2)
Differential Nonlinearity DNL -50 — +50 %LSB %LSB (Note 2)
ILIMIT_OUT Sink Current
(Open-Drain)
ILOUT —1 —mAV
ILIMIT_OUT 50 mV
ZC Back EMF Sampler Comparator (MCP8025)
Maximum Output Voltage
Swing
ZCVOL,
ZCVOH
0.05 —5.0 VI
OUT =1mA
Reference Input Impedance ZCZREF —83 — k
Input to Output Delay ZCDELAY —— 500 ns VIN_STEP = 500 mV (Note 2)
Voltage Divider RC Time
Constant
ZCTRC — 100 — ns
ZC Output Pull-Up Range ZCRPULLUP 3.3 10 — k
ZC Output Sink Current
(Open-Drain)
ZCIOL —1 —mAV
OUT 50 mV
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
MCP8025/6
DS20005339C-page 14 2014-2017 Microchip Technology Inc.
Back EMF Sampler Phase Multiplexer (MCP8025)
MUX[1:2] Input Pull-Down RPULLDN —47 — k
Transition Time tTRAN — 150 250 ns (Note 2)
Delay from MUX Select to ZC
Out
MUXDELAY — 210 — ns
Phase Filter Capacitors CPHASE — 1.5 — pF MUX input to ground
COMMUNICATION PORTS
Stan dard LIN (MCP8025)
Microcontroller Interface
TX Input Pull-Up Resistor RPUTXD —48 — kPull up to 5V
Bus Interface
LIN Bus High-Level Input
Voltage
VHI 0.6 x
VDD
— — V Recessive state
LIN Bus Low-Level Input
Voltage
VLO ——0.4x
VDD
V Dominant state
LIN Bus Input Hysteresis VHYS ——0.175x
VDD
VV
HI –V
LO
LIN Bus Low-Level Output
Current
IOL 7.3 — — mA VO=0.2xV
DD, VDD =8V
16.5 — — VO=0.2xV
DD, VDD = 18V
30.6 — — VO=0.251xV
DD, VDD =18V
LIN Bus Input Pull-Up Current IPU 5 — 180 µA
LIN Bus Short-Circuit Current
Limit ISC
50 — 200 mA
LIN Bus Low-Level Output
Voltage
VOL ——0.2x
VDD
V
LIN Bus Input Leakage Current
(at receiver during dominant
bus level)
IBUS_PAS_DOM
-1 — — mA Driver OFF
VBUS =0V
VDD =12V
LIN Bus Input Leakage Current
(at receiver during recessive
bus level) IBUS_PAS_REC
— 12 20 µA Driver OFF
VBUS VDD
7V < VBUS <19V
7V < VDD <19V
LIN Bus Input Leakage Current
(disconnected from ground) IBUS_NO_GND
-1 — 1 mA GND = VDD =12V
0V < VBUS <19V
LIN Bus Input Leakage Current
(disconnected from VDD)
IBUS_NO_BAT —— 10 µAV
DD =0V
0V < VBUS <19V
Receiver Center Voltage VBUS_CNT 0.475
xV
DD
0.5 x
VDD
0.525 x
VDD
VV
BUS _CNT =(V
HI –V
LO)/2
LIN Bus Slave Pull-Up
Resistance
RPULLUP 20 30 47 k
LIN Dominant State Timeout tDOM_TOUT —25 — ms
Propagation Delay TRX_PD — 3.0 6.0 µs Propagation delay of receiver
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
2014-2017 Microchip Technology Inc. DS20005339C-page 15
MCP8025/6
Symmetry TRX_SYM -2 — +2 µs Symmetry of receiver
propagation delay rising edge
w.r.t.falling edge
Voltage Level Translato rs (MCP8026)
High-Voltage Input Range VIN 0—V
DD V
Low-Voltage Output Range VOUT 0 — 5.0V V
Input Pull-Up Resistor RPU — 30 — k
High-Level Input Voltage VIH 0.60 — — VDD VDD =15V
Low-Level Input Voltage VIL — — 0.40 VDD VDD =15V
Input Hysteresis VHYS —0.24 — V
DD
Propagation Delay TLV_OUT —3.0 6.0 µs(Note 2)
Maximum Communication Fre-
quency
FMAX — — 20 kHz (Note 2)
Low-Voltage Output Sink
Current (Open-Drain)
IOL —1 —mAV
OUT 50 mV
DE2 Communications
Baud Rate BAUD — 9600 — bps
Power-Up Delay PU_DELAY — 1 — ms Time from rising VDD 6V
to DE2 active
DE2 Sink Current DE2iSINK 1——mAV
DE2 50 mV (Note 2)
DE2 Message Response Time DE2RSP 0—— µsTime from last received Stop
bit to Response Start bit
(Note 2)
DE2 Host Wait Time DE2WAIT 3.125 — — ms Minimum time for host
to wait for response. Three
packets based on 9600 baud
(Note 2)
DE2 Message Receive Timeout DE2RCVTOUT — 5 — ms Time between message bytes
INTERNAL ROM (READ-ONLY MEMORY) DATA RETENTION
Cell High Temperature
Operating Life
HTOL — 1000 — Hours TJ= 150°C (Note 1)
Cell Operating Life — 10 — Years TJ= 85°C
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, TJ= -40°C to +150°C, typical values are for +25°C, VDD =13V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: 1000 hour cumulative maximum for ROM data retention (typical).
2: Limits are by design, not production tested.
MCP8025/6
DS20005339C-page 16 2014-2017 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges (Note 1)
Specified Temperature Range TA-40 +150 °C
Operating Temperature Range TA-40 +150 °C
TJ-40 +160 °C
Storage Temperature Range TA-55 +150 °C (Note 2)
Package Thermal Resistances
Thermal Resistance, 5 mm x 5 mm
40LD-QFN
JA — 37 — °C/W 4-Layer JC51-5 standard board
Natural convection
JC —6.9—
Thermal Resistance, 7 mm x 7 mm
48LD-TQFP with Exposed Pad
JA —30—°C/W
JC —15—
Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum 160°C rating. Sustained junction temperatures above 160°C can impact the device reliability.
2: 1000 hour cumulative maximum for ROM data retention (typical).
ESD, SUSCEPTIBILITY, SURGE AND LATCH-UP TESTING
Parameter Standard and Test Condition Value
Input voltage surges ISO 16750-2 28V for 1 minute,
45V for 0.5 seconds
ESD according to IBEE LIN EMC
– Pins LIN_BUS, VDD (HMM)
Test specification 1.0 following IEC 61000-4.2 ± 8 kV
ESD HBM with 1.5 k/100 pF CEI/IEC 60749-26: 2006
AEC-Q100-002-Ref E
JEDEC JS-001-2012
±2kV
ESD HBM with 1.5 k/100 pF
– Pins LIN_BUS, VDD, HV_IN1 against PGND
CEI/IEC 60749-26: 2006
AEC-Q100-002-Ref E
JEDEC JS-001-2012
±8kV
ESD CDM (Charged Device Model,
field-induced method – replaces
machine-model method)
ESD-STM5.3.1-1999 ± 750V all pins
Latch-Up Susceptibility AEC Q100-004, 150°C > 100 mA
2014-2017 Microchip Technology Inc. DS20005339C-page 17
MCP8025/6
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA= +25°C; Junction Temperature (TJ) is approximated by soaking the device under
test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the
rise in junction temperature over the ambient temperature is not significant.
FIGURE 2-1: LDO Line Regulation vs.
Temperature.
FIGURE 2-2: LDO Load Regulation vs.
Temperature.
FIGURE 2-3: ILIMIT_OUT Low to DE2
Message Delay.
FIGURE 2-4: Bootstrap Voltage @ 92%
Duty Cycle.
FIGURE 2-5: LDO Short-Circuit Current
vs. Input Voltage.
FIGURE 2-6: 5V LDO Dynamic Linestep –
Rising VDD.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-0.010
-0.008
-0.006
-0.004
-0.002
0.000
0.002
0.004
0.006
0.008
0.010
-45-205 305580105130155
Line Regulation (%/V)
Temperature (°C)
VOUT = 5V
VOUT = 12V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
-45 -20 5 30 55 80 105 130 155
Load Regulation (%)
Temperature (°C)
VOUT = 5V
VOUT = 12V
012345678910
Time (µs)
DE2
ILIMIT_OUT
0 5 10 15 20 25 30 35 40 45 50
Volts (V)
Time (µs)
HSA
VBA
20
15
10
5
0
25
20
15
10
5
0
VDD = 6V
100
105
110
115
120
125
130
135
140
145
150
7 1013161922252831
Current (mA)
Voltage (V)
5V LDO
12V LDO
-40
-20
0
20
40
60
80
100
120
140
0
3
6
9
12
15
18
0 20406080100
VOUT (mV)
VIN (V)
Time (µs)
VIN = 14V VIN = 15V
VOUT (AC)
CIN = COUT = 10 µF
IOUT = 20 mA
MCP8025/6
DS20005339C-page 18 2014-2017 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C; Junction Temperature (TJ) is approximated by soaking the device under
test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the
rise in junction temperature over the ambient temperature is not significant.
FIGURE 2-7: 5V LDO Dynamic Linestep –
Falling VDD.
FIGURE 2-8: 12V LDO Dynamic Linestep
– Rising VDD.
FIGURE 2-9: 12V LDO Dynamic Linestep
– Falling VDD.
FIGURE 2-10: 5V LDO Dynamic Loadstep.
FIGURE 2-11: 12V LDO Dynamic
Loadstep.
FIGURE 2-12: 12V LDO Output V oltage vs.
Rising Input Voltage.
-40
-20
0
20
40
60
80
100
120
140
0
3
6
9
12
15
18
0 20406080100
VOUT (mV)
VIN (V)
Time (µs)
VIN = 15V VIN = 14V
VOUT (AC)
CIN = COUT = 10 µF
IOUT = 20 mA
-40
-20
0
20
40
60
80
100
120
140
0
3
6
9
12
15
18
0 20406080100
VOUT (mV)
VIN (V)
Time (µs)
VIN = 14V VIN = 15V
VOUT (AC)
CIN = COUT = 10 µF
IOUT = 20 mA
-40
-20
0
20
40
60
80
10
11
12
13
14
15
16
0 20406080100
VOUT (mV)
VIN (V)
Time (µs)
VIN = 15V
VIN = 14V
VOUT (AC)
CIN = COUT = 10 µF
IOUT = 20 mA
-100
-80
-60
-40
-20
0
20
40
60
80
100
0.0 0.5 1.0 1.5 2.0 2.5
VOUT AC (mV)
Time (ms)
VIN = 14V
VOUT = 5V
CIN = COUT = 10 µF
IOUT = 1 mA to 20 mA Pulse
20 mA
1 mA
-100
-80
-60
-40
-20
0
20
40
60
80
100
0.00.51.01.52.02.5
VOUT AC (mV)
Time (ms)
1 mA
VIN = 14V
VOUT = 12V
CIN = COUT = 10 µF
IOUT = 1 mA to 20 mA Pulse
20 mA
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
6 101418222630
VOUT (V)
VIN (V)
VOUT = 12V
CIN = COUT = 10 µF
IOUT = 20 mA
Charge Pump
Switch Point
2014-2017 Microchip Technology Inc. DS20005339C-page 19
MCP8025/6
Note: Unless otherwise indicated, TA= +25°C; Junction Temperature (TJ) is approximated by soaking the device under
test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the
rise in junction temperature over the ambient temperature is not significant.
FIGURE 2-13: Quiescent Current vs.
Temperature (MCP8025).
FIGURE 2-14: Quiescent Current vs.
Temperature (MCP8026).
FIGURE 2-15: 500 ns PWM Dead Time
Injection.
FIGURE 2-16: Driver RDSON vs.
Temperature.
FIGURE 2-17: Typical Baud Rate
Deviation.
0
200
400
600
800
1000
1200
-45-20 5 305580105130155
Quiescent Current (µA)
Temperature (°C)
CE Low
CE High
0
200
400
600
800
1000
1200
-45-20 5 305580105130155
Quiescent Current (µA)
Temperature (°C)
CE Low
CE High
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Time (µs)
Dead Time
PWMxH
PWMxL
Dead Time
10
12
14
16
18
20
22
24
-45 -20 5 30 55 80 105 130 155
RDSON (Ω)
Temperature(°C)
High-Side
Low-Side
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
-45-20 5 305580105130155
Typical Baud Rate Deviation (%)
Temperature (&
MIN
AVERAGE
MAX
MCP8025/6
DS20005339C-page 20 2014-2017 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Tables 3-1 and 3-2.
TABLE 3-1: MCP8025 – PIN FUNCTION TAB LE
QFN TQFP Symbol I/O Description
2 1 PWM1L I Digital input, phase A low-side control, 47 k pull-down
3 2 PWM1H I Digital input, phase A high-side control, 47 k pull-down
4 3 CE I Digital input, device enable, 47 k pull-down
— 4 NC — No connection
— 5 NC — No connection
5 6 LIN_BUS I/O LIN Bus physical layer
— 7 PGND Power Power 0V reference
6 8 RX O LIN Bus receive data, open-drain
7 9 TX I LIN Bus transmit data
810FAULTn
/TXE I/O LIN transceiver fault and transmit enable
9 11 MUX1 I Digital input Back EMF sampler phase multiplexer control, 47 k pull-down
10 12 MUX2 I Digital input Back EMF sampler phase multiplexer control, 47 k pull-down
11 13 ZC_OUT O Back EMF sampler comparator output, open-drain
12 14 COMP_REF I Back EMF sampler comparator reference
13 15 ILIMIT_OUT O Current limit comparator, MOSFET driver fault output, open-drain
14 16 I_OUT1 O Motor current sense amplifier output
15 17 ISENSE1- I Motor current sense amplifier inverting input
16 18 ISENSE1+ I Motor current sense amplifier noninverting input
17 19,20 PGND Power Power 0V reference
18 21 LSA O Phase A low-side N-channel MOSFET driver, active high
19 22 LSB O Phase B low-side N-channel MOSFET driver, active high
20 23 LSC O Phase C low-side N-channel MOSFET driver, active high
— 24 PGND Power Power 0V reference
21 25 HSC O Phase C high-side N-channel MOSFET driver, active high
22 26 HSB O Phase B high-side N-channel MOSFET driver, active high
23 27 HSA O Phase A high-side N-channel MOSFET driver, active high
24 28 PHC I/O Phase C high-side MOSFET driver reference, Back EMF sense input
25 29 PHB I/O Phase B high-side MOSFET driver reference, Back EMF sense input
26 30 PHA I/O Phase A high-side MOSFET driver reference, Back EMF sense input
27 31 VBC Power Phase C high-side MOSFET driver bias
28 32 VBB Power Phase B high-side MOSFET driver bias
29 33 VBA Power Phase A high-side MOSFET driver bias
30 34 +12V Power Analog circuitry and low-side gate drive bias
— 35, 36 PGND Power Power 0V reference
31 37 LX Power Buck regulator switch node, external inductor connection
32 38, 39 VDD Power Input Supply
33 40 FB I Buck regulator feedback node
34 41 +5V Power Internal circuitry bias
35 42 CAP2 Power Charge pump flying capacitor input
36 43 CAP1 Power Charge pump flying capacitor input
37 44 DE2 O Voltage and temperature supervisor output, open-drain
38 45 PWM3L I Digital input, phase C low-side control, 47 k pull-down
39 46 PWM3H I Digital input, phase C high-side control, 47 k pull-down
40 47 PWM2L I Digital input, phase B low-side control, 47 k pull-down
1 48 PWM2H I Digital input, phase B high-side control, 47 k pull-down
EP EP PGND Power Exposed Pad. Connect to Power 0V reference.
2014-2017 Microchip Technology Inc. DS20005339C-page 21
MCP8025/6
TABLE 3-2: MCP8026 – PIN FUNCTION TAB LE
QFN TQFP Symbol I/O Description
2 1 PWM1L I Digital input, phase A low-side control, 47 k pull-down
3 2 PWM1H I Digital input, phase A high-side control, 47 k pull-down
4 3 CE I Digital input, device enable, 47 k pull-down
— 4 LV_OUT2 O Level Translator 2 logic level translated output, open-drain
— 5 HV_IN2 I Level Translator 2 high-voltage input, 30 k configurable pull up
5 6 HV_IN1 I Level Translator 1 high-voltage input, 30 k configurable pull up
— 7 PGND Power Power 0V reference
6 8 LV_OUT1 O Level Translator 1 logic level translated output, open-drain
7 9 I_OUT3 O Motor phase current sense amplifier 3 output
8 10 ISENSE3- I Motor phase current sense amplifier 3 inverting input
9 11 ISENSE3+ I Motor phase current sense amplifier 3 noninverting input
10 12 I_OUT2 O Motor phase current sense amplifier 2 output
11 13 ISENSE2- I Motor phase current sense amplifier 2 inverting input
12 14 ISENSE2+ I Motor phase current sense amplifier 2 noninverting input
13 15 ILIMIT_OUT O Current limit comparator, MOSFET driver fault output, open-drain
14 16 I_OUT1 O Motor current sense amplifier 1 output
15 17 ISENSE1- I Motor current sense amplifier 1 inverting input
16 18 ISENSE1+ I Motor current sense amplifier 1 noninverting input
17 19,20 PGND Power Power 0V reference
18 21 LSA O Phase A low-side N-Channel MOSFET driver, active high
19 22 LSB O Phase B low-side N-Channel MOSFET driver, active high
20 23 LSC O Phase C low-side N-Channel MOSFET driver, active high
— 24 PGND Power Power 0V reference
21 25 HSC O Phase C high-side N-Channel MOSFET driver, active high
22 26 HSB O Phase B high-side N-Channel MOSFET driver, active high
23 27 HSA O Phase A high-side N-Channel MOSFET driver, active high
24 28 PHC I/O Phase C high-side MOSFET driver reference, Back EMF sense input
25 29 PHB I/O Phase B high-side MOSFET driver reference, Back EMF sense input
26 30 PHA I/O Phase A high-side MOSFET driver reference, Back EMF sense input
27 31 VBC Power Phase C high-side MOSFET driver bias
28 32 VBB Power Phase B high-side MOSFET driver bias
29 33 VBA Power Phase A high-side MOSFET driver bias
30 34 +12V Power Analog circuitry and low-side gate drive bias
— 35,36 PGND Power Power 0V reference
31 37 LX Power Buck regulator switch node, external inductor connection
32 38, 39 VDD Power Input supply
33 40 FB I Buck regulator feedback node
34 41 +5V Power Internal circuitry bias
35 42 CAP2 Power Charge pump flying capacitor input
36 43 CAP1 Power Charge pump flying capacitor input
37 44 DE2 O Voltage and temperature supervisor output, open-drain
38 45 PWM3L I Digital input, phase C low-side control, 47 k pull-down
39 46 PWM3H I Digital input, phase C high-side control, 47 k pull-down
40 47 PWM2L I Digital input, phase B low-side control, 47 k pull-down
1 48 PWM2H I Digital input, phase B high-side control, 47 k pull-down
EP EP PGND Power Exposed Pad. Connect to Power 0V reference.
MCP8025/6
DS20005339C-page 22 2014-2017 Microchip Technology Inc.
3.1 Low-Side PWM Inputs
(PWM1L, PWM2L, PWM3L)
Digital PWM inputs for low-side driver control. Each
input has a 47 k pull-down to ground. The PWM
signals may contain dead-time timing or the system
may use configuration register 2 (CFG2) to set the
dead time.
3.2 High-Side PWM Inputs
(PWM1H, PWM2H, PWM3H)
Digital PWM inputs for high-side driver control. Each
input has a 47 k pull-down to ground. The PWM
signals may contain dead-time timing or the system
may use the configuration register 2 (CFG2) to set the
dead time.
3.3 No Connect (NC)
Reserved. Do not connect.
3.4 Chip Enable Input (CE)
Chip Enable input is used to enable/disable the output
driver and on-board functions. When CE is high, all
device functions are enabled. When CE is low, the
device operates in Standby or Sleep mode. When
Standby mode is active, the current amplifiers and the
12V LDO are disabled. The buck regulator, the DE2
pin, the voltage and temperature sensor functions are
not affected. The 5V LDO is disabled on the MCP8026.
The H-bridge driver outputs are all set to a low state
within 100 ns of CE = 0. The device transitions to
Standby or Sleep mode 1 ms after CE = 0.
The CE pin may be used to clear any hardware faults.
When a fault occurs, the CE input may be used to clear
the fault by setting the pin low and then high again. The
fault is cleared by the rising edge of the CE signal if the
hardware fault is no longer active.
The CE pin is used to enable Sleep mode when the
SLEEP bit in the CFG0 configuration register is set
to ‘1’. CE must be low for a minimum of 1 ms before the
transition to Standby or Sleep mode occurs. This allows
time for CE to be toggled to clear any faults without
going into Sleep mode.
The CE pin is used to awaken the device from the
Sleep mode state. To awaken the device from a Sleep
mode state, the CE pin must be set low for a minimum
of 250 μs. The device will then wake-up with the next
rising edge of the CE pin.
The CE pin has an internal 47 k pull-down.
3.5 Level Translators (HV_IN1,
HV_IN2, LV_OUT1, LV_OUT2)
Unidirectional digital level translators. These pins
translate digital input signal on the HV_INx pin to a
low-level digital output signal on the LV_OUTx pin. The
HV_INx pins have internal 30 k pull ups to VDD that
are controlled by bit PU30K in the CFG0 configuration
register. The PU30K bit is only sampled during CE = 0.
The HV_IN1 pin has higher ESD protection than the
HV_IN2 pin. The higher ESD protection makes the
HV_IN1 pin better suited for connection to external
switches.
LV_OUT1 and LV_OUT2 are open-drain outputs. An
external pull-up resistor to the low-voltage logic supply
is required.
The HV_IN1 pin may be used to awaken the device
from the Sleep mode state. The MCP8026 will awaken
on the rising edge of the pin after detecting a low state
lasting > 250 µs on the pin.
3.6 LIN Transceiver Bus (LIN_BUS)
The bidirectional LIN_BUS interface pin connects to
the LIN Bus network. The LIN_BUS driver is controlled
by the TX pin. The driver is an open-drain output. The
MCP8025 device contains a LIN Bus 30 k pull-up
resistor that may be enabled or disabled by setting the
PU30K bit in the CFG0 configuration register. The pull
up may only be changed while in Standby mode.
During normal operation, the 30 k pull up is always
enabled. In Sleep mode, the 30 k pull up is always
disabled.
The LIN bus may be used to awaken the device from
the Sleep mode state. When a LIN wake-up event is
detected on the LIN_BUS pin, the device will wake-up.
The MCP8025 will awaken on the rising edge of the
bus after detecting a dominant state lasting > 150 µs
on the bus. The LIN Bus master must provide the
dominant state for > 250 µs to meet the LIN 2.2A
specifications.
3.7 Power Ground (PGND),
Exposed Pad (EP)
Device ground. The PCB ground traces should be short
and wide and should form a STAR pattern to the power
source. The Exposed Pad (EP) must be soldered to the
PCB. The PCB area below the EP should be a copper
pour with thermal vias to help transfer heat away from
the device.
3.8 LIN Transceiver Received Data
Output (RX)
The RX output pin follows the state of the LIN_BUS pin.
The data received from the LIN bus is output on the RX
pin for connection to a host MCU.
The RX pin is an open-drain output.
2014-2017 Microchip Technology Inc. DS20005339C-page 23
MCP8025/6
3.9 LIN Transceiver Transmit Data
Input (TX)
The TX input pin is used to send data to the LIN Bus.
The LIN_BUS pin is low (dominant) when TXD is low
and high (recessive) when TXD is high. Data to be
transmitted from a host MCU is sent to the LIN bus via
the TX pin.
3.10 LIN Transceiver Fault/
Transmit Enable (FAULTn/TXE)
Fault Detect output and Transmitter Enable input
bidirectional pin. The FAULTn/TXE pin will be driven
low whenever a LIN fault occurs. There is a
47 kresistor between the internal fault signal and the
FAULTn/TXE pin to allow the pin to be externally driven
high after a fault has occurred. The FAULTn/TXE pin
must be pulsed high to start a transmit. If there is no
fault present when the pin is pulsed, the FAULTn/TXE
pin will latch and be driven high by an internal 47 k
impedance. The FAULTn/TXE pin may then be
monitored for faults.
No external pull-up is needed. The microcontroller pin
controlling the FAULTn/TXE pin must be able to switch
between output and input modes.
3.11 Zero-Crossing Multiplexer Inputs
(MUX1, MUX2)
The MUX1 and MUX2 multiplexer inputs select the
desired phase winding to be used as the zero-crossing
Back EMF phase reference. The output of the
multiplexer connects to one input of the zero-crossing
comparator. The other zero-crossing comparator input
connects to the neutral voltage. The MUX1 and MUX2
inputs must be driven by the host processor
synchronously with the motor commutation.
3.12 Zero-Crossing Detector Output
(ZC_OUT)
The ZC_OUT output pin is the output of the
zero-crossing comparator. When the phase voltage
selected by the multiplexer inputs crosses the neutral
voltage, the zero-crossing detector will change the
output state.
The ZC_OUT output is an open-drain output.
3.13 Neutral Voltage Reference Input
(COMP_REF)
The COMP_REF input pin is used to connect to the
neutral point of a motor if the neutral point is available.
The COMP_REF input may be selected via a
configuration register as the neutral voltage reference
used by the zero-crossing comparator.
3.14 Current Limit and Driver Fault
Output (ILIMIT_OUT)
Dual-purpose output pin. The open-drain output goes
low when the current sensed by current sense
amplifier 1 exceeds the value set by the internal current
reference DAC. The DAC has an offset of 0.991V
(typical) which represents the zero current flow.
The open-drain output will also go low while a fault is
active. Ta b l e 4 - 1 shows the faults that cause the
ILIMIT_OUT pin to go low.
The ILIMIT_OUT pin is able to sink 1 mA of current
while maintaining less than a 50 mV drop across the
output.
3.15 Operational Amplifier Outputs
(I_OUT1, I_OUT2, I_OUT3)
Current sense amplifier outputs. May be used with
feedback resistors to set the current sense gain. The
amplifiers are disabled when CE = 0.
3.16 Operational Amplifier Inputs
(ISENSE1 +/-, ISENSE2 +/-,
ISENSE3 +/-)
Current sense amplifier inverting and noninverting
inputs. Used in conjunction with the I_OUTn pin to set
the current sense gain. The amplifiers are disabled
when CE = 0.
3.17 Low-Side N-Channel MOSFET
Driver Outputs (LSA, LSB, LSC)
Low-side N-channel MOSFET drive signal. Connect to
the gate of the external MOSFETs. A low-impedance
resistor may be used between these pins and the
MOSFET gates to limit current and slew rate.
3.18 High-Side N-Channel MOSFET
Driver Outputs (HSA, HSB, HSC)
High-side N-channel MOSFET drive signal. Connect to
the gate of the external MOSFETs. A low-impedance
resistor may be used between these pins and the
MOSFET gates to limit current and slew rate.
3.19 Driver Phase Inputs
(PHA, PHB, PHC)
Phase signals from motor. These signals provide
high-side N-channel MOSFET driver reference and
Back EMF sense input. The phase signals are also
used with the bootstrap capacitors to provide high-side
gate drive via the VBx inputs.
MCP8025/6
DS20005339C-page 24 2014-2017 Microchip Technology Inc.
3.20 Driver Bootstrap Inputs
(VBA, VBB, VBC)
High-side MOSFET driver bias. Connect these pins
between the bootstrap charge pump diode cathode and
the bootstrap charge pump capacitor. The 12V LDO
output is used to provide 12V at the diode anodes. The
phase signals are connected to the other side of the
bootstrap charge pump capacitors. The bootstrap
capacitors charge to 12V when the phase signals are
pulled low by the low-side drivers. When the low-side
drivers turn off and the high-side drivers turn on, the
phase signal is pulled to VDD, causing the bootstrap
voltage to rise to VDD +12V.
3.21 12V LDO (+12V)
+12-volt Low Dropout (LDO) voltage regulator output.
The +12V LDO may be used to power external devices
such as Hall-effect sensors or amplifiers. The LDO
requires an output capacitor for stability. The positive
side of the output capacitor should be physically
located as close to the +12V pin as is practical. For
most applications, 4.7 µF of capacitance will ensure
stable operation of the LDO circuit. The +12V LDO is
supplied by the internal charge pump when the charge
pump is active. When the charge pump is inactive, the
+12V LDO is supplied by VDD.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high frequency.
3.22 Buck Regulator Switch Output
(LX)
Buck regulator switch node external inductor
connection. Connect this pin to the external inductor
chosen for the buck regulator.
3.23 Power Supply Input (VDD)
Connect VDD to the main supply voltage. This voltage
should be the same as the motor voltage. The driver
overcurrent and overvoltage shutdown features are
relative to the VDD pin. When the VDD voltage is
separate from the motor voltage, the overcurrent and
overvoltage protection features may not be available.
The VDD voltage must not exceed the maximum
operating limits of the device. Connect a bulk capacitor
close to this pin for good loadstep performance and
transient protection.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high frequency.
3.24 Buck Regulator Feedback Input
(FB)
Buck regulator feedback node that is compared to an
internal 1.25V reference voltage. Connect this pin to a
resistor divider that sets the buck regulator output
voltage. Connecting this pin to a separate +2.5V to
+5.5V supply will disable the buck regulator. The FB pin
should not be connected to the +5V LDO to disable the
buck because the +5V LDO starts after the buck in the
internal state machine. The lack of voltage at the FB pin
would cause a buck UVLO fault.
3.25 5V LDO (+5V)
+5-volt Low Dropout (LDO) voltage regulator output.
The +5V LDO may be used to power external devices,
such as Hall-effect sensors or amplifiers. The +5V LDO
is disabled on the MCP8026 when CE = 0. The internal
state machine starts the buck regulator before the +5V
LDO, so the +5V LDO should not be connected to the
buck FB pin to disable the buck regulator. A buck UVLO
fault will occur if the +5V LDO is used to disable the
buck regulator. The LDO requires an output capacitor
for stability. The positive side of the output capacitor
should be physically located as close to the +5V pin as
is practical. For most applications, 4.7 µF of
capacitance will ensure stable operation of the LDO
circuit.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high frequency.
3.26 Charge Pump Flying Capacitor
(CAP1, CAP2)
Charge pump flying capacitor connections. Connect
the charge pump capacitor across these two pins. The
charge pump flying capacitor supplies the power for the
12V LDO when the charge pump is active.
3.27 Communications Port (DE2)
Open-drain communication node. The DE2
communication is a half-duplex, 9600 baud, 8-bit, no
parity communication link. The open-drain DE2 pin
must be pulled high by an external pull-up resistor. The
pin has a minimum drive capability of 1 mA resulting in
a VDE2 of 50 mV when driven low.
2014-2017 Microchip Technology Inc. DS20005339C-page 25
MCP8025/6
4.0 DETAILED DESCRIPTION
4.1 State Diagrams
4.1.1 MCP8025/6 STATE DIAGRAM
FIGURE 4-1: MCP8025/6 State Diagram .
V5 enabled
(standby
MCP8025)
V12
enabled
Buck
enabled
Digital
configuration
FB>1.1V
Start-up
ACTIVE
MTC_FAULT
V12>10.8V
V5>4.5V
and CE=1
Driver over current or
Driver UVLO or
Supply >20V (MCP8025)
ACK
(FAULT)
Sleep
CE = 0
CE timeout
CE = 0
CE = 1 and time<1ms
CE = 0 and time>=1ms and EnableSleep=1
CE = 0 and time>=1ms and EnableSleep=0
CE = 0 and
Supply > 6.0V
BK_ACK
(FAULT)
BK_OFF
Power-on reset
LIN wake-up event (MCP8025) or
HV_IN1 wake-up event (MCP8026)
or CE wake-up event
Supply < 30V
Temp < 145°C
Supply > 6V
Supply < 30V
Temp < 145°C
MCP8025/26
All states
Supply > 32V
Temp>170°C
All states
Supply < 5.5V
FB<1.0V
Supply < 4.0V
Supply > 4.5V
All states
Brown-out
LIN
(standby
MCP8026)
MCP8025
or CE=1
CE=0 and
EnableSleep=1
CE=0 and (EnableSleep=1
or MCP8026)
MCP8025/6
DS20005339C-page 26 2014-2017 Microchip Technology Inc.
4.2 Bias Generator
The internal bias generator controls three voltage rails.
Two fixed-output low-dropout linear regulators, an
adjustable buck switch-mode power converter and an
unregulated charge pump are controlled through the
bias generator. In addition, the bias generator performs
supervisory functions.
4.2.1 +12V LOW-DROPOUT LINEAR
REGULATOR (LDO)
The +12V rail is used for bias of the 3-phase power
MOSFET bridge.
The regulator is capable of supplying 30 mA of external
load current. The regulator has a minimum overcurrent
limit of 40 mA.
When operating at a supply voltage (VDD) that is in the
range of +12V to +12.7V, the +12V charge pump will be
off and the +12V source will be the VDD supply voltage.
The +12V output may be lower than +12V while
operating in the VDD range of +12V to +12.7V due to
the dropout voltage of the regulator.
The low-dropout regulators require an output capacitor
connected from VOUT to GND to stabilize the internal
control loop. A minimum of 4.7 µF ceramic output
capacitance is required for the 12V LDO.
The +12V LDO is disabled when the Chip Enable (CE)
pin is not active.
Table 4-1 shows the faults that will also disable the
+12V LDO.
4.2.2 +5V LOW-DROPOUT LINEAR
REGULATOR (LDO)
The +5V LDO is used for bias of an external
microcontroller, the internal current sense amplifier and
the gate control logic.
The +5V LDO is capable of supplying 30 mA of external
load current. The regulator has a minimum overcurrent
limit of 40 mA. If additional external current is
required, the buck switch-mode power converter
should be utilized.
A minimum of 4.7 µF ceramic output capacitance is
required for the +5V LDO.
The +5V LDO is disabled when the system is in Sleep
mode. The +5V LDO is enabled in the MCP8025 and
disabled in the MCP8026 when in Standby mode.
Table 4-1 shows the faults that will also disable the +5V
LDO.
4.2.3 BUCK SWITCH MODE POWER
SUPPLY (SMPS)
The SMPS is a high-efficiency, fixed-frequency,
step-down DC-DC converter. The SMPS provides all
the active functions for local DC-DC conversion with
fast transient response and accurate regulation.
During normal operation of the buck power stage, Q1 is
repeatedly switched on and off with the ON and
OFF times governed by the control circuit. This
switching action causes a train of pulses at the LX node
which are filtered by the L/C output filter to produce a
DC output voltage, VO. Figure 4-2 depicts the
functional block diagram of the SMPS.
FIGURE 4-2: SMPS Functional Block
Diagram.
The SMPS is designed to operate in Discontinuous
Conduction Mode (DCM) with Voltage mode control
and current-limit protection. The SMPS is capable of
supplying 750 mW of power to an external load at a
fixed switching frequency of 460 kHz with an input
voltage of 6V. The output of the SMPS is power-limited.
For a programmed output voltage of 3V, the SMPS will
be capable of supplying 250 mA to an external load. An
external diode is required between the LX pin and
ground. The diode will be required to handle the
inductor current when the switch is off. The diode is
external to the device to reduce substrate currents and
power dissipation caused by the switcher. The external
diode carries the current during the switch-off time,
eliminating the current path back through the device.
OUTPUT
CONTROL
LOGIC
VIN
+
-
LX
FB
+
-
Q1
CURRENT_REF
VDD-12V
BANDGAP
REFERENCE
+
-
2014-2017 Microchip Technology Inc. DS20005339C-page 27
MCP8025/6
The SMPS enters Pulse Frequency Modulation (PFM)
mode at light loads, improving efficiency at the expense
of higher output voltage ripple. The PFM circuitry
provides a means to disable the SMPS as well. If the
SMPS is not utilized in the application, connecting the
feedback pin (FB) to an external supply (2.5V to 5.5V)
will force the SMPS to a shutdown state.
The maximum inductor value for operation in
Discontinuous Conduction mode can be determined by
using Equation 4-1.
EQUATION 4-1: LMAX SIMPLIFIED
Using the LMAX inductor value calculated using
Equation 4-1 will ensure Discontinuous Conduction
mode operation for output load currents below the
critical current level, IO(CRIT). For example, with an
output voltage of +5V, a standard inductor value of
4.7 µH will ensure Discontinuous Conduction mode
operation with an input voltage of 6V, a switching
frequency of 468 kHz and a critical load current of
150 mA.
The output voltage is set by using a resistor divider
network. The resistor divider is connected between the
inductor output and ground. The divider common point
is connected to the FB pin which is then compared to
an internal 1.25V reference voltage.
The buck regulator will set the BIOCPW bit in the
STAT0 register and send a STATUS_0 message to the
host whenever the input switching current exceeds
2.5A peak (typical). The bit will be cleared when the
peak input switching current drops back below the 2.5A
(typical) limit. This is a warning bit only, no action is
taken to shut down the buck operation. The overcurrent
limit will shorten the buck duty cycle and therefore limit
the maximum power out of the buck regulator.
The buck regulator will set the BUVLOW bit in the
STAT0 register and send a STATUS_0 message to the
host whenever the output voltage drops below 90% of
the rated output voltage. The bit will be cleared when
the output voltage returns to 94% of the rated value.
If the buck regulator output voltage falls below 80% of
rated output voltage, the device will shut down with a
Buck Undervoltage Lockout Fault. The BUVLOF bit in
the STAT0 register will be set and a STATUS_0
message will be sent to the host. The ILIMIT_OUT
signal will transition low to indicate the fault.
The Voltage Supervisor is designed to shut down the
buck regulator when VDD rises above AOVLOSTOP
.
When shutting down the buck regulator is not
desirable, the user should add a voltage suppression
device to the VDD input in order to prevent VDD from
rising above AOVLOSTOP
.
The Voltage Supervisor is also designed to shut down
the buck regulator when VDD falls below
UVLOBK_STOP
.
The device will set the BUVLOF bit in the STAT0
register and send a STATUS_0 message to the host
when the buck input voltage drops below
UVLOBK_STOP
.
Table 4-1 shows the faults that will disable the buck
regulator.
4.2.4 CHARGE PUMP
An unregulated charge pump is utilized to boost the
input to the +12V LDO during low input conditions.
When the input bias to the device (VDD) drops below
CPSTART
, the charge pump is activated. When
activated, 2 x VDD is presented to the input of the
+12V LDO, which maintains a minimum of +10V at its
output.
The typical charge pump flying capacitor is a 0.1 µF to
1.0 µF ceramic capacitor.
4.2.5 SUPERVISOR
The bias generator incorporates a voltage supervisor
and a temperature supervisor.
4.2.5.1 Brownout – Configuration Lost
When the device first powers up or when VDD drops
below 3.8V, the brown-out reset warning flag bit
(BORW) in the STAT1 register will be set. The bit is only
a warning indicating that the contents of the configura-
tion registers may have been compromised by a low
supply voltage condition. The host processor should
send new configuration information to the device.
4.2.5.2 Voltage Supervisor
The voltage supervisor protects the device, the
external power MOSFETs and the external
microcontroller from damage caused by overvoltage or
undervoltage of the input supply, VDD.
In the event of an undervoltage condition
(VDD < +5.5V) or an overvoltage condition of the
MCP8025 device (VDD > +20V), the motor drivers are
switched off. The bias generator, the communication
port and the remainder of the motor control unit remain
active. The failure state is flagged on the DE2 pin with
a status message. In extreme overvoltage conditions
(VDD > +32V), all functions are turned off.
In the event of a severe undervoltage condition
(VDD < +4.0V), the buck regulator will be disabled. If
the set point of the buck regulator output voltage is
above the buck undervoltage lockout value, the buck
output voltage will decrease as VDD decreases.
LMAX
VO1VO
VIN
--------–


T
2I
OCRIT
----------------------------------------------
MCP8025/6
DS20005339C-page 28 2014-2017 Microchip Technology Inc.
4.2.5.3 Temperature Supervisor
An integrated temperature sensor self-protects the
device circuitry. If the temperature rises above the
overtemperature shutdown threshold, all functions are
turned off. Active operation resumes when the
temperature has cooled down below a set hysteresis
value and the fault has been cleared by toggling CE.
It is desirable to signal the microcontroller with a
warning message before the overtemperature
threshold is reached. When the Thermal Warning
Temperature set point is exceeded, a warning message
will be sent to the host microcontroller. The
microcontroller should take appropriate actions to
reduce the temperature rise. The method to signal the
microcontroller is through the DE2 pin.
4.2.5.4 Internal Function Block Status
Table 4-1 shows the effects of the CE pin, the faults and
the SLEEP bit upon the functional status of the internal
blocks of the MCP8025/6.
TABLE 4-1: INTERNAL FUNCTION BLOCK STATUS
System State Fault Conditions
5V LDO
Buck
LIN, HV_IN1, HV_IN2
12V LDO
Motor Drivers
DE2
Internal
UVLO, OVLO, OTP
Sleep CE = 0, SLEEP = 1——W——— —
Standby
(MCP8025) CE = 0
SLEEP = 0AAR——A A
Standby
(MCP8026) CE = 0
SLEEP = 0—A A——A A
Operating CE = 1, ILIMIT_OUT =1AAAAAA A
Faults
CE = 1
ILIMIT_OUT =0
Driver OTP TJ> 160°C — — — — — A A
VDD UVLO VIN 5.5V — A ——— A A
Buck Input UVLO VIN 4V ————— A A
Buck Output Brownout VBUCK < 80% (Brownout) — A — — — A A
5V LDO UVLO VOUT5 4V A A R A — A A
Driver OVLO (MCP8025) VIN 20V AAAA—A A
System OVLO VIN 32V ————— A A
MOSFET UVLO VHS[A:C] <8V, V
LS[A:C] <8V A A A A — A A
MOSFET OCP VDrain-Source > EXTOC<1:0> setting A A A A — A A
Warnings
CE = 1
ILIMIT_OUT =1
Buck OCP IBUCK Input>2.5A Peak AAAAAA A
Buck Output
Undervoltage
VBUCK <90% AAAAAA A
Driver Temperature TJ>72% T
SD_MIN
(115°C for 160°C Driver OTP)
AAAAAA A
Config Lost (BORW) Set at initial power-up
or when VDD <UVLO
BK_STOP
AAAAAA A
Legend: “A” = ACTIVE (ON), “—” = INACTIVE (OFF), “W” = WAKEUP (from Sleep), “R” = RECEIVER ONLY
OCP = Overcurrent Protection
OTP = Overtemperature Protection
UVLO = Undervoltage Lockout
OVLO = Overvoltage Lockout
2014-2017 Microchip Technology Inc. DS20005339C-page 29
MCP8025/6
4.3 Motor Control Unit
The motor control unit is comprised of the following:
• External drive for a 3-phase bridge with
NMOS/NMOS MOSFET pairs
• Back EMF sampler with phase multiplexer and
neutral simulator (MCP8025)
• Motor current sense amplifier and comparator
• Two additional current sense amplifiers
(MCP8026)
4.3.1 MOTOR CURRENT SENSE
CIRCUITRY
The internal motor current sense circuitry consists of an
operational amplifier and a comparator. The amplifier
output is presented to the inverting comparator input
and as an output to the microcontroller. The
noninverting comparator input is connected to an
internally programmable 8-bit DAC. A selectable motor
current limit threshold may be set with a SET_ILIMIT
message from the host to the MCP8025/6 via the DE2
communication link. The DACREF<7:0> bits in the
CFG1 register contain the DAC current reference
value. The dual-purpose ILIMIT_OUT pin handles the
current limit output as well as system fault outputs. The
8-bit DAC is powered by the 5V supply. The DAC
output voltage ranges from 0.991V to 4.503V.
The DAC
has a bit value of (4.503V – 0.991V)/(28–1)=13.77mV/bit
.
A DAC input of 00H yields a DAC output voltage of
0.991V. The default power-up DAC value is 40H
(1.872V). The DAC uses a 100 kHz filter. Input code
to output voltage delay is approximately five time
constants 50 µs. The desired current sense gain is
established with an external resistor network.
The comparator output may be employed as a current
limit. Alternatively, the current sense output can be
employed in a chop-chop PWM speed loop for any
situations where the motor is being accelerated, either
positively or negatively. An analog chop-chop speed
loop can be implemented by hysteretic control or fixed
off-time of the motor current. This makes for a very
robust controller, as the motor current is always in
instantaneous control.
A sense resistor in series with the bridge ground return
provides a current signal for both feedback and current
limiting. This resistor should be noninductive to
minimize ringing from high di/dt. Any inductance in the
power circuit represents potential problems in the form
of additional voltage stress and ringing, as well as
increasing switching times. While impractical to
eliminate, careful layout and bypassing will minimize
these effects. The output stage should be as compact
as heat sinking will allow, with wide, short traces
carrying all pulsed currents. Each half-bridge should be
separately bypassed with a low ESR/ESL capacitor,
decoupling it from the rest of the circuit. Some layouts
will allow the input filter capacitor to be split into three
smaller values and serve double duty as the half-bridge
bypass capacitors.
The current sense resistor is chosen to establish the
peak current limit threshold, which is typically set 20%
higher than the maximum current command level to
provide overcurrent protection during abnormal
conditions. Under normal circumstances with a
properly compensated current loop, peak current limit
will not be exercised.
The current sense operational amplifier is disabled
when CE = 0.
4.3.2 BACK EMF SAMPLER WITH PHASE
MULTIPLEXER AND NEUTRAL
SIMULATOR (MCP8025)
The commutation loop of a BLDC motor control is a
phase lock loop (PLL) that locks to the rotor’s position.
Note that this inner loop does not attempt to modify the
position of the rotor, but modifies the commutation
times to match whatever position the rotor has. An
outer speed loop changes the rotor velocity, and the
commutation loop locks to the rotor’s position to
commutate the phases at the correct times.
The Back EMF sensor consists of the motor, a
Back EMF sampler, a phase multiplexer and a neutral
simulator.
The Back EMF sampler takes the motor phase
voltages and calculates the neutral point of the motor
by using Equation 4-2.
EQUATION 4-2: NEUTRAL POINT
Note: The motor current limit comparator output
is internally ‘OR’d with the DRIVER
FAULT output of the driver logic block.
The microcontroller should monitor the
comparator output and take appropriate
actions. The motor current limit
comparator circuitry does not disable the
motor drivers when an overcurrent
situation occurs. Only one current limit
comparator is provided. The MCP8026
provides three current sense amplifiers
which can be used for implementation of
advanced control algorithms, such as
Field-Oriented Control (FOC).
Note: With a chop-chop control, motor current
always flows through the sense resistor.
When the PWM is off, however, the
flyback diodes or synchronous rectifiers
conduct, causing the current to reverse
polarity through the sense resistor.
NEUTRAL
A
B
C++
3
----------------------------------------=
MCP8025/6
DS20005339C-page 30 2014-2017 Microchip Technology Inc.
This allows the microcontroller to compare the
Back EMF signal to the motor’s neutral point without
the need to bring out an extra wire on a WYE wound
motor. For DELTA wound motors, there is no physical
neutral to bring out, so this reference point must be
calculated in any case.
The Back EMF sampler measures the motor phase that
is not driven, i.e. if LSA and HSB are ON, then phase A
is driven low, phase B is driven high and phase C is
sampled. The sampled phase provides a Back EMF
signal that is compared against the neutral of the motor.
The sampler is controlled by the microcontroller via the
MUX1 and MUX2 input signals.
When the BEMF signal crosses the neutral point, the
zero-crossing detector will switch the ZC_OUT signal.
The host controller may use this signal as a
30 degrees-before-commutation reference point. The
host controller must commutate the system after
30 degrees of electrical rotation have occurred.
Different motor control scenarios may increase or
decrease the commutation point by a few degrees.
Internal filtering capacitors are connected after the
phase voltage dividers to help eliminate transients
during the zero-crossing detection.
The neutral simulator may be disabled when access to
the motor winding neutral point is available. When
disabling the neutral simulator, the motor neutral is
connected directly to the COMP_REF pin. The actual
motor neutral is then used for zero-crossing detection.
The neutral simulator may be disabled via DE2
communications.
4.3.3 MOTOR CONTROL
The commutation loop of a BLDC motor control is a
phase lock loop (PLL) which locks to the rotor’s
position. Note that this inner loop does not attempt to
modify the position of the rotor, but modifies the
commutation times to match whatever position the
rotor has. An outer speed loop changes the rotor
velocity and the commutation loop locks to the rotor’s
position to commutate the phases at the correct times.
4.3.3.1 Sensorless Motor Control
Many control algorithms can be implemented with the
MCP8025/6 in conjunction with a microcontroller. The
following discussion provides a starting point for
implementing the MCP8025 or MCP8026 in a
sensorless control application of a 3-phase motor. The
motor is driven by energizing two windings at a time
and sequencing the windings in a
six-step-per-electrical-revolution method. This method
leaves one winding unenergized at all times and the
voltage (Back EMF or BEMF) on that unenergized
winding can be monitored to determine the rotor
position.
4.3.3.2 Start-Up Sequence
When the motor being driven is at rest, the BEMF
voltage is equal to zero. The motor needs to be rotating
for the BEMF sensor to lock onto the rotor position and
commutate the motor. The recommended start-up
sequence is to bring the rotor from rest up to a speed
fast enough to allow BEMF sensing. Motor operation is
comprised of five modes: Disabled mode, Bootstrap
mode, Lock or Align mode, Ramp mode and Run
mode. Refer to the commutation state machine in
Table 4-3. The order in which the microcontroller steps
through the commutation state machine determines the
direction the motor rotates.
Disabled Mode (CE = 0)
When the driver is disabled (CE = 0), all of the
MOSFET driver outputs are set low.
Bootstrap Mode
The high-side driver obtains the high-side biasing
voltage from the +12V LDO, the bootstrap diode and
the bootstrap capacitor. The bootstrap capacitors must
first be charged before the high-side drives may be
used. The bootstrap capacitors are all charged by
activating all three low-side drivers. The active low-side
drivers pull their respective phase nodes low, charging
the bootstrap capacitors to the +12V LDO voltage. The
three low-side drivers should be active for at least
1.2 ms per 1 µF of bootstrap capacitance. This
assumes a +12V voltage change and 30 mA (10 mA
per phase) of current coming from the +12V LDO.
Lock Mode
Before the motor can be started, the rotor should be in
a known position. In Lock mode, the microcontroller
drives phase B low and phases A and C high. This
aligns the rotor 30 electrical degrees before the center
of the first commutation state. Lock mode must last
long enough to allow the motor and its load to settle into
this position.
TABLE 4-2: PHASE SAMPLER
MUX Phase Sampled
MUX2 MUX1
0 0 PHASE A
0 1 PHASE B
1 0 PHASE C
1 1 PHASE C
2014-2017 Microchip Technology Inc. DS20005339C-page 31
MCP8025/6
Ramp Mode
At the end of the Lock mode, Ramp mode is entered. In
Ramp mode, the microcontroller steps through the
commutation state machine, increasing linearly, until a
minimum speed is reached. Ramp mode is an
open-loop commutation. No knowledge of the rotor
position is used.
Run Mode
At the end of Ramp mode, Run mode is entered. In Run
mode, the Back EMF sensor is enabled and
commutation is now under the control of the phase lock
loop. Motor speed can be regulated by an outer speed
control loop.
4.3.3.3 PWM Speed Control
The inner commutation loop is a phase-lock loop,
which locks to the rotor’s position. This inner loop does
not attempt to modify the position of the rotor, but
modifies the commutation times to match whatever
position the rotor has. The outer speed loop changes
the rotor velocity and the inner commutation loop locks
to the rotor’s position to commutate the phase at the
correct times.
The outer speed loop pulse-width modulates the motor
drive inverter to produce the desired wave shape and
voltage at the motor. The inductance of the motor then
integrates this pulse-width modulation (PWM) pattern
to produce the desired average current, thus controlling
the desired torque and speed of the motor. For a
trapezoidal BLDC motor drive with six-step
commutation, the PWM is used to generate the
average voltage to produce the desired motor current
and motor speed.
There are two basic methods to pulse-width modulate
the inverter switches. The first method returns the
reactive energy in the motor inductance to the source
by reversing the voltage on the motor winding during
the current decay period. This method is referred to as
fast decay or chop-chop. The second method
circulates the reactive current in the motor with minimal
voltage applied to the inductance. This method is
referred to as slow decay or chop-coast.
The preferred control method employs a chop-chop
PWM for any situation where the motor is being
accelerated, either positively or negatively. For
improved efficiency, chop-coast PWM is employed
during steady-state conditions. The chop-chop speed
loop is implemented by hysteretic control, fixed off-time
control or average current mode control of the motor
current. This makes for a very robust controller, as the
motor current is always in instantaneous control.
The motor speed presented to the chop-chop loop is
reduced by approximately 9%. A fixed-frequency PWM
that only modulates the high-side switches implements
the chop-coast loop. The chop-coast loop is presented
with the full motor speed, so, if it is able to control the
speed, the chop-chop loop will never be satisfied and
will remain saturated. The chop-chop remains able to
assume full control if the motor torque is exceeded,
either through a load change or a change in speed that
produces acceleration torque. The chop-coast loop will
remain saturated, with the chop-chop loop in full
control, during start-up and acceleration to full speed.
The bandwidth of the chop-coast loop is set to be
slower than the chop-chop loop so that any transients
will be handled by the chop-chop loop and the
chop-coast loop will only be active in steady-state
operation.
TABLE 4-3: COMMUTATION STATE MACHINE
State Outputs BEMF
Phase
HSA HSB HSC LSA LSB LSC
CE = 0OFF OFF OFF OFF OFF OFF N/A
BOOTSTRAP OFF OFF OFF ON ON ON N/A
LOCK ON OFF ON OFF ON OFF N/A
1 ON OFF OFF OFF OFF ON Phase B
2 OFF ON OFF OFF OFF ON Phase A
3 OFF ON OFF ON OFF OFF Phase C
4 OFF OFF ON ON OFF OFF Phase B
5 OFF OFF ON OFF ON OFF Phase A
6 ON OFF OFF OFF ON OFF Phase C
MCP8025/6
DS20005339C-page 32 2014-2017 Microchip Technology Inc.
4.3.4 EXTERNAL DRIVE FOR A 3-PHASE
BRIDGE WITH NMOS/NMOS
MOSFET PAIRS
Each motor phase is driven with external
NMOS/NMOS MOSFET pairs. These are controlled by
a low-side and a high-side gate driver. The gate drivers
are controlled directly by the digital input pins
PWM[1:3]H/L. A logic high turns the associated gate
driver ON and a logic low turns the associated gate
driver OFF. The PWM[1:3]H/L digital inputs are
equipped with internal pull-down resistors.
The low-side gate drivers are biased by the +12V LDO
output, referenced to ground. The high-side gate
drivers are a floating drive biased by a bootstrap
capacitor circuit. The bootstrap capacitor is charged by
the +12V LDO whenever the accompanying low-side
MOSFET is turned on.
The high-side and low-side driver outputs all go to a low
state whenever there is a fault or when CE = 0,
regardless of the PWM[1:3]H/L inputs.
4.3.4.1 MOSFET Driver External Protection
Features
Each driver is equipped with Undervoltage Lockout
(UVLO) and short-circuit protection features.
4.3.4.1.1 MOSFET Driver Undervoltage Lockout
(UVLO)
The MOSFET UVLO fault detection monitors the
available voltage used to drive the external MOSFET
gates. The fault detection is only active while the driver
is actively driving the external MOSFET gate. Anytime
the driver bias voltage is below the Driver Undervoltage
Lockout (DUVLO) threshold for a period longer than the
one specified by the tDUVLO parameter, the driver will
not turn on when commanded ON. A driver fault will be
indicated to the host microcontroller on the
ILIMIT_OUT open-drain output pin and also via a DE2
communication STATUS_1 message. This is a latched
fault. Clearing the fault requires either removal of
device power or disabling and re-enabling the device
via the device enable input (CE). The EXTUVLO bit in
the CFG0 register is used to enable or disable the
Driver Undervoltage Lockout feature. This protection
feature prevents the external MOSFETs from being
controlled with a gate voltage not suitable to fully
enhance the device.
4.3.4.1.2 External MOSFET Short-Circuit Current
Short-circuit protection monitors the voltage across the
external MOSFETs during an ON condition. The
high-side driver voltage is measured from VDD to
PH[1:3]. The low-side driver voltage is measured from
PH[1:3] to PGND. If the voltage rises above a
user-configurable threshold after the external MOSFET
gate voltage has been driven high, all drivers will be
turned OFF. A driver fault will be indicated to the host
microcontroller on the open-drain ILIMIT_OUT output
pin and also via a DE2 communication STATUS_1
message. This is a latched fault. Clearing the fault
requires either removal of device power or disabling
and re-enabling the device via the device enable input
(CE). This protection feature helps detect internal
motor failures such as winding to case shorts.
The short-circuit voltage may be set via a DE2
SET_CFG_0 message. The EXTOC<1:0> bits in the
CFG0 register are used to select the voltage level for
the short-circuit comparison. If the voltage across the
MOSFET drain-source terminals exceeds the selected
voltage level when the MOSFET is active, a fault will be
triggered. The selectable voltage levels are 250 mV,
500 mV, 750 mV and 1000 mV. The EXTSC bit in the
CFG0 register is used to enable or disable the
MOSFET driver short-circuit detection.
4.3.4.1.3 Fault Pin Output (ILIMIT_OUT)
The dual-purpose ILIMIT_OUT pin is used as a fault
indicator and as an overcurrent indicator when used
with the internal DAC. The pin is capable of sinking a
minimum of 1 mA of current while maintaining less than
50 mV of voltage across the output. An external pull-up
resistor to the logic supply is required.
The open-drain ILIMIT_OUT pin transitions low when a
fault occurs. Table 4-4 lists the faults that activate the
ILIMIT_OUT signal. Warnings do not activate the
ILIMIT_OUT signal. Table 4 -5 lists the warnings.
Note: The driver short-circuit protection is
dependent on application parameters. A
configuration message is provided for a
set number of threshold levels. The
MOSFET Driver UVLO and short-circuit
protection features have the option to be
disabled.
2014-2017 Microchip Technology Inc. DS20005339C-page 33
MCP8025/6
4.3.4.2 Gate Control Logic
The gate control logic provides level shifting of the
digital inputs, polarity control and cross conduction
protection.
4.3.4.2.1 Cross Conduction Protection
Logic prevents switching on one power MOSFET while
the opposite one in the same half-bridge is already
switched on. If both MOSFETs in the same half-bridge
are commanded ON simultaneously by the digital
inputs, both will be turned off.
4.3.4.2.2 Programmable Dead Time
The gate control logic employs a break-before-make
dead-time delay that is programmable. A configuration
message is provided to configure the driver dead time.
The programmable dead times range from 250 ns to
2000 ns (default) in 250 ns increments. The dead time
allows the PWM inputs to be direct inversions of each
other and still allow proper motor operation. The dead
time internally modifies the PWMH/L gate drive timing
to prevent cross conduction. The DRVDT<2:0> bits in
the CFG2 register are used to set the dead time value.
4.3.4.2.3 Programmable Blanking Time
A configuration message is provided to configure the
driver current limit blanking time. The blanking time
allows the system to ignore any current spikes that may
occur when switching the driver outputs. The allowable
blanking times are 500 ns, 1 µs, 2 µs and 4 µs
(default). The blanking time will start after the
dead-time circuitry has timed out. The DRVBT<1:0>
bits in the CFG2 register are used to set the blanking
time value.
The blanking time affects the driver undervoltage
lockout. The driver undervoltage lockout latches the
external MOSFET undervoltage lockout fault if the
undervoltage condition lasts longer than the time
specified by the tDUVLO parameter. The tDUVLO
parameter takes into account the blanking time if
blanking is in progress.
4.4 Chip Enable (CE)
The Chip Enable (CE) pin allows the device to be
disabled by external control. The Chip Enable pin has
four modes of operation.
4.4.1 FAULT CLEARING STATE
The CE pin is used to clear any faults and re-enable the
driver. After toggling the CE pin low to high, the system
requires a minimum time period to re-enable and start
up all the driver blocks. The start-up time is
approximately 35 μs. The maximum pulse time for the
high-low-high transition to clear faults should be less
than 1 ms. If the high-low-high transition is longer than
1 ms, the device will start up from the Standby state.
Any fault status bits that are set will be cleared by the
low-to-high transition of the CE pin if, and only if, the
fault condition has ceased to exist. If the fault condition
still exists, the active fault status bit will remain active.
No additional fault messages will be sent for a fault that
remains active.
4.4.2 WAKE FROM SLEEP MODE
The CE pin is also used to awaken the device from the
Sleep mode state. To wake the device from a Sleep
mode state, the CE pin must be set low for a minimum
of 250 μs. The device will then wake-up with the next
rising edge of the CE pin.
The LIN bus may be used to wake the device from the
Sleep mode state. When a LIN wake-up event is
detected on the LIN_BUS pin, the device will wake-up.
The MCP8025 will wake-up on the rising edge of the
bus after detecting a dominate state lasting > 150 µs
on the bus. The LIN Bus master must provide the
dominate state for > 250 µs to meet the LIN 2.2A
specifications.
TABLE 4-4: ILIMIT_OUT FAULTS
Fault DE2 Register
Overtemperature 0x85 0x02
Device Input Undervoltage 0x85 0x04
Driver Input Overvoltage 0x85 0x08
Device Input Overvoltage 0x85 0x10
Buck Regulator Output Undervoltage 0x85 0x80
External MOSFET Undervoltage
Lockout
0x86 0x04
External MOSFET Overcurrent
Detection
0x86 0x08
5V LDO Undervoltage Lockout 0x86 0x20
TABLE 4-5: WARNINGS
Fault DE2 Register
Temperature Warning 0x85 0x01
Buck Regulator Overcurrent 0x85 0x20
Buck Regulator Undervoltage 0x85 0x40
Brownout – Configuration Lost 0x86 0x10
MCP8025/6
DS20005339C-page 34 2014-2017 Microchip Technology Inc.
The HV_IN1 pin may be used to wake the device from
the Sleep mode state. The MCP8026 will wake-up on
the rising edge of the pin after detecting a low state
lasting > 250 µs on the pin.
4.4.3 STANDBY STATE
Standby state is entered when the CE pin goes low for
longer than 1 ms and the Sleep configuration bit is
inactive. When Standby mode is entered, the following
subsystems are disabled:
• high-side gate drives (HSA, HSB, HSC), forced
low
• low-side gate drives (LSA, LSB, LSC), forced low
• +12V LDO
•+5V LDO (MCP8026)
•the 30k pull-up resistor connected to the level
translator is switched out of the circuit to minimize
current consumption (configurable) (MCP8026)
•the 30k pull-up resistor connected to the LIN
Bus is switched out of the circuit to minimize
current consumption (configurable) (MCP8025)
The buck regulator stays enabled. The DE2
communication port remains active but the port may
only respond to commands. When CE is inactive, the
DE2 port is prevented from initiating communications in
order to conserve power.
The total current consumption of the device when CE is
inactive (device disabled) stays within the Standby
mode input quiescent current limits specified in the
AC/DC Characteristics table.
4.4.4 SLEEP MODE
Sleep mode is entered when both a SLEEP command
is sent to the device via DE2 communication and the
CE pin is low. The two conditions may occur in any
order. The transition to Sleep mode occurs after the last
of the two conditions occurs and the tSLEEP delay time
has elapsed. The SLEEP bit in the CFG0 configuration
register indicates when the device should transition to
a low-power mode. The device will operate normally
until the CE pin is transitioned low by an external
device. At that point in time, the SLEEP bit value
determines whether the device transitions to Standby
mode or low-power Sleep mode. The quiescent current
during Sleep mode will typically be 5 μA. When Sleep
mode is activated, most functions will be shut off,
including the buck regulator. Only the power-on reset
monitor, the voltage translators and the minimal state
machine will remain active to detect a wake-up event.
This indicates that the host processor will be shut down
if the host is using the buck regulator for power. The
device will stay in the low-power Sleep mode until
either of the following conditions is met:
• The CE pin is toggled low for a minimum of
250 μs and then transitioned high.
• The LIN_BUS pin receives a LIN wake-up event.
The wake-up event must last at least 250 µs, per
LIN Standard 2.2A. (MCP8025)
• The HV_IN1 pin transitions high after being in a
low state lasting longer than 250 µs. (MCP8026)
The MCP8025/6 devices are not required to retain
configuration data while in Sleep mode. Sleep mode
will set the BORW bit. When exiting Sleep mode, the
host should send a new configuration message to
configure the device if the default configuration values
are not desired. The same configuration sequence
used during power-up may be used when exiting Sleep
mode. Sleep mode will not be entered if there is a fault
active that will affect the buck regulator output voltage.
This prevents a transition to Sleep mode when the host
is powered by the buck regulator and the regulator is in
an unreliable state.
4.5 Communication Port s
The communication ports provide a means of
communicating to the host system.
4.5.1 LIN BUS TRANSCEIVER (MCP8025)
The MCP8025 provides a physical interface between a
microcontroller and a LIN half-duplex bus. It is intended
for automotive and industrial applications with serial
bus speeds up to 20 kilobaud. The MCP8025 provides
a half-duplex, bidirectional communication interface
between a microcontroller and the serial network bus.
This device will translate the CMOS/TTL logic levels to
LIN level logic and vice versa.
The LIN Bus transceiver circuit provides a LIN
Bus-compliant interface between the LIN Bus and a
LIN-capable UART on an external microcontroller. The
LIN Bus transceiver is load dump protected and
conforms to LIN 2.1.
4.5.1.1 LIN Wake-Up
A LIN wake-up event may be used to wake-up the
MCP8025 from Sleep mode. The MCP8025 will
wake-up on the rising edge of the LIN bus after
detecting a dominate state lasting > 150 µs on the
LIN_BUS pin. The LIN Bus master must provide the
dominate state for > 250 µs to meet the LIN 2.2A and
SAE J2602.
4.5.1.2 FAULT/TXE (MCP8025)
The FAULT/TXE pin is a bidirectional open-drain output
pin. The state of the pin is defined in Ta bl e 4 -6 .
Whenever the FAULT/TXE signal is low, the LIN
transmitter is OFF. The transmitter may be re-enabled
whenever the FAULT/TXE signal returns high, either by
removing the internal fault condition or by the host
returning the FAULT/TXE high.
The FAULT/TXE will go low when there is a mismatch
between the TX input and the LIN_BUS level. This may
be used to detect a bus contention.
2014-2017 Microchip Technology Inc. DS20005339C-page 35
MCP8025/6
The FAULT/TXE pin will go low whenever the internal
circuits have detected a short circuit and have disabled
the LIN_BUS output driver. The MCP8025 limits the
transmitter current to less than 200 mA when a short
circuit is detected. If the host MCU is driving the
FAULT/TXE pin high, then the transmitter will remain
enabled and the fault condition will be overruled. If the
host MCU is driving the pin low or is in High Z mode,
the MCP8025 will drive the pin low and will disable the
LIN transmitter.
4.5.1.3 LIN Dominant State Timeout
The MCP8025 has an additional LIN feature, LIN
Dominant State Timeout, that is not in the current LIN
2.0 specification. If the LIN TX pin is externally held low
for more than the time specified by tDOM_TOUT
, the
MCP8025 will disable the LIN transmitter. The
FAULT/TXE pin will go low, indicating a LIN Dominant
State Timeout fault. Forcing the FAULT/TXE pin high
will not re-enable the transmitter. The transmitter will
stay disabled until the TX pin is set high again. This
prevents the LIN transceiver from inadvertently locking
up the bus.
4.5.2 LEVEL TRANSLATOR (MCP8026)
The level translators are an interface between the
companion microcontroller’s logic levels and the input
voltage levels from the system. Automotive
applications typically drive the inputs from the Engine
Control Unit (ECU) and the ignition key on/off signals.
The level translators are unidirectional translators.
Signals on the high-voltage input are translated to
low-voltage signals on the low-voltage outputs. The
high-voltage HV_IN[1:2] inputs have a configurable
30 k pull up. The pull up is configured via a
SET_CFG_0 message. The PU30K bit in the
CFG0 register controls the state of the pull up. The bit
may only be changed when the CE pin is low. The
low-voltage LV_OUT[1:2] outputs are open-drain
outputs. The outputs are capable of sinking a minimum
of 1 mA of current while maintaining less than 50 mV at
the output.
The HV_IN1 translator is also used to wake-up the
device from the Sleep mode whenever the HV_IN1
input is transitioned to a low level for a minimum of
250 µs followed by a transition to the high voltage level.
TABLE 4-6: FAULT/TXE TRUTH TABLE
TX
In RX
Out LIN_BUS
I/O
FAULT/TXE
Definition
External
Input Driven
Output
LH V
DD High Z L FAULT, TX driven low, LIN_BUS shorted to VDD (Note 1)
LH V
DD HLFAULT, Overridden by CPU driving FAULT/TXE high
HH V
DD High Z, H H OK
H L GND High Z, H H OK, data is being received from the LIN_Bus
L L GND High Z, H H OK
L L GND
VDD High Z, H L FAULT, if TX is low longer than tDOM_TOUT
xx V
DD LxNO FAULT, the CPU is commanding the transceiver to
turn off the transmitter driver
Legend: x = don’t care
Note 1: The FAULT/TXE is valid approximately 25 µs after the TXD falling edge. This helps eliminate false fault
reporting during bus propagation delays.
Note: The TQFP package has two level
translators. The second level translator
typically interfaces to an ignition key on/off
signal.
MCP8025/6
DS20005339C-page 36 2014-2017 Microchip Technology Inc.
4.5.3 DE2 COMMUNICATIONS PORT
A half-duplex 9600 baud UART interface is available to
communicate with an external host. The port is used to
configure the MCP8025/6 and also for status and fault
messages. The DE2 communication port is described
in detail in Section 4.5.3.1 “Communication
Interface”.
4.5.3.1 Communication Interface
A single-wire, half-duplex, 9600 baud, 8-bit
bidirectional communication interface is implemented
using the open-drain DE2 pin. The interface consists of
eight data bits, one Stop bit and one Start bit. The
implementation of the interface is described in the
following sections.
The DE2 interface is an open-drain interface. The
open-drain output is capable of sinking a minimum of
1 mA of current while maintaining less than 50 mV at
the output.
A 5 k resistor should typically be used between the
host transmit pin and the MCP8025/6 DE2 pin to allow
the MCP8025/6 to drive the DE2 line when the host TX
pin is at an idle high level.
The DE2 communication is active when CE = 0 with
the constraint that the MCP8025/6 devices will not
initiate any messages. The host processor may initiate
messages regardless of the state of the CE pin when
the device is not in Sleep mode. The MCP8025/6
devices will respond to host commands when the CE
pin is low. The time from receiving the last bit of a
command message to sending the first bit of the
response message ranges from DE2RSP to DE2WAIT
corresponding to 0 µs to 3.125 ms.
4.5.3.2 Packet Format
Every internal status change will provide a
communication to the microcontroller. The interface
uses a standard UART baud rate of 9600 bits per
second.
In the DE2 protocol, the transmitter and the receiver do
not share a clock signal. A clock signal does not
emanate from one transmitter to the other receiver.
Due to this reason, the protocol is asynchronous. The
protocol uses only one line to communicate, so the
transmit/receive packet must be done in Half-Duplex
mode. A new transmit message is allowed only when a
complete packet has been transmitted.
The host must listen to the DE2 line in order to check
for contentions. In case of contention, the host must
release the line and wait for at least three packet-length
times before initiating a new transfer.
Figure 4-3 illustrates a basic DE2 data packet.
4.5.3.3 Packet Timing
While no data is being transmitted, a logic ‘1’ must be
placed on the open-drain DE2 line by an external
pull-up resistor. A data packet is composed of one Start
bit, which is always a logic ‘0’, followed by eight data
bits and a Stop bit. The Stop bit must always be a logic
‘1’. It takes 10 bits to transmit a byte of data.
The device detects the Start bit by detecting the
transition from logic ‘1’ to logic ‘0’ (note that, while the
data line is idle, the logic level is high). Once the Start
bit is detected, the next data bit’s “center” can be
assured to be 24 ticks minus 2 (worst-case
synchronizer uncertainty) later. From then on, every
next data bit center is 16 clock ticks later. Figure 4-4
illustrates this point.
4.5.3.4 Message Handling
The driver will not transition to Standby mode or Sleep
mode while a message is being received. If a DE2
message is being received or transmitted while the
driver is transitioning from Operational mode to either
Sleep mode (tSLEEP) or Standby mode (tSTANDBY), the
driver will wait until the ongoing message is completed
before changing modes.
2014-2017 Microchip Technology Inc. DS20005339C-page 37
MCP8025/6
FIGURE 4-3: DE2 Packet Format.
FIGURE 4-4: DE2 Packet Timing.
4.5.4 MESSAGING INTERFACE
A command byte will always have the most significant
bit 7 (MSb) set to ‘1’. Bits 6 and 5 are reserved for future
use and should be set to ‘0’. Bits 4–0 are used for
commands. That allows for 32 possible commands.
4.5.4.1 Host to MCP8025/6
Messages sent from the host to the MCP8025/6
devices consist of either one or two eight-bit bytes. The
first byte transmitted is the command byte. The second
byte transmitted, if required, is the data for the
command.
If a multi-byte command is sent to the MCP8025/6
devices and no second byte is received by the
MCP8025/6 devices, then a ‘Not Acknowledged’
(NACK) message will be sent back to the host after a
5 ms time-out period.
4.5.4.2 MCP8025/6 to Host
A solicited response byte from the MCP8025/6 devices
will always echo the command byte with bit 7 set to ‘0’
(Response) and with bit 6 set to ‘1’ for ‘Acknowledged’
(ACK) or ‘0’ for ‘Not Acknowledged’ (NACK). The
second byte, if required, will be the data for the host
command. Any command that causes an error or is not
supported will receive a NACK response.
The MCP8025/6 devices may send unsolicited
command messages to the host controller. No
message to the host controller requires a response
from the host controller.
STOP
STARTDE2
Message Format
B0B1B2B3B4B5B6B7
STOP
START B0B1B2B3B4B5B6B7
TSTART = 1.5T – uncertainty on start
Detection (worse case: 2x TS)
TS = T/16 (oversampled bit-cell period)
Receiver samples the incoming data
using x16 baud rate clock
Sample incoming data
at the bit-cell center
TS
TSTART
T
T = 1/Baud Rate (bit-cell period)
Detect start bit by sensing
transition from logic 1 to logic 0
worst
MCP8025/6
DS20005339C-page 38 2014-2017 Microchip Technology Inc.
4.5.5 MESSAGES
4.5.5.1 SET_CFG_0
The SET_CFG_0 message is sent by the host to the
MCP8025/6 devices to configure the devices. The
SET_CFG_0 message may be sent to the device at any
time. The host is responsible for making sure the
system is in a state that will not be compromised by
sending the SET_CFG_0 message. The SET_CFG_0
message format is indicated in Tab le 4 - 7. The
response is indicated in Table 4-8.
4.5.5.2 GET_CFG_0
The GET_CFG_0 message is sent by the host to the
MCP8025/6 devices to retrieve the device
configuration register. The GET_CFG_0 message
format is indicated in Table 4-7. The response is
indicated in Tabl e 4-8 .
4.5.5.3 STATUS_0 and STATUS_1
STATUS_0 and STATUS_1 messages are sent by the
host to the MCP8025/6 devices to retrieve the device
STAT0 or STAT1 register. Unsolicited STATUS_0 and
STATUS_1 messages may also be sent to the host by
the MCP8025/6 devices to inform the host of status
changes. The unsolicited STATUS_0 and STATUS_1
messages will only be sent when a status bit changes
to an active state. The STATUS_0 and STATUS_1
message format is indicated in Tab le 4 - 7. The
response is indicated in Table 4-8.
When a STATUS_0 and STATUS_1 message is sent to
the host in response to a new fault becoming active, the
fault bit will be cleared either by the host issuing a
STATUS_0 and STATUS_1 request message or by the
host toggling the CE pin low then high. The fault bit will
stay active and not be cleared if the fault condition still
exists at the time the host attempted to clear the fault.
The BORW bit in the STAT1 register will be set every
time the device restarts due to a brown-out event, a
Sleep mode wake-up or a normal power-up. When the
bit is set, a single unsolicited message will be sent to
the host indicating a voltage brownout or power-up has
taken place and that the configuration data may have
been lost. The flag is reset by a ‘STATUS_1 ACK’
(01000110 (46H)) from the device in response to a
Host Status Request command.
4.5.5.4 SET_CFG_1
The SET_CFG_1 message is sent by the host to the
MCP8025/6 devices to configure the motor current limit
reference DAC. The SET_CFG_1 message may be
sent to the device at any time. The host is responsible
for making sure the system is in a state that will not be
compromised by sending the SET_CFG_1 message.
The SET_CFG_1 message format is indicated in
Table 4-7. The response is indicated in Table 4-8.
4.5.5.5 GET_CFG_1
The GET_CFG_1 message is sent by the host to the
MCP8025/6 devices to retrieve the motor current limit
reference DAC configuration register. The GET_CFG_1
message format is indicated in Tabl e 4- 7 . The
response is indicated in Table 4-8.
4.5.5.6 SET_CFG_2
The SET_CFG_2 message is sent by the host to the
MCP8025/6 devices to configure the driver current limit
blanking time. The SET_CFG_2 message may be sent
to the device at any time. The host is responsible for
making sure the system is in a state that will not be
compromised by sending the SET_CFG_2 message.
The SET_CFG_2 message format is indicated in
Table 4-7. The response is indicated in Table 4-8.
4.5.5.7 GET_CFG_2
The GET_CFG_2 message is sent by the host to the
MCP8025/6 devices to retrieve the device
Configuration Register 2. The GET_CFG_2 message
format is indicated in Tabl e 4-7 . The response is
indicated in Tabl e 4-8 .
2014-2017 Microchip Technology Inc. DS20005339C-page 39
MCP8025/6
TABLE 4-7: DE2 COMMUNICATION COMMANDS TO MCP8025/6 FROM HOST
Command Byte Bit Value Description
SET_CFG_0 110000001 (81H) Set Configuration Register 0
27 0Reserved
6—(Always ‘0’ in Sleep mode)
0Enable Disconnect of 30 k LIN Bus/Level Translator Pull Up when
CE = 0 (Default)
1Disable Disconnect of 30 k LIN Bus/Level Translator Pull Up when
CE = 0
50System Enters Standby Mode when CE = 0
1System Enters Sleep Mode when CE = 0, 30 k LIN Bus/Level
Translator Pull Up Disconnect always enabled
40Disable Internal Neutral Simulator (Start-Up Default)
1Enable Internal Neutral Simulator
30Enable MOSFET Undervoltage Lockout (Start-Up Default)
1Disable MOSFET Undervoltage Lockout
20Enable External MOSFET Short-Circuit Detection (Start-Up Default)
1Disable External MOSFET Short-Circuit Detection
1:0 00 Set External MOSFET Overcurrent Limit to 0.250V (Start-Up Default)
01 Set External MOSFET Overcurrent Limit to 0.500V
10 Set External MOSFET Overcurrent Limit to 0.750V
11 Set External MOSFET Overcurrent Limit to 1.000V
GET_CFG_0 110000010 (82H) Get Configuration Register 0
SET_CFG_1 110000011 (83H) Set Configuration Register 1
DAC Motor Current Limit Reference Voltage
2 7:0 00H – FFH Select DAC Current Reference value
(4.503V – 0.991V)/255 = 13.77 mV/bit
00H = 0.991V
40H = 1.872V (40H x 0.1377 mV/bit + 0.991V) (Start-Up Default)
FFH = 4.503V (FFH x 0.1377 mV/bit + 0.991V)
GET_CFG_1 110000100 (84H) Get Configuration Register 1
Get DAC Motor Current Limit Reference Voltage
STATUS_0 110000101 (85H) Get Status Register 0
STATUS_1 110000110 (86H) Get Status Register 1
SET_CFG_2 110000111 (87H) Set Configuration register 2
27:5 00H Reserved
4:2 —Driver Dead Time (for PWMH/PWML inputs)
000 2000 ns (Default)
001 1750 ns
010 1500 ns
011 1250 ns
100 1000 ns
101 750 ns
110 500 ns
111 250 ns
1:0 —Driver Blanking Time (Ignore Switching Current Spikes)
00 4 µs (Default)
01 2µs
10 1µs
11 500 ns
MCP8025/6
DS20005339C-page 40 2014-2017 Microchip Technology Inc.
GET_CFG_2 110001000 (88H) Get Configuration Register 2
TABLE 4-8: DE2 COMMUNICATION MESSAGES FROM MCP8025/6 TO HOST
MESSAGE BYTE BIT VALUE DESCRIPTION
SET_CFG_0 17:000000001 (01H) Set Configuration Register 0 ‘Not Acknowledged’ (Response)
01000001 (41H) Set Configuration Register 0 ‘Acknowledged’ (Response)
27 0Reserved
6—Ignored in Sleep mode
0Enable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0 (Default)
1Disable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0
50System Enters Standby Mode when CE = 0
1System Enters Sleep Mode when CE = 0, 30K LIN Bus/Level
Translator Pull Up Disconnect always enabled
40Internal Neutral Simulator Disabled (Start-Up Default)
1Internal Neutral Simulator Enabled
30Undervoltage Lockout Enabled (Default)
1Undervoltage Lockout Disabled
20External MOSFET Overcurrent Detection Enabled (Default)
1External MOSFET Overcurrent Detection Disabled
1:0 00 0.250V External MOSFET Overcurrent Limit (Default)
01 0.500V External MOSFET Overcurrent Limit
10 0.750V External MOSFET Overcurrent Limit
11 1.000V External MOSFET Overcurrent Limit
GET_CFG_0 17:000000010 (02H) Get Configuration Register 0 ‘Not Acknowledged’ (Response)
01000010 (42H) Get Configuration Register 0 ‘Acknowledged’ (Response)
27 0Reserved
6—Ignored in Sleep mode
0Enable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0 (Default)
1Disable Disconnect of 30K LIN Bus/Level Translator Pull Up when
CE = 0
50System Enters Standby Mode when CE = 0
1System Enters Sleep Mode when CE = 0, 30K LIN Bus/Level
Translator Pull Up Disconnect always enabled
40Internal Neutral Simulator Disabled (Start-Up Default)
1Internal Neutral Simulator Enabled
30Undervoltage Lockout Enabled
1Undervoltage Lockout Disabled
20External MOSFET Overcurrent Detection Enabled
1External MOSFET Overcurrent Detection Disabled
1:0 00 0.250V External MOSFET Overcurrent Limit
01 0.500V External MOSFET Overcurrent Limit
10 0.750V External MOSFET Overcurrent Limit
11 1.000V External MOSFET Overcurrent Limit
TABLE 4-7: DE2 COMMUNICATION COMMANDS TO MCP8025/6 FROM HOST (CONTINUED)
Command Byte Bit Value Description
2014-2017 Microchip Technology Inc. DS20005339C-page 41
MCP8025/6
SET_CFG_1 100000011 (03H) Set DAC Motor Current Limit Reference Voltage ‘Not Acknowledged’
(Response)
01000011 (43H) Set DAC Motor Current Limit Reference Voltage ‘Acknowledged’
(Response)
2 7:0 00H – FFH Current DAC Current Reference Value: 13.77 mV/bit + 0.991V
GET_CFG_1 100000100 (04H) Get DAC Motor Current Limit Reference Voltage ‘Not Acknowledged’
(Response)
01000100 (44H) Get DAC Motor Current Limit Reference Voltage ‘Acknowledged’
(Response)
2 7:0 00H – FFH Current DAC Current Reference Value: 13.77 mV/bit + 0.991V
STATUS_0 17:000000101 (05H) Status Register 0 ‘Not Acknowledged’ (Response)
01000101 (45H) Status Register 0 ‘Acknowledged’ (Response)
10000101 (85H) Status Register 0 Command to Host (Unsolicited)
27:0 00000000 Normal Operation
00000001 Temperature Warning (TJ>72% T
SD_MIN = 115°C) (Default)
00000010 Overtemperature (TJ> 160°C)
00000100 Input Undervoltage (VDD <5.5V)
00001000 Driver Input Overvoltage (20V < VDDH <32V)
00010000 Input Overvoltage (VDD >32V)
00100000 Buck Regulator Overcurrent
01000000 Buck Regulator Output Undervoltage Warning
10000000 Buck Regulator Output Undervoltage (< 80%, Brown-out Error)
STATUS_1 17:000000110 (06H) Status Register 1 ‘Not Acknowledged’ (Response)
01000110 (46H) Status Register 1 ‘Acknowledged’ (Response)
10000110 (86H) Status Register 1 Command to Host (Unsolicited)
27:0 00000000 Normal Operation
00000001 Reserved
00000010 Reserved
00000100 External MOSFET Undervoltage Lockout (UVLO)
00001000 External MOSFET Overcurrent Detection
00010000 Brown-out Reset – Config Lost (Start-Up Default = 1)
00100000 +5V LDO Undervoltage Lockout (UVLO)
01000000 Reserved
10000000 Reserved
TABLE 4-8: DE2 COMMUNICATION MESSAGES FROM MCP8025/6 TO HOST (CONTINUED)
MESSAGE BYTE BIT VALUE DESCRIPTION
MCP8025/6
DS20005339C-page 42 2014-2017 Microchip Technology Inc.
SET_CFG_2 100000111 (07H) Set Configuration Register 2 ‘Not Acknowledged’ (Response)
01000111 (47H) Set Configuration Register 2 ‘Acknowledged’ (Response)
2 7:5 00H Reserved
4:2 —Driver Dead Time (for PWMH/PWML inputs)
000 2000 ns (Default)
001 1750 ns
010 1500 ns
011 1250 ns
100 1000 ns
101 750 ns
110 500 ns
111 250 ns
1:0 —Driver Blanking Time (Ignore Switching Current Spikes)
00 4 µs (Default)
01 2µs
10 1µs
11 500 ns
GET_CFG_2 100001000 (08H) Get Configuration Register 2 ‘Not Acknowledged’ (Response)
01001000 (48H) Get Configuration Register 2 ‘Acknowledged’ (Response)
2 7:5 00H Reserved
4:2 —Driver Dead Time (for PWMH/PWML inputs)
000 2000 ns (Default)
001 1750 ns
010 1500 ns
011 1250 ns
100 1000 ns
101 750 ns
110 500 ns
111 250 ns
1:0 —Driver Blanking Time (Ignore Switching Current Spikes)
00 4 µs (Default)
01 2µs
10 1µs
11 500 ns
TABLE 4-8: DE2 COMMUNICATION MESSAGES FROM MCP8025/6 TO HOST (CONTINUED)
MESSAGE BYTE BIT VALUE DESCRIPTION
2014-2017 Microchip Technology Inc. DS20005339C-page 43
MCP8025/6
4.6 Register Definitions
REGISTER 4-1: CFG0: CONFIGURATION REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— PU30K SLEEP NEUSIM EXTUVLO EXTSC EXTOC1 EXTOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 PU30K: 30K LIN/Level Translator Pull Up (1)
1 = Disable disconnect of 30K Pull Up when CE = 0.
0 = Enable disconnect of 30K Pull Up when CE = 0.
bit 5 SLEEP: Sleep Mode bit
1 = System enters Sleep Mode when CE = 0. Disconnect of 30K LIN/Level Translator Pull Up always
enabled.
0 = System enters Standby Mode when CE = 0.
bit 4 NEUSIM: Neutral Simulator (MCP8025)
1 = Enable Internal Neutral Simulator
0 = Disable Internal Neutral Simulator
bit 3 EXTUVLO: External MOSFET Undervoltage Lockout
1 = Disable
0 = Enable
bit 2 EXTSC: External MOSFET Short-Circuit Detection
1 = Disable
0 = Enable
bit 1-0 EXTOC<1:0>: External MOSFET Overcurrent Limit Value
00 = Overcurrent limit set to 0.250V
01 = Overcurrent limit set to 0.500V
10 = Overcurrent limit set to 0.750V
11 = Overcurrent limit set to 1.000V
Note 1: Bit may only be changed while in Standby mode.
MCP8025/6
DS20005339C-page 44 2014-2017 Microchip Technology Inc.
REGISTER 4-2: CFG1: CONFIGURATION REGISTER 1
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DACREF7 DACREF6 DACREF5 DACREF4 DACREF3 DACREF2 DACREF1 DACREF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DACREF<7:0>: DAC Current Reference Value
(4.503V – 0.991V)/255 = 13.77 mV/bit
00H = 0.991V
40H = 1.872V (40H x 0.1377 mV/bit + 0.991V)
FFH = 4.503V (FFH x 0.1377 mV/bit + 0.991V)
REGISTER 4-3: CFG2: CONFIGURATION REGISTER 2
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DRVDT2 DRVDT1 DRVDT0 DRVBL1 DRVBL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-2 DRVDT<2:0>: Driver Dead Time Selection bits
000 = 2000 ns
001 = 1750 ns
010 = 1500 ns
011 = 1250 ns
100 = 1000 ns
101 = 750 ns
110 = 500 ns
111 = 250 ns
bit 1-0 DRVB<1:0>: Driver Blanking Time Selection bits
00 =4000ns
01 =2000ns
10 =1000ns
11 = 500ns
2014-2017 Microchip Technology Inc. DS20005339C-page 45
MCP8025/6
REGISTER 4-4: STAT0: STATUS REGISTER 0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BUVLOF BUVLOW BIOCPW OVLOF DOVLOF UVLOF OTPF OTPW
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BUVLOF: Buck Undervoltage Lockout Fault
1 = Buck output voltage is below 80% of expected value
0 = Buck output voltage is above 80% of expected value
bit 6 BUVLOW: Buck Undervoltage Lockout Warning
1 = Buck output voltage is below 90% of expected value
0 = Buck output voltage is above 90% of expected value
bit 5 BIOCPW: Buck Input Overcurrent Protection Warning
1 = Buck input current is above 2A peak
0 = Buck input current is below 2A peak
bit 4 OVLOF: Input Overvoltage Lockout Fault
1 =V
DD Input Voltage > 32V
0 =V
DD Input Voltage < 32V
bit 3 DOVLOF: Driver Input Overvoltage Lockout Fault (MCP8025 only, MCP8026 =0)
1 =20V<V
DDH
0 =V
DD < 20V
bit 2 UVLOF: Input Undervoltage Fault
1 =V
DD Input Voltage < 5.5V
0 =V
DD Input Voltage > 5.5V
bit 1 OTPF: Overtemperature Protection Fault
1 = Device junction temperature is > 160°C
0 = Device junction temperature is < 160°C
bit 0 OTPW: Overtemperature Protection Warning
1 = Device junction temperature is > 115°C
0 = Device junction temperature is < 115°C
MCP8025/6
DS20005339C-page 46 2014-2017 Microchip Technology Inc.
REGISTER 4-5: STAT1: STATUS REGISTER 1
U-0 U-0 R-0 R-1 R-0 R-0 U-0 U-0
— — UVLOF5V BORW XOCPF XUVLOF — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 UVLOF5V: +5V LDO Undervoltage Lockout
1 = +5V LDO output voltage < 4.0V
0 = +5V LDO output voltage > 4.0V
bit 4 BORW: Brown-out Reset Warning, Configuration Lost
1 = Internal device reset has occurred since last configuration message
0 = No internal device reset has occurred since last configuration message
bit 3 XOCPF: External MOSFET Overcurrent Protection Fault (1)
1 = External MOSFET VDS > CFG0<EXTOC> value
0 = External MOSFET VDS < CFG0<EXTOC> value
bit 2 XUVLOF: External MOSFET Gate Drive Undervoltage Fault
1 =HS
X Output Voltage < 8V
0 =HS
X Output Voltage > 8V
bit 1-0 Unimplemented: Read as ‘0’
Note 1: Only valid when CFG0<EXTSC> = 1.
2014-2017 Microchip Technology Inc. DS20005339C-page 47
MCP8025/6
5.0 APPLICATION INFORMATION
5.1 Component Calculations
5.1.1 CHARGE PUMP CAPACITORS
FIGURE 5-1: Charge Pump.
Let:
5.1.1.1 Flying Capacitor
The flying capacitor should be chosen to charge to a
minimum of 95% (3) of VDDH within one half of a
switching cycle.
Choose a 180 nF capacitor.
5.1.1.2 Charge Pump Output Capacitor
Solve for the charge pump output capacitance,
connected between V12P and ground, that will supply
the 20 mA load for one switch cycle. The +12V LDO
pin on the MCP8025/6 is the “V12P” pin referenced in
the calculations.
For stability reasons, the +12V LDO and +5V LDO
capacitors must be greater than 4.7 µF, so choose
C4.7 µF.
5.1.1.3 Charging Path (Flying Capacitor
across CAP1 and CAP2)
5.1.1.4 Transfer Path (Flying and Output
Capacitors)
5.1.1.5 Calculate the Flying Capacitor
Voltage Drop in One Cycle while
Supplying 20 mA
The second and subsequent transfer cycles will have
a higher voltage available for transfer, since the
capacitor is not completely depleted with each cycle.
VCAP will then be VCAP – dV after the first transfer,
plus VDDH –(V
CAP – dV) times the RC constant. This
repeats for each subsequent cycle, allowing a larger
charge pump capacitor to be used if the system
tolerates several charge transfers before requiring
full-output voltage and current.
Repeating the steps in Section 5.1.1.3, Charging Path
(Flying Capacitor across CAP1 and CAP2) for the
second cycle (and subsequent by re-calculating for
each new value of VCAP after each transfer):
5.1.1.6 Charge Pump Results
The maximum charge pump flying capacitor value is
202 nF to maintain a 95% voltage transfer ratio on the
first charge pump cycle. Larger capacitor values may
be used but they will require more cycles to charge to
maximum voltage. The minimum required output
capacitor value is 2.65 µF to supply 20 mA for 13.3 µs
with a 100 mV drop. A larger output capacitor may be
used to cover losses due to capacitor tolerance over
temperature, capacitor dielectric and PCB losses.
IOUT =20mA
fCP = 75 kHz (charge/discharge in one cycle)
50% duty cycle
VDDH = 6V (worst case)
RDSON =7.5 (RPMOS), 3.5 (RNMOS)
V12P = 2 x VDDH (ideal)
CESR =20m (ceramic capacitors)
VDROP = 100 mV (VOUT ripple)
TCHG =T
DCHG =0.5x1/75kHz=6.67µs
3x=T
CHG
=T
CHG/3
RC = TCHG/3
C=T
CHG/(R x 3)
C = 6.67 µs/([7.5+3.5+0.02]x3)
C = 202 nF
C=I
OUT x dt/dV
C=I
OUT x 13.3 µs/(VDROP +I
OUT xC
ESR)
C = 20 mA x 13.3 µs/(0.1V + 20 mA x 20 m)
C2.65 µF
Transfer
Charge
VCAP =V
DDH (1–e
-T/)
VCAP =
6V (1–e
– [6.67 µs/([7.5
+3.5
+20m
] x 180 nF)]
)
VCAP = 5.79V available for transfer
V12P = VDDH +V
CAP –I
OUT xdt/C
V12P = 6V + 5.79V – (20 mA x 6.67 µs/180 nF)
V12P = 11.049V
dV = IOUT xdt/C
dV = 20 mA x 6.67 µs/180 nF
dV = 0.741V @ 20 mA
VCAP
=(V
CAP
–dV)+(V
DDH
–(V
CAP
–dV))
(1 – e
-T/
)
VCAP
= (5.79V – 0.741V) + (6V – (5.79V – 0.741V)) x
(1–e
– [6.67 µs/([7.5+3.5+20m]x180nF)]
)
VCAP
= 5.049V + 0.951V x 0.96535
VCAP
= 5.967V available for transfer on second cycle
MCP8025/6
DS20005339C-page 48 2014-2017 Microchip Technology Inc.
These are approximate calculations. The actual
voltages may vary due to incomplete charging or
discharging of capacitors per cycle due to load
changes. The charge pump calculations assume the
charge pump is able to charge up the external boot
cap within a few cycles.
5.1.2 BOOTSTRAP CAPACITOR
The high-side driver bootstrap capacitor needs to
power the high-side driver and gate for 1/3 of the
motor electrical period for a 3-phase BLDC motor.
Let:
Solve for the smallest capacitance that can supply:
- 130 nC of charge to the MOSFET gate
-1M Gate-Source resistor current
- Driver bias current and switching losses
Sum all of the energy requirements:
Choose a bootstrap capacitor value that is larger than
43.86 nF.
5.1.3 BUCK SWITCHER
5.1.3.1 Calculate the Buck Inductor for
Discontinuous Mode Operation
Let:
Solve for maximum inductance value.
Choose an inductor 3.64 µH to ensure
Discontinuous Conduction mode.
Table 5-1 shows the various maximum inductance
values for a worst case input voltage of 6V and various
output voltages.
MOSFET driver current =300mA
PWM period = 50µs (20kHz)
Minimum duty cycle = 1% (500 ns)
Maximum duty cycle = 99% (49.5 µs)
VIN =12V
Minimum gate drive voltage =8V (V
GS)
Total gate charge = 130 nC (80A MOSFET)
Allowable VGS drop (VDROP)=3V
Switch RDSON =100m
Driver internal bias current =20µA (I
BIAS)
QMOSFET =130 nC
QRESISTOR =[(VGS/R) x TON]
QDRIVER =(IBIAS xT
ON)
TON =49.5 µs (99% DC) for worst case
QRESISTOR =(12V/1 M)x49.5µs
QRESISTOR =0.594 nC
QDRIVER =20 µA x 49.5 µs
QDRIVER =0.99 nC
C=(QMOSFET +Q
RESISTOR +Q
DRIVER)/VDROP
C=(130 nC + 0.594 nC + 0.99 nC)/3V
C=43.86 nF
VIN =4.3V (worst case is BUVLO)
VOUT =3.3V
IOUT =225 mA
fSW =468 kHz (TSW =2.137µs)
LMAX =VOUT x(1–V
OUT/VIN)xT
SW/(2 x IOUT)
LMAX =
3.3V x (1 – 3.3V/4.3V) x 2.137 µs/(2 x 225 mA)
LMAX =3.64 µH
TABLE 5-1: MAXIMUM INDUCTANCE FOR BUCK DISCONTINUOUS MODE OPERATION
VIN
(worst case) VOUT IOUT Maximum Inductance
4.3V (BUVLO) 3V 250 mA 4.3 µH
4.3V (BUVLO) 3.3V 225 mA 3.6 µH
6V 5.0V 150 mA 5.9 µH
2014-2017 Microchip Technology Inc. DS20005339C-page 49
MCP8025/6
5.1.3.2 Determine the Peak Switch Current
for the Calculated Inductor
5.1.3.3 Setting the Buck Output Voltage
The buck output voltage is set by a resistor voltage
divider from the inductor output to ground. The divider
center tap is fed back to the MCP8025 FB pin. The
FB pin is compared to an internal 1.25V reference
voltage. When the FB pin voltage drops below the
reference voltage, the buck duty cycle increases.
When the FB pin rises above the reference voltage,
the buck duty cycle decreases.
FIGURE 5-2: Typical Buck Application.
See Errata section 6.9 for resistor value requirements..
5.1.3.4 Start-Up Delay for Bootstrap
Charging
A start-up delay is required whenever the device has
been disabled (CE = 0) and the bootstrap capacitors
have discharged. When the device is re-enabled
(CE = 1), there is a voltage divider between the
+12V LDO capacitor and the bootstrap capacitors. To
prevent a gate drive undervoltage lockout, the
+12V LDO capacitor must be sized to prevent the
bootstrap capacitors from pulling the 12V supply below
the UVLO threshold when the 12V supply is enabled.
Assuming the V12 capacitor is 4.7 µF, V12 LDO is 12V,
CBOOTSTRAP = 1 µF, the bootstrap voltage when the
12V supply is first turned on will be:
12V x (4.7 µF/(4.7 µF + 3 bootstrap caps charging x
1 µF)) = 7.32V which will trip the gate driver UVLO if the
low-side is turned on at this time.
By sizing the 12V LDO capacitor to prevent the
bootstrap voltage from dropping below 8V, the UVLO
may be averted.
Where "n" is the number of simultaneous bootstrap
caps being charged at the same time.
Letting VBOOT = 9V, CapBOOTSTRAP = 470 nF and
charging three caps simultaneously:
Use a 4.7 µF capacitor for the +12V LDO.
Letting VBOOT = 9V, CapBOOTSTRAP = 1 µF and
charging three caps simultaneously:
Use a 10 µF capacitor for the +12V LDO.
Letting VBOOT =9V, Cap
BOOTSTRAP = 1 µF and
charging one cap at a time:
Use a 3.3 µF capacitor for the +12V LDO.
IPEAK =
(V
S
–V
O
)xDxT/L
IPEAK =
(4.3V – 3.3V) x (3.3V/4.3V) x 2.137 µs/3.64 µH
IPEAK =
450 mA
VBUCK = 1.25V x (R1 + R2)/R2
OUTPUT
CONTROL
LOGIC
VDD
+
-
LX
FB
+
-
Q1
CURRENT_REF
VDD-12V
BANDGAP
REFERENCE
+
-
R1
R2
C1
L1
D1
Schottky
V
BOOTCAP
= 12V (Cap12V/(Cap12V + n x Cap
BOOTSTRAP
))
VBOOTCAP/12V
= Cap12V/(Cap12V + n x Cap
BOOT-
STRAP
)
12V/VBOOTCAP = (Cap12V + n x CapBOOTSTRAP)/
Cap12V
Cap12V x 12V/VBOOTCAP = Cap12V + n x CapBOOT-
STRAP
12V/V
BOOTCAP
x Cap12V – Cap12V = n x Cap
BOOTSTRAP
Cap12V = (n x CapBOOTSTRAP)/(12V/VBOOTCAP – 1)
Cap12V =(3 x 470 nF)/(12V/9V – 1) = 4.23 µF
Cap12V =(3 x 1 µF)/(12V/9V – 1) = 9.0 µF
Cap12V =(1 x 1 µF)/(12V/9V – 1) = 3.0 µF
MCP8025/6
DS20005339C-page 50 2014-2017 Microchip Technology Inc.
5.2 Device Protection
5.2.1 MOSFET VOLTAGE SUPPRESSION
When a motor shaft is rotating and power is removed,
the magnetism of the motor components will cause the
motor to act like a generator. The current that was
flowing into the motor will now flow out of the motor. As
the motor magnetic field decays, the generator output
will also decay. The voltage across the generator
terminals will be proportional to the generator current
and the circuit impedance of the generator circuit. If
the power supply is part of the return path for the
current and the power supply is disconnected, then the
voltage at the generator terminals will increase until
the current flows. This voltage increase must be
handled external to the driver. A voltage suppression
device must be used to clamp the motor terminal
voltage to a level that will not exceed the maximum
motor operating voltage. A voltage suppressor should
be connected from ground to each motor terminal. The
PCB traces must be capable of carrying the motor
current with minimum voltage and temperature rise.
An additional method is to inactivate the high-side
drivers and to activate the low-side drivers. This allows
current to flow through the low-side external
MOSFETs and prevents the voltage increases at the
power supply terminals. A pure hardware
implementation may be done by connecting a
bidirectional transient voltage suppressor (TVS) from
the gate of each external low-side driver MOSFET to
the drain of the same MOSFET. When the phase
voltage rises above the TVS standoff voltage, the TVS
will start to conduct, pulling up the gate of the low-side
MOSFET. This turns on the MOSFET and creates a
low-voltage current path for the motor windings to
dissipate stored energy. The implementation is a
failsafe mechanism in cases where the supply
becomes disconnected or the controller shuts down
due to a fault or command. The MCP8025/6
overvoltage lockout (OVLO) is 32V, so a 33V TVS
would be used. This allows the MCP8025/6 to shut
down before the TVS forces the low-side gates high,
preventing the MCP8025/6 low-side drivers from
sinking current if they are being driven low. The
MCP8025 may use a lower voltage transzorb due to
the fact that the MCP8025 driver overvoltage lockout
(DOVLO) occurs at a lower voltage.
5.2.2 BOOTSTRAP VOLTAGE
SUPPRESSION
The pins which handle the highest voltage during
motor operation are the bootstrap pins (VBx). The
bootstrap pin voltage is typically 12V higher than the
associated phase voltage. When the high-side
MOSFET is conducting, the phase pin voltage is
typically at VDD and the bootstrap pin voltage is
typically at VDD + 12V. When the phase MOSFETs
switch, current-induced voltage transients occur on the
phase pins. Those induced voltages cause the
bootstrap pin voltages to also increase. Depending on
the magnitude of the phase pin voltage, the bootstrap
pin voltage may exceed the safe operating voltage of
the device. The current-induced transients may be
reduced by slowing down the turn-on and turn-off
times of the MOSFETs. The external MOSFETs may
be slowed down by adding a 10 to 75 resistor in
series with the gate drive. The high-side MOSFETs
may also be slowed down by inserting a 4 resistor
between each bootstrap pin and the associated
bootstrap diode-capacitor junction. Another 25 to
50 resistor is then added between the gate drive and
the MOSFET gate. This results in a high-side turn-on
resistance of 4plus the resistance of the series gate
resistor. The high-side turn-off resistance only consists
of the series gate resistance and will allow for a faster
shutoff time.
36V TVS devices (40V breakdown voltage) should
also be connected from each bootstrap pin (VBx) to
ground. This will ensure that the bootstrap voltage
does not exceed the 46V absolute maximum voltage
allowed on the pins. The resistors connected between
the bootstrap pins and the bootstrap diode-capacitor
junctions mentioned in the previous paragraph should
also be used in order to limit the TVS current and
reduce the TVS package size.
5.2.3 FLOATING GATE SUPPRESSION
The gate drive pins may float when the supply voltage
is lost or an overvoltage situation shuts down the
driver. When an overvoltage condition exists, the
driver high-side and low-side outputs are high Z. Each
external MOSFET that is connected to the gate driver
should have a gate-to-source resistor to bleed off any
charge that may accumulate due to the high Z state.
This will help prevent inadvertent turn-on of the
MOSFET.
5.2.4 MOSFET BODY DIODE REVERSE
RECOVERY SNUBBER
When motor current is flowing through the external
MOSFET body diodes and the complimentary
MOSFET of the phase pair turns on, the body diode
reverse recovery creates a momentary short-circuit
until the reverse recovery time is complete. When the
body diode reverse recovery is complete, the current
path is opened, causing the phase node voltage to slew
rapidly towards ground or VDD levels. The rapid slew
rate may cause an inversion of the gate-to-source
voltage on the MOSFET that is turning on and result in
that MOSFET turning off.
Adding a drain-to-source snubber slows down the slew
rate of the phase node and results in a more controlled
excursion of the phase node voltage. The snubber
consists of a resistor and a capacitor connected in
series between the drain and source of the MOSFET.
The resistor is chosen to keep the initial snubber
voltage below a few volts when peak motor current is
2014-2017 Microchip Technology Inc. DS20005339C-page 51
MCP8025/6
flowing through the body diode. The capacitor is then
chosen to provide an RC time constant longer than the
MOSFET body diode reverse recovery time. A
0.1resistor is typically used along with a 0.1 µF
capacitor to provide an RC of 10 ns.
The power dissipated by the capacitor is calculated by
applying Equation 5-1.
EQUATION 5-1: SNUBBER CAPACITOR
POWER DISSIPATION
The capacitor and resistor form factors are chosen to
handle the dissipated power.
5.3 Related Literature
• AN885, “Brushless DC (BLDC) Motor
Fundamentals”, DS00885, Microchip Technology
Inc., 2003
• AN1160, “Sensorless BLDC Control with
Back-EMF Filtering Using a Majority Function”,
DS01160, Microchip Technology Inc., 2008
• AN1078, “Sensorless Field Oriented Control of a
PMSM”, DS01078, Microchip Technology Inc.,
2010
Where:
PDISS 2
fCV
2
Dissipation Factor=
Dissipation Factor 2
fCESR
=ESR XC
=
f = PWM frequency
C = Capacitance
V = Motor Voltage
2014-2017 Microchip Technology Inc. DS20005339C-page 52
MCP8025/6
Figure 5-3 shows the location of the overvoltage TVS devices, gate resistors, bootstrap resistors and gate-to-source resistors.
FIGURE 5-3: Overvoltage Protection.
PHA
PHB
PHC VDD
HSA
HSB
HSC
LSA
LSB
LSC
VBA
VBB
VBC
CB
A
+
_
+12V
R
R
R
R
R
R
R
R
R
SSS
RRR
R
R
R
2014-2017 Microchip Technology Inc. DS20005339C-page 53
MCP8025/6
6.0 ERRATA
6.1 VBOOT Not Ready
When CE = 0, VBOOT must attain 10.8V before the
driver outputs will be enabled. If the PWM inputs
change state before VBOOT attains 10.8V, the driver
outputs will not change and no driver fault will be
issued.
Workaround: When setting CE = 1 from standby
mode, allow time for the VBOOT capacitor to
charge up to 10.8V. Typical time is 250 µs.
Device: MCP8025 - All datecodes
Device: MCP8026 - Datecodes prior to
YYWW = 1635
6.2 PWM Pulsewidth = Driver
Deadtime Pulsewidth
When the PWM input pulse width is the same as the
driver programmed deadtime, a dead time race
condition may occur that forces both driver outputs to
go low until both PWM inputs go low again. Normally,
the PWM pulse width is longer than the deadtime in
order to generate an output pulse equal to
PWM_PULSEWIDTH - DEADTIME. However, some
systems allow the PWM pulse width to be smaller than
the driver deadtime, knowing that there will be no driver
output.
Workaround: Setup host minimum PWM
pulsewidth to be at least 50 ns larger or smaller
than driver deadtime setting.
Device: All
6.3 Motor Driver Lock
It has been detected that the motor driver can be
locked after a momentary drop of VDD below the
minimum operating voltage or after enabling the driver
output when using low VGS threshold MOSFETs
(VGS < 1.1V). The issue was traced back to the high
side driver operation at voltages below the minimum
operating voltage.
Workaround: None.
Device: MCP8025 - All datecodes
Device: MCP8026 - Datecodes prior to
YYWW = 1635
6.4 External MOSFET DUVLO and
OCP Detection
These detection functions could flag an inexistent
motor driver under voltage or power MOSFET over
current fault when a DE2 message was sent to enable
the functions while the motor was running.
Workaround: Stop the motor before enabling the
external MOSFET UVLO and OCP protection.
Device: MCP8025 - All datecodes
Device: MCP8026 - Datecodes prior to
YYWW = 1635
6.5 External MOSFET DUVLO and
OCP Fault
When a resistor is used in series with the VBx bootstrap
pins, an external MOSFET undervoltage fault and/or
overcurrent protection fault may occur. This is caused
by the voltage drop across the resistor when the
complementary driver transistors switch state. The
switching overlap may draw enough current to lower
the voltage long enough to trigger the fault. Increasing
the bootstrap capacitance and charge time will provide
more energy storage.
Workaround: When a series VBx bootstrap
resistor is used with short duration OFF time
duty cycles (< 8%), the value should be kept
below 4 ohms.
Device: All
6.6 Supply Start-up Sequence
It has been detected that in cases where VDD
momentarily dropped below the minimum operating
voltage and then recovered, the driver buck regulator
could restart before the supply voltage reached 6V.
Workaround: Keep VDD within the operational
voltage limits set forth in the data sheet.
Device: MCP8025 - All datecodes
Device: MCP8026 - Datecodes prior to
YYWW = 1635
6.7 LIN BCI (MCP8025)
When applying the BCI stress on the LIN pin, the LIN
bus voltage could drop below -5V. This is not allowed
by the SAE 2962 standard.
Workaround: None.
Device: MCP8025 - All datecodes
6.8 LIN TX = 0 Time-out Function
(MCP8025)
The TX = 0 LIN time-out function could cause a TX
lockup fault at power up or waking up. Unlocking was
only possible by powering down or going to sleep mode
repeatedly until the TX became unlocked.
Workaround: None
Device: MCP8025 - All datecodes
6.9 Buck Over-Voltage
It has been observed that the buck output voltage may
exceed the target voltage for <1.5 ms after power-up
under certain power-up scenarios. The issue is caused
MCP8025/6
DS20005339C-page 54 2014-2017 Microchip Technology Inc.
by an unintended current that may flow into the FB pin,
causing an additional voltage drop across the resistor
R1 (high side of resistor divider) from the buck output
to the FB pin. The over-voltage has only been observed
on an application with no resistive load on the +5V LDO
output to discharge the 5V LDO capacitor to 0V before
the system is powered up again, but it cannot be
excluded that other applications may also be affected.
Workaround: The over-voltage will be minimized if
the resistor selection for R2 (low side of resistor
divider) in Section 5.1.3.3 is 620 ohms or less.
Device: All devices
2014-2017 Microchip Technology Inc. DS20005339C-page 55
MCP8025/6
7.0 PACKAGING INFORMATION
7.1 Package Marking Information
40-Lead QFN (5x5x0.85 mm) Example
MCP8026
EPT1730
256
48-Lead TQFP (7x7x1 mm) Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
MCP8025
E/MP^^
1730256
3
e
MCP8025/6
DS20005339C-page 56 2014-2017 Microchip Technology Inc.
0.20 C
0.20 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
1
2
N
2X
TOP VIEW
SIDE VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.08 C
Microchip Technology Drawing C04-047-002A Sheet 1 of 2
40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN]
D2
D
E
AB
40X b
e0.07 C A B
0.05 C
A
(A3)
With 3.7x3.7 mm Exposed Pad
E2
A1
0.10 C
K
L
2X
2014-2017 Microchip Technology Inc. DS20005339C-page 57
MCP8025/6
Microchip Technology Drawing C04-047-002A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Overall Length
Terminal Length
Exposed Pad Width
Exposed Pad Length
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E2
D2
A3
e
L
E
N
0.40 BSC
0.20 REF
0.30
0.15
0.80
0.00
0.20
5.00 BSC
0.40
3.70 BSC
3.70 BSC
0.85
0.02
5.00 BSC
MILLIMETERS
MIN NOM
40
0.50
0.25
0.90
0.05
MAX
K-0.20 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN]
With 3.7x3.7 mm Exposed Pad
MCP8025/6
DS20005339C-page 58 2014-2017 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
SILK SCREEN
Dimension Limits
Units
C1
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
3.80
3.80
MILLIMETERS
0.40 BSC
MIN
E
MAX
5.00
Contact Pad Length (X40)
Contact Pad Width (X40)
Y1
X1
0.80
0.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing C04-2047-002A
NOM
40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN]
With 3.7x3.7 mm Exposed Pad
E
C1
C2 Y2
X2
Y1
X1
C2Contact Pad Spacing 5.00
2014-2017 Microchip Technology Inc. DS20005339C-page 59
MCP8025/6
C
SEATING
PLANE
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
Microchip Technology Drawing C04-183A Sheet 1 of 2
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad
TOP VIEW
EE1
D
0.20 HA-B D
4X
D1/2
12
AB
AA
D
D1
A1
A
H
0.10 C
0.08 C
SIDE VIEW
D2
E2
N
12
N
0.20 CA-B D
48X TIPS
0.20 HA-B D
4X
0.20
4X
E1/4
D1/4
A2
TOP VIEW
E1/2
e48x b
0.08 CA-B D
e/2
MCP8025/6
DS20005339C-page 60 2014-2017 Microchip Technology Inc.
Microchip Technology Drawing C04-183A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad
H
L
(L1)
T
c
D
E
SECTION A-A
2.
1.
4.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
3.
protrusions shall not exceed 0.25mm per side.
Mold Draft Angle Bottom
Molded Package Thickness
Dimension Limits
Mold Draft Angle Top
Notes:
Foot Length
Lead Width
Lead Thickness
Molded Package Length
Molded Package Width
Overall Length
Overall Width
Foot Angle
Footprint
Standoff
Overall Height
Lead Pitch
Number of Leads
12°
E11° 13°
0.750.600.45L
12°
0.22
7.00 BSC
7.00 BSC
9.00 BSC
9.00 BSC
3.5°
1.00 REF
c
D
b
D1
E1
0.09
0.17
11°
D
E
I
L1
0°
13°
0.27
0.16-
7°
1.00
0.50 BSC
48
NOM
MILLIMETERS
A1
A2
A
e
0.05
0.95
-
Units
N
MIN
1.05
0.15
1.20
-
-
MAX
Chamfers at corners are optional; size may vary.
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
Exposed Pad Length
Exposed Pad Width
D2
E2 3.50 BSC
3.50 BSC
2014-2017 Microchip Technology Inc. DS20005339C-page 61
MCP8025/6
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C2 Y2
X1
C1
X2
E
Y1
Dimension Limits
Units
C1
Optional Center Tab Width
Contact Pad Spacing
Contact Pad Spacing
Optional Center Tab Length
Contact Pitch
C2
Y2
X2
3.50
3.50
MILLIMETERS
0.50 BSC
MIN
E
MAX
8.40
8.40
Contact Pad Length (X48)
Contact Pad Width (X48)
Y1
X1
1.50
0.30
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2183A
NOM
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Thermal Tab
2014-2017 Microchip Technology Inc. DS20005339C-page 62
MCP8025/6
APPENDIX A: REVISION HISTORY
Revision C (October 2017)
The following is the list of modifications:
1. Updated the Input Hysteresis values in the
AC/DC Characteristics table.
2. Updated Figure 4-1 “MCP8025/6 State Dia-
gram.”.
3. Added Section 6.0 “ERRATA”.
Revision B (March 2016)
The following is the list of modifications:
4. Added Figure 2-17 “Typical Baud Rate Devia-
tion.”
5. Corrected resistor values in Section 3.10 “LIN
Transceiver Fault/ Transmit Enable
(FAULTn/TXE)”.
6. Added Section 4.1 “State Diagrams”.
7. Added Section 5.1.3.4 “Start-Up Delay for
Bootstrap Charging”.
8. Added Section 5.2.4 “MOSFET Body Diode
Revers e Rec overy Snubb er”.
Revision A (September 2014)
• Original Release of this Document.
MCP8025/6
DS20005339C-page 63 2014-2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP8025: 3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module and LIN
Transceiver
MCP8025T: 3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module and LIN
Transceiver (Tape and Reel)
MCP8026: 3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module
MCP8026T: 3-Phase Brushless DC (BLDC) Motor
Gate Driver with Power Module (Tape
and Reel)
Tape and
Reel: T = Tape and Reel (1)
Blank = Tube
Temperature
Warning: 115 = 115°C
Temperature
Range: E = -40°C to +125°C (Extended)
H = -40°C to +150°C (High)
Package: MP = Plastic Quad Flat, No Lead Package – 5x5 mm
Body with 3.5x3.5 mm Exposed Pad, 40-lead
PT = Thin Quad Flatpack – 7x7x1.0 mm Body with
Exposed Pad, 48-lead
Examples:
a) MCP8025-115E/MP: Extended temperature
40LD 5x5 QFN package
b) MCP8025T-115E/MP: Tape and Reel
Extended temperature
40LD 5x5 QFN package
c) MCP8025-115H/MP: High temperature
40LD 5x5 QFN package
d) MCP8025T-115H/MP: Tape and Reel
High temperature
40LD 5x5 QFN package
e) MCP8026-115E/MP: Extended temperature
40LD 5x5 QFN package
f) MCP8026T-115E/MP: Tape and Reel
Extended temperature
40LD 5x5 QFN package
g) MCP8026-115H/MP: High temperature
40LD 5x5 QFN package
h) MCP8026T-115H/MP: Tape and Reel
High temperature
40LD 5x5 QFN package
i) MCP8025-115E/PT: Extended temperature
48LD TQFP-EP package
j) MCP8025T-115E/PT: Tape and Reel
Extended temperature
48LD TQFP-EP package
k) MCP8025-115H/PT: High temperature
48LD
TQFP-EP package
l) MCP8025T-115H/PT: Tape and Reel
High Temperature
48LD TQFP-EP package
m) MCP8026-115E/PT: Extended temperature
48LD TQFP-EP package
n) MCP8026T-115E/PT: Tape and Reel
Extended temperature
48LD TQFP-EP package
o) MCP8026-115H/PT: High temperature
48LD TQFP-EP package
p) MCP8026T-115H/PT: Tape and Reel
High temperature
48LD TQFP-EP package
PART NO. -X /XX
PackageTemperature
Device
X
Temperature
Range
Warning
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the Tape
and Reel option.
X (1)
Tape and Reel
2014-2017 Microchip Technology Inc. DS20005339C-page 64
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014-2017, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-2221-1
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Ore gon and design centers in California
and India. The Company’ s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, micro perip hera ls, n onvolat ile memory and
analog products . In add ition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005339C-page 65 2014-2017 Microchip Technology Inc.
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