S-8211E Series
www.ablicinc.com
BATTERY PROTECTION IC
FOR 1-CELL PACK
© ABLIC Inc., 2009-2015 Rev.2.4_03
1
The S-8211E Series has high-accuracy voltage detections circuit and delay circuits.
The S-8211E Series is suitable for monitoring overcharge and overdischarge of 1-cell lithium ion / lithium polymer
rechargeable battery pack.
Features
(1) High-accuracy voltage detection circuit
Overcharge detection voltage 3.6 V to 4.5 V (5 mV step) Accuracy 25 mV (25C)
Accuracy 30 mV (5C to 55C)
Overcharge release voltage 3.5 V to 4.4 V*1 Accuracy 50 mV
Overdischarge detection voltage 2.0 V to 3.0 V (10 mV step) Accuracy 50 mV
Overdischarge release voltage 2.0 V to 3.4 V*2 Accuracy 100 mV
(2) Detection delay times are generated by an internal circuit
(external capacitors are unnecessary) Accuracy 20%
(3) Wide operating temperature range 40C to 85C
(4) Low current consumption
During operation 3.0 A typ., 5.5 A max. (25C)
During overdischarge 2.0 A typ., 3.5 A max. (25C)
(5) Output logic of CO pin is selectable. Active “H”, Active “L”
(6) Lead-free, Sn 100%, halogen-free*3
*1. Overcharge release voltage = Overcharge detection voltage Overcharge hysteresis voltage
(Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step.)
*2. Overdischarge release voltage = Overdischarge detection voltage Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 100 mV step.)
*3. Refer to “ Product Name Structure” for details.
Applications
Lithium-ion rechargeable battery pack
Lithium-polymer rechargeable battery pack
Packages
SOT-23-5
SNT-6A
www.ablic.com
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
2
Block Diagram
－
＋
－
＋
VM
VSS
VDD
CO
DO
Overcharge
detection
comparator
Output control circuit
Divider control
circuit
Overdischarge
detection
comparator
Oscillator control
circuit
Remark All diodes shown in figure are parasitic diodes.
Figure 1
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
3
Product Name Structure
1. Product Name
S-8211E xx - xxxx U
Serial code*2
Sequentially set from AA to ZZ
Package name (abbreviation) and IC packing specifications*1
M5T1: SOT-23-5, Tape
I6T1: SNT-6A, Tape
Environmental code
U: Lead-free (Sn 100%), halogen-free
*1. Refer to the tape drawing.
*2. Refer to “3. Product Name List”.
2. Packages
Package Name Drawing Code
Package Tape Reel Land
SOT-23-5 MP005-A-P-SD MP005-A-C-SD MP005-A-R-SD
SNT-6A PG006-A-P-SD PG006-A-C-SD PG006-A-R-SD PG006-A-L-SD
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
4
3. Product Name List
3. 1 SOT-23-5
Table 1
Product Name
Overcharge
Detection
Voltage
[V
CU
]
Overcharge
Release
Voltage
[V
CL
]
Overdischarge
Detection
Voltage
[V
DL
]
Overdischarge
Release
Voltage
[V
DU
]
Delay Time
Combination
*1
CO Pin
Output Form
S-8211EAC-M5T1U 3.600 V 3.600 V 2.00 V 2.00 V (1) CMOS output active “L”
S-8211EAF-M5T1U 3.650 V 3.550 V 2.00 V 2.30 V (2) CMOS output active “L”
S-8211EAG-M5T1U 3.800 V 3.600 V 2.00 V 2.30 V (2) CMOS output active “L”
S-8211EAJ-M5T1U 4.180 V 4.180 V 2.50 V 3.00 V (1) CMOS output active “H”
S-8211EAK-M5T1U 3.600 V 3.600 V 2.00 V 2.30 V (1) CMOS output active “H”
*1. Refer to the Table 3 about the details of the delay time combinations (1), (2).
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
3. 2 SNT-6A
Table 2
Product Name
Overcharge
Detection
Voltage
[V
CU
]
Overcharge
Release
Voltage
[V
CL
]
Overdischarge
Detection
Voltage
[V
DL
]
Overdischarge
Release
Voltage
[V
DU
]
Delay Time
Combination
*1
CO Pin
Output Form
S-8211EAA-I6T1U 4.220 V 4.220 V 2.00 V 2.00 V (2) CMOS output active “L”
S-8211EAB-I6T1U 4.270 V 4.270 V 2.00 V 2.00 V (2) CMOS output active “L”
S-8211EAD-I6T1U 4.220 V 4.220 V 2.50 V 2.50 V (2) CMOS output active “L”
S-8211EAE-I6T1U 4.220 V 4.220 V 2.30 V 2.30 V (2) CMOS output active “L”
S-8211EAH-I6T1U 4.000 V 3.800 V 3.00 V 3.20 V (1) CMOS output active “L”
S-8211EAI-I6T1U 3.800 V 3.700 V 2.30 V 2.40 V (1) CMOS output active “L”
S-8211EAP-I6T1U 4.280 V 4.080 V 2.50 V 2.50 V (1) CMOS output active “L”
*1. Refer to the Table 3 about the details of the delay time combinations (1), (2).
Remark Please contact our sales office for the products with detection voltage value other than those specified above.
Table 3
Delay Time
Combination
Overcharge Detection Delay Time
[tCU]
Overdischarge Detection Delay Time
[tDL]
(1) 1.2 s 150 ms
(2) 573 ms 300 ms
Remark The delay times can be changed within the range listed Table 4. For details, please contact our sales office.
Table 4
Delay Time
Symbol Selection Range
Remark
Overcharge detection delay time
t
CU
143 ms 573 ms 1.2 s
Select a value from the left.
Overdischarge detection delay time
t
DL
38 ms 150 ms 300 ms
Select a value from the left.
Remark The value surrounded by bold lines is the delay time of the standard products.
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
5
Pin Configurations
1. SOT-23-5
SOT-23-5
Top view
5
4
3
2
1
Table 5
Pin No. Symbol Description
1 VM Negative power supply input pin for CO pin
2 VDD Input pin for positive power supply
3 VSS Input pin for negative power supply
4 DO Output pin for overdischarge detection
(CMOS output)
5 CO Output pin for overcharge detection
(CMOS output)
Figure 2
2. SNT-6A
SNT-6A
Top view
1
2
3 4
6
5
Table 6
Pin No. Symbol Description
1
NC*1 No connection
2 CO
Output pin for overcharge detection
(CMOS output)
3 DO
Output pin for overdischarge detection
(CMOS output)
4 VSS Input pin for negative power supply
Figure 3 5 VDD Input pin for positive power supply
6 VM Negative power supply input pin for CO pin
*1. The NC pin is electrically open.
The NC pin can be connected to VDD pin or VSS pin.
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
6
Absolute Maximum Ratings
Table 7
(Ta = 25C unless otherwise specified)
Item Symbol Applied pin Absolute Maximum Ratings Unit
Input voltage between VDD pin and
VSS pin VDS VDD
VSS 0.3 to VSS 12 V
VM pin input voltage VVM VM VDD 28 to VDD 0.3 V
DO pin output voltage VDO DO VSS 0.3 to VDD 0.3 V
CO pin output voltage VCO CO VVM 0.3 to VDD 0.3 V
Power dissipation SOT-23-5 PD 600*1 mW
SNT-6A 400*1 mW
Operating ambient temperature Topr 40 to 85 C
Storage temperature Tstg 55 to 125 C
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm × 76.2 mm × t1.6 mm
(2) Board name: JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
050 100 150
700
400
0
Power Dissi
p
ation
(
PD
)
[
mW
]
Ambient Tem
p
erature
(
Ta
)
[
C
]
200
600
500
300
100
SNT-6A
SOT-23-5
Figure 4 Power Dissipation of Package (When Mounted on Board)
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
7
Electrical Characteristics
1. Except Detection Delay Time (25C)
Table 8
(Ta = 25C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condi-
tion
Test
Circuit
DETECTION VOLTAGE
Overcharge detection voltage V
CU
3.60 V to 4.50 V, Adjustable V
CU
0.025
V
CU
V
CU
0.025 V 1 1
3.60 V to 4.50 V, Adjustable,
Ta =
5
C to
55
C
*1
V
CU
0.03
V
CU
V
CU
0.03 V 1 1
Overcharge release voltage V
CL
3.50 V to 4.40 V,
Adjustable
V
CL
V
CU
V
CL
0.05
V
CL
V
CL
0.05 V 1 1
V
CL
= V
CU
V
CL
0.05
V
CL
V
CL
0.025 V 1 1
Overdischarge detection voltage V
DL
2.00 V to 3.00 V, Adjustable V
DL
0.05
V
DL
V
DL
0.05 V 2 2
Overdischarge release voltage V
DU
2.00 V to 3.40 V,
Adjustable
V
DU
V
DL
V
DU
0.10
V
DU
V
DU
0.10 V 2 2
V
DU
= V
DL
V
DU
0.05
V
DU
V
DU
0.05 V 2 2
INPUT VOLTAGE
Operating voltage between VDD pin and VSS pin
V
DSOP1
1.5
8 V
INPUT CURRENT
Current consumption during operation I
OPE
V
DD
= 3.5 V, V
VM
= 0 V 1.0 3.0 5.5
A 3 2
Current consumption during overdischarge I
OPED
V
DD
= 1.5 V, V
VM
= 0 V 0.3 2.0 3.5
A 3 2
OUTPUT RESISTANCE
CO pin resistance “H” R
COH
2.5 5 10 k
4 3
CO pin resistance “L” R
COL
CO pin output logic active “H”
2.5 9 15 k
4 3
CO pin output logic active “L”
2.5 5 10 k
4 3
DO pin resistance “H” R
DOH
2.5 5 10 k
5 3
DO pin resistance “L” R
DOL
2.5 5 10 k
5 3
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
8
2. Except Detection Delay Time (40°C to 85°C *1)
Table 9
(Ta = 40°C to 85°C *1 unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Condi-
tion
Test
Circuit
DETECTION VOLTAGE
Overcharge detection voltage
V
CU
3.60 V to 4.50 V, Adjustable V
CU
0.060
V
CU
V
CU
0.040 V 1 1
Overcharge release voltage
V
CL
3.50 V to 4.40 V,
Adjustable
V
CL
V
CU
V
CL
0.08
V
CL
V
CL
0.065 V 1 1
V
CL
= V
CU
V
CL
0.08
V
CL
V
CL
0.04 V 1 1
Overdischarge detection voltage
V
DL
2.00 V to 3.00 V, Adjustable V
DL
0.11
V
DL
V
DL
0.13 V 2 2
Overdischarge release voltage
V
DU
2.00 V to 3.40 V,
Adjustable
V
DU
V
DL
V
DU
0.15
V
DU
V
DU
0.19 V 2 2
V
DU
= V
DL
V
DU
0.11
V
DU
V
DU
0.13 V 2 2
INPUT VOLTAGE
Operating voltage between VDD pin and VSS pin
V
DSOP1
1.5
8
V
INPUT CURRENT
Current consumption during operation
I
OPE
V
DD
= 3.5 V, V
VM
= 0 V 0.7 3.0 6.0
A 3 2
Current consumption during overdischarge
I
OPED
V
DD
= 1.5 V, V
VM
= 0 V 0.2 2.0 3.8
A 3 2
OUTPUT RESISTANCE
CO pin resistance “H”
R
COH
1.2 5 15
k
4 3
CO pin resistance “L”
R
COL
CO pin output logic active “H”
1.2 9 27
k
4 3
CO pin output logic active “L”
1.2 5 15
k
4 3
DO pin resistance “H”
R
DOH
1.2 5 15
k
5 3
DO pin resistance “L”
R
DOL
1.2 5 15
k
5 3
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
9
3. Detection Delay Time
3. 1 S-8211EAC, S-8211EAH, S-8211EAI, S-8211EAJ, S-8211EAK, S-8211EAP
Table 10
Item Symbol Condition Min. Typ. Max. Unit
Test
Condi-
tion
Test
Circuit
DELAY TIME (Ta =
25°C)
Overcharge detection delay time t
CU
0.96 1.2 1.4 s 6 4
Overdischarge detection delay time t
DL
120 150 180 ms 6 4
DELAY TIME (Ta =
40°C to
85°C)
*1
Overcharge detection delay time t
CU
0.7 1.2 2.0 s 6 4
Overdischarge detection delay time t
DL
83 150 255 ms 6 4
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
3. 2 S-8211EAA, S-8211EAB, S-8211EAD, S-8211EAE, S-8211EAF, S-8211EAG
Table 11
Item Symbol Condition Min. Typ. Max. Unit
Test
Condi-
tion
Test
Circuit
DELAY TIME (Ta =
25°C)
Overcharge detection delay time t
CU
458 573 687
ms 6 4
Overdischarge detection delay time t
DL
240 300 360
ms 6 4
DELAY TIME (Ta =
40°C to
85°C)
*1
Overcharge detection delay time t
CU
334 573 955
ms 6 4
Overdischarge detection delay time t
DL
166 300 510
ms 6 4
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
10
Test Circuits
Caution Unless otherwise specified, the output voltage levels “H” and “L” at CO pin (VCO) are judged by VVM
1.0 V, and the output voltage levels “H” and “L” at DO pin (VDO) are judged by VSS 1.0 V. Judge the
CO pin level with respect to VVM and the DO pin level with respect to VSS.
1. Overcharge Detection Voltage, Overcharge Release Voltage
(Test Condition 1, Test Circuit 1)
1. 1 CO pin output logic = Active “H”
Overcharge detection voltage (VCU) is defined as the voltage between the VDD pin and VSS pin at which VCO
goes from “L” to “H” when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V.
Overcharge release voltage (VCL) is defined as the voltage between the VDD pin and VSS pin at which VCO goes
from “H” to “L” when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined
as the difference between overcharge detection voltage (VCU) and overcharge release voltage (VCL).
1. 2 CO pin output logic = Active “L”
Overcharge detection voltage (VCU) is defined as the voltage between the VDD pin and VSS pin at which VCO
goes from “H” to “L” when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V.
Overcharge release voltage (VCL) is defined as the voltage between the VDD pin and VSS pin at which VCO goes
from “L” to “H” when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined
as the difference between overcharge detection voltage (VCU) and overcharge release voltage (VCL).
2. Overdischarge Detection Voltage, Overdischarge Release Voltage
(Test Condition 2, Test Circuit 2)
Overdischarge detection voltage (VDL) is defined as the voltage between the VDD pin and VSS pin at which VDO goes
from “H” to “L” when the voltage V1 is gradually decreased from the starting condition of V1 = 3.5 V, V2 = 0 V.
Overdischarge release voltage (VDU) is defined as the voltage between the VDD pin and VSS pin at which VDO goes
from “L” to “H” when the voltage V1 is then gradually increased. Overdischarge hysteresis voltage (VHD) is defined as
the difference between overdischarge release voltage (VDU) and overdischarge detection voltage (VDL).
3. Current Consumption during Operation
(Test Condition 3, Test Circuit 2)
The current consumption during operation (IOPE) is the current that flows through the VDD pin (IDD) under the set
conditions of V1 = 3.5 V and V2 = 0 V (normal status).
4. Current Consumption during Overdischarge
(Test Condition 3, Test Circuit 2)
The current consumption during overdischarge (IOPED) is the current that flows through the VDD pin (IDD) under the
set conditions of V1 = 1.5 V, V2 = 0V (overdischarge status).
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
11
5. CO Pin Resistance “H”
(Test Condition 4, Test Circuit 3)
5. 1 CO pin output logic = Active “H”
The CO pin resistance “H” (RCOH) is the resistance at the CO pin under the set conditions of V1 = 4.5 V, V2 =
0 V, V3 = 4.0 V.
5. 2 CO pin output logic = Active “L”
The CO pin resistance “H” (RCOH) is the resistance at the CO pin under the set conditions of V1 = 3.5 V, V2 =
0 V, V3 = 3.0 V.
6. CO Pin Resistance “L”
(Test Condition 4, Test Circuit 3)
6. 1 CO pin output logic = Active “H”
The CO pin resistance “L” (RCOL) is the resistance at the CO pin under the set conditions of V1 = 3.5 V, V2 =
0 V, V3 = 0.5 V.
6. 2 CO pin output logic = Active “L”
The CO pin resistance “L” (RCOL) is the resistance at the CO pin under the set conditions of V1 = 4.5 V, V2 =
0 V, V3 = 0.5 V.
7. DO Pin Resistance “H”
(Test Condition 5, Test Circuit 3)
The DO pin “H” resistance (RDOH) is the resistance at the DO pin under the set conditions of V1 = 3.5 V, V2 =
0 V, V4 = 3.0 V.
8. DO Pin Resistance “L”
(Test Condition 5, Test Circuit 3)
The DO pin “L” resistance (RDOL) is the resistance at the DO pin under the set conditions of V1 = 1.8 V, V2 =
0 V, V4 = 0.5 V.
9. Overcharge Detection Delay Time
(Test Condition 6, Test Circuit 4)
9. 1 CO pin output logic = Active “H”
The overcharge detection delay time (tCU) is the time needed for VCO to change from “L” to “H” just after the
voltage V1 momentarily increases (within 10 s) from overcharge detection voltage (VCU) 0.2 V to overcharge
detection voltage (VCU) 0.2 V under the set conditions of V2 = 0 V.
9. 2 CO pin output logic = Active “L”
The overcharge detection delay time (tCU) is the time needed for VCO to change from “H” to “L” just after the
voltage V1 momentarily increases (within 10 s) from overcharge detection voltage (VCU) 0.2 V to overcharge
detection voltage (VCU) 0.2 V under the set conditions of V2 = 0 V.
10. Overdischarge Detection Delay Time
(Test Condition 6, Test Circuit 4)
The overdischarge detection delay time (tDL) is the time needed for VDO to change from “H” to “L” just after the voltage
V1 momentarily decreases (within 10 s) from overdischarge detection voltage (VDL) 0.2 V to overdischarge
detection voltage (VDL) 0.2 V under the set condition of V2 = 0 V.
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
12
V V
DO
V V
CO
CO
DO
VSS
VDD
VM
S-8211E Series
R1 =
220
V1
COM
VVDO V VCO
CO
DO
VSS
VDD
VM
S-8211E Series
V1
V2
COM
A
IDD
Figure 5 Test Circuit 1 Figure 6 Test Circuit 2
A IDO A ICO
CO
DO
VSS
VDD
VM
S-8211E Series
V1
V2
COM
V4 V3
CO DO
VSS
VDD
VM
S-8211E Series
V1
V2
COM
Oscilloscope Oscilloscope
Figure 7 Test Circuit 3 Figure 8 Test Circuit 4
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
13
Operation
Remark Refer to the “ Battery Protection IC Connection Example”.
1. Normal Status
The S-8211E Series monitors the voltage of the battery connected between the VDD and VSS pins.
In case of overdischarge detection voltage (VDL) battery voltage overcharge detection voltage (VCU), the output
levels of CO and DO pins are as follows. This is the normal status.
Table 12
CO Pin Output Logic CO Pin DO Pin
Active “H” VVM V
DD
Active “L” VDD V
DD
2. Overcharge Status
When the battery voltage in the normal status exceeds the overcharge detection voltage (VCU) during charge, and this
status is held for the overcharge detection delay time (tCU) or more, the output levels of CO and DO pins are as
follows. This is the overcharge status.
This overcharge status is released when the battery voltage decreases to the overcharge release voltage (VCL) or
less.
Table 13
CO Pin Output Logic CO Pin DO Pin
Active “H” VDD V
DD
Active “L” VVM V
DD
3. Overdischarge Status
When the battery voltage in the normal status decreases than the overcharge detection voltage (VDL) during
discharge, and this status is held for the overdischarge detection delay time (tDL) or more, the output levels of CO and
DO pins are as follows. This is the overdischarge status.
This overdischarge status is released when the battery voltage increases to the overdischarge release voltage (VDU)
or more.
Table 14
CO Pin Output Logic CO Pin DO Pin
Active “H” VVM V
SS
Active “L” VDD V
SS
4. Delay Circuit
The detection delay times are determined by dividing a clock of approximately 3.5 kHz by the counter.
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
14
Timing Chart
1. Overcharge Detection, Overdischarge Detection
VCU
VDU
VDL
VCL
Battery voltage
VDD
DO pin voltage
VSS
Status
*1
Overcharge detection delay time (t
CU
)
(1) (2) (1) (3) (1)
VM
VDD
Overdischarge detection delay time (t
DL
)
CO pin voltage
(active ”H”)
VDD
VM
V
CO pin voltage
(active ”L”)
*1. (1) : Normal status
(2) : Overcharge status
(3) : Overdischarge status
Figure 9
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
15
Battery Protection IC Connection Example
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
CO
DO
R2
Figure 10
Table 15 Constants for External Components
Symbol Part Purpose Min. Typ. Max. Remark
R1 Resistor
ESD protection,
For power fluctuation 100 220 330
Resistance should be as small as possible to
avoid lowering the overcharge detection
accuracy due to current consumption. *1
C1 Capacitor For power fluctuation 0.022 F 0.1 F 1.0 F Connect a capacitor of 0.022 F or higher
between VDD pin and VSS pin. *2
R2*
3
Resistor ESD protection 300 1 k 4 k -
*1. Insert a resistor of 100 or higher as R1 for ESD protection.
*2. If a capacitor of less than 0.022 F is connected to C1, DO pin may oscillate. Be sure to connect a capacitor of 0.022 F
or higher to C1.
*3. Be sure to using R2, connect the VM pin with the VSS pin.
Caution 1. The above constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant do not
guarantee proper operation. Perform thorough evaluation using the actual application to set the
constant.
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
16
Application Circuit Examples
1. Protection circuits series multi-cells
R2
R2
R2
R2
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
CO
DO
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
CO
DO
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
CO
DO
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
CO
DO
Figure 11
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
17
2. Charge cell-balance detection circuit
R2
R2
R2
R2
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
R1
Battery C1
VSS
DO
VDD
CO VM
S-8211E Series
Protection IC
EB
EB
Figure 12
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
18
Precautions
The application conditions for the input voltage, output voltage, and load current should not exceed the package
power dissipation.
Be sure to using R2, connect the VM pin with the VSS pin.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
19
Characteristics (Typical Data)
1. Current Consumption
1. 1 IOPE vs. Ta 1. 2 IOPED vs. Ta
40 25 0 25 50 75 85
6
5
4
3
2
1
0
Ta [ C]
I
OPE
[A]
40
25 0 25 50 7585
4
3
2
1
0
Ta [ C]
I
OPED
[A]
1. 3 IOPE vs. VDD
0 2 4 6
VDD [V]
6
5
4
3
2
1
0
IOPE [A]
8
2. Overcharge Detection / Release Voltage, Overdischarge Detection / Release Voltage, Overcurrent
Detection Voltage, and Delay Time
2. 1 VCU vs. Ta 2. 2 VCL vs. Ta
40 25 0 25 50 75 85
Ta [ C]
4.350
4.345
4.340
4.335
4.330
4.325
4.300
V
CU
[V]
4.320
4.315
4.310
4.305
40
25 0 25 50 75 85
Ta [ C]
4.125
4.115
4.105
4.095
4.085
4.075
4.025
V
CL
[V]
4.065
4.055
4.045
4.035
2. 3 VDU vs. Ta 2. 4 VDL vs. Ta
40 25 0 25 50 75 85
Ta [ C]
2.95
2.94
2.93
2.92
2.91
2.90
2.85
V
DU
[V]
2.89
2.88
2.87
2.86
40
25 0 25 50 7585
Ta [ C]
2.60
2.58
2.56
2.54
2.52
2.50
2.40
V
DL
[V]
2.48
2.46
2.44
2.42
BATTERY PROTECTION IC FOR 1-CELL PACK
S-8211E Series Rev.2.4_03
20
2. 5 tCU vs. Ta 2. 6 tDL vs. Ta
40 25 0 25 50 7585
Ta [C]
1.50
1.45
1.40
1.35
1.30
1.25
1.00
t
CU
[s]
1.20
1.15
1.10
1.05
40
25 0 25 50 7585
Ta [ C]
200
190
180
170
160
150
100
tDL [ms]
140
130
120
110
3. CO pin / DO pin
3. 1 ICOH vs. VCO 3. 2 ICOL vs. VCO
0
0.1
0.2
0.5
I
COH
[mA]
0.3
0.4
0 1 2 3 4
V
CO
[V]
0.5
0.4
0.3
0
I
COL
[mA]
0.2
0.1
0 1 2 3 4
V
CO
[V]
3. 3 IDOH vs. VDO 3. 4 IDOL vs. VDO
0 1 2 3 4
VDO [V]
0
0.05
0.10
0.15
0.30
IDOH [mA]
0.20
0.25
0 0.5 1.0 1.5
VDO [V]
0.20
0.15
0.10
0
IDOL [mA]
0.05
BATTERY PROTECTION IC FOR 1-CELL PACK
Rev.2.4_03 S-8211E Series
21
Marking Specifications
1. SOT-23-5
123
45
Top view
(1) (2) (3) (4)
(1) to (3): Product Code (refer to Product Name vs. Product Code)
(4) : Lot number
Product Name vs. Product Code
Product Name Product Code
(1) (2) (3)
S-8211EAC-M5T1U R 3 C
S-8211EAF-M5T1U R 3 F
S-8211EAG-M5T1U R 3 G
S-8211EAJ-M5T1U R 3 J
S-8211EAK-M5T1U R 3 K
2. SNT-6A
Top view
132
645
(1) (2) (3)
(4) (5) (6)
(1) to (3): Product Code (refer to Product Name vs. Product Code)
(4) to (6): Lot number
Product Name vs. Product Code
Product Name Product Code
(1) (2) (3)
S-8211EAA-I6T1U R 3 A
S-8211EAB-I6T1U R 3 B
S-8211EAD-I6T1U R 3 D
S-8211EAE-I6T1U R 3 E
S-8211EAH-I6T1U R 3 H
S-8211EAI-I6T1U R 3 I
S-8211EAP-I6T1U R 3 P
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
2.9±0.2
1.9±0.2
0.95±0.1
0.4±0.1
0.16 +0.1
-0.06
123
4
5
No. MP005-A-P-SD-1.3
MP005-A-P-SD-1.3
SOT235-A-PKG Dimensions
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
ø1.5 +0.1
-0 2.0±0.05
ø1.0 +0.2
-0 4.0±0.1 1.4±0.2
0.25±0.1
3.2±0.2
123
45
No. MP005-A-C-SD-2.1
MP005-A-C-SD-2.1
SOT235-A-Carrier Tape
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY. 3,000
No. MP005-A-R-SD-1.1
MP005-A-R-SD-1.1
SOT235-A-Reel
Enlarged drawing in the central part
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A-PKG Dimensions
PG006-A-P-SD-2.1
No. PG006-A-P-SD-2.1
0.2±0.05
0.48±0.02
0.08 +0.05
-0.02
0.5
1.57±0.03
123
45
6
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5
1.85±0.05 0.65±0.05
0.25±0.05
mm
PG006-A-C-SD-2.0
SNT-6A-A-Carrier Tape
No. PG006-A-C-SD-2.0
+0.1
-0
1
2
4
3
56
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY.
No. PG006-A-R-SD-1.0
PG006-A-R-SD-1.0
Enlarged drawing in the central part
SNT-6A-A-Reel
5,000
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A
-Land Recommendation
PG006-A-L-SD-4.1
No. PG006-A-L-SD-4.1
0.3
0.2
0.52
1.36
0.52
1
2
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.30 mm ~ 1.40 mm)
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).
1.
2. (1.30 mm ~ 1.40 mm)
(0.25 mm min. / 0.30 mm typ.)
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
www.ablic.com
