CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Internal Look-Ahead for Fast Counting
D
Carry Output for n-Bit Cascading
D
Synchronous Counting
D
Synchronously Programmable
description/ordering information
The ’AC163 devices are 4-bit binary counters.
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. Synchronous
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating.
This mode of operation eliminates the output counting spikes normally associated with synchronous
(ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge
of the clock waveform.
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000
(LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15, with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. T ransitions at ENP or ENT are allowed, regardless of the
level of CLK.
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – E Tube CD74AC163E CD74AC163E
55°Cto125°C
SOIC M
Tube CD74AC163M
AC163M
–
55°C
to
125°C
SOIC
–
M
Tape and reel CD74AC163M96
AC163M
CDIP – F Tube CD54AC163F3A CD54AC163F3A
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
CD54AC163 ...F PACKAGE
CD74AC163 . . . E OR M PACKAGE
(TOP VIEW)
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION
CLR CLK ENP ENT LOAD A,B,C,D QnRCO
FUNCTION
L↑X X X X L L Reset (clear)
h↑X X l l L L
Parallel load
h↑XX l h HNote 1
Parallel
load
h↑h h h X Count Note 1 Count
h X l X h X qnNote 1
Inhibit
h X X l h X qnL
Inhibit
H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK
low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the
state of the referenced output prior to the CLK low-to-high transition, and ↑ = CLK low-to-high
transition.
NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count
(HHHH).
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
9
10
7
3
15
14
CLR
LOAD
ENT
ENP
CLK
A
RCO
QA
†For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
M1
G2
G4
3D
4R
1, 2T/1C3
4
13
B
QB
M1
G2
G4
3D
4R
1, 2T/1C3
5
12
C
QC
M1
G2
G4
3D
4R
1, 2T/1C3
6
11
D
QD
M1
G2
G4
3D
4R
1, 2T/1C3
2
LD†
CK†
CK
R
LD
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol, each D/T flip-flop
M1LD (Load)
Q (Output)
G2TE (Toggle Enable)
CK (Clock) G4
3D
4R
1, 2T/1C3
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
TG
TG
TG
TG
TG
TG
CK
LD
TE
LD†
LD†
D
R
CK†
CK†
CK†
CK†
Q
†The origins of LD and CK are shown in the logic diagram of the overall device.
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Sync
Clear Preset
Count Inhibit
12 13 14 15 0 1 2
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): E package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
TA = 25°C–55°C to
125°C–40°C to
85°CUNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 V
VCC = 1.5 V 1.2 1.2 1.2
VIH High-level input voltage VCC = 3 V 2.1 2.1 2.1 V
VCC = 5.5 V 3.85 3.85 3.85
VCC = 1.5 V 0.3 0.3 0.3
VIL Low-level input voltage VCC = 3 V 0.9 0.9 0.9 V
VCC = 5.5 V 1.65 1.65 1.65
VIInput voltage 0 VCC 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC 0 VCC V
IOH High-level output current –24 –24 –24 mA
IOL Low-level output current 24 24 24 mA
∆t/∆v
In
p
ut transition rise or fall rate
VCC = 1.5 V to 3 V 50 50 50
ns
∆t/∆v
Input
transition
rise
or
fall
rate
VCC = 3.6 V to 5.5 V 20 20 20
ns
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
TA = 25°C–55°C to
125°C–40°C to
85°CUNIT
CC
MIN MAX MIN MAX MIN MAX
1.5 V 1.4 1.4 1.4
IOH = –50 µA3 V 2.9 2.9 2.9
4.5 V 4.4 4.4 4.4
VOH VI = VIH or VIL IOH = –4 mA 3 V 2.58 2.4 2.48 V
IOH = –24 mA 4.5 V 3.94 3.7 3.8
IOH = –50 mA†5.5 V –3.85 –
IOH = –75 mA†5.5 V – – 3.85
1.5 V 0.1 0.1 0.1
IOL = 50 µA3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
VOL VI = VIH or VIL IOL = 12 mA 3 V 0.36 0.5 0.44 V
IOL = 24 mA 4.5 V 0.36 0.5 0.44
IOL = 50 mA†5.5 V –1.65 –
IOL = 75 mA†5.5 V – – 1.65
IIVI = VCC or GND 5.5 V ±0.1 ±1±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 µA
Ci10 10 10 pF
†T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
V
CC
–55°C to
125°C–40°C to
85°CUNIT
CC
MIN MAX MIN MAX
1.5 V 7 8
fclock Clock frequency 3.3 V ± 0.3 V 64 73 MHz
5 V ±0.5 V 90 103
1.5 V 69 61
twPulse duration CLK high or low 3.3 V ± 0.3 V 7.7 6.8 ns
5 V ±0.5 V 5.5 4.8
↑
1.5 V 63 55
↑
A, B, C, or D 3.3 V ± 0.3 V 7 6.1
↑
5 V ±0.5 V 5 4.4
↑
1.5 V 63 55
↑
ENP or ENT 3.3 V ± 0.3 V 9.6 8.2
t
Setu
p
time before CLK↑
5 V ±0.5 V 5 4.4
ns
t
su
Setup
time
,
before
CLK↑
1.5 V 75 66
ns
LOAD low 3.3 V ± 0.3 V 8.4 7.4
5 V ±0.5 V 6 5.3
1.5 V 75 66
CLR inactive 3.3 V ± 0.3 V 8.4 7.4
5 V ±0.5 V 6 5.3
↑
1.5 V 0 0
↑
A, B, C, or D 3.3 V ± 0.3 V 0 0
↑
5 V ±0.5 V 0 0
↑
1.5 V 0 0
↑
ENP or ENT 3.3 V ± 0.3 V 0 0
th
Hold time after CLK↑
5 V ±0.5 V 0 0
ns
th
Hold
time
,
after
CLK↑
1.5 V 0 0
ns
LOAD low 3.3 V ± 0.3 V 0 0
5 V ±0.5 V 0 0
1.5 V 0 0
CLR inactive 3.3 V ± 0.3 V 0 0
5 V ±0.5 V 0 0
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
V
CC
–55°C to
125°C–40°C to
85°CUNIT
(INPUT)
(OUTPUT)
CC
MIN MAX MIN MAX
1.5 V 7 8
fmax 3.3 V ± 0.3 V 64 73 MHz
5 V ±0.5 V 90 103
1.5 V –209 –190
RCO 3.3 V ± 0.3 V 6 23.4 6 21
CLK
5 V ±0.5 V 4.3 16.7 4.3 15.2
CLK
1.5 V –207 –188
tpd Any Q 3.3 V ± 0.3 V 5.9 23.1 5.9 21 ns
5 V ±0.5 V 4.2 16.5 4.2 15
1.5 V –129 –117
ENT RCO 3.3 V ± 0.3 V 3.6 14.4 3.7 13.1
5 V ±0.5 V 2.6 10.3 2.7 9.4
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 66 pF
CD54AC163, CD74AC163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS299B – APRIL 2000 – REVISED MARCH 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
I. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × VCC
R1 = 500 Ω Open
GND
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
Output
Control
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
VOH – 0.3 V
VCC
R2 = 500 Ω
NOTE: When VCC = 1.5 V , R1 and R2 = 1 kΩ.
VOLTAGE WAVEFORMS
RECOVER Y TIME
50% VCC VCC
0 V
CLR
Input
CLK 50% VCC VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54AC163F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74AC163E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC163EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74AC163M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC163M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC163M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC163M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC163ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74AC163MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74AC163M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74AC163M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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