NM27C040Q170 - Fairchild Semiconductor

NM27C040

4,194,304-Bit (512K x 8) High Performance CMOS

EPROM

General Description

The NM27C040 is a high performance, 4,194,304-bit Electri-

cally Programmable UV Erasable Read Only Memory. It is

organized as 512K words of 8 bits each. Its pin-compatibility

with byte-wide JEDEC EPROMs enables upgrades through

8 Mbit EPROMs. The “Don’t Care” feature on V

during

read operations allows memory expansions from 1M to

8 Mbits with no printed circuit board changes.

The NM27C040 provides microprocessor-based systems

extensive storage capacity for large portions of operating

system and application software. Its 120 ns access time pro-

vides high speed operation with high-performance CPUs.

The NM27C040 offers a single chip solution for the code

storage requirements of 100%firmware-based equipment.

Frequently used software routines are quickly executed from

EPROM storage, greatly enhancing system utility.

The NM27C040 is manufactured using Fairchild’s advanced

CMOS AMG™EPROM technology.

Features

nHigh performance CMOS

— 120 ns access time

nSimplified upgrade path

—V

is a “Don’t Care” during normal read operation

nManufacturer’s identification code

nJEDEC standard pin configuration

— 32-pin DIP

— 32-pin PLCC

— 32-pin TSOP

Block Diagram

AMG™is a trademark of WSI, Inc.

DS010836-1

March 1997

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

NM27C040

PrintDate=1997/08/11 PrintTime=19:20:20 6769 ds010836 Rev. No. 3 cmserv Proof 1

Connection Diagrams

Commercial Temperature Range

(0˚C to +70˚C)

=5V ±10%

Parameter/Order Number Access Time (ns)

NM27C040 Q, V, T 120 120

NM27C040 Q, V, T 150 150

NM27C040 Q, V, T 170 170

NM27C040 Q, V, T 200 200

Military Temperature Range (−55˚C

to +125˚C)

=5V ±10%

Parameter/Order Number Access Time (ns)

NM27C040 QM 150 150

NM27C040 QM 200 200

Pin Names

A0–A18 Addresses

CE /PGM Chip Enable/Program

OE Output Enable

O0–O7 Outputs

XX Don’t Care (During Read)

Extended Temperature Range

(−40˚C to +85˚C)

=5V ±10%

Parameter/Order Number Access Time (ns)

NM27C040 QE, VE, TE 150 150

NM27C040 QE, VE, TE 170 170

NM27C040 QE, VE, TE 200 200

Package Types: NM27C040 Q, V, T XXX

Q=Quartz-Windowed Ceramic DIP

V=PLCC

T=TSOP

•All packages conform to the JEDEC standard.

•All versions are guaranteed to function for slower speeds.

DS010836-2

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C040 pin.

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Absolute Maximum Ratings (Note 1)

Storage Temperature −65˚C to +150˚C

All Input Voltages except A9 with

Respect to Ground −0.6V to +7V

and A9 with Respect to Ground −0.6V to +14V

Supply Voltage with

Respect to Ground −0.6V to +7V

ESD Protection >2000V

All Output Voltages with

Respect to Ground V

+10V to GND −0.6V

Operating Range

Range Temperature V

Tolerance

Commercial 0˚C to +70˚C +5V ±10%

Industrial −40˚C to +85˚C +5V ±10%

Read Operation

DC Electrical Characteristics

Over operating range with V

Symbol Parameter Test Conditions Min Max Units

Input Low Level −0.5 0.8 V

Input High Level 2.0 V

+1 V

Output Low Voltage I

=2.1 mA 0.4 V

Output High Voltage I

=−2.5 mA 3.5 V

SB1

Standby Current (CMOS) CE =V

±0.3V 100 µA

SB2

Standby Current CE =V

1mA

Active Current CE =OE =V

, I/O =0mA f=5 MHz 30 mA

Supply Current V

10 µA

Read Voltage V

− 0.4 V

Input Load Current V

=5.5V or GND −1 1 µA

Output Leakage Current V

OUT

=5.5V or GND −10 10 µA

AC Electrical Characteristics

Over operating range with V

Symbol Parameter 120 150 170 200 Units

Min Max Min Max Min Max Min Max

ACC

Address to Output Delay 120 150 170 200

CE to Output Delay 120 150 170 200

OE to Output Delay 50 50 50 50

Output Disable to 35 35 45 55 ns

(Note 2) Output Float

Output Hold from Addresses

(Note 2) CE or OE , Whichever 0000

Occurred First

Capacitance T

=+25˚C, f =1 MHz (Note 2)

Symbol Parameter Conditions Typ Max Units

Input Capacitance V

=0V 9 15 pF

OUT

Output Capacitance V

OUT

=0V 12 15 pF

AC Test Conditions

Output Load 1 TTL Gate and

=100 pF (Note 8)

Input Rise and Fall Times ≤5ns

Input Pulse Levels 0.45V to 2.4V

Timing Measurement Reference Level (Note 10)

Inputs 0.8V and 2V

Outputs 0.8V and 2V

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AC Waveforms (Notes 6, 7, 9)

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op-

eration of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100%tested.

Note 3: OE may be delayed up to tACC −t

OE after the falling edge of CE without impacting tACC.

Note 4: The tDF and tCF compare level is determined as follows:

High to TRI-STATE®, the measured VOH1 (DC) − 0.10V;

Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE .

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on

every device between VCC and GND.

Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOL =1.6 mA, IOH =−400 µA.

CL: 100 pF includes fixture capacitance.

Note 9: VPP may be connected to VCCexcept during programming.

Note 10: Inputs and outputs can undershoot to −2.0V for 20 ns Max.

Programming Waveform (Note 13)

DS010836-4

DS010836-5

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Programming Characteristics (Notes 11, 12, 13, 14)

Symbol Parameter Conditions Min Typ Max Units

Address Setup Time 1 µs

OES

OE Setup Time 1µs

Data Setup Time 1 µs

VPS

Setup Time 1 µs

VCS

Setup Time 1 µs

Address Hold Time 0 µs

Data Hold Time 1 µs

Output Enable to Output Float Delay CE /PGM =X060ns

Program Pulse Width 45 50 105 µs

Data Valid from OE CE /PGM =X 100 ns

Supply Current during CE /PGM =V

30 mA

Programming Pulse

Supply Current 30 mA

Temperature Ambient 20 25 30 ˚C

Power Supply Voltage 6.25 6.5 6.75 V

Programming Supply Voltage 12.5 12.75 13.0 V

Input Rise, Fall Time 5 ns

Input Low Voltage −0.1 0.0 0.45 V

Input High Voltage 2.4 4.0 V

Input Timing Reference Voltage 0.8 2.0 V

OUT

Output Timing Reference Voltage 0.8 2.0 V

Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein.

Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a

board with voltage applied to VPP or VCC.

Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP

supply to prevent any overshoot from exceeding this 14V maximum specification.At least a 0.1 µF capacitor is required across VPP,V

CC to GND to suppress spurious

voltage transients which may damage the device.

Note 14: During power up the CE /PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.

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Turbo Programming Algorithm Flow Chart

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in

Table

. It should be noted that all inputs for the six modes are at

TTL levels. The power supplies required are V

and V

The V

power supply must be at 12.75V during the three

programming modes, and must be at 5V in the other three

modes. The V

power supply must be at 6.25V during the

three programming modes, and at 5V in the other three

modes.

Read Mode

The EPROM has two control functions, both of which must

be logically active in order to obtain data at the outputs. Chip

Enable (CE /PGM ) is the power control and should be used

for device selection. Output Enable (OE) is the output control

and should be used to gate data to the output pins, indepen-

dent of device selection. Assuming that addresses are

stable, address access time (t

ACC

) is equal to the delay from

CE to output (t

). Data is available at the outputs t

after

the falling edge of OE, assuming that CE /PGM has been low

and addresses have been stable for at least t

ACC

-t

Standby Mode

The EPROM has a standby mode which reduces the active

power dissipation by over 99%, from of 65 mW to 0.55 mW.

The EPROM is placed in the standby mode by applying a

DS010836-6

FIGURE 1.

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Functional Description (Continued)

CMOS high signal to the CE/PGM input. When in standby

mode, the outputs are in a high impedance state, indepen-

dent of the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL

high signal to the OE input. When in output disable all cir-

cuitry is enabled, except the outputs are in a high impedance

state (TRI-STATE).

Output OR-Typing

Because the EPROM is usually used in larger memory ar-

rays, Fairchild has provided a 2-line control function that ac-

commodates this use of multiple memory connections. The

2-line control function allows for:

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not

occur.

To most efficiently use these two control lines, it is recom-

mended that CE /PGM be decoded and used as the primary

device selecting function, while OE be made a common con-

nection to all devices in the array and connected to the

READ line from the system control bus. This assures that all

deselected memory devices are in their low power standby

modes and that the output pins are active only when data is

desired from a particular memory device.

Programming

CAUTION: Exceeding 14V on pin 1 (V

) will damage the

EPROM.

Initially, and after each erasure, all bits of the EPROM are in

the “1’s” state. Data is introduced by selectively program-

ming “0’s” into the desired bit locations. Although only “0’s”

will be programmed, both “1’s” and “0’s” can be presented in

the data word. The only way to change a “0” to a “1” is by ul-

traviolet light erasure.

The EPROM is in the programming mode when the V

PP-

power supply is at 12.75V and OE is at V

. It is required that

at least a 0.1 µF capacitor be placed across V

ground to suppress spurious voltage transients which may

damage the device. The data to be programmed is applied 8

bits in parallel to the data output pins. The levels required for

the address and data inputs are TTL.

When the address and data are stable, an active low, TTL

program pulse is applied to the CE /PGM input. A program

pulse must be applied at each address location to be pro-

grammed. The EPROM is programmed with the Turbo Pro-

grammingAlgorithm shown in

Figure 1

. EachAddress is pro-

grammed with a series of 50 µs pulses until it verifies good,

up to a maximum of 10 pulses. Most memory cells will pro-

gram with a single 50 µs pulse. (The standard National

Semiconductor Algorithm may also be used but it will have

longer programming time.)

The EPROM must not be programmed with a DC signal ap-

plied to the CE /PGM input.

Programming multiple EPROM in parallel with the same data

can be easily accomplished due to the simplicity of the pro-

gramming requirements. Like inputs of the parallel EPROM

may be connected together when they are programmed with

the same data.Alow level TTL pulse applied to the CE /PGM

input programs the paralleled EPROM.

Program Inhibit

Programming multiple EPROMs in parallel with different data

is also easily accomplished. Except for CE/PGM all like in-

puts (including OE) of the parallel EPROMs may be com-

mon. A TTL low level program pulse applied to an EPROM’s

CE /PGM input with V

at 12.75V will program that

EPROM. A TTL high level CE /PGM input inhibits the other

EPROMs from being programmed.

Program Verify

A verify should be performed on the programmed bits to de-

termine whether they were correctly programmed. The verify

may be performed with V

at 12.75V. V

must be at V

except during programming and program verify.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window to

prevent unintentional erasure. Covering the window will also

prevent temporary functional failure due to the generation of

photo currents.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s identification code to aid

in programming. When the device is inserted in an EPROM

programmer socket, the programmer reads the code and

then automatically calls up the specific programming algo-

rithm for the part. This automatic programming control is only

possible with programmers which have the capability of

reading the code.

The Manufacturer’s Identification code, shown in

Table 2

specifically identifies the manufacturer and device type. The

code for NM27C040 is “8F08”, where “8F” designates that it

is made by Fairchild Semiconductor, and “08” designates a 4

Megabit (512K x 8) part.

The code is accessed by applying 12V ±0.5V to address pin

A9. Addresses A1–A8, A10–A18, and all control pins are

held at V

. Address pin A0 is held at V

for the manufactur-

er’s code, and held at V

for the device code. The code is

read on the eight data pins, O

–O

. Proper code access is

only guaranteed at 25˚C ±5˚C.

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that era-

sure begins to occur when exposed to light with wavelengths

shorter than approximately 4000Angstroms (Ar). It should be

noted that sunlight and certain types of fluorescent lamps

have wavelengths in the 3000Ar–4000Arrange.

The recommended erasure procedure for the EPROM is ex-

posure to short wave ultraviolet light which has a wavelength

of 2537Ar. The integrated dose (i.e., UV intensity X exposure

time) for erasure should be minimum of 15W-sec/cm

The EPROM should be placed within 1 inch of the lamp

tubes during erasure. Some lamps have a filter on their

tubes which should be removed before erasure.

An erasure system should be calibrated periodically. The dis-

tance from lamp to device should be maintained at one inch.

The erasure time increase as the square of the distance from

the lamp. (If distance is doubled the erasure time increases

by factor of 4.) Lamps lose intensity as they age. When a

lamp is changed, the distance has changed, or the lamp has

aged, the system should be checked to make certain full era-

sure is occurring. Incomplete erasure will cause symptoms

that can be misleading. Programmers, components, and

even system designs have been erroneously suspected

when incomplete erasure was the problem.

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Functional Description (Continued)

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require

careful decoupling of the devices. The supply current, I

has three segments that are of interest to the system de-

signer: the standby current level, the active current level, and

the transient current peaks that are produced by voltage

transitions on input pins. The magnitude of these transient

current peaks is dependent of the output capacitance load-

ing of the device. The associated V

transient voltage

peaks can be suppressed by properly selected decoupling

capacitors. It is recommended that at least a 0.1 µF ceramic

capacitor be used on every device between V

and GND.

This should be a high frequency capacitor of low inherent in-

ductance. In addition, at least a 4.7 µF bulk electrolytic ca-

pacitor should be used between V

and GND for each eight

devices. The bulk capacitor should be located near where

the power supply is connected to the array. The purpose of

the bulk capacitor is to overcome the voltage drop caused by

the inductive effects of the PC board traces.

Mode Selection

The modes of operation of the NM27C040 are listed in

Table 1

. A single 5V power supply is required in the read mode.All inputs

are TTL levels except for V

and A9 for device signature.

TABLE 1. Modes Selection

Pins CE /PGM OE V

Outputs

Mode

Read V

X 5.0V D

OUT

(Note 15)

Output Disable X V

X 5.0V High Z

Standby V

X X 5.0V High Z

Programming V

12.75V 6.25V D

Program Verify X V

12.75V 6.25V D

OUT

Program Inhibit V

12.75V 6.25V High Z

Note 15: X can be VIL or VH

TABLE 2. Manufacturer’s Identification Code

Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex

(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data

Manufacturer

Code V

12V100011118F

Device Code V

12V0000100008

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Book

Extract

End

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THIS PAGE IS IGNORED IN THE DATABOOK

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Physical Dimensions inches (millimeters) unless otherwise noted

32-Lead EPROM Ceramic Dual-In-Line Package (Q)

Order Number NM27C040QXXX

Package Number J32AQ

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

32-Lead PLCC Package (V)

Order Number NM27C040VXXX

Package Number VA32A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-

VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-

CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, and (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

Fairchild Semiconductor

Corporation

Americas

Customer Response Center

Tel: 1-888-522-5372

www.fairchildsemi.com

Fairchild Semiconductor

Europe Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 8 141-35-0

English Tel: +44 (0) 1 793-85-68-56

Italy Tel: +39 (0) 2 57 5631

Fairchild Semiconductor

Hong Kong Ltd.

13th Floor, Straight Block,

Ocean Centre, 5 Canton Rd.

Tsimshatsui, Kowloon

Hong Kong

Tel: +852 2737-7200

Fax: +852 2314-0061

National Semiconductor

Japan Ltd.

Tel: 81-3-5620-6175

Fax: 81-3-5620-6179

32-Lead TSOP Package

Order Number NM27C040TXXX

Package Number MBH32A

NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.