LTC2301/LTC2305 1-/2-Channel, 12-Bit ADCs with I2C Compatible Interface DESCRIPTION FEATURES n n n n n n n n n n n n n n 12-Bit Resolution Low Power: 1.5mW at 1ksps, 35W Sleep Mode 14ksps Throughput Rate Internal Reference Low Noise: SNR = 73.5dB Guaranteed No Missing Codes Single 5V Supply 2-wire I2C Compatible Serial Interface with 9 Addresses Plus One Global for Synchronization Fast Conversion Time: 1.3s 1-Channel (LTC2301) and 2-Channel (LTC2305) Versions Unipolar or Bipolar Input Ranges (Software Selectable) Internal Conversion Clock Guaranteed Operation from -40C to 125C (MSOP Package) 12-Pin 4mm x 3mm DFN and 12-Pin MSOP Packages APPLICATIONS n n n n n n Industrial Process Control Motor Control Accelerometer Measurements Battery Operated Instruments Isolated and/or Remote Data Acquisition Power Supply Monitoring BLOCK DIAGRAM The LTC(R)2301/LTC2305 are low noise, low power, 1-/2-channel, 12-bit successive approximation ADCs with an I2C compatible serial interface. These ADCs include an internal reference and a fully differential sample-andhold circuit to reduce common mode noise. The LTC2301/ LTC2305 operate from an internal clock to achieve a fast 1.3s conversion time. The LTC2301/LTC2305 operate from a single 5V supply and draw just 300A at a throughput rate of 1ksps. The ADC enters nap mode when not converting, reducing the power dissipation. The LTC2301/LTC2305 are available in small 12-pin 4mm x 3mm DFN and 12-pin MSOP packages. The internal 2.5V reference further reduces PCB board space requirements. The low power consumption and small size make the LTC2301/LTC2305 ideal for battery operated and portable applications, while the 2-wire I2C compatible serial interface makes these ADCs a good match for space-constrained systems. 12-Bit I2C ADC Family Input Channels Part Number 1 2 8 LTC2301 LTC2305 LTC2309 L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 5V Integral Nonlinearity vs Output Code (LTC2305) 10F 0.1F 1.00 0.75 VDD CH0(IN +) ANALOG INPUT 0V TO 4.096V UNIPOLAR CH1(IN+) 2.048V BIPOLAR ANALOG INPUT MUX + AD1 AD0 12-BIT SAR ADC - I2C PORT 0.50 INL (LSB) LTC2301 LTC2305 SCL SDA 0.00 -0.25 VREF INTERNAL 2.5V REF 0.25 -0.50 2.2F -0.75 PIN NAMES IN PARENTHESES REFER TO LTC2301 GND 0.1F 23015 TA01a REFCOMP 10F -1.00 0 1024 2048 3072 OUTPUT CODE 4096 23015 TA01b 23015fb 1 LTC2301/LTC2305 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD) ................................ -0.3V to 6.0V Analog Input Voltage (Note 3) CH0(IN+), CH1(IN-), REF, REFCOMP .............(GND - 0.3V) to (VDD + 0.3V) Digital Input Voltage..........(GND - 0.3V) to (VDD + 0.3V) Digital Output Voltage .......(GND - 0.3V) to (VDD + 0.3V) Power Dissipation ...............................................500mW Operating Temperature Range LTC2301C/LTC2305C ............................... 0C to 70C LTC2301I/LTC2305I.............................. -40C to 85C LTC2301H/LTC2305H (Note 13) ......... -40C to 125C Storage Temperature Range................... -65C to 150C PIN CONFIGURATION LTC2305 LTC2301 TOP VIEW TOP VIEW GND 1 12 AD0 GND 1 12 AD0 SDA 2 11 AD1 SDA 2 11 AD1 SCL 3 10 VDD SCL 3 GND 4 9 GND GND 4 9 GND CH0 5 8 REFCOMP IN+ 5 8 REFCOMP VREF IN- 6 7 VREF 13 6 CH1 7 13 10 VDD DE PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN DE PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB LTC2305 LTC2301 TOP VIEW GND SDA SCL GND CH0 CH1 1 2 3 4 5 6 TOP VIEW 12 11 10 9 8 7 AD0 AD1 VDD GND REFCOMP VREF MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 150C, JA = 130C/W GND SDA SCL GND IN+ IN- 1 2 3 4 5 6 12 11 10 9 8 7 AD0 AD1 VDD GND REFCOMP VREF MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 150C, JA = 130C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2301CDE#PBF LTC2301CDE#TRPBF 2301 12-Lead (3mm x 4mm) Plastic DFN 0C to 70C LTC2301IDE#PBF LTC2301IDE#TRPBF 2301 12-Lead (3mm x 4mm) Plastic DFN -40C to 85C LTC2305CDE#PBF LTC2305CDE#TRPBF 2305 12-Lead (3mm x 4mm) Plastic DFN 0C to 70C LTC2305IDE#PBF LTC2305IDE#TRPBF 2305 12-Lead (3mm x 4mm) Plastic DFN -40C to 85C LTC2301CMS#PBF LTC2301CMS#TRPBF 2301 12-Lead Plastic MSOP 0C to 70C LTC2301IMS#PBF LTC2301IMS#TRPBF 2301 12-Lead Plastic MSOP -40C to 85C LTC2301HMS#PBF LTC2301HMS#TRPBF 2301 12-Lead Plastic MSOP -40C to 125C LTC2305CMS#PBF LTC2305CMS#TRPBF 2305 12-Lead Plastic MSOP 0C to 70C 23015fb 2 LTC2301/LTC2305 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2305IMS#PBF LTC2305IMS#TRPBF 2305 12-Lead Plastic MSOP -40C to 85C LTC2305HMS#PBF LTC2305HMS#TRPBF 2305 12-Lead Plastic MSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ CONVERTER AND MULTIPLEXER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX l 0.4 1 LSB Differential Linearity Error l 0.3 1 LSB Bipolar Zero Error l 0.5 8 l Resolution (No Missing Codes) Integral Linearity Error (Note 5) (Note 6) 12 Bits Bipolar Zero Error Drift Unipolar Zero Error 0.002 l (Note 6) UNITS 0.7 LSB LSB/C 6 LSB Unipolar Zero Error Drift 0.002 Unipolar Zero Error Match (LTC2305) 0.1 1 LSB l l 1 0.9 10 9 LSB LSB l l 0.5 0.7 Bipolar Full-Scale Error External Reference (Note 7) REFCOMP = 4.096V (Note 7) Bipolar Full-Scale Error Drift External Reference Unipolar Full-Scale Error External Reference (Note 7) REFCOMP = 4.096V (Note 7) Unipolar Full-Scale Error Drift External Reference LSB/C 0.05 LSB/C 10 6 0.05 Unipolar Full-Scale Error Match (LTC2305) 0.1 LSB LSB LSB/C 2 LSB ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (CH0, CH1, IN+) (Note 8) l -0.05 MIN TYP REFCOMP V VIN- Absolute Input Range (CH0, CH1, IN-) Unipolar (Note 8) Bipolar (Note 8) l -0.05 -0.05 0.25 * REFCOMP 0.75 * REFCOMP V V VIN+ - VIN- Input Differential Voltage Range VIN = VIN+ - VIN- (Unipolar) VIN = VIN+ - VIN- (Bipolar) l IIN Analog Input Leakage Current CIN Analog Input Capacitance CMRR Input Common Mode Rejection Ratio 0 to REFCOMP REFCOMP/2 l Sample Mode Hold Mode MAX UNITS V V 1 A 55 5 pF pF 70 dB 23015fb 3 LTC2301/LTC2305 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = -1dBFS. (Notes 4,9) SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-(Noise + Distortion) Ratio fIN = 1kHz l 71 73.4 SNR Signal-to-Noise Ratio THD Total Harmonic Distortion fIN = 1kHz l 71 73.5 fIN = 1kHz l SFDR Spurious Free Dynamic Range fIN = 1kHz, First 5 Harmonics l Channel-to-Channel Isolation -91 79 MAX UNITS dB dB -77 dB 92 dB fIN = 1kHz -109 dB Full Linear Bandwidth fIN = 1kHz 700 kHz -3dB Input Linear Bandwidth (Note 10) 25 MHz 13 ns 240 ns Aperture Delay Transient Response Full-Scale Step INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 4) PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 VREF Output Tempco IOUT = 0 VREF Output Impedance -0.1mA IOUT 0.1mA VREFCOMP Output Voltage IOUT = 0 VREF Line Regulation VDD = 4.75V to 5.25V l MIN TYP MAX UNITS 2.46 2.50 2.54 V 25 ppm/C 8 k 4.096 V 0.8 mV/V I2C INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 4) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage l TYP MAX 2.85 UNITS V VIL Low Level Input Voltage l VIHA High Level Input Voltage for Address Pins A1, A0 l VILA Low Level Input Voltage for Address Pins A1, A0 l 0.25 RINH Resistance from A1, A0 to VDD to Set Chip Address Bit to 1 l 10 k RINL Resistance from A1, A0 to GND to Set Chip Address Bit to 0 l 10 k RINF Resistance from A1, A0 to GND or VDD to Set Chip Address Bit to Float l 2 II Digital Input Current VIN = VDD l -10 VHYS Hysteresis of Schmitt Trigger Inputs (Note 8) l 0.25 VOL Low Level Output Voltage (SDA) I = 3mA l tOF Output Fall Time VIN(MIN) to VIL(MAX) Bus Load CB 10pF to 400pF (Note 11) l tSP Input Spike Suppression CCAX External Capacitance Load on Chip Address Pins (A1, A0) for Valid Float 1.5 4.75 V V V M 10 A V 0.4 V 250 ns l 50 ns l 10 pF 20 + 0.1CB 23015fb 4 LTC2301/LTC2305 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN l 4.75 TYP MAX UNITS VDD Supply Voltage 5 5.25 V IDD Supply Current Nap Mode Sleep Mode 14ksps Sample Rate SLP Bit = 0, Conversion Done SLP Bit = 1, Conversion Done l l l 2.3 225 7 3.5 400 15 mA A A PD Power Dissipation Nap Mode Sleep Mode 14ksps Sample Rate SLP Bit = 0, Conversion Done SLP Bit = 1, Conversion Done l l l 11.5 1.125 35 17.5 2 75 mW mW W I2C TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 400 kHz fSCL SCL Clock Frequency l tHD(SDA) Hold Time (Repeated) START Condition l 0.6 s tLOW LOW Period of the SCL Pin l 1.3 s tHIGH HIGH Period of the SCL Pin l 0.6 s tSU(STA) Set-Up Time for a Repeated START Condition l 0.6 s tHD(DAT) Data Hold Time l 0 tSU(DAT) Data Set-Up Time l 100 tr Rise Time for SDA/SCL Signals (Note 11) l 20 + 0.1CB 300 ns tf Fall Time for SDA/SCL Signals (Note 11) l 20 + 0.1CB 300 ns 0.6 s 1.3 s tSU(STO) Set-Up Time for STOP Condition l tBUF Bus Free Time Between a Second START Condition l 0.9 s ns ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS fSMPL Throughput Rate (Successive Reads) tCONV Conversion Time tACQ Acquisition Time (Note 8) tREFWAKE REFCOMP Wakeup Time (Note 12) CREFCOMP = 10F, CREF = 2.2F MIN TYP l l MAX 14 1.3 l 200 UNITS ksps 1.6 s 240 ns ms 23015fb 5 LTC2301/LTC2305 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. These products can handle input currents greater than 100mA below ground or above VDD without latchup. Note 4: VDD = 5V, fSMPL = 14kHz, internal reference unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Bipolar zero error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Unipolar zero error is the offset voltage measured from 0.5 LSB when the output code flickers between 0000 0000 0000 and 0000 0000 0001. Note 7: Full-scale bipolar error is the worst-case of -FS or FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. Note 8: Guaranteed by design, not subject to test. Note 9: All specifications in dB are referred to a full-scale 2.048V input with a 2.5V reference voltage. Note 10: Full linear bandwidth is defined as the full-scale input frequency at which the SINAD degrades to 60dB or 10 bits of accuracy. Note 11: CB = capacitance of one bus line in pF (10pF CB 400pF) Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin to settle within 0.5 LSB at 12-bit resolution of its final value after waking up from sleep mode. Note 13: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105C. 23015fb 6 LTC2301/LTC2305 TYPICAL PERFORMANCE CHARACTERISTICS (LTC2301) TA = 25C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted. 1.00 1.00 0.75 0.75 0.50 0.50 0.25 0.25 0.00 -0.25 0.00 -0.25 -0.50 -0.50 -0.75 -0.75 -1.00 1024 0 2048 3072 OUTPUT CODE 4096 1kHz Sine Wave 8192 Point FFT Plot MAGNITUDE (dB) Differential Nonlinearity vs Output Code DNL (LSB) INL (LSB) Integral Nonlinearity vs Output Code -1.00 1024 0 2048 3072 OUTPUT CODE 4096 23015 G01 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 SNR = 73.2 dB SINAD = 73.1 dB THD = -90dB 0 1 2 3 4 5 FREQUENCY (kHz) 23015 G02 Supply Current vs Sampling Frequency 7 6 23015 G03 Offset Error vs Temperature Full-Scale Error vs Temperature 2.5 1.5 4 2.0 1.0 2 1.5 1.0 0.5 0.5 BIPOLAR 0.0 UNIPOLAR -0.5 0 0.1 1 10 SAMPLING FREQUENCY (ksps) 100 FULL-SCALE ERROR (LSB) OFFSET ERROR (LSB) SUPPLY CURRENT (mA) UNIPOLAR -1.0 -50 -25 0 50 25 75 TEMPERATURE (C) 100 23015 G04 BIPOLAR 0 -2 -4 -6 -50 125 -25 0 50 25 75 TEMPERATURE (C) 100 23015 G06 23015 G05 Supply Current vs Temperature Analog Input Leakage Current vs Temperature Sleep Current vs Temperature 2.4 125 10 1000 1.8 1.6 800 LEAKAGE CURRENT (nA) 2.2 SLEEP CURRENT (A) SUPPLY CURRENT (mA) 900 8 6 4 2 700 600 500 400 300 200 100 1.4 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 23015 G07 0 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 23015 G08 0 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 23015 G09 23015fb 7 LTC2301/LTC2305 TYPICAL PERFORMANCE CHARACTERISTICS (LTC2305) TA = 25C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted. Differential Nonlinearity vs Output Code 1.00 0.75 0.75 0.50 0.50 0.25 0.25 0.00 -0.25 0.00 -0.25 -0.50 -0.50 -0.75 -0.75 -1.00 -1.00 1024 0 2048 3072 OUTPUT CODE 1kHz Sine Wave 8192 Point FFT Plot 4096 1024 0 2048 3072 OUTPUT CODE 4096 Supply Current vs Sampling Frequency Offset Error vs Temperature FULL-SCALE ERROR (LSB) OFFSET ERROR (LSB) 0.5 0.0 UNIPOLAR 0.5 1 10 SAMPLING FREQUENCY (ksps) 100 2 3 4 5 FREQUENCY (kHz) -0.5 -50 -25 0 50 25 75 TEMPERATURE (C) 100 2 BIPOLAR 0 UNIPOLAR -2 -4 -6 -50 125 -25 0 50 25 75 TEMPERATURE (C) 100 Analog Input Leakage Current vs Temperature Sleep Current vs Temperature 2.4 125 23015 G15 23015 G14 23015 G13 Supply Current vs Temperature 7 6 Full-Scale Error vs Temperature BIPOLAR 0 0.1 1 4 2.0 1.0 0 23015 G12 1.0 2.5 1.5 SNR = 73.2 dB SINAD = 73.1 dB THD = -90dB 23015 G11 23015 G10 SUPPLY CURRENT (mA) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 MAGNITUDE (dB) 1.00 DNL (LSB) INL (LSB) Integral Nonlinearity vs Output Code 1000 10 800 1.8 1.6 LEAKAGE CURRENT (nA) 2.2 SLEEP CURRENT (A) SUPPLY CURRENT (mA) 900 8 6 4 700 600 500 400 CH(ON) 300 CH(OFF) 200 2 100 1.4 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 23015 G16 0 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 23015 G17 0 -50 -25 25 75 0 50 TEMPERATURE (C) 100 125 23015 G18 23015fb 8 LTC2301/LTC2305 PIN FUNCTIONS (LTC2301) GND (Pins 1, 4, 9): Ground. All GND pins must be connected to a solid ground plane. SDA (Pin 2): Bidirectional Serial Data Line of the I2C Interface. In transmitter mode (read), the conversion result is output at the SDA pin, while in receiver mode (write), the DIN word is input at the SDA pin to configure the ADC. The pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to VDD) during the data output mode. SCL (Pin 3): Serial Clock Pin of the I2C Interface. The LTC2301 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. IN+, IN- (Pins 5, 6): Positive (IN+) and negative (IN-) differential analog inputs. VREF (Pin 7): 2.5V Reference Output. Bypass to GND with a minimum 2.2F ceramic capacitor. The internal reference may be overdriven by an external 2.5V reference at this pin. REFCOMP (Pin 8): Reference Buffer Output. Bypass to GND with 10F and 0.1F ceramic capacitors in parallel. Nominal output voltage is 4.096V. The internal reference buffer driving this pin is disabled by grounding VREF, allowing REFCOMP to be overdriven by an external source (see Figure 5c). VDD (Pin 10): 5V Analog Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with 10F and 0.1F ceramic capacitors in parallel. AD1 (Pin 11): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) address control bit for the device I2C address. See Table 2 for address selection. AD0 (Pin 12): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) address control bit for the device I2C address. See Table 2 for address selection. GND (Pin 13 - DFN Package Only): Exposed Pad Ground. Must be soldered directly to ground plane. 23015fb 9 LTC2301/LTC2305 PIN FUNCTIONS (LTC2305) GND (Pins 1, 4, 9): Ground. All GND pins must be connected to a solid ground plane. SDA (Pin 2): Bidirectional Serial Data Line of the I2C Interface. In transmitter mode (read), the conversion result is output at the SDA pin, while in receiver mode (write), the DIN word is input at the SDA pin to configure the ADC. The pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to VDD) during the data output mode. SCL (Pin 3): Serial Clock Pin of the I2C Interface. The LTC2305 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. CH0-CH1 (Pins 5, 6): Channel 0 and Channel 1 Analog Inputs. CH0 and CH1 can be configured as single-ended or differential input channels. See the Analog Input Multiplexer section. VREF (Pin 7): 2.5V Reference Output. Bypass to GND with a minimum 2.2F ceramic capacitor. The internal reference may be overdriven by an external 2.5V reference at this pin. REFCOMP (Pin 8): Reference Buffer Output. Bypass to GND with 10F and 0.1F ceramic capacitors in parallel. Nominal output voltage is 4.096V. The internal reference buffer driving this pin is disabled by grounding VREF, allowing REFCOMP to be overdriven by an external source (see Figure 5c). VDD (Pin 10): 5V Analog Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with 10F and 0.1F ceramic capacitors in parallel. AD1 (Pin 11): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) address control bit for the device I2C address. See Table 2 for address selection. AD0 (Pin 12): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) address control bit for the device I2C address. See Table 2 for address selection. GND (Pin 13 - DFN Package Only): Exposed Pad Ground. Must be soldered directly to ground plane. 23015fb 10 LTC2301/LTC2305 FUNCTIONAL BLOCK DIAGRAM VDD AD1 AD0 LTC2301 LTC2305 CH0(IN+) CH1(IN-) + ANALOG INPUT MUX 12-BIT SAR ADC I2C PORT SCL 8k VREF SDA - INTERNAL 2.5V REF GAIN = 1.6384x PIN NAMES IN PARENTHESES REFER TO LTC2301 GND REFCOMP 23015 BD TIMING DIAGRAM Definition of Timing for Fast/Standard Mode Devices on the I2C Bus SDA tSU(DAT) tLOW tf tHD(SDA) tf tr tSP tr tBUF SCL tHD(SDA) S tHD(DAT) tHIGH tSU(STA) tSU(STO) Sr P S 23015 TD S = START, Sr = REPEATED START, P = STOP 23015fb 11 LTC2301/LTC2305 APPLICATIONS INFORMATION Overview The LTC2301/LTC2305 are low noise, 1-/2-channel, 12-bit successive approximation register (SAR) A/D converters with an I2C compatible serial interface. The LTC2301/ LTC2305 both include a precision internal reference. The LTC2305 includes a 2-channel analog input multiplexer (MUX) while the LTC2301 includes an input MUX that allows the polarity of the differential input to be selected. These ADCs can operate in either unipolar or bipolar mode. Unipolar mode should be used for single-ended operation with the LTC2305, since single-ended input signals are always referenced to GND. A sleep mode option is also provided to further reduce power during inactive periods. The LTC2301/LTC2305 communicate through a 2-wire I2C compatible serial interface. Conversions are initiated by signaling a STOP condition after the part has been successfully addressed for a read/write operation. The device will not acknowledge an external request until the conversion is finished. After a conversion is finished, the device is ready to accept a read/write request. Once the LTC2301/LTC2305 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conversion result. There are 12 bits of output data followed by four trailing zeros. Data is updated on the falling edges of SCL, allowing the user to reliably latch data on the rising edge of SCL. A write operation may follow the read operation by using a repeat START or a STOP condition may be given to start a new conversion. By selecting a write operation, these ADCs can be programmed by a 6-bit DIN word. The DIN word configures the MUX and programs various modes of operation. During a conversion, the internal 12-bit capacitive chargeredistribution DAC output is sequenced through a successive approximation algorithm by the SAR starting from the most significant bit (MSB) to the least significant bit (LSB). The sampled input is successively compared with binary weighted charges supplied by the capacitive DAC using a differential comparator. At the end of a conversion, the DAC output balances the analog input. The SAR contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out via the I2C interface. Programming the LTC2301 and LTC2305 The software compatible LTC2301/LTC2305/LTC2309 family features a 6-bit DIN word to program various modes of operation. Don't care bits (X) are ignored. The SDA data bits are loaded on the rising edge of SCL during a write operation, with the S/D bit loaded on the first rising edge and the SLP bit on the sixth rising edge (see Figure 7b in the I2C Interface section). The input data word for the LTC2305 is defined as follows: S/D O/S X X UNI SLP S/D = SINGLE-ENDED/DIFFERENTIAL BIT O/S = ODD/SIGN BIT UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT For the LTC2301, the input word is defined as: X O/S X X UNI SLP Analog Input Multiplexer The analog input MUX is programmed by the S/D and O/S bits of the DIN word for the LTC2305 and the O/S bit of the DIN word for the LTC2301. Table 1 and Table 2 list the MUX configurations for all combinations of the configuration bits. Figure 1a shows several possible MUX configurations and Figure 1b shows how the MUX can be reconfigured from one conversion to the next. Table 1. Channel Configuration for the LTC2305 S/D O/S CH0 CH1 0 0 + - 0 1 - + 1 0 + 1 1 + 23015fb 12 LTC2301/LTC2305 APPLICATIONS INFORMATION Driving the Analog Inputs Table 2. Channel Configuration for the LTC2301 O/S IN+ IN- 0 + - 1 - + 1 Differential + (-) - (+) { 2 Single-Ended + + CH0 CH1 CH0 CH1 LTC2305 LTC2305 GND (-) 1 Differential + (-) - (+) { CH0 CH1 Input Filtering The noise and distortion of the input amplifier and other circuitry must be considered since they will add to the ADC noise and distortion. Therefore, noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. LTC2301 23015 F01a Figure 1a. Example MUX Configurations 1st Conversion + -{ CH0 CH1 LTC2305 The analog inputs of the LTC2301/LTC2305 are easy to drive. Each of the analog inputs of the LTC2305 (CH0 and CH1) can be used as single-ended input relative to GND or as a differential pair. The analog inputs of the LTC2301 (IN+, IN-) are always configured as a differential pair. Regardless of the MUX configuration, the "+" and "-" inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors during the acquire mode. In conversion mode, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, the ADC inputs can be driven directly. Otherwise, more acquisition time should be allowed for a source with higher impedance. 2nd Conversion - + { CH0 CH1 LTC2305 GND (-) 23015 F01b Figure 1b. Changing the MUX Assignment "On the Fly" The analog inputs of the LTC2301/LTC2305 can be modeled as a 55pF capacitor (CIN) in series with a 100 resistor (RON), as shown in Figure 2a. CIN gets switched to the selected input once during each conversion. Large filter RC time constants will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (tACQ) if DC accuracy is important. When using a filter with a large CFILTER value (e.g. 1F), the inputs do not completely settle and the capacitive input switching currents are averaged into a net DC current (IDC). In this case, the analog input can be modeled by an equivalent resistance (REQ = 1/(fSMPL * CIN)) in series with an ideal voltage source (VREFCOMP/2), as shown in Figure 2b. 23015fb 13 LTC2301/LTC2305 APPLICATIONS INFORMATION The magnitude of the DC current is then approximately IDC = (VIN - VREFCOMP/2)/REQ, which is roughly proportional to VIN. To prevent large DC drops across the resistor RFILTER, a filter with a small resistor and large capacitor should be chosen. When running at the maximum throughput rate of 14ksps, the input current equals 1.5A at VIN = 4.096V, which amounts to a full-scale error of 0.5 LSBs when using a filter resistor (RFILTER) of 333. Applications requiring lower sample rates can tolerate a larger filter resistor for the same amount of full-scale error. Figures 3a and 3b show respective examples of input filtering for single-ended and differential inputs. For the single-ended case in Figure 4a, a 50 source resistor and a 2000pF capacitor to ground on the input will limit the input bandwidth to 1.6MHz. High quality capacitors and resistors should be used in the RC filter since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating Dynamic Performance Fast Fourier Transform (FFT) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling ANALOG INPUT INPUT CH0, CH1, IN+, IN- RSOURCE and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. RON = 100 50 CH0, CH1 2000pF LTC2301 LTC2305 VIN LTC2305 CIN = 55pF CFILTER REFCOMP 10F 0.1F 23015 F03a 23015 F02a Figure 2a. Analog Input Equivalent Circuit RFILTER IDC Figure 3a. Optional RC Input Filtering for Single-Ended Input 1000pF INPUT (CH0, CH1, IN+, IN-) 50 LTC2301 REQ = LTC2305 1/(fSMPL * CIN) VIN CFILTER + - DIFFERENTIAL ANALOG INPUTS CH0, IN+ 1000pF 50 LTC2301 LTC2305 CH1, IN- 1000pF VREFCOMP/2 REFCOMP 23015 F02b 10F 0.1F 23015 F03b Figure 2b. Analog Input Equivalent Circuit for Large Filter Capacitances Figure 3b. Optional RC Input Filtering for Differential Inputs 23015fb 14 LTC2301/LTC2305 APPLICATIONS INFORMATION MAGNITUDE (dB) frequency. Figure 4 shows a typical SINAD of 73.2dB with a 14kHz sampling rate and a 1kHz input. A SNR of 73.3dB can be achieved with the LTC2301/LTC2305. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 SNR = 73.2 dB SINAD = 73.1 dB THD = -90dB noise performance. The internal reference buffer can also be overdriven from 1V to VDD with an external reference at REFCOMP, as shown in Figure 5c. To do so, VREF must be grounded to disable the reference buffer. This will result in an input range of 0V to VREFCOMP in unipolar mode and 0.5 * VREFCOMP in bipolar mode. R1 8k VREF 2.5V BANDGAP REFERENCE 2.2F REFCOMP 4.096V 0 1 2 3 4 5 FREQUENCY (kHz) 7 6 REFERENCE AMP 10F R2 0.1F 23015 F04 Figure 4. 1kHz Sine Wave 8192 Point FFT Plot GND R3 LTC2301 LTC2305 Total Harmonic Distortion (THD) 23015 F05a Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: Figure 5a. LTC2301/LTC2305 Reference Circuit 5V 0.1F 2 2 2 V + V3 + V4 ... + VN THD = 20log 2 V1 2 VIN LT1790A-2.5 VOUT VREF 2.2F where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. LTC2301 LTC2305 REFCOMP 10F 0.1F GND Internal Reference The LTC2301/LTC2305 have an on-chip, temperature compensated bandgap reference that is factory trimmed to 2.5V (Refer to Figure 5a). It is internally connected to a reference amplifier and is available at VREF (Pin 7). VREF should be bypassed to GND with a 2.2F ceramic capacitor to minimize noise. An 8k resistor is in series with the output so that it can be easily overdriven by an external reference if more accuracy and/or lower drift are required, as shown in Figure 5b. The reference amplifier gains the VREF voltage by 1.638 to 4.096V at REFCOMP. To compensate the reference amplifier, bypass REFCOMP with a 10F ceramic capacitor in parallel with a 0.1F ceramic capacitor for best 23015 F05b Figure 5b. Using the LT1790A-2.5 as an External Reference 5V 0.1F VREF VIN LTC2301 LTC2305 LT1790A-4.096 VOUT REFCOMP 10F 0.1F GND 23015 F05c Figure 5c. Overdriving REFCOMP Using the LT1790A-4.096 23015fb 15 LTC2301/LTC2305 APPLICATIONS INFORMATION Internal Conversion Clock START Condition The internal conversion clock is factory trimmed to achieve a typical conversion time (tCONV) of 1.3s and a maximum conversion time of 1.6s over the full operating temperature range. I2C Interface STOP Condition SDA S SCL SDA SCL P 23015 F06 Figure 6. Timing Diagrams of START and STOP Conditions I2C The LTC2301/LTC2305 communicate through an interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. The connected devices can only pull the serial data line (SDA) LOW and can never drive it HIGH. SDA is required to be externally connected to the supply through a pull-up resistor. When the data line is not being driven low, it is HIGH. Data on the I2C bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. The VDD power should not be removed from the LTC2301/ LTC2305 when the I2C bus is active to avoid loading the I2C bus lines through the internal ESD protection diodes. Each device on the I2C bus is recognized by a unique address stored in the device and can only operate either as a transmitter or receiver, depending on the function of the device. A device can also be considered as a master or a slave when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit the transfer. Devices addressed by the master are considered slaves. The LTC2301/LTC2305 can only be addressed as slaves. Once addressed, they can receive configuration bits (DIN word) or transmit the last conversion result. The serial clock line (SCL) is always an input to the LTC2301/LTC2305 and the serial data line (SDA) is bidirectional. These devices support the standard mode and the fast mode for data transfer speeds up to 400kbits/s (see Timing Diagram section for definition of the I2C timing). The START and STOP Conditions Referring to Figure 6, a START (S) condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP (P) condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free after a STOP condition is generated. START and STOP conditions are always generated by the master. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START timing is functionally identical to the START and is used for writing and reading from the device before the initiation of a new conversion. Data Transferring After the START condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA LOW or issue a Not Acknowledge (NACK) by leaving the SDA line high impedance (the external pull-up resistor will hold the line HIGH). Change of data only occurs while the SCL line is LOW. Data Format After a START condition, the master sends a 7-bit address followed by a read/write (R/W) bit. The R/W bit is 1 for a read request and 0 for a write request. If the 7-bit address matches one of the LTC2301/LTC2305's 9 pinselectable addresses (see Table 2), the ADC is selected. When the ADC is addressed during a conversion, it will not acknowledge R/W requests and will issue a NACK by leaving the SDA line HIGH. If the conversion is complete, the LTC2301/LTC2305 issues an ACK by pulling the SDA line LOW. The LTC2301/LTC2305 has two registers. The 12-bit wide output register contains the last conversion result. The 6-bit wide input register configures the input MUX and the operating mode of the ADC. 23015fb 16 LTC2301/LTC2305 APPLICATIONS INFORMATION Output Data Format The output register contains the last conversion result. After each conversion is completed, the device automatically enters either nap or sleep mode depending on the setting of the SLP bit (see Nap Mode and Sleep Mode sections). When the LTC2301/LTC2305 is addressed for a read operation, it acknowledges by pulling SDA LOW and acts as a transmitter. The master/receiver can read up to two bytes from the LTC2301/LTC2305. After a complete read operation of 2 bytes, a STOP condition is needed to initiate a new conversion. The device will NACK subsequent read operations while a conversion is being performed. The data output stream is 16 bits long and is shifted out on the falling edges of SCL (see Figure 7a). The first bit is the MSB and the 12th bit is the LSB of the conversion 1 2 3 4 5 6 7 8 9 result. The remaining four bits are zero. Figures 13 and 14 are the transfer characteristics for the bipolar and unipolar modes. Data is output on the SDA line in 2's complement format for bipolar readings and in straight binary for unipolar readings. Input Data Format When the LTC2301/LTC2305 is addressed for a write operation, it acknowledges by pulling SDA LOW during the LOW period before the 9th cycle and acts as a receiver. The master/transmitter can then send 1 byte to program the device. The input byte consists of the 6-bit DIN word followed by two bits that are ignored by the ADC and are considered don't cares (X) (see Figure 7b). The input bits are latched on the rising edge of SCL during the write operation. 1 2 3 4 5 6 7 8 9 *** SCL SDA A6 A5 A4 A3 A2 A1 A0 B11 R/W START BY MASTER ACK BY ADC B10 B9 B8 B7 B6 B5 *** B4 ACK BY MASTER MOST SIGNIFICANT DATA BYTE ADDRESS FRAME READ 1 BYTE 1 SCL (CONTINUED) 2 3 4 5 6 7 8 9 *** CONVERSION INITIATED SDA (CONTINUED) *** B3 B2 B1 STOP BY MASTER B0 NACK BY MASTER LEAST SIGNIFICANT DATA BYTE READ 1 BYTE 23015 F07a Figure 7a. Timing Diagram for Reading from the LTC2301/LTC2305 NOTE: S/D BIT IS A DON'T CARE (X) FOR THE LTC2301 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL CONVERSION INITIATED SDA A6 A5 A4 A3 A2 A1 START BY MASTER A0 S/D R/W ACK BY ADC ADDRESS FRAME O/S X X UNI SLP X DIN WORD WRITE 1 BYTE X ACK BY ADC STOP BY MASTER 23015 F07b Figure 7b. Timing Diagram for Writing to the LTC2301/LTC2305 23015fb 17 LTC2301/LTC2305 APPLICATIONS INFORMATION After power-up, the ADC initiates an internal reset cycle which sets the DIN word to all 0s (S/D=O/S=UNI=SLP=0). A write operation may be performed if the default state of the ADC's configuration is not desired. Otherwise, the ADC must be properly addressed and followed by a STOP condition to initiate a conversion. Table 2. Address Assignment Initiating a New Conversion The LTC2301/LTC2305 awakens from either nap or sleep when properly addressed for a read/write operation. A STOP command may then be issued after performing the read/write operation to trigger a new conversion. The LTC2301/LTC2305 have two address pins (AD0 and AD1) that may be tied high, low or left floating to enable one of the 9 possible addresses (see Table 2). In addition to the configurable addresses listed in Table 2, the LTC2301/LTC2305 also contain a global address (1101011) which may be used for synchronizing multiple LTC2301/LTC2305s or other I2C LTC230X SAR ADCs (see Synchronizing Multiple LTC2301/LTC2305s with Global Address Call section). CONVERSION NAP R ACK READ DATA OUTPUT P ADDRESS LOW LOW 0001000 LOW Float 0001001 LOW HIGH 0001010 Float HIGH 0001011 Float Float 0011000 Float LOW 0011001 HIGH LOW 0011010 HIGH Float 0011011 HIGH HIGH 0101000 In applications where the same input channel is sampled each cycle, conversions can be continuously performed and read without a write cycle (see Figure 8). The DIN word remains unchanged from the last value written into the device. If the device has not been written to since powerup, the DIN word defaults to all 0s (S/D=O/S=UNI=SLP=0). At the end of a read operation, a STOP condition may be given to start a new conversion. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not concluded and a valid address selects the device, the LTC2301/LTC2305 generates a NACK signal indicating the conversion cycle is in progress. LTC2301/LTC2305 Address 7-BIT ADDRESS AD0 Continuous Read Issuing a STOP command after the 8th SCL clock pulse of the address frame and before the completion of a read/write operation will also initiate new conversion, but the output result may not be valid due to lack of adequate acquisition time (see Acquisition section). S AD1 S CONVERSION 7-BIT ADDRESS R NAP ACK READ DATA OUTPUT P CONVERSION 23015 F08 Figure 8. Consecutive Reading with the Same Configuration 23015fb 18 LTC2301/LTC2305 APPLICATIONS INFORMATION Continuous Read/Write Once the conversion cycle is complete, the LTC2301/ LTC2305 can be written to and then read from using the repeated START (Sr) command. Figure 9 shows a cycle which begins with a data write, a repeated START, followed by a read and concluded with a STOP command. After all 16 bits are read out, a conversion may be initiated by issuing a STOP command. The following conversion will be performed using the newly programmed data. Nap Mode Synchronizing Multiple LTC2301/LTC2305s with a Global Address Call In applications where several LTC2301/LTC2305s or other I2C SAR ADCs from Linear Technology Corporation are used on the same I2C bus, all converters can be synchronized through the use of a global address call. Prior to issuing the global address call, all converters must have completed a conversion cycle. The master then issues a START, followed by the global address 1101011, and a write request. All converters will be selected and acknowl- S 7-BIT ADDRESS CONVERSION NAP W ACK WRITE edge the request. The master then sends a write byte (optional) followed by the STOP command. This will update the channel selection (optional) and simultaneously initiate a conversion for all ADCs on the bus (see Figure 10). In order to synchronize multiple converters without changing the channel, a STOP command may be issued after acknowledgement of the global write command. Global read commands are not allowed and the converters will NACK a global read request. Sr DATA INPUT The ADCs enter nap mode after a conversion is complete (tCONV) if the SLP bit is set to a logic 0. The supply current decreases to 225A in nap mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. For example, the LTC2301/LTC2305 draw an average of 300A at a 1ksps sampling rate. The LTC2301/LTC2305 keep only the reference (VREF) and reference buffer (REFCOMP) circuitry active when in nap mode. 7-BIT ADDRESS R ADDRESS ACK READ DATA OUTPUT P CONVERSION 23015 F09 Figure 9. Write, Read, START Conversion SCL SDA S CONVERSION LTC2301/LTC2305 LTC2301/LTC2305 GLOBAL ADDRESS W NAP ACK LTC2301/LTC2305 WRITE (OPTIONAL) DATA OUTPUT P CONVERSION OF ALL LTC2301/05s 23015 F10 Figure 10. Synchronize Multiple LTC2301/LTC2305s with a Global Address Call 23015fb 19 LTC2301/LTC2305 APPLICATIONS INFORMATION Sleep Mode performed, acquisition of the input signal begins on the rising edge of the 9th clock pulse following the address frame, as shown in Figure 12a. The ADCs enter sleep mode after a conversion is complete (tCONV) if the SLP bit is set to a logic 1. The ADCs draw only 7A in sleep mode, provided that none of the digital inputs are switching. When the LTC2301/LTC2305 are properly addressed, the ADCs are released from sleep mode and require 200ms (tREFWAKE) to wake up and charge the respective 2.2F and 10F bypass capacitors on the VREF and REFCOMP pins. A new conversion should not be initiated before this time, as shown in Figure 11. If a write operation is being performed, acquisition of the input signal begins on the falling edge of the sixth clock cycle after the DIN word has been shifted in, as shown in Figure 12b. The LTC2301/LTC2305 will acquire the signal from the input channel that was most recently programmed by the DIN word. A minimum of 240ns is required to acquire the input signal before initiating a new conversion. Acquisition Board Layout and Bypassing The LTC2301/LTC2305 begin acquiring the input signal at different instances depending on whether a read or write operation is being performed. If a read operation is being To obtain the best performance, a printed circuit board with a solid ground plane is required. Layout for the printed board should ensure digital and analog signal lines are S 7-BIT ADDRESS CONVERSION R/W ACK SLEEP P tREFWAKE CONVERSION 23015 F11 Figure 11. Exiting Sleep Mode and Starting a New Conversion 1 2 3 4 5 6 7 8 9 1 2 SCL ACQUISITION BEGINS SDA A6 A5 A4 A3 A2 A1 A0 R/W B11 tACQ B10 23015 F12a Figure 12a. Timing Diagram Showing Acquisition During a Read Operation 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL ACQUISITION BEGINS SDA A2 A1 A0 R/W S/D O/S X X UNI SLP X X tACQ 23015 F12b Figure 12b. Timing Diagram Showing Acquisition During a Write Operation 23015fb 20 LTC2301/LTC2305 APPLICATIONS INFORMATION for the common return of these bypass capacitors is essential to the low noise operation of the ADC. These traces should be as wide as possible. See Figures 15a-15e for a suggested layout. 011...111 111...111 BIPOLAR ZERO 011...110 111...110 OUTPUT CODE OUTPUT CODE (TWO'S COMPLEMENT) separated as much as possible. Care should be taken not to run any digital signals alongside an analog signal. All analog inputs should be shielded by GND. VREF, REFCOMP and VDD should be bypassed to the ground plane as close to the pin as possible. Maintaining a low impedance path 000...001 000...000 111...111 111...110 FS = 4.096V 1LSB = FS/2n 1LSB = 1mV 100...001 100...000 -FS/2 -1 0V 1 LSB LSB INPUT VOLTAGE (V) 100...001 100...000 011...111 UNIPOLAR ZERO 011...110 FS = 4.096V 1LSB = FS/2n 1LSB = 1mV 000...001 000...000 FS/2 - 1LSB 0V FS - 1LSB INPUT VOLTAGE (V) 23015 F13 23015 F14 Figure 13. Bipolar Transfer Characteristics (2's Complement) Figure 14. Unipolar Transfer Characteristics (Straight Binary) Figure 15a. Top Silkscreen 23015fb 21 LTC2301/LTC2305 APPLICATIONS INFORMATION Figure 15b. Topside Figure 15c. Layer 2 Ground Plane Figure 15d. Layer 3 Power Plane Figure 15e. Bottom Side 23015fb 22 LTC2301/LTC2305 PACKAGE DESCRIPTION DE/UE Package 12-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1695) 0.70 p0.05 3.60 p0.05 2.20 p0.05 3.30 p0.05 1.70 p 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p0.10 (2 SIDES) 7 R = 0.115 TYP 0.40 p 0.10 12 R = 0.05 TYP PIN 1 TOP MARK (NOTE 6) 0.200 REF 3.00 p0.10 (2 SIDES) 3.30 p0.10 1.70 p 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER 0.75 p0.05 6 0.25 p 0.05 1 (UE12/DE12) DFN 0806 REV D 0.50 BSC 2.50 REF 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 23015fb 23 LTC2301/LTC2305 PACKAGE DESCRIPTION MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev O) 0.889 p 0.127 (.035 p .005) 5.23 (.206) MIN 3.20 - 3.45 (.126 - .136) 4.039 p 0.102 (.159 p .004) (NOTE 3) 0.65 (.0256) BSC 0.42 p 0.038 (.0165 p .0015) TYP 12 11 10 9 8 7 RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL "A" 3.00 p 0.102 (.118 p .004) (NOTE 4) 4.90 p 0.152 (.193 p .006) 0o - 6o TYP 0.406 p 0.076 (.016 p .003) REF GAUGE PLANE 0.53 p 0.152 (.021 p .006) 1 2 3 4 5 6 1.10 (.043) MAX DETAIL "A" 0.18 (.007) 0.86 (.034) REF SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.650 (.0256) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.1016 p 0.0508 (.004 p .002) MSOP (MS12) 1107 REV O 23015fb 24 LTC2301/LTC2305 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 8/10 Revised Typical Performance Characteristics curves G03 and G12 7, 8 Revised VREF, REFCOMP and VDD descriptions in Pin Functions section 9, 10 Revised Figure 4 in Applications Information section 15 Revised Figures 5a, 5b and 5c, Internal Reference section and I2C Interface section in Applications Information 15, 16 Changed "NAK" command to NACK 16, 17 23015fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 25 LTC2301/LTC2305 TYPICAL APPLICATION Driving the LTC2305 with 10V Input Signals Using a Precision Attenuator 5V IN OUT LT1790-2.5 0.1F 1F 5V GND 10V 10F 0.1F 7 8 450k 50k 9 150k 10 1.7k 1.7k LTC2305 - 450k 1 450k AD1 AD0 VDD + 4pF LT1991 6 100 CH0 47pF CH1 450k ANALOG INPUT MUX + - SCL I2C PORT 12-BIT SAR ADC CONTROL LOGIC (FPGA, CPLD, DSP, ETC) SDA 2 150k 10V INPUT SIGNAL 3 50k 4pF 4 INTERNAL 2.5V REF 5 VREF 2.2F -10V REFCOMP GND 0.1F 10F 23015 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1417 14-Bit, 400ksps Serial ADC 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package LTC1468/LT1469 Single/Dual 90MHz, 22V/s, 16-Bit Accurate Op Amps Low Input Offset: 75V/125V LTC1609 16-Bit, 200ksps Serial ADC 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply LTC1790 Micropower Low Dropout Reference 60A Supply Current, 10ppm/C, SOT-23 Package LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC Parallel Output, Programmable MUX and Sequencer, 5V Supply LTC1852/LTC1853 10-Bit/12-Bit, 8-Channel, 400ksps ADC Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply LTC1860/LTC1861 12-Bit, 1-/2-Channel 250ksps ADC in MSOP 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel 150ksps ADC 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages LTC1863/LTC1867 6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 12-/16-Bit, 8-Channel 200ksps ADC LTC1863L/LTC1867L 3V, 12-/16-Bit, 8-Channel 175ksps ADC 2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package LTC1864/LTC1865 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 16-Bit, 1-/2-Channel 250ksps ADC in MSOP LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages LTC2302/LTC2306 12-Bit, 1-/2-Channel 500ksps SPI ADCs in 3mm x 3mm DFN 14mW at 500ksps, Single 5V Supply, Software Compatible with LTC2308 LTC2308 12-Bit, 8-Channel 500ksps SPI ADC 5V, Internal Reference, 4mm x 4mm QFN Package, Software Compatible with LTC2302/LTC2306 LTC2309 12-Bit, 8-Channel ADC with I2C Interface 5V, Internal Reference, 4mm x 4mm QFN and 20-Pin TSSOP Packages, Software Compatible with LTC2301/LTC2305 LTC2451/LTC2453 Easy-to-Use, Ultra-Tiny 16-Bit I2C Delta Sigma ADCs 2 LSB INL, 50nA Sleep Current, 60Hz Output Rate, 3mm x 2mm DFN Package, Single-Ended/Differential Inputs LTC2487/LTC2489/ LTC2493 2-/4-Channel Easy Drive I2C Delta Sigma ADCs 16-/24-Bits, PGA and Temp Sensor, 4mm x 3mm DFN Packages LTC2495/LTC2497/ LTC2499 8-/16-Channel Easy Drive I2C Delta Sigma ADCs 16-/24-Bits, PGA and Temp Sensor, 5mm x 7mm QFN Packages 23015fb 26 Linear Technology Corporation LT 0810 REV B * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2008