LTC2301/LTC2305
1
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BLOCK DIAGRAM
FEATURES
APPLICATIONS
DESCRIPTION
1-/2-Channel, 12-Bit ADCs
with I2C Compatible Interface
The LTC
®
2301/LTC2305 are low noise, low power,
1-/2-channel, 12-bit successive approximation ADCs
with an I2C compatible serial interface. These ADCs include
an internal reference and a fully differential sample-and-
hold circuit to reduce common mode noise. The LTC2301/
LTC2305 operate from an internal clock to achieve a fast
1.3µs conversion time.
The LTC2301/LTC2305 operate from a single 5V supply
and draw just 300µA at a throughput rate of 1ksps. The
ADC enters nap mode when not converting, reducing the
power dissipation.
The LTC2301/LTC2305 are available in small 12-pin
4mm × 3mm DFN and 12-pin MSOP packages. The in-
ternal 2.5V reference further reduces PCB board space
requirements.
The low power consumption and small size make the
LTC2301/LTC2305 ideal for battery operated and portable
applications, while the 2-wire I2C compatible serial interface
makes these ADCs a good match for space-constrained
systems.
12-Bit I2C ADC Family
Input Channels 1 2 8
Part Number LTC2301 LTC2305 LTC2309
Integral Nonlinearity vs Output Code (LTC2305)
n 12-Bit Resolution
n Low Power: 1.5mW at 1ksps, 35μW Sleep Mode
n 14ksps Throughput Rate
n Internal Reference
n Low Noise: SNR = 73.5dB
n Guaranteed No Missing Codes
n Single 5V Supply
n 2-wire I2C Compatible Serial Interface with 9
Addresses Plus One Global for Synchronization
n Fast Conversion Time: 1.3s
n 1-Channel (LTC2301) and 2-Channel (LTC2305)
Versions
n Unipolar or Bipolar Input Ranges (Software
Selectable)
n Internal Conversion Clock
n Guaranteed Operation from –40°C to 125°C
(MSOP Package)
n 12-Pin 4mm × 3mm DFN and 12-Pin MSOP
Packages
n Industrial Process Control
n Motor Control
n Accelerometer Measurements
n Battery Operated Instruments
n Isolated and/or Remote Data Acquisition
n Power Supply Monitoring
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
23015 TA01a
+
–
12-BIT
SAR ADC
ANALOG
INPUT
MUX
ANALOG INPUT
0V TO 4.096V UNIPOLAR
±2.048V BIPOLAR
I2C
PORT
INTERNAL
2.5V REF
0.1µF 10µF
2.2µF
VREF
REFCOMP
SCL
SDA
AD1
AD0
CH0(IN+)
CH1(IN+)
PIN NAMES IN PARENTHESES
REFER TO LTC2301
10µF 0.1µF
VDD
LTC2301
LTC2305
GND
5V
OUTPUT CODE
0
INL (LSB)
1.00
0.75
0.25
–0.25
–0.75
0.50
0.00
–0.50
–1.00 20481024 3072
23015 TA01b
4096
LTC2301/LTC2305
2
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ................................ –0.3V to 6.0V
Analog Input Voltage (Note 3)
CH0(IN+), CH1(IN–),
REF, REFCOMP .............(GND – 0.3V) to (VDD + 0.3V)
Digital Input Voltage ..........(GND – 0.3V) to (VDD + 0.3V)
Digital Output Voltage .......(GND – 0.3V) to (VDD + 0.3V)
(Notes 1, 2)
PIN CONFIGURATION
ORDER INFORMATION
Power Dissipation ...............................................500mW
Operating Temperature Range
LTC2301C/LTC2305C ............................... 0°C to 70°C
LTC2301I/LTC2305I .............................. –40°C to 85°C
LTC2301H/LTC2305H (Note 13) .........–40°C to 125°C
Storage Temperature Range ................... –65°C to 150°C
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2301CDE#PBF LTC2301CDE#TRPBF 2301 12-Lead (3mm × 4mm) Plastic DFN 0°C to 70°C
LTC2301IDE#PBF LTC2301IDE#TRPBF 2301 12-Lead (3mm × 4mm) Plastic DFN –40°C to 85°C
LTC2305CDE#PBF LTC2305CDE#TRPBF 2305 12-Lead (3mm × 4mm) Plastic DFN 0°C to 70°C
LTC2305IDE#PBF LTC2305IDE#TRPBF 2305 12-Lead (3mm × 4mm) Plastic DFN –40°C to 85°C
LTC2301CMS#PBF LTC2301CMS#TRPBF 2301 12-Lead Plastic MSOP 0°C to 70°C
LTC2301IMS#PBF LTC2301IMS#TRPBF 2301 12-Lead Plastic MSOP –40°C to 85°C
LTC2301HMS#PBF LTC2301HMS#TRPBF 2301 12-Lead Plastic MSOP –40°C to 125°C
LTC2305CMS#PBF LTC2305CMS#TRPBF 2305 12-Lead Plastic MSOP 0°C to 70°C
LTC2305 LTC2301
12
11
10
9
8
7
13
1
2
3
4
5
6
AD0
AD1
VDD
GND
REFCOMP
VREF
GND
SDA
SCL
GND
CH0
CH1
TOP VIEW
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
12
11
10
9
8
7
13
1
2
3
4
5
6
AD0
AD1
VDD
GND
REFCOMP
VREF
GND
SDA
SCL
GND
IN+
IN–
TOP VIEW
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
LTC2305 LTC2301
1
2
3
4
5
6
GND
SDA
SCL
GND
CH0
CH1
12
11
10
9
8
7
AD0
AD1
VDD
GND
REFCOMP
VREF
TOP VIEW
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 130°C/W
1
2
3
4
5
6
GND
SDA
SCL
GND
IN+
IN–
12
11
10
9
8
7
AD0
AD1
VDD
GND
REFCOMP
VREF
TOP VIEW
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 130°C/W
LTC2301/LTC2305
3
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ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2305IMS#PBF LTC2305IMS#TRPBF 2305 12-Lead Plastic MSOP –40°C to 85°C
LTC2305HMS#PBF LTC2305HMS#TRPBF 2305 12-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi
cations, go to: http://www.linear.com/tapeandreel/
CONVERTER AND MULTIPLEXER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) l 12 Bits
Integral Linearity Error (Note 5) l±0.4 ±1 LSB
Differential Linearity Error l±0.3 ±1 LSB
Bipolar Zero Error (Note 6) l±0.5 ±8 LSB
Bipolar Zero Error Drift 0.002 LSB/°C
Unipolar Zero Error (Note 6) l±0.7 ±6 LSB
Unipolar Zero Error Drift 0.002 LSB/°C
Unipolar Zero Error Match (LTC2305) ±0.1 ±1 LSB
Bipolar Full-Scale Error External Reference (Note 7)
REFCOMP = 4.096V (Note 7)
l
l
±1
±0.9
±10
±9
LSB
LSB
Bipolar Full-Scale Error Drift External Reference 0.05 LSB/°C
Unipolar Full-Scale Error External Reference (Note 7)
REFCOMP = 4.096V (Note 7)
l
l
±0.5
±0.7
±10
±6
LSB
LSB
Unipolar Full-Scale Error Drift External Reference 0.05 LSB/°C
Unipolar Full-Scale Error Match (LTC2305) ±0.1 ±2 LSB
ANALOG INPUT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range (CH0, CH1, IN+) (Note 8) l–0.05 REFCOMP V
VIN– Absolute Input Range (CH0, CH1, IN–) Unipolar (Note 8)
Bipolar (Note 8)
l–0.05
–0.05
0.25 • REFCOMP
0.75 • REFCOMP
V
V
VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN– (Unipolar)
VIN = VIN+ – VIN– (Bipolar)
l0 to REFCOMP
±REFCOMP/2
V
V
IIN Analog Input Leakage Current l±1 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
55
5
pF
pF
CMRR Input Common Mode Rejection Ratio 70 dB
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 4)
LTC2301/LTC2305
4
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DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 1kHz l71 73.4 dB
SNR Signal-to-Noise Ratio fIN = 1kHz l71 73.5 dB
THD Total Harmonic Distortion fIN = 1kHz l–91 –77 dB
SFDR Spurious Free Dynamic Range fIN = 1kHz, First 5 Harmonics l79 92 dB
Channel-to-Channel Isolation fIN = 1kHz –109 dB
Full Linear Bandwidth fIN = 1kHz 700 kHz
–3dB Input Linear Bandwidth (Note 10) 25 MHz
Aperture Delay 13 ns
Transient Response Full-Scale Step 240 ns
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C and AIN = –1dBFS. (Notes 4,9)
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Notes 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 l2.46 2.50 2.54 V
VREF Output Tempco IOUT = 0 ±25 ppm/°C
VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 8 kΩ
VREFCOMP Output Voltage IOUT = 0 4.096 V
VREF Line Regulation VDD = 4.75V to 5.25V 0.8 mV/V
I2C INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Notes 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l2.85 V
VIL Low Level Input Voltage l1.5 V
VIHA High Level Input Voltage for Address Pins A1, A0 l4.75 V
VILA Low Level Input Voltage for Address Pins A1, A0 l0.25 V
RINH Resistance from A1, A0 to VDD to Set Chip
Address Bit to 1
l10 k
RINL Resistance from A1, A0 to GND to Set Chip
Address Bit to 0
l10 k
RINF Resistance from A1, A0 to GND or VDD to Set
Chip Address Bit to Float
l2M
IIDigital Input Current VIN = VDD l–10 10 A
VHYS Hysteresis of Schmitt Trigger Inputs (Note 8) l0.25 V
VOL Low Level Output Voltage (SDA) I = 3mA l0.4 V
tOF Output Fall Time VIN(MIN) to VIL(MAX) Bus Load CB 10pF to 400pF (Note 11) l20 + 0.1CB250 ns
tSP Input Spike Suppression l50 ns
CCAX External Capacitance Load on Chip Address Pins
(A1, A0) for Valid Float
l10 pF
LTC2301/LTC2305
5
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POWER REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l4.75 5 5.25 V
IDD Supply Current
Nap Mode
Sleep Mode
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
l
l
l
2.3
225
7
3.5
400
15
mA
µA
µA
PDPower Dissipation
Nap Mode
Sleep Mode
14ksps Sample Rate
SLP Bit = 0, Conversion Done
SLP Bit = 1, Conversion Done
l
l
l
11.5
1.125
35
17.5
2
75
mW
mW
µW
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 4)
I2C TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL SCL Clock Frequency l400 kHz
tHD(SDA) Hold Time (Repeated) START Condition l0.6 µs
tLOW LOW Period of the SCL Pin l1.3 µs
tHIGH HIGH Period of the SCL Pin l0.6 µs
tSU(STA) Set-Up Time for a Repeated START
Condition
l0.6 µs
tHD(DAT) Data Hold Time l0 0.9 µs
tSU(DAT) Data Set-Up Time l100 ns
trRise Time for SDA/SCL Signals (Note 11) l20 + 0.1CB300 ns
tfFall Time for SDA/SCL Signals (Note 11) l20 + 0.1CB300 ns
tSU(STO) Set-Up Time for STOP Condition l0.6 µs
tBUF Bus Free Time Between a Second START
Condition
l1.3 µs
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
ADC TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Throughput Rate (Successive Reads) l14 ksps
tCONV Conversion Time l1.3 1.6 µs
tACQ Acquisition Time (Note 8) l240 ns
tREFWAKE REFCOMP Wakeup Time (Note 12) CREFCOMP = 10µF, CREF = 2.2µF 200 ms
LTC2301/LTC2305
6
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: VDD = 5V, fSMPL = 14kHz, internal reference unless otherwise
noted.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Bipolar zero error is the offset voltage measured from –0.5 LSB
when the output code fl ickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from 0.5 LSB
when the output code fl ickers between 0000 0000 0000 and 0000 0000
0001.
Note 7: Full-scale bipolar error is the worst-case of –FS or FS untrimmed
deviation from ideal fi rst and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: Guaranteed by design, not subject to test.
Note 9: All specifi cations in dB are referred to a full-scale ±2.048V input
with a 2.5V reference voltage.
Note 10: Full linear bandwidth is defi ned as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
Note 11: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF)
Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin
to settle within 0.5 LSB at 12-bit resolution of its fi nal value after waking
up from sleep mode.
Note 13: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
ELECTRICAL CHARACTERISTICS
LTC2301/LTC2305
7
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
Supply Current
vs Sampling Frequency Offset Error vs Temperature Full-Scale Error vs Temperature
Supply Current vs Temperature Sleep Current vs Temperature
Analog Input Leakage Current
vs Temperature
(LTC2301) TA = 25°C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted.
OUTPUT CODE
0
INL (LSB)
1.00
0.75
0.25
–0.25
–0.75
0.50
0.00
–0.50
–1.00 20481024 3072
23015 G01
4096
OUTPUT CODE
0
DNL (LSB)
1.00
0.75
0.25
–0.25
–0.75
0.50
0.00
–0.50
–1.00 20481024 3072
23015 G02
4096
FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–70
–60
–50
–40
–30
–20
–10
–90
–110
–130
–80
–100
–120
–140 51234 6
23015 G03
7
SNR = 73.2 dB
SINAD = 73.1 dB
THD = –90dB
SAMPLING FREQUENCY (ksps)
SUPPLY CURRENT (mA)
23015 G04
2.5
1.0
1.5
2.0
0.5
00.1 10 1001
TEMPERATURE (°C)
–50
OFFSET ERROR (LSB)
1.5
1.0
0.0
0.5
–0.5
–1.0 500 100
23015 G05
12525–25 75
BIPOLAR
UNIPOLAR
TEMPERATURE (°C)
–50
FULL-SCALE ERROR (LSB)
4
2
–2
0
–4
–6 500 100
23015 G06
12525–25 75
BIPOLAR
UNIPOLAR
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
2.4
2.2
1.6
1.8
1.4 500 100
23015 G07
12525–25 75
TEMPERATURE (°C)
–50
SLEEP CURRENT (µA)
10
8
2
4
6
0500 100
23015 G08
12525–25 75
TEMPERATURE (°C)
–50
LEAKAGE CURRENT (nA)
1000
800
900
700
200
100
400
300
600
500
0500 100
23015 G09
12525–25 75
LTC2301/LTC2305
8
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
1kHz Sine Wave
8192 Point FFT Plot
Supply Current
vs Sampling Frequency Offset Error vs Temperature Full-Scale Error vs Temperature
Supply Current vs Temperature Sleep Current vs Temperature
Analog Input Leakage Current
vs Temperature
(LTC2305) TA = 25°C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted.
OUTPUT CODE
0
INL (LSB)
1.00
0.75
0.25
–0.25
–0.75
0.50
0.00
–0.50
–1.00 20481024 3072
23015 G10
4096
OUTPUT CODE
0
DNL (LSB)
1.00
0.75
0.25
–0.25
–0.75
0.50
0.00
–0.50
–1.00 20481024 3072
23015 G11
4096
FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–70
–60
–50
–40
–30
–20
–10
–90
–110
–130
–80
–100
–120
–140 51234 6
23015 G12
7
SNR = 73.2 dB
SINAD = 73.1 dB
THD = –90dB
SAMPLING FREQUENCY (ksps)
SUPPLY CURRENT (mA)
23015 G13
2.5
1.0
1.5
2.0
0.5
00.1 10 1001
TEMPERATURE (°C)
–50
OFFSET ERROR (LSB)
1.0
0.0
0.5
–0.5 500 100
23015 G14
12525–25 75
BIPOLAR
UNIPOLAR
TEMPERATURE (°C)
–50
FULL-SCALE ERROR (LSB)
4
2
–2
0
–4
–6 500 100
23015 G15
12525–25 75
BIPOLAR
UNIPOLAR
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
2.4
2.2
1.6
1.8
1.4 500 100
23015 G16
12525–25 75
TEMPERATURE (°C)
–50
SLEEP CURRENT (µA)
10
8
2
4
6
0500 100
23015 G17
12525–25 75
TEMPERATURE (°C)
–50
LEAKAGE CURRENT (nA)
1000
800
900
700
200
100
400
300
600
500
0500 100
23015 G18
12525–25 75
CH(ON)
CH(OFF)
LTC2301/LTC2305
9
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PIN FUNCTIONS
GND (Pins 1, 4, 9): Ground. All GND pins must be con-
nected to a solid ground plane.
SDA (Pin 2): Bidirectional Serial Data Line of the I2C In-
terface. In transmitter mode (read), the conversion result
is output at the SDA pin, while in receiver mode (write),
the DIN word is input at the SDA pin to confi gure the ADC.
The pin is high impedance during the data input mode and
is an open drain output (requires an appropriate pull-up
device to VDD) during the data output mode.
SCL (Pin 3): Serial Clock Pin of the I2C Interface. The
LTC2301 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
IN+, IN– (Pins 5, 6): Positive (IN+) and negative (IN–)
differential analog inputs.
VREF (Pin 7): 2.5V Reference Output. Bypass to GND with
a minimum 2.2µF ceramic capacitor. The internal refer-
ence may be overdriven by an external 2.5V reference at
this pin.
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with 10µF and 0.1µF ceramic capacitors in parallel.
Nominal output voltage is 4.096V. The internal reference
buffer driving this pin is disabled by grounding VREF, al-
lowing REFCOMP to be overdriven by an external source
(see Figure 5c).
VDD (Pin 10): 5V Analog Supply. The range of VDD is 4.75V
to 5.25V. Bypass VDD to GND with 10µF and 0.1µF ceramic
capacitors in parallel.
AD1 (Pin 11): Chip Address Control Pin. This pin is con-
fi gured as a three-state (LOW, HIGH, fl oating) address
control bit for the device I2C address. See Table 2 for
address selection.
AD0 (Pin 12): Chip Address Control Pin. This pin is con-
fi gured as a three-state (LOW, HIGH, fl oating) address
control bit for the device I2C address. See Table 2 for
address selection.
GND (Pin 13 – DFN Package Only): Exposed Pad Ground.
Must be soldered directly to ground plane.
(LTC2301)
LTC2301/LTC2305
10
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PIN FUNCTIONS
GND (Pins 1, 4, 9): Ground. All GND pins must be con-
nected to a solid ground plane.
SDA (Pin 2): Bidirectional Serial Data Line of the I2C In-
terface. In transmitter mode (read), the conversion result
is output at the SDA pin, while in receiver mode (write),
the DIN word is input at the SDA pin to confi gure the ADC.
The pin is high impedance during the data input mode and
is an open drain output (requires an appropriate pull-up
device to VDD) during the data output mode.
SCL (Pin 3): Serial Clock Pin of the I2C Interface. The
LTC2305 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
CH0-CH1 (Pins 5, 6): Channel 0 and Channel 1 Analog
Inputs. CH0 and CH1 can be confi gured as single-ended
or differential input channels. See the Analog Input Multi-
plexer section.
VREF (Pin 7): 2.5V Reference Output. Bypass to GND with
a minimum 2.2µF ceramic capacitor. The internal refer-
ence may be overdriven by an external 2.5V reference at
this pin.
REFCOMP (Pin 8): Reference Buffer Output. Bypass to
GND with 10µF and 0.1µF ceramic capacitors in parallel.
Nominal output voltage is 4.096V. The internal reference
buffer driving this pin is disabled by grounding VREF, al-
lowing REFCOMP to be overdriven by an external source
(see Figure 5c).
VDD (Pin 10): 5V Analog Supply. The range of VDD is 4.75V
to 5.25V. Bypass VDD to GND with 10µF and 0.1µF ceramic
capacitors in parallel.
AD1 (Pin 11): Chip Address Control Pin. This pin is con-
fi gured as a three-state (LOW, HIGH, fl oating) address
control bit for the device I2C address. See Table 2 for
address selection.
AD0 (Pin 12): Chip Address Control Pin. This pin is con-
fi gured as a three-state (LOW, HIGH, fl oating) address
control bit for the device I2C address. See Table 2 for
address selection.
GND (Pin 13 – DFN Package Only): Exposed Pad Ground.
Must be soldered directly to ground plane.
(LTC2305)
LTC2301/LTC2305
11
23015fb
FUNCTIONAL BLOCK DIAGRAM
23015 BD
+
–
12-BIT
SAR ADC
ANALOG
INPUT
MUX
I2C
PORT
INTERNAL
2.5V REF
GAIN = 1.6384x
VREF
REFCOMP
SCL
SDA
AD1
AD0
CH0(IN+)
CH1(IN–)
PIN NAMES IN PARENTHESES
REFER TO LTC2301
VDD
LTC2301
LTC2305
8k
GND
TIMING DIAGRAM
SDA
SCL
SSrPS
tHD(SDA)
S = START, Sr = REPEATED START, P = STOP
tHD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW tHD(SDA) tSP
tBUF
tr
trtf
tf
tHIGH 23015 TD
Defi nition of Timing for Fast/Standard Mode Devices on the I2C Bus
LTC2301/LTC2305
12
23015fb
APPLICATIONS INFORMATION
Overview
The LTC2301/LTC2305 are low noise, 1-/2-channel, 12-bit
successive approximation register (SAR) A/D converters
with an I2C compatible serial interface. The LTC2301/
LTC2305 both include a precision internal reference. The
LTC2305 includes a 2-channel analog input multiplexer
(MUX) while the LTC2301 includes an input MUX that allows
the polarity of the differential input to be selected. These
ADCs can operate in either unipolar or bipolar mode. Uni-
polar mode should be used for single-ended operation with
the LTC2305, since single-ended input signals are always
referenced to GND. A sleep mode option is also provided
to further reduce power during inactive periods.
The LTC2301/LTC2305 communicate through a 2-wire
I2C compatible serial interface. Conversions are initiated
by signaling a STOP condition after the part has been
successfully addressed for a read/write operation. The
device will not acknowledge an external request until the
conversion is fi nished. After a conversion is fi nished, the
device is ready to accept a read/write request. Once the
LTC2301/LTC2305 is addressed for a read operation, the
device begins outputting the conversion result under the
control of the serial clock (SCL). There is no latency in
the conversion result. There are 12 bits of output data fol-
lowed by four trailing zeros. Data is updated on the falling
edges of SCL, allowing the user to reliably latch data on
the rising edge of SCL. A write operation may follow the
read operation by using a repeat START or a STOP condi-
tion may be given to start a new conversion. By selecting
a write operation, these ADCs can be programmed by a
6-bit DIN word. The DIN word confi gures the MUX and
programs various modes of operation.
During a conversion, the internal 12-bit capacitive charge-
redistribution DAC output is sequenced through a succes-
sive approximation algorithm by the SAR starting from
the most signifi cant bit (MSB) to the least signifi cant bit
(LSB). The sampled input is successively compared with
binary weighted charges supplied by the capacitive DAC
using a differential comparator. At the end of a conver-
sion, the DAC output balances the analog input. The SAR
contents (a 12-bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out via the I2C interface.
Programming the LTC2301 and LTC2305
The software compatible LTC2301/LTC2305/LTC2309 fam-
ily features a 6-bit DIN word to program various modes of
operation. Don’t care bits (X) are ignored. The SDA data
bits are loaded on the rising edge of SCL during a write
operation, with the S/D bit loaded on the fi rst rising edge
and the SLP bit on the sixth rising edge (see Figure 7b
in the I2C Interface section). The input data word for the
LTC2305 is defi ned as follows:
S/D O/S X X UNI SLP
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
For the LTC2301, the input word is defi ned as:
X O/S X X UNI SLP
Analog Input Multiplexer
The analog input MUX is programmed by the S/D and
O/S bits of the DIN word for the LTC2305 and the O/S
bit of the DIN word for the LTC2301. Table 1 and Table 2
list the MUX confi gurations for all combinations of the
confi guration bits. Figure 1a shows several possible MUX
confi gurations and Figure 1b shows how the MUX can be
reconfi gured from one conversion to the next.
Table 1. Channel Confi guration for the LTC2305
S/D O/S CH0 CH1
00+–
01–+
10+
11 +
LTC2301/LTC2305
13
23015fb
APPLICATIONS INFORMATION
Table 2. Channel Confi guration for the LTC2301
O/S IN+IN–
0+–
1–+
Figure 1a. Example MUX Confi gurations
Figure 1b. Changing the MUX Assignment “On the Fly”
CH0
CH1
GND (–)
2 Single-Ended
+
1 Differential
+(–)+
–(+)
1 Differential
+ (–)
– (+)
{
{
23015 F01a
CH0
CH1
CH0
CH1
LTC2305 LTC2305
LTC2301
GND (–)
1st Conversion 2nd Conversion
+
–+
–
{{
CH0
CH1
CH0
CH1
23015 F01b
LTC2305 LTC2305
Driving the Analog Inputs
The analog inputs of the LTC2301/LTC2305 are easy to
drive. Each of the analog inputs of the LTC2305 (CH0 and
CH1) can be used as single-ended input relative to GND
or as a differential pair. The analog inputs of the LTC2301
(IN+, IN–) are always confi gured as a differential pair.
Regardless of the MUX confi guration, the “+” and “–“
inputs are sampled at the same instant. Any unwanted
signal that is common to both inputs will be reduced by
the common mode rejection of the sample-and-hold cir-
cuit. The inputs draw only one small current spike while
charging the sample-and-hold capacitors during the acquire
mode. In conversion mode, the analog inputs draw only
a small leakage current. If the source impedance of the
driving circuit is low, the ADC inputs can be driven directly.
Otherwise, more acquisition time should be allowed for a
source with higher impedance.
Input Filtering
The noise and distortion of the input amplifi er and other
circuitry must be considered since they will add to the
ADC noise and distortion. Therefore, noisy input circuitry
should be fi ltered prior to the analog inputs to minimize
noise. A simple 1-pole RC fi lter is suffi cient for many
applications.
The analog inputs of the LTC2301/LTC2305 can be modeled
as a 55pF capacitor (CIN) in series with a 100Ω resistor
(RON), as shown in Figure 2a. CIN gets switched to the
selected input once during each conversion. Large fi lter
RC time constants will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle to
12-bit resolution within the acquisition time (tACQ) if DC
accuracy is important.
When using a fi lter with a large CFILTER value (e.g. 1µF),
the inputs do not completely settle and the capacitive input
switching currents are averaged into a net DC current
(IDC). In this case, the analog input can be modeled by an
equivalent resistance (REQ = 1/(fSMPL • CIN)) in series with
an ideal voltage source (VREFCOMP/2), as shown in Figure 2b.
LTC2301/LTC2305
14
23015fb
APPLICATIONS INFORMATION
The magnitude of the DC current is then approximately
IDC = (VIN – VREFCOMP/2)/REQ, which is roughly proportional
to VIN. To prevent large DC drops across the resistor RFILTER,
a fi lter with a small resistor and large capacitor should be
chosen. When running at the maximum throughput rate
of 14ksps, the input current equals 1.5µA at VIN = 4.096V,
which amounts to a full-scale error of 0.5 LSBs when using
a fi lter resistor (RFILTER) of 333Ω. Applications requiring
lower sample rates can tolerate a larger fi lter resistor for
the same amount of full-scale error.
Figures 3a and 3b show respective examples of input
fi ltering for single-ended and differential inputs. For the
single-ended case in Figure 4a, a 50Ω source resistor
and a 2000pF capacitor to ground on the input will limit
the input bandwidth to 1.6MHz. High quality capacitors
and resistors should be used in the RC fi lter since these
components can add distortion. NPO and silver mica type
dielectric capacitors have excellent linearity. Carbon surface
mount resistors can generate distortion from self heating
Figure 2a. Analog Input Equivalent Circuit
Figure 2b. Analog Input Equivalent
Circuit for Large Filter Capacitances
VIN
INPUT
CH0, CH1,
IN+, IN–RON =
100
CIN =
55pF
CFILTER
RSOURCE
23015 F02a
LTC2301
LTC2305
VIN
INPUT
(CH0, CH1,
IN+, IN–)
REQ =
1/(fSMPL • CIN)
VREFCOMP/2
CFILTER
RFILTER IDC
23015 F02b
LTC2301
LTC2305
+
–
and from damage that may occur during soldering. Metal
fi lm surface mount resistors are much less susceptible
to both problems.
Dynamic Performance
Fast Fourier Transform (FFT) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
Figure 3a. Optional RC Input Filtering for Single-Ended Input
Figure 3b. Optional RC Input Filtering for Differential Inputs
23015 F03a
CH0, CH1
LTC2305
REFCOMP
2000pF
0.1µF
10µF
50
ANALOG
INPUT
1000pF
23015 F03b
CH0, IN+
CH1, IN–
LTC2301
LTC2305
REFCOMP
1000pF
1000pF
0.1µF10µF
50
50
DIFFERENTIAL
ANALOG
INPUTS
LTC2301/LTC2305
15
23015fb
APPLICATIONS INFORMATION
frequency. Figure 4 shows a typical SINAD of 73.2dB with
a 14kHz sampling rate and a 1kHz input. A SNR of 73.3dB
can be achieved with the LTC2301/LTC2305.
Figure 4. 1kHz Sine Wave 8192 Point FFT Plot
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD =20log V2
2+V3
2+V4
2...+VN
2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
Internal Reference
The LTC2301/LTC2305 have an on-chip, temperature
compensated bandgap reference that is factory trimmed
to 2.5V (Refer to Figure 5a). It is internally connected to
a reference amplifi er and is available at VREF (Pin 7). VREF
should be bypassed to GND with a 2.2F ceramic capacitor
to minimize noise. An 8k resistor is in series with the output
so that it can be easily overdriven by an external reference
if more accuracy and/or lower drift are required, as shown
in Figure 5b. The reference amplifi er gains the VREF volt-
age by 1.638 to 4.096V at REFCOMP. To compensate the
reference amplifi er, bypass REFCOMP with a 10F ceramic
capacitor in parallel with a 0.1F ceramic capacitor for best
noise performance. The internal reference buffer can also
be overdriven from 1V to VDD with an external reference at
REFCOMP, as shown in Figure 5c. To do so, VREF must be
grounded to disable the reference buffer. This will result
in an input range of 0V to VREFCOMP in unipolar mode and
±0.5 • VREFCOMP in bipolar mode.
R2
R3
REFERENCE
AMP
0.1µF
10µF
2.2µF
REFCOMP
GND
VREF
R1
8k
2.5V
4.096V
LTC2301
LTC2305
23015 F05a
BANDGAP
REFERENCE
Figure 5a. LTC2301/LTC2305 Reference Circuit
Figure 5b. Using the LT1790A-2.5 as an External Reference
Figure 5c. Overdriving REFCOMP Using the LT1790A-4.096
0.1µF
10µF
23015 F05b
LT1790A-2.5
VOUT
VIN
5V
VREF
LTC2301
LTC2305
GND
REFCOMP
2.2µF
0.1µF
0.1µF
10µF
23015 F05c
LT1790A-4.096
VOUT
VIN
5V
VREF
LTC2301
LTC2305
GND
REFCOMP
0.1µF
FREQUENCY (kHz)
0
MAGNITUDE (dB)
0
–70
–60
–50
–40
–30
–20
–10
–90
–110
–130
–80
–100
–120
–140 51234 6
23015 F04
7
SNR = 73.2 dB
SINAD = 73.1 dB
THD = –90dB
LTC2301/LTC2305
16
23015fb
APPLICATIONS INFORMATION
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (tCONV) of 1.3s and a
maximum conversion time of 1.6s over the full operating
temperature range.
I2C Interface
The LTC2301/LTC2305 communicate through an I2C in-
terface. The I2C interface is a 2-wire open-drain interface
supporting multiple devices and multiple masters on a
single bus. The connected devices can only pull the serial
data line (SDA) LOW and can never drive it HIGH. SDA is
required to be externally connected to the supply through
a pull-up resistor. When the data line is not being driven
low, it is HIGH. Data on the I2C bus can be transferred at
rates up to 100kbits/s in the standard mode and up to
400kbits/s in the fast mode.
The VDD power should not be removed from the LTC2301/
LTC2305 when the I2C bus is active to avoid loading the I2C
bus lines through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function of
the device. A device can also be considered as a master
or a slave when performing data transfers. A master is
the device which initiates a data transfer on the bus and
generates the clock signals to permit the transfer. Devices
addressed by the master are considered slaves.
The LTC2301/LTC2305 can only be addressed as slaves.
Once addressed, they can receive confi guration bits (DIN
word) or transmit the last conversion result. The serial clock
line (SCL) is always an input to the LTC2301/LTC2305 and
the serial data line (SDA) is bidirectional. These devices
support the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see Timing Diagram
section for defi nition of the I2C timing).
The START and STOP Conditions
Referring to Figure 6, a START (S) condition is generated
by transitioning SDA from HIGH to LOW while SCL is
HIGH. The bus is considered to be busy after the START
condition. When the data transfer is fi nished, a STOP (P)
condition is generated by transitioning SDA from LOW
to HIGH while SCL is HIGH. The bus is free after a STOP
condition is generated. START and STOP conditions are
always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NACK) by leaving the
SDA line high impedance (the external pull-up resistor will
hold the line HIGH). Change of data only occurs while the
SCL line is LOW.
Data Format
After a START condition, the master sends a 7-bit ad-
dress followed by a read/write (R/W) bit. The R/W bit is
1 for a read request and 0 for a write request. If the 7-bit
address matches one of the LTC2301/LTC2305’s 9 pin-
selectable addresses (see Table 2), the ADC is selected.
When the ADC is addressed during a conversion, it will
not acknowledge R/W requests and will issue a NACK by
leaving the SDA line HIGH. If the conversion is complete,
the LTC2301/LTC2305 issues an ACK by pulling the SDA
line LOW. The LTC2301/LTC2305 has two registers. The
12-bit wide output register contains the last conversion
result. The 6-bit wide input register confi gures the input
MUX and the operating mode of the ADC.
Figure 6. Timing Diagrams of START and STOP Conditions
S
START Condition STOP Condition
P
23015 F06
SDA
SCL
SDA
SCL
LTC2301/LTC2305
17
23015fb
APPLICATIONS INFORMATION
Output Data Format
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters either nap or sleep mode depending on the
setting of the SLP bit (see Nap Mode and Sleep Mode
sections). When the LTC2301/LTC2305 is addressed for a
read operation, it acknowledges by pulling SDA LOW and
acts as a transmitter. The master/receiver can read up to
two bytes from the LTC2301/LTC2305. After a complete
read operation of 2 bytes, a STOP condition is needed to
initiate a new conversion. The device will NACK subsequent
read operations while a conversion is being performed.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 7a). The fi rst bit
is the MSB and the 12th bit is the LSB of the conversion
result. The remaining four bits are zero. Figures 13 and 14
are the transfer characteristics for the bipolar and unipolar
modes. Data is output on the SDA line in 2’s complement
format for bipolar readings and in straight binary for
unipolar readings.
Input Data Format
When the LTC2301/LTC2305 is addressed for a write op-
eration, it acknowledges by pulling SDA LOW during the
LOW period before the 9th cycle and acts as a receiver.
The master/transmitter can then send 1 byte to program
the device. The input byte consists of the 6-bit DIN word
followed by two bits that are ignored by the ADC and are
considered don’t cares (X) (see Figure 7b). The input bits
are latched on the rising edge of SCL during the write
operation.
Figure 7a. Timing Diagram for Reading from the LTC2301/LTC2305
12
A6SDA
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
NACK BY
MASTER
STOP
BY MASTER
CONVERSION
INITIATED
SCL
SCL
(CONTINUED)
A5 A4 A3 A2 A1 A0 R/W
3456789 123456789
123456789
23015 F07a
B11 B10
READ 1 BYTE
B9 B8 B7
MOST SIGNIFICANT DATA BYTE
B6 B5 B4
• • •
• • •
SDA
(CONTINUED) • • •
• • •
B3 B2 B1 B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
Figure 7b. Timing Diagram for Writing to the LTC2301/LTC2305
12
A6SDA
START BY
MASTER
ACK BY
ADC
ACK BY
ADC
CONVERSION
INITIATED
STOP BY
MASTER
SCL
A5 A4 A3 A2 A1 A0 R/W
3456789 123456789
23015 F07b
S/D O/S
WRITE 1 BYTE
X X UNI
DIN WORD
SLP X X
ADDRESS FRAME
NOTE: S/D BIT IS A DON’T CARE (X) FOR THE LTC2301
LTC2301/LTC2305
18
23015fb
APPLICATIONS INFORMATION
After power-up, the ADC initiates an internal reset cycle
which sets the DIN word to all 0s (S/D=O/S=UNI=SLP=0).
A write operation may be performed if the default state
of the ADC’s confi guration is not desired. Otherwise, the
ADC must be properly addressed and followed by a STOP
condition to initiate a conversion.
Initiating a New Conversion
The LTC2301/LTC2305 awakens from either nap or sleep
when properly addressed for a read/write operation. A
STOP command may then be issued after performing the
read/write operation to trigger a new conversion.
Issuing a STOP command after the 8th SCL clock pulse of
the address frame and before the completion of a read/write
operation will also initiate new conversion, but the output
result may not be valid due to lack of adequate acquisition
time (see Acquisition section).
LTC2301/LTC2305 Address
The LTC2301/LTC2305 have two address pins (AD0 and
AD1) that may be tied high, low or left fl oating to enable
one of the 9 possible addresses (see Table 2).
In addition to the confi gurable addresses listed in Table 2,
the LTC2301/LTC2305 also contain a global address
(1101011) which may be used for synchronizing multiple
LTC2301/LTC2305s or other I2C LTC230X SAR ADCs (see
Synchronizing Multiple LTC2301/LTC2305s with Global
Address Call section).
Table 2. Address Assignment
AD1 AD0 ADDRESS
LOW LOW 0001000
LOW Float 0001001
LOW HIGH 0001010
Float HIGH 0001011
Float Float 0011000
Float LOW 0011001
HIGH LOW 0011010
HIGH Float 0011011
HIGH HIGH 0101000
Continuous Read
In applications where the same input channel is sampled
each cycle, conversions can be continuously performed
and read without a write cycle (see Figure 8). The DIN word
remains unchanged from the last value written into the
device. If the device has not been written to since power-
up, the DIN word defaults to all 0s (S/D=O/S=UNI=SLP=0).
At the end of a read operation, a STOP condition may be
given to start a new conversion. At the conclusion of the
conversion cycle, the next result may be read using the
method described above. If the conversion cycle is not
concluded and a valid address selects the device, the
LTC2301/LTC2305 generates a NACK signal indicating the
conversion cycle is in progress.
Figure 8. Consecutive Reading with the Same Confi guration
S
CONVERSION NAP DATA OUTPUT CONVERSION CONVERSIONNAP DATA
OUTPUT
R ACK READ7-BIT ADDRESS P S R ACK
23015 F08
READ7-BIT ADDRESS P
LTC2301/LTC2305
19
23015fb
APPLICATIONS INFORMATION
Continuous Read/Write
Once the conversion cycle is complete, the LTC2301/
LTC2305 can be written to and then read from using the
repeated START (Sr) command. Figure 9 shows a cycle
which begins with a data write, a repeated START, followed
by a read and concluded with a STOP command. After
all 16 bits are read out, a conversion may be initiated by
issuing a STOP command. The following conversion will
be performed using the newly programmed data.
Synchronizing Multiple LTC2301/LTC2305s with a
Global Address Call
In applications where several LTC2301/LTC2305s or other
I2C SAR ADCs from Linear Technology Corporation are
used on the same I2C bus, all converters can be synchro-
nized through the use of a global address call. Prior to
issuing the global address call, all converters must have
completed a conversion cycle. The master then issues a
START, followed by the global address 1101011, and a
write request. All converters will be selected and acknowl-
edge the request. The master then sends a write byte
(optional) followed by the STOP command. This will update
the channel selection (optional) and simultaneously initi-
ate a conversion for all ADCs on the bus (see Figure 10).
In order to synchronize multiple converters without chang-
ing the channel, a STOP command may be issued after
acknowledgement of the global write command. Global
read commands are not allowed and the converters will
NACK a global read request.
Nap Mode
The ADCs enter nap mode after a conversion is complete
(tCONV) if the SLP bit is set to a logic 0. The supply current
decreases to 225A in nap mode between conversions,
thereby reducing the average power dissipation as the
sample rate decreases. For example, the LTC2301/LTC2305
draw an average of 300µA at a 1ksps sampling rate. The
LTC2301/LTC2305 keep only the reference (VREF) and
reference buffer (REFCOMP) circuitry active when in nap
mode.
Figure 9. Write, Read, START Conversion
Figure 10. Synchronize Multiple LTC2301/LTC2305s with a Global Address Call
S
CONVERSION NAP DATA INPUT ADDRESS CONVERSIONDATA
OUTPUT
WACK WRITE7-BIT ADDRESS Sr R ACK
23015 F09
READ7-BIT ADDRESS P
S
SDA
SCL
CONVERSION NAP
LTC2301/LTC2305
DATA OUTPUT CONVERSION OF ALL LTC2301/05s
WACK WRITE (OPTIONAL)GLOBAL ADDRESS P
LTC2301/LTC2305 LTC2301/LTC2305
23015 F10
LTC2301/LTC2305
20
23015fb
APPLICATIONS INFORMATION
Sleep Mode
The ADCs enter sleep mode after a conversion is complete
(tCONV) if the SLP bit is set to a logic 1. The ADCs draw
only 7µA in sleep mode, provided that none of the digital
inputs are switching. When the LTC2301/LTC2305 are
properly addressed, the ADCs are released from sleep
mode and require 200ms (tREFWAKE) to wake up and charge
the respective 2.2F and 10F bypass capacitors on the
VREF and REFCOMP pins. A new conversion should not be
initiated before this time, as shown in Figure 11.
Acquisition
The LTC2301/LTC2305 begin acquiring the input signal at
different instances depending on whether a read or write
operation is being performed. If a read operation is being
performed, acquisition of the input signal begins on the
rising edge of the 9th clock pulse following the address
frame, as shown in Figure 12a.
If a write operation is being performed, acquisition of the
input signal begins on the falling edge of the sixth clock
cycle after the DIN word has been shifted in, as shown in
Figure 12b. The LTC2301/LTC2305 will acquire the signal
from the input channel that was most recently programmed
by the DIN word. A minimum of 240ns is required to acquire
the input signal before initiating a new conversion.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
board should ensure digital and analog signal lines are
S
CONVERSION SLEEP tREFWAKE CONVERSION
R/WACK7-BIT ADDRESS P
23015 F11
Figure 11. Exiting Sleep Mode and Starting a New Conversion
Figure 12a. Timing Diagram Showing Acquisition During a Read Operation
12
A6SDA
SCL
A5 A4 A3 A2 A1 A0 R/W
3456789 12
B11
ACQUISITION BEGINS
tACQ
23015 F12a
B10
Figure 12b. Timing Diagram Showing Acquisition During a Write Operation
12
A2 A1 A0 R/WSDA
SCL
S/D O/S X X UNI X X
34556789 6789
ACQUISITION BEGINS
tACQ 23015 F12b
SLP
LTC2301/LTC2305
21
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separated as much as possible. Care should be taken not
to run any digital signals alongside an analog signal. All
analog inputs should be shielded by GND. VREF, REFCOMP
and VDD should be bypassed to the ground plane as close
to the pin as possible. Maintaining a low impedance path
APPLICATIONS INFORMATION
Figure 15a. Top Silkscreen
for the common return of these bypass capacitors is es-
sential to the low noise operation of the ADC. These traces
should be as wide as possible. See Figures 15a–15e for
a suggested layout.
Figure 13. Bipolar Transfer Characteristics (2’s Complement) Figure 14. Unipolar Transfer Characteristics (Straight Binary)
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
23015 F13
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
FS = 4.096V
1LSB = FS/2n
1LSB = 1mV
INPUT VOLTAGE (V)
OUTPUT CODE
23015 F14
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS – 1LSB0V
UNIPOLAR
ZERO
FS = 4.096V
1LSB = FS/2n
1LSB = 1mV
LTC2301/LTC2305
22
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APPLICATIONS INFORMATION
Figure 15c. Layer 2 Ground Plane
Figure 15d. Layer 3 Power Plane Figure 15e. Bottom Side
Figure 15b. Topside
LTC2301/LTC2305
23
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PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
4.00 p0.10
(2 SIDES)
3.00 p0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 p 0.10
0.75 p0.05
R = 0.115
TYP
R = 0.05
TYP
2.50 REF
16
127
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0806 REV D
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 p0.05
0.70 p0.05
3.60 p0.05
PACKAGE OUTLINE
3.30 p0.10
0.25 p 0.05
0.50 BSC
1.70 p 0.05
3.30 p0.05
0.50 BSC
0.25 p 0.05
LTC2301/LTC2305
24
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MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev Ø)
PACKAGE DESCRIPTION
MSOP (MS12) 1107 REV Ø
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.650
(.0256)
BSC
12 11 10 9 8 7
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 p 0.038
(.0165 p .0015)
TYP
0.65
(.0256)
BSC
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.1016 p 0.0508
(.004 p .002)
123456
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.406 p 0.076
(.016 p .003)
REF
4.90 p 0.152
(.193 p .006)
LTC2301/LTC2305
25
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 8/10 Revised Typical Performance Characteristics curves G03 and G12 7, 8
Revised VREF, REFCOMP and VDD descriptions in Pin Functions section 9, 10
Revised Figure 4 in Applications Information section 15
Revised Figures 5a, 5b and 5c, Internal Reference section and I2C Interface section in Applications Information 15, 16
Changed “NAK” command to NACK 16, 17
(Revision history begins at Rev B)
LTC2301/LTC2305
26
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0810 REV B • PRINTED IN USA
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Driving the LTC2305 with ±10V Input Signals Using a Precision Attenuator
23015 TA02
I2C
PORT
ANALOG
INPUT
MUX
REFCOMP
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC)
INTERNAL
2.5V REF
VDD
5V
10V
–10V
±10V
INPUT
SIGNAL
GND
LTC2305
0.1µF
12-BIT
SAR ADC
+
–
2.2µF
10µF0.1µF
10µF
1µF
0.1µF
47pF
7
45
6
8
1
9
10
100
450k
LT1790-2.5
5V
IN OUT
GND
50k
150k
450k
150k
450k 4pF
VREF
SDA
SCL
1.7k 1.7k
AD1 AD0
CH0CH0
CH1
450k
4pF
3
2
50k
–
+
LT1991