REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Quad, 12-Bit DAC
Voltage Output with Readback
DAC8412/DAC8413
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
FUNCTIONAL BLOCK DIAGRAM
INPUT
REG A OUTPUT
REG A DAC A
A0
A1
DATA I/O
INPUT
REG B
INPUT
REG C
INPUT
REG D
OUTPUT
REG B
OUTPUT
REG C
OUTPUT
REG D
DAC B
DAC C
DAC D
CONTROL
LOGIC
I/O
PORT
R/W
CS
RESET
LDAC
DGND
12
VLOGIC VDD
VOUTA
VOUTB
VOUTC
VOUTD
VSS
VREFH
VREFL
FEATURES
+5 to 615 Volt Operation
Unipolar or Bipolar Operation
True Voltage Output
Double-Buffered Inputs
Reset to Min or Center Scale
Fast Bus Access Time
Readback
APPLICATIONS
Automatic Test Equipment
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
GENERAL DESCRIPTION
The DAC8412 and DAC8413 are quad, 12-bit voltage output
DACs with readback capability. Built using a complementary
BiCMOS process, these monolithic DACs offer the user very
high package density.
Output voltage swing is set by the two reference inputs V
REFH
and V
REFL
. By setting the V
REFL
input to 0 volts and V
REFH
to a
positive voltage, the DAC will provide a unipolar positive output
range. A similar configuration with V
REFH
at 0 volts and V
REFL
at a negative voltage will provide a unipolar negative output
range. Bipolar outputs are configured by connecting both V
REFH
and V
REFL
to nonzero voltages. This method of setting output
voltage range has advantages over other bipolar offsetting meth-
ods because it is not dependent on internal and external resis-
tors with different temperature coefficients.
Digital controls allow the user to load or read back data from
any DAC, load any DAC and transfer data to all DACs at one
time.
An active low RESET loads all DAC output registers to mid-
scale for the DAC8412 and zero scale for the DAC8413.
The DAC8412/DAC8413 are available in 28-pin plastic DIP,
cerdip, PLCC and LCC packages. They can be operated from
a wide variety of supply and reference voltages with supplies
ranging from single +5 volt to ±15 volts, and references from
+2.5 to ±10 volts. Power dissipation is less than 330 mW with
±15 volt supplies and only 60 mW with a +5 volt supply.
For MIL-STD-883 applications, contact your local ADI sales
office for the DAC8412/DAC8413/883 data sheet which speci-
fies operation over the –55°C to +125°C temperature range. All
883 parts are also available on Standard Military Drawings
5962-91-76401MXA through -76404M3A.
INL vs. Code Over Temperature
DAC8412/DAC8413–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units
Integral Linearity “E” INL 0.25 ±0.5 LSB
Integral Linearity “F” INL ±1 LSB
Differential Linearity DNL Monotonic Over Temperature –1 LSB
Min Scale Error V
ZSE
R
L
= 2 kΩ±2 LSB
Full-Scale Error V
FSE
R
L
= 2 kΩ±2 LSB
Min Scale Tempco TCV
ZSE
R
L
= 2 kΩ15 ppm/°C
Full-Scale Tempco TCV
FSE
R
L
= 2 kΩ20 ppm/°C
MATCHING PERFORMANCE
Linearity Matching ±1 LSB
REFERENCE
Positive Reference Input Range Note 2 V
REFL
+ 2.5 V
DD
– 2 5 V
Negative Reference Input Range Note 2 –10 V
REFH
– 2.5 V
Reference High Input Current I
REFH
–2.75 +1.5 +2.75 mA
Reference Low Input Current I
REFL
0 +2 +2.75 mA
AMPLIFIER CHARACTERISTICS
Output Current I
OUT
–5 +5 mA
Settling Time t
S
to 0.01% 6 µs
Slew Rate SR 10% to 90% 2.2 V/µs
LOGIC CHARACTERISTICS
Logic Input High Voltage V
INH
T
A
= +25°C 2.4 V
Logic Input Low Voltage V
INL
T
A
= +25°C 0.8 V
Logic Output High Voltage V
OH
I
OH
= +0.4 mA 2.4 V
Logic Output Low Voltage V
OL
I
OL
= –1.6 mA 0.4 V
Logic Input Current I
IN
1µA
Input Capacitance C
IN
8pF
Crosstalk >72 dB
Large Signal Bandwidth –3 dB, V
REFH
= 0 to +10 V p-p 160 kHz
LOGIC TIMING CHARACTERISTICS Note 3
WRITE
Chip Select Write Pulse Width t
WCS
80 40 ns
Write Setup t
WS
t
WCS
= 80 ns 0 ns
Write Hold t
WH
t
WCS
= 80 ns 0 ns
Address Setup t
AS
0ns
Address Hold t
AH
0ns
Load Setup t
LS
70 30 ns
Load Hold t
LH
30 10 ns
Write Data Setup t
WDS
t
WCS
= 80 ns 20 ns
Write Data Hold t
WDH
t
WCS
= 80 ns 0 ns
Load Pulse Width t
LWD
170 130 ns
Reset Pulse Width t
RESET
140 100 ns
READ
Chip Select Read Pulse Width t
RCS
130 100 ns
Read Data Hold t
RDH
t
RCS
= 130 ns 0 ns
Read Data Setup t
RDS
t
RCS
= 130 ns 0 ns
Data to Hi Z t
DZ
C
L
= 10 pF 150 ns
Chip Select to Data t
CSD
C
L
= 100 pF 120 160 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSS 14.25 V ≤ V
DD
≤ 15.75 V 150 ppm/V
Positive Supply Current I
DD
V
REFH
= +2.5 V 8.5 12 mA
Negative Supply Current I
SS
–10 –6.5 mA
Power Dissipation P
DISS
330 mW
NOTES
1
All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.
2
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
3
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
REV. C
–2–
(@ VDD = +15.0 V, VSS = –15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V,
–408C ≤ TA ≤ +858C unless otherwise noted. See Note 1 for supply variations.)
DAC8412/DAC8413
REV. C –3–
(@ VDD = VLOGIC = +5.0 V 6 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and
VSS = –5.0 V 6 5%, VREFL = –2.5 V, –408C ≤ TA ≤ +858C unless otherwise noted.
See Note 1 for supply variations.)
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units
Integral Linearity “E” INL 1/2 ±1 LSB
Integral Linearity “F” INL ±2 LSB
Integral Linearity “E” INL V
SS
= 0.0 V; Note 2 ±2 LSB
Integral Linearity “F” INL V
SS
= 0.0 V; Note 2 ±4 LSB
Differential Linearity DNL Monotonic Over Temperature –1 LSB
Min Scale Error V
ZSE
V
SS
= –5.0 V ±4 LSB
Full-Scale Error V
FSE
V
SS
= –5.0 V ±4 LSB
Min Scale Error V
ZSE
V
SS
= 0.0 V ±8 LSB
Full-Scale Error V
FSE
V
SS
= 0.0 V ±8 LSB
Min Scale Tempco TCV
ZSE
100 ppm/°C
Full-Scale Tempco TCV
FSE
100 ppm/°C
MATCHING PERFORMANCE
Linearity Matching ±1 LSB
REFERENCE
Positive Reference Input Range Note 3 V
REFL
+ 2.5 V
DD
– 2 5 V
Negative Reference Input Range V
SS
= 0.0 V 0 V
REFH
– 2.5 V
Negative Reference Input Range V
SS
= –5.0 V –2.5 V
REFH
– 2.5 V
Reference High Input Current I
REFH
Code 000H –1.0 +1.0 mA
AMPLIFIER CHARACTERISTICS
Output Current I
OUT
–1.25 +1.25 mA
Settling Time t
S
to 0.01% 6 µs
Slew Rate SR 10% to 90% 2.2 V/µs
LOGIC CHARACTERISTICS
Logic Input High Voltage V
INH
T
A
= +25°C 2.4 V
Logic Input Low Voltage V
INL
T
A
= +25°C 0.8 V
Logic Output High Voltage V
OH
I
OH
= +0.4 mA 2.4 V
Logic Output Low Voltage V
OL
I
OL
= –1.6 mA 0.45 V
Logic Input Current I
IN
1µA
Input Capacitance C
IN
8pF
LOGIC TIMING CHARACTERISTICS Note 4
WRITE
Chip Select Write Pulse Width t
WCS
150 90 ns
Write Setup t
WS
t
WCS
= 150 ns 0 ns
Write Hold t
WH
t
WCS
= 150 ns 0 ns
Address Setup t
AS
0ns
Address Hold t
AH
0ns
Load Setup t
LS
70 30 ns
Load Hold t
LH
50 20 ns
Write Data Setup t
WDS
t
WCS
= 150 ns 20 ns
Write Data Hold t
WDH
t
WCS
= 150 ns 0 ns
Load Pulse Width t
LWD
180 130 ns
Reset Pulse Width t
RESET
150 110 ns
READ
Chip Select Read Pulse Width t
RCS
170 120 ns
Read Data Hold t
RDH
t
RCS
= 170 ns 20 ns
Read Data Setup t
RDS
t
RCS
= 170 ns 0 ns
Data to Hi Z t
DZ
C
L
= 10 pF 200 ns
Chip Select to Data t
CSD
C
L
= 100 pF 220 320 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSS 100 ppm/V
Positive Supply Current I
DD
712 mA
Negative Supply Current I
SS
V
SS
= –5.0 V –10 mA
NOTES
1
All supplies can be varied ±5%, and operation is guaranteed. Device is tested with V
DD
= +4.75 V.
2
For single supply operation only (V
REFL
= 0.0 V, V
SS
= 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002
H
).
3
Operation
is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
DAC8412/DAC8413
REV. C
–4–
WAFER TEST LIMITS
DAC8412GBC
DAC8413GBC
Parameter Symbol Conditions Limit Units
Integral Nonlinearity INL +1 LSB max
Differential Nonlinearity DNL +1 LSB max
Min Scale Offset V
ZSE
+1 LSB max
Full-Scale Offset V
FSE
+1 LSB max
Logic Input High Voltage V
INH
2.4 V min
Logic Input Low Voltage V
INL
0.8 V max
Logic Input Current I
IN
1µA max
Logic Output High Voltage V
OH
I
OH
= +0.4 mA 2.4 V min
Logic Output Low Voltage V
OL
I
OL
= –1.6 mA 0.4 V max
Positive Supply Current I
DD
V
REFH
= +2.5 V 12 mA max
Negative Supply Current I
SS
–10 mA min
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
(
T
A
= +25°C unless otherwise noted)
V
SS
to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V
V
SS
to V
LOGIC
. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +33.0 V
V
LOGIC
to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18.0 V
V
SS
to V
REFL
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +V
SS
–2.0 V
V
REFH
to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V
V
REFH
to V
REFL
. . . . . . . . . . . . . . . . . . . . . . . . +2.0 V, V
SS
–V
DD
Current into Any Pin 4 . . . . . . . . . . . . . . . . . . . . . . . ±15 mA
Digital Input Voltage to DGND . . . . . –0.3 V, V
LOGIC
+0.3 V
Digital Output Voltage to DGND . . . . . . . . . . –0.3 V, +7.0 V
Operating Temperature Range
ET, FT, EP, FP, FPC . . . . . . . . . . . . . . . . –40°C to +85°C
AT, BT, BTC . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation Package . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
Thermal Resistance
Package Type θ
JA
*θ
JC
Units
28-Pin Hermetic DIP (T) 50 7 °C/W
28-Pin Plastic DIP (P) 48 22 °C/W
28-Lead Hermetic Leadless Chip Carrier (TC) 70 28 °C/W
28-Lead Plastic Leaded Chip Carrier (PC) 63 25 °C/W
NOTE
*θ
JA
is specified for worst case mounting conditions, i. e., θ
JA
is specified for device
in socket.
DICE CHARACTERISTICS
CAUTION
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation at or above this specification is not
implied. Exposure to the above maximum rating conditions for extended periods may affect
device reliability.
2. Digital inputs and outputs are protected, however, permanent damage may occur on unprotected units
from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until
ready to use. Use proper antistatic handling procedures.
3. Remove power before inserting or removing units from their sockets.
4. Analog outputs are protected from short circuit to ground or either supply.
WARNING!
ESD SENSITIVE DEVICE
(@ VDD = +15.0 V, VSS = –15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = –10.0 V, TA = +258C unless
otherwise noted.)
DAC8412/DAC8413
REV. C –5–
ORDERING INFORMATION
1
Extended
Military
2
Industrial
2
INL Temperature Temperature Package
(LSB) –558C to +1258C –408C to +858C Package Option
±1 DAC8412FPC PLCC P-28A
±1.5 DAC8412BTC/883 LCC E-28A
±0.5 DAC8412ET Cerdip Q-28
±0.75 DAC8412AT/883 Cerdip Q-28
±1 DAC8412FT Cerdip Q-28
±1.5 DAC8412BT/883 Cerdip Q-28
±0.5 DAC8412EP Plastic N-28
±1 DAC8412FP Plastic N-28
±1 DAC8412GBC Dice
±1 DAC8413FPC PLCC P-28A
±1.5 DAC8413BTC/883 LCC E-28A
±0.5 DAC8413ET Cerdip Q-28
±0.75 DAC8413AT/883 Cerdip Q-28
±1 DAC8413FT Cerdip Q-28
±1.5 DAC8413BT/883 Cerdip Q-28
±0.5 DAC8413EP Plastic N-28
±1 DAC8413FP Plastic N-28
±1 DAC8413GBC Dice
NOTES
1
Burn-in is available on extended industrial temperature range parts in cerdip.
2
A complete /883 data sheet is available. For availability and burn-in informa-
tion, contact your local sales office.
DATA VALID
A0/A1
DATA
OUT
tRCS
tRDS tRDH
tCSD
tAS tAH
tDZ
CS
R/W
Data Output (Read) Timing
A0/A1
t
WCS
t
WS
t
WH
t
LWD
t
AS
t
AH
CS
R/W
DATA IN
LDAC
RESET
t
LH
t
RESET
t
LS
t
DS
t
DH
Data WRITE (Input and Output Registers) Timing
PIN CONFIGURATIONS
Cerdip
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC8412
DAC8413
TOP VIEW
(Not to Scale)
DGND
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6 DB7
DB8
DB9
DB10
DB11 (MSB)
A1
A0
V
REFH
V
OUTB
V
OUTA
V
SS
V
REFL
V
OUTC
V
OUTD
V
DD
V
LOGIC
CS
R/W
RESET
LDAC
PLCC
DGND
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11 (MSB)
A1
A0
VSS
VDD
VLOGIC
CS
R/W
RESET
LDAC
DAC8412PC
DAC8413PC
TOP VIEW
(Not to Scale)
28 27 261234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12 13 14 15 16 17 18
VOUTA
VOUTB
VREFH
VREFL
VOUTC
VOUTD
LCC
DAC8412TC
DAC8413TC
TOP VIEW
(Not to Scale)
28 27 26
1
234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12 13 14 15 16 17 18
DGND
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11 (MSB)
A1
A0
V
SS
V
DD
V
LOGIC
CS
R/W
RESET
LDAC
V
OUTA
V
OUTB
V
REFH
V
REFL
V
OUTC
V
OUTD
DAC8412/DAC8413
REV. C
–6–
Table I. DAC8412/DAC8413 Logic Table
A1 A0 R/WCS RS LDAC INPUT REG OUTPUT REG MODE DAC
L L L L H L WRITE WRITE WRITE A
L H L L H L WRITE WRITE WRITE B
H L L L H L WRITE WRITE WRITE C
H H L L H L WRITE WRITE WRITE D
L L L L H H WRITE HOLD WRITE INPUT A
L H L L H H WRITE HOLD WRITE INPUT B
H L L L H H WRITE HOLD WRITE INPUT C
H H L L H H WRITE HOLD WRITE INPUT D
L L H L H H READ HOLD READ INPUT A
L H H L H H READ HOLD READ INPUT B
H L H L H H READ HOLD READ INPUT C
H H H L H H READ HOLD READ INPUT D
X X X H H L HOLD Update all output registers All
X X X H H H HOLD HOLD HOLD All
X X X X L X *All registers reset to mid/zero-scale All
XXXHgX *All registers latched to mid/zero-scale All
*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care.
DB7
DB8
DB9
DB10
DB11
A1
A0
V
REFL
V
OUTC
V
OUTD
V
DD
V
LOGIC
CS
R/W
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
V
REFH
V
OUTB
V
OUTA
V
SS
RESET
LDAC
R3 R3
R3
ONCE PER PORT
*
V
DD
V
REFH
V
REFL
GND
V
SS
D1 D1
C1 C1 C1 D1
C2
C2
N/C
N/C
R6
R1
C1
D1 +
++
+
R5 R4 R4
C2
C2
N/C
N/C
R1
R2 R2
V = +15V, V = –15V, V = +10V, V = –10V
R1 = 10Ω, R2 = 100Ω, R3 = 5kΩ, R4 = 10kΩ, R5 = 100kΩ,
R6 = 47Ω for LCC, R6 = 100Ω for DIP
C1 = 4.7 µF (ONCE PER PORT), C2 = 0.01µF (EACH DEVICE)
D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)
DD SS REFH REFL
DAC8412/DAC8413 Burn-In Diagram
OPERATION
Introduction
The DAC8412 and DAC8413 are quad, voltage output, 12-bit
DACs featuring a 12-bit data bus with readback capability. The
only differences between the DAC8412 and DAC8413 are the
reset functions. The DAC8412 resets to midscale (code 800
H
)
and the DAC8413 resets to minimum scale (code 000
H
).
The ability to operate from a single +5 volt only supply is a
unique feature of these DACs.
dividing the system into three separate functional groups: the
digital I/O and logic, the digital to analog converters and the
output amplifiers.
DACs
Each DAC is a voltage switched, high impedance (R = 50 kΩ),
R-2R ladder configuration. Each 2R resistor is driven by a pair
of switches that connect the resistor to either V
REFH
or V
REFL
.
Reference Inputs
All four DACs share common reference high (V
REFH
) and refer-
ence low (V
REFL
) inputs. The voltages applied to these reference
inputs set the output high and low voltage limits of all four of
the DACs. Each reference input has voltage restrictions with re-
spect to the other reference and to the power supplies. The
V
REFL
can be set at any voltage between V
SS
and V
REFH
– 2.5 volts,
and V
REFH
can be set to any value between +V
DD
– 2.5 volts and
V
REFL
+ 2.5 volts. Note that because of these restrictions the
DAC8412 references cannot be inverted (i.e., V
REFL
cannot be
greater than V
REFH
).
It is important to note that the DAC8412’s V
REFH
input both
sinks and sources current. Also the input current of both V
REFH
and V
REFL
are code dependent. Many references have limited
current sinking capability and must be buffered with an ampli-
fier to drive V
REFH
. The V
REFL
has no such special requirements.
It is recommended that the reference inputs be bypassed with
0.2 µF capacitors when operating with ±10 volt references.
Digital I/O
See Table I for digital control logic truth table. Digital I/O con-
sists of a 12-bit wide bidirectional data bus, two register select
inputs, A0 and A1, a R/W input, a RESET input, a Chip Select
(CS), and a Load DAC (LDAC) input. Control of the DACs
and bus direction is determined by these inputs as shown in
Table I. Digital data bits are labeled with the MSB defined as
data bit “11” and the LSB as data bit “0.” All digital pins are
TTL/CMOS compatible.
DAC8412/DAC8413
REV. C –7–
ADDRESS
DECODE INPUT
REG A OUTPUT
REG A
*WRA
*RDA
12 12
12
DAC A
*RDD
*WRD
TO
AMPLIFIER
RESET
A0
A1
CS
R/W
DATA
LDAC
R/W
DECODE
*NOTE: THE SIGNALS RDA, WRA, ETC., ARE INTERNAL CONTROL SIGNALS.
THEY ARE INCLUDED FOR CLARIFICATION ONLY.
Figure 1. I/O Logic Diagram
See Figure 1 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers “A”
(binary code 00) through “D” (binary code 11). Decoding of
the registers is enabled by the CS input. When CS is high no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the LDAC input. By taking CS low
while CS is high, all output registers can be updated simulta-
neously. Note that the t
LWD
required pulse width for updating
all DACs is a minimum of 170 ns.
The R/W input, when enabled by CS, controls the writing to
and reading from the input register.
Coding
Both the DAC-8412 and DAC8413 use binary coding. The
output voltage can be calculated by:
VOUT =VREFL +(VREFL _VREFL )*N
4096
where N is the digital code in decimal.
RESET
The RESET function can be used either at power-up or at any
time during the DAC’s operation. The RESET function is inde-
pendent of CS. This pin is active LOW and sets the DAC out-
put registers to either center code for the DAC8412, or zero
code for the DAC8413. The reset to center code is most useful
when the DAC is configured for bipolar references and an out-
put of zero volts after reset is desired.
Supplies
Supplies required are V
SS
, V
DD
and V
LOGIC
. The V
SS
supply can
be set between –15 volts and 0 volts. V
DD
is the positive supply;
its operating range is between +5 and +15 volts.
V
LOGIC
is the digital output reference voltage for the readback
function. It is normally connected to +5 volts. This pin is a
logic reference input only. It does not supply current to the de-
vice. If you are not using the readback function, V
LOGIC
can be
hardwired to V
DD
. While V
LOGIC
does not supply current to the
DAC8412, it does supply currents to the digital outputs when
readback is used.
Amplifiers
Unlike many voltage output DACs, the DAC8412 features buff-
ered voltage outputs. Each output is capable of both sourcing
and sinking 5 mA at ±10 volts, eliminating the need for external
amplifiers in most applications. These amplifiers are short cir-
cuit protected.
Careful attention to grounding is important to accurate opera-
tion of the DAC8412. This is not because the DAC8412 is
more sensitive than other 12-bit DACs, but because with four
outputs and two references there is greater potential for ground
loops. Since the DAC8412 has no analog ground, the ground
must be specified with respect to the reference.
Reference Configurations
Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices a wide variety of options ex-
ists. The unipolar configuration can be either positive or nega-
tive voltage output, and the bipolar configuration can be either
symmetrical or nonsymmetrical.
OP-400
REF10
DAC8412
OR
DAC8413
+
+15V
INPUT OUTPUT
TRIM 10kΩ
V
REFH
0.2µF
V
REFL
+10V OPERATION
Figure 2. Unipolar +10 V Operation
DAC8412
OR
DAC8413
+15V
V
REFH
1µF±5 OR ±10V OPERATION
0.2µF
0.2µF
4
6
12
5
813
7
15
14
1
3
AD688
For ± 10v
AD588
For ± 5v
39kΩ
6.2Ω
6.2ΩV
REFL
BALANCE
100kΩ
GAIN
100kΩ
Figure 3. Symmetrical Bipolar Operation
Figure 3 (Symmetrical Bipolar Operation) shows the DAC8412
configured for ±10 volt operation. Note: See the AD688 data
sheet for a full explanation of reference operation. Adjustments may
not be required for many applications since the AD688 is a very
high accuracy reference. However if additional adjustments are
required, adjust the DAC8412 full scale first. Begin by loading
the digital full-scale code (FFF
H
), and then adjust the Gain Ad-
just potentiometer to attain a DAC output voltage of 9.9976
volts. Then, adjust the Balance Adjust to set the center scale
output voltage to 0.000 volts.
The 0.2 µF bypass capacitors shown at the reference inputs in
Figure 3 should be used whenever ±10 volt references are used.
Applications with single references or references to ±5 volts
may not require the 0.2 µF bypassing. The 6.2 Ω resistor in
series with the output of the reference amplifier is to keep the
amplifier from oscillating with the capacitive load. We have
DAC8412/DAC8413
REV. C
–8–
found that this is large enough to stabilize this circuit. Larger
resistor values are acceptable, provided that the drop across the
resistor doesn’t exceed a V
BE
. Assuming a minimum V
BE
of 0.6
volts and a maximum current of 2.75 mA, then the resistor
should be under 200 Ω for the loading of a single DAC8412.
Using two separate references is not recommended. Having two
references could cause different drifts with time and tempera-
ture; whereas with a single reference, most drifts will track.
Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 volt full-scale output, the circuit can be configured as shown in
Figure 2. In this configuration the full-scale value is set first by
adjusting the 10 kΩ resistor for a full-scale output of
9.9976 volts.
REF08 DAC8412
OR
DAC8413
–15V
TRIM
10kΩ
VREFH
0.2µF
VREFL
ZERO TO –10V OPERATION
GND
.01µF
10µF
OUT
Figure 4. Unipolar –10 V Operation
Figure 4 shows the DAC8412 configured for –10 volt to zero
volt operation. A REF08 with a –10 volt output is connected
directly to V
REFL
for the reference voltage.
Single +5 Volt Supply Operation
For operation with a +5 volt supply, the reference should be set
between 1.0 and +2.5 volts for optimum linearity. Note that
lower reference voltages will have greater effects due to noise.
Figure 5 shows a REF43 used to supply a +2.5 volt reference
voltage. The headroom of the reference and DAC are both suf-
ficient to support a +5 volt supply with ±5% tolerance. V
DD
and
V
LOGIC
should be connected to the same supply and separate
bypassing to each pin should be used.
REF43
DAC8412
OR
DAC8413
+5V
TRIM 10kΩ
V
REFH
0.2µF
V
REFL
ZERO TO +2.5V OPERATION
SINGLE +5V SUPPLY
GND
0.01µF
10µF
OUTPUT
INPUT
Figure 5. +5 V Single Supply Operation
+1
–1
6
0
121110987
MAXIMUM LINEARITY ERROR – LSB
V – Volts
REFH
V = +15V
V = –15V
V = –10.0V
T = +25˚C
DD
REFL
A
SS
Differential Linearity vs. V
REFH
MAXIMUM LINEARITY ERROR – LSB
V – Volts
REFH
0
–2
–1
+2
+1
321
V = +5V
V = 0V
V = 0V
T = +25˚C
DD
SS
REFL
A
Differential Linearity vs. V
REFH
MAXIMUM LINEARITY ERROR – LSB
V – Volts
REFH
0.3
0.1
0.2
1086 12
V = +15V
V = –15V
V = 0V
T = +25˚C
DD
SS
REFL
A
INL vs. V
REFH
Typical Performance Characteristics
DAC8412/DAC8413
REV. C –9–
MAXIMUM LINEARITY ERROR – LSB
V – Volts
REFH
+1
–1
0
123
V = +5V
V = 0V
V = 0V
T = +25°C
DD
SS
REFL
A
INL vs. V
REFH
V = +15V
V = –15V
V = +10V
V = –10V
DD
SS
REFL
FULL-SCALE ERROR – LSB
0.4
–0.6 1000
–0.4
0
0
–0.2
0.2
600400 800200
T = HOURS OF OPERATION AT +125°C
REFH
X
X+3
σ
X–3
σ
Full-Scale Error vs. Time
Accelerated by Burn-In
ZERO-SCALE ERROR – LSB
0.3
–0.7 1000
–0.5
0
–0.1
–0.3
0.1
600400 800200
T = HOURS OF OPERATION AT +125°C
X
V = +15V
V = –15V
V = +10V
V = –10V
DD
SS
REFL
REFH
X+3
σ
X–3
σ
Zero-Scale Error vs. Time
Accelerated by Burn-In
150–75 750
0.2
–0.6
–0.4
–0.2
0
FULL-SCALE ERROR – LSB
TEMPERATURE – °C
DAC A DAC D
DAC B
DAC C
V = +15V
V = –15V
V = +10V
V = –10V
DD
SS
REFL
REFH
Full-Scale Error vs. Temperature
0.3
–0.5 150
–0.3
–75
–0.1
0.1
750
ZERO-SCALE ERROR – LSB
TEMPERATURE – °C
DAC A
DAC D DAC C
V = +15V
V = –15V
V = +10V
V = –10V
DD
SS
REFL
REFH
DAC B
Zero-Scale Error vs. Temperature
Channel-to-Channel Matching (V
SUPPLY
=
±
15 V) Channel-to-Channel Matching (V
SUPPLY
= +5 V)
DAC8412/DAC8413
REV. C
–10–
I
VREFH
vs. Code
V – Volts
REFH
13
413–7
7
10
951–3
I – mA
DD
V = +15V
V = –15V
V = –10V
DD
SS
REFL
I
DD
vs. V
REFH
All DACS High I
NL
vs. Code
Settling Time (Positive)
Settling Time (Negative) Positive Slew Rate Negative Slew Rate
DAC8412/DAC8413
REV. C –11–
TEMPERATURE – °C
10
–10 150
–6
–75
2
–2
6
750
POWER SUPPLY CURRENT – mA
I
DD
I
SS
V = +15V
V = –15V
DD
SS
Power Supply Current vs.
Temperature
100
01M
60
20
100
40
10
80
100k10k1k
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
+PSRR
–PSRR
+PSRR:
V = +15V±1V
V = –15V
–PSRR:
V = +15V
V = –15V±1V
V = 10V
ALL DATA 0
DD
SS
DD
SS
P
P
REFH
PSRR vs. Frequency
10M1001M
100k10k1k
100
V = +15V
V = –15V
V = 0 ±100mV
V = –10V
DATA BITS = +5V
200mV
DD
SS
REFL
REFH
P–P
–10
0
–30
–50
GAIN – dB
FREQUENCY – Hz
Small Signal Response
0
025
–20
–30
–25 –20
0
–10
10
20
30
20151050–5–10–15
V = +15V
V = –15V
V = +10V
V = –10V
T = +25˚C
DATA = 000
H
DD
SS
REFL
REFH
A
I – mA
OUT
V – Volts
OUT
I
OUT
vs. V
OUT
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Position Leadless Chip Carrier
(TC Suffix)
SIDE VIEW
TOP VIEW
BOTTOM
VIEW
0.075 (1.91) REF
0.458 (11.63)
0.442 (11.23)
0.300 (7.62)
REF
0.075 (1.91)
REF
0.458 (11.63) MAX
PLANE 2 PLANE 1
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
0.093 (2.36)
0.077 (1.96)
0.055 (1.40)
0.045 (1.14)
0.200 (5.08) BSC
45° TYP
0.050 (1.27) MIN
0.150 (3.81) REF 0.015 (0.38) MIN
0.028 (0.71)
0.022 (0.56)
DAC8412/DAC8413
REV. C
–12–
C1544–24–5/91
PRINTED IN U.S.A.
28-Lead PLCC
(PC Suffix)
PIN 1
IDENTIFIER
426
5
11
25
19
12 18
0.430 (10.920)
0.390 (9.910)
0.021 (0.533)
0.013 (0.331)
0.032 (0.812)
0.026 (0.661)
0.180 (4.51)
0.165 (4.20)
0.456 (11.582)
0.450 (11.430)
TOP VIEW
0.020 (0.510) MIN
SEATING PLANE
x 45°
0.050 (1.270)
BSC
0.048 (1.219)
0.042 (1.067)
0.495 (12.570)
0.485 (12.320)
28-Lead Cerdip
(T Suffix)
28
1
15
14
SEATING
PLANE
1.490 (37.85) MAX
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
15°
0°
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
0.008 (0.20)
0.610 (15.49)
0.500 (12.70)
0.225
MAX
(5.72)
0.100 (2.54)
BSC
0.150
(3.81)
MIN
0.120 (3.05)
0.200 (5.08)
0.005 (0.13) MIN 0.098 (2.49) MAX
PIN 1
0.075 (1.91)
0.015 (0.38)
28-Lead Epoxy DIP
(P Suffix)
28
1
15
14
SEATING
PLANE
0.130
(3.32)
MIN
0.022 (0.558)
0.014 (0.36)
0.015 (0.381)
0.008 (0.203)
0.580 (14.73)
0.485 (12.32)
1.565 (39.70)
1.380 (35.10)
0.250
(6.35)
MAX
0.625 (15.87)
0.600 (15.24)
0.100 (2.54)
BSC
PIN 1
0.200 (5.08)
0.115 (2.93)
0.015 (0.39) MIN
15°
0°
0.070 (1.78)
0.030 (0.76)
