DS26324GN+T&R - Maxim Integrated

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Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any devic e

may be simultaneousl y available through various sales channe ls . F or inf or ma tion about device err ata, c lick her e:

www.maxim-ic.com/errata

.

GENERAL DESCRIPTION

The DS26324 is a 16-channel short-haul line

interface unit (LIU) that supports E1/T1/J1 from a

single 3.3V power supply. A wide variety of

applications are supported through internal

impedance matching. A single bill of material can

support E1/T1/J1 that requires no external

termination. Redundancy is supported through

nonintrusive monitoring, optimal high-impedance

modes and configurable 1:1 or 1+1 backup

enhancement s. A n on-c hip synthesi z er gener ates the

E1/T1/ J 1 cl oc k r ates by a singl e master cl ock input of

v arious f requenci es. Two cl ock out put ref erences are

also offered. The device is offered in a 256-pin

TE-CSBGA, the smallest package available for a

16-channel LIU.

APPLICATIONS

T1 D igital Cros s -Connects

ATM and Frame Relay Equipment

Wireless Base Stations

ISDN P rimary Rate Int erface

E1/T1/ J 1 Multiplexer and Channel B ank s

E1/T1/ J 1 LAN/WAN Routers

FUNCTIONAL DIAGRAM

TNEG

RCLK

TPOS

TCLK

RPOS

RNEG

SOFTWARE CONTROL

AND JTAG

TRANSMITTER

RECEIVER

LOSS

1

16

RTIP

RRING

JTAG

TTIP

TRING

FEATURES

 16 E1, T1, or J1 Short-Haul Line Interface

Units

 Independent E1, T1 or J1 Selections

 Fully Internal Impedance Match Requires No

Extern al Resi stors

 Software-Sel ect able Tran smit and Receive-

Side Impedance Match

 Crystal-Less Ji t t er Atten uator

 Sele c t a ble Single-Rail and Dual-Rai l Mod e

and AMI or HDB3/ B8ZS Line Encod in g and

Decoding

 Detection and Generation of AIS

 Digital/Analog Loss of Signal Detection as

per T 1.231, G.775 and ETS 300 233

 Extern al Mast er Clo ck Can Be Mul tipl e of

2.048MHz or 1.544MHz for T1/J1 or E1

Operation; This Clock Will Be Internally

A da pt e d for T1 or E1 Usage

 Receiver Sig nal Level Indicat or from -2.5dB to

-20dB in 2.5dB Incremen t s

 Two Built-In BE RT Testers for Diagno st ics

 8-Bit Parall el Int erf ace Supp ort for Intel or

Motorola Mode or a 4-Wire Serial Interface

 Transmit Short-Circuit Protection

 G.772 Nonintrusive Monitoring

 Receive Monit or Mode Handles Combinatio ns

of 14dB to 20dB of Resistive Atten uatio n

Along with 12dB to 30dB of Cable Attenuation

 Specification Compliance to the Latest T1

and E1 Standar ds

 Single 3.3V Supply with 5V Tolerant I/O

 JTAG Boundary Scan as P er IEEE 1149. 1

ORDERING INFORMATION

PART T E M P RANGE PIN-PACKAGE

DS26324G+

0°C to +70°C

256 TE-CSBGA

DS26324GN+

-40°C to +85°C

256 TE-CSBGA

DS26324G

0°C to +70°C

256 TE-CSBGA

DS26324GN

-40°C to +85°C

256 TE-CSBGA

+Denotes a lead(Pb)-free/RoHS compliant package.

DEMO KIT AVAILABLE

DS26324

3.3V, 16-Channel, E1/T1/J1 Short-

Haul Line Interface Unit

19-5754; Rev 3/11

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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TABLE OF CONTENTS

1 ST AND ARDS COMPLIANCE ........................................................................................................ 6

1.1 TELECOM SPECIFICATIONS CO MPLIANCE ....................................................................................... 6

2 DET AILED DESCRIPTION ............................................................................................................ 7

3 BLOCK DIAGR AMS ...................................................................................................................... 8

4 PIN DESCRIPTION ...................................................................................................................... 10

5 FUNCTIONAL DESCRIPTION ..................................................................................................... 17

5.1 PORT OPERATION ...................................................................................................................... 17

5.1.1 Serial Port Operation ..................................................................................................................... 17

5.1.2 Parallel P or t Oper ation ................................................................................................................... 18

5.1.3 Interr upt Handling .......................................................................................................................... 18

5.2 POWER-UP AND RESET .............................................................................................................. 19

5.3 MASTER CLOCK ......................................................................................................................... 19

5.4 TRANSMITTER ............................................................................................................................ 20

5.4.1 Transmit Line Templates ................................................................................................................ 22

5.4.2 LIU Transmit Front-End .................................................................................................................. 25

5.4.3 Tr ans m it Dual-Rail Mode ............................................................................................................... 26

5.4.4 Transmit Single-Rail Mode ............................................................................................................. 26

5.4.5 Zer o S uppr es s ion—B 8ZS or HDB3 ................................................................................................ 26

5.4.6 Transmit Power-Down.................................................................................................................... 26

5.4.7 Transmit All Ones .......................................................................................................................... 27

5.4.8 Driver Fail Monit or.......................................................................................................................... 27

5.5 RECEIVER .................................................................................................................................. 27

5.5.1 Receiver Impedanc e M atching Calibration ..................................................................................... 27

5.5.2 Receiver M onitor Mode .................................................................................................................. 27

5.5.3 Peak Detect or and Slicer ............................................................................................................... 28

5.5.4 Receive Lev el Indicator .................................................................................................................. 28

5.5.5 Clock and Data Recover y............................................................................................................... 28

5.5.6 Loss of Signal ................................................................................................................................ 28

5.5.7 AIS ................................................................................................................................................ 29

5.5.8 Receive Dual-Rail M ode ................................................................................................................ 29

5.5.9 Receive S ingle-Rail Mode .............................................................................................................. 30

5.5.10 Bipolar V iolation and Exc es s iv e Zero Detector ............................................................................... 30

5.6 JITTER ATTENUATOR .................................................................................................................. 31

5.7 G.772 MONITOR ........................................................................................................................ 32

5.8 LOOPBACKS ............................................................................................................................... 32

5.8.1 Analog Loopback ........................................................................................................................... 32

5.8.2 Digital Loopbac k ............................................................................................................................ 33

5.8.3 Remot e Loopbac k .......................................................................................................................... 33

5.9 BERT........................................................................................................................................ 34

5.9.1 Gener al Des c r iption ....................................................................................................................... 34

5.9.2 Configur ation and Monit or ing ......................................................................................................... 35

5.9.3 Receive P atter n Detection.............................................................................................................. 36

5.9.4 Transmit Pattern Generation .......................................................................................................... 38

6 REGISTER MAPS AND DEFINITION .......................................................................................... 39

6.1 REGISTER DESCRIPTION ............................................................................................................. 48

6.1.1 Prim ar y Regis ter Bank ................................................................................................................... 48

6.1.2 Secondar y Regis ter Bank............................................................................................................... 63

6.1.3 Individ ual LIU Reg is ter B ank .......................................................................................................... 66

6.1.4 BERT Regist er s ............................................................................................................................. 84

7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................................. 91

7.1 TAP CONTROLLER STATE MACHINE ............................................................................................ 92

7.1.1 Test-Logic-Reset ........................................................................................................................... 92

7.1.2 Run-Test-Idle ................................................................................................................................. 92

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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7.1.3 Select-DR-Scan ............................................................................................................................. 92

7.1.4 Capture-DR ................................................................................................................................... 92

7.1.5 Shift-DR ......................................................................................................................................... 92

7.1.6 Exit1-DR ........................................................................................................................................ 92

7.1.7 Pause-DR ...................................................................................................................................... 92

7.1.8 Exit2-DR ........................................................................................................................................ 92

7.1.9 Update-DR..................................................................................................................................... 92

7.1.10 Select-IR-Scan............................................................................................................................... 93

7.1.11 Capture-IR ..................................................................................................................................... 93

7.1.12 Shift-IR .......................................................................................................................................... 93

7.1.13 Exit1-IR.......................................................................................................................................... 93

7.1.14 Pause-IR ....................................................................................................................................... 93

7.1.15 Exit2-IR.......................................................................................................................................... 93

7.1.16 Update-IR ...................................................................................................................................... 93

7.2 INSTRUCTION REGISTER ............................................................................................................. 95

7.2.1 EXTEST ........................................................................................................................................ 95

7.2.2 HIGHZ ........................................................................................................................................... 95

7.2.3 CLAMP .......................................................................................................................................... 95

7.2.4 SAMPLE/PRELOAD ...................................................................................................................... 95

7.2.5 IDCODE ........................................................................................................................................ 95

7.2.6 BYPASS ........................................................................................................................................ 95

7.3 TEST REGISTERS ....................................................................................................................... 96

7.3.1 Boundary S c an Regis ter ................................................................................................................ 96

7.3.2 Bypas s Regis ter ............................................................................................................................. 96

7.3.3 Identif ic ation Regist er .................................................................................................................... 96

8 DC ELECTRIC AL CHARACTERIZATION ................................................................................... 97

8.1 DC PIN LOGIC LEVELS ................................................................................................................ 97

8.2 SUPPLY CURRENT AND OUTPUT VOLTAGE ................................................................................... 97

9 AC TI MING CHARACT ERISTICS ................................................................................................ 98

9.1 LINE INTERFACE CHARACTERISTICS ............................................................................................ 98

9.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS................................................................ 99

9.3 SERIAL PORT ............................................................................................................................111

9.4 SYSTEM TIMING ........................................................................................................................112

9.5 JTAG TIMING ............................................................................................................................114

10 PIN CONFIGU RATION................................................................................................................115

11 PACKAGE INFOR MAT ION .........................................................................................................116

12 THERMAL INFORMATION .........................................................................................................117

13 DATA SHEET REVISION HISTOR Y ...........................................................................................119

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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LIST OF FIGURES

Figure 3-1. Bloc k Di agr am ..................................................................................................................................... 8

Figure 3-2. Receive Logic Detail ............................................................................................................................ 9

Figure 3-3. Transmi t Logic Det ail ........................................................................................................................... 9

Figure 5-1. Serial Port Operation for Write Access ............................................................................................... 17

Figure 5-2. Seri al P or t Operat ion for Read A ccess with CLKE = 0 ........................................................................ 17

Figure 5-3. Seri al P or t Operat ion for Read A ccess with CLKE = 1 ........................................................................ 18

Figure 5-4. I nterr upt Handli ng Flow Diagram ........................................................................................................ 19

Figure 5-5. Pr escaler PLL and Cloc k Generator ................................................................................................... 20

Figure 5-6. T1 Tr ansmit P ulse Tem plates ............................................................................................................. 23

Figure 5-7. E1 Transmit Pulse Templates............................................................................................................. 24

Figure 5-8. LI U Front-End .................................................................................................................................... 25

Figure 5-9. Jitt er Attenuation ................................................................................................................................ 31

Figure 5-10. Analog Loopback ............................................................................................................................. 32

Figure 5-11. Digital Loopbac k .............................................................................................................................. 33

Figure 5-12. Remote Loopback ............................................................................................................................ 33

Figure 5-13. PRB S Sync hr oniz ation St ate Diagram .............................................................................................. 36

Figure 5-14. Repet itive Patt er n S y nc hr oniz ation Stat e Diagr am ............................................................................ 37

Figure 7-1. JTAG F unctional Bloc k Di agr am ......................................................................................................... 91

Figure 7-2. TAP Controller State Diagram ............................................................................................................ 94

Figure 9-1. I ntel Nonmux ed Read Cy c le ............................................................................................................. 100

Figure 9-2. Intel Mux R ead Cy cl e ....................................................................................................................... 101

Figure 9-3. I ntel Nonmux Write Cycl e ................................................................................................................. 103

Figure 9-4. Intel Mux Wr ite Cyc le ....................................................................................................................... 104

Figure 9-5. Motorola Nonmux Read Cycle .......................................................................................................... 106

Figure 9-6. Motorola Mux Read Cycle ................................................................................................................ 107

Figure 9-7. M otor ola Nonmux Write Cy cl e .......................................................................................................... 109

Figure 9-8. Motorola Mux Write Cycle ................................................................................................................ 110

Figure 9-9. Seri al B us Timi ng Write Operati on.................................................................................................... 111

Figure 9-10. Seri al B us Timi ng Read Operati on with CLKE = 0 .......................................................................... 111

Figure 9-11. Seri al B us Timi ng Read Operati on with CLKE = 1 .......................................................................... 111

Figure 9-12. T r ansmit ter Systems Timing ........................................................................................................... 112

Figure 9-13. Receiver System s Timi ng ............................................................................................................... 113

Figure 9-14. JTAG Timing .................................................................................................................................. 114

Figure 10-1. 256-Ball TE-CSBGA ....................................................................................................................... 115

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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LIST OF TABLES

Table 4-1. Pin Descri ptions .................................................................................................................................. 10

Table 5-1. Parallel Port Mode Selection and Pin Functions ................................................................................... 18

Table 5-2. Telec ommunicati ons Specification Compliance for DS 26324 Transmitters ........................................... 21

Table 5-3. Regi ster s Rel ated to Control of DS26324 Transmitter s ........................................................................ 21

Table 5-4. Template Selecti ons for Short -Haul M ode............................................................................................ 22

Table 5-6. LIU Front-End Values .......................................................................................................................... 26

Table 5-7. Loss Criter ia ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications .......................................... 28

Table 5-8. AIS Criteria ANSI T1. 231, ITU-T G.775, and ETS 300 233 S pecific ations ............................................ 29

Table 5-9. AIS Det ection and Reset Cr it eri a for DS26324 ..................................................................................... 29

Table 5-10. Regi ster s Rel ated to AIS Detection .................................................................................................... 29

Table 5-11. BPV, Code Vi olation, and Excessive Z er o Err or Repor ting ................................................................. 30

Table 5-12. Pseudorandom Pat tern Generation ................................................................................................... 35

Table 5-13. Repetitive Pattern Generat ion............................................................................................................ 35

Table 6-1. Prim ar y Regi ster S et ........................................................................................................................... 40

Table 6-2. Secondar y Register Set....................................................................................................................... 41

Table 6-3. Indiv idual LIU Regi ster S et .................................................................................................................. 42

Table 6-4. BERT Register Set .............................................................................................................................. 43

Table 6-5. Prim ar y Regi ster S et Bit Map .............................................................................................................. 44

Table 6-6. Secondar y Register Set Bit M ap .......................................................................................................... 45

Table 6-7. Indiv idual LIU Regi ster S et Bit Map ..................................................................................................... 46

Table 6-8. BERT Register Bit Map ....................................................................................................................... 47

Table 6-9. G.772 Monitoring Cont r ol ( LIU 1) ......................................................................................................... 54

Table 6-10. G.772 Monitoring Control (LIU 9) ....................................................................................................... 54

Table 6-11. TST Template Select Transm itt er Regi ster (LIUs 1–8) ....................................................................... 59

Table 6-12. TST Template Select Transm itt er Regi ster (LIUs 9–16) ..................................................................... 59

Table 6-13. Template Selection............................................................................................................................ 60

Table 6-14. Address Pointer Bank S elec tion ........................................................................................................ 63

Table 6-15. DS26324 MCLK S elec tions ............................................................................................................... 69

Table 6-16. Receiver Sensitivit y/M onitor M ode Gain Selection ............................................................................. 73

Table 6-17. Receiver Signal Lev el ........................................................................................................................ 75

Table 6-18. Bit Error Rate T r ansceiver Sel ect for Channels 1–8 ........................................................................... 79

Table 6-19. Bit Error Rate T r ansceiver Select for Channel s 9–16 ......................................................................... 79

Table 6-20. PLL Clock S elec t ............................................................................................................................... 82

Table 6-21. Cl ock A Sel ect ................................................................................................................................... 82

Table 7-1. Instr uc tion Codes for IEE E 1149.1 Architec ture ................................................................................... 95

Table 7-2. ID Code Str uctur e ............................................................................................................................... 96

Table 7-3. Device ID Codes ................................................................................................................................. 96

Table 8-1. Recomm ended DC Operati ng Conditions ............................................................................................ 97

Table 8-2. Pin Capacitance .................................................................................................................................. 97

Table 8-3. DC Characteristics .............................................................................................................................. 97

Table 9-1. Transmitter Characteristic s .................................................................................................................. 98

Table 9-2. Receiver Characteristics...................................................................................................................... 98

Table 9-3. Intel Read Mode Char ac teristics .......................................................................................................... 99

Table 9-4. Intel Write Cy cl e Char ac teristics ........................................................................................................ 102

Table 9-5. Mot or ola Read Cy cl e Char ac teristics ................................................................................................. 105

Table 9-6. Mot or ola Write Cycl e Charact eri stics ................................................................................................. 108

Table 9-7. Serial P or t Timing Characteristic s ...................................................................................................... 111

Table 9-8. Transmitter System Timing ................................................................................................................ 112

Table 9-9. Receiver System Timing.................................................................................................................... 113

Table 9-10. JTAG Timi ng Char ac teristics ........................................................................................................... 114

Table 12-1. Thermal Characteristic s ................................................................................................................... 117

Table 12-2. Pack age P ower Di ssipat ion (for Therm al Considerat ions) ................................................................ 117

Table 12-3. Per-Channel Power-Down Savings (f or Therm al Consi der ations)..................................................... 118

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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1 STANDARDS COMPLIANCE

1.1 Telecom Specifications compliance

The DS26324 LIU meets all the relevant latest Telecommunications Specifications. The following provides the T1

and E1 Specifications and relevant sections that are applicable to t he DS 26324.

• T1-Related Telecommunications Specifications

• ANSI T1. 102: Digit al Hier ar c hy El ectr ic al Interface

• ANSI T1. 231: Digit al Hier ar c hy - Layer 1 in S ervice Performance Moni toring

• ANSI T1.403: Network and Custom er Installation Interface- DS1 Electrical Interface

• G.736: Charac teristic s of a synchr onous di git al m ultiplex equipment operating at 2048kbps

• G.823: The cont r ol of jit ter and wander within digital network s whi c h ar e based on the 2048k bps hi er archy

• Pub 62411: High Capacity Terrestr ial Digital Service

• ITU-T G. 772: Protected monitoring point s provided on digital tr ansmission system s

• E1-Related Telecommunications Specifications

• ITU-T G. 703: Physical/ El ec tric al Char ac teristics of G.703 Hierarc hical Digital Interfaces

• ITU-T G. 736: Characteristic s of S y nc hr onous Di gital Multi plex Equipment operati ng at 2048kbps

• ITU-T G. 742: Second Order Digital Multiplex Equipm ent O per ating at 8448kbps

• ITU-T G.772: Protected monitoring points provided on digital transmission systems

• ITU-T G. 775: Loss of signal ( LOS) and alarm indication signal ( AIS ) defec t detecti on and cl ear anc e c ri teria

• ETS 300 166: Phy si c al and electri c al c har ac teristics of hier ar c hic al digital int erfaces for equi pm ent using

the 2048kbps-ba se d plesiosynchr onous or synchronous digit al hier ar c hies

• ETS 300 233: I ntegrated Services Digital Net work (ISDN)

• G.736: Charac teristic s of a synchr onous di git al m ultiplex equipment operating at 2048kbps

• G.823: The cont r ol of jit ter and wander within digital network s whi c h ar e based on the 2048k bps hi er ar c hy

• Pub 62411: High Capacity Terrestr ial Digital Service

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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2 DETAILED DESCRIPTION

The DS26324 is a single-chip, 16-channel, short-haul line interface unit for T1 (1.544Mbps) and E1 (2.048Mbps)

applications. Sixteen independent receivers and transmitters are provided in a single TE-CSBGA package. The

LIUs can be i ndividually selected for T1, J1, or E 1 operation. The LI U requi r es a single master ref er enc e cl oc k. This

cl ock can be either 1. 544MHz or 2.048M Hz or multi ples t hereof , and ei ther frequenc y can be int ernall y adapted f or

T1, J1, or E1 mode. Internal impedance matching provided for both transmit and receive paths reduces external

component count. The transmit waveforms are compliant to G.703 and T1.102 specification. The DS26324

provi des sof tware-sel ectabl e i nter nal transmi t t ermination f or 100Ω T1 twisted pai r, 110Ω J1 t wi sted pair , 120Ω E1

twisted pair, and 75Ω E1 coaxial applications. The transmitters have fast high-impedance capability and can be

individually powered down.

The receivers can function with up to an 18dB receive signal attenuation. A monitor gain setting also can be

enabled to provide 14dB and 20dB. The DS26324 can be conf igured as a 14-channel LIU with Channel 1 and 9

used for nonintrusiv e monitor ing in accordanc e with G.772. The r ec eiv er s and tr ansmitter s can be progr am med into

single or dual-rail mode. AMI or HDB3/B8ZS encoding and decoding is selectable in single-rail mode. A 128-bit

crystal-less on-board jitter attenuator for each LIU can be placed in receive or transmit directions. The jitter

attenuator meets the ETS CTR12/13 ITU-T G. 736, G.742, G.823, and AT& T Pub 62411 specif ic ations.

The DS26324 detects and generates AIS in accordance with T1.231, G.775, and ETS 300 233. Loss of signal is

detect ed in accordance with T1. 231, G .775, and ETS 300 233. The DS26324 can perf orm digit al , analog, rem ote,

and dual loopbac k s on i ndiv idual LI Us. JTAG boundar y scan is provided for the digital pins.

The DS26324 can be configured using 8-bit multiplexed or nonmultiplexed Intel or Motorola ports. A 4-pin serial

port sel ec tion is also available for confi gur ation and monitoring of the devic e.

The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled

into the RTIP and RRING pins of the DS26324. The user can terminate the receive line using only internal

termination that requires no external resistors. Or, the user has the option to use partially internal impedance

m atching usi ng a c om mon 120Ω external r esi stor for E1, T1, and J1, and matching t he line impedanc e int er nally to

obtain 75Ω, 100Ω, 110Ω, or 120Ω termination values. Note that fully internal impedance match requires a 1:1

transf orm er on the receiv e l i ne. Parti al ly inter nal im pedance m atchi ng supports eit her a 1:1 or a 1:2 transf ormer on

the rec eiv e li ne. If a 1:2 t ransf ormer is used, the ex ternal term inati on resistor shoul d be 30Ω. The DS26324 driv es

the E1 or T1 line f r om the TTIP and TRING pins by a 1:2 coupling transform er.

The device recovers clock and data from the analog signal and passes it through a selectable jitter attenuator

output ting the received line cl ock at RCLK and dat a at RPOS and RNEG.

The DS26324 receivers can recover data and clock for up to 18dB of attenuation of the transmitted signals in T1

mode and 43dB for E1 mode. Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8.

Receiver 9 can monitor the perform anc e of rec eiv er s 10 to 16 or transmitter s 10 to 16.

The DS26324 contains 16 identical transmitters. Digital transmit data is input at TPOS/TNEG with reference to

TCLK. The data at these pins can be single-rail or dual-rail. This data is processed by waveshaping circuitry and

the line driv er to out put at TTIP and TRI NG in acc or dance with A NSI T1. 102 for T1/J 1 or G.703 for E1 mask.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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3 BLOCK DIAGRAMS

Figure 3-1. Block Diagram

Line Drivers

Optional

Termination

Filter

Peak Detector

Clock/Data

Recovery

Analog Loopback

CSU Filters

Wave Shaping

Remote Loopback (Dual Mode)

Local Loopback

Jitter Attenuator

Remote Loopback

Receive Logic

Transmit Logic

VCO/PLL

MUX

Unframed All

Ones Insertion

RRING

RTIP

TRING

TTIP

RPOS/RDAT

RNEG/CV

RCLK

TPOS/TDAT

TNEG

TCLK

Master Clock

Adapter

JTAG PORT

Control

and

Interrupt

Port Interface

CLKE

RDB/RWB

RDY/ACKB/SDO

MOTEL

ASB/ALE/SCLK

A5/BSWB

A0 to A4

D0 to D7/

AD0 to AD7

CSB

INTB

TRSTB

TMS

TCLK

TDI

TDO

MCLK

T1CLK E1CLK

16 16

TYPI CA L OF ALL 16 CHANNELS

OE

MODESEL

WRB/DSB/SDI

85

Reset

RSTB

LOS

Reset

T1CLK E1CLK

DS26324

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Figure 3-2. Receive Logic Det ail

B8ZS/HDB3/AMI

Decoder (G.703, T1. 102)

BPVs, Code Violatiions

(T1.231, O.161)

AIS

Detector

G.775, ETS I 300233,

T1.231

Excessive

Zero

Detect

T1.231

MUX

All Ones

Insert

(AIS)

NRZ Data

BPV/CV/EXZ

RPOS

RNEG/CV

RCLK

LOS

EN

SRMS

IAISEL

AISEL

MCLK

EZDE

LASCS

POS

NEG

RCLK

CVDEB

ENCODE ENCV

LCS

CODE

ENCODE

Figure 3-3. Transmit Logic Det a il

MUX

TPOS/

TDATA

TNEG/

BPV

B8ZS/HDB3/AMI

Coder (G.703,

T1.102)

TCLK

BPV

Insert

LCS

CODE

ENCODE

BEIR

To Remot e

Loopback

SRMS

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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4 PIN DESCRIPTION

Table 4-1. Pin Desc ript ions

NAME PIN TYPE FUNCTION

ANALOG TRANSMIT AND RECEIV E

TTIP1

E1

Analog

output

Transmit Bipolar Tip for Channels 1–16. These pins are differential

line driver tip out puts. These pins can be high im pedanc e if pin OE is

low. W hen “ 1” is set i n the Output Enable Register OE bit , t he

associated T TI P n pin will be enabled when the OE pin is high. The

differential out puts of TT IPn and TRINGn can pr ov ide internal

m atched im pedanc e for E 1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

If the T CLK i nput f or a given LIU is held low for 64 MCLKs, that LIU’s

transmit ter is powered down and the TT IP/T RING outputs are hi gh

impedance.

TTIP2

F1

TTIP3

K1

TTIP4

L1

TTIP5

T5

TTIP6

T6

TTIP7

T10

TTIP8

T11

TTIP9

M16

TTIP10

L16

TTIP11

G16

TTIP12

F16

TTIP13

A12

TTIP14

A11

TTIP15

A7

TTIP16

A6

TRING1

E2

Analog

output

Transmit Bipolar Ring for Channels 1–16. These pi ns are

differential line driver ring out puts. These pins can be high impedance

if pin OE is l ow. W hen “ 1” is set i n the Output Enable Register OE bit,

the associat ed TRI NGn pin will be enabl ed when the OE pin is high.

The dif ferential outputs of TTIPn and TRI NGn can pr ov ide internal

m atched im pedanc e for E 1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

If the T CLK i nput f or a given LIU is held low for 64 MCLKs, that LIU’s

transmit ter is powered down and the TT IP/T RING outputs are high

impedance.

TRING2

F2

TRING3

K2

TRING4

L2

TRING5

R5

TRING6

R6

TRING7

R10

TRING8

R11

TRING9

M15

TRING10

L15

TRING11

G15

TRING12

F15

TRING13

B12

TRING14

B11

TRING15

B7

TRING16

B6

RTIP1

A1

Analog

input

Receive Bi polar Ti p for Channels 1–16. Receive analog input for

differential rec eiv er . Dat a and cl oc k are rec ov er ed and output at

RPOS /RNEG and RCLK pins, r espect ively. The dif ferential input s of

RTI P n and RRING n c an provide int er nal im pedanc e matc hing with

ex ternal r esi stanc e for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

RTIP2

C1

RTIP3

H1

RTIP4

N1

RTIP5

T1

RTIP6

T3

RTIP7

T8

RTIP8

T13

RTIP9

T16

RTIP10

P16

RTIP11

J16

RTIP12

D16

RTIP13

A16

RTIP14

A14

RTIP15

A9

RTIP16

A4

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

11 of 120

NAME PIN TYPE FUNCTION

RESREF R9 Analog

input

Resistor Reference. If fully in ternal receive impedance match is

select ed, a 16kΩ ±1% r esi stor to GND is needed. If not used, tie pin

low.

RRING1

A2

Analog

input

Receive Bi polar Rin g for Channels 1–16. Receive analog input for

differ ential receiv er . Dat a and cl oc k are rec ov er ed and output at

RPOS /RNEG and RCLK pins, r espect ively. The dif ferential input s of

RTI P n and RRING n c an provide int er nal im pedanc e matc hing wit h

ex ternal r esi stanc e for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

RRING2

C2

RRING3

H2

RRING4

N2

RRING5

R1

RRING6

R3

RRING7

R8

RRING8

R13

RRING9

T15

RRING10

P15

RRING11

J15

RRING12

D15

RRING13

B16

RRING14

B14

RRING15

B9

RRING16

B4

DIGI TA L Tx /R x

TPOS1/TDATA1

F6

I

Tra ns m it P ositive Data Input for Channels 1–6. When DS 26324 is

configured in dual-rail m ode, t he data input to TPOSn is output as a

positive pulse on the line (tip and ring).

Transmit Dat a Input for Channels 1–16. When t he dev ic e is

configured in single-rail mode NRZ data is input to TDATAn. The data

is sampled on the f alling edge of TCLK n and encoded HDB3/ B 8ZS or

AMI before being output to the li ne.

TPOS2/TDATA2

G7

TPOS3/TDATA3

J6

TPOS4/TDATA4

K6

TPOS5/TDATA5

L9

TPOS6/TDATA6

N5

TPOS7/TDATA7

P12

TPOS8/TDATA8

M11

TPOS9/TDATA9

L11

TPOS10/TDATA10

J11

TPOS11/TDATA11

G11

TPOS12/TDATA12

C14

TPOS13/TDATA13

F9

TPOS14/TDATA14

E7

TPOS15/TDATA15

N12

TPOS16/TDATA16

D5

TNEG1

C3

I

Transmit Negative Data for Channel s 1–16. When DS26324 i s

configured in dual-rail mode. The data input to TNEGn is output as a

negative mark on the line. TPOS and TNEG in dual-ra il mode result in

positive and negative pulses sent on t he line:

TNEG2

J14

TNEG3

J5

TNEG4

G10

TNEG5

M6

TNEG6

P6

TNEG7

P7

TPOSn

TNEGn

OUTPUT P ULS E

TNEG8

K9

0

Space

TNEG9

L12

0

1

Negative mark

TNEG10

J12

1

0

Positive mark

TNEG11

H11

1

Space

TNEG12

E13

TNEG13

G8

TNEG14

F7

TNEG15

C6

TNEG16

C5

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

12 of 120

NAME PIN TYPE FUNCTION

TCLK1

F5

I

Transmit Clo ck for Channels 1–16. The transmit clock has to be

1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock used

to sam ple the dat a TPOS/T NEG or TDAT on the f alling edge. T he

ex pec ted TCLK can be inv erted.

If TCLKn is ‘high’ for 16 or more MCLKs, then trans mit all ones

(TAOs) is sent to the line side of t he c or r espondi ng transmit c hannel.

When TCLKn starts clocking again, normal oper ation will begi n again

for the corresponding transm it channel.

If TCLKn is ‘l ow’ for 64 or more MCLKs, t hen the cor r espondi ng

transmit c hannel on the line side will power-down and be put int o high

im pedanc e. When TCLKn star ts clocking again the corresponding

transmit c hannel will power-up and come out of high impedance.

TCLK2

G4

TCLK3

G9

TCLK4

H6

TCLK5

M7

TCLK6

L8

TCLK7

L10

TCLK8

P9

TCLK9

K11

TCLK10

K12

TCLK11

F14

TCLK12

E12

TCLK13

C11

TCLK14

D12

TCLK15

N7

TCLK16

D11

RPOS1/RDATA1

F4

O,

tri-state

Receive Posi t ive Data Output fo r Channels 1–16. In dual-rail mode

the NRZ data output indic ates a positive pulse on RTIP/RRING. Upon

detecting an LOS, AIS can be inserted if the AISEL bit in t he GC

(0Fh) r egister is set; otherwise, t he pins wil l be ac tive. AIS insert ion

can al so be cont r olled on an indiv idual LI U basis by the IAISEL (05h)

regi ster . If a giv en r ec eiv er i s in power-down mode, the as sociated

RPOS pin is high impedance.

Receive Data Ou tput for Channels 1–16. I n singl e-rail mode, NRZ

data is sent out on t his pi n. If a giv en r ec eiv er is in power-down mode,

the associat ed RP OS pin is hi gh im pedanc e.

Note: During an LO S condit ion, t he RPOS/RDA TA output s remain

active.

RPOS2/RDATA2

F3

RPOS3/RDATA3

L3

RPOS4/RDATA4

L4

RPOS5/RDATA5

K8

RPOS6/RDATA6

M9

RPOS7/RDATA7

P8

RPOS8/RDATA8

M12

RPOS9/RDATA9

M14

RPOS10/RDATA10

K13

RPOS11/RDATA11

G12

RPOS12/RDATA12

E14

RPOS13/RDATA13

C12

RPOS14/RDATA14

C10

RPOS15/RDATA15

C8

RPOS16/RDATA16

E5

RNEG1/CV1

E3

O,

tri-state

Receive Neg at ive Data Ou tput for Channel s 1–16. In dual-rail

m ode the NRZ data output indic ates a negative pulse on

RTI P/RRING. Upon detecti ng a LOS, AIS can be i nserted if A ISE L bit

in the GC register is set; otherwise, t he pins will be active. AIS

insert ion c an also be cont rolled on an indiv idual LI U basis by IAISEL

regi ster . If a giv en r ec eiv er i s in power-down mode, the as sociated

RNEG pin is high impedance.

Code Violation for Channels 1–16. In si ngle-rail mode, bipolar

v iolation, code violati on, and exc essive zeros are reported on CVn. If

HDB3 or B8ZS i s not sel ec ted, this pi n indicates only BPVs. If a given

receiver is i n power-down mode, the associat ed CV pin is high

impedance.

RNEG2/CV2

G5

RNEG3/CV3

K4

RNEG4/CV4

M3

RNEG5/CV5

L7

RNEG6/CV6

M10

RNEG7/CV7

P11

RNEG8/CV8

K10

RNEG9/CV9

M13

RNEG10/CV10

L14

RNEG11/CV11

F13

RNEG12/CV12

F11

RNEG13/CV13

E10

RNEG14/CV14

C9

RNEG15/CV15

C7

RNEG16/CV16

J3

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

13 of 120

NAME PIN TYPE FUNCTION

RCLK1

D3

O,

tri-state

Receive Cl ock for Ch ann els 1–16. The receive data (RPOS/RNEG)

is clock ed out on the rising edge of RCLK. If a given r eceiver is i n

power-do wn m ode the RCLK is hi gh im pedanc e. Upon an LO S being

detected, the RCLK is swit c hed from the r ec ov er ed cl ock t o MCLK.

RCLK can be inverted by the RCLKI register.

RCLK2

G6

RCLK3

K3

RCLK4

K5

RCLK5

P5

RCLK6

M8

RCLK7

P10

RCLK8

P13

RCLK9

L13

RCLK10

K14

RCLK11

G13

RCLK12

F12

RCLK13

E8

RCLK14

E9

RCLK15

F8

RCLK16

E6

MCLK H12 I

Master Cl ock. This i s an i ndependent free-runni ng cl ock t hat can be

a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz ±50ppm

for T1 mode. The clock sel ection is availabl e by MC bits MPS0,

MPS1, FREQS, and PLLE. A m ultiple of 2.048MHz can be i nternal

adapted t o 1.544MHz and a m ultiple of 1.544MHz can be inter nal

adapted t o 2.048MHz .

LOS1

D2

O

Loss-of-Signal Outp ut. T his output goes high when there is no

transi tion on the received si gnal over a spec ifi ed interval . The output

will go low when ther e is sufficient ones densit y in the received signal.

The LO S criteria for assertion and desertion cr iteria are described in

Section 5.5.6. The LOS outputs can be configured to com ply with

T1.2 3 1 , ITU -T G. 775, or ETS 300 233.

T1/E1 Clock (TE CLK) ( Ball E 11 only) . T his output becomes a T1 or

E1 program mable cl oc k output when enabled by r egister MC. Fo r T1

or E1 f r equenc y sel ec tion, see the CCR register.

Clo ck A (CLKA) (Bal l F10 only). This output bec om es a

programmable cl oc k output when enabled by register MC. Fo r

frequenc y options, see CCR register.

LOS2

G2

LOS3

J2

LOS4

M2

LOS5

R2

LOS6

T2

LOS7

R4

LOS8

R7

LOS9

R14

LOS10

N15

LOS11

K15

LOS12

H15

LOS13

B10

LOS14

B8

LOS15/TECLK

E11

LOS16/CLKA

F10

HOST SELECTION

MODESEL A3 I

Mode Selection. Thi s pin is used to sel ec t t he c ontrol mode of t he

DS26324:

Low → Serial Host Mode

High → Parallel Host Mode

MOTEL B3 I

Mot or ola Inte l S e le c t. When this pin is low, Motorola mode is

select ed. W hen this pin is high Int el mode i s selected.

CSB P14 I

Chi p Select Bar. T his signal must be low during all ac cesses to the

registers.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

14 of 120

NAME PIN TYPE FUNCTION

SCLK/ALE/ASB N14 I

Shift Clock. In the serial host m ode, t his pi n is the serial cloc k. Data

on SDI is clock ed on the risi ng edge of SCLK. The data is clock ed on

SDO on the risi ng edge of SCLK if CLK E is high. If CLKE is l ow the

data on SDO is clocked on the f alling edge of SCLK.

Address Lat ch Enable. In parallel Intel multiplexed mode, the

address lines are latc hed on the f alling edge of ALE.

Address Strob e Bar. In paralle l Motorola multiplexed mode, the

address is sampled on the falling edge of A SB.

Note: Ti e ALE/ ASB pin high if using nonmux ed m ode.

RDB/RWB H14 I Read Bar. In Intel host m ode, t his pi n m ust be low for read operat ion.

Read Writ e Bar. In Motorola mode, t his pi n is l ow for wri te operation

and high for read operation.

SDI/WRB/DSB G14 I

Serial Data Input. In the serial host mode, t his pi n is the serial input

SDI; it is sampl ed on the risi ng edge of SCLK.

Write Bar. In Intel host m ode, this pin is active low during writ e

operation. The data or addr ess (m ultiplexed m ode) is sampled on the

ri si ng edge of WRB.

Data Strob e Bar. I n the parallel Motorola mode, this pin is active low.

Duri ng a wri te operation the data or addr ess is sampled on the rising

edge of DSB. Duri ng a read operat ion the data or address i s driven

on the risi ng edge of DSB. In t he nonm ultipl ex ed Motorol a m ode the

address bus (A[5: 0]) is latched on the falli ng edge of DSB.

SD0/RDYB/ACKB C13 O

Serial Data Out. In serial host mode, the SDO data is output on this

pin. If a serial write is in progr ess thi s pi n is hi gh im pedance. Dur ing a

read SDO is hi gh im pedanc e when the SDI is in command/addres s

m ode. If CLK E i s low SDO is output on the risi ng edge of SCLK , if

CLKE is hi gh on the falling edge.

Ready Bar O utpu t . A high on this pin report s to the host t hat the

cycle is not complet e and wai t states must be inserted. A low means

the cy cl e is complete.

Acknowledge Bar. In Motorola parallel mode, a low on thi s pin

indic ates that the read data is available for the Host or that the writt en

data cy cl e is complete.

INTB D7 O,

open

drain

In t errup t Bar ( Active Lo w). This signal is tri -state when RSTB pin is

low. T his inter r upt signal is driven low when an event is detect ed on

any of the enabled interrupt sources i n any of t he r egister bank s.

When there are no activ e and enabled inter r upt sources, t he pin can

be programmed to eit her drive high or as open drain. The reset

default is open drain when there are no active enabled interr upt

sources. A ll interrupt sources are di sabl ed when RS TB = 0 and they

m ust be pr ogr ammed to be enabl ed.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

15 of 120

NAME PIN TYPE FUNCTION

D7/AD7

N3

I/O,

tri-state

Data Bus 7–0. In nonmult iplexed host m ode, these pins are the

bidir ectional dat a bus.

Address/Dat a Bus 7–0. In multipl ex ed host m ode, t hese pins are the

bidir ectional address/data bus. Note: AD7 and AD6 do not car r y

address information.

In seri al host m ode, t hese pi ns should be grounded.

D6/AD6

P3

D5/AD5

M4

D4/AD4

L5

D3/AD3

K7

D2/AD2

P4

D1/AD1

M5

D0/AD0

L6

A5/BSWP E4 I

Address 5. In the host nonmultiplexed mode, this is th e most

signific ant bit of the address bus.

Bit Swap. In serial host m ode, t his bi t defi nes the serial dat a posi tion

to be MS B fir st when low and LSB fi r st when high.

In multiplexed host mode, t his pi n shoul d be gr ounded.

A4

C4

I

Address Bus 4–0. These fiv e pins are addres s pi ns i n the parallel

host m ode.

In seri al host m ode and m ultiplexed host mode, these pins should be

grounded.

A3

H5

A2

G3

A1

H3

A0

N10

OE R12 I

Output Enable. If this pi n is pul led low all the tr ansmitters outputs

(TTI P and TRI NG) ar e high im pedanc e. If pulled high all the

transmit ters are enabl ed when the associat ed output enable OE bit is

set. If TST.RHPMC is set, the OE pin is granted control of the

receiver internal termination. When OE is low, receiver internal

termi nation will be high impedanc e. When OE is hi gh, receiver

termi nation will be enabled. The rec eiv er can still m onitor inc omi ng

signal s even when terminati on is i n high im pedanc e.

CLKE/MUX T14 I

Clock Edge. If CLK E is high, S DO is cl oc k ed out on fall ing edge of

SCLK and if low SDO is on rising edge of SCLK .

Multiplexed/Nonmultiplexed Select Pin. When in paral lel port

m ode, t his pi n is used to select multipl ex ed addr ess and dat a

operation or separat e addr es s and data. When m ux i s a high

m ultiplexed addr es s and data is used and when mux is l ow

nonmultiplexed is used.

JTAG

TRSTB E15

I,

pullup

JTAG Test Port Reset. T his pi n if low will reset t he JTAG por t. If not

used it c an be left unconnected.

TMS B13 I,

pullup

JTAG Test Mode Select. T his pi n is clock ed on the rising edge of

TCK and is used to cont r ol the JTAG selec tion between scan and

Test Machine control.

TCK D14 I

JTAG Test Clock. The data TDI and TMS are clock ed on rising edge

of T CK and TDO is cl ocked out on the f alling edge of TCK.

TDO A15

O,

high-Z

JTAG Test Data Out. Thi s is the serial output of t he JTAG por t. The

data is clocked out on the falling edge of TCK .

TDI B15 I,

pullup

Test Data Input. This pin input is the seri al data of the JTAG Test.

The dat a on TDI is clock ed on the rising edge of T CK. This pin can be

left unconnected.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

16 of 120

NAME PIN TYPE FUNCTION

RESET

RSTB B5 I,

pullup

Reset Bar. This is the asynchr onous reset i nput bar. It is i nternally

pulled high. A 1µs low on this pi n will reset the DS26324 r egister s to

default va lue.

POWER SUPPLIES

DVDD

H8,

J9

I 3.3V Digital Power Supply

DVSS

H9,

J8

I Digital Gro un d

VDDT1

D1

I,

high-Z 3.3V P ow er Supp ly for the Transmitter. All VDDT pins must be

connect ed to VDDT, whic h has to be 3.3V.

VDDT2

G1

VDDT3

J1

VDDT4

M1

VDDT5

T4

VDDT6

T7

VDDT7

T9

VDDT8

T12

VDDT9

N16

VDDT10

K16

VDDT11

H16

VDDT12

E16

VDDT13

A13

VDDT14

A10

VDDT15

A8

VDDT16

A5

GNDT1

D4

I Ana log Gr ound for Tr a ns m it te r s

GNDT2

H4

GNDT3

J4

GNDT4

N4

GNDT5

N6

GNDT6

N8

GNDT7

N9

GNDT8

N11

GNDT9

N13

GNDT10

J13

GNDT11

H13

GNDT12

D13

GNDT13

D10

GNDT14

D9

GNDT15

D8

GNDT16

D6

AVDD

B1,

C16,

P1,

R16,

H7,

J10

I 3.3V Analog Core Power Suppl y. Decouple each pin separatel y .

AVSS

B2,

C15,

P2,

R15,

H10,

J7

I Analog Core Ground

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

17 of 120

5 FUNCTIONAL DESCRIPTION

5.1 Port Operation

5.1.1 Serial Port Operation

Setting MODESEL = ‘low’ enables the serial bus interface on the DS26324. Port read/write timing is unrelated to

the system tr ansmit and receiv e timing, all owi ng asynchronous read s or wri tes by t he host. See S ecti on 9.3 f or the

AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is high and MSB first when

BSWP is low. Figure 5-1 to Figure 5-3 show oper ati on with LSB first.

Thi s port is compati ble with t he SPI interfac e defi ned for Mot orol a Processor s. An ex ample of this i s the MMC2107

from M otorola.

Reading or writi ng t o the i nternal registers requi res wri ti ng one address/com m and byte pri or to transf erri ng register

data. The first bit wri tten (LSB) of the address/comm and byte specifies whether the access is a read (1) or a wri te

(0). The next 6 bits identify the register addr es s (A1 to A6) (A7 is ignor ed) .

All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising

edge of SCLK and when CLKE is hi gh, data is output on the falling edge of SCLK. Data is held until the next fal ling

or rising edge. All dat a transfers are t erminated if CSB input transitions high. Port control logic is di sabl ed and S DO

is tri-stated when CSB i s hi gh. SDI is always sam pled on the rising edge of SCLK.

Figure 5-1. Serial Port Operation for Write Access

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

CSB

0

A1

A2

A3

A4

A5

A

6

x

(adrs

msb)

SDI

SDO

D1

D2

D3

D4

D5

D7

(lsb)

(msb)

DO

D6

(lsb)

WRITE ACCESS ENABLED

Figure 5-2. Serial Port Operation for Read Access with CLKE = 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0A1 A2 A3 A4 A5

D1 D2 D3 D4 D5 D6

SCLK

SDI

SDO

CSB

(lsb) (msb)

D0

(lsb)

D7

(msb)

A6 X

Read

Access

Enabled

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

18 of 120

Figure 5-3. Se rial Port Operation for Read Access with CLKE = 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0A1 A2 A3 A4 A5

D1 D2 D3 D4 D5 D6

SCLK

SDI

SDO

CSB

(lsb)

(msb)

D0

(lsb)

D7

(msb)

A6 X

5.1.2 Parallel Port Operation

When using the parallel interface on the DS26324 the user has the option for either multiplexed bus operation or

nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26324 can

operate wit h either Intel or Mot orol a bus-timing configurati ons select ed by MOTEL pin. Thi s pi n bei ng high selects

the I ntel mode. The par allel por t is only operati onal if MODE SEL pin i s pulled hi gh. The foll owing Table lists all the

pins and their functions in t he par allel por t mode. See the timing diagram s i n Secti on 9 for more details.

Table 5-1. Parallel Port Mode Selection and P in Functions

MODESEL, MOTEL,

MUX

PARALLEL HOST

INTERFACE

ADDRESS, DAT A, AND CONTROL

100

Nonmultiplexed Motorola

CSB, ACKB, DSB, RWB, ASB, A[5:0], D[7:0], INTB

110

Nonmultiplexed Intel

CSB, RDYB, WRB, RDB, ALE, A[5:0], D[7:0], INTB

101

Multiplexed Motorola

CSB, ACKB, DSB, RWB, ASB, AD[7:0], INTB

111

Mul tiplexed Intel

CSB, RDY B, WRB, RDB, ALE, A D[7: 0], INTB

5.1.3 Interrupt Handling

There ar e four sets of ev ents that can potentially trigger an Int er r upt. The int er r upt functi ons as f ollows:

• When status changes on an interruptible event, INTB pin will go low if the event is enabled through the

corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10kΩ resister for

wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when

not active by setting register GISC.INTM.

• W hen an Int errupt occurs the Ho st Pr ocessor has to re ad t he Int errupt Stat us register to det erm i ne the sourc e

of t he Inter r upt. The read will also clear the Interr upt Status register and this will clear the out put INTB pin. The

Int errupt Status regi ster can al so be confi gured as cl ear on writ e as per register GISC.CWE. When set t o c lear

on write, and interrupt status register bit (and t he inter rupt i t generates) wil l only be cl eared on writ ing a ‘1’ t o

it’s bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a

regi ster without cl ear ing them on all bit s.

• Subsequently the host processor can read the corresponding Status Register to check the real-time status of

the event.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Figure 5-4. Interrupt Handling Flow Diagram

Interrupt Al l owed

Interrupt Condit on

Exist?

Read Interrupt St atus

Register

Read Corresponding Stat us

Register (Opti onal )

Service the I nt errupt

No

Yes

5.2 Power-Up and Reset

Internal Power_On_Res et ci rc uitry generates a reset d uri ng po wer-up. Al l r egister s are reset t o the def aul t v alues.

Writing t o the Sof tware Reset Register gener ate s at least 1µs reset cyc le, which has the same effect as the power-

up reset.

The DS26324 c an be r eset by a low going pulse on the RSTB pi n (see Table 4-1). A reset can al so be perf ormed in

software by writ ing any val ue to the SWR register.

5.3 Master Clock

The DS26324 requir es 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiv er uses t he MCLK

as a ref erence f or clock recover y, jitt er attenuat ion and generat i ng RCLK duri ng LOS. T he AIS tTr ansmission uses

MCLK f or transmit all ones condi tion. S ee r egister MC to set de si r ed inc omi ng f r equenc y . When the PLLE bit is set ,

the master cl oc k adapter will generate bot h 2.048MHz (E1) and 1.544MHz ( T1) cloc k s. If the PLLE bit i s clear, bot h

internal r eference cl oc k s will trac k MCLK.

MCLK or RCLK can also be used to output CLKA on the LOS16 pin. Register CCR is used to select the clock

generated for CLKA and t he TE CLK. A ny RCLK can also be select ed as an i nput t o the cl ock generator usin g t his

same register . For a detailed description of selecti ons available see Figure 5-5.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Figure 5-5. Prescaler PLL and Clock Generator

Pre

Scaler

PLL

CLK

GEN

E1CLK

T1CLK

FREQSMPS1..0

PLLE

RLCK9..16

PCLKS2..0

PCLKI1..0

RLCK1..8

PLLE CLKA3..0

CLKA LOS16

RLOS16

CLKAE

LOS15

RLOS15

TECLKE

TECLK

TECLKS

MCLK

5.4 Transmitter

NRZ data arrives on TPOS and TNEG on the transmit system side. The TPOS and TNEG data is sampl ed on the

falling edge of TCLK.

The data is encoded with HDB3 or B8ZS or AMI encoding when single-rail mode is selected (only TPOS as the

data sour ce). W hen i n singl e-rail mode only, BPV errors can be inserted for test purposes by register BEIR. Pre-

encoded data is expect ed when dual-rail mode is select ed. T he enc oded data pa s se s thr ough a jit ter att enuator if it

is enabled for the t ransmi t path. A digital sequencer and DAC are used to generate transmi t wav ef orms compli ant

with T 1.102 and G.703 pulse masks.

The line driv er support s i nternal impedanc e m atching for 75Ω, 100Ω, 110Ω, and 120Ω modes.

The DS26324 drivers have short and open circuit driver fail monitor detection. There is an OE pin that can high

impedance the transmitter outputs f or protection switching when low. The individual transmitters are by default in

high impedance. The OE register is used to enable the transmitters individually when the OE pin is high. The

DS26324 has to have the transmitter’s enabled by setting the register and then pulling the OE pin high. The

regi ster s that control t he transmitter oper ation are shown i n Table 5-2.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters

TRANSMITTER FUNCTION T E LECOMMUNICATIONS COMPLIANCE

AMI Coding, B8ZS Substi tution, DS1 El ec tric al Interface

ANSI T1.102

T1 T elec om Pul se Mask complianc e

ANSI T1.403

T1 T elec om Pul se Mask complianc e

ANSI T1.102

Transmit Electrical Characteristics for E1 Transmiss ion

and Return Los s Compliance

ITU-T G.703

Table 5-3. Registers Related to Control of DS26324 Transmitters

REGISTER

NAME

FUNCTION

Transmit All Ones Enable

TAOE

Transmit all ones enabl e.

Driver Fault M onitor Status

DFMS

Driver fault status.

Driver Fault M onitor Inter r upt Enable

DFMIE

Driver fault status interrupt mask.

Driver Fault M onitor Inter r upt Stat us

DFMIS

Driver fault status interrupt mask.

Autom atic Transmit All Ones Select

ATAOS

Transmit all ones enabl ed automati c ally on LOS.

Global Confi gur ation GC

Global control of jitter att enuator, line coding and short

circuit protec tion.

Template Select Transmitter TST

The transmitter that the Temp late Select Transmitter

Register applies to.

Temp late Sele ct TS

The T S 2 to TS0 bit s for selection of the t em plates for

transmit ter and TIMPOFF and TIMPRI M bits to c ontrol

transmit impedance match.

Output Enable Configuration OE

These regi ster bits can be used to enable the t r ansmit ter

outputs.

Master Clock Selection MC

Sel ec ts the MCLK frequency used for transmit and

receive.

Single-Rail Mode Select SRMS

This regi ster c an be used to select between single-rail

and dual-rail mode.

Line Code S election LCS The individual transceiver line codes can be selec ted to

ov er wri te the global setting.

Transmit Power-Down Enable

TPDE

Individual transmi tt er s can be powered down.

Individual Jitter Attenuator E nable

IJAE

Enabl es the jitt er att enuator.

Individual Jitt er Att enuator Posi tion

Select

IJAPS

Sel ec ts whether jit ter att enuator is in transmit or receiv e

path

Individual Jitt er Attenuator FIFO

Depth Selec t

IJAFDS Selects depth of jitter attenuator FIFO.

Individual Jitt er Att enuator FIFO

Limit Trip

IJAFLT

Indicates jitter att enuator FIFO wit hin 4 bits of its us eful

limit.

Individual Short-Circuit Protection

Disable

ISCPD

This regi ster allows the individual transmit ters to have

short-circ uit prot ection disabl e.

Bi t Er r or Rate Tester Control BTCR

This regi ster allows mappi ng of the i nternal BERT s into

an individual transmit path.

Transmit Cloc k Inv er t

TCLKI

Inverts TCLK input.

BPV Error I nsertion BEIR

Inserts a bi polar er r or in the transm it path when in single-

rail mode.

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5.4.1 Transmit Line Templates

The DS26324 transmi tt er s can be selec ted i ndividually to meet the pulse masks for E 1 and T1/ J 1 m ode. The T1/ J 1

pulse mask is shown in the Transmit Pulse Template and can be configured on an individual LIU basis. The

transmit template is selected via the TS2-TS0 bits in the TS register. Transmit impedance matching is selected

using the TIMPOFF and the TIMPRM bits of the same register. When transmit impedance matching is enabled

TIMPRM will select between 75Ω and 120Ω impedance if an E1 template is selected, and between 100Ω and

110Ω impedance if a T1/J1 template is selected. In E1 mode, if 75Ω is selected via the TIMPRM bit, the output

pulse amplit ude will be 2.37V, if 120Ω is selected via the TIMPRIM bit, t he output pul se amplitude will be 3.0V.

The E1 pulse template is shown in Figure 5-7 and the T1 pulse template is shown in Figure 5-6.

Table 5-4. Template Sele ctions for Sh ort-Haul Mode

TS2, TS 1 , TS 0

APPLICATION

000

E1

001

Reserved

010

011

DSX-1 (0–133ft)

100

DSX-1 (133–266ft)

101

DSX-1 (266–399ft)

110

DSX-1 (399–533ft)

111

DSX-1 (533–655ft)

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Figure 5-6. T1 Tran smit Pu lse Template s

1.2

0

-0.1

-0.2

-0.3

-0.4

-0.5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

-500 -300 -100 0300 500 700

-400 -200 200 400 600100

T IM E (n s )

NORMALIZED AMPLITUDE

T1 .10 2/87, T1 .40 3,

CB 119 (O ct. 79), &

I.431 Tem plate

-0.77

-0.39

-0.27

-0.12

0.00

0.27

0.35

0.93

1.16

-500

-255

-175

-75

0

175

225

600

750

0.05

0.80

1.15

1.05

-0.07

0.05

-0.77

-0.23

-0.15

0.00

0.15

0.23

0.46

0.66

0.93

1.16

-500

-150

-100

0

100

150

300

430

600

750

-0.05

0.50

0.95

0.90

0.50

-0.45

-0.20

-0.05

UI Tim e Amp.

MAXIMUM CURVE UI Tim e Amp.

MINIM UM CURVE

-0.77

-0.39

-0.27

-0.12

0.00

0.27

0.34

0.77

1.16

-500

-255

-175

-75

0

175

225

600

750

0.05

0.80

1.20

1.05

-0.05

0.05

-0.77

-0.23

-0.15

0.00

0.15

0.23

0.46

0.61

0.93

1.16

-500

-150

-100

0

100

150

300

430

600

750

-0.05

0.50

0.95

0.90

0.50

-0.45

-0.26

-0.05

UI Tim e Amp.

MAXIMUM CURVE UI Tim e Amp.

MINIM UM CURVE

D SX -1 T em plate (per AN SI T 1.102 -1993) D S1 Template (per A N SI T 1.403 -1995)

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Figure 5-7. E1 Transm it Pulse Tem plates

0

-0.1

-0.2

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0

TIME (n s )

SCALED AMPLITUDE

50 100 150 200 250-50-100-150-200-250

269ns

194ns

219ns

(in 75 ohm systems, 1 .0 on the scale = 2.37V peak

in 120 ohm systems, 1.0 on the scale = 3.00Vpeak)

G.703

Template

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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5.4.2 LI U Transmit Front-End

It is recommended t hat t he LIU for the transmit ter be configur ed as descri bed in Figure 5-8 and in Table 5-5.

Figure 5-8. LI U Fron t-End

optional

termination

C1

(One Channel)

TTIP

TRING

RTIP

RRING

Dt

Ct

1:2

TFt

1:1 or 1:2

TFr

Tx Line

Rx Line

VDDTn

GNDTn

TVS1

3.3V

C2

3.3V

C3

AVDDn

AVSSn

3.3V

C4 Rt

C5

Rt

A110 A100 A75

Dt

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Table 5-5. LIU Front-End Values

MODE COMPONENT 75

Ω

COAX, 120

Ω

TWISTED PAIR,

100/110Ω T WISTED PAIR

Tx Capac itance Ct 560pF typical. Adjust for board parasit ic s for optim al r eturn loss.

Tx Protecti on Dt1

Int er national Rectifier 11DQ04 or 10BQ060,

Motorola MBR0540T1

Rx Tr ansformer RTR 1: 1 TFr Pulse TX1475

Tx Transformer 1:2 TFt Halo TG83-S005NU

Rx Tr ansformer RTR 1: 2 TFr Pulse T1124 (0°C to +70°C),

Pul se T1114 ( -40°C to 85°C)

Tx Transformer 1:2 TFt

Tx Dec oupling (TV DDn)

C1

Common decoupling for all 16 channels = 68

µ

F.

Tx Dec oupling (TV DDn)

C2

Recommended dec oupling per c hannel = 0.1

µ

F.

Rx Decoupling (AVDD) C3

Common decoupling for all 16 channels = 68

µ

F.

Rx Decoupling (AVDD)

C4

Decoupl e all six pins separately with a 0.1

µ

F capacitor .

Rx Terminati on

C51

Rx capacitance for all 16 channels = 0.1

µ

F.

Rx Terminati on RTR 1:1

Rt1

Need two resi stor s = 60.4

Ω

±1%.

Rx Terminati on RTR 1:2

Rt1

Need two resi stor s = 15.0Ω ±1%.

Vol tage Pr otection

TVS1

SGS-Thomson SMLVT 3V 3 (3.3V Tr ansi ent Suppressor )

1Only us e if necess ar y for app lic at ion.

5.4.3 Tran s mit D ual-Rail Mode

Transmit dual-rail m ode c onsi sts of the T P OS, T NEG, and TCLK pi ns on t he system side. NRZ data i s sampled o n

the f alling edge of T CLK as shown in Figure 9-12.

B8ZS or HDB 3 enc oding is not available in transmit dual-rail mode. The data that appear s on the TPOS and T NE G

pins i s output on TTI P and TRING wit hout any m odificati on. The Singl e-Rail Mode S el ect Register (SRMS) i s used

f or sel ection of dual -rail or single-rail m ode. The data that arriv es at the TPOS and TNEG c an be ov erwr it ten in t he

m aintenance m ode by setting the BERT Cont r ol Register (BTCR).

5.4.4 Transmit Single-Rail Mode

Transmi t si ngle-r ail mode consists of t he TPOS and TCLK pi ns on the system si de (TNEG i s not used.). NRZ dat a

is sampl ed on t he f alli ng edge of TCLK as sh o wn i n Figure 9-12. The zer o substi t ution B8Z S or HDB 3 encodi ng is

allowed. The TPOS data is encoded in AMI or B8ZS/HDB3 format on the TTIP and TRING pins after pulse

shaping. The Single-Rail Mode Select Register (SRMS) is used for selection of dual-rail or single-rail mode. The

data that arrives at the TPOS can be overwritten in the maintenance mode by setting in Bit Error Rate Tester

Control Register (BTCR).

5.4.5 Zero Suppression—B8ZS or HDB3

B8ZS coding is av ailable when the device is in T1 mode (selected by TS2, TS1 and TS0 bits in the TS register).

B8ZS/HDB3 coding are enabled by default in single-rail mode. Setting the LCS bit in the LCS Register disables

B8ZS /HDB3. Not e that if the i ndiv i dual LIU is confi gured i n E1 mode t hen HDB3 code substi t uti on will be select ed.

Bipolar violations can be inserted via the BEIR register only if B8ZS or HDB3 coding is tur ned off .

B8ZS substi tuti on is defined in ANSI T1. 102 and HDB 3 in IT U-T G.703 standards.

5.4.6 Tran s mit Power-Down

The t r ansmit ter will be powered down if the relevant bits in the TPDE ar e set. The TTI P/TRING out puts wi ll be high

im pedanc e when TPDE is set.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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5.4.7 Transmit All Ones

When Transmit All Ones is invoked, continuous ones are transmitted using MCLK as the timing reference. Data

input at TPOS and TNEG is i gnor ed.

Transmi t A ll O nes can be sent by sett ing bi ts i n the TAOE Register . Al so, T ransmit All Ones will be enabl ed i f bi ts

in ATAOS are set and the corr espondi ng r ec eiver goes into LOS state in stat us register LOSS.

5.4.8 Dr iv er Fail Mo nitor

The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a short or open circuit on the

secondary side of the transmit transformer. The drive current will be limited to 50mA if a short circuit is detected.

The DFMS stat us register s and the c orre spondi ng int errupt and enabl e regi ster s can be u sed to m onit or t he driv er

failure.

5.5 Receiver

The DS26324’s 16 receivers are all identic al. A 1:2 or 1:1 tr ansformer can be used on the r ec eive side ( sel ec ted by

the RTR bit), but only a 1:1 transformer can be used if fully internal impedance match is enabled. Fully internal

receive impdeance match does not require the use of any external resistor on the receive line. If partially internal

im pdeance mat ching is sel ected, the DS26334 wil l need only an ex ternal 120Ω resistor (30Ω for a 1:2 transf orm er)

for E1, T1, and J1. The receive impedance match settings are controlled by the transmit template/impedance

selection. See Figure 5-8 and Table 5-5 for external component values. Partially internal impedance matching is

enabled via the TS.RIMPON bit. Fully internal impedance matching is enabled by setting GC.RIMPMS and

TS.RIMPON.

The peak det ect or and data sli cer process the r eceiv ed signal . The output of the dat a slicer goes to clock and data

recovery. A 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery

system deriv es E1 or T1 cl ock. T he clock recov ery system uses the clock from the PLL circui t to form a 16 tim es

oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding

performance to meet jitter toleranc e specif ications.

B8ZS /HDB3/AMI decoding is av ailabl e when single-rail mode i s selected. The selection of single-r ai l or dual rail i s

done by settings i n the SRMS register.

The rec eiver is capable of recovering si gnals up to 18dB worth of att enuation. The rec eiver contains functionalit y to

provide resistive gain up to 20dB for monitor mode.

Three r ec eive termi nation modes are available:

1) External Impedance Matching. Internal impedance matching is disabled, external resistor should match

line im pedanc e.

2) Partially Internal Impedance Matching. Internal impedance matching is enabled, in parallel with an

ex ternal termi nati on resistor ( one value for all termi nations).

3) Fully Internal Impedance Matching. Internal impedance matching is enabled, no external termination

necessary. This m ode r equir es a 1:1 receive-side transformer.

5.5.1 Receiver Impedance Matching Calibration

In fully internal impedance matching mode, calibration of the internal resistors is necessary to match the line

impedance accurately. Calibration must be done upon power-up of the device. The resistance of the internal

resistors does vary across temperature. Therefore, it may be necessary to recalibrate if the ambient temperature

changes more than 30°C. The user may conclude that it is necessary to recalibrate on a periodic basis if he

ex pec ts such temperature swings. Calibr ation is not neces sary for partiall y i nternal impedanc e m atch m ode.

5.5.2 Re ceiver Monitor Mode

The receiv e equalizer is equipped wi th m oni tor mode function that allows for resistiv e gain up to 20dB, along with

cabl e att enuation of 6dB to 24dB as shown in the RSMM1–4 registers.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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5.5.3 Peak Detector and Slicer

The slicer determines the polarity and presence of the received data. The output of the slicer is sent to the clock

and data rec over y c ir c uitry for extrac tion of data and clock . T he sl icer has a built-in peak detector for determi nation

of t he sli ci ng threshol d.

5.5.4 Receive Level Indicator

The DS26324 will repor t the si gnal str ength at RTI P and RRING in incr em ents described in Table 6-17. via r egister

bits CnRL3–CnRL0 l oc ated i n the RSL1–4 registers.

5.5.5 Clock and Data Recovery

The resul tant E 1 or T1 clock derived from the 2. 048/1.544 PLL i s i nternally multiplied by 16 via another i nternal P LL

and f ed to the clock recovery system. The clock recovery system uses the cl ock f rom t he PLL circuit to form a 16

times oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding

performance to meet jitter toleranc e specif ications.

5.5.6 Loss of Signal

The DS26324 use s both the digi tal and analog l oss-detec ti on m ethod in com plianc e with t he latest ANSI T1.231 for

T1/J1 and ITU-T G.775 or ETS 300 233 for E1 mode of operati on.

LOS is detected if the receiver level falls bellow a threshold analog voltage for certain duration. Alternatively, this

can be termed as having received “zeros” for certain duration. The signal level and timing duration are defined in

accordanc e with t he A NSI T1. 231, ITU-T G.775, or ETS 300 233 specif ic ations.

The loss detection thresholds are based on c able loss of 18dB for bot h T1 and E1 m odes.

RCLK is replaced by MCLK when the receiv er det ects a l oss of signal. If the AISEL bit is set in the GC regi ster or

the IAISEL bit is set, the RPO S /RNEG dat a is replaced by A IS. The loss stat e is exited when the receiver detects a

cert ain num ber of ones densit y at a higher signal lev el than t he loss detect ion l evel. T he l oss det ect ion si gnal lev el

and los s reset signal l evel are defi ned with a hy ster esi s to pr event t he receiv er f rom bounci ng bet ween “LOS ” and

“no LOS ” states.

Table 5-6 outlines the specif ications governi ng the loss func tion.

Table 5-6. Loss Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications

CRITERIA

STANDARD

T1.231

ITU-T G.7 7 5

ETS 300 233

Loss

Detection

Criteria

No pulses are detected for 175

±75 bi ts.

No pulses are detected for

duration of 10 t o 255 bit

periods.

No pulses are detected for a

duration of 2048 bit peri ods or

1ms.

Loss Reset

Criteria

Loss is term inated if a duration

of 12. 5% ones are det ec ted over

duration of 175 ±75 bits.

Loss is not t erminat ed if 8

consecutive zeros are found if

B8ZS enc oding is used. If B8ZS

is not used l oss is not

termi nated if 100 c onsecut ive

pulses are zero.

The incomi ng si gnal has

transi tions for dur ation of 10 to

255 bit periods.

Loss reset c r iteria is not

defined.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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5.5.6.1 ANSI T1.231 for T1 and J1 Mod es

Loss is detected if the rec eived si gnal lev el is less than 200mV for dur ation of 192 bit periods. LOS is reset if the all

of t he following cri teria are m et:

• 24 or m ore ones are detect ed i n 192-bit peri od with a detect i on threshold of 300mV m easured

at RTIP and RRING.

• During the 192 bit s l ess than 100 consecutive zeros are detected.

• 8 consecutive zeros are not detec ted if B8ZS is set.

5.5.6.2 ITU-T G.775 for E1 Modes

LOS is detec ted if the rec eiv ed signal level i s l ess than 200m V for a c ontinuous durati on of 192 bit peri ods. LOS is

reset if the rec eiv e si gnal level is great er than 300mV for a durat ion of 192 bi t periods.

5.5.6.3 ETS 300 233 for E 1 Modes

LOS is detec ted if the r eceived signal level is l ess t han 200m V f or a conti nuous durati on of 2048 (1m s) bit periods.

LOS is reset if the rec eiv e si gnal lev el is great er than 300mV for a duration of 192 bit periods.

5.5.7 AIS

Table 5-7 outlines the DS26324 A IS related specif ications. Table 5-8 state s t he AIS f unctionality i n the DS26324.

The register s related to t he AIS detec tion are shown in Table 5-9.

Table 5-7. AIS Criteria ANSI T1.231, ITU-T G.775, and ETS 300 233 Specifications

CRITERIA

STANDARD

ITU-T G. 775 for E 1

ETS 300 233 for E 1

ANSI T1.231 fo r T1

AIS

Detection

Criteria

2 or fewer zeros i n eac h of 2

consecutive 512-bit stream

received.

Fewer than 3 zer os detec ted in

512 bit period.

Fewer than 9 zer os detec ted in

a 8192-bit period ( a ones

density of 99. 9% ov er a period

of 5. 3m s) are r ec eiv ed.

AIS

Clearance

Criteria

3 or more z er os i n each of 2

consecutive 512-bit streams

received.

3 or more z er os i n 512 bits

received. 9 or m or e z er os detec ted in a

8192-bit period are received.

Table 5-8. AIS Detection and Reset Criteria for DS26324

CRITERIA

STANDARD

ITU-T G. 775 for E 1

ETS 300 233 for E 1

ANSI T1.231 fo r T1

AIS

Detection

Criteria

2 or fewer zeros i n eac h of 2

consecutive 512-bit streams

received.

Fewer than 3 zer os detec ted in

512-bit period. Fewer t han 9 z er os cont ained

in 8192 bits.

AIS

Clearance

Criteria

3 or more z er os i n each of 2

consecutive 512-bit streams

received.

3 or more z er os i n 512 bits

received. 9 or m or e bits received in a

8192-bit stream .

Table 5-9. Registers Related to AIS Detection

REGISTER NAME FUNCTIONALITY

LOS/AIS Criter ia Selection

LASCS

Sect ion crit eri a for AIS (T1.231, G.775, ETS 300 233 f or E1).

Al arm I ndic ation Signal Status

AIS

Set when AIS is detec ted.

AIS Interrupt Enable

AISIE

If r eset, interrupt due to AIS is not generat ed.

AIS Interrupt Status

AISIS

Latched if t her e is a change in AIS and the inter r upt is enabled.

5.5.8 Receive Dual-Ra il Mod e

Receive dual-rail mode consists of the RPOS, RNEG, and RCLK pins on the system side. In receive dual-rail

m ode, B8ZS and HDB 3 dec oding is not availabl e. The data t hat appears on the RTIP and RRING pins i s o utput on

RPOS and RNEG without any modificati on. The Single-Rail Mode Select Regi st er (SRMS) i s used f or selection of

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dual-rail or single-rail mode. The bipolar violation (and B8ZS/HDB3) detectors detect violations in dual-rail and

single-rail modes, but in dual-rail mode the violations will only be reported to the Line Violation Detect Status

(LVDS) r egister s.

5.5.9 Receive Single-Rail Mod e

Receiv e si ngle-rail mode consists of t he RPOS, RCLK, and CV pins on the system side. B8ZS or HDB3 decoding

is available. The Single-Rail Mode Select Register (SRMS) i s used f or sel ec tion of dual-r ail or single-rail mode.

5.5.10 Bipolar V iolation and Excessive Zero De tector

The DS26324 d et ects HDB3 co de v i ol ati ons, BPV s, and ex cessive zero err ors. The r eporti ng of t he errors i s done

through t he RNEGn/CVn pin in single-rail mode and t he LVDS registers in both si ngle- and dual-rail m odes. Code

v iolati ons are only detect ed i n E1 mode wit h HDB3 enc oding. The c ode v i olati on detec tion decl ares an error when

a bipolar violation of t he same polarity as the last bipolar violation is received.

Excessive zeros are detected if eight consecutive zeros are detected with B8ZS enabled and four consecutive

zeros are detec ted with HDB 3 enabled. Exc essive zero detec ti on is enabled vi a t he Ex c essive Zero Det ect Enable

Register ( EZDE) and when HDB3/B8ZS encoding/decoding is select ed v ia the Line Code Selection Register (LCS).

The bits in the LCS, EZDE, and CVDEB registers determine the combinations that are reported. Table 5-10

outlines the functionality.

Table 5-10. BPV, Code Violation, and Excessive Zero Error Rep orting

CONDITIONS ERRORS DETECTED

LCS

EZDE

CVDEB

0

BPV (T1) /Code Violati on (E1)

0

1

BPV

0

1

0

Excessive Zeros and BPV (T1)/Code Vi olation (E1)

0

1

Excessive Zeros and BPV

1

X

BPV

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5.6 Jitter Attenuator

The DS26324 c ontains an on-board jitter attenuator that can be set to a dept h of either 32 or 128 bits via the JA DS

bit in register GC. It can also be contr olled on an individual LIU basis by setti ngs i n the IJAFDS register.

The 128-bi t m ode i s used i n appl i cations where large ex c ursions of wander are ex pected. The 32-bit mode is use d

in del ay sensi tiv e appli cations. The characteristi cs of the attenuation are shown i n Figure 5-9. T he jitter attenuator

can be pl ac ed in either t he r ec eive path or the t r ansmit path or none by appr opr iat ely setting t he JAPS and the JAE

bits in regi ster GC. These selecti ons can be changed on an indiv idual LI U basis by settings in the IJAPS and IJAE.

In order for the jitter attenuator to operate properly, a 2.048MHz clock or multiple thereof, or 1.544MHz clock or

m ul ti ple t hereof , m ust be appl ied at MCLK. ITU-T specifi cation G.703 requires an accuracy of ±50ppm for both T1

and E1 appl ic ati ons. A T&T Pub 62411 and A NS I specs r equir e an ac c ur ac y of ±32ppm f or T1 interfac es. On-board

ci rcuit ry adjusts eit her t he recovered cl ock f rom the c lock/ data rec ov ery bl ock or the cl ock appli ed at the T CLK pi n

to create a sm ooth ji tter-free clock, which is used to cl ock data out of the jit ter attenuat or FIFO. It is accept abl e to

provide a jittery clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter

exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), the DS26324 will divide the

int ernal nominal 32.768M Hz (E1) or 24.704M Hz (T 1) cl ock by eit her 15 or 17 i nstead of the nor m al 16 t o keep t he

buffer from overflowing. When the device divides by either 15 or 17, it also sets the jitter attenuator limit trip

(IJAFLT) bits in the IJAFLT register described.

Figure 5-9. Jitter Atten u ation

FREQUENCY (Hz)

0dB

-20dB

-40dB

-60dB

110 100 1K 10K

JITTER ATTENUATION (dB)

100K

TR 62 411 ( Dec . 90)

Prohibited Area

Cur ve B

Cur ve A

ITU G.7XX

Prohibited Area

TBR12

Prohibited

Area

T1E1

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5.7 G.772 Monitor

In t his appl ic ation, only 14 transceivers are f unct i onal and t wo transceivers are used f or noni ntr usiv e monit oring of

input and out put of the ot her 14 c hannels. Channel 9 is used for 10 to 16 channels and Channel 1 is used for 2 to 8

channel s. G. 772 moni tori ng is configur ed by the B ERT and G. 772 Moni toring Cont rol Register (BGMC) (see Table

6-9). While m onitoring, Channel 1 c an be c onfigured in rem ote loopback and the monit or ed si gnal can be output on

TTIP 1 and T RING 1. W hile m oni t oring, Channel 9 can be conf igured i n rem ote loopback and t he monitor ed si gnal

can be output on TTIP9 and TRING9.

5.8 Loopbacks

The DS26324 provides four loopbacks for diagnostic purposes: analog loopback, digital loopback, remote

loopbac k , and dual loopback. Dual loopback is accom plished by tur ning on digital loopback and r em ote loopback at

the sam e time.

5.8.1 Analog Loopback

The anal og output of the t ransmi tt er TTIP and T RING is looped back to RTIP and RRING of the receiv er. Dat a at

RTI P and RRING is i gnor ed in analog loopback. T his i s shown in Figure 5-10.

Figure 5-10. Analog Loopback

Line

Driver

HDB3/

B8ZS

Encoder

Optional

J itte r

Attenuator T ra n s m it

Digital Transm it

Analog

TCLK

TPOS

TNEG

HDB3/

B8ZS

Decoder

O ptional

J itte r

Attenuator

Receive

Digital Receive

Analog

RCLK

RPOS

RNEG

Rtip

Rring

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5.8.2 Digital Loopback

The transmit system data TPOS, TNEG, and TCLK will be looped back to out put on RCLK, RPOS, and RNEG. The

data input at TPOS and TNEG is output on TTIP and TRING. All ones can also be output when selected by the

Transmit All Ones Enable Register (TAOE). Signals at RTIP and RRING will be ignored. This loopback is

concept ually shown in Figure 5-11.

Figure 5-11. Digital Loopback

Line

Driver

HDB3/

B8ZS

Encoder

Optional

J itte r

Attenuator

T ra n s m it

Digital Transm it

Analog

TCLK

TPOS

TNEG

HDB3/

B8ZS

Decoder

O ptional

J itte r

Attenuator

Receive

Digital Receive

Analog

RCLK

RPOS

RNEG

RTIP

RRING

TPOS

TNEG

5.8.3 Remote Loopback

The inputs at RTIP and RRING are looped back to TTIP and TRING. The inputs at TCLK, TPOS, and TNEG are

ignor ed dur ing a r em ote loopback . This loopback is conceptually shown in Figure 5-12.

Note: Remote loopback does not take precedence over transmit power-down and requires TCLK to operate. The

transmitters will use the recovered RCLK in remote loopback. TCLK is still required because if it is removed the

transmit ters will power-down (T CLK held low) or transmi t all ones (TCLK held high) .

Figure 5-12. Remote Loop back

Line

Driver

HDB3/

B8ZS

Encoder

Optional

J itte r

Attenuator

T ra n s m it

Digital Transm it

Analog

TCLK

TPOS

TNEG

HDB3/

B8ZS

Decoder

O ptional

J itte r

Attenuator

Receive

Digital Receive

Analog

RCLK

RPOS

RNEG

RTIP

RRING

TPOS

TNEG

TTIP

TRING

TTIP

TRING

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5.9 BERT

There are two bit error-rate testers av ailable on the DS26324. One BERT can be mapped into LIUs 1–8 and the

other into LIUs 9–16 via the BTCR r egister s. The t wo BERT s operat e independent ly of each other.

Each BE RT t r ansmitter, by default, r eplac es data from T P OS and TNEG ; each B E RT receiver, by default, samples

recover ed data from RTIP and RRING.

The BERT can be enabled to replace data received on RTIP and RRING via the BERTDIR bit in the BERT and

G. 772 M onitoring Control Register (BGMC). In this m ode, t he S RMS bit determi nes whether data com es out si ngle-

rai l or dual -rail . BERT data can be sourced u si ng the recov er ed cl ock, MCLK, or TCLK. I n this mode of operation,

the BERT receiver samples data on TPOS and TNEG on the falling edge of TCLK. This function is useful for

testing the digital side of the LIU. If TCLK is selected as a source for this mode, the input TCLK will control the

BERT transmitter and receiver. If the recovered clock or MCLK is selected, the RCLK output needs to drive the

TCLK input in order for the BERT receiver to sync t o the dat a.

5.9.1 General Description

The BERT is a software-programmable test pattern generator and monitor capable of meeting most error

performance requirements for digital transmission equipment. It will generate and synchronize to pseudorandom

patt erns wi th a generation polynomi al of the form x n + xy + 1, where n and y can take on v alues f rom 1 to 32 and

repetitive patter ns of any length up to 32 bits.

The transmit di rection generates the programm able test pattern, and i nserts the t est pattern payload int o the data

stream.

The receiv e di recti on ext racts the test patt ern payload from the rec eiv e data stream, and monitors the test pat tern

payl oad for the progr ammabl e test pat tern.

5.9.1.1 BERT Features

• Programmable PRBS Pattern. The pseudorandom bit sequence (PRBS) polynomial (xn + xy + 1) and

seed are programmable (length n = 1 to 32, tap y = 1 to n – 1, and seed = 0 to 2n – 1).

• Programmable Repetitive Pattern. The repetitive pattern length and pattern are programmable (the

length n = 1 to 32 and pattern = 0 to 2n – 1).

• 24-Bit Error Count and 32-Bit Bit Count Registers

• Prog rammabl e Bit-Error In sert io n. E rrors can be i nserted i ndiv idually, on a pi n transiti on, or at a specifi c

rate. The rat e 1/10n i s programmable (n = 1 to 7).

• Pattern Synchronization at a 10-3 BER. Pattern synchronization is achieved even in the presence of a

random bit error r ate (BER) of 10-3.

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5.9.2 Configuration and Mon itor ing

Set BTCR.BERTE = 1 to enable the BERT. The following t ables show how to configure the on-boar d B E RT t o send

and receive c ommon patterns.

Table 5-11. Pseudorandom Pat tern Generation

PA TTERN TYPE BPCR REGISTER BERT.

PCR BERT.

SPR2 BERT.

SPR1

BERT.CR

PTF[4:0]

(hex)

PLF[4:0]

(hex)

PTS QRSS

TPIC,

RPIC

29-1 O.153 ( 511 type) 04 08 0 0 0x0408 0xFFFF 0xFFFF 0

211-1 O.152 and O. 153

(2047 ty pe)

08 0A 0 0 0x080A 0xFFFF 0xFFFF 0

215-1 O.151 0D 0E 0 0 0x0D0E 0xFFFF 0xFFFF 1

220-1 O.153 10 13 0 0 0x1013 0xFFFF 0xFFFF 0

220-1 O.151 QRSS 02 13 0 1 0x0253 0xFFFF 0xFFFF 0

2

23

-1 O. 151 11 16 0 0 0x1116 0xFFFF 0xFFFF 1

Table 5-12. Repetitive Pattern Generation

PA TTERN TYPE BPCR REGISTER BERT.

PCR BERT.

SPR2 BERT.

SPR1

PTF[4:0]

(hex)

PLF[4:0]

(hex)

PTS QRSS

All Ones NA 00 1 0 0x0020 0xFFFF 0xFFFF

All Zeros NA 00 1 0 0x0020 0xFFFF 0xFFFE

Al ternating Ones and Zeros NA 01 1 0 0x0021 0xFFFF 0xFFFE

Double A lternating and Zer os NA 03 1 0 0x0023 0xFFFF 0xFFFC

3 in 24 NA 17 1 0 0x0037 0xFF20 0x0022

1 in 16 NA 0F 1 0 0x002F 0xFFFF 0x0001

1 in 8 NA 07 1 0 0x0027 0xFFFF 0xFF01

1 in 4 NA 03 1 0 0x0023 0xFFFF 0xFFF1

After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one

transi tion on BCR.TNPL and BCR.RNPL

Moni toring the BERT requires reading t he BSR regi st er, which contains the Bit Error Count (BEC) bit and the Out

of Synchroni zati on (OOS) bit. The BEC bit will be one when the bi t error counter is one or m ore. The OOS will be

one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it

receives a minimum 6 bit errors within a 64-bit window. The Receive BERT Bit Count Register (RBCR) and the

Receive BERT Bit Error Count Register (RBECR) will be updated upon the reception of a Performance Monitor

Update signal (e. g., BCR.LP MU). This signal will update t he regi sters wi t h the v alues of t he counter s si nce t he last

update and will reset the count er s.

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5.9.3 Receive Pattern Detection

The Receiv e BERT receives only the pay load dat a and sy nchroni zes the receiv e patt ern generat or to the incomi ng

patt ern. T he receiv e patt ern generat or is a 32-bit shift regi ster t hat shif t s data from the l east signifi cant bit ( LSB) or

bit 1 to the most signifi cant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generati ng

polynomial xn + xy + 1), the feedback is an XOR of bit n and bit y . For a repetitiv e patt er n (l ength n), the feedback is

bit n. The values for n and y ar e individually progr am m able ( 1 to 32). The output of the rec eive pat tern generator is

the feedback. If QRSS is enabl ed, the feedback is an XOR of bits 17 and 20, and the output will be for c ed to one if

the nex t 14 bit s are all zer os. QRSS is program m able (on or of f ). For P RBS and Q RSS pat terns, t he feedbac k wil l

be forc ed to one i f bits 1 through 31 are all zer os. Depending on the type of patter n pr ogr am med, pattern detecti on

performs either PRBS synchroniz ation or repetitive pat tern synchr oniz ati on.

5.9.3.1 Receive PRBS Synchronization

PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The

receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and

then chec ki ng the next 32 dat a stream bits. Synchr onizati on is achi ev ed if all 32 bit s m at ch the i ncoming pattern. If

at least six inc omi ng bits in the cur r ent 64-bit window do not match t he r ec eive patt er n gener ator, automatic patter n

re-synchroniz ation is initi ated. Aut om atic patter n re-synchronizati on c an be disabl ed.

See Figure 5-13 f or the PRBS synchroniz ation diagram.

Figure 5-13. PRBS Synchronization State Diagram

Sync

LoadVerify

1 bit error

32 bits loaded

32 bits without errors

6 of 64 bits with errors

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5.9.3.2 Receive Rep et iti ve P attern S ynch ron izat io n

Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.

The receive pattern generator is synchronized by searching each incoming data stream bit position for the

repetitive pattern, and then checki ng t he next 32 data stream bits. Synchroni zati on i s achi ev ed if all 32 bit s m atch

the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS

pattern generator, automatic pattern re-synchronization is initiated. Automatic pattern re-synchronization can be

disabled.

See Figure 5-14 f or the repetitive patter n synchr onization stat e diagr am .

Figure 5-14. Repetitive Pattern Synch ronization State Diagram

Sync

MatchVerify

1 bit error

Pattern Matches

32 bits without errors

6 of 64 bits with errors

5.9.3.3 Receive Pat t ern Monitoring

Receive pattern monitoring monitors the incoming dat a str eam for both an OOS c ondition and bit er r or s and count s

the i ncoming bit s. An O ut Of Synchroniz ation (OO S) condi ti on is declar ed when the synchroni zat i on state m achine

is not i n t he “Sync ” state. An O OS condi tion i s terminated when the synchroni zat i on state m achi ne is in t he “Sy nc”

state.

Bi t err or s are det er m ined by c om par ing the incoming data stream bit t o the receive pattern generator out put. If they

do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit

count is incremented. The bit count and bit error count are not incremented when an OOS condi tion exists.

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5.9.4 Transmit Pattern Generation

Pattern generation generates the outgoing test pattern, and passes it onto error insertion. The transmit pattern

generator is a 32-bit shift regi ster that shifts data f rom the l east si gnificant bit (LSB) or bit 1 to the m ost si gnificant

bit (M SB) or bit 32. The input t o bit 1 is the f eedback. For a PRBS pattern (generati ng pol ynomial x n + xy + 1), the

feedback is an XOR of bit n and bit y . F or a r epeti tive patter n ( length n), the feedback is bit n. The values for n and

y are i ndividuall y programmable (1 to 32). The output of t he receive pattern generator i s the f eedback. If QRSS is

enabled, the f eedback is an XOR of bits 17 and 20, and the out put wil l be f orced to one if the next 14 bi ts are al l

zeros. Q RSS i s programm able (on or off ). For P RBS and QRSS pat terns, t he feedbac k wil l be f orced t o one if bit s

1 through 31 ar e all zer os. When a new pattern is loaded, the pat tern generator is loaded with a seed/ patt er n value

before patt er n gener ati on starts. The seed/pat tern value is program m able (0 – 2n – 1).

5.9.4.1 Transmit Error Insertion

Error insert ion insert s error s i nto the outgoing patter n data stream . Errors are i nsert ed one at a time or at a rate of

one out of ev er y 10n bits. The value of n is programmable (1 to 7 or off). Single bit er r or i nserti on c an be initi ated

from the microprocess or interface, or by the manual error insertion input (TMEI). The method of single error

insert ion is program mable ( r egister or input). If patt er n inversion is enabled, the dat a s tream is inverted before the

ov er head/stuff bit s are inserted. Patt er n inv er si on is programmable (on or off).

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6 REGISTER MAPS AND DEFINITION

Six address bi ts are u sed to contr ol t he setti ngs of the regi sters. I n the par all el nonmulti plex ed m ode address [ 5:0]

is used. In multiplexed mode A D[5: 0] is used and A[6:1] i s used in t he serial mode. T he r egister space contai ns two

independent set s of regi st ers. The lower set of registers (LIUs 1–8) is locat ed f rom address 00 hex to 1F hex and

contai ns control s f or LIU s 1–8. The upper set of registers (LIUs 9–16) i s a dupl icate of the lower set, located f rom

address 20 hex t o 3F hex t hat cont rol s LIUs 9–16. Ea ch of these sets of regi sters consi sts of f our bank s: Pri m ary,

Secondary , I ndiv idual LI U, and BE RT.

The ADDP register f or the lower set of registers (LIUs 1–8) is loc ated at address 1F hex . Thi s regi ster i s used as a

point er to access the 4 bank s of regi st ers in t he l ower (LIUs 1–8) register set. Similarly, the ADDP register f or the

upper set of r egisters (LI Us 9–16) i s l oc ated at addr ess 3F hex . Thi s register is used as a point er to acc ess th e four

banks of registers in the upper (LIUs 9–16) register set. Setting an ADDP register to AA hex will access the

secondary bank of register s, 01 hex wi ll access the In divi dual LIU bank of regi sters, 02 hex will access the BERT

bank of registers, and 00 hex (default on power-up) will access the Primary bank of registers. Note that bank

select ion f or the l ower set of r egister s (LIUs 1–8) i s cont roll ed onl y by the ADDP at 1F hex and that bank select i on

for the upper set of registers (LI Us 9–16) i s cont r olled only by the A DDP at 3F hex.

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Table 6-1. Primary Register Set

REGISTER NAME HEX FOR

CH 1–8

ADDRESS FOR CH 1–8

HEX FOR

CH 9–16

ADDRESS FOR CH 9–16

RW

PARALLEL

INTERFACE

A[7:0] (HEX)

SERIAL

INTERFACE

A[7:1] (HEX)

PARALLEL

INTERFACE

A[7:0] (HEX)

SERIAL

INTERFACE

A[7:1] (HEX)

Identification

ID

00

xx000000

x000000

20

Not used

R

Anal og Loopbac k Control

ALBC

01

xx000001

x000001

21

xx100001

x100001

RW

Rem ote Loopback Contr ol

RLBC

02

xx000010

x000010

22

xx100010

x100010

RW

Transmit All Ones Enable

TAOE

03

xx000011

x000011

23

xx100011

x100011

RW

Loss of Si gnal S tatus

LOSS

04

xx000100

x000100

24

xx100100

x100100

R

Driver Fault M onitor Status

DFMS

05

xx000101

x000101

25

xx100101

x100101

R

Loss of Si gnal Int er r upt Enable

LOSIE

06

xx000110

x000110

26

xx100110

x100110

RW

Driver Fault M onitor Inter r upt Enable

DFMIE

07

xx000111

x000111

27

xx100111

x100111

RW

Loss of Si gnal Int er r upt Stat us

LOSIS

08

xx001000

x001000

28

xx101000

x101000

R

Driver Fault M onitor Inter r upt Stat us

DFMIS

09

xx001001

x001001

29

xx101001

x101001

R

Software Reset

SWR

0A

xx001010

x001010

2A

xx101010

x101010

W

BERT and G. 772 M onitoring Control

BGMC

0B

xx001011

x001011

2B

xx101011

x101011

RW

Digital Loopback Control

DLBC

0C

xx001100

x001100

2C

xx101100

x101100

RW

LOS/AIS Criter ia Selection

LASCS

0D

xx001101

x001101

2D

xx101101

x101101

RW

Autom atic Transmit All Ones Select

ATAOS

0E

xx001110

x001110

2E

xx101110

x101110

RW

Global Confi gur ation

GC

0F

xx001111

x001111

2F

xx101111

x101111

RW

Template Select Transmitter

TST

10

xx010000

x010000

30

xx110000

x110000

RW

Temp late Sele ct

TS

11

xx010001

x010001

31

xx110001

x110001

RW

Output Enable Configuration

OE

12

xx010010

x010010

32

xx110010

x110010

RW

Al arm I ndic ation Signal Stat us

AIS

13

xx010011

x010011

33

xx110011

x110011

R

AIS Interrupt Enable

AISIE

14

xx010100

x010100

34

xx110100

x110100

RW

AIS Interrupt Status

AISIS

15

xx010101

x010101

35

xx110101

x110101

R

Reserved — 16–1E

xx010110–

xx011110

x010110–

x011110

36–3E

xx110110–

x111110

x110110–

x111110

—

Address Pointer for Bank Selection

ADDP

1F

xx011111

x011111

3F

xx111111

x111111

RW

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Table 6-2. Secondary Register Set

REGISTER NAME HEX

FOR

CH 1–8

ADDRESS FOR CHANNELS 1–8

HEX

FOR

CH 9–16

ADDRESS FOR CHANNELS 9–16

RW

PARALLEL

INTERFACE

A[7:0] (HEX)

SERIAL

INTERFACE

A[7:1] (HEX)

PARALLEL

INTERFACE

A[7:0] (HEX)

SERIAL

INTERFACE

A[7:1] (HEX)

Single-Rail Mode Select

SRMS

00

xx000000

x000000

20

xx100000

x100000

RW

Line Code S election

LCS

01

xx000001

x000001

21

xx100001

x100001

R

Not Used

—

02

xx000010

x000010

22

xx100010

x100010

R

Receive Power-Down E nable

RPDE

03

xx000011

x000011

23

xx100011

x100011

RW

Transmit Power-Down Enable

TPDE

04

xx000100

x000100

24

xx100100

x100100

RW

Excessive Zero Detect Enable

EZDE

05

xx000101

x000101

25

xx100101

x100101

R

Code Vi olation Detect Enabl e B ar

CVDEB

06

xx000110

x000110

26

xx100110

x100110

R

Not Used — 07–1E

xx000111–

xx011110

x000111–

x011110

27–3E

xx100111–

xx111110

x100111–

x111110

W

Address Point er for Bank Selection

ADDP

1F

xx011111

x011111

3F

xx111111

x111111

RW

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

42 of 120

Table 6-3. Individual LIU Register Set

REGISTER NAME HEX

FOR

CH 1–8

ADDRESS FOR CHANNELS 1–8

HEX F OR

CH 9–16

ADDRESS FOR CHANNELS 9–16

RW

PARALLEL

INTERFACE

A[7:0] (HEX)

SERIAL

INTERFACE

A[7:1] (HEX)

PARALLEL

INTERFACE

A[7:0] (HEX)

SERIAL

INTERFACE

A[7:1] (HEX)

Individual Jitt er Att enuator Enable

IJAE

00

xx000000

x000000

20

xx100000

x100000

RW

Individual Jitt er Att enuator Posi tion

Select

IJAPS 01 xx000001 x000001 21 xx100001 x100001 RW

Individual Jitt er Att enuator FIFO

Depth Selec t

IJAFDS 02 xx000010 x000010 22 xx100010 x100010 RW

Individual Jitt er Att enuator FIFO

Limit Trip

IJAFLT 03 xx000011 x000011 23 xx100011 x100011 R

Individual Short-Circuit Protection

Disable

ISCPD 04 xx000100 x000100 24 xx100100 x100100 RW

Individual AIS Select

IAISEL

05

xx000101

x000101

25

xx100101

x100101

RW

Master Clock Select

MC

06

xx000110

x000110

26

Not used

RW

Receive Sensitivity Monitor Mode

1–4

RSMM1,

RSMM2,

RSMM3,

RSMM4

08–0B xx001000–

xx001011 x001000–

x001011 28–2B xx101000–

xx101011 x101000–

x101011 RW

Receive Signal Level Indicator 1–4 RSL1–4 0C–0F

xx001100–

xx001111

x001100–

x001111

2C–2F

xx101100–

xx101111

x101100–

x101111

R

Bi t Er r or Rate Tester Control

BTCR

10

xx010000

x010000

30

xx110000

x110000

RW

Line Vi olation Detect Status

LVDS

12

xx010010

x010010

32

xx110010

x110010

R

Receive Clock Invert

RCLKI

13

xx010011

x010011

33

xx110011

x110011

RW

Transmit Cloc k Inv er t

TCLKI

14

xx010100

x010100

34

xx110100

x110100

RW

Cloc k Control Register

CCR

15

xx010101

x010101

35

Not used

RW

RCLK Di sabl e Upon LOS

RDULR

16

xx010110

x010110

36

xx110110

x110110

RW

Global I nterr upt Status Contr ol

GISC

1E

xx011110

x011110

3E

Not used

RW

Address Point er for Bank Selection

ADDP

1F

xx011111

x011111

3F

xx111111

x111111

RW

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

43 of 120

Table 6-4. BERT Reg ister Set

REGISTER NAME HEX FO R

CH 1–8

ADDRESS FO R CHANNELS 1–8

HEX FOR

CH 9–16

ADDRESS FOR CHANNELS 9–16

RW

PARALLEL

INTERFACE

A[7 :0] (HE X )

SERIAL

INTERFACE

A[7 :1] (HE X )

PARALLEL

INTERFACE

A[7 :0] (HE X )

SERIAL

INTERFACE

A[7 :1] (HE X )

BERT Control

BCR

00

xx000000

x000000

20

xx100000

x100000

RW

Reserved

—

01

xx000001

x000001

21

xx100001

x100001

—

BERT Pattern Configurati on 1

BPCR1

02

xx000010

x000010

22

xx100010

x100010

RW

BERT Pattern Configurati on 2

BPCR2

03

xx000011

x000011

23

xx100011

x100011

RW

BERT Seed/Pattern 1

BSPR1

04

xx000100

x000100

24

xx100100

x100100

RW

BERT Seed/Pattern 2

BSPR2

05

xx000101

x000101

25

xx100101

x100101

RW

BERT Seed/Pat tern 3

BSPR3

06

xx000110

x000110

26

xx100110

x100110

RW

BERT Seed/Pattern 4

BSPR4

07

xx000111

x000111

27

xx100111

x100111

RW

Transmit Error Insertion Control

TEICR

08

xx001000

x001000

28

xx101000

x101000

RW

Reserved — 09–0A

xx001001–

x001010

— 29–2A

xx101001–

x101010

— —

BERT Status

BSR

0C

xx001100

x001100

2C

xx101100

x101100

R

Reserved

—

0D

xx001101

x001101

2D

xx101101

x101101

—

BERT Status Register Latched

BSRL

0E

xx010011

x010011

2E

xx110011

x110011

RW

BERT Status Register Interrupt E nable

BSRIE

10

xx010000

x010000

30

xx110000

x110000

RW

Reserved — 11–13

xx010001–

xx010011

X010001–

x010011

31–33

xx110001–

xx110011

x110001–

x110011

—

Receive Bit Err or Count Register 1

RBECR1

14

xx010100

x010100

34

xx110100

x110100

R

Receive Bit Err or Count Register 2

RBECR2

15

xx010101

x010101

35

xx110101

x110101

R

Receive Bit Err or Count Register 3

RBECR3

16

xx010110

x010110

36

xx110110

x110110

R

Receive Bit Count Register 1

RBCR1

18

xx011000

x011000

38

xx111000

x111000

R

Receive Bit Count Register 2

RBCR2

19

xx011001

x011001

39

xx111001

x111001

R

Receive Bit Count Register 3

RBCR3

1A

xx011010

x011010

3A

xx111010

x111010

R

Receive Bit Count Register 4

RBCR4

1B

xx011011

x011011

3B

xx111011

x111011

R

Reserved — 1C–1E

xx011100–

xx011110

x011100–

x011110

3C–3E

xx111100–

xx111110

x111100–

x111110

—

Address Pointer for Bank Selection

ADDP

1F

xx011111

x011111

3F

xx111111

x111111

RW

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

44 of 120

Table 6-5. Primary Register Set Bit Map

REGISTER

ADDRESS

FOR L I Us

1–8

R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ID

00

R

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

ALBC 01 RW ALBC8 ALBC7 ALBC6 ALBC5 ALBC4 ALBC3 ALBC2 ALBC1

RLBC

02

RW

RLBC8

RLBC7

RLBC6

RLBC5

RLBC4

RLBC3

RLBC2

RLBC1

TAOE

03

RW

TAOE8

TAOE7

TAOE6

TAOE5

TAOE4

TAOE3

TAOE2

TAOE1

LOSS 04 RW LOSS8 LOSS7 LOSS6 LOSS5 LOSS4 LOSS3 LOSS2 LOSS1

DFMS

05

RW

DFMS8

DFMS7

DFMS6

DFMS5

DFMS4

DFMS3

DFMS2

DFMS1

LOSIE

06

RW

LOSIE8

LOSIE7

LOSIE6

LOSIE5

LOSIE4

LOSIE3

LOSIE2

LOSIE1

DFMIE

07

RW

DFMIE8

DFMIE7

DFMIE6

DFMIE5

DFMIE4

DFMIE3

DFMIE2

DFMIE1

LOSIS

08

R

LOSIS8

LOSIS7

LOSIS6

LOSIS5

LOSIS4

LOSIS3

LOSIS2

LOSIS1

DFMIS

09

R

DFMIS8

DFMIS7

DFMIS6

DFMIS5

DFMIS4

DFMIS3

DFMIS2

DFMIS1

SWR

0A

W

SWRL

BGMC

0B

RW

BERTDIR

BMCKS

BTCKS

—

GMC4

GMC3

GMC2

GMC1

DLBC

0C

RW

DLBC8

DLBC7

DLBC6

DLBC5

DLBC4

DLBC3

DLBC2

DLBC1

LASCS

0D

RW

LASCS8

LASCS7

LASCS6

LASCS5

LASCS4

LASCS3

LASCS2

LASCS1

ATAOS 0E RW ATAOS8 ATAOS7 ATAOS6 ATAOS5 ATAOS4 ATAOS3 ATAOS2 ATAOS1

GC

0F

RW

RIMPMS

AISEL

SCPD

CODE

JADS

CRIMP

JAPS

JAE

TST

10

RW

JABWS1

JABWS0

RHPMC

—

TST2

TST1

TST0

TS 11 RW RIMPON TIMPOFF —

—

TIMPRM TS2 TS1 TS0

OE

12

RW

OE8

OE7

OE6

OE5

OE4

OE3

OE2

OE1

AIS

13

R

AIS8

AIS7

AIS6

AIS5

AIS4

AIS3

AIS2

AIS1

AISIE

14

RW

AISIE8

AISIE7

AISIE6

AISIE5

AISIE4

AISIE3

AISIE2

AISIE1

AISIS

15

R

AISIS8

AISIS7

AISIS6

AISIS5

AISIS4

AISIS3

AISIS2

AISIS1

Not Used

16-1E

—

ADDP

1F

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

REGISTER ADDRESS

FOR L I Us

9–16

R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Not Used

20

R

—

ALBC

21

RW

ALC16

ALBC15

ALBC14

ALBC13

ALBC12

ALBC11

ALBC10

ALBC9

RLBC

22

RW

RLBC16

RLBC15

RLBC14

RLBC13

RLBC12

RLBC11

RLBC10

RLBC9

TAOE

23

RW

TAOE16

TAOE15

TAOE14

TAOE13

TAOE12

TAOE11

TAOE10

TAOE9

LOSS

24

RW

LOSS16

LOSS15

LOSS14

LOSS13

LOSS12

LOSS11

LOSS10

LOSS9

DFMS 25 RW DFMS16 DFMS15 DFMS14 DFMS13 DFMS12 DFMS11 DFMS10 DFMS9

LOSIE

26

RW

LOSIE16

LOSIE15

LOSIE14

LOSIE13

LOSIE12

LOSIE11

LOSIE10

LOSIE9

DFMIE

27

RW

DFMIE16

DFMIE15

DFMIE14

DFMIE13

DFMIE12

DFMIE11

DFMIE10

DFMIE9

LOSIS 28 R LOSIS16 LOSIS15 LOSIS14 LOSIS13 LOSIS12 LOSIS11 LOSIS10 LOSIS9

DFMIS

29

R

DFMIS16

DFMIS15

DFMIS14

DFMIS13

DFMIS12

DFMIS11

DFMIS10

DFMIS9

SWR

2A

W

SWRU

BGMC

2B

RW

BERTDIR

BMCKS

BTCKS

—

GMC4

GMC3

GMC2

GMC1

DLBC

2C

RW

DLBC16

DLBC15

DLBC14

DLBC13

DLBC12

DLBC11

DLBC10

DLBC9

LASCS

2D

RW

LASCS16

LASCS15

LASCS14

LASCS13

LASCS12

LASCS11

LASCS10

LASCS9

ATAOS

2E

RW

ATAOS16

ATAOS15

ATAOS14

ATAOS13

ATAOS12

ATAOS11

ATAOS10

ATAOS9

GC 2F RW RIMPMS AISEL SCPD CODE JADS CALEN JAPS JAE

TST

30

RW

—

TST2

TST1

TST0

TS

31

RW

RIMPON

TIMPOFF

—

TIMPRM

TS2

TS1

TS0

OE

32

RW

OE16

OE15

OE14

OE13

OE12

OE11

OE10

OE9

AIS

33

R

AIS16

AIS15

AIS14

AIS13

AIS12

AIS11

AIS10

AIS9

AISIE

34

RW

AISIE16

AISIE15

AISIE14

AISIE13

AISIE12

AISIE11

AISIE10

AISIE9

AISIS

35

R

AISIS16

AISIS15

AISIS14

AISIS13

AISIS12

AISIS11

AISIS10

AISIS9

Not Used

36-3E

—

ADDP

3F

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

Note: U nderlined bits ar e read on ly.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

45 of 120

Table 6-6. Secondary Register Set Bit Map

REGISTER

ADDRESS

FOR L I Us

1–8

RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SRMS

00

RW

SRMS8

SRMS7

SRMS6

SRMS5

SRMS4

SRMS3

SRMS2

SRMS1

LCS 01 RW LCS8 LCS7 LCS6 LCS5 LSC4 LCS3 LSC2 LSC1

Not Used

02

RW

—

RPDE

03

RW

RPDE8

RPDE7

RPDE6

RPDE5

RPDE4

RPDE3

RPDE2

RPDE1

TPDE 04 RW TPDE8 TDPE7 TPDE6 TPDE5 TPDE4 TPDE3 TPDE2 TPDE1

EZDE

05

RW

EZDE8

EZDE7

EZDE6

EZDE5

EZDE4

EZDE3

EZDE2

EZDE1

CVDEB

06

RW

CVDEB8

CVDEB7

CVDEB6

CVDEB5

CVDEB4

CVDEB3

CVDEB2

CVDEB1

Not Used

07–1E

—

ADDP

1F

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

REGISTER

ADDRESS

FOR L I Us

9–16

RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SRMS

20

RW

SRMS16

SRMS15

SRMS14

SRMS13

SRMS12

SRMS11

SRMS10

SRMS9

LCS

21

RW

LCS16

LCS15

LCS14

LCS13

LSC12

LCS11

LSC10

LSC9

Not Used

22

RW

—

RPDE 23 RW RPDE16 RPDE15 RPDE14 RPDE13 RPDE12 RPDE11 RPDE10 RPDE9

TPDE

24

RW

TPDE16

TDPE15

TPDE14

TPDE13

TPDE12

TPDE11

TPDE10

TPDE9

EZDE

25

RW

EZDE16

EZDE15

EZDE14

EZDE13

EZDE12

EZDE11

EZDE10

EZDE9

CVDEB 26 RW CVDEB16 CVDEB15 CVDEB14 CVDEB13 CVDEB12 CVDEB11 CVDEB10 CVDEB9

Not Used

27–3E

—

ADDP

3F

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

46 of 120

Table 6-7. Individual LIU Register Set Bit Map

REGISTER

ADDRESS

FOR L I Us

1–8

RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IJAE

00

RW

IJAE8

IJAE7

IJAE6

IJAE5

IJAE4

IJAE3

IJAE2

IJAE1

IJAPS 01 RW IJAPS8 IJAPS7 IJAPS6 IJAPS5 IJAPS4 IJAPS3 IJAPS2 IJAPS1

IJAFDS

02

RW

IJAFDS8

IJAFDS7

IJAFDS6

IJAFDS5

IJAFDS4

IJAFDS3

IJAFDS2

IJAFDS1

IJAFLT

03

R

IJAFLT8

IJAFLT7

IJAFLT6

IJAFLT5

IJAFLT4

IJAFLT3

IJAFLT2

IJAFLT1

ISCPD 04 RW ISCPD8 ISCPD7 ISCPD6 ISCPD5 ISCPD4 ISCPD3 ISCPD2 ISCPD1

IAISEL

05

RW

IAISEL8

IAISEL7

IAISEL6

IAISEL5

IAISEL4

IAISEL3

IAISEL2

IAISEL1

MC

06

RW

PCLKI1

PCLKI0

TECLKE

CLKAE

MPS1

MPS0

FREQS

PLLE

RSMM1

08

RW

RTR2

C2RSM2

C2RSM1

C2RSM0

RTR1

C1RSM2

C1RSM1

C1RSM0

RSMM2

09

RW

RTR4

C4RSM2

C4RSM1

C4RSM0

RTR3

C3RSM2

C3RSM1

C3RSM0

RSMM3

0A

RW

RTR6

C6RSM2

C6RSM1

C6RSM0

RTR5

C5RSM2

C5RSM1

C5RSM0

RSMM4

0B

RW

RTR8

C8RSM2

C8RSM1

C8RSM0

RTR7

C7RSM2

C7RSM1

C7RSM0

RSL1

0C

R

C2RSL3

C2RSL2

C2RSL1

C2RSL0

C1RSL3

C1RSL2

C1RSL1

C1RSL0

RSL2

0D

R

C4RSL3

C4RSL2

C4RSL1

C4RSL0

C3RSL3

C3RSL2

C3RSL1

C3RSL0

RSL3

0E

R

C6RSL3

C6RSL2

C6RSL1

C6RSL0

C5RSL3

C5RSL2

C5RSL1

C5RSL0

RSL4 0F R C8RSL3 C8RSL2 C8RSL1 C8RSL0/

CALSTAT

C7RSL3 C7RSL2 C7RSL1 C7RSL0

BTCR

10

RW

BTS2

BTS1

BTS0

—

BERTE

BEIR

11

RW

BEIR8

BEIR7

BEIR6

BEIR5

BEIR4

BEIR3

BEIR2

BEIR1

LVDS

12

R

LVDS8

LVDS7

LVDS6

LVDS5

LVDS4

LVDS3

LVDS2

LVDS1

RCLKI 13 RW RCLKI8 RCLKI7 RCLKI6 RCLKI5 RCLKI4 RCLKI3 RCLKI2 RCLKI1

TCLKI

14

RW

TCLKI8

TCLKI7

TCLKI6

TCLKI5

TCLKI4

TCLKI3

TCLKI2

TCLKI1

CCR

15

RW

PCLKS2

PCLKS1

PCLKS0

TECLKS

CLKA3

CLKA2

CLKA1

CLKA0

RDULR 16 RW RDULR8 RDULR7 RDULR6 RDULR5 RDULR4 RDULR3 RDULR2 RDULR1

GISC

1E

RW

—

INTM

CWE

ADDP

1F

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

REGISTER

ADDRESS

FOR L I Us

9–16

RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IJAE

20

RW

IJAE16

IJAE15

IJAE14

IJAE13

IJAE12

IJAE11

IJAE10

IJAE9

IJAPS

21

RW

IJAPS16

IJAPS15

IJAPS14

IJAPS13

IJAPS12

IJAPS11

IJAPS10

IJAPS9

IJAFDS 22 RW IJAFDS16 IJAFDS15 IJAFDS14 IJAFDS13 IJAFDS12 IJAFDS11 IJAFDS10 IJAFDS9

IJAFLT

23

R

IJAFLT16

IJAFLT15

IJAFLT14

IJAFLT13

IJAFLT12

IJAFLT11

IJAFLT10

IJAFLT9

ISCPD

24

RW

ISCPD16

ISCPD15

ISCPD14

ISCPD13

ISCPD12

ISCPD11

ISCPD10

ISCPD9

IAISEL

25

RW

IAISEL16

IAISEL15

IAISEL14

IAISEL13

IAISEL12

IAISEL11

IAISEL10

IAISEL9

Not Used

26

RW

—

RSMM1

28

RW

RTR10

C10RSM2

C10RSM1

C10RSM0

RTR9

C9RSM2

C9RSM1

C9RSM0

RSMM2

29

RW

RTR12

C12RSM2

C12RSM1

C12RSM0

RTR11

C11RSM2

C11RSM1

C11RSM0

RSMM3 2A RW RTR14 C14RSM2 C14RSM1 C14RSM0 RTR13 C13RSM2 C13RSM1 C13RSM0

RSMM4

2B

RW

RTR16

C16RSM2

C16RSM1

C16RSM0

RTR15

C15RSM2

C15RSM1

C15RSM0

RSL1

2C

R

C10RSL3

C10RSL2

C10RSL1

C10RSL0

C9RSL3

C9RSL2

C9RSL1

C9RSL0

RSL2 2D R C12RSL3 C12RSL2 C12RSL1 C12RSL0 C11RSL3 C11RSL2 C11RSL1 C11RSL0

RSL3

2E

R

C14RSL3

C14RSL2

C14RSL1

C14RSL0

C13RSL3

C13RSL2

C13RSL1

C13RSL0

RSL4

2F

R

C16RSL3

C16RSL2

C16RSL1

C16RSL0

C15RSL3

C15RSL2

C15RSL1

C15RSL0

BTCR

30

RW

BTS2

BTS1

BTS0

—

BERTE

BEIR

31

RW

BEIR16

BEIR15

BEIR14

BEIR13

BEIR12

BEIR11

BEIR10

BEIR9

LVDS

32

R

LVDS16

LVDS15

LVDS14

LVDS13

LVDS12

LVDS11

LVDS10

LVDS9

RCLKI

33

RW

RCLKI16

RCLKI15

RCLKI14

RCLKI13

RCLKI12

RCLKI11

RCLKI10

RCLKI9

TCLKI 34 RW TCLKI16 TCLKI15 TCLKI14 TCLKI13 TCLKI12 TCLKI11 TCLKI10 TCLKI9

Not Used

35

RW

—

RDULR

36

RW

RDULR16

RDULR15

RDULR14

RDULR13

RDULR12

RDULR11

RDULR10

RDULR9

Not Used

3E

RW

—

INTM

CWE

ADDP

3F

RW

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

Note: U nderlined bits ar e read on ly.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

47 of 120

Table 6-8. BERT Reg ister Bit Map

REGISTER

ADDRESS F OR

LIUs

RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

1–8 9–16

BCR 00 20 RW PMUM LPMU RNPL RPIC MPR APRD TNPL TPIC

Not Used 01 21 — —

—

BPCR1 02 22 RW —

QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0

BPCR2 03 23 — —

—

PTF4 PTF3 PTF2 PTF1 PTF0

BSPR1 04 24 RW BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSP0

BSPR2 05 25 — BSP15 BSP14 BSP13 BSP12 BSP11 BSP10 BSP9 BSP8

BSPR3 06 26 RW BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16

BSPR4 07 27 — BSP31 BSP30 BSP29 BSP28 BSP27 BSP26 BSP25 BSP24

TEICR 08 28 RW —

—

TEIR2 TEIR1 TEIR0 BEI TSEI MEIMS

Not Used 09–0B 29–2B — —

—

BSR 0C 2C R —

—

PMS —

BEC OOS

Not Used 0D 2D — —

—

— —

—

BSRL 0E 2E R —

—

PMSL BEL BECL OOSL

Not Used 0F 2F — —

—

BSRIE 10 30 RW —

—

PMSIE BEIE BECIE OOSIE

Not Used 11–13 31–33 — —

—

RBECR1 14 34 R BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0

RBECR2 15 35 R BEC15 BEC14 BEC13 BEC12 BEC11 BEC10 BEC9 BEC8

RBECR3 16 36 R BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16

Not Used 17 37 —

—

RBCR1 18 38 R BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

RBCR2 19 39 R BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8

RBCR3 1A 3A R BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16

RBCR4 1B 3B R BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24

Not Used 1C–1E 3C–3E —

—

ADDP 1F 3F RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

Note:

U n derli n e d bits ar e re ad only .

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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6.1 Register Descrip tion

This section contains the detailed register descriptions of each bit. W henever the variable “n” in italics is used in

any of the register descriptions, it represents 1–16. Note that in the register descriptions, there are duplicate

regi st ers f or LIUs 1–8 and LIUs 9–16. There are regi st ers in LI Us 1–8 that do not hav e a duplicate in t he register

set for LIUs 9–16. For these regi ster s, only one addr es s i s l isted. Al l other r egisters li st two addresses, one for LIUs

1–8 and one for LIUs 9–16.

6.1.1 Primary Register Bank

The ADDP r egister m ust be set to 00h to access thi s bank.

Register Name:

ID

Register Descripti on:

ID Reg ister

Register A ddr ess:

00h

Bit #

7

6

5

4

3

2

1

0

Name

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

Bit 7: Device CODE ID Bit 7 (ID7). This bi t is “zero” for short -haul operation.

Bits 6 to 3: Device CODE ID Bits 6 to 3 (ID6 to ID3). These bits tell the user the number of ports the device

contains.

Bits 2 t o 0: Devi ce CODE ID Bi ts 2 to 0 (ID2 to ID0). T hese bits tel l the user the rev i sion of the part . Cont act the

factory for details.

Register Name:

ALBC

Register Descripti on:

A na log Loopba c k Co ntr ol

Register A ddr es s (LI Us 1–8):

01h

Bit #

7

6

5

4

3

2

1

0

Name

ALBC8

ALBC7

ALBC6

ALBC5

ALBC4

ALBC3

ALBC2

ALBC1

Default

0

Register A ddr es s (LI Us 9–16):

21h

Bit #

7

6

5

4

3

2

1

0

Name

ALBC16

ALBC15

ALBC14

ALBC13

ALBC12

ALBC11

ALBC10

ALBC9

Default

0

Bits 7 to 0: Analog Loopback Control Bits Channel n (ALBCn). When this bit is set, LIUn is placed in Analog

Loopback. TT IP and TRI NG are looped back to RTIP and RRING. The dat a at RT IP and RRING is ignored. LOS

Detector is sti ll in operation. The jitt er att enuator is i n use if enabled f or the transmitter or receiver.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

RLBC

Register Descripti on:

Remote Lo op back Cont rol

Register A ddr es s (LI Us 1–8):

02h

Bit #

7

6

5

4

3

2

1

0

Name

RLBC8

RLBC7

RLBC6

RLBC5

RLBC4

RLBC3

RLBC2

RLBC1

Default

0

Register A ddr es s (LI Us 9–16):

22h

Bit #

7

6

5

4

3

2

1

0

Name

RLBC16

RLBC15

RLBC14

RLBC13

RLBC12

RLBC11

RLBC10

RLBC9

Default

0

Bits 7 to 0: Remote Loopback Control Bits Channel n (RLBCn). When this bit is set, remote loopback is

enabled on LIUn. T he analog r ec eived signal goes thr ough t he r ec eive digit al and is looped bac k to t he transm itter .

The dat a at T POS and TNEG is i gnor ed. The jitter attenuator is i n use if enabled.

Register Name:

TAOE

Register Descripti on:

Transmit All Ones Enable

Register A ddr es s (LI Us 1–8):

03h

Bit #

7

6

5

4

3

2

1

0

Name

TAOE8

TAOE7

TAOE6

TAOE5

TAOE4

TAOE3

TAOE2

TAOE1

Default

0

Register A ddr es s (LI Us 9–16):

23h

Bit #

7

6

5

4

3

2

1

0

Name

TAOE16

TAOE15

TAOE14

TAOE13

TAOE12

TAOE11

TAOE10

TAOE9

Default

0

Bits 7 to 0: Transmit All Ones Enable Channel n (TAOEn). When this bit is set, continuous str eam of All ones on

TTIP and TRING ar e sent on Channel n. M CLK is used as a referenc e cl oc k for Transmi t All Ones Si gnal. The data

arriving at T POS and TNEG is i gnor ed.

Register Name:

LOSS

Register Descripti on:

Loss of S ig na l Sta tus

Register A ddr es s (LI Us 1–8):

04h

Bit #

7

6

5

4

3

2

1

0

Name

LOSS8

LOSS7

LOSS6

LOSS5

LOSS4

LOSS3

LOSS2

LOSS1

Default

0

Register A ddr es s (LI Us 9–16):

24h

Bit #

7

6

5

4

3

2

1

0

Name

LOSS16

LOSS15

LOSS14

LOSS13

LOSS12

LOSS11

LOSS10

LOSS9

Default

0

Bits 7 to 0: Loss of Signal Status Channel n (LOSSn). W hen this bit i s set , a LOS condi ti on has been detected

on LIUn. The criteri a and c onditi ons of LOS ar e described in S ection 5.5.6.

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Register Name:

DFMS

Register Descripti on:

Driver Fault Monitor Status

Register A ddr es s (LI Us 1–8):

05h

Bit #

7

6

5

4

3

2

1

0

Name

DFMS8

DFMS7

DFMS6

DFMS5

DFMS4

DFMS3

DFMS2

DFMS1

Default

0

Register A ddr es s (LI Us 9–16):

25h

Bit #

7

6

5

4

3

2

1

0

Name

DFMS16

DFMS15

DFMS14

DFMS13

DFMS12

DFMS11

DFMS10

DFMS9

Default

0

Bits 7 t o 0: Driver Faul t Monitor Status Channel n (DFMSn). When thi s bit is set, it indi c ates that there is a short

or open circ uit at the transm it driver for LIUn.

Register Name:

LOSIE

Register Descripti on:

Loss of S ig na l Int e r r upt Ena ble

Register A ddr es s (LI Us 1–8):

06h

Bit #

7

6

5

4

3

2

1

0

Name

LOSIE8

LOSIE7

LOSIE6

LOSIE5

LOSIE4

LOSIE3

LOSIE2

LOSIE1

Default

0

Register A ddr es s (LI Us 9–16):

26h

Bit #

7

6

5

4

3

2

1

0

Name

LOSIE16

LOSIE15

LOSIE14

LOSIE13

LOSIE12

LOSIE11

LOSIE10

LOSIE9

Default

0

Bits 7 to 0: Loss of Signal Interrupt Enable Channel n (LOSIEn). W hen this bit is set, a change in LO S stat us

for LIUn can generate an Interr upt.

Register Name:

DFMIE

Register Descripti on:

Driver Fault Monitor Interrupt Enable

Register A ddr es s (LI Us 1 –8):

07h

Bit #

7

6

5

4

3

2

1

0

Name

DFMIE8

DFMIE7

DFMIE6

DFMIE5

DFMIE4

DFMIE3

DFMIE2

DFMIE1

Default

0

Register A ddr es s (LI Us 9–16):

27h

Bit #

7

6

5

4

3

2

1

0

Name

DFMIE16

DFMIE15

DFMIE14

DFMIE13

DFMIE12

DFMIE11

DFMIE10

DFMIE9

Default

0

Bits 7 to 0: Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). W hen this bit is set, a change in DFM

Status can generat e an interrupt in monitor n.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

LOSIS

Register Descripti on:

Loss of S ig na l Int e r r upt Status

Register A ddr es s (LI Us 1–8):

08h

Bit #

7

6

5

4

3

2

1

0

Name

LOSIS8

LOSIS7

LOSIS6

LOSIS5

LOSIS4

LOSIS3

LOSIS2

LOSIS1

Default

0

Register A ddr es s (LI Us 9–16):

28h

Bit #

7

6

5

4

3

2

1

0

Name

LOSIS16

LOSIS15

LOSIS14

LOSIS13

LOSIS12

LOSIS11

LOSIS10

LOSIS9

Default

0

Bits 7 to 0: Loss of Signal Interrupt Status Channel n (LOSISn). W hen this bit is set , it indi cat es a LO S stat us

has transition f rom a “0 to 1” or “1 to 0” and was detected f or LIUn. The bit for LIUn i s enabl ed by register LOSIE

(06h). This bit when lat c hed is cleared on a read oper ation.

Register Name:

DFMIS

Register Descripti on:

Driver Fault Monitor Interrupt Status

Register A ddr es s (LI Us 1–8):

09h

Bit #

7

6

5

4

3

2

1

0

Name

DFMIS8

DFMIS7

DFMIS6

DFMIS5

DFMIS4

DFMIS3

DFMIS2

DFMIS1

Default

0

Register A ddr es s (LI Us 9–16):

29h

Bit #

7

6

5

4

3

2

1

0

Name

DFMIS16

DFMIS15

DFMIS14

DFMIS13

DFMIS12

DFMIS11

DFMIS10

DFMIS9

Default

0

Bits 7 t o 0: Driver Faul t S t atus Regist er Channel n (DFMISn). When t his bi t is set, i t indicat es a DFM status has

transi tioned from “0 to 1” or “1 to 0” and was detected for LI Un. The bit for LIUn is enabled by register DFMIE (07h).

This bit when lat c hed is cleared on a read operation.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

SWR

Register Descripti on:

Sof tware Reset

Register A ddr es s (LI Us 1–8):

0Ah

Bit #

7

6

5

4

3

2

1

0

Name

SWRL

Default

0

Bits 7 to 0: Software Reset (SWRL). W henev er any write is performed to this register, at least 1µs reset will be

generated t hat resets the lower set of registers (LIUs 1–8). All t he regi sters will be restored t o thei r default v alues.

A read operation will always read back all z er os.

Register A ddr es s (LI Us 9–16):

2Ah

Bit #

7

6

5

4

3

2

1

0

Name

SWRU

Default

0

Bits 7 to 0: Software Reset (SWRU). W henev er any wri te is perf orm ed to thi s register, at l east 1µs reset will be

generated that r esets the upper set of registers (LIUs 9–16). All t he r egister s will be restor ed to their default v alues.

A read operation will always read back all z er os.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

BGMC

Register Descripti on:

BERT an d G.7 7 2 Monitor ing Co ntr ol

Register A ddr es s (LI Us 1–8):

0Bh

Bit #

7

6

5

4

3

2

1

0

Name

BERTDIR

BMCKS

BTCKS

—

GMC3

GMC2

GMC1

GMC0

Default

0

Bit 7: BERT Direction Control Bit (BERTDIR). W hen t hi s bi t is set, t he BERT for LIUs 1–8 wi ll be enabl ed on the

system si de of the part (BERT dat a will c om e out on RPOS/RNEG and be expected on TPO S/TNEG) for whichever

LIU t he BERT is enabl ed.

Bit 6: BERT MCLK Selecti on (BMCKS). W hen the BERT i s enabled on t he system side (BE RTDIR = 1), sett ing

thi s bi t will select MCLK as the BERT clock unl ess BT CKS is set. If neit her BMCKS nor BTCK S is set, the BE RT

will use the r ec overed clock.

Bit 5: BERT TCLK Selection (BTCKS). When the BERT is enabled on the system side (BERTDIR = 1), setting

this bit selects TCLK as the B E RT clock , regar dless of the stat e of the BM CK S bit. If neither BM CKS nor B TCKS i s

set, the B E RT will use the rec overed clock .

Bits 3 to 0: G.772 Monitoring Control (GMC[3:0]). These bits are used to select transmitter or receiver for

nonintrusive monitoring. Receiver 1 is used to monitor Channels 2 to 8 of one receiver from RTIP2–

RTIP8/RRING2–RRING8 or of one t r ansmit ter from TTIP2–TTIP8/TRING2–TRING8. See Table 6-9.

Register A ddr es s (LI Us 9–16):

2Bh

Bit #

7

6

5

4

3

2

1

0

Name

BERTDIR

BMCKS

BTCKS

—

GMC3

GMC2

GMC1

GMC0

Default

0

Bit 7: BERT Direction Control Bit (BERTDIR). When this bit is set, the BERT for LIUs 9–16 will be enabled on

the system side of the part (BERT data will come out on RPOS/RNEG and be expected on TPOS/TNEG) for

whichever LIU the BERT is enabled.

Bit 6: BERT MCLK Selecti on (BMCKS). W hen the BERT i s enabled on t he system side (BE RTDIR = 1), sett ing

thi s bi t will select MCLK as the BERT clock unl ess BT CKS is set. If neit her BMCKS nor BTCK S is set, the BERT

will use the recov ered clock. If the clock used as the BERT clock i s MCLK or the recov ered cl ock, TCLK must be

frequenc y loc k ed to the BERT cloc k in or der for the BERT to sy nc .

Bit 5: BERT TCLK Selection (BTCKS). When the BERT is enabled on the system side (BERTDIR = 1), setting

this bit selects TCLK as the B E RT clock , regar dless of the stat e of the BM CK S bit. If neither BM CKS nor B TCKS i s

set, t he B E RT will use the rec overed clock .

Bits 3 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for

nonintrusive monitoring. Receiver 9 is used to monitor Channels 10 to 16 of one receiver from RTIP10–

RTIP16/RRING10–RRING 16 or of one transmitter from TTI P 10–TTIP16/TRING10–TRING16. See Table 6-10.

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Table 6-9. G.772 Monitoring Control (LIU 1)

GMC3 GMC2 GMC1 GMC0 SELECTION

0

No Moni toring

0

1

Receiver 2

0

1

0

Receiver 3

0

1

Receiver 4

0

1

0

Receiver 5

0

1

0

1

Receiver 6

0

1

0

Receiver 7

0

1

Receiver 8

1

0

No Moni toring

1

0

1

Transmit ter 2

1

0

1

0

Transmit ter 3

1

0

1

Transmit ter 4

1

0

Transmit ter 5

1

0

1

Transmit ter 6

1

0

Transmit ter 7

1

Transmit ter 8

Table 6-10. G.772 Monitoring Control (LIU 9)

GMC3 GMC2 GMC1 GMC0 SELECTION

0

No Moni toring

0

1

Receiver 10

0

1

0

Receiver 11

0

1

Receiver 12

0

1

0

Receiver 13

0

1

0

1

Receiver 14

0

1

0

Receiver 15

0

1

Receiver 16

1

0

No Moni toring

1

0

1

Transmit ter 10

1

0

1

0

Transmit ter 11

1

0

1

Transmit ter 12

1

0

Transmit ter 13

1

0

1

Transmit ter 14

1

0

Transmit ter 15

1

Transmit ter 16

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Register Name:

DLBC

Register Descripti on:

Digital Loop ba c k Co ntr ol

Register A ddr es s (LI Us 1–8):

0Ch

Bit #

7

6

5

4

3

2

1

0

Name

DLBC8

DLBC7

DLBC6

DLBC5

DLBC4

DLBC3

DLBC2

DLBC1

Default

0

Register A ddr es s (LI Us 9–16):

2Ch

Bit #

7

6

5

4

3

2

1

0

Name

DLBC16

DLBC15

DLBC14

DLBC13

DLBC12

DLBC11

DLBC10

DLBC9

Default

0

Bits 7 to 0: Digital Loopback Control Channel n (DLBCn). When this bit is set the LIUn is placed in digital

loopbac k. The data at TPOS/TNEG is encoded and l ooped back t o the decoder and output on RPOS/RNEG. The

Ji tt er Attenuat or can optionally be incl uded in the tr ansmit or rec eiv e paths.

Register Name:

LASCS

Register Descripti on:

LOS/AIS Criteria Selection

Register A ddr es s (LI Us 1–8):

0Dh

Bit #

7

6

5

4

3

2

1

0

Name

LASCS8

LASCS7

LASCS6

LASCS5

LASCS4

LASCS3

LASCS2

LASCS1

Default

0

Register A ddr es s (LI Us 9–16):

2Dh

Bit #

7

6

5

4

3

2

1

0

Name

LASCS16

LASCS15

LASCS14

LASCS13

LASCS12

LASCS11

LASCS10

LASCS9

Default

0

Bits 7 to 0: LOS/AIS Criteria Selection Channel n (LASCSn). T hi s bi t is used for LOS /AIS sel ection c riteri a f or

LIUn. In E1 mode, if set it uses ETS 300 233 mode sel ec tions. If reset it uses G.775 c r iteria. In T 1/J1 mode T1. 231

criteria is selected.

Register Name:

ATAOS

Register Descripti on:

Automatic Transmit All Ones Select

Register A ddr es s (LI Us 1–8):

0Eh

Bit #

7

6

5

4

3

2

1

0

Name

ATAOS8

ATAOS7

ATAOS6

ATAOS5

ATAOS4

ATAOS3

ATAOS2

ATAOS1

Default

0

Register A ddr es s (LI Us 9–16):

2Eh

Bit #

7

6

5

4

3

2

1

0

Name

ATAOS16

ATAOS15

ATAOS14

ATAOS13

ATAOS12

ATAOS11

ATAOS10

ATAOS9

Default

0

Bits 7 to 0: Automatic Transmit All Ones Select Channel n (ATAOSn). When this bit is set all ones signal is

sent if an LOS is detected for LIUn. “All Ones Si gnal” uses MCLK as the reference cl oc k .

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Register Name:

GC

Register Description:

Global Configuration

Register A ddr es s (LI Us 1–8):

0Fh

Bit #

7

6

5

4

3

2

1

0

Name

RIMPMS

AISEL

SCPD

CODE

JADS

CRIMP

JAPS

JAE

Default

0

Note: CRIMP controls all 16 LIUs. All other bits are for LIUs 1–8 only.

Bit 7: Receive I mpedance Mode Sel ect (RIMPMS). W hen t his bi t i s set , fully int ernal im pedance m atch mode is

select ed, so RT IP and RRING requi re no ext ernal resistor. I f t hi s bit i s set, the r eceiver li ne transf orm er must be a

1:1 turns ratio and the RTR bit set. When reset, external termination mode is selected and an external resistor is

required to terminate the receive line. This external resistor will be adjusted internally to the correct termination

value if partially internal impedance matching is turned on (TS.R IM PON = 1) .

Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the system side upon detecting

LOS f or each channel . The indiv idual LIU register IAISEL setti ngs will be ignored when this bit i s set. W hen reset ,

the IAISEL register will hav e contr ol.

Bit 5: Short Ci rcuit Protection Disable (SCPD). If this bit is set the short-ci rcuit prot ection is disabled f or all the

transmitters. The individual LIU register ISCPD set ti ngs wi ll be ignored when thi s bit i s set . W hen reset, the ISCPD

regi ster will hav e c ontrol.

Bit 4: Code (CODE). If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored

when this bit is set. If reset, the LCS register will have control.

Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The

settings in the IJAFDS register will be ignor ed if this register is set. If reset the IJAFDS register will hav e c ontrol.

Bit 2: Calibrate Receive Internal Termination (CRIMP). A low-to-high transition on this bit initiates a calibration

cycle for the receive internal termination. This requires a 16kΩ ±1% resistor on the RESREF pin. Bit 2 of the GC

register at address 0x2F must also be set to enable calibration. While this bit is set, RSL4.4 (0x0F in individual

bank) will indicat e the stat us of the calibr ation cycl e.

Bit 1: Jitter Attenu ator Position S elect (JAPS). W hen the JAP S bit is set hi gh, the jitter attenuator wi ll be in the

receive path and when default or set low in t he Transm it path. T hese settings ca n be c hanged for an individual LI U

by settings i n the IJAPS register. Note t hat when bit J AE is set, the settings in the IJAPS r egister will be ignor ed.

Bit 0: Jit ter Attenu ator Enabl e (JAE). When thi s bit is set the jit ter att enuator is enabl ed. The settings i n the IJAE

regi ster will be ignor ed if this register is set. If r eset, the IJAE regi ster will hav e c ontrol.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register A ddr es s (LI Us 9–16):

2Fh

Bit #

7

6

5

4

3

2

1

0

Name

RIMPMS

AISEL

SCPD

CODE

JADS

CALEN

JAPS

JAE

Default

0

Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, the fully internal receive impedance

matching mode is selected, so RTIP and RRING require no external resistor. If this bit is set, the receiver line

transformer must be a 1:1 turns ratio and the RTR bit set. When reset and TS.RIMPON = 1, partially internal

receive impedance matching mode is selected and an external resistor is required to terminate the receive line.

This exter nal r esi stor will be adjusted int er nally to the correct termination value.

Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the system side upon detecting

LOS f or each channel . The indiv idual LIU register IAISEL setti ngs will be ignored when this bit i s set. W hen reset ,

the IAISEL register will hav e contr ol.

Bit 5: Short Ci rcuit Protection Disable (SCPD). If this bit is set the short-ci rcuit prot ection is disabled f or all the

transmitters. The individual LIU register ISCPD set ti ngs wi ll be ignored when thi s bit i s set . W hen reset, the ISCPD

regi ster will hav e c ontrol.

Bit 4: Code (CODE). If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored

when this bit is set. If reset, the LCS register will have control.

Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The

settings in the IJAFDS register will be ignor ed if this register is set. If reset the IJAFDS register will hav e c ontrol.

Bit 2: Calibrate Receive Impedance Match (CALEN). This bit must be set to enable calibration of the receive

term i nati on. If thi s bit is set and a 1 6kΩ resi stor i s on the RESREF pin, then a low-to-high tr ansition on t he CRIMP

bit will initiate a calibration cycle for the receive internal termination. The user should wait at least 5µs before

setting t he CRIMP bit.

Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set, the jitter attenuator will be in the

receiv e pat h for eac h channel . T he individual LI U r egister IJAPS setti ngs wi l l be i gnored when this bi t i s set . When

reset, the IJAPS register will have contr ol.

Bit 0: Jit ter Attenu ator Enabl e (JAE). W hen this bit i s set t he jitt er attenuat or is enabled. The setti ngs in the IJAE

regi ster will be ignor ed if this register is set. If r eset, the IJAE regi ster will hav e c ontrol.

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Register Name:

TST

Register Descripti on:

Template Select Transmitter

Register A ddr es s (LI Us 1–8):

10h

Bit #

7

6

5

4

3

2

1

0

Name

JABWS1

JABWS0

RHPMC

—

TST2

TST1

TST0

Default

0

Bits 7 and 6: Jit t er Atten uator Bandwidt h Selection [1:0] (JABWS[1:0] ) . In E 1 m ode, JABW S[1:0] is used to

contr ol the bandwidt h of the jitt er att enuator ac c or ding to t he following table:

JABWS

BANDWIDTH (Hz)

00

0.625

01

1.25

10

2.5

11

5

Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match

on/of f selec tion will be cont rolled by the OE pin. If OE is high, receiv e im pedance mat ch is on. If OE is l ow, receiv e

impedance match is off (Internal impedance to RTIP and RRING is high impedance). When this bit is reset, the

RIMP ON register bit will control receive impedance match.

Bits 2 t o 0: TST Templat e S elect Transceiver [2: 0] ( TST [ 2: 0] ). T ST[2:0] is used to sel ec t t he transceiver that t he

Transmit Template Select Register ( 0x 11) will c onfigure for LIUs 1–8. See Table 6-11.

Register A ddr es s (LI Us 9–16):

30h

Bit #

7

6

5

4

3

2

1

0

Name

JABWS1

JABWS0

RHPMC

—

TST2

TST1

TST0

Default

0

Bits 7 and 6: Jit t er Atten uator Bandwidt h Selection [1:0] (JABWS[1:0] ) . In E1 mode, JAB WS[1:0] is used to

contr ol the bandwidt h of the jitt er att enuator ac c or ding to t he following table:

JABWS

BANDWIDTH (Hz)

00

0.625

01

1.25

10

2.5

11

5

Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match

on/of f selec tion will be cont rolled by the OE pin. If OE is high, receiv e im pedance mat ch is on. If OE is l ow, receive

impedance match is off (internal impedance to RTIP and RRING is high impedance). When this bit is reset, the

RIMP ON register bit will control receive impedance match.

Bits 2 t o 0: TST Templat e S elect Transceiver [2: 0] ( TST [ 2: 0] ). T ST[2:0] is used to sel ec t t he transceiver that t he

Transmit Template Select Register ( 0x 11) will c onfigure for LIUs 9–16. See Table 6-12.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Table 6-11. TST Template Select Transmit ter Register (LIUs 1–8)

TST[2:0]

CHANNEL

TST[2:0]

CHANNEL

000

1

100

5

001

2

101

6

010

3

110

7

011

4

111

8

Table 6-12. TST Template Select Transmit ter Register (LIUs 9–16)

TST[2:0]

CHANNEL

TST[2:0]

CHANNEL

000

9

100

13

001

10

101

14

010

11

110

15

011

12

111

16

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

TS

Register Descripti on:

Templat e Select

Register A ddr es s (LI Us 1–8):

11h

Register A ddr es s (LI Us 9–16):

31h

Bit #

7

6

5

4

3

2

1

0

Name

RIMPON

TIMPOFF

—

TIMPRM

TS2

TS1

TS0

Default

0

Note: This register configures each LIU indi vi dually. This register c onfigures the LIU selected by TST.TST[2:0].

Bit 7: Receive Impedance Match On (RIMPON). If this bit is set, internal receive impedance matching is turned

on. O therwise, the receiver i s i n high impedanc e. Not e that the O E pin c an have c ontrol instead of this bit when the

TST.RHPMC bit is set.

Bit 6: Transmit Impedance Termination Off (TIMPOFF). If this bit is set all the internal transmit terminating

im pedanc e is tur ned off .

Bit 3: Transmit Impedance Receive Match (TIMPRM). This bit selects the internal transmit termination

impedance and receive impedance match for E1 mode and T1/J1 mode.

0 = 75Ω for E1 mode or 100Ω for T1 mode.

1 = 120Ω for E1 mode or 110Ω for J1 mode.

Bits 2 to 0: T emplate Selection [2:0] (T S[2:0]). Bits TS[2:0] are use d to sel ect E1 or T1/J1 mode, t he template,

and the sett ings f or vari ous cable lengt hs. The im pedance termi nati on for t he transmi tter and im pedanc e m atch f or

the rec eiver are specified by bit TIM P RM. See Table 6-13 for bit selec tion of TS [2: 0].

Table 6-13. Templ ate Sel ecti on

TEMPLATE SELECTION

TS[2:0] LINE LENGTH (ft)

CABLE LOSS

(dB)

IMPEDANCE (

Ω

)

011

0–133 ABAM

0.6

100/110

100

133–266 ABAM

1.2

100/110

101

266–399 ABAM

1.8

100/110

110

399–533 ABAM

2.4

100/110

111

533–655 ABAM

3.0

100/110

000

G. 703 c oaxi al and twisted pair cable

75/120

001 and 010

Reserved

—

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

OE

Register Descripti on:

Output Enable Configuration

Register A ddr es s (LI Us 1–8):

12h

Bit #

7

6

5

4

3

2

1

0

Name

OE8

OE7

OE6

OE5

OE4

OE3

OE2

OE1

Default

0

Register A ddr es s (LI Us 9–16):

32h

Bit #

7

6

5

4

3

2

1

0

Name

OE16

OE15

OE14

OE13

OE12

OE11

OE10

OE9

Default

0

Bits 7 to 0: Output Enable Channel n (OEn). When this bit is reset, the transmitter output for LIUn is high

impedance. When this bit is set, the transmitter output for LIUn is enabled. Note that the OE pin will override this

setting when low.

Register Name:

AIS

Register Description:

Alarm Indication Signal Status

Register A ddr es s (LI Us 1–8):

13h

Bit #

7

6

5

4

3

2

1

0

Name

AIS8

AIS7

AIS6

AIS5

AIS4

AIS3

AIS2

AIS1

Default

0

Register A ddr es s (LI Us 9–16):

33h

Bit #

7

6

5

4

3

2

1

0

Name

AIS16

AIS15

AIS14

AIS13

AIS12

AIS11

AIS10

AIS9

Default

0

Bits 7 to 0: Alarm Indication Signal Channel n (AISn). This bit will be set when AIS is detected f or LIUn. The

criteria for AIS selection is detailed in Section 5.5.7. The selection of the AIS criteria is done by settings in the

LASCS ( 0D) r egister .

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Register Name:

AISIE

Register Descripti on:

AIS Interrupt Enable

Register A ddr es s (LI Us 1–8):

14h

Bit #

7

6

5

4

3

2

1

0

Name

AISIE8

AISIE7

AISIE6

AISIE5

AISIE4

AISIE3

AISIE2

AISIE1

Default

0

Register A ddr es s (LI Us 9–16):

34h

Bit #

7

6

5

4

3

2

1

0

Name

AISIE16

AISIE15

AISIE14

AISIE13

AISIE12

AISIE11

AISIE10

AISIE9

Default

0

Bits 7 to 0: AIS In terrupt Mask Channel n (AISIEn). W hen this bit is set, i nterrupts can be generated for LIUn if

AIS status transi tions.

Register Name:

AISIS

Register Descripti on:

AI S I n terrupt Statu s

Register A ddr es s (LI Us 1–8):

15h

Bit #

7

6

5

4

3

2

1

0

Name

AISIS8

AISIS7

AISIS6

AISIS5

AISIS4

AISIS3

AISIS2

AISIS1

Default

0

Register A ddr es s (LI Us 9–16):

35h

Bit #

7

6

5

4

3

2

1

0

Name

AISIS16

AISIS15

AISIS14

AISIS13

AISIS12

AISIS11

AISIS10

AISIS9

Default

0

Bits 7 t o 0: AIS Interrupt Status Channel n (AISISn). This bit is set when AI S r ansi tions f r om a “ 0 to 1” or “ 1 to 0”

and int errupt s are enabled by the AISIE( 14) regi ster f or LI Un. If set, thi s bit is cl eared on a read oper ati on or when

the interrupt enabl e regi ster is di sabl ed.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

ADDP

Register Descripti on:

Address Po inter for Bank Selection

Register A ddr es s (LI Us 1–8):

1Fh

Register A ddr es s (LI Us 9–16):

3Fh

Bit #

7

6

5

4

3

2

1

0

Name

ADDP7

ADDP6

ADDP5

ADDP4

ADDP3

ADDP2

ADDP1

ADDP0

Default

0

Bits 7 t o 0: Address P oi nter (ADDP). This point er is used to s witch between poi nting to the primar y r egisters, the

secondary registers, individual registers, and BERT registers. See Table 6-14 for bank selection. The register

space contains control for Channels 1 to 8 from address 00 hex to 1F hex and a duplicate set of registers for

contr ol of Channel s 9 to 16 from addres s 20 hex to 3F hex . T he ADDP at address 1F hex select the bank s f or t he

set of regi sters f or LIUs 1–8. The ADDP regi ster at addres s 3F select the banks f or t he set of registers f or LIUs 9–

16.

Table 6-14. Address Pointer Bank Selection

ADDP[7:0] (HEX)

BANK NAME

00

Primary Bank

AA

Secondary B ank

01

Individual LIU Bank

02

BERT Bank

6.1.2 Secondary Register Bank

The ADDP r egister m ust be set to AAh in order to acc ess thi s bank.

Register Name:

SRMS

Register Descripti on:

Single-Rail Mode Sel ect

Register A ddr es s (LI Us 1–8):

00h

Bit #

7

6

5

4

3

2

1

0

Name

SRMS8

SRMS7

SRMS6

SRMS5

SRMS4

SRMS3

SRMS2

SRMS1

Default

0

Register A ddr es s (LI Us 9–16):

20h

Bit #

7

6

5

4

3

2

1

0

Name

SRMS16

SRMS15

SRMS14

SRMS13

SRMS12

SRMS11

SRMS10

SRMS9

Default

0

Bits 7 to 0: Single-Rail Mode Select Channel n (SRMSn). W hen thi s bi t is set si ngle-r ail mode is select ed for the

system transmit and receive n. If t his bi t is reset, dual-rail is selected.

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Register Name:

LCS

Register Descripti on:

Line Cod e S election

Register A ddr es s (LI Us 1–8):

01h

Bit #

7

6

5

4

3

2

1

0

Name

LCS8

LCS7

LCS6

LCS5

LCS4

LCS3

LCS2

LCS1

Default

0

Register A ddr es s (LI Us 9–16):

21h

Bit #

7

6

5

4

3

2

1

0

Name

LCS16

LCS15

LCS14

LCS13

LCS12

LCS11

LCS10

LCS9

Default

0

Bits 7 t o 0: Li ne Code Select Channel n (LCSn). When this bit is set AMI encodi ng/decoding is selected for LIUn.

If reset, B8ZS or HDB3 encodi ng/decodi ng is selected f or LIUn. Note that if the GC.CODE register bi t is set it will

ignor e this regi ster .

Register Name:

RPDE

Register Descripti on:

Receive Pow er-D own En a ble

Register A ddr es s (LI Us 1–8):

03h

Bit #

7

6

5

4

3

2

1

0

Name

RPDE8

RPDE7

RPDE6

RPDE5

RPDE4

RPDE3

RPDE2

RPDE1

Default

0

Register A ddr es s (LI Us 9–16):

23h

Bit #

7

6

5

4

3

2

1

0

Name

RPDE16

RPDE15

RPDE14

RPDE13

RPDE12

RPDE11

RPDE10

RPDE9

Default

0

Bits 7 to 0: Receive Power-Down Enable Channel n (RPDEn). When this bit is set the receiver for LIUn is

powered do wn.

Register Name:

TPDE

Register Descripti on:

Transmit Power-Down Enable

Register A ddr es s (LI Us 1–8):

04h

Bit #

7

6

5

4

3

2

1

0

Name

TPDE8

TPDE7

TPDE6

TPDE5

TPDE4

TPDE3

TPDE2

TPDE1

Default

0

Register A ddr es s (LI Us 9–16):

24h

Bit #

7

6

5

4

3

2

1

0

Name

TPDE16

TPDE15

TPDE14

TPDE13

TPDE12

TPDE11

TPDE10

TPDE9

Default

0

Bits 7 to 0: Transmit Power-Down Enable Channel n (TPDEn). W hen this bit is set the transmitter for LIUn is

powered do wn.

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Register Name:

EZDE

Register Descripti on:

Excessive Zero Det ect Enabl e

Register A ddr es s (LI Us 1–8):

05h

Bit #

7

6

5

4

3

2

1

0

Name

EZDE8

EZDE7

EZDE6

EZDE5

EZDE4

EZDE3

EZDE2

EZDE1

Default

0

Register A ddr es s (LI Us 9–16):

25h

Bit #

7

6

5

4

3

2

1

0

Name

EZDE16

EZDE15

EZDE14

EZDE13

EZDE12

EZDE11

EZDE10

EZDE9

Default

0

Bits 7 to 0: Excessive Zero Det ect Enabl e Channel n (EZDEn). When t his bit is reset exc essive zero detection is

disabled for LIUn. W hen this bit is set excessive zero detect enable is enabled. Excessive zero detection is only

rel ev ant when HDB3 or B8ZS decoding is enabled (LCS register).

Register Name:

CVDEB

Register Descripti on:

Cod e Viol at io n Detect Enabl e Bar

Register A ddr es s (LI Us 1–8):

06h

Bit #

7

6

5

4

3

2

1

0

Name

CVDEB8

CVDEB7

CVDEB6

CVDEB5

CVDEB4

CVDEB3

CVDEB2

CVDEB1

Default

0

Register A ddr es s (LI Us 9–16):

26h

Bit #

7

6

5

4

3

2

1

0

Name

CVDEB16

CVDEB15

CVDEB14

CVDEB13

CVDEB12

CVDEB11

CVDEB10

CVDEB9

Default

0

Bits 7 t o 0: Cod e Viol ation Detect E nable Bar Ch annel n (CVDEBn). If t his bit is set, c ode v iolati on detec tion is

disabled for the LIUn. If this bit is reset, code violation detection is enabled. Code violation detection is only

relev ant when HDB3 decodi ng is enabled (LCS register).

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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6.1.3 Individual LIU Register Bank

The ADDP r egister m ust be set to 01h to access thi s bank.

Register Name:

IJAE

Register Descripti on:

Individual Jitter Attenuator Enable

Register A ddr es s (LI Us 1–8):

00h

Bit #

7

6

5

4

3

2

1

0

Name

IJAE8

IJAE7

IJAE6

IJAE5

IJAE4

IJAE3

IJAE2

IJAE1

Default

0

Register A ddr es s (LI Us 9–16):

20h

Bit #

7

6

5

4

3

2

1

0

Name

IJAE16

IJAE15

IJAE14

IJAE13

IJAE12

IJAE11

IJAE10

IJAE9

Default

0

Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn). W hen t his bit i s set, t he LIU j itt er attenuat or

n is enabled. Not e that if the GC.JA E register bit i s set, this regi ster will be ignored.

Register Name:

IJAPS

Register Descripti on:

Indiv idua l Jit t e r A tt e nua tor P os i t i on S e le c t

Register A ddr es s (LI Us 1–8):

01h

Bit #

7

6

5

4

3

2

1

0

Name

IJAPS8

IJAPS7

IJAPS6

IJAPS5

IJAPS4

IJAPS3

IJAPS2

IJAPS1

Default

0

Register A ddr es s (LI Us 9–16):

21h

Bit #

7

6

5

4

3

2

1

0

Name

IJAPS16

IJAPS15

IJAPS14

IJAPS13

IJAPS12

IJAPS11

IJAPS10

IJAPS9

Default

0

Bits 7 t o 0: In dividu al Ji tter Atten uato r Position Select Chan nel n (IJAPSn). When t hi s bit is set hi gh, t he jit ter

attenuator is in the receive path n; when this bit is default or set low the jitter attenuator is in the transmit path n.

Note t hat if the GC.J A E regi ster bit is set, t his register will be ignored.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

IJAFDS

Register Descripti on:

Individual Jitter Attenuator FIFO Depth Select

Register A ddr es s (LI Us 1–8):

02h

Bit #

7

6

5

4

3

2

1

0

Name

IJAFDS8

IJAFDS7

IJAFDS6

IJAFDS5

IJAFDS4

IJAFDS3

IJAFDS2

IJAFDS1

Default

0

Register A ddr es s (LI Us 9–16):

22h

Bit #

7

6

5

4

3

2

1

0

Name

IJAFDS16

IJAFDS15

IJAFDS14

IJAFDS13

IJAFDS12

IJAFDS11

IJAFDS10

IJAFDS9

Default

0

Bits 7 to 0: Individual Jitter Attenuator FIFO Depth Select n (IJAFDSn). W hen this bi t is set f or LIUn the j itter

attenuator FIFO depth will be 128 bi ts. W hen reset the j itter at tenuator FIFO depth wil l be 32 bits. Not e that if t he

GC.IJAFDS register bit is set, t his register will be ignored.

Register Name:

IJAFLT

Register Descripti on:

Individual Jitter Attenuator FIFO Limit Trip

Register A ddr es s (LI Us 1–8):

03h

Bit #

7

6

5

4

3

2

1

0

Name

IJAFLT8

IJAFLT7

IJAFLT6

IJAFLT5

IJAFLT4

IJAFLT3

IJAFLT2

IJAFLT1

Default

0

Register A ddr es s (LI Us 9–16):

23h

Bit #

7

6

5

4

3

2

1

0

Name

IJAFLT16

IJAFLT15

IJAFLT14

IJAFLT13

IJAFLT12

IJAFLT11

IJAFLT10

IJAFLT9

Default

0

Bits 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn). Set when the jitter attenuator FIFO

reaches to wit hin 4 bits of its useful limit for transmitter n. This bi t will be clear ed when read.

Register Name:

ISCPD

Register Descripti on:

Individual Short-Circuit Protection Disable

Register A ddr es s (LI Us 1–8):

04h

Bit #

7

6

5

4

3

2

1

0

Name

ISCPD8

ISCPD7

ISCPD6

ISCPD5

ISCPD4

ISCPD3

ISCPD2

ISCPD1

Default

0

Register A ddr es s (LI Us 9–16):

24h

Bit #

7

6

5

4

3

2

1

0

Name

ISCPD16

ISCPD15

ISCPD14

ISCPD13

ISCPD12

ISCPD11

ISCPD10

ISCPD9

Default

0

Bits 7 to 0: Individual Short-Circuit Protection Disable n. (ISCPDn). When this bit is set the short-circuit

protec tion is disabled for the i ndiv idual t r ansmit ter n. Note t hat if the GC.SCPD register bit is set, t he setti ngs in this

regi ster will be ignor ed.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

IAISEL

Register Descripti on:

Individual AIS Select

Register A ddr es s (LI Us 1–8):

05h

Bit #

7

6

5

4

3

2

1

0

Name

IAISEL8

IAISEL7

IAISEL6

IAISEL5

IAISEL4

IAISEL3

IAISEL2

IAISEL1

Default

0

Register A ddr es s (LI Us 9–16):

25h

Bit #

7

6

5

4

3

2

1

0

Name

IAISEL16

IAISEL15

IAISEL14

IAISEL13

IAISEL12

IAISEL11

IAISEL10

IAISEL9

Default

0

Bits 7 to 0: Individual AIS Enable During Loss n (IAISELn). W hen this bit is set, individual AIS enable during

loss is enabled for the individual r ec eiver n, and AIS is sent to the system si de upon detect ion of an LOS. Note that

if t he GC.AISEL register bit is set, t he settings in thi s register will be ignor ed.

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Register Name:

MC

Register Descripti on:

Master Cl ock Select

Register A ddr es s:

06h

Bit #

7

6

5

4

3

2

1

0

Name

PCLKI1

PCLKI0

TECLKE

CLKAE

MPS1

MPS0

FREQS

PLLE

Default

0

Bits 7 and 6: PLL Clo ck Input [ 1: 0] (PCLKI[1:0] ) . Thes e bits select the input into to the PLL.

00: MCLK is used.

01: RCLK1 to 8 is used based on t he sel ec tion in register CCR.

10: RCLK9 to 16 is used based on the selecti on in r egister CCR.

11: Reserved.

Bit 5: T1/E1 Clock Enable (TECLKE). W hen this bit is set t he TECLK output is enabled. If not set T ECLK wil l be

disabl ed and the T E CLK output is a LOS output. TECLK requi r es PLLE to be set for correct f unc tionality.

Bit 4: Clo ck A En abl e (CLKAE). When t hi s bit is set the CLKA output is enabl ed. If not set CLKA wil l be disabled

and the CLKA output is a LOS output. CLK A requires PLLE to be set f or corr ec t f unctionalit y .

Bits 3 and 2: Master Period Select [1:0] (MPS[1:0]). These bits MPS[1:0] selects the external MCLK f requency

for the DS26324. See Table 6-15 for details. This register when written to will also controller functionality of

Channels 9 to 16.

Bit 1: Frequency Select (FREQS). In conjunction with MPS[1:0] selects the external MCLK frequency for the

DS26324. If this bit is set the external Master clock can be 1.544MHz or multiple thereof. If not set the external

m aster cl oc k c an be 2.048MHz or m ultiple ther eof. S ee Table 6-15 f or details. This register when wri tten to will also

controller functionality of Channels 9 to 16.

Bit 0: Phase Lock Loop Enable (PLLE). W hen this bit is set the phase lock loop is enabled. If not set MCLK will

be the applied input clock.

Table 6-15. DS26324 MCLK Selections

PLLE MPS1, MPS0

MCLK,

MHz ±50pp m

FREQS MODE

0

xx

1.544

x

T1

0

xx

2.048

x

E1

1

00

1.544

1

T1/ J 1 or E1

1

01

3.088

1

T1/ J 1 or E1

1

10

6.176

1

T1/ J 1 or E1

1

11

12.352

1

T1/ J 1 or E1

1

00

2.048

0

T1/ J 1 or E1

1

01

4.096

0

T1/ J 1 or E1

1

10

8.192

0

T1/ J 1 or E1

1

11

16.384

0

T1/ J 1 or E1

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

70 of 120

Register Name:

RSMM1

Register Descripti on:

Receive Sensi t ivity Monitor Mode 1

Register A ddr es s (LI Us 1–8):

08h

Bit #

7

6

5

4

3

2

1

0

Name

RTR2

C2RSM2

C2RSM1

C2RSM0

RTR1

C1RSM2

C1RSM1

C1RSM0

Default

0

Bit 7: Receiver T ransformer Turn s Ratio Channel 2 (RTR2). If thi s bit is set t he turns rat io is 1:1 on t he receiv er

side. T hi s bit shoul d be s et when a 1:1 rec eiv er transfor m er is used. Not e that in order to use f ull y i nternal receiv e

im pedanc e termi nation, a 1:1 transform er must be used and this bit must be set to 1.

Bits 6 to 4: Channel 2 Receive Sensitivity/Monitor Select [2:0] (C2RSM[2:0]). Bits C2RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver T ransformer Turn s Ratio Channel 1 (RTR1). If thi s bit is set t he turns rat io is 1:1 on t he receiv er

side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully internal

receive im pedanc e termination, a 1:1 transform er must be used and this bit must be set to 1.

Bits 2 to 0: Channel 1 Receive Sensitivity/Monitor Select [2:0] (C1RSM[2:0]). Bits C1RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Register A ddr es s (LI Us 9–16):

28h

Bit #

7

6

5

4

3

2

1

0

Name

RTR10

C10RSM2

C10RSM1

C10RSM0

RTR9

C9RSM2

C9RSM1

C9RSM0

Default

0

Bit 7: Receiver Transformer Turns Ratio Channel 10 (RTR10). If this bit is set the turns ratio is 1:1 on the

receiv er si de. This bit should be set when a 1:1 receiver t ransf ormer i s used. Note t hat in or der to use fully internal

receive impedanc e termi nation, a 1:1 transform er must be used and this bit must be set to 1.

Bits 6 t o 4: Channel 10 Receive S ensiti vity/Mon itor Select [ 2:0] (C10RS M[2:0] ). Bit s C10RSM[2: 0] ar e used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 9 (RTR9). If this bit is set the Turns Ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully

internal r ec eive impedance t erminati on, a 1:1 transf ormer m ust be used and this bit must be set to 1.

Bits 2 to 0: Channel 9 Receive Sensitivity/Monitor Select [2:0] (C9RSM[2:0]). Bits C9RSM[2:0] are used to

select the r ec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

71 of 120

Register Name:

RSMM2

Register Descripti on:

Receive Sensi t ivity Monitor Mode 2

Register A ddr es s (LI Us 1–8):

09h

Bit #

7

6

5

4

3

2

1

0

Name

RTR4

C4RSM2

C4RSM1

C4RSM0

RTR3

C3RSM2

C3RSM1

C3RSM0

Default

0

Bit 7: Receiver T ransformer Turn s Ratio Channel 4 (RTR4). If thi s bit is set t he turns rat io is 1:1 on t he receiv er

side. T hi s bit shoul d be s et when a 1:1 rec eiv er transfor m er is used. Not e that in order to use f ull y i nternal receiv e

im pedanc e termi nation, a 1:1 transform er must be used and this bit must be set to 1.

Bit 6 to 4: Channel 4 Receive Sensitivity/Monitor Select [2:0] (C4RSM[2:0]). Bits C4RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver T ransformer Turn s Ratio Channel 3 (RTR3). If thi s bit is set t he turns rat io is 1:1 on t he receiver

side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully internal

receive im pedanc e termination, a 1:1 transform er must be used and this bit must be set to 1.

Bit 2 to 0: Channel 3 Receive Sensitivity/Monitor Select [2:0] (C3RSM[2:0]). Bits C3RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Register A ddr es s (LI Us 9–16):

29h

Bit #

7

6

5

4

3

2

1

0

Name

RTR12

C12RSM2

C12RSM1

C12RSM0

RTR11

C11RSM2

C11RSM1

C11RSM0

Default

0

Bit 7: Receiver Transformer Turns Ratio Channel 12 (RTR12). If this bit is set the turns ratio is 1:1 on the

receiv er si de. This bit should be set when a 1:1 receiver t ransf ormer i s used. Note t hat in or der to use fully internal

receive im pedanc e termination, a 1:1 transform er must be used and this bit must be set to 1.

Bits 6 t o 4: Channel 12 Receive S ensiti vity/Mon itor Select [ 2:0] (C12RS M[2:0]). Bit s C12RSM[2: 0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 11 (RTR11). If this bit is set the rurns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully

internal r ec eive impedance t erminati on, a 1:1 transf ormer m ust be used and this bit must be set to 1.

Bits 2 t o 0: Channel 11 Receive S ensiti vity/Mon itor Select [ 2:0] (C11RS M[2:0] ). Bit s C11RSM[2: 0] ar e used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

72 of 120

Register Name:

RSMM3

Register Descripti on:

Receive Sensi t ivity Monitor Mode 3

Register A ddr es s (LI Us 1–8):

0Ah

Bit #

7

6

5

4

3

2

1

0

Name

RTR6

C6RSM2

C6RSM1

C6RSM0

RTR5

C5RSM2

C5RSM1

C5RSM0

Default

0

Bit 7: Receiver T ransformer Turn s Ratio Channel 6 (RTR6). If thi s bit is set the t urns rati o is 1:1 on the receiv er

side. T hi s bit shoul d be s et when a 1:1 rec eiv er transfor m er is used. Not e that in order to use f ull y i nternal receiv e

im pedanc e termi nation, a 1:1 transform er must be used and this bit must be set to 1.

Bits 6 to 4: Channel 6 Receive Sensitivity/Monitor Select [2:0] (C6RSM[2:0]). Bits C6RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver T ransformer Turn s Ratio Channel 5 (RTR5). If thi s bit is set t he turns rat io is 1:1 on t he receiv er

side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully internal

receive impedance termi nation, a 1:1 transform er must be used and this bi t must be set to 1.

Bits 2 to 0: Channel 5 Receive Sensitivity/Monitor Select [2:0] (C5RSM[2:0]). Bits C5RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Register A ddr es s (LI Us 9–16):

2Ah

Bit #

7

6

5

4

3

2

1

0

Name

RTR14

C14RSM2

C14RSM1

C14RSM0

RTR13

C13RSM2

C13RSM1

C13RSM0

Default

0

Bit 7: Receiver Transformer Turns Ratio Channel 14 (RTR14). If this bit is set the turns ratio is 1:1 on the

receiv er si de. This bit should be set when a 1:1 receiver t ransf ormer i s used. Note t hat in or der to use fully internal

receive im pedanc e termination, a 1:1 transform er must be used and this bit must be set to 1.

Bits 6 t o 4: Channel 14 Receive S ensiti vity/Mon itor Select [ 2:0] (C14RS M[2:0] ). Bit s C14RSM[2: 0] ar e used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 13 (RTR13). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully

internal r ec eive impedance t erminati on, a 1:1 transformer m ust be used and this bi t must be set to 1.

Bits 2 t o 0: Channel 13 Receive S ensiti vity/Mon itor Select [ 2:0] (C13RS M[2:0] ). Bit s C13RSM[2: 0] ar e used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

73 of 120

Register Name:

RSMM4

Register Descripti on:

Receive Sensi t ivity Monitor Mode 4

Register A ddr es s (LI Us 1–8):

0Bh

Bit #

7

6

5

4

3

2

1

0

Name

RTR8

C8RSM2

C8RSM1

C8RSM0

RTR7

C7RSM2

C7RSM1

C7RSM0

Default

0

Bit 7: Receiver T ransformer Turn s Ratio Channel 8 (RTR8). If thi s bit is set t he turns rat io is 1:1 on t he receiv er

side. T hi s bit shoul d be s et when a 1:1 rec eiv er transfor m er is used. Not e that in order to use f ull y i nternal receiv e

im pedanc e termi nation, a 1:1 transform er must be used and this bit must be set to 1.

Bits 6 to 4: Channel 8 Receive Sensitivity/Monitor Select [2:0] (C8RSM[2:0]). Bits C8RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver T ransformer Turn s Ratio Channel 7 (RTR7). If thi s bit is set t he turns rat io is 1:1 on t he receiv er

side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully internal

receive im pedanc e termination, a 1:1 transform er must be used and this bit must be set to 1.

Bits 2 to 0: Channel 7 Receive Sensitivity/Monitor Select [2:0] (C7RSM[2:0]). Bits C7RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Register A ddr es s (LI Us 9–16):

2Bh

Bit #

7

6

5

4

3

2

1

0

Name

RTR16

C16RSM2

C16RSM1

C16RSM0

RTR15

C15RSM2

C15RSM1

C15RSM0

Default

0

Bit 7: Receiver Transformer Turns Ratio Channel 16 (RTR16). If this bit is set the turns ratio is 1:1 on the

receiv er si de. This bit should be set when a 1:1 receiver t ransf ormer i s used. Note t hat in order to use fully internal

receive im pedanc e termination, a 1:1 transform er must be used and this bit must be set to 1.

Bit 6 to 4: Channel 16 Receive Sensi tivity/ Monitor Select [2:0] (C16RSM[2:0]). Bits C16RSM[2:0] are used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Bit 3: Receiver Transformer Turns Ratio Channel 15 (RTR15). If this bit is set the turns ratio is 1:1 on the

receiver side. This bit should be set when a 1:1 receiver transformer is used. Note that in order to use the fully

internal r ec eive impedance t erminati on, a 1:1 transf ormer m ust be used and this bit must be set to 1.

Bits 2 t o 0: Channel 15 Receive S ensiti vity/Mon itor Select [2:0] (C15RSM[2:0]). Bits C15RSM[2: 0] ar e used to

select the rec eiv er sensit ivity lev el and the monitor m ode resistive gain. See Table 6-16.

Table 6-16. Receiver Sensitivity/Monitor Mode Gain Selection

RECEIVER

MONITOR

MODE

DISABLED

CnRSM[2:0],

T1/ E1 M ODE

RECEIVER

SENSITIVITY

(MAXIMUM

LOSS)

(dB)

RECEIVER

MONITOR

MODE GAIN

SETTINGS

(dB)

LOSS

DECLARATION

LEVEL

(dB)

No flat gain

000

12

0

15

No flat gain

001

18

0

21

Receiver

monitor mode

enabled CnRSM[2:0] Max cable loss Receiver

monitor mode

gain settings —

Flat gai n

100

30

14

37

Flat gai n

101

22.5

20

45.5

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

74 of 120

Register Name:

RSL1

Register Descripti on:

Receive Signal Level Indicator 1

Register A ddr es s (LI Us 1–8):

0Ch

Bit #

7

6

5

4

3

2

1

0

Name

C2RSL3

C2RSL2

C2RSL1

C2RSL0

C1RSL3

C1RSL2

C1RSL1

C1RSL0

Default

0

Bits 7 to 4: Channel 2 Receive Signal Level [3:0] (C2RSL[3:0]). C2RSL[3:0] bits provide the receive signal

lLevel as shown in Table 6-17.

Bits 3 to 0: Chann el 1 Receive Signal Level [3:0] (C1RSL[3:0] ). C1RSL[3: 0] bits provi de the receiv e si gnal level

as shown in Table 6-17.

Register Addres s (LI Us 9–16):

2Ch

Bit #

7

6

5

4

3

2

1

0

Name

C10RSL3

C10RSL2

C10RSL1

C10RSL0

C9RSL3

C9RSL2

C9RSL1

C9RSL0

Default

0

Bits 7 to 4: Channel 10 Receive Sig nal Level [3:0] (C10RSL[3:0]). C10RSL[3:0] bits provi de the receiv e signal

level as shown in Table 6-17.

Bits 3 to 0: Chann el 9 Receive Signal Level [3:0] (C9RSL[3:0] ). C9RSL[3: 0] bits provi de the receiv e si gnal level

as shown in Table 6-17.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

75 of 120

Table 6-17. Receiver Signal Level

CnRSL3 to

CnRSL0

RECEIVE L EVEL (dB)

T1

E1

0000

>-2.5

0001

-2.5 t o -5

0010

-5 to -7.5

0011

-7.5 t o -10

0100

-10 to -12.5

0101

-12.5 t o -15

0110

-15 to -17.5

0111

-17.5 t o -20

-17.5 t o –20

Register Name:

RSL2

Register Descripti on:

Receive Signal Level Indicator 2

Register A ddr es s (LI Us 1–8):

0Dh

Bit #

7

6

5

4

3

2

1

0

Name

C4RSL3

C4RSL2

C4RSL1

C4RSL0

C3RSL3

C3RSL2

C3RSL1

C3RSL0

Default

0

Bits 7 to 4: Chann el 4 Receive Signal Level [3:0] (C4RSL[3:0] ). C4RSL[3: 0] bits provi de the receiv e si gnal level

as shown in Table 6-17.

Bits 3 to 0: Chann el 3 Receive Signal Level [3:0] (C3RSL[3:0] ). C3RSL[3: 0] bits provi de the receiv e si gnal level

as shown in Table 6-17.

Register A ddr es s (LI Us 9–16):

2Dh

Bit #

7

6

5

4

3

2

1

0

Name

C12RSL3

C12RSL2

C12RSL1

C12RSL0

C11RSL3

C11RSL2

C11RSL1

C11RSL0

Default

0

Bits 7 to 4: Channel 12 Receive Sig nal Level [3:0] (C12RSL[3:0]). C12RSL[3:0] bits provi de the receiv e signal

lev el as shown in Table 6-17.

Bits 3 to 0: Channel 11 Receive Sig nal Level [3:0] (C11RSL[3:0]). C11RSL[3:0] bits provi de the receiv e signal

lev el as shown in Table 6-17.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

76 of 120

Register Name:

RSL3

Register Descripti on:

Receive Signal Level Indicator 3

Register A ddr es s (LI Us 1–8):

0Eh

Bit #

7

6

5

4

3

2

1

0

Name

C6RSL3

C6RSL2

C6RSL1

C6RSL0

C5RSL3

C5RSL2

C5RSL1

C5RSL0

Default

0

Bits 7 to 4: Chann el 6 Receive Signal Level [3:0] (C6RSL[3:0]). C6RSL[ 3:0] bit s prov i de t he receiv e signal lev el

as shown in Table 6-17.

Bits 3 to 0: Chann el 5 Receive Signal Level [3:0] (C5RSL[3:0] ). C5RSL[3: 0] bits provi de the receiv e si gnal level

as shown in Table 6-17.

Register A ddr es s (LI Us 9–16):

2Eh

Bit #

7

6

5

4

3

2

1

0

Name

C14RSL3

C14RSL2

C14RSL1

C14RSL0

C13RSL3

C13RSL2

C13RSL1

C13RSL0

Default

0

Bits 7 to 4: Channel 14 Receive Sig nal Level [3:0] (C14RSL[3:0]). C14RSL[3:0] bits prov ide the receiv e signal

lev el as shown in Table 6-17.

Bits 3 to 0: Channel 13 Receive Sig nal Level [3:0] (C13RSL[3:0]). C13RSL[3:0] bits provi de the receiv e signal

lev el as shown in Table 6-17.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

77 of 120

Register Name:

RSL4

Register Descripti on:

Receive Signal Level Indicator 4

Register A ddr es s (LI Us 1–8):

0Fh

Bit #

7

6

5

4

3

2

1

0

Name

C8RSL3 C8RSL2 C8RSL1

C8RSL0/

CALSTAT C7RSL3 C7RSL2 C7RSL1 C7RSL0

Default

0

Bits 7 to 4: Chann el 8 Receive Signal Level [3:0] (C8RSL[3:0] ). C8RSL[3: 0] bits provi de the receiv e si gnal level

as shown in Table 6-17.

Bit 4: Channel 8 Receive Signal Level 0/Calibration Status (C8RSL0/CALSTAT). When CRIMP is high,

C8RSL0 will be replaced by a real -tim e st atus bit f or the receiv e i nternal t erminati on calibrat ion circuit. If the bit i s

low, this indicates that the calibration has not com pleted. If the bit is high, t his indi cates the cal ibration completed

successfully. Normally this bit should go high within 7µs of the low-to-high transition of the CRIMP bit. Receive

term ination values will be updated subsequently.

Bits 3 to 0: Chann el 7 Receive Signal Level [3:0] (C7RSL[3: 0]). C7RSL[3: 0] bits provi de the receiv e si gnal level

as shown in Table 6-17.

Register A ddr es s (LI Us 9–16):

2Fh

Bit #

7

6

5

4

3

2

1

0

Name

C16RSL3

C16RSL2

C16RSL1

C16RSL0

C15RSL3

C15RSL2

C15RSL1

C15RSL0

Default

0

Bits 7 to 4: Channel 16 Receive Sig nal Level [3:0] (C16RSL[3:0]). C16RSL[3:0] bits provi de the receiv e signal

lev el as shown in Table 6-17.

Bits 3 to 0: Channel 15 Receive Sig nal Level [3:0] (C15RSL[3:0]). C15RSL[3:0] bits provi de the receiv e signal

lev el as shown in Table 6-17.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

78 of 120

Register Name:

BTCR

Register Description:

Bit E rror Rate Tester Con t rol

Register A ddr es s (LI Us 1–8):

10h

Bit #

7

6

5

4

3

2

1

0

Name

BTS2

BTS1

BTS0

—

BERTE

Default

0

Note: This register enables the LIU1-LIU8 BERT. The BERT can only connect to one LIU at a time. The LIU1-LIU8 BERT operates

independently of the LIU9-LIU16 BERT.

Bits 7 t o 5: Bit Error Rate Tran sceiver Sel ect [ 2: 0] (BTS [ 2: 0] ) . These bits BT S [2:0] selec t the LIU t hat t he BERT

applies to ( see Table 6-18). This is only applicable if t he BERT E bit is set.

Bit 0: Bit Error Rate Tester Enabl e (BERT E). W hen thi s bit i s set and 2µs hav e past, the BERT will be enabled.

The BE RT r egister set should be written and r ead to only after bei ng enabled. The BERT is only active f or one LI U

at a time selected by BTS[2:0]. This bit also forces the part into single-rail mode with HDB3/B8ZS encoding

enabled.

Register A ddr es s (LI Us 9–16):

30h

Bit #

7

6

5

4

3

2

1

0

Name

BTS2

BTS1

BTS0

—

BERTE

Default

0

Note: This register enables the LIU9-LIU 16 B ER T. T he BER T can on ly c onnec t to on e L IU at a tim e. T he L IU 9-LIU16 BERT operates

independently of the LIU1–LIU8 BERT.

Bits 7 t o 5: Bit Error Rat e Tran sceiver S elect [ 2:0] (BTS [2:0]) T hese bit s BTS[2:0] select the LI U that the BERT

applies too ( see Table 6-19). Thi s is only applicable if the BERTE bit is set.

Bit 0: Bit Error Rate Tester Enabl e (BERT E). W hen thi s bit i s set and 2µs hav e past, the BERT will be enabled.

The BE RT r egister set should be written and r ead to only after bei ng enabled. The BERT is only activ e f or one LI U

at a time selected by BTS[2:0]. This bit also forces the part into single-rail mode with HDB3/B8ZS encoding

enabled.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

79 of 120

Table 6-18. Bit Error Rate Transceiver Select for Channels 1–8

REGISTER

ADDRESS

BTS2 BTS1 BTS0

CHANNEL BERT

A PPLIES TO

10h

0

Channel 1

10h

0

Channel 2

10h

0

1

0

Channel 3

10h

0

1

Channel 4

10h

1

0

Channel 5

10h

1

0

1

Channel 6

10h

1

0

Channel 7

10h

1

Channel 8

Table 6-19. Bit Error Rate Transceiver Select for Channels 9–16

REGISTER

ADDRESS

BTS2 BTS1 BTS0

CHANNEL BERT

A PPLIES TO

30h

0

Channel 9

30h

0

Channel 10

30h

0

1

0

Channel 11

30h

0

1

Channel 12

30h

1

0

Channel 13

30h

1

0

1

Channel 14

30h

1

0

Channel 15

30h

1

Channel 16

Register Name:

BEIR

Register Descripti on:

BPV Error Insertion

Register A ddr es s (LI Us 1–8):

11h

Bit #

7

6

5

4

3

2

1

0

Name

BEIR8

BEIR7

BEIR6

BEIR5

BEIR4

BEIR3

BEIR2

BEIR1

Default

0

Register A ddr es s (LI Us 9–16):

31h

Bit #

7

6

5

4

3

2

1

0

Name

BEIR16

BEIR15

BEIR14

BEIR13

BEIR12

BEIR11

BEIR10

BEIR9

Default

0

Bits 7 to 0: BPV Error Insertion Register n (BEIRn). A 0-to-1 transition on this bit will cause a single bipolar

v iolati on (BPV) to be inserted int o the transmi t data stream Channel n. Thi s bi t must be cleared and set agai n f or a

subsequent er r or to be inserted. This i s only applicable in single-ra il mode.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

LVDS

Register Descripti on:

Line V io lation Det ect Status

Register A ddr es s (LI Us 1–8):

12h

Bit #

7

6

5

4

3

2

1

0

Name

LVDS8

LVDS7

LVDS6

LVDS5

LVDS4

LVDS3

LVDS2

LVDS1

Default

0

Register A ddr es s (LI Us 9–16):

32h

Bit #

7

6

5

4

3

2

1

0

Name

LVDS16

LVDS15

LVDS14

LVDS13

LVDS12

LVDS11

LVDS10

LVDS9

Default

0

Bits 7 t o 0: L in e Viol ation Detect Statu s n (LVDSn). A bi polar v i ol ation, a code v i olati on, or ex cessive zeros will

cause the associated LVDSn bit to latch. Thi s bit wi ll be cleared on a read operation. The LVDS register capture s

the first violation within a three clock period window. If a second violation occurs af ter the first violation within the

three clock period window, then the second violation will not be latched even if a read to the LVDS register was

performed. Excessive z er os need to be e nabled by the EZDE r egister for detecti on by this register . Code violations

are only relevant when in HDB3 mode and can be disabled for detection by this register by setting the CVDEB

register.

Register Name:

RCLKI

Register Descripti on:

Receive Cl ock Invert

Register A ddr es s (LI Us 1–8):

13h

Bit #

7

6

5

4

3

2

1

0

Name

RCLKI8

RCLKI7

RCLKI6

RCLKI5

RCLKI4

RCLKI3

RCLKI2

RCLKI1

Default

0

Register A ddr es s (LI Us 9–16):

33h

Bit #

7

6

5

4

3

2

1

0

Name

RCLKI16

RCLKI15

RCLKI14

RCLKI13

RCLKI12

RCLKI11

RCLKI10

RCLKI9

Default

0

Bit 7 t o 0: Recei ve Clo ck In vert n (RCLKIn). W hen thi s bit is set the RCLK for Channel n is inv ert ed. Thi s ali gns

RPOS/RNEG on the falling edge of RCLK. When reset or default RPOS/RNEG is aligned on the rising edge of

RCLK.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

TCLKI

Register Description:

Transmit Clock Invert

Register A ddr es s (LI Us 1–8):

14h

Bit #

7

6

5

4

3

2

1

0

Name

TCLKI8

TCLKI7

TCLKI6

TCLKI5

TCLKI4

TCLKI3

TCLKI2

TCLKI1

Default

0

Register A ddr es s (LI Us 9–16):

34h

Bit #

7

6

5

4

3

2

1

0

Name

TCLKI16

TCLKI15

TCLKI14

TCLKI13

TCLKI12

TCLKI11

TCLKI10

TCLKI9

Default

0

Bits 7 t o 0: T ransmi t Clock I nvert n (TCLKIn). W hen thi s bit i s set t he ex pect ed TCLK f or Channel n i s inv er ted .

TPOS/T NEG should be ali gned on the falli ng edge of TCLK. When reset or def ault TPOS/T NEG should be aligned

on the risi ng edge of T CLK.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

CCR

Register Descripti on:

Clo ck Con t rol

Register A ddr es s:

15h

Bit #

7

6

5

4

3

2

1

0

Name

PCLKS2

PCLKS1

PCLKS0

TECLKS

CLKA3

CLKA2

CLKA1

CLKA0

Default

0

Bits 7 t o 5: P LL Clo ck S elect ( P CLKS[2:0]). T hese bi ts determine t he RCLK that is to be used as the input to the

PLL. If an LOS is detec t f or the channel that RCLK is recov ered f rom, the PLL will swi tc h to MCLK until t he LOS is

cl eared. W hen the LOS is cleared RCLK will be used again. See Table 6-20 for RCLK selection. MC.PCLKI[1:0]

m ust be set to ‘01’ or ‘10’ in or der for these settings to take effect.

Table 6-20. PLL Clock Select

PCLKS[2:0]

PLL CLOCK

SELECTED

MC.PCLKI[1:0]=01

PLL CLOCK

SELECTED

MC.PCLKI[1:0]=10

000

RCLK1

RCLK9

001

RCLK2

RCLK10

010

RCLK3

RCLK11

011

RCLK4

RCLK12

100

RCLK5

RCLK13

101

RCLK6

RCLK14

110

RCLK7

RCLK15

111

RCLK8

RCLK16

Bit 4: T1/E1 Clock Select (TECLKS). When this bit is set the T1/E1 clock output is 2.048MHz. When this bit is

reset the T1/ E 1 clock r ate is 1.544MHz

Bits 3 t o 0: Clock A Select (CL KA[3:0]). These bit s sel ect the output frequency f or CLKA pi n. See Table 6-21 for

available frequencies. For best jitter performance, select MCLK as the source for CLKA and input a 2.048MHz

MCLK.

Table 6-21. Clock A Select

CLKA[3:0]

CLKA (Hz)

0000

2.048M

0001

4.096M

0010

8.192M

0011

16.384M

0100

1.544M

0101

3.088M

0110

6.176M

0111

12.352M

1000

1.536M

1001

3.072M

1010

6.144M

1011

12.288M

1100

32k

1101

64k

1110

128k

1111

256k

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

RDULR

Register Descripti on:

RCLK Di sabl e Upon LO S

Register A ddr es s (LI Us 1–8):

16h

Bit #

7

6

5

4

3

2

1

0

Name

RDULR8

RDULR7

RDULR6

RDULR5

RDULR4

RDULR3

RDULR2

RDULR1

Default

0

Register A ddr es s (LI Us 9–16):

36h

Bit #

7

6

5

4

3

2

1

0

Name

RDULR16

RDULR15

RDULR14

RDULR13

RDULR12

RDULR11

RDULR10

RDULR9

Default

0

Bits 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLK for Channel n is

disabled upon a loss of signal and set as a low output. When reset or default RCLK will switch to MCLK upon a

loss of si gnal within 10ms.

Register Name:

GISC

Register Descripti on:

Global Interrupt Status Control

Register A ddr es s:

1Eh

Bit #

7

6

5

4

3

2

1

0

Name

—

INTM

CWE

Default

0

Bit 1: INT Pin Mode (INTM). Thi s bi t determi nes t he inactive mode of t he INT pin. The INT pin always driv es l ow

when active.

0 = Pi n is hi gh im pedanc e when not active.

1 = Pi n drives high when not active.

Bit 0: Clear O n Writ e Enab le ( CWE). W hen t his bi t i s set t he cl ear on wri te i s enabled f or all t he lat ched i nterrupt

status registers. The host processor must write a 1 to the latched interrupt status register bit position before the

partic ular bit will be cleared. Def ault f or all the lat c hed interr upt status registers i s to cl ear on a r ead.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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6.1.4 BERT Re gisters

Register Name:

BCR

Register Descripti on:

BERT Control

Register A ddr es s (LI Us 1–8):

00h

Register A ddr es s (LI Us 9–16):

20h

Bit #

7

6

5

4

3

2

1

0

Name

PMUM

LPMU

RNPL

RPIC

MPR

APRD

TNPL

TPIC

Default

0

Bit 7: Performance Monitoring Update Mode (PM UM). When 0, a perf orm ance m onit oring updat e i s i ni tiated by

the LPM U r egister bit . When 1, a per formance monitoring update is init iated by t he r ec eive perform anc e m onitoring

update signal (RPMU). Note: If RPMU or LPMU is one, changing the state of this bit may cause a performance

m onitoring update to occur.

Bit 6: Local Performance Monitoring Update (LPMU). This bit causes a performance monitoring update to be

initiated if local perform anc e m onitoring updat e is enab led (P M UM = 0). A 0-to-1 tr ansi tion causes the per f ormance

m oni toring regi st ers t o be updated with t he latest dat a, and the count ers reset (0 or 1). For a second perf ormanc e

monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit

goes high, an update might not be performed. This bit has no affect when PMUM = 1.

Bit 5: Receive New Pattern Load (RNPL). A 0-to-1 transition of this bit will cause the programmed test pattern

(QRS S, PTS, P LF[4:0], PTF[4:0], and BSP[31: 0]) to be l oaded i n to the receiv e patt ern generat or. T his bit must be

changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces the receive

pattern generator out of the “Sync” state which causes a resynchronization to be initiated. Note: QRSS, PTS,

PLF[4:0], PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four RXCK

cl oc k cycl es after this bit transiti ons fr om 0 to 1.

Bit 4: Receive Pat t ern Inversi on Cont rol ( RP IC). W hen 0, t he r ec eive incomi ng data stream is not alt er ed. When

1, t he r ec eiv e inc omi ng data stream is inverted.

Bit 3: M anu al Patt ern Resyn chronization (MPR). A zero t o one transition of this bit will cause the r ec eive pat tern

generator to resynchroni ze to the i ncoming pattern. This bit m ust be changed to zero and back to one f or another

resynchroni zati on to be initi ated. Note: A manual resynchroni zation forces the rec eive pattern generator out of the

“Sync” st ate.

Bit 2: Automatic Pattern Resynchronization Disable (APRD). When 0, the receive pattern generator will

automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the

incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern

generator will not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is

prevented by not al lowing the receiv e patt er n gener ator to aut om atically exit the “Sync” state.

Bit 1: Transmit New Pattern Load (TNPL). A 0-to-1 transition of this bit will cause the programmed test pattern

(QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be l oaded in t o the tr ansmit patt er n gener ator. This bi t must be

changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0], PTF[4:0], and

BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TXCK clock cycles after this bit

transi tions from 0 to 1.

Bit 0: Transmit Pattern Inversion Control (TPIC). When 0, the transmit outgoing data stream is not altered.

When 1, the transmit outgoing data str eam is i nv erted.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

BPCR1

Register Description:

BERT P at t ern Conf igurat ion Regi st er 1

Register A ddr es s (LI Us 1–8):

02h

Register A ddr es s (LI Us 9–16):

22h

Bit #

7

6

5

4

3

2

1

0

Name

—

QRSS

PTS

PLF4

PLF3

PLF2

PLF1

PLF0

Default

0

Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and

PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a

generati ng pol ynomi al of x20 + x17 + 1. The output of the pat tern gener ator wil l be for ced to one if the nex t fourteen

output bits are all z er o.

Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive

pattern.

Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These five bits control the “length” feedback of the pattern

generator . The “l ength” feedback wil l be f rom bit n of the patt ern generator (n = PLF[4: 0] +1). For a PRBS signal ,

the f eedbac k is an XOR of bit n and bit y. For a r epetit ive patt er n the f eedbac k is bi t n.

Register Name:

BPCR2

Register Descripti on:

BERT P at t ern Conf igurat ion Regi st er 2

Register A ddr es s (LI Us 1–8):

03h

Register A ddr es s (LI Us 9–16):

23h

Bit #

7

6

5

4

3

2

1

0

Name

—

PTF4

PTF3

PTF2

PTF1

PTF0

Default

0

Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS “tap” feedback of the pattern

generator . The “tap” feedback wil l be from bi t y of the patt ern generator (y = PTF[ 4:0] +1). These bit s are ignored

when programmed for a repetitive pattern. F or a PRBS signal, the feedback is an XOR of bit n and bit y.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

BSPR1

Register Descripti on:

BERT S eed/ P at t ern Reg ister 1

Register A ddr es s (LI Us 1–8):

04h

Register A ddr es s (LI Us 9–16):

24h

Bit #

7

6

5

4

3

2

1

0

Name

BSP7

BSP6

BSP5

BSP4

BSP3

BSP2

BSP1

BSP0

Default

0

Register Name:

BSPR2

Register Descripti on:

BERT S eed/ P at t ern Reg ister 2

Register A ddr es s (LI Us 1–8):

05h

Register A ddr es s (LI Us 9–16):

25h

Bit #

7

6

5

4

3

2

1

0

Name

BSP15

BSP14

BSP13

BSP12

BSP11

BSP10

BSP9

BSP8

Default

0

Register Name:

BSPR3

Register Descripti on:

BERT S eed/ P at t ern Reg ister 3

Register A ddr es s (LI Us 1–8):

06h

Register A ddr es s (LI Us 9–16):

26h

Bit #

7

6

5

4

3

2

1

0

Name

BSP23

BSP22

BSP21

BSP20

BSP19

BSP18

BSP17

BSP16

Default

0

Register Name:

BSPR4

Register Descripti on:

BERT S eed/ P at t ern Reg ister 4

Register A ddr es s (LI Us 1–8):

07h

Register A ddr es s (LI Us 9–16):

27h

Bit #

7

6

5

4

3

2

1

0

Name

BSP31

BSP30

BSP29

BSP28

BSP27

BSP26

BSP25

BSP24

Default

0

Bits 31 to 0: BERT Seed/Pattern (BSP[31:0]). These 32 bits are the programmable seed for a transmit PRBS

patt ern, or the progr amm abl e patt ern for a transm it or receiv e repet itiv e pat tern. BS P(31) will be t he f i rst bit out put

on the transmit side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) will be the first bit input on the

receive si de for a 32-b it repetitive pattern.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

TEICR

Register Descripti on:

Transmit Error In sert io n Cont rol Register

Register A ddr es s (LI Us 1–8):

08h

Register A ddr es s (LI Us 9–16):

28h

Bit #

7

6

5

4

3

2

1

0

Name

—

TEIR2

TEIR1

TEIR0

BEI

TSEI

MEIMS

Default

0

Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]). These three bits indicate the rate at which errors are

insert ed in the output dat a stream. O ne out of ever y 10n bits i s i nver ted. TEIR[2:0] is the value n. A TEIR[2:0] v alue

of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A

TEIR[2:0] value of 2 result in every 100th bit being inverted. Error insertion starts when this register is written to

with a TEIR[2:0] value that is nonzero. If this register is written to during the middle of an error insertion process,

the new error rate will be start ed aft er the next err or is inserted.

Bit 2: Bit Error Insertion Enable (BEI). When 0, single bit error insertion is disabled. When 1, single bit error

insertion is enabled.

Bit 1: T ran smit Sing le Erro r Insert (T SEI) . T his bi t causes a bi t err or to be i nserted i n the t ransm it dat a stream if

manual er r or insert ion is disabl ed ( M E IMS = 0) and si ngle bit er r or insert ion is enabl ed. A 0 to 1 tr ansi tion cause s a

singl e bit err or to be i nserted. F or a second bi t error to be inserted, this bit must be set t o 0, and back to 1. Note: If

MEIMS is low, and this bit transitions more t han once between error i nsertion opportuni ties, only one error will be

inserted.

Bit 0: Manual Error Insert Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit.

When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is

one, changing the state of t his bit m ay cause a bit err or to be insert ed.

Register Name:

BSR

Register Descripti on:

BERT S t atus

Register A ddr es s (LI Us 1–8):

0Ch

Register Addres s (LI Us 9–16):

2Ch

Bit #

7

6

5

4

3

2

1

0

Name

—

PMS

—

BEC

OOS

Default

0

Bit 3: Performance Monitoring Update Status (PMS). This bit indicates the status of the receive performance

m onitoring r egister ( c ounters) updat e. T his bit will transi tion fr om low to high when the up date i s completed. PMS is

asynchrono usl y forced low when the LPM U bit (PMUM = 0) or RPMU signal (PMUM=1) goes l ow.

Bit 1: Bit E rror Count (BEC). When 0, the bit er r or count i s zero. W hen 1, t he bit error count is one or more.

Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming

pattern. When 1, the r ec eiv e patt er n gener ator is not synchr onized to the incoming patter n.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

BSRL

Register Description:

BERT S t atus Regi st er Latched

Register A ddr es s (LI Us 1–8):

0Eh

Register A ddr es s (LI Us 9–16):

2Eh

Bit #

7

6

5

4

3

2

1

0

Name

—

PMSL

BEL

BECL

OOSL

Default

0

Bit 3: P erf orman ce M on itoring Upd at e Status L at ched (PM SL) . Thi s bit is set when the P M S bit transi tions from

0 to 1. A read oper ation clear s this bit.

Bit 2: Bit E rror L at ched (BEL ). This bit is set when a bit error is detec ted. A read operation clear s this bit.

Bit 1: Bit E rror Co un t Lat ched (BECL ). T hi s bit i s se t whe n t he BEC bi t t ransit ions f rom 0 to 1. A read oper ati on

cl ear s this bit.

Bit 0: Out Of Synchronization Latched (OOSL). T his bit is set when the OOS bit changes state. A read oper ation

cl ear s this bit.

Register Name:

BSRIE

Register Descripti on:

BERT Status Register Int errupt Enable

Register A ddr es s (LI Us 1–8):

10h

Register A ddr es s (LI Us 9–16):

30h

Bit #

7

6

5

4

3

2

1

0

Name

—

PMSIE

BEIE

BECIE

OOSIE

Default

0

Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit enables an interrupt if the

PMSL bi t is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 2: Bit E rror Int errup t Enable (BEIE). This bit enables an interr upt if the BEL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 1: Bit Error Count Interrupt Enable ( BE CIE) . T his bi t enables an interrupt if the BECL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit enables an interr upt if the OOSL bit is set.

0 = interrupt disabled

1 = interrupt enabled

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

RBECR1

Register Descripti on:

Receive BERT Bi t Erro r Count Register 1

Register A ddr es s (LI Us 1–8):

14h

Register A ddr es s (LI Us 9–16):

34h

Bit #

7

6

5

4

3

2

1

0

Name

BEC7

BEC6

BEC5

BEC4

BEC3

BEC2

BEC1

BEC0

Default

0

Register Name:

RBECR2

Register Descripti on:

Receive BERT Bi t Erro r Count Register 2

Register A ddr es s (LI Us 1–8):

15h

Register A ddr es s (LI Us 9–16):

35h

Bit #

7

6

5

4

3

2

1

0

Name

BEC15

BEC14

BEC13

BEC12

BEC11

BEC10

BEC9

BEC8

Default

0

Register Name:

RBECR3

Register Descripti on:

Receive BERT Bi t Erro r Count Register 3

Register A ddr es s (LI Us 1–8):

16h

Register A ddr es s (LI Us 9–16):

36h

Bit #

7

6

5

4

3

2

1

0

Name

BEC23

BEC22

BEC21

BEC20

BEC19

BEC18

BEC17

BEC16

Default

0

Bits 23 to 0: BERT Bit Erro r Count (BEC[23:0]). These 24 bit s i ndicat e the number of bi t errors detected in t he

incoming data stream. This count stops incrementing when it reaches a count of FF FFFFh. The associated bit

error c ounter will not increm ented when an OOS condition exists.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

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Register Name:

RBCR1

Register Descripti on:

Receive BERT Bi t Count Regist er 1

Register A ddr es s (LI Us 1–8):

18h

Register A ddr es s (LI Us 9–16):

38h

Bit #

7

6

5

4

3

2

1

0

Name

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

Default

0

Register Name:

RBCR2

Register Descripti on:

Receive BERT Bi t Count Regist er 2

Register A ddr es s (LI Us 1–8):

19h

Register A ddr es s (LI Us 9–16):

39h

Bit #

15

14

13

12

11

10

9

8

Name

BC15

BC14

BC13

BC12

BC11

BC10

BC9

BC8

Default

0

Register Name:

RBCR3

Register Descripti on:

Receive BERT Bi t Count Regist er 3

Register A ddr es s (LI Us 1–8):

1Ah

Register A ddr es s (LI Us 9–16):

3Ah

Bit #

7

6

5

4

3

2

1

0

Name

BC23

BC22

BC21

BC20

BC19

BC18

BC17

BC16

Default

0

Register Name:

RBCR4

Register Descripti on:

Receive BERT Bi t Count Regist er 4

Register A ddr es s (LI Us 1–8):

1Bh

Register A ddr es s (LI Us 9–16):

3Bh

Bit #

15

14

13

12

11

10

9

8

Name

BC31

BC30

BC29

BC28

BC27

BC26

BC25

BC24

Default

0

Bits 31 to 0: BERT Bit Count (BC[31: 0]). These 32 bits indicate the number of bits in the incoming dat a stream.

This count stops incrementing when it reaches a count of FFFF FFFFh. The associated bit counter will not

inc r em ented when an OOS condit ion ex ists.

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7 JTAG BOUND ARY SCAN ARCHI TEC TURE AND TES T ACCESS PORT

The DS26324 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and

EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26324 contains the

following as requi r ed by IEEE 1149.1 Standar d Test-Access Port and B oundar y-Scan Archit ecture:

Test Access Port (TAP)

TAP Controller

Instruc tion Register

Bypass Regi ster

Boundary S c an Register

Device Identification Register

Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE

1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins: TRSTB, TCLK,

TMS, TDI, and TDO. See the pin descriptions for details. For the latest BSDL files

go to www.maxim-ic.com/tools/bsdl/ and search f or DS26324.

Figure 7-1. JTAG Func tional Block Diagram

+V

BOUNDARY SCAN

REGISTER

INDENTIFICATION

REGISTER

BYPASS

REGISTER

INSTRUCTION

REGISTER

TDI

TMS

TCLK

TRSTB

TDO

+V

TEST AC C ESS PORT

CONTROLLER

MUX

10kΩ

SELECT

OUTPUT ENABLE

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7.1 TAP Cont roller State Machine

The T A P contr oller is a finit e state mac hine that r esponds to the logic lev el at TMS on the risi ng edge of TCLK. T he

state diagram is shown in Figure 7-2.

7.1.1 Test-Logic-Reset

Upon power-up, the TAP controller will be in the Test-Logic-Reset state. The instruction register will contain the

IDCO DE i nstructi on. All system l ogi c of t he dev ic e will oper ate norm all y. This state i s aut om atic ally entered duri ng

power-up. This state is entered f r om any stat e if t he TMS i s hel d high for at least 5 clocks.

7.1.2 Run-Test-Idle

The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test

registers will remain idle. The controller remains in this state when TMS is held low. When the TMS is high and

ri si ng edge of TCLK is applied the controller m oves to the Sel ec t-DR-Scan state.

7.1.3 Select-DR-Scan

All test registers retain their previous state. With TMS LOW, a rising edge of TCLK moves the controller into the

Capture-DR stat e and wi ll i niti ate a scan sequence. TM S HIGH duri ng a risi ng edge on TCLK m oves the controll er

to t he S elec t-IR-Scan stat e.

7.1.4 Capture-DR

Data can be parallel-loaded i nto t he test-data r egisters if t he c ur r ent instruc tion is EXTEST or S AMPLE/PRELOAD.

If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test

register will remain at its current value. On the rising edge of TCLK, the controller will go to the shift-DR state if

TMS is LOW or it will go t o the exit1-DR state if TMS is HIGH.

7.1.5 Shift-DR

The t est-data register sel ec ted by the cur r ent instruction will be connec ted between TDI and TDO and will shift data

one stage towards i ts seri al output on eac h r isi ng edge of TCLK . If a test register sel ec ted by t he c ur r ent instruc ti on

is not placed in the serial path, it will maintain its previous state. When the TAP controller is in this state and a

ri si ng edge of TCLK is appli ed, t he c ontroller enters the E x it1-DR stat e if TMS i s hi gh or r em ains i n S hift-DR state if

TMS is low.

7.1.6 Exit1-DR

While in this state, a rising edge on TCLK will put the controller in the Update-DR state, which terminates the

scanning process, if TMS is HIGH. A rising edge o n TCLK wit h TMS LOW will put the control ler in t he Pause-DR

state.

7.1.7 Pause-DR

Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will

retain their previous state. The controller will remain in this state while TMS is LOW. A rising edge on TCLK with

TMS HIG H will put t he contr oller in the Exit2-DR state.

7.1.8 Exit2-DR

A rising edge on TCLK with TMS HIGH while in this state will put the controller in the Update-DR state and

termi nate t he scanning proc ess. A rising edge on TCLK wi th TMS LOW will enter the Shift-DR state.

7.1.9 Update-DR

A falling edge on TCLK while in the Update-DR state will latch the data from the shift register path of the test

registers into the data output latches. This prevents changes at the parallel output due to changes in the shift

register.

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7.1.10 Select-IR-Scan

All test registers retain their previous state. The instruction register will remain unchanged during this state. With

TMS LOW, a risi ng edge on TCLK m ov es the c ontroll er int o the Capt ure-IR stat e and wi ll i niti ate a scan sequence

for the instruction register. TMS HIGH during a rising edge on TCLK puts the controller back into the Test-Logic-

Reset state.

7.1.11 Capture-IR

The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is

loaded on the rising edge of TCLK. If TMS i s HIGH on the ri si ng edge of TCLK, t he c ontroller will enter t he Exit1-IR

state. If TMS is LOW on the rising edge of TCLK, the controller will enter the Shift-IR state.

7.1.12 Shift-IR

In this state, the shift register in the instruction register is connected between TDI and TDO and shifts data one

stage for every rising edge of TCLK towards the serial output. The parallel registers as well as all test registers

remain at their previous states. A rising edge on TCLK with TMS HIGH will move the controller to the Exit1-IR

state. A rising edge on TCLK with TMS LOW will keep the controller in the Shift-IR state while moving data one

stage thorough the instruction shift register.

7.1.13 Exit1-IR

A rising edge on TCLK with TMS LOW will put the controller in the pause-IR state. If TMS is HIGH on the rising

edge of TCLK, the c ontroller will enter the updat e-IR state and termi nate the scanning pr oc es s.

7.1.14 Pause-IR

Shifting of the instruction shift register is halted temporarily. With TMS HIGH, a rising edge on TCLK will put the

contr oller in t he Exit 2-IR state. The cont roll er will remain i n the P ause-IR stat e if T MS is LOW duri ng a risi ng edge

on TCLK.

7.1.15 Exit2-IR

A rising edge on TCLK wit h TMS HIG H will put the c ontroller in the Updat e-IR state. The controller will loop back to

Shift-I R if TMS is LOW during a ri si ng edge of T CLK i n this state.

7.1.16 Update-IR

The i nstructi on code shift ed i nto the instruct i on shift register is latched int o the parall el output on the falli ng edge of

TCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising

edge on TCLK wit h TMS LOW will put the controller in the Run-Test-Idle stat e. Wit h TMS HIGH, the controll er will

enter the Selec t -DR-Scan stat e.

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Figure 7-2. TAP Controller State Diagram

1

0

01

1 1

1

11

1 1

11 0 0

00

0

1

00

11

00

Select

DR-Scan

Capture DR

Shift DR

Exit D R

Pause DR

Exit2 DR

Update DR

Select

IR-Scan

Capture IR

Shi ft IR

Exit IR

Pause IR

Exit2 IR

Update IR

Test Logic

Reset

Run Test/

Idle

0

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7.2 Instruction Register

The instruc tion register c ontains a shift r egister as well as a latched par allel out put and is 3 bits in lengt h. When the

TAP c ontroller enters the Shift-IR state, the instruc tion shift r egister will be c onnec ted between TDI and TDO. While

in the Shift-IR stat e, a rising edge on TCLK wit h TMS LOW will shift the data one stage toward s the seri al output at

TDO . A rising edge on TCLK in the Ex it1-I R st ate or the Exit2-IR state wit h TMS HIGH will m ov e the cont roller t o

the update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift register to the

instruction parallel output. Instructions supported by the DS26324 and its respectiv e operational binary codes are

shown in Table 7-1.

Table 7-1. Instruction Codes for IEEE 1149.1 Architecture

INSTRUCTION SELECTED REGISTER INSTRUCTION CODES

EXTEST

Boundary S c an

000

HIGHZ

Bypass

010

CLAMP

Bypass

011

SAMPLE/PRELOAD

Boundary S c an

100

IDCODE

Device Identification

110

BYPASS

Bypass

111

7.2.1 EXTEST

Thi s all ows testi ng of all int erconnections to t he dev ice. When the EXTEST instruction is latched i n the instructi on

regi ster, t he f ollowing act i ons occur. O nce enabl ed v ia the Updat e-IR state, the par all el output s of all di git al output

pins will be driven. The Boundary Scan Register will be connected between TDI and TDO. The Capture-DR will

sampl e all digit al inputs into t he Boundary S c an Register.

7.2.2 HIGHZ

All digital outputs of the device will be placed in a high-impedance state. The Bypass Register will be connected

between T DI and TDO.

7.2.3 CLAMP

All digital outputs of the dev ic e will out put dat a from t he boundary scan par allel output while connecting t he B y pas s

Register between TDI and TDO. The outputs wi ll not change during the CLAM P instructi on.

7.2.4 SAMPLE/PRELOAD

This is a mandator y instr uc tion for the I E E E 1149.1 specification that supports two functions. The di gital I/O s of the

device can be sampled at the Boundary Scan Register without interfering with the normal operation of the device

by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the Boundary Scan

Register v ia TDI using t he S hift-DR state.

7.2.5 IDCODE

When the IDCODE instruction is latched into the Parallel Instruction Register, the Identification Test Register is

selected. The device identification code will be loaded into the Identification Register on the rising edge of TCLK

following entr y into the Capture-DR stat e. Shif t-DR can be used to shi ft the i dentifi cati on code out seriall y v i a T DO.

Duri ng Test-Logic-Reset, the ident ificati on c ode is for ced i nto the Instruc tion Regi ster ’s parallel output. The I D code

will al way s hav e a 1 in the LSB position. The next 11 bit s i dentify the manuf act urer’s JEDEC num ber and num ber

of continuation bytes followed by 16 bits for the device and 4 bits for the version Table 7-2. Table 7-3 lists the

devi c e ID code for the DS26324.

7.2.6 BYPASS

When the BYPASS instruction is latched into the Parallel Instruction Register, TDI connects to TDO through the

one-bit t est Bypass Register. Thi s all ows data to pass fr om TDI to TDO not affecti ng the device’s normal oper ation.

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Table 7-2. ID Code Structure

MSB

LSB

Version

Contact F actor y

Device ID

JEDEC

1

4 bits

16 bits

00010100001

1

Table 7-3. Device ID Codes

DEVICE 16-BIT ID

DS26324 003Ch

7.3 Test Registers

IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An

optional test register has been included with the DS26324 design. This test register is the Identification Register

and is used wit h the IDCODE i nstr uc tion and the Test-Logic-Reset stat e of the TAP controller.

7.3.1 Bounda r y Scan Register

Thi s register contains both a shi f t regi ster path and a lat ched paral l el output for all c ontrol c ells and digi tal I/O cell s

and is n bits i n length.

7.3.2 B ypass Register

Thi s r egister is a singl e 1-bit shift regi ster used with t he BYPASS, CLAMP, and HIGHZ instructi ons that prov ide a

short path between TDI and TDO.

7.3.3 Identification Register

The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is

selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See Table

7-2 and Table 7-3 for m ore informati on about bit usage.

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8 DC ELECTRICAL CHARACTERIZATION

ABSOLUTE MAXIMUM RATINGS

Vol tage Range on Any Lead with Respect to VSS (except VDD)…………………………………………….-0.3V to +5.5V

Suppl y V oltage (VDD) Range wit h Respect to VSS…..………………………………………………………-0.3V to +3.63V

Operating Temperature Range for DS26324G………………………………………………………………..0°C to +70°C

Operating Temperature Range for DS26324GN……… ………………………………………..…………..-40°C to +85°C

Storage Tem perature…………………………………………………………………………………………-55° C to +125°C

Soldering Tem per ature (refl ow)

Lead(Pb)-free ........................................................................................................................................ +260°C

Containing lead(Pb) ............................................................................................................................... +240°C

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification i s not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

8.1 DC Pin Logic Levels

Table 8-1. Recommended DC Operating Conditions

(TA = -40°C to +85°C for DS26324GN.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Logic 1 VIH 2.0 5.5 V

Logic 0 VIL -0.3 +0.8 V

Supply VDD 3.135 3.3 3.465 V

Table 8-2. Pin Capacitance

(TA = +25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capac itance CIN 7 pF

Out put Capacitance COUT 7 pF

8.2 Supply Current and Output Voltage

Table 8-3. DC Characteristics

(VDD = 3.135 to 3.465V, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Suppl y Cur r ent at 3.465V IDD 1100 mA 2, 3

Supply Curr ent at 3.3V 500

Input Leak age IIL -10.0 +10.0 µA

Tri-St ate Output Leakage IOL -10.0 +10.0 µA

Output Voltage (Io = –4.0mA) VOH 2.4 V

Output Voltage (Io = +4.0mA) VOL 0.4 V

Not e 1: Spe cifications to -40°C ar e gu aranteed by des ig n (GBD) and not production tested.

Not e 2: RCLK1-n = TCLK1-n = 1.544MHz .

Not e 3: Power dis s ip at i on with all por ts act ive, T T IP and TR IN G dr i vin g a 25Ω l oad, f or an all-ones data density.

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9 AC TIMING CHARACTERISTICS

9.1 Line Interface Characteristics

Table 9-1. Transm itter Char acteri stics

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Output Mark

Amplitude

E1 75Ω

VM

2.14 2.37 2.6

V

E1 120Ω 2.7 3.0 3.3

T1 100Ω 2.4 3.0 3.6

T1 110Ω 2.4 3.0 3.6

Output Zero Amplitude VS -0.3 +0.3 V 1

Transmit Amplit ude V ar iati on with

Supply -1 +1 %

Transmit Path Delay Single-Rail 8 UI

Dual-Rail 3

Table 9-2. Receiver Characteristics

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Cable A tt enuation Attn 12 dB

Anal og Loss-of-Signal Thr eshol d 200 mV 1

Hysteresis Short-Haul Mode 100 mV

All owable Zeros Bef or e Loss

192

2

192

2048

All owable Ones Before Loss

24

3

192

Receive Path Delay Single-Rail 8 UI

Dual-Rail 3

Not e 1: Measured at the RRING and RTIP pins.

Not e 2: 192 zeros for T1 and T1.231 Specification Compliance; 192 zeros for E1 and G.775 Specification

Compliance; 2048 zeros for ETS 300 233 compliance .

Note 3: 24 ones in 192-bit period for T1.231; 192 ones for G.775; 192 ones for ETS 300 233.

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9.2 Parallel Host Interface Timing Characteristics

The f ollowing tables show the A C c har ac teristics for the external bus i nterface.

Table 9-3. Intel Read Mode Characteristics

(VDD = 3.3V ±5%, TJ = -40°C to +125°C.) ( Note 1) (See Figure 9-1 and Figure 9-2.)

SIGNAL

NAME(S) SYMBOL DESCRIPTION MIN TYP MAX UNITS NOTES

RDB t1 Pulse width if not usi ng RDYB 40 ns 2

CSB t2 Setup time to RDB 0 ns 2

CSB t3 Hold time from RDB 0 ns 2

AD[7:0] t4 Setup time to ALE 2 ns 2

A[5:0] t5 Hold time from RDB 0 ns 2

D[7: 0], AD[ 7:0] t6 Delay time RDB, CSB active 40 ns 2

D[7: 0], AD[ 7:0] t7 Deassert delay from RDB, CSB inac tive 2 20 ns 2

RDYB t8 Enabl e delay tim e from CSB active 20 ns 2

RDYB t9 Disable delay time from the CSB inactive 15 ns 2

AD[7:0] t10 Hold time from ALE 3 ns 2

ALE t11 Pulse width 5 ns 2

D[7:0] t12 Output delay from ALE Latched 40 ns 2

A[5:0] t13 S etup tim e to RDB 10 ns 2

RDYB t14 Del ay time from RDB 0 ns 2

RDYB t15 Active out put delay time from RDB 10 35 ns 2

Not e 1: The timing parameters in this table are guaranteed by design (GBD).

Not e 2: The input/output timing reference level for all signals is VDD/2.

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Figure 9-1. Intel Nonmuxed Read Cycle

A[5:0]

RDB

CSB

D[7:0]

ALE=(1)

ADDRESS

DATA OUT

t1

t13

t3

t7

t15

t8

t5

t9

t2

t6

t14

RDYB

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Figure 9-2. Intel Mux Read Cycle

RDB

CSB

AD[7:0]

ALE

ADDRESS DATA OUT

t1

t12

t3

t7

t15

t8 t9

t2

t6

t14

t11

t10

t4

RDYB

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Table 9-4. Intel Write Cycle Characteristics

(VDD = 3.3V ±5%, TJ = -40°C to +125°C.) ( Note 1) (See Figure 9-3 and Figure 9-4.)

SIGNAL

NAME(S)

SYMBOL DESCRIPTION MIN TYP MAX UNITS NOTES

WRB t1 Pul se width 40 ns 2

CSB t2 Setup time to WRB 0 ns 2

CSB t3 Hold time to WRB 0 ns 2

AD[7:0] t4 Setup time to ALE 2 ns 2

A[5:0] t5 Hold time fro m WRB 0 ns 2

D[7: 0], AD[ 7:0] t6 Input setup t im e to WRB 10 ns 2

D[7: 0], AD[ 7:0] t7 Input hold time to WR B 5 ns 2

RDYB t8 Enabl e delay fr om CSB activ e 20 ns 2

RDYB t9 Delay time from WRB active 10 ns 2

RDYB t10 Delay time from WRB inactive 0 ns 2

RDYB t11 Disable delay time from CSB inactive 15 ns 2

ALE t12 Pulse width 5 ns 2

AD[7:0] t13 Hold time from ALE inactive 3 ns 2

A[5:0] t14 Valid address to WRB inactive 35 ns 2

Not e 1: The timing parameters in this table are guaranteed by design (GBD).

Not e 2: The input/output timing reference level for all signals is VDD/2.

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Figure 9-3. Int e l No nmux Writ e Cycle

A[5:0]

WRB

CSB

D[7:0]

ALE=(1)

ADDRESS

WRITE DATA

t1

t14

t3

t7

t9

t5

t11

t2

t6

t10

t8

RDYB

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Figure 9-4. Int e l Mux Write Cycle

WRB

CSB

AD[7:0]

ALE

ADDRESS WRITE DATA

t1

t3

t7

t2

t12

t13

t4 t6

t9

t8 t11

t10

RDYB

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Table 9-5. Motorola Read Cycle Characteristics

(VDD = 3.3V ±5%, TJ = -40°C to +125°C.) ( Note 1) (See Figure 9-5 and Figure 9-6.)

SIGNAL

NAME(S) SYMBOL DESCRIPTION MIN TYP MAX UNITS NOTES

DSB t1 Pul se width 40 ns 2

CSB t2 Setup time to DSB active 0 ns 2

CSB t3 Hold time from DSB inactive 0 ns 2

RWB t4 Setup time to DSB activ e 0 ns 2

RWB t5 Hold time from DSB inactive 0 ns 2

AD[7:0] t6 Setup time to ASB activ e 2 ns 2

AD[7:0] t7 Hold time to ASB inactive 3 ns 2

AD[7:0] , D[ 7:0] t8 Output delay time from DSB activ e 40 ns 2

AD[7:0] , D[ 7:0] t10 Output v alid delay time from DSB inactive 2 20 ns 2

ACKB t11 Output delay time from CSB inactive 15 ns 2

ACKB t12 Output delay time from DSB inactive 0 ns 2

ACKB t13 Enable output delay time from DSB activ e 20 ns 2

ACKB t14 Output delay time from DSB activ e 10 35 ns 2

A[5:0] t15 Hold time from DSB inactive 0 ns 2

A[5:0] t16 S etup tim e to DSB active 10 ns 2

Not e 1: The timing parameters in this table are guaranteed by design (GBD).

Not e 2: The input/output timing reference level for all signals is VDD/2.

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Figure 9-5. Motorola Nonmux Read Cycle

A[5:0]

DSB

CSB

D[7:0]

ASB=(1)

ADDRESS

DATA OUT

t1

t16

t3

t10

t15

t2

RWB

t8

t4 t5

t14

t11

t12

ACKB

t13

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Figure 9-6. Motorola Mux Read Cycle

DSB

CSB

AD[7:0]

ASB

DATA OUT

t1

t3

t10

t2

RWB

t4 t5

ADDRESS

t14

t7 t8

t6

t14

t11

t12

ACKB

t13

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Table 9-6. Motorola Write Cycle Characteristics

(VDD = 3.3V ±5%, TJ = -40°C to +125°C.) ( Note 1) (See Figure 9-7 and Figure 9-8.)

SIGNAL

NAME(S)

SYMBOL DESCRIPTION MIN TYP MAX UNITS NOTES

DSB t1 Pul se width 35 ns 2

CSB t2 Setup time to DSB active 0 ns 2

CSB t3 Hold time from DSB inactive 0 ns 2

RWB t4 Setup time to DSB activ e 0 ns 2

RWB t5 Hold time to DSB inactive 0 ns 2

AD[7:0] t6 Setup time to ASB active 2 ns 2

AD[7:0] t7 Hold time from ASB active 3 ns 2

AD[7:0] , D[ 7:0] t8 Setup tim e to DSB i nactive 10 ns 2

AD[7:0] , D[ 7:0] t9 Hold time fro m DSB inactive 5 ns 2

A[5:0] t10 S etup tim e to DSB active 10 ns 2

ACKB t11 O utput delay from CSB inactive 15 ns 2

ACKB t12 Output delay from DSB inactive 0 ns 2

ACKB t13 O utput enable delay tim e from DSB active 20 ns 2

ACKB t14 O utput delay time from DSB activ e 10 ns 2

A[5:0] t15 Hold time from DSB 0 ns 2

Not e 1: The timing parameters in this table are guaranteed by design (GBD).

Not e 2: The input/output timing reference level for all signals is VDD/2.

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Figure 9-7. Motorola Nonmux Write Cyc le

A[5:0]

DSB

CSB

D[7:0]

ASB=(1)

ADDRESS

WRITE DATA

t1

t10

t3

t9

t15

t2

RWB

t4 t5

t8

t14

t11

t12

ACKB t13

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Figure 9-8. Motorola Mux Write Cycle

DSB

CSB

AD[7:0] ADDRESS WRITE DATA

t1

t3

t9

t2

RWB

t4 t5

t8

ASB

t7

t6

t13

t14

t11

t12

ACKB t13

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

111 of 120

9.3 Serial Po rt

Table 9-7. Serial Port Timing Characteristics

(See Figure 9-9, Figure 9-10, and Figure 9-11.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

SCLK High Time

t1

25

ns

SCLK Low Time

t2

25

ns

Active CSB to SCLK Setup Time

t3

50

ns

Last SCLK t o CS B Inac tive Time

t4

50

ns

CSB Idle Time

t5

50

ns

SDI to SCLK Setup Tim e

t6

5

ns

SCLK t o S DI Hold Time

t7

5

ns

SCLK F alling Edge to S DO

High Impedanc e ( CLK E = 0); CSB Rising to SDO

High Impedanc e ( CLK E = 1)

t8 100 ns

Figure 9-9. Serial Bus Timing Write Operation

SCLK

SDI

CSB

t3

t6

t4

t5

LSB MSB

t2

t1

t7

Figure 9-10. Seria l Bus Timing Read Operatio n with CLKE = 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCLK

CSB

SDO

t4

t8

Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCLK

CSB

SDO

t4

t8

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

112 of 120

9.4 Syst em Timing

Table 9-8. Transmitt er System Timing

(See Figure 9-12.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

TPOS, TNEG Setup Tim e wi th Respect t o TCLK

Falling Edge t1 40 ns

TPOS, TNEG Hold Tim e wi th Respect t o TCLK

Falling Edge t2 40 ns

TCLK P ulse-Width High t3 75 ns

TCLK P ulse-Width Low t4 75 ns

TCLK P eri od t5 488 ns

648

TCLK Rise Time t6 25 ns

TCLK Fall Time t7 25 ns

Figure 9-12. Transm itter Sy stem s Timin g

TPOS, TNEG

t1

TCLK

t2

t3 t4

t5

t6

t7

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

113 of 120

Table 9-9. Receiver System Timing

(See Figure 9-13.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Delay RCLK to RPOS, RNEG Valid t1 50 ns

Delay RCLK to CV Valid in Single-Rail Mode t2 50 ns

RCLK Pulse-Width High t3 200 ns

RCLK Pulse-Width Low t4 200 ns

RCLK Period t5

488

ns

648

Figure 9-13. Receiver Systems Timing

t1

t2

t5

t3 t4

RCLK

RPOS,RNEG

CV BPV/

EXZ/

CV

BPV/

EXZ/

CV

1

2

Notes:

1) CLKE = 1.

2) CLKE = 0.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

114 of 120

9.5 JTAG Timing

Table 9-10. JTAG Timing Characteristics

(See Figure 9-14.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

TCK P eri od t1 100 ns

TMS and TDI Setup to TCK t2 25 ns

TMS and TDI Hold to TCK t3 25 ns

TCK to TDO Hold t4 50 ns

Figure 9-14. JTAG Timin g

TCK

TMS

TDI

TDO

t1

t2 t3

t4

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

115 of 120

10 PIN CONFIGURATION

Figure 10-1. 256-B all TE-CSBGA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

RTIP1

RRING1

MODESEL

RTIP16

VDDT16

TTIP16

TTIP15

VDDT15

RTIP15

VDDT14

TTIP14

TTIP13

VDDT13

RTIP14

TDO

RTIP13

B

AVDD

AVSS

MOTEL

RRING16

RSTB

TRING16

TRING15

LOS14

RRING15

LOS13

TRING14

TRING13

TMS

RRING14

TDI

RRING13

C

RTIP2

RRING2

TNEG1

A4

TNEG16

TNEG15

RNEG15

RPOS15

RNEG14

RPOS14

TCLK13

RPOS13

SDO/RDY/ACKB

TPOS12

AVSS

AVDD

D

VDDT1

LOS1

RCLK1

GNDT1

TPOS16

GNDT16

INTB

GNDT15

GNDT14

GNDT13

TCLK16

TCLK14

GNDT12

TCK

RRING12

RTIP12

E

TTIP1

TRING1

RNEG1

A5

RPOS16

RCLK16

TPOS14

RCLK13

RCLK14

RNEG13

LOS15

TCLK12

TNEG12

RPOS12

TRSTB

VDDT12

F

TTIP2

TRING2

RPOS2

RPOS1

TCLK1

TPOS1

TNEG14

RCLK15

TPOS13

LOS16

RNEG12

RCLK12

RNEG11

TCLK11

TRING12

TTIP12

G

VDDT2

LOS2

A2

TCLK2

RNEG2

RCLK2

TPOS2

TNEG13

TCLK3

TNEG4

TPOS11

RPOS11

RCLK11

SDI/WRB/DSB

TRING11

TTIP11

H

RTIP3

RRING3

A1

GNDT2

A3

TCLK4

AVDD

DVDD

DVSS

AVSS

TNEG11

MCLK

GNDT11

RDB/RWB

LOS12

VDDT11

J

VDDT3

LOS3

RNEG16

GNDT3

TNEG3

TPOS3

AVSS

DVSS

DVDD

AVDD

TPOS10

TNEG10

GNDT10

TNEG2

RRING11

RTIP11

K

TTIP3

TRING3

RCLK3

RNEG3

RCLK4

TPOS4

D3

RPOS5

TNEG8

RNEG8

TCLK9

TCLK10

RPOS10

RCLK10

LOS11

VDDT10

L

TTIP4

TRING4

RPOS3

RPOS4

D4

D0

RNEG5

TCLK6

TPOS5

TCLK7

TPOS9

TNEG9

RCLK9

RNEG10

TRING10

TTIP10

M

VDDT4

LOS4

RNEG4

D5

D1

TNEG5

TCLK5

RCLK6

RPOS6

RNEG6

TPOS8

RPOS8

RNEG9

RPOS9

TRING9

TTIP9

N

RTIP4

RRING4

D7

GNDT4

TPOS6

GNDT5

TCLK15

GNDT6

GNDT7

A0

GNDT8

TPOS15

GNDT9

SCLK/ALE/ASB

LOS10

VDDT9

P

AVDD

AVSS

D6

D2

RCLK5

TNEG6

TNEG7

RPOS7

TCLK8

RCLK7

RNEG7

TPOS7

RCLK8

CSB

RRING10

RTIP10

R

RRING5

LOS5

RRING6

LOS7

TRING5

TRING6

LOS8

RRING7

RESREF

TRING7

TRING8

OE

RRING8

LOS9

AVSS

AVDD

T

RTIP5

LOS6

RTIP6

VDDT5

TTIP5

TTIP6

VDDT6

RTIP7

VDDT7

TTIP7

TTIP8

VDDT8

RTIP8

CLKE/MUX

RRING9

RTIP9

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

116 of 120

11 PACKAGE INFORMATION

For t he l atest package outline inform ati on and l and patterns (f ootprints), go to www.maxim-ic.com/packages. Note

that a “ +” , “#”, or “ -” in the pack age c ode indicates RoHS status onl y . Pack age dr awings may sho w a differ ent suff ix

character, but the drawing per tains to t he pac k age r egardl ess of RoHS status.

PA CKA GE TYPE PACK AGE CODE OUTLINE NO. LAND PATTERN NO.

265 TE-CSBGA X256T+2 21-0315 90-0291

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

117 of 120

12 THERMAL INFORMATION

Table 12-1. Ther mal Character istics

PARAMETER MIN TYP MAX V (m/s) NOTES

Ambient Tem per ature

-40

°

C

+85

°

C

1

Junction Temperature

+125

°

C

Theta-JA (θJA) in S till Air Conduct ion

16.6°C/W

0

2

Theta-JC (θJC) Conduc tion

3.0°C/W

Theta-JB (

θ

JB) Conduc ti on

7.5

°

C/W

Theta-JA (

θ

JA) in Forced Air

15.0

°

C/W

0.75

Theta-JA (

θ

JA) in Forced Air

14.6

°

C/W

1.25

Theta-JA (

θ

JA) in Forced Air

14.0

°

C/W

2.5

No te 1: The package is mounted on a four-layer JEDEC standard test board.

Not e 2: Theta-JA (θJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC s tandard

t est b oard.

Table 12-2. Packag e Power Dissip ation (for Thermal Considerations)

MODE

TYP ICAL 50% 1s (Note 1)

TYP ICAL 100% 1s (Note 2)

MAXIMUM 100% 1s (No t e 3)

FULLY

INTERNAL

PARTIALLY

INTERNAL EXTERNAL FULLY

INTERNAL PARTIALLY

INTERNAL EXTERNAL

FULLY

INTERNAL PARTIALLY

INTERNAL EXTERNAL

E1-75Ω

1.64

1.43

1.31

2.56

2.15

1.90

2.82

2.36

1.98

E1-120

Ω

1.49

1.19

2.23

1.62

2.54

1.69

T1-LBO0

1.87

1.52

1.47

2.96

2.26

2.14

3.56

2.51

2.23

T1-LBO1

1.92 1.57 1.51 3.03 2.32 2.20 3.63 2.57 2.30

T1-LBO2

1.95 1.60 1.55 3.06 2.35 2.29 3.66 2.60 2.39

T1-LBO3

1.99

1.63

1.58

3.12

2.41

2.29

3.72

2.67

2.39

T1-LBO4

2.02 1.67 1.61 3.16 2.46 2.34 3.77 2.72 2.44

J1-LBO0

1.84 1.49 1.47 2.90 2.20 2.14 3.44 2.36 2.23

J1-LBO1

1.89 1.54 1.51 2.96 2.26 2.20 3.51 2.42 2.30

J1-LBO2

1.92

1.57

1.55

2.99

2.29

3.54

2.45

2.39

J1-LBO3

1.95 1.60 1.58 3.05 2.35 2.29 3.60 2.52 2.39

J1-LBO4

1.99 1.63 1.61 3.10 2.39 2.34 3.65 2.57 2.44

No te 1: Typical voltage, transmitting/ r ecei vin g 50 % 1s in Watts.

Not e 2: Typical voltage, transmitting/receiving 100% 1s in Watts.

Not e 3: Maximum voltage, transmitting/receiving 100% 1s in Watts.

Table 12-3 describes how much power to deduct per-channel from the t otal power dis si pati on v alues li sted in

Table 12-2.

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

118 of 120

Table 12-3. Per-Cha nnel Power-Down Savings (for Thermal Considerations)

MODE

TYP ICAL 50% 1s (Note 1)

TYP ICAL 100% 1s (Note 2)

MAXIMUM 100% 1s (No t e 3)

FULLY

INTERNAL

PARTIALLY

INTERNAL EXTERNAL FULLY

INTERNAL PARTIALLY

INTERNAL EXTERNAL

FULLY

INTERNAL PARTIALLY

INTERNAL EXTERNAL

E1-75

Ω

0.093 0.080 0.072 0.151 0.125 0.109 0.166 0.137 0.113

E1-120

Ω

0.084

0.065

0.130

0.092

0.148

0.095

T1-LBO0 0.108 0.086 0.083 0.176 0.132 0.125 0.213 0.147 0.130

T1-LBO1 0.111 0.089 0.086 0.180 0.136 0.129 0.217 0.151 0.134

T1-LBO2

0.113

0.091

0.088

0.182

0.138

0.134

0.219

0.153

0.140

T1-LBO3

0.115

0.093

0.090

0.186

0.142

0.134

0.223

0.157

0.140

T1-LBO4 0.117 0.095 0.092 0.189 0.145 0.137 0.226 0.160 0.143

J1-LBO0 0.106 0.084 0.083 0.172 0.128 0.125 0.205 0.137 0.130

J1-LBO1 0.109 0.087 0.086 0.176 0.132 0.129 0.209 0.141 0.134

J1-LBO2 0.111 0.089 0.088 0.178 0.134 0.134 0.211 0.143 0.140

J1-LBO3 0.113 0.091 0.090 0.182 0.138 0.134 0.215 0.147 0.140

J1-LBO4 0.115 0.093 0.092 0.185 0.141 0.137 0.218 0.150 0.143

No te 1: Typical vol t ag e, tr ansmit ti ng/rec ei vin g 50% 1s in Watts.

Not e 2: Typical voltage, transmitting/receiving 100% 1s in Watts.

Not e 3: Maximum voltage, transmitting/receiving 100% 1s in Watts.

TA

°

C +

θ

JA x Power Dissipation

≤

Maximum Junction Temperature

Where: TA = Maximum Ambient Temper ature

Example:

TA = +70

°

C

Mode = Typic al 100% 1s E 1-75

Ω

, Fully Inter nal Impedanc e M atching

Air F low = 1.25m/s

70

°

C + 14.6

°

C/W x 2.56W = 107

°

C

This is below the max im um junct ion temperature and, theref or e, t his s olution will support the therm al r equir ements .

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

119 of 120

13 DATA SHEET REVISION HISTORY

REVISION

DATE DESCRIPTION PAGES

CHANGED

070105 Initial r elease. —

042007

Added descri ptions of feature enhanc em ents implem ented in revi si on A2:

1) Programmable corner frequency for the jitter attenuator in E1 mode.

2) Fully internal impedance matchi ng option for RTIP/RRING.

3) Option for syste m-side deployment of BERT.

4) Revised B8ZS /HDB3 sections for clarification of functions.

5) Added RES RE F pin f or receiv e termi nati on cali br ation.

See bel ow for the det ailed list of changes m ade to this data sheet revision.

See Features bullets, Detailed Descr iption, and S ec tion 5.5.1 for mention of fully

internal receive impedance match ing. 1, 7, 27

Added RESRE F pin (R9). 11

In O E pi n description, c hanged GC.RTCTL to TST. RHPMC. 15

Deleted R9 from DV SS. 16

In Section 5.4: Transmitter, second paragraph, c hanged NRZ encoding to AMI

encoding. 20

Replaced F igur e 5-8. 25

In Table 5-6, updated Rt ; updat ed S ec tion 5.4.3 and Section 5.4.4; in Section

5.4.5: Zero Suppression—B 8ZS or HDB 3, removed “or Transmit Maintenance

Register settings” from last sentenc e of fi r st par agr aph (no such regi ster for t his

part).

26

Changed Section 5. 4.8 name from Drive Failure Monitor to Dr iv er Fail M onitor;

updated S ec tion 5. 5; added new Section 5. 5.1: Rec eive Impedance Matching

Calibration. 27

Added Sec tion 5. 5.8: Receive Dual-Rail Mode; added new Section 5.5.9: Receiv e

Single-Rail Mode; updated T able 5-11. 30

Updated S ec tion 5. 8.2: Digital Loopback. 33

Added new paragraph to Sec tion 5.9: BE RT. 34

Changed GMC to BGMC (Table 6-1) ( see al so page 53). 40

In Table 6-4, deleted Receive B it Er r or Count Regis ter 4 (does not exist for this

part). 43

In Table 6-5, changed bi t names for LOSS (LI Us 1–16) to correctly match bit

description on page 49; for TST, c hanged bits 7–5 from Reserved to JABWS1,

JABWS0, and RHPM C (see also page 58). 44

In Table 6-6, changed SRS bit to correctly say SRM S. 45

In Table 6-7, added mi ssing addres s (27) to SHLHS for LIUs 9–16; changed bi t 7

and bits 3–0 names for RSMM4 (LIUs 9–16) to c or r ectly m atch bit description on

page 74; changed “ GI S C” (3E) to “Not Used” for LIUs 9–16. 46

In Table 6-8, changed BSR r egister bit 3 (PMS) to show i t is read only ( added

underl ine) , matching t he bit descripti on on page 88, as well as changed “RW” to

“R” to correctl y show all bits are read only; changed BSRL register bit 3 (PMSL) to

show it is read only ( added under line), matching the bit descr iption on page 89, as

well as changed “RL/W” to “R” to corr ectly show all bits ar e r ead only .

47

DS26324 3.3V , 16-Channel, E1/T1/J1 Short-Haul Line Int erface Unit

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim

reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

120 of 120

REVISION

DATE DESCRIPTION PAGES

CHANGED

Changed GMC to BGMC; changed bits 7, 6, and 5 from Reserv ed to BERTDIR,

BMCKS, and BTCKS. 53

In t he GC register ( LIUs 1–8), changed bit 7 from Reserved to RIMPM S and bit 2

from RTCT L to CRIMP ( see al so page 44, Table 6-5). 56

In t he GC register ( LIUs 9–16), changed bit 7 from Reserv ed to RIMPM S and

changed bi t 2 from Reserved to CALEN (see also page 44, T able 6-5). 57

For TST, c hanged bits 7, 6, and 5 fr om Reserved to JABWS1, JABWS0, and

RHPMC. 58

In t he bit 7 (RIMP ON) description, c hanged GC.RTCTL to TST.RHPM C; added

note t o bit description. 60

Changed bit description for OE bits 7 to 0. 61

For EZDE , cor r ec ted bit names for LIUs 1–16 from EXZDE[1:16] to EZDE[1:16];

changed bi t description to say “Excessive zer o detection is only rel ev ant when

HDB3 or B8ZS decodi ng is enabl ed.” For CVDEB, changed bit description to say

“Code violation detection is only r elev ant when HDB3 decodi ng is enabled ( LCS

register).”

65

Added note to bit 3 (RSMM1:RS S M 4) descri ption and updated descriptions f or bit s

6–4 and 2–0 (deleted “When” from each sentence for clar it y ). 71, 72, 73, 74

Updated pack age dr awing information. 117

In Table 12-1, deleted “Power Di ssipat ion in P ackage”; added new Table 12-2.

Package P ower Dissipation (f or Therm al Cons ider ations) and Table 12-3. Per-

Channel Pow er-Down S av ing (for Therm al Cons ider ations). 118

053107

Table 8-3: added “Not e 1: Spec ificati ons to -40°C are guaranteed by desi gn ( GBD)

and not produc tion tested.”

97

Table 9-3, 9 -4, 9-5, and 9-6: added “Note 1: The timing param eters i n this table are

guaranteed by desi gn ( GBD) .”

99, 102, 105,

108

012108 Changed the G C ( 2Fh) register bit 1 (J APS) description. 57

3/11

Figure 10-1 in Secti on 10 PIN CONFIGURATION: Cor rect ed c ell R9. Changed

from DVSS to RESREF.

115

Pb-free ordering information added 1

Table 4-1. PI N DESCRIPTION. TRS TB Function description c hanged. Repl ac ed

“floating” wit h “unconnected”

15

Sect ion 8 DC ELECTRICA L CHA RACTE RIZ ATIO N: Solder ing inf ormation i n

ABSOLUTE MAXIMUM RATINGS table updated

97

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