TOSHIBA 32-Bit RISC Microcontroller TX09 Series TMPA910CRAXBG Semiconductor Company TMPA910CRA Caution about the Electrostatic Discharge (ESD) Sensitivity of This Product This product is an electrostatic discharge sensitive (ESDS) product that requires extra caution in handling. For ESD test data of this product, please contact your local Toshiba sales representative. *************************************************************************************************************** ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. **************************************************************************************************************** (R) TMPA910CRA- 1 2010-06-02 TMPA910CRA - Introduction - Notes on the registers This device has SFR (Special Function Register) each IP (Peripheral circuits). SFR is shown as following in this data book. a) IP lists IP lists show the register name, address and easy descriptions. 32bit address is assigned to all registers. It shows as [base address + (specific) address]. base address = 0x0000_0000 Register Address Name (base+) SAMPLE Description 0x0001 Sample register Note1: Case of this register (SAMPLE): 00000001 address because 00000000 address (hex)+0001 address (hex) Note2: This register is sample register. There is not this data book. b) SFR (register) description Basically, each register is structured 32 bit register. (There is a part of exception.) Each description shows Bit, Bit Symbol, Type, Reset value and Description. Address = (0x0000_0000) + (0x0001) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:6] SAMPLE76 R/W 0y00 Sample setting 0y00: Set to Sample mode 0 0y01: Set to Sample mode 1 0y10: Set to Sample mode 2 0y11: Set to Sample mode 3 Note1: Basically 3types. R/W(READ/WRITE) Enable Read/Write RO(READ ONLY) Enable Read only WO(WRITE ONLY) Enable Write only There are exception types (USB device controller and SD host controller). Please refer to those sections. Note2: Bit state description: Hexadecimal: 0x00FF = 255 (Decimal) Binary: 0y0101 = 5 (Decimal) Note3: 1 Word = 32 bit. TMPA910CRA- 2 2010-06-02 TMPA910CRA 32-Bit RISC Microprocessor TMPA910CRAXBG 1. Overview and Features TMPA910CRA is a 32-bit RISC microprocessor with a built-in ARM9TM cpu core. TMPA910CRAXBG is a 361-pin BGA package product. Features of the product are as follows: (1) ARM926EJ-S manufactured by ARM is used. * Data cache: 16 Kbytes * Instruction cache: 16 Kbytes (2) Maximum operating frequency: 200 MHz (3) A 7-layer multi bus system is used. * Bus Master1: CPU data * Bus Master2: CPU instruction * Bus Master3: LCD controller * Bus Master4: LCD data process accelerator * Bus Master5: DMA controller 1 * Bus Master6: DMA controller 2 * Bus Master7: USB device controller (4) Memory access * Built-in RAM: 56 Kbytes (can be used as program, data, and display memory) * Built-in ROM: 16 Kbytes (boot memory) It can be loaded to the built-in RAM from USB * 4 GB linear access space (effective space: approximately 2.5 GB) * Separate bus system: External address 26 bits: A0-A25 External data bus 32 bits: D0-D31 (Only a 16-bit bus is available for Mobile DDR SDRAM) (5) Memory controller * Chip-select output: 4 channels * Chip-select exclusive for DRAM: 1 channel * Depending on the external pin selection, SDR (Single Data Rate)-type SDRAM and DDR (Double Data Rate) LVCMOS_I/O type SDRAM can be supported (SSTL_IO type DDR SDRAM is not supported). (6) 16-bit timer * 6 channels 16-bit timers including 4 channel timers (2 blocks) with PWM function. (7) Synchronous serial bus interface: 2 channels * Supports SPI mode/MicroWire mode. (8) I2C bus interface: 2 channels TMPA910CRA- 3 2010-06-02 TMPA910CRA (9) UART: 2 channels * Channel 0: supports Full UART / supports IrDA1.0 mode. * Channel 1: supports only 3 pins: TXD, RXD, and CTS. (10)USB controller: 1 channel * Supports USB (REV2.0). * Supports high communication speed (480Mbps) (does not support Low Speed). * Supports 4 endpoints. End-point 0: Control 64 bytes x 1- FIFO End-point 1: Bulk (Device Host: IN transfer) 512 bytes x 2 -FIFO End-point 2: Bulk (Host Device: OUT transfer) 512 bytes x 2- FIFO End-point 3: Interrupt 64 bytes x 1- FIFO (11)I2S (Inter-IC Sound) interface: 2 channels * Channel 0 (for reception: 32-byte FIFO x 2) * Channel 1 (for transmission: 32-byte FIFO x 2) (12)LCD controller * Supports 800 x 480 pixel size. * Supports TFT/STN panels. * For STN panels, 4/15 monochrome tones and 256/3375 color tones are supported. * For TFT panels, 16-bit/24-bit color is supported. (13)LCD data process accelerator * Scaling function (expansion/reduction) * Filtering function (bi-cubic convolution) * Image blending function (supports font blending) (14)RTC (real-time clock) (15)Melody/Alarm generator * Supports output of 8 alarm sound patterns. (16)Key-on wake up (key-input interrupt) (17)10-bit AD converter (with a built-in sample-and-hold circuit): 6 channels (18)Supports touch-screen interfaces * Since a low-resistance switch is built in to the product, external components for horizontal/vertical switching can be omitted. (19)Watchdog timer (20)Interrupt function: 28 types * External (26 pins): 7 types Key input * Internal : 21 types INT0 to INTH (edge: rise and fall, level: High and Low), 16-bit timer x 3, RTC x 1, and A/D converter x 1 CMOS image sensor x 1, LCDC x 1, NANDFC x 1, UART x 2, I2C x 2, SSP x 2, USB x 1, I2S x 1, SD host controller x 1, LCDDA x 1, DMAC x 2, and WDT x 1 TMPA910CRA- 4 2010-06-02 TMPA910CRA (21)I/O port: 114 pins (22)DMA controller: 8 channels (23)NAND-flash memory interface: 2 channels * Easy connection to NAND-flash memory. * Supports both 2LC (2 values) and 4LC (4 values) types. * Supports 8-bit data bus and 512/2048-byte page size. * Built-in Reed Solomon operational circuit can correct 4 addresses and detect errors in more than 5 addresses. (24)SD host controller: 2 channels * Supports SD card I/F mode (4-bit parallel). * Supports SDIO. * Built-in 512-byte FIFO buffer. (25)CMOS Sensor I/F: 1 channel * YUV data can be converted into RGB data * LCD display memory can be specified as a data save location. * Supports scaling and trimming functions for changing sizes. (26)Standby function * Status of each pin in standby mode can be set bit-by-bit. * Built-in power management circuit (PMC) to prevent leakage current. (27)Clock control function * Two blocks of built-in clock multiple circuit (PLL) enables an external 10 to 25 MHz oscillator to supply USB clock frequency of 480 MHz and clock frequency of 200 MHz to the CPU (CPU clock frequency is 192 MHz when USB is in use). * Clock gear function: A high-frequency clock can be changed within the range of fc to fc/8. * Clock (CPU) for clock (time) (fs = 32.768 kHz) (28)Operating voltage * Internal DVCC1A and DVCC1B = 1.5 V 0.1 V * High-frequency oscillator and power supply for PLL, DVCC1C = 1.5 V 0.1 V * External I/O DVCCM for memory = 3.0 V to 3.6 V or 1.8 V 0.1 V * General external I/O DVCC3IO = 3.0 V to 3.6 V * External I/O DVCC3LCD for LCD = 1.8 V to 3.6 V * External I/O DVCC3CMS for CMOS image sensor = 1.8 V to 3.6 V * External I/O AVCC3AD for AD converter = 3.0 V to 3.6 V * External I/O AVDD3T/C for USB = 3.15 V to 3.45 V * External I/O DVCC3I2S for I2S = 1.8 V to 3.6 V (29)DSU (JTAG) function * JTAG supports of the ARM9 core. (30)Package * 361-pin FBGA: P-FBGA361-1616-0.80AZ TMPA910CRA- 5 2010-06-02 TMPA910CRA Data Cache 16Kbyte Instruction Cache 16Kbyte TM ARM926EJ -S (Bus Master1&2) Bus Interface CPU Inst. LCD Controller LCDC CPU Data. DMA Controller DMA1 DMA2 (Bus Master5&6) (Bus Master3) LCD Data Process Accelerator LCDDA USB Device Controller USB (Bus Master7) (Bus Master4) Interrupt Controller A/D converter (6ch) CPU Data Touch Screen I/F 16Timer/PWM (6ch) I2S I/F (2ch) SD Host Controller (2ch) Synchronous Serial Port (2ch) CPU Data CPU Data APBTM Bridge NANDF Controller (2ch) Multi Layer Bus Matrix1 Power Management I2C I/F (2ch) UART (2ch) RTC/Melody Watch Dog Timer System Controller DMA1 DMA2 PLL Clock Gear CMOS image Sensor I/F General purpose I/O Key board matrix External Interruption DMA1 DMA2 CPU Inst. CPU Data. LCDDA LCDC USB Multi Layer Bus Matrix3 Multi Layer Bus Matrix0 Internal RAM0 16KB Internal RAM1 16KB Internal RAM2 16KB Internal RAM3 8KB Multi Layer Bus Matrix2 Memory Controller Memory Controller NORF SRAM SDR SDRAMC NORF SRAM DDR SDRAMC Boot ROM 16KB External Bus Interface Figure 1.1 TMPA910CRA block diagram TMPA910CRA- 6 2010-06-02 TMPA910CRA 2. Pin Configuration and Functions This section provides a TMPA910CRA pin configuration diagram, names of I/O pins, and brief description of their functions. 2.1 Pin configuration diagram (Top View) Figure 2.1.1 shows the TMPA910CRA pin configuration. TMPA910CRA P-FBGA361 TOP VIEW (Perspective view from the top) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Figure 2.1.1 Pin configuration diagram Note 1: No valid signals have been assigned to Balls A1 and W1. Also, A1 and W1 are electrically connected with each other inside the BGA board. Note 2: No valid signals have been assigned to Balls A19 and W19. Also, A19 and W19 are electrically connected with each other inside the BGA board. Note 3: Ball G7 is an NC pin. TMPA910CRA- 7 2010-06-02 TMPA910CRA Table 2.1.1 Pin numbers and names Ball Pin name No. Ball Pin name No. Ball Pin name No C3 SP0/TCK L6 PC5/MLDALMn/INT8 T6 D4 SP1/TMS K2 DVCC3IO4 N8 SW2/NDALE SW1/NDWEn K8 DVSSCOM1 L5 PC6/I2C0CL U6 SV3/NDD3 D3 SP2/TDI L1 PC2/PWE W3 DVCC3IO9 B1 DVCC3IO1 L4 PT5/U1RXD N9 SV6/NDD6 SV2/NDD2 E5 SP5/TDO K3 DVSSCOM7 R7 E4 SP4/RTCK N7 PT4/U1TXD N10 SW0/NDREn F5 SP3/TRSTn M1 PC7/I2C0DA/INT9 R8 PP2/INT2 G6 DVCC3CMS1 T1 SM4/RESETn V4 DVCC1A3 G5 PF6/I2C1CL P7 PG5/SDC0WP T7 SV5/NDD5 F4 PF7/I2C1DA/INTC L2 DVCC3IO5 V5 SV1/NDD1 H7 PF1/CMSHSY N6 PG4/SDC0CMD P9 PP1/INT1 J7 PE7/CMSD7 L3 PG3/SDC0DAT3 L9 DVSSCOM11 E3 PF2/CMSHBK M2 PG2/SDC0DAT2 P10 SV4/NDD4 D2 PF3/CMSVSY M8 DVSSCOM8 U7 SV0/NDD0 K8 DVSSCOM2 P1 PG7/SDC0CLK R9 PP0/INT0 F3 PF0/CMSPCK M4 PH5/SDC1WP W4 DVCC3IO10 L7 PE6/CMSD6 M3 PG6/SDC0CD M10 DVSSCOM12 C2 PE3/CMSD3 M5 PG1/SDC0DAT1 V6 SN2/SELJTAG G4 PE4/CMSD4 N2 DVCC3IO6 T8 SM6/AM0 E2 PE5/CMSD5 N5 PG0/SDC0DAT0 U8 SM7/AM1 K6 DVCC3CMS2 R2 DVCC1A2 W5 DVCC3IO11 C1 PE0/CMSD0 P6 PH6/SDC1CD R10 SN0/SELMEMC H5 PE1/CMSD1 R1 PH4/SDC1CMD T10 SN1/SELDVCCM G3 PE2/CMSD2 R6 PH2/SDC1DAT2 W6 DVCC1C J8 DVSSCOM3 P2 PH1/SDC1DAT1 W7 SM0/X1 D1 PT2/SP0DO P4 DVSSCOM9 V7 DVSS1C H4 PT0/SP0FSS N3 PH0/SDC1DAT0 W8 SM1/X2 E1 DVCC3IO2 N1 PH7/SDC1CLK V8 DVCC1C H6 PN1/U0RXD/SIR0IN N4 PH3/SDC1DAT3 U9 PT7/X1USB F2 PN0/U0TXD/SIR0OUT P3 DVCC3IO7 T9 DVCC1A4 J5 PT3/SP0DI T2 VREFH K9 DVSSCOM13 F1 DVCC1A1 U2 VREFL V9 AVDD3C J8 DVSSCOM4 U1 AVSS3AD W9 SR4/VSENSE SR3/REXT H3 PT1/SP0CLK V1 AVCC3AD V10 K5 PT6/U1CTSn P5 PD5/AN5/MY W10 AVSS3C G2 PN4/U0DSRn/INTD R3 PD4/AN4/MX U10 AVDD3T1 M6 PN7/U0RTSn/INTG R5 PD3/AN3 V11 AVSS3T3 G1 DVCC3IO3 R4 PD2/AN2 U11 AVSS3T2 J4 PN3/U0DCDn T5 PD1/AN1 W11 SR1/DM H2 PN5/U0RIn/INTE T3 PD0/AN0 W12 SR0/DP K4 PN2/U0CTSn U3 PD6/PX/INTA(TSI) V12 AVSS3T1 H1 PN6/U0DTRn/INTF T4 PD7/PY/INTB U12 AVSS3T1 L8 DVSSCOM5 V2 DVCC3IO8 W13 AVSS3T0 J1 SM2/XT1 V3 SW6/NDRB V13 AVDD3T0 K1 SM3/XT2 U4 SW4/NDCE0n J10 DVSSCOM14 M9 DVSSCOM6 W2 SW5/NDCE1n V14 DVCC1A5 J3 PC4/FSOUT/PWM2OUT U5 SW3/NDCLE T11 PM0/I2S1WS M7 DVCC1B1 L9 DVSSCOM10 V15 PM2/I2S1DATO J2 PC3/MLDALM/PWM0OUT P8 SV7/NDD7 R11 PL2/I2S0DATI/SP1DO Note: Power supply signals that are indicated in bold and shaded will not be output to the balls as they are connected to the other power supplies of the same type on the board inside BGA. TMPA910CRA- 8 2010-06-02 TMPA910CRA Table 2.1.2 Pin numbers and names Ball Pin name No. Ball No. Pin name Ball Pin name No W14 PL4/I2SSCLK M14 SD3/D27 E19 DVCC1A9 T12 DVCC3I2S1 R18 SB1/D9 H14 SD6/D30 U13 PL1/I2S0CLK/SP1CLK M15 SD2/D26 F18 SE4/A4 P11 PM3/I2S1MCLK T19 DVCCM6 G15 SG4/A20 W16 PM1/I2S1CLK M16 SB7/D15 J11 DVSSCOM26 N11 PL3/I2S0MCLK/SP1DI P18 SB4/D12 G16 SG2/A18 L10 DVSSCOM15 L11 DVSSCOM21 G17 SF4/A12 R12 PL0/I2S0WS/SP1FSS L12 PP3/INT3 F15 SG5/A21 U14 DVCC3I2S2 M17 PP4/INT4 D19 DVCCM9 T13 PR0/RESETOUTn L13 PP5/INT5 F16 SG3/A19 W15 PR1/SMCWPn/FCOUT R19 PP6/INT6 E18 SE5/A5 W17 DVCC1A6 L14 PP7/INT7 F17 SF5/A13 U15 DVCCM1 N18 PA0/KI0 G14 DVSSCOM27 R13 SC3/D19 P19 DVCC3IO12 E15 SG6/A22 V16 SA0/D0 N19 PA1/KI1 D18 SE6/A6 P12 SC6/D22 L15 PA2/KI2 C19 SE7/A7 M11 DVSSCOM16 L17 PA3/KI3 E16 DVCCM10 P13 SC5/D21 L16 PA4/KI4 C18 SF1/A9 W18 SL6/DMCCLKIN M18 PA5/KI5 E17 SF6/A14 P14 SC4/D20 L11 DVSSCOM22 D17 SF7/A15 U15 DVCCM2 M19 PA6/KI6 H13 DVSSCOM28 T14 SC1/D17 K16 PA7/KI7 B19 SF0/A8 V17 SA1/D1 L19 DVCC1A8 C17 SG0/A16 V18 SA2/D2 K15 PB0/KO0 D16 DVSSCOM29 M11 DVSSCOM17 L18 PB1/KO1 B18 SK3/DMCSDQM3 R14 SC2/D18 K13 PB2/KO2 A18 SK2/DMCSDQM2 R15 SC0/D16 K17 SM5/TEST0n D15 DVCCM11 U16 SA3/D3 K19 DVCC3IO13 C16 SL2/DMCAP T15 DVCCM3 K18 PB3/KO3 E14 SG7/A23 T16 SA5/D5 K14 PB4/KO4 D14 DVSSCOM30 U17 SL4/DMCDDQS0 J19 PB5/KO5 C15 SJ4/DMCBA0 V19 SL5/DMCDDQS1 K11 DVSSCOM23 C14 SJ5/DMCBA1 N13 DVSSCOM18 J18 PB6/KO6 F14 DVSSCOM31 T17 SA6/D6 J15 PB7/KO7 F13 SH1/A25 R17 SB0/D8 H19 PC0/KO8 E13 DVCC1A10 R16 SA7/D7 J16 PC1/KO9 B17 SK0/DMCSDQM0/DMCDDM0 P15 DVCCM4 K11 DVSSCOM24 B16 DVCCM12 N14 SD0/D24 J14 DVCC1B2 G13 SH0/A24 U18 SA4/D4 J17 SF2/A10 A17 DVSSCOM32 P16 SB2/D10 J13 SD7/D31 D13 SK7/SMCBE3n M12 DVSSCOM19 H18 SE2/A2 C13 SJ2/DMCRASn N15 SC7/D23 K12 DVCCM7 B13 DVSSCOM33 P17 SB3/D11 G19 SE0/A0 D12 SK5/SMCBE1n U19 DVCC1A7 H16 SG1/A17 H12 PR2/INTH N12 SD1/D25 G18 SE3/A3 B15 DVCCM13 T18 DVCCM5 J12 DVSSCOM25 F12 SH2/SMCBE0n M13 SD4/D28 H17 SF3/A11 C12 SK6/SMCBE2n N17 SB6/D14 H15 SD5/D29 E12 SK4/SMCWEn N16 SB5/D13 F19 SE1/A1 A14 DVSSCOM34 K10 DVSSCOM20 K12 DVCCM8 A16 SL0/DMCDCLKP Note: Power supply signals that are indicated in bold and shaded will not be output to the balls as they are connected to the other power supplies of the same type on the board inside BGA. TMPA910CRA- 9 2010-06-02 TMPA910CRA Table 2.1.3 Pin numbers and names Ball Pin name No. Ball No. Pin name A15 SL1/DMCDCLKN A4 DVCC3LCD4 A14 DVSSCOM35 J6 PJ2/LD10 B14 SK1/DMCSDQM1/DMCDDM1 B3 PJ1/LD9 D11 SJ7/SMCAVDn E7 SU2/LCLLE F10 DVCCM14 C6 DVSSCOM43 G12 SJ1/DMCWEn G8 PJ5/LD13 A13 SL3/SMCCLK A3 PJ4/LD12 F11 DVCC1A11 D6 PJ3/LD11 B11 DVSSCOM36 A2 DVCC3LCD5 E11 SJ0/SMCOEn C4 SU1/LCLAC B12 SJ3/DMCCASn E6 PJ7/LD15 A12 DVSSCOM37 D5 PJ6/LD14 B10 SH5/SMCCS2n H9 DVSSCOM44 E10 SH6/SMCCS3n C5 SU3/LCLFP A12 DVSSCOM38 F7 SU4/LCLLP D10 SH3/SMCCS0n F6 PK7/LD23 A11 SJ6/DMCCKE B2 DVCC1A14 F10 DVCCM15 C10 SH4/SMCCS1n C11 SH7/DMCCSn A10 DVSSCOM39 G11 SL7/SMCWAITn A9 DVCC1A12 G10 PK1/LD17 B9 PK0/LD16 D9 DVCC3LCD1 C9 ST2/LD2 E9 ST1/LD1 A8 ST0/LD0 H11 DVSSCOM40 B8 PK4/LD20 F9 PK3/LD19 A7 PK2/LD18 D8 DVCC3LCD2 B7 ST5/LD5 G9 ST4/LD4 C8 ST3/LD3 H10 DVSSCOM41 A6 SU0/LCLCP E8 PK6/LD22 B6 PK5/LD21 D7 DVCC3LCD3 C7 PJ0/LD8 H8 ST7/LD7 B5 ST6/LD6 J9 DVSSCOM42 A5 DVCC1A13 F8 SU7/LPRG2 B4 SU6/LPRG1 K7 SU5/LPRG0 Note: Power supply signals that are indicated in bold and shaded will not be output to the balls as they are connected to the other power supplies of the same type on the board inside BGA. TMPA910CRA- 10 2010-06-02 TMPA910CRA 2.2 Pin Names and Functions The names and functions of I/O pins are shown below. Pins associated with memory are switched to either of two types of MPMC (MPMC0/1) depending on the status of the external pin "SELMEMC". Table 2.2.1 Pin names and functions (1/8) Pin name Number of pins Input/Output Function Remarks - - Input/Output Data: Data bus D0 to D7 - - Input/Output Data: Data bus D8 to D15 - Input/Output Data: Data bus D16 to D23 - Input/Output Data: Data bus D24 to D31 - - Output Address: Address bus A0 to A7 - - Output Address: Address bus A8 to A15 - - Output Address: Address bus A16 to A23 - - Output Address: Address bus A24 to A25 - - Output Byte enable signal (D0 to D7) for NORF/SRAM/MROM - - Output Byte enable signal (D8 to D15) for NORF/SRAM/MROM - - Output Byte enable signal (D16 to D23) for NORF/SRAM/MROM - - Output Byte enable signal (D24 to D31) for NORF/SRAM/MROM - - Output Chip select signal 0 for NORF/SRAM/MROM - - Output Chip select signal 1 for NORF/SRAM/MROM - - Output Chip select signal 2 for NORF/SRAM/MROM - - Output Chip select signal 3 for NORF/SRAM/MROM - - Output Chip select signal for SDR_SDRAM - When using MPMC0 DMCCSn Output Chip select signal for DDR_SDRAM When using MPMC1 SJ0 - - Output Out-enable signal for NORF/SRAM/MROM - For both MPMC0 and MPMC1 - - Output Write-enable signal for SDR_SDRAM - When using MPMC0 DMCWEn Output Write-enable signal for DDR_SDRAM When using MPMC1 SJ2 - - Output Row address strobe signal for SDR_SDRAM - When using MPMC0 Output Row address strobe signal for DDR_SDRAM When using MPMC1 SA0 to SA7 D0 to D7 SB0 to SB7 D8 to D15 SC0 to SC7 D16 to D23 SD0 to SD7 D24 to D31 SE0 to SE7 A0 to A7 SF0 to SF7 A8 to A15 SG0 to SG7 A16 to A23 SH0 to SH1 A24 to A25 8 8 8 8 8 8 8 2 SH2 SMCBE0n 1 SK5 SMCBE1n 1 SK6 SMCBE2n 1 SK7 SMCBE3n SH3 SMCCS0n SH4 SMCCS1n SH5 SMCCS2n SH6 SMCCS3n 1 1 1 1 1 SH7 DMCCSn SMCOEn 1 1 SJ1 DMCWEn DMCRASn DMCRASn 1 1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 - For both MPMC0 and MPMC1 Note: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." TMPA910CRA- 11 2010-06-02 TMPA910CRA Table 2.2.1 Pin names and functions (2/8) Pin name Number of Input/Output Function Remarks pins - - Output Column address strobe signal for SDR_SDRAM - When using MPMC0 DMCCASn Output Column address strobe signal for DDR_SDRAM When using MPMC1 SJ4 - - Output BANK0 strobe signal for SDR_SDRAM - When using MPMC0 DMCBA0 Output BANK0 strobe signal for DDR_SDRAM When using MPMC1 SJ5 - - Output BANK1 strobe signal for SDR_SDRAM - When using MPMC0 DMCBA1 Output BANK1 strobe signal for DDR_SDRAM When using MPMC1 SJ6 - - Output Clock-enable signal for SDR_SDRAM - When using MPMC0 DMCCKE Output Clock-enable signal for DDR_SDRAM When using MPMC1 SJ7 - - Output Address is valid for NORF/SRAM/MROM - For both MPMC0 and MPMC1 - - Output Byte enable signal (D0 to D7) for SDR_SDRAM - When using MPMC0 DMCDDM0 Output Data mask signal (D0 to D7) for DDR_SDRAM When using MPMC1 SK1 - - Output Byte enable signal (D8 to D15) for SDR_SDRAM - When using MPMC0 DMCDDM1 Output Data mask signal (D8 to D15) for DDR_SDRAM When using MPMC1 SK2 - - Output Byte enable signal (D16 to D23) for SDR_SDRAM - When using MPMC0 - - Not used When using MPMC1 SK3 - - Output Byte enable signal (D24 to D31) for SDR_SDRAM - When using MPMC0 - - Not used When using MPMC1 SK4 - - Output Write-enable signal for NORF/SRAM/MROM - For both MPMC0 and MPMC1 - - Output Clock signal for SDR_SDRAM - When using MPMC0 DMCDCLKP Output Positive phase clock signal for DDR_SDRAM When using MPMC1 SL1 - - - Not used - When using MPMC0 DMCDCLKN Output Negative phase clock signal for DDR_SDRAM When using MPMC1 SL2 - - Output Address/Precharge signal for SDR_SDRAM - When using MPMC0 DMCAP Output Address/Precharge signal for DDR_SDRAM When using MPMC1 SL3 - - Output Clock signal for NORF/SRAM/MROM - For both MPMC0 and MPMC1 - - - Not used - When using MPMC0 DMCDDQS0 Input/Output Data strobe signal (D0 to D7) for DDR_SDRAM When using MPMC1 SL5 - - - Not used - When using MPMC0 DMCDDQS1 Input/Output Data strobe signal (D8 to D15) for DDR_SDRAM When using MPMC1 SL6 - - Input FB clock for SDR/DDR_SDRAM - For both MPMC0 and MPMC1 - - Input WAIT signal for NORF/SRAM/MROM SJ3 DMCCASn DMCBA0 DMCBA1 DMCCKE SMCAVDn 1 1 1 1 1 SK0 DMCSDQM0 DMCSDQM1 DMCSDQM2 DMCSDQM3 SMCWEn 1 1 1 1 1 SL0 DMCSCLK - DMCAP SMCCLK 1 1 1 1 SL4 - - DMCCLKIN SL7 SMCWAITn 1 1 1 1 - For both MPMC0 and MPMC1 Note: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." TMPA910CRA- 12 2010-06-02 TMPA910CRA Table 2.2.1 Pin names and functions (3/8) Pin name SM0 X1 SM1 X2 SM2 XT1 SM3 XT2 Number of pins 1 1 1 1 SM4 RESETn SM5 TEST0n SM6 to SM7 AM0 to AM1 SN0 SELMEMC SN1 SELDVCCM SN2 SELJTAG SP0 TCK SP1 TMS SP2 TDI SP3 TRSTn SP4 RTCK SP5 TDO SR0 DP SR1 DM SR3 REXT SR4 VSENS ST0 to ST7 LD0 to LD7 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 8 Input/Output Function - - Input High-frequency oscillator connecting input pin - - Output High-frequency oscillator connecting output pin - - Input Low-frequency oscillator connecting input pin - - Output Low-frequency oscillator connecting output pin - - Input Reset: Initializes TMPA910CRA (with Schmitt input and pull-up resistor) - - Input TEST0n pin: fix to 1 level - - Input Startup mode input pins - - Input Memory controller selection pin - - Input Memory-related operating voltage selection pin - - Input Boundary scan switching pin - - Input Clock pin for JTAG - - Input Pin for JTAG - - Input Data input pin for JTAG - - Input Reset pin for JTAG - - Output Clock output pin for JTAG - - Output Data output pin for JTAG - - Input/Output USB pin (D+) - - Input/Output USB pin (D-) - - Input Connect to the VSENS pin at 12 k - - Input Connect to the REXT pin at 12 k - - Output Data bus LD0 to LD7 for LCD driver. Remarks - Note: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." TMPA910CRA- 13 2010-06-02 TMPA910CRA Table 2.2.1 Pin names and functions (4/8) Pin name SU0 LCLCP SU1 LCLAC SU2 LCLLE SU3 LCLFP SU4 LCLLP SU5 LPRG0 SU6 LPRG1 SU7 LPRG2 SV0 to SV7 NDD0 to NDD7 SW0 NDREn SW1 NDWEn SW2 NDALE SW3 NDCLE SW4 NDCE0n SW5 NDCE1n SW6 NDRB Number of pins 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 Input/Output Function - - Output LCD driver output pin - - Output LCD driver output pin - - Output LCD driver output pin - - Output LCD driver output pin - - Output LCD driver output pin - - Output LCD driver output pin - - Output LCD driver output pin - - Output LCD driver output pin - - Input/ Output Data buses for NANDF memory - - Output Read enable for NAND-Flash - - Output Write enable for NAND-Flash - - Output Address latch enable for NAND-Flash - - Output Command latch enable for NAND-Flash - - Output NAND-Flash0 chip select - - Output NAND-Flash1 chip select - - Input NAND-Flash Ready(1)/Busy(0) input Note: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." TMPA910CRA- 14 2010-06-02 TMPA910CRA Table 2.2.1 Pin names and functions (5/8) Pin name Number of pins PA0 to PA7 Input/Output Function Input Port A0 to A7: Input ports Input Key input KI0 to KI7: Pins for key-on wake up 0 to 7 (with Schmitt input and pull-up resistor) Output Port B0 to B7: Output ports Output Key output KO0 to KO7: Key out pins (open-drain can be set) Output Port C0 to C1: Output ports Output Key output KO8 to KO9: Key out pins (open-drain can be set) PC2 Output Port C2: Output port PWE Output External power source control output: KI0 to KI7 PB0 to PB7 KO0 to KO7 PC0 to PC1 KO8 to KO9 8 8 2 1 This pin controls ON/OFF of the external power source. The "H" level is output during regular operations, and the "L" level PC3 MLDALM is output during standby mode. Port C3: Output port Output Melody alarm output pin PWM0OUT Output Timer PWM out port PC4 Output Port C4: Output port Output Low-frequency output clock pin PWM2OUT Output Timer PWM out port PC5 Input/Output Port C5: I/O port MLDALMn Output Melody alarm reversed output pin Input Interrupt request pin8: an interrupt request pin that can program the rising/falling edge Input/Output Port C6: I/O port Input/Output I C clock I/O PC7 Input/Output Port C7: I/O port I2C0DA Input/Output I C data I/O Input Interrupt request pin9: an interrupt request pin that can program the rising/falling edge Input Port D0 to D3: Input ports Input Analog input 0 to 3: AD converter input pins Input Port D4: Input port Input Analog input 4: AD converter input pin MX Output X-minus: X-connecting pin for touch panel PD5 Input Port D5: Input port Input Analog input 4: AD converter input pin MY Output Y-minus: Y-connecting pin for touch panel PD6 Input Port D6: Input port PX Output X-plus: X-connecting pin for touch panel Input Interrupt request pin A: an interrupt request pin that can program the rising/falling edge PD7 Input Port D7: Input port PY Output FSOUT INT8 PC6 I2C0CL INT9 PD0 to PD3 AN0 to AN3 1 Output 1 1 1 1 4 PD4 AN4 AN5 INTA(TSI) INTB 1 1 1 1 PE0 to PE7 CMSD0 to CMSD7 PF0 CMSPCK PF1 CMSHSY 8 1 1 Input 2 2 Y-plus: Y-connecting pin for touch panel Interrupt request pin B: an interrupt request pin that can program the rising/falling edge Input Port E0 to E7: Input ports Input Data buses for CMOS sensor Input Port F0: Input port Input Clock input pin for CMOS sensor Input Port F1: Input port Input Horizontal synchronization input pin for CMOS sensor TMPA910CRA- 15 2010-06-02 TMPA910CRA Table 2.2.1 Pin names and functions (6/8) Pin name PF2 Number of pins Input/Output Function Input Port F2: Input port Input Input pin for CMOS sensor Input Port F3: Input port Input Input pin for CMOS sensor Input/Output Port F6: I/O port Input/Output I C clock I/O PF7 Input/Output Port F7: I/O port I2C1DA Input/Output I C data I/O Input Interrupt request pin C: an interrupt request pin that can program the rising/falling edge Input/Output Port G0 to G3: I/O port Input/Output Data I/O pin for SD card Input/Output Port G4: I/O port Input/Output Command I/O pin for SD card Input/Output Port G5: I/O port input Write-protect input pin for SD card Input/Output Port G6: I/O port Input Card detection input pin for SD card Input/Output Port G7: I/O port Input/Output Clock output pin for SD card Input/Output Port H0 to H3: I/O ports Input/Output Data I/O pins for SD card Input/Output Port H4: I/O port Input/Output Command I/O pin for SD card Input/Output Port H5: I/O port Input Write-protect input pin for SD card Input/Output Port H6: I/O port Input Card detection input pin for SD card Input/Output Port H7: I/O port Input/Output Clock output pin for SD card Output Port J0 to J7: Output ports Output Data buses for LCD driver Output Port K0 to K7: Output ports Output Data buses for LCD driver Input/Output Port L0: I/O port Input/Output I S0 word select Input/output SP1FSS Input/Output FSS pin for SSP1 PL1 Input/Output Port L1: I/O port Input/Output I S1 serial clock Input/output Input/Output Clock output pin for SSP1 Input/Output Port L2: I/O port Input I S0 receive serial data input SP1DO Output Data output pin for SSP1 PL3 Input/Output Port L3: I/O port Output I S0 master clock output for receive circuit SP1DI Output Data input pin for SSP1 PL4 Input/Output Port L4: I/O port Input I S external source clock pin CMSHBK PF3 CMSVSY PF6 I2C1CL INTC 1 1 1 1 PG0 to PG3 SDC0DAT0 to SDC0DAT3 PG4 SDC0CMD PG5 SDC0WP PG6 SDC0CD PG7 SDC0CLK 4 1 1 1 1 PH0 to PH3 SDC1DAT0 to SDC1DAT3 PH4 SDC1CMD PH5 SDC1WP PH6 SDC1CD PH7 SDC1CLK PJ0 to PJ7 LD8 to LD15 PK0 to PK7 LD16 to LD23 4 1 1 1 1 8 8 PL0 I2S0WS I2S0CLK 1 1 SP1CLK PL2 I2S0DATI I2S0MCLK I2SSCLK 1 1 1 2 2 2 2 2 2 2 TMPA910CRA- 16 2010-06-02 TMPA910CRA Table 2.2.1 Pin names and functions (7/8) Pin name PM0 Number of pins Input/Output Function Input/Output Port M0: I/O port Input/Output I S1 word select input/output Input/Output Port M1: I/O port Input/Output I S1 serial clock input/output Input/Output Port M2: I/O port Output I S1 transmission serial data output Input/Output Port M3: I/O port Output I S1 master clock output for transmission circuit Input/Output Port N0: I/O port Output UART function 0 transmission data Output Data output pin for IrDA1.0 Input/Output Port N1: I/O port Input UART function 0 receive data SIR0IN Input Data input pin for IrDA1.0 PN2 Input/Output Port N2: I/O port Input UART function 0 data can be transmitted (Clear to send) Input/Output Port N3: I/O port Input Modem status signal DCD (Data Carrier Detect) PN4 Input/Output Port N4: I/O port U0DSRn Input Modem status signal DSR (Data Set Ready) Input Interrupt request pin D: an interrupt request pin that can program the rising/falling edge PN5 Input/Output Port N5: I/O port U0RIn Input Modem status signal RI (Ring Indicator) Input Interrupt request pin E: an interrupt request pin that can program the rising/falling edge PN6 Input/Output Port N6: I/O port U0DTRn Output Output modem control line DTR (Data Terminal Ready) Input Interrupt request pin F: an interrupt request pin that can program the rising/falling edge PN7 Input/Output Port N7: I/O port U0RTSn Output Output modem control line RTD (Request To Send) Input Interrupt request pin G: an interrupt request pin that can program the rising/falling edge Input/Output Port P0 to P7: I/O ports Input Interrupt request pins 0 to 7: interrupt request pins that can program the rising/falling edge Output Port R0: Output port Output Reset output pin Output Port R1: Output port Output Write-protect control pin for memory FCOUT Output High-frequency clock output pin PR2 Input/Output Port R2: I/O port Input Interrupt request pin H: an interrupt request pin that can program the rising/falling edge Input/Output Port T0: I/O port Input/Output FSS pin for SSP0 Input/Output Port T1: I/O port Input/Output Clock pin for SSP0 Input/Output Port T2: I/O port Output Data output pin for SSP0 Input/Output Port T3: I/O port Input Data input pin for SSP0 I2S1WS PM1 I2S1CLK PM2 I2S1DATO PM3 I2S1MCLK 1 1 1 1 PN0 U0TXD 1 SIR0OUT PN1 U0RXD U0CTSn PN3 U0DCDn INTD INTE INTF INTG 1 1 1 1 1 1 1 PP0 to PP7 INT0 to INT7 PR0 RESETOUTn 8 1 PR1 SMCWPn INTH PT0 SP0FSS PT1 SP0CLK PT2 SP0DO PT3 SP0DI 1 1 1 1 1 1 2 2 2 2 TMPA910CRA- 17 2010-06-02 TMPA910CRA Table 2.2.1 Pin names and functions (8/8) Pin name PT4 U1TXD PT5 U1RXD PT6 U1CTSn PT7 X1USB Number of pins 1 1 1 1 Input/Output Function Input/Output Port T4: I/O port Output UART function 1 transmission data Input/Output Port T5: I/O port Input UART function 1 receive data Input/Output Port T6: I/O port Input UART function 1 data can be transmitted (Clear to send) Input/Output Port T7: I/O port Input Clock input pin for USB DVCC1Ax 14 Power supply VCC power supply for the main internal area DVCC1B 2 Power supply VCC power supply for the internal B/U area DVCC1C 2 Power supply VCC power supply for high-frequency clock/PLL circuit DVSS1C 1 Power supply VSS power supply for high-frequency clock/PLL circuit DVCC3IO 13 Power supply VCC power supply for external I/O (general) DVCCM 12 Power supply VCC power supply for external I/O (for memory) DVCC3LCD 5 Power supply VCC power supply for external I/O (LCD) DVCC3I2S 2 Power supply VCC power supply for external I/O (I S) 2 DVCC3CMS 2 Power supply VCC power supply for external I/O (CMOS_IS) AVCC 1 Power supply VCC power supply for external I/O (A/DC) AVSS 1 Power supply VSS power supply for external I/O (A/DC) VREFH 1 Input Reference voltage for A/D converter VREFL 1 Input Reference voltage for A/D converter AVDD3Tx 2 Power supply VDD power supply for external I/O (USB) AVSS3Tx 5 Power supply VSS power supply for external I/O (USB) AVDD3C 1 Power supply VCC power supply for external I/O (USB) AVSS3C 1 Power supply VSS power supply for external I/O (USB) DVSSCOMx 36 Power supply Common VSS power supply (GND) TMPA910CRA- 18 2010-06-02 TMPA910CRA Pin Functions and Initial Values Arranged by Type of Power Supply - 1 (DVCCM ) Power supply Typical pin to be used name Alternative Alternative Pull Input buffer Initial value after reset function function up/down SA0 to SA7 D0 to D7 SB0 to SB7 D8 to D15 ON D8 to D15 / Hz* SC0 to SC7 D16 to D23 ON D16 to D23 / Hz* SD0 to SD7 D24 to D31 ON D24 to D31 / Hz* SE0 to SE7 A0 to A7 Address out / "L" output ON function/pin state D0 to D7 / Hz* SF0 to SF7 A8 to A15 Address out / "L" output SG0 to SG7 A16 to A23 Address out / "L" output SH0 to SH1 A24 to A25 Address out / "L" output SH2 SMCBE0n SMCBE0n out / "H" output SK5 SMCBE1n SMCBE1n out / "H" output SK6 SMCBE2n SMCBE2n out / "H" output SK7 SMCBE3n SMCBE3n out / "H" output SH3 SMCCS0n SMCCS0n out / "H" output SH4 SMCCS1n SMCCS1n out / "H" output SH5 SMCCS2n SMCCS2n out / "H" output SH6 SMCCS3n SMCCS3n out / "H" output SH7 DMCCSn DMCCSn out / "H" output SJ0 SMCOEn SMCOEn out / "H" output SJ1 DMCWEn DMCWEn out / "H" output SJ2 DMCRASn DMCRASn out / "H" output SJ3 DMCCASn DMCCASn out / "H" output SJ4 DMCBA0 DMCBA0n out / "L" output SJ5 DMCBA1 DMCBA1n out / "L" output SJ6 DMCCKE DMCCKEn out / "H" output SJ7 SMCAVDn SMCAVDn out / "H" output DVCCM When SELMEMC = 0 SK0 DMCSDQM0 DMCDDM0 DMCSDQM0 out / "L" output When SELMEMC = 1 DMCDDM0 out / "L" output When SELMEMC = 0 SK1 DMCSDQM1 DMCDDM1 DMCSDQM1 out / "L" output When SELMEMC = 1 DMCDDM1 out / "L" output When SELMEMC = 0 SK2 DMCSDQM2 DMCSDQM2 out / "L" output When SELMEMC = 1 Invalid signal// "L" output When SELMEMC = 0 SK3 DMCSDQM3 SK4 SMCWEn DMCSDQM3 out / "L" output When SELMEMC = 1 Invalid signal/ "L" output Note 1: SMCWEn out / "H" output Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. The data bus pins (SA0-SA7, SB0-SB7, SC0-SC7, SD0-SD7) are always enabled as inputs. These pins must be tied externally (pulled up/down, etc.) to prevent flow-through current. TMPA910CRA- 19 2010-06-02 TMPA910CRA Pin Functions and Initial Values Arranged by Type of Power Supply - 2 (DVCCM) Power supply to be used Typical pin name SL0 Alternative Alternative Pull function function up/down DMCSCLK DMCDCLKP Input buffer Initial value after reset function/pin state When SELMEMC = 0 DMCSCLK out / CLK output When SELMEMC = 1 DMCDCLKP out / CLK output When SELMEMC = 0 Invalid signal/ "H" output SL1 DMCDCLKN SL2 DMCAP DMCAP out / "L" output SL3 SMCCLK SMCCLK out / "L" output SL4 DMCDDQS0 ON DMCDDQS0 / Hz* SL5 DMCDDQS1 ON DMCDDQS1 / Hz* SL6 DMCCLKIN ON DMCCLKIN input / Hz SL7 SMCWAITn ON When SELMEMC = 1 DMCDCLKN out /Inverted CLK output DVCCM SMCWAITn input / Hz RESETOUTn output / PR0 RESETOUTn PR1 FCOUT SMCWPn Port out / "L" output PR2 INTH ON INTH Input / Hz During reset: "L" output After reset: "H" output Note 1: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. When DDR SDRAM is used, the DQS signals (DMCDDQS0, DMCDDQS1) are always enabled as inputs. These pins must be tied externally (pulled up/down, etc.) to prevent flow-through current. TMPA910CRA- 20 2010-06-02 TMPA910CRA Pin Functions and Initial Values Arranged by Type of Power Supply - 3 (DVCC3IO) Power supply to be used Alternative Alternative Pull Input Initial state after reset function function up/down buffer function/pin state SM2 XT1 Oscillating SM3 XT2 Oscillating SM4 RESETn PU ON RESETn input / "H" output SM5 TEST0n ON TEST0n input / Hz SM6 AM0 ON AM0 input / Hz SM7 AM1 ON AM1 input / Hz SN0 SELMEMC ON SELMEMC input / Hz SN1 SELDVCCM ON SELDVCCM input / Hz SN2 SELJTAG ON SELJTAG input / Hz SP0 TCK ON TCK input / Hz SP1 TMS ON TMS input/ Hz SP2 TDI ON TDI input / Hz SP3 TRSTn ON TRSTn input / Hz SP4 RTCK RTCK out / CLK output SP5 TDO TDO out / TDO output SV0 to SV7 NDD0 to NDD7 OFF SW0 NDREn NDREn out / "H" output SW1 NDWEn NDWEn out / "H" output SW2 NDALE NDALE out / "L" output SW3 NDCLE NDCLE out / "L" output SW4 NDCE0n NDCE0n out / "H" output SW5 NDCE1n NDCE1n out / "H" output SW6 NDRB ON NDRB input / Hz PA0 to PA7 KI0 to KI7 PU ON PA0 to PA7 input / "H" output PB0 to PB7 KO0 to KO7 PB0 to PB7 out / "H" output Typical pin name DVCC3IO Note 1: NDD0 to NDD7 / Hz Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. The data bus pins for NAND Flash memory (NDD0-NDD7) are disabled as inputs in the initial state. TMPA910CRA- 21 2010-06-02 TMPA910CRA Pin Functions and Initial Values Arranged by Type of Power Supply - 4 (DVCC3IO) Power supply to be used Typical pin name Alternative Alternative Pull Input buffer Initial state after reset function function up/down PC0 KO8 PC0 out / "H" output PC1 KO9 PC1 out / "H" output PC2 PWE PWE out / "H" output PC3 MLDALM PWM0OUT PC3 out / "H" output PC4 FSOUT PWM2OUT PC4 out / "L" output PC5 MLDALMn INT8 ON PC5 input / Hz PC6 I2C0CL ON PC6 input / Hz PC7 I2C0DA INT9 ON PC7 input / Hz PG0 SDC0DAT0 ON PG0 input / Hz PG1 SDC0DAT1 ON PG1 input / Hz PG2 SDC0DAT2 ON PG2 input / Hz PG3 SDC0DAT3 ON PG3 input / Hz PG4 SDC0CMD ON PG4 input / Hz PG5 SDC0WP ON PG5 input / Hz PG6 SDC0CD ON PG6 input / Hz PG7 SDC0CLK ON PG7 input / Hz PH0 SDC1DAT0 ON PH0 input / Hz PH1 SDC1DAT1 ON PH1 input / Hz PH2 SDC1DAT2 ON PH2 input / Hz PH3 SDC1DAT3 ON PH3 input / Hz PH4 SDC1CMD ON PH4 input / Hz PH5 SDC1WP ON PH5 input / Hz PH6 SDC1CD ON PH6 input / Hz PH7 SDC1CLK ON PH7 input / Hz PN0 U0TXD SIR0OUT ON PN0 input / Hz PN1 U0RXD SIR0IN ON PN1 input / Hz PN2 U0CTSn ON PN2 input / Hz PN3 U0DCDn ON PN3 input / Hz PN4 U0DSRn INTD ON PN4 input / Hz PN5 U0RIn INTE ON PN5 input / Hz PN6 U0DTRn INTF ON PN6 input / Hz PN7 U0RTSn INTG ON PN7 input / Hz PP0 to PP7 INT0 to INT7 ON PP0 to PP7 input / Hz PT0 SP0FSS ON PT0 input / Hz PT1 SP0CLK ON PT1 input / Hz PT2 SP0DO ON PT2 input / Hz PT3 SP0DI ON PT3 input / Hz PT4 U1TXD ON PT4 input / Hz PT5 U1RXD ON PT5 input / Hz PT6 U1CTSn ON PT6 input / Hz PT7 X1USB ON PT7 input / Hz DVCC3IO Note 1: function/pin state Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. TMPA910CRA- 22 2010-06-02 TMPA910CRA Pin Functions and Initial Values Arranged by Type of Power Supply - 5 (DVCC3LCD) Power supply to be used Typical pin name Alternative Alternative Pull Input Initial value after reset function function up/down buffer function/pin state ST0 to ST7 LD0 to LD7 LD0 to LD7 out / "L" output SU0 LCLCP LCLCP out / "L" output SU1 LCLAC LCLAC out / "L" output SU2 LCLLE LCLLE out / "L" output SU3 LCLFP LCLFP out / "L" output SU4 LCLLP LCLLP out / "L" output SU5 LPRG0 LPRG0 out / "L" output SU6 LPRG1 LPRG1 out / "L" output SU7 LPRG2 LPRG2 out / "L" output PJ0 to PJ7 LD8 to LD15 PJ0 to PJ7 out / "L" output PK0 to PK7 LD16 to LD23 PK0 to PK7 out / "L" output DVCC3LCD Note 1: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. Pin Functions and Initial Values Arranged by Type of Power Supply - 6 (DVCC3CMS) Power supply to be used Alternative Alternative Pull Input Initial value after reset function function up/down buffer function/pin state PE0 to PE7 CMSD0 to CMSD7 ON PE0-PE7 input / Hz PF0 CMSPCK ON PF0 input / Hz PF1 CMSHSY ON PF1 input / Hz PF2 CMSHBK ON PF2 input / Hz PF3 CMSVSY ON PF3 input / Hz PF6 I2C1CL ON PF6 input / Hz PF7 I2C1DA INTC ON PF7 input / Hz Typical pin name DVCC3CMS Note 1: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. TMPA910CRA- 23 2010-06-02 TMPA910CRA Pin Functions and Initial Values Arranged by Type of Power Supply - 7 (DVCC3I2S) Power supply to be used Alternative Alternative Pull Input Initial state after reset function function up/down buffer function/pin state PL0 I2S0WS SP1FSS ON PL0 input / Hz PL1 I2S0CLK SP1CLK ON PL1 input / Hz PL2 I2S0DATI SP1DO ON PL2 input / Hz PL3 I2S0MCLK SP1DI ON PL3 input / Hz PL4 I2SSCLK ON PL4 input / Hz PM0 I2S1WS ON PM0 input / Hz PM1 I2S1CLK ON PM1 input / Hz PM2 I2S1DATO ON PM2 input / Hz PM3 I2S1MCLK ON PM3 input / Hz Typical pin name DVCC3I2S Note 1: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. Pin Functions and Initial Values Arranged by Type of Power Supply - 8 (AVCC3AD) Power supply to be used AVCC3AD Note 1: Pull Input Initial state after reset Alternative Alternative function function up/down PD0 AN0 OFF AN0 input / Hz PD1 AN1 OFF AN1 input / Hz PD2 AN2 OFF AN2 input / Hz PD3 AN3 OFF AN3 input / Hz PD4 AN4 MX OFF AN4 input / Hz PD5 AN5 MY OFF AN5 input / Hz PD6 INTA(TSI) PX PD* ON PD6 input / Hz PD7 INTB PY ON PD7 input / Hz Typical pin name buffer function/pin state Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. Note 3: The pull-down resistor for PD6 is disabled after reset. TMPA910CRA- 24 2010-06-02 TMPA910CRA Pin Functions and Initial Values Arranged by Type of Power Supply - 9 (USB) Power supply to be used Alternative Alternative Pull Input Initial value after reset function function up/down buffer function/pin state SR0 DP PD ON DP input / "L" output SR1 DM PD ON DM input / "L" output SR3 REXT REXT input / Hz SR4 VSENS VSENS input / Hz Typical pin name AVDD3C/T Note 1: Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. The D+ and D- signals for USB contain a pull-down resistor in PHY. Pin Functions and Initial Values Arranged by Type of Power Supply - 10 (OSC) Power supply to be used Typical pin name DVCC1C Note 1: Alternative function Alternative function Pull Input Initial value after reset up/down buffer function/pin state SM0 X1 Oscillating SM1 X2 Oscillating Pin names "SA0 through SA7, ..., and SW0 through SW6" are symbols used for convenience and are different from general-purpose port functions "PA0 through PA7, ..., and PT0 through PT7." Note 2: When the "Input buffer" column shows "ON", the pin is enabled as an input in the initial state. If necessary, the pin should be processed externally. TMPA910CRA- 25 2010-06-02 TMPA910CRA 3. Operational Description This chapter provides a brief description of the CPU circuitry of the TMPA910CRA. 3.1 CPU This section describes the basic operations of the CPU of the TMPA910CRA for each block. Note that this document provides only an overview of the CPU block. Please contact ARM Holdings for details of the operation. The TMPA910CRA has a built-in 32-bit RISC processor ARM926EJ-S manufactured by ARM. The schematic diagram of the ARM926EJ-S core is shown below. CPU core (ARM9EJ-STM) Data cache 16KB MMU Instruction cache 16KB WB AMBATM AHB I/F for data AMBA AHB I/F for instruction Figure 3.1.1 ARM926EJ-S core The TMPA910CRA does not contain the functions shown below. 1. Coprocessor I/F 2. Embedded ICE RT 3. TCM I/F 4. ETM9TM I/F 5. Version of CPU is controlled by ARM Limited, version of CPU is r0p5. TMPA910CRA- 26 2010-06-02 TMPA910CRA 3.1.1 Reset Operation Before resetting the TMPA910CRA, make sure that the power supply voltage is within the operating range, oscillation from the internal oscillator is stable at 20 system clock cycles (0.8 s @ X1 = 25 MHz) at least, and the RESETn input pin is pulled Low. When the TMPA910CRA is reset, the PLL stops, the PLL output is unselected, and the clock gear is set to TOP (1/1). The system clock therefore operates at 25 MHz (X1 = 25 MHz). If the reset instruction is accepted, the built-in I/O, I/O ports and other pins are initialized. Reset the registers of the built-in I/O. (Refer to the chapter on ports or on Pin, for reset values.) Note 1: The IC has a built-in RAM, but its data may be lost due to the reset operation. Initialize data in the built-in RAM after the reset operation. Note 2: Although this IC cuts off some of the power supplies (DVCC1A, DVCC1C, AVDD3Tx,AVDD3Cx) to reduce standby current (PCM function), the reset operation may cause current penetration within the IC if it is executed while power to be cut off (DVCC1A, DVCC1C, AVDD3Tx, ADCC3Cx) is not being supplied. Before executing the reset operation, make sure that the power supply to be cut off (DVCC1A, DVCC1C, AVDD3Tx, AVDD3Cx) is sufficiently stable. Although the original ARM926EJ-S allows selection of a vector location immediately after reset operation and endianness, they are already set as follows for this IC. Endian Boot vector Little endian 0x00000000 TMPA910CRA- 27 2010-06-02 TMPA910CRA 3.1.2 Exceptions The TMPA910CRA includes 7 types of exception, and each of them has privileged processing mode. Exception Address Note Reset 0x00000000 Undefined instruction execution 0x00000004 Software interrupt (SWI) instruction 0x00000008 It is used for operating system call. Pre-fetch abort 0x0000000C Instruction fetch memory abort Data abort 0x00000010 Data access memory abort IRQ 0x00000018 Normal interrupt FIQ 0x0000001C High-speed interrupt TMPA910CRA- 28 2010-06-02 TMPA910CRA Multilayer AHB The TMP910CRA uses a multilayer AHB bus system with 7 layers. Data Cache 16 KB Instruction Cache 16 KB ARM926EJ-S (Bus Master 1 & 2) Bus Interface CPU Inst. LCD Controller LCDC CPU Data. DMA Controller DMA1 DMA2 (Bus Master 3) (Bus Master 5&6) LCD Data Process Accelerator LCDDA USB Device Controller USB (Bus Master 7) (Bus Master 4) Interrupt Controller A/D Converter (6 ch) CPU Data Touch Screen I/F I2S I/F (2 ch) 16-bit Timer/PWM (6ch) NANDF Controller (2 ch) I2C I/F (2 ch) SD Host Controller (2 ch) Synchronous Serial Port (2 ch) CPU Data CPU Data APB Bridge Power Management Multilayer Bus Matrix 1 3.1.3 UART (2 ch) RTC/Melody Watch Dog Timer System Controller DMA1 DMA2 PLL Clock Gear CMOS Image Sensor I/F General Purpose I/O Key board matrix External Interruption DMA1 DMA2 CPU Inst. CPU Data. LCDDA LCDC USB Multilayer Bus Matrix 0 Internal RAM0 16 KB Internal RAM1 16 KB Internal RAM2 16 KB Internal RAM3 8 KB Multilayer Bus Multilayer Bus Matrix 3 Matrix 2 Memory Controller Memory Controller NORF SRAM SDR SDRAMC NORF SRAM DDR SDRAMC Boot ROM 16 KB TMPA910CRA- 29 External Bus Interface 2010-06-02 TMPA910CRA 3.2 JTAG Interface 3.2.1 Overview The TMPA910CRAXBG provides a boundary-scan interface that is compatible with Joint Test Action Group (JTAG) specifications and uses the industry-standard JTAG protocol (IEEE Standard 1149.1*1990 <Includes IEEE Standard 1449.1a*1993>). This chapter describes the JTAG interface, with the descriptions of boundary scan and the pins and signals used by the interface. 1) JTAG standard version IEEE Standard 1149.1*1990 (Includes IEEE Standard 1149.1a*1993) 2) JTAG instructions Standard instructions (BYPASS, SAMPLE/PRELOAD, EXTEST) HIGHZ instruction CLAMP instruction 3) IDCODE Not available 4) Pins excluded from boundary scan register (BSR) a) Oscillator circuit pins (SM0-3) b) USB pins (SR0, SR1, SR3, SR4) c) JTAG control pins (SN2, SP0-5) d) Power supply/GND pins (including VREFH, REFL) e) A/D pins (PD0-5) f) Touch panel PX and PY pins (PD6, PD7) Note: PR2 pin is I/O pin. However, PR2 pin does not support the capture function by using SAMPLE/PRELOAD instructions because the BSR for the output is connected to the pin. TMPA910CRA- 30 2010-06-02 TMPA910CRA 3.2.2 Signal Summary and Connection Example The JTAG interface signals are listed below. TDI JTAG serial data input TDO JTAG serial data output TMS JTAG test mode select TCK JTAG serial clock input TRSTn JTAG test reset input RTCK JTAG test feedback serial clock output SELJTAG ICE/JTAG test select input (compatible with the Enable signal) 0: ICE 1: JTAG The TMPA910CRA supports debugging by connecting the JTAG interface with a JTAG-compliant development tool. For information about debugging, refer to the specification of the development tool used. Note TMPA910CRAXBG TDI TDO TMS JTAG TOOL TCK TRSTn SELJTAG RTCK Note: In the case of not using JTAG Tool, fix the TRSTn pin to GND. In the case of using JTAG Tool, Once set the TRSTn pin to "Low" level to reset the JTAG Circuits, and then translate to "High" level. Pull-up resistance is built in some JTAG Tools, the value of external pull-up resistance need to be considered according to the JTAG Tools. Figure 3.2.1 Example of connection with a JTAG development tool Mode Setting Pin SELJTAG Operation mode Set this pin to 0 except for Boundary Scan Mode. 0 The TMPA910CRA operates as regular Debug Mode. Note: Debugging is not available if the internal BOOT is carried out with AM1 = 1 and AM0 = 1. 1 The TMPA910CRA operates in Boundary Scan Mode TMPA910CRA- 31 2010-06-02 TMPA910CRA 3.2.3 Outline of Boundary Scan With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices, double-sided component mounting on printed-circuit boards (PCBs), and set-in recesses, in-circuit tests that depend upon physical contact like the connection of the internal board and chip has become more and more difficult to use. The more ICs have become complex, the lager and more difficult the test program became. As one of the solutions, boundary-scan circuits started to be developed. A boundary-scan circuit is a series of shift register cells placed between the pins and the internal circuitry of the IC to which the said pins are connected. Normally, these boundary-scan cells are bypassed; when the IC enters test mode, however, the scan cells can be directed by the test program to pass data along the shift register path and perform various diagnostic tests. To accomplish this, the tests use the six signals, TCK, TMS, TDI, TDO, RTCK and TRSTn. The JTAG boundary-scan mechanism (hereinafter referred to as JTAG mechanism in the chapter) allows testing of the connections between the processor, the printed circuit board to which it is attached, and the other components on the circuit board. The JTAG mechanism cannot test the processor alone. TMPA910CRA- 32 2010-06-02 TMPA910CRA 3.2.4 JTAG Controller and Registers The processor contains the following JTAG controller and registers: Instruction register Boundary scan register Bypass register Device identification register Test Access Port (TAP) controller JTAG basically operates to monitor the TMS input signal with the TAP controller state machine. When the monitoring starts, the TAP controller determines the test functionality to be implemented. This includes both loading the JTAG instruction register (IR) and beginning a serial data scan through a data register (DR), as shown in Table 3.2.1. As the data is scanned, the state of the TMS pin signals each new data word and indicates the end of the data stream. The data register is selected according to the contents of the instruction register. 3.2.5 Instruction Register The JTAG instruction register includes four shift register-based cells. This register is used to select the test to be performed and/or the test data register to be accessed. As listed in Table 3.2.1, this instruction codes select either the boundary scan register or the bypass register. Table 3.2.1 JTAG Instruction Register Bit Configuration Instruction code (MSB to LSB) Instruction Selected data register 0000 EXTEST Boundary scan register 0001 SAMPLE/PRELOAD Boundary scan register 0100 to 1110 Reserved Reserved 0010 HIGHZ Bypass register 0011 CLAMP Bypass register 1111 BYPASS Bypass register Figure 3.2.2 shows the format of the instruction register. 3 2 1 0 MSB LSB Figure 3.2.2 Instruction register The instruction code is shifted out to the instruction register from the LSB. Bypass Register MSB LSB TDI TDO Figure 3.2.3 Instruction Register Shift Direction TMPA910CRA- 33 2010-06-02 TMPA910CRA The bypass register is 1 bit wide. When the TAP controller is in the Shift-DR (bypass) state, the data on the TDI pin is shifted into the bypass register, and the bypass register output shifts to the date out on the TDO output pin. In essence, the bypass register is an alternative route which allows bypassing of board-level devices in the serial boundary-scan chain, which are not required for a specific test. The logical location of the bypass register in the boundary-scan chain is shown in Figure 3.2.4. Use of the bypass register speeds up access to the boundary scan register in the IC that remains active in the board-level test data path. TDI B oard in put TDO B oa rd o utp ut Byp ass Reg is ter TDO TDI TDO TDI TDI TDO TDI TDO B oundary scan regist er pa d cell I C packag e Bo ard Figure 3.2.4 Bypass Register Operation TMPA910CRA- 34 2010-06-02 TMPA910CRA 3.2.6 Boundary Scan Register The boundary scan register provides all the inputs and outputs of the TMPA910CRA processor except some analog outputs and control signals. The pins of the TMPA910CRA allow any pattern to be driven by scanning the data into the boundary scan register in the Shift-DR state. Incoming data to the processor is examined by enabling the boundary scan register and shifting the data when the BSR is in the Capture-DR state. The boundary scan register is a single, 231-bit-wide, shift register-based path containing cells connected to the input and output pads on the TMPA910CRA. The TDI input is loaded to the LSB of the boundary scan register. The MSB of the boundary scan register is shifted out on the TDO output. 3.2.7 Test Access Port (TAP) The Test Access Port (TAP) consists of the five signal pins: TRSTn, TDI, TDO, TMS and TCK. These pins control a test by communicating the serial test data and instructions. As Figure 3.2.5 shows, data is serially scanned into one of the three registers (instruction register, bypass register or boundary scan register) on the TDI pin, or it is scanned out from one of these three registers on the TDO pin. The TMS input controls the state transitions of the main TAP controller state machine. The TCK input is a special test clock that allows serial JTAG data to be shifted synchronously, independent of any chip-specific or system clocks. TCK TMS and TDI are sampled on the rising edge of TCK. TDO is sampled on the falling edge of TCK. Data is scanned out serially. Data is scanned in serially. 3 0 3 Instruction register 0 Instruction register 0 0 Bypass register Bypass register TDO pin TDI pin 115 0 Boundary scan register 0 115 TMS pin Boundary scan register Figure 3.2.5 JTAG Test Access Port Data on the TDI and TMS pins are sampled on the rising edge of the TCK input clock signal. Data on the TDO pin changes on the falling edge of the TCK clock signal. TMPA910CRA- 35 2010-06-02 TMPA910CRA 3.2.8 TAP Controller The processor incorporates the 16-state TAP controller stipulated in the IEEE JTAG specification. 3.2.9 Resetting the TAP Controller The TAP controller state machine can be put into the Reset state by the following method. Assertion of the TRSTn signal input (low) resets the TAP controller. After the processor reset state is released, keep the TMS input signal asserted through five consecutive rising edges of TCK input. Keeping TMS asserted maintains the Reset state. 3.2.10 State Transitions of the TAP Controller The state transition diagram of the TAP controller is shown in Figure 3.2.6. Each arrow between states is labeled with a 1 or 0, indicating the logic value of TMS that must be set up before the rising edge of TCK to cause the transition. 1 T e s t-L o g ic -R e s e t 0 0 R u n -T e s t/Id le 1 S e le c t-D R -S c a n 1 S e le c t-IR -S c a n 0 0 C a p tu re -D R 1 C a p tu re -IR 1 0 0 S h ift-D R S h ift-IR 0 1 1 E x it 1 -IR 0 1 0 P a u s e -D R P a u s e -IR 0 1 0 1 E x it 2 -D R 0 E x it 2 -IR 1 1 U p d a te -D R 1 0 1 E x it 1 -D R 0 1 0 U p d a te -IR 1 0 Figure 3.2.6 TAP Controller State Transition Diagram TMPA910CRA- 36 2010-06-02 TMPA910CRA The following paragraphs describe each of the controller states. The left column in Figure 3.2.6 is the data column, and the right column is the instruction column. The data column and instruction column reference the data register (DR) and the instruction register (IR), respectively. * Test-Logic-Reset When the TAP controller is in the Reset state, the device identification register is selected by default. The MSB of the boundary scan register is cleared to 0 which disables the outputs. The TAP controller remains in this state while TMS is high. If TMS is held low while the TAP controller is in this state, then the controller moves to the Run-Test/Idle state. * Run-Test/Idle In the Run-Test/Idle state, the IC is put in test mode only when certain instructions such as a built-in self test (BIST) instruction are present. For instructions that do not cause any activities in this state, all test data registers selected by the current instruction retain their previous states. The TAP controller remains in this state while TMS is held low. When TMS is held high, the controller moves to the Select-DR-Scan state. * Select-DR-Scan This is a temporary controller state. Here, the IC does not execute any specific functions. If TMS is held low when the TAP controller is in this state, the controller moves to the Capture-DR state. If TMS is held high, the controller moves to the Select-IR-Scan state. * Select-IR-Scan This is a temporary controller state. Here, the IC does not execute any specific functions. If TMS is held low when the TAP controller is in this state, the controller moves to the Capture-IR state. IF TMS is held high, the controller returns to the Test-Logic-Reset state. * Capture-DR In this state, if the test data register selected by the current instruction has parallel inputs, then data is parallel-loaded into the shift portion of the data register. If the test data register does not have parallel inputs, or if data needs not be loaded into the selected data register, then the data register retains its previous state. If TMS is held low when the TAP controller is in this state, the controller moves to the Shift-DR state. If TMS is held high, the controller moves to the Exit 1-DR state. TMPA910CRA- 37 2010-06-02 TMPA910CRA * Shift-DR In this controller state, the test data register connected between TDI and TDO shifts data out serially. When the TAP controller is in this state, then it remains in the Shift-DR state if TMS is held low, or moves to the Exit 1-DR state if TMS is held high. * Exit 1-DR This is a temporary controller state. If TMS is held low when the TAP controller is in this state, the controller moves to the Pause-DR state. If TMS is held high, the controller moves to the Update-DR state. * Pause-DR This state allows the shifting of the data register selected by the instruction register to be temporarily suspended. Both the instruction register and the data register retain their current states. When the TAP controller is in this state, then it remains in the Pause-DR state if TMS is held low, or moves to the Exit 2-DR state. * Exit 2-DR This is a temporary controller state. When the TAP controller is in this state, it returns to the Shift-DR state if TMS is held low, or moves on to the Update-DR state if TMS is held high. * Update-DR In this state, data is latched, on the rising edge of TCK, onto the parallel outputs of the data registers from the shift register path. The data held at the parallel output does not change while data is shifted in the associated shift register path. When the TAP controller is in this state, it moves to either the Run-Test/Idle state if TMS is held low, or the Select-DR-Scan state if TMS is held high. * Capture-IR In this state, data is parallel-loaded into the instruction register. The data to be loaded is 0001. The Capture-IR state is used for testing the instruction register. Faults in the instruction register, if any, may be detected by shifting out the loaded data. When the TAP controller is in this state, it moves to either the Shift-IR state if TMS is held low, or the Exit 1-IR state if TMS is high. * Shift-IR In this state, the instruction register is connected between TDI and TDO and shifts the captured data toward its serial output on the rising edge of TCK. When the TAP controller is in this state, it remains in the Shift-IR state if TMS is low, or moves to the Exit 1-IR state if TMS is high. TMPA910CRA- 38 2010-06-02 TMPA910CRA * Exit 1-IR This is a temporary controller state. When the TAP controller is in this state, it moves to either the Pause-IR state if TMS is held low, or the Update-IR state if TMS is held high. * Pause-IR This state allows the shifting of the instruction register to be temporarily suspended. Both the instruction register and the data register retain their current states. When the TAP controller is in this state, it remains in the Pause-IR state if TMS is held low, or moves to the Exit 2-IR state if TMS is held high. * Exit 2-IR This is a temporary controller state. When the TAP controller is in this state, it moves to either the Shift-IR state if TMS is held low, or the Update-IR state if TMS is held high. * Update-IR This state allows the instruction previously shifted into the instruction register to be output in parallel on the rising edge of TCK. Then it becomes the current instruction, setting a new operational mode. When the TAP controller is in this state, it moves to either the Run-Test/Idle state if TMS is low, or the Select-DR-Scan state if TMS is high. TMPA910CRA- 39 2010-06-02 TMPA910CRA 3.2.11 Boundary Scan Order Table 3.2.2 shows the boundary scan order with respect to the processor signals. TDI -> 1(PF6) -> 2(PF7) ... -> 230(SU4) -> 231(PK7) -> TDO Table 3.2.2 JTAG Scan Order of the TMPA910CRA Processor Pins No. Pin Name No. Pin Name No. Pin Name No. Pin Name No. Pin Name No. Pin Name TDI 1 PF6 41 PG7 81 PM3 121 PP5 161 SG6 201 PK0 2 PF7 42 PH5 82 PM1 122 PP6 162 SE6 202 ST2 3 PF1 43 PG6 83 PL3 123 PP7 163 SE7 203 ST1 4 PE7 44 PG1 84 PL0 124 PA0 164 SF1 204 ST0 5 PF2 45 PG0 85 PR0 125 PA1 165 SF6 205 PK4 6 PF3 46 PH6 86 PR1 126 PA2 166 SF7 206 PK3 7 PF0 47 PH4 87 SC3 127 PA3 167 SF0 207 PK2 8 PE6 48 PH2 88 SA0 128 PA4 168 SG0 208 ST5 9 PE3 49 PH1 89 SC6 129 PA5 169 SK3 209 ST4 10 PE4 50 PH0 90 SC5 130 PA6 170 SK2 210 ST3 11 PE5 51 PH7 91 SL6 131 PA7 171 SL2 211 SU0 12 PE0 52 PH3 92 SC4 132 PB0 172 SG7 212 PK6 13 PE1 53 SW6 93 SC1 133 PB1 173 SJ4 213 PK5 14 PE2 54 SW4 94 SA1 134 PB2 174 SJ5 214 PJ0 15 PT2 55 SW5 95 SA2 135 SM5 175 SH1 215 ST7 16 PT0 56 SW3 96 SC2 136 PB3 176 SK0 216 ST6 17 PN1 57 SV7 97 SC0 137 PB4 177 SH0 217 SU7 18 PN0 58 SW2 98 SA3 138 PB5 178 SK7 218 SU6 19 PT3 59 SW1 99 SA5 139 PB6 179 SJ2 219 SU5 20 PT1 60 SV3 100 SL4 140 PB7 180 SK5 220 PJ2 21 PT6 61 SV6 101 SL5 141 PC0 181 PR2 221 PJ1 22 PN4 62 SV2 102 SA6 142 PC1 182 SH2 222 SU2 23 PN7 63 SW0 103 SB0 143 SF2 183 SK6 223 PJ5 24 PN3 64 PP2 104 SA7 144 SD7 184 SK4 224 PJ4 25 PN5 65 SV5 105 SD0 145 SE2 185 SL0 225 PJ3 26 PN2 66 SV1 106 SA4 146 SE0 186 SL1 226 SU1 27 PN6 67 PP1 107 SB2 147 SG1 187 SK1 227 PJ7 28 PC4 68 SV4 108 SC7 148 SE3 188 SJ7 228 PJ6 29 PC3 69 SV0 109 SB3 149 SF3 189 SJ1 229 SU3 30 PC5 70 PP0 110 SD1 150 SD5 190 SL3 230 SU4 31 PC6 71 SM6 111 SD4 151 SE1 191 SJ0 231 PK7 32 PC2 72 SM7 112 SB6 152 SD6 192 SJ3 33 PT5 73 SN0 113 SB5 153 SE4 193 SH5 34 PT4 74 SN1 114 SD3 154 SG4 194 SH6 35 PC7 75 PT7 115 SB1 155 SG2 195 SH3 36 SM4 76 PM0 116 SD2 156 SF4 196 SJ6 37 PG5 77 PM2 117 SB7 157 SG5 197 SH4 38 PG4 78 PL2 118 SB4 158 SG3 198 SH7 39 PG3 79 PL4 119 PP3 159 SE5 199 SL7 PG2 80 PL1 120 PP4 160 SF5 200 PK1 40 TMPA910CRA- 40 TDO 2010-06-02 TMPA910CRA 3.2.12 Instructions Supported by the JTAG Controller Cells This section describes the instructions supported by the JTAG controller cells of the TMPA910CRA. (1) EXTEST instruction The EXTEST instruction is used for external interconnect tests. The EXTEST instruction permits BSR cells at output pins to shift out test patterns in the Update-DR state and those at input pins to capture test results in the Capture-DR state. Typically, before EXTEST is executed, the initialization pattern is shifted into the boundary scan register using the SAMPLE/PRELOAD instruction. If the boundary scan register is not reset, indeterminate data will be transferred in the Update-DR state and bus conflicts between ICs may occur. Figure 3.2.7 shows data flow when the EXTEST instruction is selected. Boundary scan path Input Core logic TDI Output TDO Figure 3.2.7 Test Data Flow when the EXTEST Instruction is Selected The following steps describe the basic test procedure of the external interconnect test. 1. Reset the TAP controller to the Test-Logic-Reset state. 2. Load the instruction register with the SAMPLE/PRELOAD instruction. This causes the boundary scan register to be connected between TDI and TDO. 3. Reset the boundary scan register by shifting certain data in. 4. Load the test pattern into the boundary scan register. 5. Load the instruction register with the EXTEST instruction. 6. Capture the data applied to the input pin into the boundary scan register. 7. Shift out the captured data while simultaneously shifting the next test pattern in. 8. Send out the test pattern in the boundary scan register at the output on the output pin. Repeat steps 6 to 8 for each test pattern. TMPA910CRA- 41 2010-06-02 TMPA910CRA (2) SAMPLE/PRELOAD instruction This instruction targets the boundary scan register between TDI and TDO. As its name implies, the SAMPLE/PRELOAD instruction provides two functions. SAMPLE allows the input and output pads of an IC to be monitored. While it does so, it does not disconnect the system logic from the IC pins. SAMPLE is executed in the Capture-DR state. It is mainly used to capture the values of the IC's I/O pins on the rising edge of TCK during normal operation. Figure 3.2.8 shows the flow of data for the SAMPLE phase of the SAMPLE/PRELOAD instruction. Boundary scan path Input Core logic TDI Output TDO Figure 3.2.8 Test Data Flow while the SAMPLE is Selected PRELOAD allows the boundary scan register to be reset before any other instruction is selected. For example, prior to selection of the EXTEST instruction, PRELOAD is used to load reset data into the boundary scan register. PRELOAD permits data shifting of the boundary scan register without interfering with the normal operation of the system logic. Figure 3.2.9 shows the data flow for the PRELOAD phase of the SAMPLE/PRELOAD instruction. Boundary scan path Input Core logic TDI Output TDO Figure 3.2.9 Test Data Flow while PRELOAD is Selected TMPA910CRA- 42 2010-06-02 TMPA910CRA (3) BYPASS instruction This instruction targets the bypass register between JTDI and JTDO. The bypass register provides the shortest serial path that bypasses the IC (between JTDI and JTDO) when the test does not require control or monitoring of the IC. The BYPASS instruction does not cause interference in the normal operation of the on-chip system logic. Figure 3.2.10 shows the data flow through the bypass register when the BYPASS instruction is selected. Bypass register TDI TDO 1 bit Figure 3.2.10 Test Data Flow when the BYPASS Instruction is Selected (4) CLAMP instruction The CLAMP instruction outputs the value that boundary scan register is programmed according to the PRELOAD instruction, and execute Bypass operation. The CLAMP instruction selects the bypass register between TDI and TDO. (5) HIGHZ instruction The HIGHZ instruction disables the output of the internal logical circuits. When the HIGHZ instruction is executed, it places the 3-state output pins in the high-impedance state. The HIGHZ instruction also selects the bypass register between TDI and TDO. * Notes This section describes the cautions of the JTAG boundary-scan operations specific to the processor. 1) The PR2 pin serves as an I/O pin. However, the PR2 pin does not support the capture function by using SAMPLE/PRELOAD instructions because the BSR is connected to the pin. 2) The JTAG circuit can be released from the reset state by either of the following two methods: Assert TRSTn, initialize the JTAG circuit, and then deassert TRSTn. Supply the TCK signal for 5 or more clock pulses to TCK while pulling the TMS pin High. TMPA910CRA- 43 2010-06-02 TMPA910CRA 3.3 Memory Map The memory map of the TMPA910CRA is as follows: Table 3.3.1 Outline of Access to Internal Areas Characteristics Outline of Access CPU Address Width CPU Data Bus Width Internal Operation Frequency Minimum Bus Cycle Internal RAM Internal Boot ROM Internal I/O 32 bits 32 bits Max 200 MHz 1-fCLK clock access (5 ns at 200 MHz) 32-bit 1-HCLK clock access 32-bit 1-HCLK clock access 32-bit, 1-HCLK LCDC, LCDDA, INTC, DMAC, clock access USB Device, I2S, NANDFC, SDHC, SSP, CMSIF, MPMC 32-bit, 2-PCLK A/D C, TSI, Timer/PWM, PMC, I2C, UART, RTC, WDT, clock access System C, PLL CG, GPIO TMPA910CRA- 44 2010-06-02 TMPA910CRA Start Address 0x0000_0000 0x0000_2000 0x0000_4000 0x0100_0000 0x2000_0000 0x2100_0000 Internal BOOT ROM Mode Internal ROM: 8 KB + 8 KB External Memory Mode Remap area (8 KB) SMCCS0n SMCCS0n External area (15.8 MB) Reserved area External area (496 MB) Reserved area Reserved area External area (16 MB) Reserved area SMCCS0n External area (496 MB) SMCCS0n DMCCSn External area (512 MB) DMCCSn SMCCS1n External area (512 MB) SMCCS1n Reserved area External area (512 MB) Reserved area SMCCS2n External area (512 MB) SMCCS2n Reserved area External area (512 MB) Reserved area SMCCS3n External area (256 MB) SMCCS3n 0x4000_0000 0x6000_0000 0x8000_0000 0xA000_0000 0xC000_0000 0xE000_0000 0xF000_0000 Internal IO-0 (APB): 1 MB Internal IO-0 (APB): 1 MB 0xF010_0000 Reserved area Reserved area 0xF080_0000 Internal IO-1 (APB Port 1/2): 1 MB Internal IO-1 (APB Port1/2): 1 MB 0xF090_0000 Internal IO-2 (APB Port 2/2): 1 MB 0xF0A0_0000 Reserved area 0xF200_0000 Internal IO-3 (AHB + APB): 16 MB Internal I/O area (128 MB) Internal IO-2 (APB Port2/2): 1 MB Reserved area Internal IO-3 (AHB+APB): 16 MB 0xF300_0000 Reserved area Reserved area 0xF400_0000 Internal IO-4 (AHB): 16 MB Internal IO-4 (AHB): 16 MB Reserved area Reserved area 0xF600_0000 0xF800_0000 Reserved area Reserved area 0xF800_2000 Internal RAM-3: 8 KB (Remap) Internal RAM-3: 8 KB (Remap) 0xF800_4000 Internal RAM-0: 16 KB 0xF800_8000 Internal RAM-1: 16 KB 0xF800_C000 Internal RAM-2: 16 KB 0xF801_0000 Internal memory area (128 MB) Reserved area Internal RAM-0: 16 KB Internal RAM-1: 16 KB Internal RAM-2: 16 KB Reserved area 0xFFFF_FFFF Note1: Space between 0x0000_0000 and 0x0000_1FFF (8 KB) is a Remap area, and the Internal RAM3 area will be accessed when Remap_ON is programmed (access to F8000_2000 also leads to the RAM3 area). Note2: Access to unused area is prohibited. Figure 3.3.1 Memory Map (Details of Start Mode, External Areas and Internal Area) TMPA910CRA- 45 2010-06-02 TMPA910CRA Start Address 0x0000_0000 0x0000_2000 0x0000_4000 0x0100_0000 0x2000_0000 0x2100_0000 Bus Master and Slave Connection : Access available, x: Access unavailable : Don't access Internal BOOT ROM Mode Internal ROM: 8 KB + 8 KB CPU(D) CPU(I) LCDC LCDDA DMA1 DMA2 Remap area (8 KB) USB M1 M2 M3 M4 M5 M6 M7 x x x SMCCS0n External area (15.8 MB) Reserved area External area (496 MB) - Reserved area External area (16 MB) - SMCCS0n External area (496 MB) DMCCSn External area (512 MB) SMCCS1n External area (512 MB) Reserved area External area (512 MB) SMCCS2n External area (512 MB) Reserved area External area (512 MB) SMCCS3n External area (256 MB) 0x4000_0000 0x6000_0000 0x8000_0000 - 0xA000_0000 0xC000_0000 0xE000_0000 0xF000_0000 Internal IO-0 (APB): 1 MB 0xF010_0000 Reserved area - 0xF080_0000 Internal IO-1 (APB Port 1/2): 1 MB 0xF090_0000 Internal IO-2 (APB Port 2/2): 1 MB 0xF0A0_0000 Reserved area 0xF200_0000 Internal IO-3 (AHB + APB): 16 MB 0xF300_0000 Reserved area 0xF400_0000 Internal IO-4 (AHB): 16 MB 0xF600_0000 (128 MB) - Reserved area 0xF800_0000 Reserved area 0xF800_2000 Internal RAM-3 : 8 KB (Remap) 0xF800_4000 - Internal RAM-0: 16 KB Dual port RAM share with LCDDA Internal memory area 0xF800_8000 Internal RAM-1: 16 KB (128 MB) 0xF800_C000 Internal RAM-2: 16 KB 0xF801_0000 Please refer to the next page. Internal I/O area - Reserved area 0xFFFF_FFFF Figure 3.3.2 Memory Map (Details of Start Mode and Bus Master and Slave Connection) TMPA910CRA- 46 2010-06-02 TMPA910CRA Start Address End Address 0xF000_0000 0xF000_0FFF 0xF001_0000 0xF001_0FFF 0xF002_0000 0xF002_0FFF 0xF003_0000 0xF003_0FFF 0xF004_0000 0xF004_0FFF 0xF004_1000 0xF004_1FFF 0xF004_2000 0xF004_2FFF 0xF005_0000 0xF005_0FFF 0xF006_0000 0xF006_0FFF 0xF007_0000 0xF007_0FFF 0xF007_1000 0xF007_1FFF 0xF008_0000 0xF008_0FFF 0xF009_0000 0xF009_0FFF 0xF00A_0000 0xF00A_0FFF 0xF00B_0000 0xF00B_0FFF 0xF080_0000 0xF080_FFFF 0xF200_0000 0xF200_1FFF 0xF200_2000 0xF200_3FFF 0xF201_0000 0xF201_0FFF 0xF202_0000 0xF202_0FFF 0xF203_0000 0xF203_0FFF 0xF204_0000 0xF204_0FFF 0xF205_0000 0xF205_0FFF 0xF400_0000 0xF400_0FFF 0xF410_0000 0xF410_0FFF 0xF420_0000 0xF420_0FFF 0xF430_0000 0xF430_0FFF 0xF431_0000 0xF431_0FFF 0xF440_0000 0xF440_0FFF Details of Internal IO Master Internal IO (APB) 1 MB SysCtrl WDT PMC RTC/ Melody Timer01/ PWM Timer23/ PWM Timer45 PLLCG TSI I2C0 I2C1 ADC Reserved EBI LCDOP M1 (CPU Data) Internal IO (APB) 1 MB PORT M1 (CPU Data) Internal IO (AHB + APB) 16 MB UART0, 1 (Note2) SSP NANDFC CMOS_IS_IF SDHostCtrl I2S LCDDA INTC Internal IO area M1 (CPU Data) M5 (DMAC1) M6 (DMAC2) DMAC Internal IO (AHB) 16 MB LCDC MPMC0 MPMC1 USB M1 (CPU Data) Note1: Any area without the addresses shown above is a reserved area. Do not access any reserved area. Note2: TMPA910CRAXBG does not support UART1 DMAC transfer. Figure 3.3.3 Memory Map (Details of Internal Registers) TMPA910CRA- 47 2010-06-02 TMPA910CRA 3.3.1 Boot mode The TMPA910CRA has boot modes determined by the external pin setting. 1. Boot memory setting Mode Setting Pin RESETn AM1 2. Operation Mode AM0 0 1 Start from the external 16-bit NOR Flash memory (Internal BOOT ROM cannot be seen) 1 0 Start from the external 32-bit NOR Flash memory (Internal BOOT ROM cannot be seen) 1 1 BOOT (start from the Internal boot ROM) 0 0 TEST (this setting cannot be used) External memory voltage setting (Except NANDF) Mode Setting Pin Operation Mode SELVCCM 3. 0 Memory-related control pins operate at 1.8 0.1 V (DVCCM) 1 Memory-related control pins operate at 3.3 0.3 V (DVCCM) External memory controller setting Mode Setting Pin Operation Mode SELMEMC 4. 0 Only the SDR (Single Data Rate) and Mobile SDR types of SDRAM can be used. 1 Only the Mobile DDR (Mobile Double Data Rate) type of SDRAM can be used. JTAG pin setting Mode Setting Pin SELJTAG Operation Mode Set this pin to 0 except for Boundary Scan Mode. 0 The TMPA910CRA operates as regular Debug Mode. Note: Debugging is not available if the internal BOOT is carried out with AM1 = 1 and AM0 = 1. 1 The TMPA910CRA operates in Boundary Scan Mode. TMPA910CRA- 48 2010-06-02 TMPA910CRA 3.4 System Controller 3.4.1 Remapping Function The remapping function allows the 8 Kbyte area of the built-in RAM in the TMPA910CRA to be accessed from the two memory areas (0x0000_0000 to 0x0000_1FFF and 0xF800_2000 to 0xF800_3FFF). Write access to the Remap <REMAP> activates the Remapping function. System reset Reset state AM0 pin = 1, AM1 pin = 0: 16-bit bus AM0 pin = 1, AM1 pin = 1 Cancel the reset AM0 pin = 0, AM1 pin =1: 32-bit bus Multi mode BOOT mode The remapping function is turned on. Remap ON state Note: The Remap ON status is activated by the register programming. It can only be deactivated by resetting the system. Figure 3.4.1 Transition of the Memory State Transition TMPA910CRA- 49 2010-06-02 TMPA910CRA BOOT Mode 0x0000_0000 Built-in ROM 16 KB 0x0000_2000 0x0000_4000 0x0100_0000 0x2000_0000 0x2100_0000 Remap_ON Built-in RAM-3 8 KB (Remap) Cannot be used Multi Mode External area SMCCS0n External area SMCCS0n External area SMCCS0n External area SMCCS0n Reserved area Reserved area Reserved area Reserved area Reserved area Reserved area External area External area External area Built-in IO area Built-in IO area Built-in IO area Built-in RAM-3: 8 KB (Remap) Built-in RAM-0: 16 KB Built-in RAM-1: 16 KB Built-in RAM-2: 16 KB Built-in RAM-3: 8 KB (Remap) Built-in RAM-0: 16 KB Built-in RAM-1: 16 KB Built-in RAM-2: 16 KB Built-in RAM-3: 8 KB (Remap) Built-in RAM-0: 16 KB Built-in RAM-1: 16 KB Built-in RAM-2: 16 KB 0xF000_0000 0xF800_0000 0xF800_2000 0xF800_4000 0xF800_8000 0xF800_C000 0xF801_0000 0xFFFF_FFFF Note: Space between 0x0000_0000 and 0x0000_1FFF (8KB) is a Remap area. The built-in RAM3 area will be accessed when Remap_ON is programmed (access to 0xF8000_2000 also leads to the RAM3 area). Figure 3.4.2 Memory Map (Details of Boot Mode and External Areas) TMPA910CRA- 50 2010-06-02 TMPA910CRA 3.4.2 Register Descriptions The following lists the SFRs: Base address = 0F000_0000 Register Address Name (base+) Remap 0x0004 Description Reset memory map (REMAP) 1. Remap Register Address = (0xF000_0000) + (0x0004) Bit Bit Reset Type Symbol Value Description [31:1] - - Undefined Read as undefined. Write as zero. [0] REMAP RW 0y0 REMAP setting [Description] a. <REMAP> It is the register that enables the REMAP function. By writing arbitrary data, the built-in RAM3 can be accessed from the beginning of the memory map. The register cannot turn off the remap status (to reset to the initial state). TMPA910CRA- 51 2010-06-02 TMPA910CRA 3.5 Clock Controller 3.5.1 Overview The clock controller is a circuit that controls all clocks in the MCU. It has the following features: a. By using a clock multiplication circuit (PLL), the clock controller supplies a clock of up to 200 MHz to the CPU. A multiplier factor 1, 6, or 8 can be dynamically selected. b. The clock gear contributes to reduction of the current consumption. c. Write access to the registers inside the clock controller is disallowed. State transition of clock operation modes is as follows: Reset ON Reset (fOSCH/1) Cancel the reset status Cancel (interrutp) request Instruction PLL-OFF mode (fOSCH/gear value) Interrupt HALT mode (CPU Halt) Instruction Instruction Instruction PCM state (only some power is ON) PLL-ON mode Interrupt ((6 or 8)xfOSCH/gear value) Figure 3.5.1 Clock Mode Status Transition TMPA910CRA- 52 2010-06-02 TMPA910CRA 3.5.2 X T1 X T2 Block Diagram L o w-f re q u e n c y o sc illa t or fs fs S Y S C R3 <P L L O N> , <ND >, <C 2 S > S Y S C R2 <L UP F L A G > C loc k g e a r fc f c/ 2 Loc k - up tim er f c/ 4 ( fo r P LL) ci rc ui t (P LL ) X1 X2 Hig h -f re q u e n c y os c illa to r fO SC H x 12 o r 1 6 fF C LK f c /8 f P LL C l oc k m u ltip l ic a ti o n /2 /2 /4 /8 S Y S CR 1 <G E A R 2 : 0> S Y S CR 2 <FC S E L > S Y S CR 0 <U S B CL K S E L 1 : 0 > fU SB X 1 US B fF C LK CP U /2 fHC L K S t a n d a rd I P /2 C L K CR 5 <S E L _ S M C_ M CL K > MP MC fPC L K AP B Bridge IP x fHC L K IP y Input clock frequency applied on the X1 and X2 pins is defined as fOSCH. Input clock frequency applied on the XT1 and XT2 pins is defined as fS, and the clock programmed with SYSCR1 <GEAR2:0> is defined as fFCLK for the CPU core. Clocks for peripheral IPs connected to the AHB bus and the APB bus are defined as fHCLK (signal name: HCLK) and fPCLK (signal name: PCLK) respectively. They are obtained by dividing fFCLK by 2. Two types of clock, for DRAM and for SRAM/NORF respectively, are supplied to the memory controller. For SRAM/NORF, fHCLK or a half of fHCLK can be selected (Please refer to MPMC section). TMPA910CRA- 53 2010-06-02 TMPA910CRA The clock restrictions are defined below. Select an appropriate clock for the intended applications within the restrictions. Table 3.5.1 Clock Restrictions (a) fOSCH (High speed oscillator frequency) (b) fPLL (PLL output frequency) (c) fFCLK (Frequency for the CPU) (d) fUSB (Frequency for the USB) (e) fS (Low speed oscillator frequency) Lowest Frequency Highest Frequency 10 MHz 27 MHz 60 MHz 200 MHz 1.25 MHz 200 MHz 24 MHz 24 MHz 30 kHz 34 kHz Notes Within 100 ppm accuracy at 24 MHz is required. The table below shows the examples of recommended use that meet the conditions listed above. Table 3.5.2 Examples of Recommended Uses High Speed Oscillation: fOSCH PLL Output Clock for Clock for Clock: fPLL CPU: fFCLK USB: fUSB 24 MHz Max. 192 MHz Max. 192 MHz 24 MHz (1) CPU: max. 192 MHz with USB (2) CPU: max. 200 MHz with USB 24 MHz 25 MHz Max. 200 MHz Max.200 MHz (Input from the X1USB pin is required) (3) CPU: max. 200 MHz without USB 25 MHz Max. 200 MHz TMPA910CRA- 54 Max. 200 MHz - 2010-06-02 TMPA910CRA 3.5.3 Operational Descriptions 3.5.3.1 Register Descriptions The following lists the SFRs: Base Address = 0xF005_0000 Register Address Name (base+) Description SYSCR0 0x000 System Control Register 0 SYSCR1 0x004 System Control Register 1 SYSCR2 0x008 System Control Register 2 SYSCR3 0x00C System Control Register 3 SYSCR4 0x010 System Control Register 4 SYSCR5 0x014 System Control Register 5 SYSCR6 0x018 System Control Register 6 SYSCR7 0x01C System Control Register 7 - 0x040 Reserved - 0x044 Reserved - 0x048 Reserved - 0x04C Reserved - 0x050 Reserved CLKCR5 0x054 Clock Control Register 5 TMPA910CRA- 55 2010-06-02 TMPA910CRA 1. SYSCR0 (System Control Register 0) Address = (0xF005_0000) + (0x0000) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7:6] USBCLKSEL R/W 0y00 Read as undefined. Write as zero. Selection of an USB clock: 0y00: fixed at GND 0y01: X1 pin clock 0y10: X1USB pin clock 0y11: fixed at GND [5] Reserved R/W 0y1 [4] - - Undefined Read as undefined. Write as one. Read as undefined. Write as zero. [3] Reserved R/W 0y0 Read as undefined. Write as zero. [2] - - Undefined Read as undefined. Write as zero. [1] Reserved R/W 0y1 Read as undefined. Write as one. [0] - - Undefined Read as undefined. Write as zero. [Description] a. <USBCLKSEL> Selects the USB clock. 0y00: Fixed at GND 0y01: X1 pin clock 0y10: X1USB pin clock 0y11: Fixed at GND TMPA910CRA- 56 2010-06-02 TMPA910CRA 2. SYSCR1 (System Control Register 1) Address = (0xF005_0000) + (0x0004) Bit Bit Symbol Type Reset Description Value [31:3] - - Undefined [2:0] GEAR R/W 0y000 Read as undefined. Write as zero. Clock gear programming (fc) 0y000: fc 0y001: fc/2 0y010: fc/4 0y011: fc/8 0y1xx: Reserved [Description] a. <GEAR> Programs the clock gear. 0y000: fc 0y001: fc/2 0y010: fc/4 0y011: fc/8 0y1xx: Reserved TMPA910CRA- 57 2010-06-02 TMPA910CRA 3. SYSCR2 (System Control Register-2) Address = (0xF005_0000) + (0x0008) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] Reserved R/W 0y0 Read as undefined. Write as zero. [6:2] - - Undefined Read as undefined. Write as zero. [1] FCSEL R/W 0y0 Read as undefined. Write as zero. Selection of the PLL output clock 0y0: fOSCH 0y1: fPLL [0] LUPFLAG RO 0y0 End flag of the PLL lockup counter Read: 0y0: Not end 0y1: End Write: Invalid [Description] a. <FCSEL> Selects the clock to be output from the PLL. 0y0: fOSCH 0y1: fPLL b. <LUPFLAG> Indicates the state of the PLL lock-up counter. 0y0: Not end 0y1: End TMPA910CRA- 58 2010-06-02 TMPA910CRA 4. SYSCR3 (System Control Register 3) Address = (0xF005_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] PLLON R/W 0y0 Read as undefined. Write as zero. PLL operation control 0y0: OFF 0y1: ON [6] - - Undefined Read as undefined. Write as zero. [5] C2S R/W 0y1 PLL constant value setting1 [4:0] ND R/W 0y00111 PLL constant value setting 2 Always write 0 0y00101 for x6, 0y00111 for x8 [Description] a. <PLLON> Controls the operation of the PLL. 0y0: OFF 0y1: ON b. <C2S> PLL constant value setting 1 1 is set as default. Rewrite it to 0 before use. c. <ND> PLL constant value setting 2 0y0_0101 for x6, 0y0_0111 for x8 TMPA910CRA- 59 2010-06-02 TMPA910CRA 5. SYSCR4 (System Control Register 4) Address = (0xF005_0000) + (0x010) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:4] RS R/W 0y0111 PLL constant value setting 3 x8 [3:2] IS R/W 0y10 x6 140MHz or Less than 140MHz or Less than more 140MHz more 140MHz 0y0110 0y1001 0y0110 0y0111 PLL constant value setting 4 Always write 0y01 [1:0] FS R/W 0y01 PLL constant value setting 5 x8 x6 140MHz or Less than 140MHz or Less than more 140MHz more 140MHz 0y01 0y10 0y01 0y10 [Description] a. <RS> PLL constant value setting 3 Program the following values according to PLL multiplying factor and frequency to be multiplied. x8 140MHz or more: Less than 140MHz: x6 0y0110 0y1001 140MHz or more: Less than 140MHz: 0y0110 0y0111 b. <IS> PLL constant value setting 4 0y10 is set as default. Rewrite it to 0y01 before use. c. <FS> PLL constant value setting 5 Program the following values according to the PLL multiplying factor and frequency to be multiplied. x8 140MHz or more: 0y01 Less than 140MHz: x6 0y10 140MHz or more: 0y01 Less than 140MHz: 0y10 TMPA910CRA- 60 2010-06-02 TMPA910CRA 6. SYSCR5 (System Control Register 5) Address = (0xF005_0000) + (0x0014) Bit Bit Symbol Type Reset Description Value [31:1] - - Undefined [0] PROTECT RO 0y0 Read as undefined. Protect Flag 0y0: OFF 0y1: ON [Description] By setting a dual key to the SYSCR6 and SYSCR7 registers, protection (write operation to certain SFRs in the clock controller) can be activated or released. [Dual key] 1st-KEY : Consecutive writing of 0x5A to SYSCR6 and 0xA5 to SYSCR7 2nd-KEY : Consecutive writing of 0xA5 to SYSCR6 and 0x5A to SYSCR7 The protection status can be checked by reading SYSCR5<PROTECT>. Reset operation turns protection OFF. If write operation is executed to certain SFRs shown below while protection is ON, written data will be invalidated. The SFRs: SYSCR0, SYSCR1, SYSCR2, SYSCR3, SYSCR4, SYSCR5, CLKCR5 TMPA910CRA- 61 2010-06-02 TMPA910CRA 7. SYSCR6 (System Control Register 6) Address = (0xF005_0000) + (0x0018) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] P-CODE0 WO 0X00 Protect code setting-0 [Description] a. <P-CODE0> Used to set the protect code 0. 8. SYSCR7 (System Control Register 7) Address = (0xF005_0000) + (0x001C) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] P-CODE1 WO 0X00 Protect code setting-1 [Description] a. <P-CODE1> Used to set the protect code 1. TMPA910CRA- 62 2010-06-02 TMPA910CRA 9. CLKCR5 (Clock Control Register-5) Address = (0xF005_0000) + (0x0054) Bit Bit Symbol Type Reset Description Value [31:7] - - Undefined Read as undefined. Write as zero. [6] Reserved R/W 0y1 Read as undefined. Write as one. Read as undefined. Write as zero. [5:4] - - Undefined [3] SEL_SMC_ R/W 0y1 SMC_MCLK selection register 0y0: fPCLK /2 MCLK 0y1: fPCLK [2] SEL_TIM45 R/W 0y1 Selection of a prescaler clock for Timer45 0y0: fs (32.768 kHz) clock 0y1: fPCLK/2 [1] SEL_TIM23 R/W 0y1 Selection of a prescaler for Timer23 0y0: fs (32.768 kHz) clock 0y1: fPCLK /2 [0] SEL_TIM01 R/W 0y1 Selection of a prescaler for Timer01 0y0: fs (32.768 kHz) clock 0y1: fPCLK/2 [Description] a. <SEL_SMC_MCLK> Selects SMC_MCLK. 0y0: fPCLK /2 0y1: fPCLK b. <SEL_TIM45> Selects the prescaler clock for Timer45. 0y0: fs (32.768 kHz) clock 0y1: fPCLK/2 c. <SEL_TIM23> Selects the prescaler clock for Timer23. 0y0: fs (32.768 kHz) clock 0y1: fPCLK/2 d. <SEL_TIM01> Selects the prescaler clock for Timer01. 0y0: fs (32.768 kHz) clock 0y1: fPCLK/2 TMPA910CRA- 63 2010-06-02 TMPA910CRA 3.5.4 System Clock Controller The system clock controller generates a clock to be supplied to the CPU core (fFCLK) and other built-in I/Os (fHCLK). With the fOSCH or fPLL clock as an input, it is possible to use SYSCR1<GEAR2:0> to change the high speed clock gear to 1, 2, 4, or 8-speed (fc, fc/2, fc/4, or fc/8) to reduce power consumption. Reset operation switches the mode to PLL-OFF, and <GEAR2:0> is initialized to 0y000; therefore, frequency of the CPU clock fFCLK will be the same as fOSCH. For example, when a 24 MHz oscillator is connected to the X1 and X2 pins, the frequency of fFCLK becomes 24 MHz when reset operation is executed. (1) Clock gear By using the clock gear selection register SYSCR1<GEAR2:0>, the gear can be set to fc, fc/2, fc/4, or fc/8. Changing fFCLK by using the clock gear contributes to reduction of power consumption. An example of clock gear switching is as follows: [Setting example] ; (SYSCR1) 3.5.5 0x0000_0011 ; switch fFCLK to 1/8. PLL Clock Multiplier The PLL outputs fPLL clock signals whose frequency is 6 or 8 times the fOSCH. By using the PLL, it is possible to lower the oscillator frequency and make the internal clock faster. Since the PLL is initialized to the halt state when reset operation is executed, it is necessary to configure the SYSCR2, SYSCR3 and SYSCR4 registers when using the PLL. As with an oscillator, this circuit requires time to stabilize the fPLL clock signals after operation is enabled, and the time required is called lock-up time. A 12-stage binary counter can be used to check the lock-up time. For example, lock-up time is approximately 164s when fOSCH = 25 MHz. Examples of the PLL start and stop settings are as follows: Setting example - 1: PLL start SYSCR4 0x00000065 ; Set the constant of PLL x8 SYSCR3 0x00000087 ; Operation is activated with PLL x8 SYSCR2 r0 ; <LUPFLAG> == 1? LOCKUP: LDR r1, = 0x01 AND r0,r0,r1 LDR r1, = 0x01 ; CMP r0 ,r1 ; r0 r1 , BNE LOCKUP (SYSCR2) 0x00000002 jump to LOCKUP ; <FCSEL> = 1 (change from 24 MHz to 192 MHz) TMPA910CRA- 64 2010-06-02 TMPA910CRA <PLLON> <FCSEL> PLL output: fPLL Lock-up timer Count up at fOSCH <LUPFLAG> During lock-up After lock-up CPU clock fFCLK PLL operation and lock-up start Switch from 24 MHz to 192 MHz Lock-up end Setting example - 2: PLL stop (SYSCR2) LUP: 0x0000_0000 ; <FCSEL> = 0 (change from 192 MHz to 24 MHz) Dummy instruction execution (Note) (SYSCR3) 0x0000_0007 ; <PLLON> = 0 <FCSEL> <PLLON> PLL output: fPLL CPU clock fFCLK Switch from 192 MHz to 24 MHz PLL operation stop Note: When switching <FCSEL> from 1 to 0, a few clock cycles are required before fFCLK is changed to fOSCH after the register write is completed. Therefore, it is necessary to first wait for the required clock cycles and then execute the next instruction. More specifically, execute 10 NOP instructions. TMPA910CRA- 65 2010-06-02 TMPA910CRA 3.6 Boot ROM TMPA910CRA contains a boot ROM for loading a user program to the internal RAM. The following loading methods are supported. 3.6.1 Operation Modes TMPA910CRA has two operation modes: external memory mode and internal boot ROM mode. Either mode is selected in accordance with the AM1 and AM0 pin status when RESETn is asserted. (1) External memory mode: After reset, the CPU fetches instructions from external memory and executes them. (2) Internal boot ROM mode: After reset, the CPU fetches instructions from the internal boot ROM and executes them. According to the program in the internal boot ROM, a user program is transferred to the internal RAM via USB communication and branches into the program in the internal RAM. This triggers the user program to boot. Table 3.6.2 shows the overview of boot operation. Table 3.6.1 Operation Modes Mode Setting Pins RESETn AM1 AM0 0 1 Operation Mode Start from the external bus memory (with 16-bit bus) 1 0 Start from the external bus memory (with 32-bit bus) 1 1 BOOT (start from the internal boot ROM) 0 0 TEST (setting prohibited) Table 3.6.2 Overview of boot operation Priority 1 Loading Source USB host such as a PC I/F Destination Operation after loading USB Internal RAM Branch into the internal 8 KB_RAM 0x0000_0000 TMPA910CRA- 66 2010-06-02 TMPA910CRA 3.6.2 Hardware Specifications of the Internal Boot ROM (1) Memory map Figure 3.6.1 shows a memory map of BOOT mode. The internal boot ROM consists of 16 KB ROM and is assigned to addresses from 0x0000_0000 to 0x0000_3FFF. 0x0000_0000 Internal boot ROM/RAM: 8 KB (Remap) 0x0000_2000 Internal boot ROM: 8 KB Remap area 0x0000_4000 External area 4GB 0xF000_0000 Internal IO-0(APB) : 1 MB 0xF080_0000 Internal IO-1(APB Port1/2) : 1 MB 0xF090_0000 Internal IO-2(APB Port2/2) : 1 MB 0xF200_0000 Internal IO-3(AHB+APB) : 16 MB 0xF400_0000 Internal IO-4(AHB) : 16 MB Internal IO area (128 MB) 0xF600_0000 0xF800_0000 0xF800_2000 Internal RAM-3 : 8 KB(Remap) 0xF800_4000 Internal RAM-0: 16 KB 0xF800_8000 Internal RAM-1: 16 KB 0xF800_C000 Internal RAM-2: 16 KB Internal memory area (128 MB) 0xF801_0000 0xFFFF_FFFF Figure 3.6.1 Memory map of BOOT mode TMPA910CRA- 67 2010-06-02 TMPA910CRA (2) The boot ROM elimination function After the boot sequence is executed in BOOT mode, remapping is executed and the internal boot ROM area changes into RAM. BOOT mode 0x0000_0000 0x0000_2000 0x0000_4000 0x2100_0000 Remap_ON Multi mode Internal ROM 16 KB Internal RAM-3 8 KB (Remap) Cannot be used External area SMCCS0n Unused area Unused area Unused area External area External area External area Internal IO area Internal IO area Internal IO area Internal RAM-3: 8 KB (Remap) Internal RAM-0: 16 KB Internal RAM-1: 16 KB Internal RAM-2: 16 KB Internal RAM-3: 8 KB (Remap) Internal RAM-0: 16 KB Internal RAM-1: 16 KB Internal RAM-2: 16 KB Internal RAM-3: 8 KB (Remap) Internal RAM-0: 16 KB Internal RAM-1: 16 KB Internal RAM-2: 16 KB 0xF000_0000 0xF800_0000 0xF800_2000 0xF800_4000 0xF800_8000 0xF800_C000 0xF801_0000 0xFFFF_FFFF Note: Space between 0x0000_0000 and 0x0000_1FFF (8 KB) is a Remap area, and the internal RAM3 area will be accessed when Remap is set to Remap_ON (access to F8000_2000 also leads to the RAM3 area). Figure 3.6.2 Memory map (details of boot mode and external area) TMPA910CRA- 68 2010-06-02 TMPA910CRA 3.6.3 Outline of Boot Operation USB can be selected as the transfer source of boot operation. After reset, operation of the boot program on the internal boot ROM follows the flow chart shown in Figure 3.6.3. In any case, the user program is transferred from the source to the internal RAM, and branched into the internal RAM. The internal RAM is used in the same manner regardless of the transfer source as shown in Figure 3.6.4. . Start No USB check Yes Download via USB Branch into the internal RAM 0x0000_0000 Note: When downloading the user program via USB, a USB device driver and special application software are needed on the PC. Figure 3.6.3 Flow chart of internal boot ROM operation TMPA910CRA- 69 2010-06-02 TMPA910CRA 0x0000 0000 Vector in ROM 0x0000 0000 Vector in RAM User program LOAD area: vector area included (8KB) BOOT ROM (16KB) 0xF800 2000 Vector in RAM 0xF800 2000 Shadow area (Same Data) Vector in RAM User program LOAD area: vector area included (8KB) User program LOAD area: vector area included (8KB) 0xF800 4000 0xF800 4000 User program LOAD area (40KB) User program LOAD area (40KB) 0xF800 E000 Boot program work space and stack space area (8 KB) 0xF800 E000 Boot program work space and stack space area (8 KB) 0xF800 FFFF 0xF800 FFFF Before Remap After Remap Figure 3.6.4 Use of the internal RAM of the boot program Within the internal RAM, the area between 0xF800_E000 and 0xF800_FFFF is used as work and stack areas for executing the boot program. Therefore, the maximum size of the user program that can be loaded to the internal RAM is 48 KB. Within 48 KB of the user program area between 0xF800_2000 and 0xF800_DFFF, the vector and program are written in an 8 KB space between 0xF800_2000 and 0xF800_3FFF. The boot program loads user program into the user program area in the internal RAM. The boot program is loaded into the work space in the internal RAM. The loaded program executes remapping. When the remap function is turned ON, the 8 KB space between 0xF800_2000 and 0xF800_3FFF can be accessed from the space between 0x0000_0000 and 0x0000_1FFF. Refer to the chapter on the "system controller" for details of this function. The boot program will branch to 0x0000_0000 of the last remapped RAM area (RESET vector). As shown in Fig. 3.6.4, remapping assigns another vector addresses to the ROM area. Ex. Before remapping 0xF800_2000 0xF800_2018 After remapping 0x0000_0000 (Reset vector) 0x0000_0018 (IRQ vector) Therefore, the vector addresses to jump after running boot program must be assigned to 0xF800_2000 and later addresses. TMPA910CRA- 70 2010-06-02 TMPA910CRA 3.6.3.1 Example of USB Boot In boot from USB, user program vector is downloaded to 8KB of Remap area (0xF800_2000 to 0xF800_3FFF), program is downloaded to 40KB of internal RAM area (0xF800_4000 to 0xF800_DFFF). Boot program remaps the area, and the data of Remap area is reflected to vector area (0x0000_0000 to 0x0000_1FFF). When the address jumps to 0x0000_0000 address, User program is started. 0x0000_0000 Vector area Note: Execution address of vector is Data of Remapped area is 0x0000_0000. reflected 0x0000_0000 to However, 0xF800_2000 and later 0xF800_2000 0x0000_1FFF Address. addresses must be assigned as the Remap area 0xF800_4000 original data area. Internal RAM (1) CPU status and port settings ARM926EJ-S starts in supervisor mode after reset, and the boot program executes all programs in supervisor mode without any mode changes. No port settings are required as ports used in the boot program are all dedicated pins. Table 3.6.3 Port settings for the boot program BOOT USB Function I/O D+ Input/Output D- Input/Output Pin configuration by the boot program No settings required as dedicated pins are used. TMPA910CRA- 71 2010-06-02 TMPA910CRA (2) Control register settings by the boot program Table 3.6.4 shows the control registers of internal circuits that are set by the boot program. After the boot sequence, create a program while taking these setting values into account. The stack pointer and the internal RAM including the area between 0xF800_E000 and 0xF800_FFFF remain in the state after execution of the boot program. Please reset them as appropriate before using. Table 3.6.4 List of SFRs Register name Setting value SYSCR1 0x0002 SYSCR2 0x0002 SYSCR3 0x0087 SYSCR4 0x0065 REMAP 0x0001 Description Clock gear = 1/4 PLL clock is used (x 8) Remap ON Important Notes Timer0 is used in the BOOT sequence. (Then Timer0control<TIM0EN> = 1: Timer0 operation is enable status.)It is possible that an interrupt of Timer0 may be generated when the program is running. Before using Timer0, clear the interrupt by writing any values to Timer0IntClr<TIM0INTCLR>. Note: The values to be set in the I/O registers for USB, VIC and DMAC are not described here. If these functions are needed in a user program, reconfigure each I/O register as necessary. TMPA910CRA- 72 2010-06-02 TMPA910CRA 3.6.4 Download via USB (1) Connection example Figure 3.6.5 shows an example of USB connection (assuming that NOR Flash is program memory) 24MHz X1 X2 CTL D+ D- PC TMPA910CRA AM0 Data NOR Flash Data AM1 Address Address Figure 3.6.5 USB connection example (2) Overview of the USB interface specifications Set the oscillation frequency for the X1 and X2 pins to 24.00 MHz ( 100 ppm) when booting using USB. The USB of this microcontroller supports high-speed communications. However, if the USB host does not support high-speed communications (USB 1.1 or older), full-speed communications will be carried out. (The boot ROM function does not support clock supply from the USB clock pin X1USB.) (For cautions on using the USB, refer to the chapter on the USB.) Although there are four types of USB transfer, the following two types are used for the boot function. Table 3.6.5 Transfer types used by the boot program Transfer type Description Control Transfer Used for transmitting standard requests and vendor requests. Bulk Transfer Used for responding to vendor requests and transmitting a user program. TMPA910CRA- 73 2010-06-02 TMPA910CRA The following shows an overview of the USB communication flow. [Legends] Control Transfer Bulk Transfer Host (PC) Connection recognition TMPA910CRA Send GET_DESCRIPTOR. Send DESCRIPTOR information. Data transfer Convert Motorola S3 format data. Send a microcontroller information command. Send microcontroller information data. Create microcontroller information data. Check data Send the user program transfer start command. Transfer data Send a user program. Load the received data into the specified RAM address area. Create microcontroller information data. (If the received data cannot be loaded into RAM for some reason, the data is discarded everytime it is received.) Transfer end processing Transmit the transfer result command over 2 seconds after completion of user program transfer. Send the transfer result command. Send transfer result data. Create transfer result data. Check data Branch to the internal RAM Figure 3.6.6 Overview of the overall flow TMPA910CRA- 74 2010-06-02 TMPA910CRA The following shows the connection of Vendor class request. The table below shows the setup command data structure. Table 3.6.6 Setup Command Data Structure Field Value bmRequestType Description 0x40 bRequest 0x00, 0x02, 0x04 D7 0y0: Host to device D6-D5 0y10: Vendor D4-D0 0y00000: Device 0x00: Microcontroller information 0x02: User program transfer start 0x04: User program transfer result wValue 0x00~0xFFFF wIndex 0x00~0xFFFF Unique data number (Not used by the microcontroller) Write size Used when starting user program transfer (user program transfer size) wLength 0x0000 Fixed The table below shows vendor request commands. Table 3.6.7 Vendor Request Commands Command Vendor request value Operation Notes Microcontroller information command 0x00 Device sends microcontroller information. Microcontroller information data is sent by bulk IN transfer after the setup stage is completed. User program transfer start command 0x02 Device starts receiving user program. Set the transfer size of a user program in wIndex. Device sends the transfer result. Transfer result data is transmitted as bulk data after the setup stage is completed. User program transfer result command 0x04 TMPA910CRA- 75 The user program is received by bulk OUT transfer after the setup stage is completed. 2010-06-02 TMPA910CRA The table below shows standard request commands. Table 3.6.8 Standard request commands Standard request Response GET_STATUS Not supported CLEAR_FEATURE Not supported SET_FEATURE Not supported SET_ADDRESS Supported GET_DESCRIPTOR Supported SET_DESCRIPTOR Not supported GET_CONFIGRATION Not supported SET_CONFIGRATION Supported GET_INTERFACE Not supported SET_INTERFACE Not supported SYNCH_FRAME Ignored The table below shows information to be returned by GET_DESCRIPTOR. Table 3.6.9 Replies to GET_DISCRIPTOR Device Descriptor Field * Value Description Blength 0x12 18 bytes BdescriptorType 0x01 Device descriptor BcdUSB 0x0200 USB Version 2.0 BdeviceClass 0x00 Device class not in use BdeviceSubClass 0x00 Sub command not in use BdeviceProtocol 0x00 Protocol not in use BmaxPacketSize0 0x40 EP0 maximum packet size is 64 bytes. IdVendor 0x0930 Vendor ID IdProduct 0x6504 Product ID (0) BcdDevice 0x0001 Device version (v0.1) Imanufacturer 0x00 Index value of string descriptor indicating the manufacturer name Iproduct 0x00 Index value of string descriptor indicating the product name IserialNumber 0x00 Index value of string descriptor indicating the product serial number BnumConfigurations 0x01 There is one configuration. The descriptor information to be returned to the USB host should be modified as required by each application. TMPA910CRA- 76 2010-06-02 TMPA910CRA Configuration Descriptor Field Value Description bLength 0x09 9 bytes bDescriptorType 0x02 Configuration descriptor wTotalLength 0x0020 Total length (32 bytes) obtained by adding each configuration and endpoint descriptor bNumInterfaces 0x01 There is one interface. bConfigurationValue 0x01 Configuration number 1 iConfiguration 0x00 Index value of string descriptor indicating the configuration name (Not in use) bmAttributes 0x80 Bus power MaxPower 0x31 Maximum power consumption (49 mA) Interface Descriptor Field Value Description bLength 0x09 bDescriptorType 0x04 9 bytes Interface descriptor bInterfaceNumber 0x00 Interface number 0 bAlternateSetting 0x00 Alternate setting number 0 bNumEndpoints 0x02 There are two endpoints. bInterfaceClass 0xFF Unique device bInterfaceSubClass 0x00 bInterfaceProtocol 0x50 iIinterface 0x00 * BulkOnly protocol Index value of string descriptor indicating the interface name (Not in use) The descriptor information to be returned to the USB host should be modified as required by each application. TMPA910CRA- 77 2010-06-02 TMPA910CRA Endpoint Descriptor (When the USB host supports USB2.0) Field Value Description <Endpoint1> blength 0x07 bDescriptorType 0x05 7 bytes Endpoint descriptor bEndpointAddress 0x81 EP1 = IN bmAttributes 0x02 Bulk transfer wMaxPacketSize 0x0200 Payload 512 bytes bInterval 0x00 (Ignored for bulk transfer) bLength 0x07 7 bytes bDescriptor 0x05 Endpoint descriptor bEndpointAddress 0x02 EP2 = OUT <Endpoint2> bmAttributes 0x02 Bulk transfer wMaxPacketSize 0x0200 Payload 512 bytes bInterval 0x00 (Ignored for bulk transfer) Endpoint Descriptor (When the USB host supports USB1.1) Field Value Description <Endpoint1> blength 0x07 bDescriptorType 0x05 7 bytes Endpoint descriptor bEndpointAddress 0x81 EP1= IN bmAttributes 0x02 Bulk transfer wMaxPacketSize 0x0040 Payload 64 bytes bInterval 0x00 (Ignored for bulk transfer) bLength 0x07 7 bytes bDescriptor 0x05 Endpoint descriptor bEndpointAddress 0x02 EP2 = OUT bmAttributes 0x02 Bulk transfer wMaxPacketSize 0x0040 Payload 64 bytes bInterval 0x00 (Ignored for bulk transfer) <Endpoint2> * The descriptor information to be returned to the USB host should be modified as required by each application. TMPA910CRA- 78 2010-06-02 TMPA910CRA The table below shows information replied to the microcontroller information command. Table 3.6.10 Information Replied to the Microcontroller Information Command Microcontroller information TMPA910CR ASCII code 0x54,0x4D,0x50,0x41,0x39,0x31,0x30,0x43,0x52,0x20,0x20,0x20,0x20,0x20,0x20 Note: produnct name in the Microcontroller information includes 6 spaces at the end of the product name. The table below shows information replied to the transfer result command. Table 3.6.11 Information returned by the transfer result command Transfer result Value Error condition Normal termination 0x00 User program not received 0x02 The user program transfer result is received without the user program transfer start command being received first. Received file not in Motorola S3 format 0x04 The first data of a user program is not S (0x53). Size of a received user program being larger than specified 0x06 The size of a received user program is larger than the value set in wIndex of the user program transfer start command. Inadequate download address 0x08 The user program download address is not in the specified area. Protocol error or errors other than above 0x0A The user program transfer start or user program transfer result command is received first. A checksum error is detected in the Motorola S3 file. A record type error is detected in the Motorola S3 file. An error is detected in the DMA transfer. TMPA910CRA- 79 2010-06-02 TMPA910CRA (3) Description of the USB boot program operation The boot program transfers data in Motorola S3 format sent from the PC to the internal RAM. The user program starts operating after data transfer is completed. The start address of the program is 0x0000_0000. Please refer to section 3.6.3 for details. This function enables users to customize on-board programming control. a. Operation procedure 1. Connect the USB cable. 2. Set both the AM0 and AM1 pins to 1 and reset the microcontroller. 3. After recognizing USB connection, the PC checks the information on the connected device using the GET_DESCRIPTOR command. 4. The PC sends the microcontroller information command by command transfer (vendor request). 5. Upon receiving the microcontroller information command, the boot program prepares microcontroller information in ASCII code. 6. The PC checks the microcontroller information data. 7. The PC sends the microcontroller transfer start command by command transfer (vendor request). After the setup stage is completed, the PC transfers the user program by bulk OUT transfer. 8. After the user program has been transferred, the PC waits for over two seconds and then sends the user program transfer result command by command transfer (vendor request). 9. Upon receiving the user program transfer result command, the boot program prepares for transmission of the transfer result value. 10. The PC checks the transfer result. 11. If the transfer results in failure, the boot program starts the error processing routine and will not automatically recover from it. In this case, terminate the device driver on the PC and retry from Step 2. b. Notes on the user program format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (0x53 for "S") of the next record. Even if data other than 0x53 is transmitted between records, it will be ignored. Note: In USB transfers, the maximum object size that can be transferred is 64 KB since the write size is set by wIndex within the address range of 0x0000H to 0xFFFF. TMPA910CRA- 80 2010-06-02 TMPA910CRA 3.6.5 Usage Note Following are the note when use the BOOT ROM. 1Using TIMER0 Timer0 is used in the BOOT sequence. (Then Timer0control<TIM0EN> = 1: Timer0 operation is enable status.) It is possible that an interrupt of Timer0 may be generated when the program is running. Before using Timer0, clear the interrupt by writing any values to Timer0IntClr<TIM0INTCLR>. 2USB connector The USB connector must not be connected or disconnected during USB boot. 3. Software on the PC A dedicated USB device driver and application software installed on the PC are needed for USB boot. TMPA910CRA- 81 2010-06-02 TMPA910CRA 3.7 Interrupts 3.7.1 Functional Overview The interrupts of the TMPA910CRA has the following features: 3.7.2 * Supports 28 interrupt sources. * Assigns 32 levels of fixed hardware(H/W) priorities to the interrupt sources (to be used if multiple interrupt requests of the same software priority level are made simultaneously). * Enables to set 16 levels (0 to15) of software(S/W) interrupt priority for each interrupt source. * Enables to mask hardware and software priority levels. * Supports two types of interrupt requests: normal interrupt request (IRQ) and fast interrupt request (FIQ). * Enables to generate software interrupts. Block Diagram FIQSTATUS [31:0] FIQ interrupt circuit VICINTSOURCE [31:0] (4 interrupt sources are not used) IRQSTATUS [31:0] Interrupt request circuit Interrupt vector 0 IRQ0 VectAddr0 Interrupt vector 1 IRQ1 VectAddr1 : : nVICFIQ (Non vectored ) logic : : Interrupt vector 31 IRQ31 VectAddr31 ARM926 EJ-S IRQ vector address nVICIRQ Priority order circuit AHB Bus AHB interface and register Figure 3.7.1 Block diagram TMPA910CRA- 82 2010-06-02 TMPA910CRA * Logic circuit of Interrupt request VICIntEnable [31:0] VICIntSelect [31:0] VICIRQStatus [31:0] VICINTSOURCE [31:0] VICFIQStatus [31:0] VICSoftInt [31:0] VICRawInterrupt [31:0] Figure 3.7.2 Status flag relation TMPA910CRA- 83 2010-06-02 TMPA910CRA 3.7.3 Operational Description For Interrupt Control(VIC), FIQ (Fast Interrupt Request) and IRQ (Interrupt Request) are available. The TMPA910CRA only has one FIQ source. FIQ is a low- latency interrupt and has the highest priority level. In handling FIQ, Interrupt Service Routine can be executed without checking which interrupt source is used. TMPA910CRA- 84 2010-06-02 TMPA910CRA * Interrupt vector flowchart An interrupt occurs (IRQ) An interrupt occurs (FIQ) CPU branches to 0x00000018, and jumps to the Interrupt Service Routine jumps to the Interrupt Service Routine CPU branches to 0x0000001C, and * As VICADDRESS of FIQ is located at last address of excepted interruptions, so ISR can be located at 0x0000001C Read the VICADDRESS register so that other higher priority interruptions than current interruption can be re-enabled If necessary, "PUSH" the register setting and etc. * In case of using multiple interruption, set to "enable" for enable register in If necessary, "PUSH" the register setting and etc. CPU. Execute the Interrupt Service Execute the Interrupt Service Routine (ISR) Routine (ISR) Clear the interrupt request of peripheral Clear the interrupt request of peripheral circuit. circuit. *In case of "software interruption" is *In case of "software interruption" is generated, clear the VICSOFTCLEAR register. generated, clear the VICSOFTCLEAR register. * In case of using multiple interruption, set to "disable" for enable register in CPU. If necessary, "POP" the register If necessary, "POP" the register setting and etc. setting and etc. Write the VICADDRESS register. (Clear Hardware priority control of VIC) Routine (ISR). Return from the Interrupt Service Routine (ISR). End End Return from the Interrupt Service TMPA910CRA- 85 2010-06-02 TMPA910CRA 3.7.4 Interrupt Sources Table 3.7.1 Interrupt sources Interrupt source number (Note) Interrupt source Vector address 0 WDT 1 RTC Vector Address 0 Vector Address 1 2 Timer01 Vector Address 2 3 Timer23 Vector Address 3 4 Timer45 Vector Address 4 5 GPIOD:INTA (TSI), INTB Vector Address 5 2 Vector Address 6 2 Vector Address 7 6 I C ch0 7 I C ch1 8 ADC Vector Address 8 9 Reserved Vector Address 9 10 UART ch0 Vector Address 10 11 UART ch1 Vector Address 11 12 SSP ch0 Vector Address 12 13 SSP ch1 Vector Address 13 14 NDFC Vector Address 14 15 CMSIF Vector Address 15 16 DMA transfer error Vector Address 16 17 DMA terminal count Vector Address 17 18 LCDC Vector Address 18 19 Reserved Vector Address 19 20 LCDDA Vector Address 20 21 USB Vector Address 21 22 SDHC 23 IS Vector Address 23 Vector Address 22 24 Reserved Vector Address 24 25 Reserved Vector Address 25 26 GPIOR (INTH) Vector Address 26 27 GPIOP (INT0 INT7) Vector Address 27 28 GPION (INTD INTG) Vector Address 28 29 GPIOF (INTC) Vector Address 29 30 GPIOC (INT8, INT9) Vector Address 30 31 GPIOA (KI0 to KI7) Vector Address 31 2 Note: INTS[Num] shows the interrupt source signal. Ex: INTS[1]: RTC interrupt source signal. TMPA910CRA- 86 2010-06-02 TMPA910CRA 3.7.5 SFRs The following lists the SFRs: Base address = 0xF400_0000 Table 3.7.2 SFR (1/2) Register Address Name (base+) Description VICIRQSTATUS 0x0000 IRQ Status Register VICFIQSTATUS 0x0004 FIQ Status Register VICRAWINTR 0x0008 Raw Interrupt Status Register VICINTSELECT 0x000C Interrupt Select Register VICINTENABLE 0x0010 Interrupt Enable Register VICINTENCLEAR 0x0014 Interrupt Enable Clear Register VICSOFTINT 0x0018 Software Interrupt Register VICSOFTINTCLEAR 0x001C Software Interrupt Clear Register VICPROTECTION 0x0020 Protection Enable Register VICSWPRIORITYMASK 0x0024 Software Priority Mask Register - 0x0028 Reserved VICVECTADDR0 0x0100 Vector Address 0 Register VICVECTADDR1 0x0104 Vector Address 1 Register VICVECTADDR2 0x0108 Vector Address 2 Register VICVECTADDR3 0x010C Vector Address 3 Register VICVECTADDR4 0x0110 Vector Address 4 Register VICVECTADDR5 0x0114 Vector Address 5 Register VICVECTADDR6 0x0118 Vector Address 6 Register VICVECTADDR7 0x011C Vector Address 7 Register VICVECTADDR8 0x0120 Vector Address 8 Register - 0x0124 Reserved VICVECTADDR10 0x0128 Vector Address 10 Register VICVECTADDR11 0x012C Vector Address 11 Register VICVECTADDR12 0x0130 Vector Address 12 Register VICVECTADDR13 0x0134 Vector Address 13 Register VICVECTADDR14 0x0138 Vector Address 14 Register VICVECTADDR15 0x013C Vector Address 15 Register VICVECTADDR16 0x0140 Vector Address 16 Register VICVECTADDR17 0x0144 Vector Address 17 Register VICVECTADDR18 0x0148 Vector Address 18 Register - 0x014C Reserved VICVECTADDR20 0x0150 Vector Address 20 Register VICVECTADDR21 0x0154 Vector Address 21 Register VICVECTADDR22 0x0158 Vector Address 22 Register VICVECTADDR23 0x015C Vector Address 23 Register - 0x0160 Reserved - 0x0164 Reserved VICVECTADDR26 0x0168 Vector Address 26 Register VICVECTADDR27 0x016C Vector Address 27 Register VICVECTADDR28 0x0170 Vector Address 28 Register VICVECTADDR29 0x0174 Vector Address 29 Register VICVECTADDR30 0x0178 Vector Address 30 Register VICVECTADDR31 0x017C Vector Address 31 Register VICVECTPRIORITY0 0x0200 Vector Priority 0 Register VICVECTPRIORITY1 0x0204 Vector Priority 1 Register VICVECTPRIORITY2 0x0208 Vector Priority 2 Register VICVECTPRIORITY3 0x020C Vector Priority 3 Register TMPA910CRA- 87 2010-06-02 TMPA910CRA Table 3.7.3 SFR (2/2) Register Address Name (base+) Description VICVECTPRIORITY4 0x0210 Vector Priority 4 Register VICVECTPRIORITY5 0x0214 Vector Priority 5 Register VICVECTPRIORITY6 0x0218 Vector Priority 6 Register VICVECTPRIORITY7 0x021C Vector Priority 7 Register VICVECTPRIORITY8 0x0220 Vector Priority 8 Register - 0x0224 Reserved VICVECTPRIORITY10 0x0228 Vector Priority 10 Register VICVECTPRIORITY11 0x022C Vector Priority 11 Register VICVECTPRIORITY12 0x0230 Vector Priority 12 Register VICVECTPRIORITY13 0x0234 Vector Priority 13 Register VICVECTPRIORITY14 0x0238 Vector Priority 14 Register VICVECTPRIORITY15 0x023C Vector Priority 15 Register VICVECTPRIORITY16 0x0240 Vector Priority 16 Register VICVECTPRIORITY17 0x0244 Vector Priority 17 Register VICVECTPRIORITY18 0x0248 Vector Priority 18 Register - 0x024C Reserved VICVECTPRIORITY20 0x0250 Vector Priority 20 Register VICVECTPRIORITY21 0x0254 Vector Priority 21 Register VICVECTPRIORITY22 0x0258 Vector Priority 22 Register VICVECTPRIORITY23 0x025C Vector Priority 23 Register - 0x0260 Reserved - 0x0264 Reserved VICVECTPRIORITY26 0x0268 Vector Priority 26 Register VICVECTPRIORITY27 0x026C Vector Priority 27 Register VICVECTPRIORITY28 0x0270 Vector Priority 28 Register VICVECTPRIORITY29 0x0274 Vector Priority 29 Register VICVECTPRIORITY30 0x0278 Vector Priority 30 Register VICVECTPRIORITY31 0x027C Vector Priority 31 Register VICADDRESS 0x0F00 Vector Address Register TMPA910CRA- 88 2010-06-02 TMPA910CRA 1. VICIRQSTATUS (IRQ Status Register) Address = (0xF400_0000) + (0x0000) Bit Bit [31:0] Type Symbol IRQStatus RO Reset Value 0x00000000 Description IRQ interrupt status after masked (for each bit) 0y0: Interrupt is inactive. 0y1: Interrupt is active. [Description] a. <IRQStatus> This bit shows IRQ interrupt status after masked. Refer the Figure 3.7.2 Status flag relation . IRQStatus [31:0] correspond to interrupt numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please. Example: When bit 0 of this register is set to 1, a WDT interrupt (interrupt source number 0) has been requested. 2. VICFIQSTATUS (FIQ Status Register) Address = (0xF400_0000) + (0x0004) Bit Bit [31:0] Symbol FIQStatus Type RO Reset Value 0x00000000 Description FIQ interrupt status after masked (for each bit) 0y0: Interrupt is inactive. 0y1: Interrupt is active. [Description] a. <FIQStatus> This bit shows FIQ interrupt status after masked. Refer the Figure 3.7.2 Status flag relation. FIQStatus [31:0] correspond to interrupt source numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please Example: When bit 0 of this register is set to 1, a WDT interrupt (interrupt source number 0) has been requested. TMPA910CRA- 89 2010-06-02 TMPA910CRA 3. VICRAWINTR (Raw Interrupt Status Register) Address = (0xF400_0000) + (0x0008) Bit Bit [31:0] Symbol RawInterrupt Reset Type RO Description Value Undefined IRQ interrupt status before masked (for each bit) 0y0: Interrupt is inactive. 0y1: Interrupts is active. [Description] a. <RawInterrupt> This bit shows IRQ interrupt status before masked. Refer the Figure 3.7.2 Status flag relation . RawInterrupt [31:0] correspond to interrupt source numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please Example: When bit 0 of this register is set to 1, a WDT interrupt (interrupt source number 0) has been requested. 4. VICINTSELECT (Interrupt Select Register) Address = (0xF400_0000) + (0x000C) Bit Bit [31:0] Symbol IntSelect Reset Type R/W Description Value 0x00000000 Selects interrupt type (for each bit) 0y0: IRQ 0y1: FIQ [Description] a. <IntSelect> This bit controls Selects interrupt type. IntSelect bit must set before interrupt generation. IntSelect [31:0] correspond to interrupt source numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please Example: When bit 0 of this register is set to 1, the WDT interrupt (interrupt source number 0) is set to be of the FIQ type. Note: Since this LSI supports only one FIQ source, only one of the bits in this register can be set to 1. Before changing the setting of this register, be sure to disable the relevant interrupts. Do not change the setting of this register while the interrupt is active and enabled. TMPA910CRA- 90 2010-06-02 TMPA910CRA 5. VICINTENABLE (Interrupt Enable Register) Address = (0xF400_0000) + (0x0010) Bit Bit [31:0] Symbol IntEnable Type RO Reset Description Value 0x00000000 Interrupt enable read(for each bit) 0y0: Disable 0y1: Enable Address = (0xF400_0000) + (0x0010) Bit Bit [31:0] Symbol IntEnable Type WO Reset Description Value 0x00000000 Interrupt enable (for each bit) 0y0: Invalid 0y1: Enable [Description] a. <IntEnable> READ: Status read register of Interrupt Enable/Disable WRITE: Setting register of Interrupt Enable This register can be set only from disable to enable. Disable setting is controlled by VICINTENCLEAR register. IntEnable [31:0] correspond to interrupt source numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please Example: When bit 0 of this register is set to 1, the WDT interrupt (interrupt source number 0) is enabled. TMPA910CRA- 91 2010-06-02 TMPA910CRA 6. VICINTENCLEAR (Interrupt Enable Clear Register) Address = (0xF400_0000) + (0x0014) Bit Bit [31:0] Symbol IntEnable Clear Type WO Reset Description Value Undefined Interrupt disable (for each bit) 0y0: Invalid 0y1: Disable [Description] a. <IntEnable Clear> This bit controls interrupt disable. Enable setting of VICINTENABLE register can be cleared, and interruption is disabled. IntEnable Clear [31:0] corresponds to interrupt source numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please 7. VICSOFTINT (Software Interrupt Register) Address = (0xF400_0000) + (0x0018) Bit Bit [31:0] Symbol SoftInt Type WO Reset Description Value 0x00000000 Software interrupt (for each bit) 0y0: Invalid 0y1: Generate a software interrupt Address = (0xF400_0000) + (0x0018) Bit Bit [31:0] Symbol SoftInt Type RO Reset Description Value 0x00000000 Software interrupt (for each bit) 0y0: Inactive 0y1: Active [Description] a. <SoftInt> READ: Status register for Active/Inactive of software interruption. WRITE: Software interruption Active/Inactive control register Set to "1" to each bit, and then software interruption is generated. SoftInt[31:0] correspond to interrupt source numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please TMPA910CRA- 92 2010-06-02 TMPA910CRA 8. VICSOFTINTCLEAR (Software Interrupt Clear Register) Address = (0xF400_0000) + (0x001C) Bit Bit [31:0] Symbol SoftIntClear Reset Type WO Description Value Undefined Software interrupt disable (for each bit) 0y0: Invalid 0y1: Disable [Description] a. <SoftIntClear> This bit controls "disable" for software interruption. Software interruption of VICSOFTINT register can be disabled. SoftIntClear [31:0] correspond to interrupt source numbers 31 to 0, respectively. About the information for interrupt sources of each circuit, refer the Table 3.7.1 Interrupt sources please 9. VICPROTECTION (Protection Enable Register) Address = (0xF400_0000) + (0x0020) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read as undefined. Write as zero. [0] Protection R/W 0y0 Protect mode enable : 0y0: Disable 0y1: Enable [Description] a. <Protection> This bit controls "Protection Control". When protection is enabled, the registers of the interrupt controller can only be accessed in privileged mode. Read/ write operations are available only in privilege mode. TMPA910CRA- 93 2010-06-02 TMPA910CRA 10. VICSWPRIORITYMASK (Software Priority Mask Register) Address = (0xF400_0000) + (0x0024) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15:0] SWPriorityMask R/W 0xFFFF Masks software priority level 0y0: Mask 0y1: Do not mask [Description] a. <SWPriorityMask> This register can be set the software priority level. SWPriorityMask [15:0] correspond to priority levels 15 to 0, respectively. Example: When SWPriorityMask [15:0] = 0xFF7F, interrupts of priority level 7 are masked. 11. VICVECTADDR0 (Vector Address 0 Register) Address = (0xF400_0000) + (0x0100) Bit Bit [31:0] Symbol VectorAddr 0 Type R/W Reset Description Value 0x00000000 ISR address for interrupt source 0 ISR: Interrupt Service Routine [Description] a. <VectorAddr 0> This register can be set the address for Interrupt Service Routine of interrupt sources. Before changing the setting of this register, be sure to disable the relevant interrupts. * VICVECTADDRn (Vector Address n Register)(n = 0 to 8, 10 to18, 20 to 23, 26 to 31) The structure and description of these registers are same as VICVECTADDR0. Please refer to the description of VICVECTADDR0. For the names and addresses of these registers, please refer to Table 3.7.2 .. TMPA910CRA- 94 2010-06-02 TMPA910CRA 12. VICVECTPRIORITY0 (Vector Priority 0 Register) Address = (0xF400_0000) + (0x0200) Bit Bit Reset Type Symbol Description Value [31:4] - - Undefined Read as undefined. Write as zero. [3:0] VectPriority R/W 0y1111 Priority level for interrupt source 0: 0y0000 to 0y1111 [Description] a. <VectPriority> This register can be set the software priority level of IRQ. 0y0000 is highest level, and can set 16 level (0y0000 to 0y1111). If multiple interrupt requests of the same software priority level occur simultaneously, the hardware priority is used to determine the interrupt to be generated. The hardware priority is assigned according to interrupt source numbers: interrupt source number 0 has the highest priority and interrupt source number 31 has the lowest priority. * VICVECTPRIORITYn (Vector Priority n Register)(n = 0 to 8, 10 to 18, 20 to 23, 26 to 31) The structure and description of these registers are same as VICVECTPRIORITY0. Please refer to the description of VICVECTPRIORITY0. The name and address of these registers, please refer to Table 3.7.2.. 13. VICADDRESS (Vector Address Register) Address = (0xF400_0000) + (0x0F00) Bit Bit [31:0] Symbol VectAddr Reset Type R/W Description Value 0x00000000 Address of the currently active Interrupt Service Routine (ISR) [Description] a. <VectAddr> This register can be read current active address of Interrupt Service Routine. And current interruption can be clear. Read: return the address of the currently active Interrupt Service Routine (ISR.) Write: Writing any data to this register clears the current interrupt. Note: A read of this register must only be performed when there is an active interrupt. A write of this register must only be performed at the end of an ISR. TMPA910CRA- 95 2010-06-02 TMPA910CRA 3.8 DMAC (DMA Controller) 3.8.1 Functional Overview The DMA controller has the following features: Table 3.8.1 DMA controller functions Item Function Number of channels 8 ch DMA start Hardware request Description 16 types of DMA requests for peripheral IPs. Refer to Table 3.8.2. Software request Activated by writing values into DMACSoftBReq Bus master 32 bits x 2 (AHB) DMA1, DMA2 Priority DMA channel 0 (high) to DMA channel 7 Hardware-fixed (low) FIFO 4 words x 8 ch Bus width 8/16/32 bits Burst size 1/4/8/16/32/64/128/256 transfer count ~4095 Address Source address incr / no-incr Destination incr / no-incr Source and destination can be programmed separately. Address wrapping is not supported. address Endian Transfer type Interrupt Only little endian is supported. Peripheral circuit (register) to pheripheral DMA cannot start by hardware circuit (register) request in memory to memory Peripheral circuit (register) to memory transfer. Refer to the description of Memory to peripheral circuit (register) DMACCxConfiguration register for Memory to memory details. Terminal count interrupt Transfer error interrupt Special function Scatter/gather function TMPA910CRA- 96 2010-06-02 TMPA910CRA * DMA Transfer Types DMA Transfer Direction 1 Memory-to-Peripheral DMA Request Generator Peripheral DMA Request Used Burst request Description 1: Use bust request in all transactions 2: When the single request, set DMAC busrt to 1 Peripheral-to-Memory Peripheral Burst request/ 2 Single For transactions that are not an integral multiple of the burst size, use both the burst and single request signals. The amount of data left to transfer Burst size request :Use burst transfer (Note 1) The amount of data left to transfer < Burst size None Start condition: : Use single transfer Memory-to-Memory DMAC (Note 2) When enabled, the DMA channel commences transfers without DMA requests. 3 Stop conditions: All transfer data has finished transfer. Disable DMAC channel (Note 2) Peripheral-to-Peripheral Source peripheral Burst Transfer size Source side request/ Single request Destination side 1)Integral multiple Burst request Burst request of the burst size (Note 1) 4 Destination Burst request peripheral 2) Single transfer Single request 3) Not imtegral Burst request multiple of the Single request burst size Note 1: Peripheral that can use the single request: UART and LCDDA. Note 2: Recommendation: You must program memory-to-memory transfers with a low channel priority (DMAC6,7), otherwise the other DMA channels cannot access the bus until the memory-to-memory transfer has finished. 1. Memory-to-peripheral DMACBREQ Peripheral DMAC DMACCLR 2. Peripheral-to-Memory DMACBREQ Peripheral DMAC DMACSREQ DMACCLR AMBA Bus TMPA910CRA- 97 2010-06-02 TMPA910CRA 3. Memory-to-Memory Memory DMAC AMBA Bus 4. Peripheral-to-peripheral 1) Integral multiple of the burst size DMACBREQ DMACBREQ Source Destination DMAC Peripheral Peripheral DMACCLR DMACCLR AMBA Bus 2) Single transfer DMACBREQ Source Peripheral Destination DMAC DMACSREQ Peripheral DMACCLR DMACCLR AMBA Bus 3) Not Integral Multiple of the burst size DMACBREQ DMACBREQ Source Peripheral Destination DMAC DMACSREQ Peripheral DMACCLR DMACCLR AMBA Bus TMPA910CRA- 98 2010-06-02 TMPA910CRA 3.8.2 Block Diagram - [15] LCDDA [14] Reserved [13] Reserved [12] 2 I S0 [11] 2 I S1 [10] Reserved [9] Reserved [8] Reserved [7] Reserved [6] CameraIF0 [5] NANDC0 [4] Reserved [3] Reserved [2] UART0 receive [1] UART0 transmit [0] DMA1 DMA2 AHB CPU Data. slave I/F Control AHB logic master and I/F 1 register burst request Reserved [15] LCDDA [14] Reserved [13] Reserved [12] - [11] - [10] - [9] - [8] - [7] - [6] - [5] - [4] Reserved [3] Reserved [2] UART0 receive [1] UART0 transmit [0] DMA Channel request logic and and response register AHB master I/F 2 I/F Single request Interrupt INTS [16] request (DMACINTERR) INTS [17] (DMACINTTC) DMACCLR[15:0] Table 3.8.2 DMA request number chart Peripheral DMA Request Number Burst Single 0 UART0 transmit UART0 transmit 1 UART0 receive UART0 receive 2 Reserved Reserved 3 Reserved Reserved 4 NANDC0 - 5 CMSI - 6 Reserved - 7 Reserved - 8 Reserved - 9 Reserved - 10 I S1 11 I S0 - 12 Reserved Reserved 13 Reserved Reserved 14 LCDDA LCDDA 15 - Reserved - 2 2 TMPA910CRA- 99 2010-06-02 TMPA910CRA 3.8.3 Register descriptions The following lists the SFRs.: Base address = 0xF410_0000 Table 3.8.3 SFR Register Name DMACIntStaus Address Description (base+) 0x0000 DMAC Interrupt Status Register DMACIntTCStatus 0x0004 DMAC Interrupt Terminal Count Status Register DMACIntTCClear 0x0008 DMAC Interrupt Terminal Count Clear Register DMACIntErrorStatus 0x000C DMAC Interrupt Error Status Register DMACIntErrClr 0x0010 DMAC Interrupt Error Clear Register DMACRawIntTCStatus 0x0014 DMAC Raw Interrupt Terminal Count Status Register DMACRawIntErrorStatus 0x018 DMAC Raw Error Interrupt Status Register DMACEnbldChns 0x01C DMAC Enabled Channel Register DMACSoftBReq 0x020 DMAC Software Burst Request Register DMACSoftSReq 0x024 DMAC Software Single Request Register - 0x028 Reserved - 0x02C Reserved DMACConfiguration 0x030 DMAC Configuration Register - 0x034 Reserved DMACC0SrcAddr 0x100 DMAC Channel0 Source Address Register DMACC0DestAddr 0x104 DMAC Channel0 Destination Address Register DMACC0LLI 0x108 DMAC Channel0 Linked List Item Register DMACC0Control 0x10C DMAC Channel0 Control Register DMACC0Configuration 0x110 DMAC Channel0 Configuration Register DMACC1SrcAddr 0x120 DMAC Channel1 Source Address Register DMACC1DestAddr 0x124 DMAC Channel1 Destination Address Register DMACC1LLI 0x128 DMAC Channel1 Linked List Item Register DMACC1Control 0x12C DMAC Channel1 Control Register DMACC1Configuration 0x130 DMAC Channel1 Configuration Register DMACC2SrcAddr 0x140 DMAC Channel2 Source Address Register DMACC2DestAddr 0x144 DMAC Channel2 Destination Address Register DMACC2LLI 0x148 DMAC Channel2 Linked List Item Register DMACC2Control 0x14C DMAC Channel2 Control Register DMACC2Configuration 0x150 DMAC Channel2 Configuration Register DMACC3SrcAddr 0x160 DMAC Channel3 Source Address Register DMACC3DestAddr 0x164 DMAC Channel3 Destination Address Register DMACC3LLI 0x168 DMAC Channel3 Linked List Item Register DMACC3Control 0x16C DMAC Channel3 Control Register DMACC3Configuration 0x170 DMAC Channel3 Configuration Register DMACC4SrcAddr 0x180 DMAC Channel4 Source Address Register DMACC4DestAddr 0x184 DMAC Channel4 Destination Address Register DMACC4LLI 0x188 DMAC Channel4 Linked List Item Register DMACC4Control 0x18C DMAC Channel4 Control Register DMACC4Configuration 0x190 DMAC Channel4 Configuration Register DMACC5SrcAddr 0x1A0 DMAC Channel5 Source Address Register DMACC5DestAddr 0x1A4 DMAC Channel5 Destination Address Register DMACC5LLI 0x1A8 DMAC Channel5 Linked List Item Register DMACC5Control 0x1AC DMAC Channel5 Control Register DMACC5Configuration 0x1B0 DMAC Channel5 Configuration Register TMPA910CRA- 100 2010-06-02 TMPA910CRA Register Name Address Description (base+) DMACC6SrcAddr 0x1C0 DMAC Channel6 Source Address Register DMACC6DestAddr 0x1C4 DMAC Channel6 Destination Address Register DMACC6LLI 0x1C8 DMAC Channel6 Linked List Item Register DMACC6Control 0x1CC DMAC Channel6 Control Register DMACC6Configuration 0x1D0 DMAC Channel6 Configuration Register DMACC7SrcAddr 0x1E0 DMAC Channel7 Source Address Register DMACC7DestAddr 0x1E4 DMAC Channel7 Destination Address Register DMACC7LLI 0x1E8 DMAC Channel7 Linked List Item Register DMACC7Control 0x1EC DMAC Channel7 Control Register DMACC7Configuration 0x1F0 DMAC Channel7 Configuration Register - 0xFE0 Reserved - 0xFE4 Reserved - 0xFE8 Reserved - 0xFEC Reserved - 0xFF0 Reserved - 0xFF4 Reserved - 0xFF8 Reserved - 0xFFC Reserved - 0x500 Reserved - 0x504 Reserved - 0x508 Reserved - 0x50C Reserved Note: Access the registers by using word reads and word writes. TMPA910CRA- 101 2010-06-02 TMPA910CRA 1. DMACIntStatus (DMAC Interrupt Status Register) Address = (0xF410_0000) + (0x0000) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. [7] IntStatus7 RO 0y0 DMAC channel 7 interrupt status 0y0: Interrupt not requested 0y1 Interrupt requested [6] IntStatus6 RO 0y0 DMAC channel 6 interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [5] IntStatus5 RO 0y0 DMAC channel 5 interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [4] IntStatus4 RO 0y0 DMAC channel 4 interrupt status 0y0: Interrupt not requesed 0y1: Interrupt requested [3] IntStatus3 RO 0y0 DMAC channel 3 interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [2] IntStatus2 RO 0y0 DMAC channel 2 interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [1] IntStatus1 RO 0y0 DMAC channel 1 interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [0] IntStatus0 RO 0y0 DMAC channel 0 interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [Description] a. <IntStatus[7:0]> Indicates the status of the DMAC interrupt after reflecting the status of the terminal count interrupt enable register and error interrupt enable register. An interrupt is requested when a transfer error occurs or the counter completes counting. DMA Terminal Count Interrupt DMACC0Configuration <ITC> DMA Transfer Error Interrupt DMACC0Configuration <IE> DMACIntTCStatus <IntStatusTC0> (Masked Transfer Error Interrupt) DMACIntErrorStatus (Masked Transfer Error Interrupt) DMACIntStatus <IntStatus0> DMACRawIntTCStatus (Raw Terminal Count Interrupt) DMACRawIntErrorStatus (Raw Transfer Error Interrupt) Figure 3.8.1 Block diagram for Interrupt TMPA910CRA- 102 2010-06-02 TMPA910CRA 2. DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register) Address = (0xF410_0000) + (0x0004) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] IntStatusTC7 RO 0y0 Read as undefined. DMAC channel 7 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [6] IntStatusTC6 RO 0y0 DMAC channel 6 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [5] IntStatusTC5 RO 0y0 DMAC channel 5 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [4] IntStatusTC4 RO 0y0 DMAC channel 4 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [3] IntStatusTC3 RO 0y0 DMAC channel 3 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [2] IntStatusTC2 RO 0y0 DMAC channel 2 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [1] IntStatusTC1 RO 0y0 DMAC channel 1 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [0] IntStatusTC0 RO 0y0 DMAC channel 0 terminal count interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [Description] a. <IntStatusTC[7:0]> Indicates the enabled state of the terminal count interrupt. TMPA910CRA- 103 2010-06-02 TMPA910CRA 3. DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register) Address = (0xF410_0000) + (0x0008) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] IntTCClear7 WO 0y0 DMAC channel 7 terminal count interrupt clear 0y0 Invalid 0y1 Clear [6] IntTCClear6 WO 0y0 DMAC channel 6 terminal count interrupt clear 0y0: Invalid 0y1: Clear [5] IntTCClear5 WO 0y0 DMAC channel 5 terminal count interrupt clear 0y0: Invalid 0y1: Clear [4] IntTCClear4 WO 0y0 DMAC channel 4 terminal count interrupt clear 0y0: Invalid 0y1: Clear [3] IntTCClear3 WO 0y0 DMAC channel 3 terminal count interrupt clear 0y0: Invalid 0y1: Clear [2] IntTCClear2 WO 0y0 DMAC channel 2 terminal count interrupt clear 0y0: Invalid 0y1: Clear [1] IntTCClear1 WO 0y0 DMAC channel 1 terminal count interrupt clear 0y0: Invalid 0y1: Clear [0] IntTCClear0 WO 0y0 DMAC channel 0 terminal count interrupt clear 0y0: Invalid 0y1: Clear [Description] a. <IntTCClear [7:0]> Writing 1 to each bit of this register clears the corresponding bit in the DMACIntTCStatus register. TMPA910CRA- 104 2010-06-02 TMPA910CRA 4. DMACIntErrorStatus (DMAC Interrupt Error Status Register) Address = (0xF410_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. [7] IntErrStatus7 RO 0y0 DMAC channel 7 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [6] IntErrStatus6 RO 0y0 DMAC channel 6 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [5] IntErrStatus5 RO 0y0 DMAC channel 5 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [4] IntErrStatus4 RO 0y0 DMAC channel 4 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [3] IntErrStatus3 RO 0y0 DMAC channel 3 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [2] IntErrStatus2 RO 0y0 DMAC channel 2 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [1] IntErrStatus1 RO 0y0 DMAC channel 1 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [0] IntErrStatus0 RO 0y0 DMAC channel 0 error interrupt status 0y0: Interrupt not requested 0y1: Interrupt requested [Description] a. <IntErrStatus[7:0]> These bits shows status of Raw Error interrupt. i TMPA910CRA- 105 2010-06-02 TMPA910CRA 5. DMACIntErrClr (DMAC Interrupt Error Clear Register) Address = (0xF410_0000) + (0x0010) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] IntErrClr7 WO 0y0 DMAC channel 7 error interrupt clear 0y0: Invalid 0y1: Clear [6] IntErrClr6 WO 0y0 DMAC channel 6 error interrupt clear 0y0: Invalid 0y1: Clear [5] IntErrClr5 WO 0y0 DMAC channel 5 error interrupt clear 0y0: Invalid 0y1: Clear [4] IntErrClr4 WO 0y0 DMAC channel 4 error interrupt clear 0y0: Invalid 0y1: Claer [3] IntErrClr3 WO 0y0 DMAC channel 3 error interrupt clear 0y0: Invalid 0y1: Clear [2] IntErrClr2 WO 0y0 DMAC channel 2 error interrupt clear 0y0: Invalid 0y1: Clear [1] IntErrClr1 WO 0y0 DMAC channel 1 error interrupt clear 0y0: Invalid 0y1: Clear [0] IntErrClr0 WO 0y0 DMAC channel 0 error interrupt clear 0y0: Invalid 0y1: Clear [Description] a. <IntErrClr[7:0]> 0y1: Clear Error interrupt request. TMPA910CRA- 106 2010-06-02 TMPA910CRA 6. DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register) Address = (0xF410_0000) + (0x0014) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] RawIntTCS7 RO 0y0 Read as undefined. DMAC channel 7 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [6] RawIntTCS6 RO 0y0 DMAC channel 6 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [5] RawIntTCS5 RO 0y0 DMAC channel 5 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [4] RawIntTCS4 RO 0y0 DMAC channel 4 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [3] RawIntTCS3 RO 0y0 DMAC channel 3 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [2] RawIntTCS2 RO 0y0 DMAC channel 2 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [1] RawIntTCS1 RO 0y0 DMAC channel 1 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [0] RawIntTCS0 RO 0y0 DMAC channel 0 terminal count interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [Description] a. <RawIntTCS[7:0]> The status of raw interrupt terminal count before an interrupt enable TMPA910CRA- 107 2010-06-02 TMPA910CRA 7. DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register) Address = (0xF410_0000) + (0x0018) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. [7] RawIntErrS7 RO 0y0 DMAC channel 7 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [6] RawIntErrS6 RO 0y0 DMAC channel 6 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [5] RawIntErrS5 RO 0y0 DMAC channel 5 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [4] RawIntErrS4 RO 0y0 DMAC channel 4 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [3] RawIntErrS3 RO 0y0 DMAC channel 3 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [2] RawIntErrS2 RO 0y0 DMAC channel 2 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [1] RawIntErrS1 RO 0y0 DMAC channel 1 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [0] RawIntErrS0 RO 0y0 DMAC channel 0 error interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested [Description] a. <RawIntErrS[7:0]> The status of raw error interrupt before an interrupt enable TMPA910CRA- 108 2010-06-02 TMPA910CRA 8. DMACEnbldChns (DMAC Enabled Channel Register) Address = (0xF410_0000) + (0x001C) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] EnabledCH7 RO 0y0 Read as undefined. DMA channel 7 enable status 0y0: Disable 0y1: Enable [6] EnabledCH6 RO 0y0 DMA channel 6 enable status 0y0: Disable 0y1: Enable [5] EnabledCH5 RO 0y0 DMA channel 5 enable status 0y0: Disable 0y1: Enable [4] EnabledCH4 RO 0y0 DMA channel 4 enable status 0y0: Disable 0y1: Enable [3] EnabledCH3 RO 0y0 DMA channel 3 enable status 0y0: Disable 0y1: Enable [2] EnabledCH2 RO 0y0 DMA channel 2 enable status 0y0: Disable 0y1: Enable [1] EnabledCH1 RO 0y0 DMA channel 1 enable status 0y0: Disable 0y1: Enable [0] EnabledCH0 RO 0y0 DMA channel 0 enable status 0y0: Disable 0y1: Enable [Description] a. <EnabledCH[7:0]> 0y0: Applicable channel bit is cleared when DMA transfer has finished. 0y1: Applicable channel DMA is in the enable state. TMPA910CRA- 109 2010-06-02 TMPA910CRA 9. DMACSoftBReq (DMAC Software Burst Request Register) Address = (0xF410_0000) + (0x0020) Bit Bit Symbol Type Reset Description Value [31:15] - - Undefined [14] SoftBReq14 R/W 0y0 Read as undefined. Write as zero. DMA burst request of LCDDA by software 0y0: Invalid when data write 0y1: Generate a DMA burst request [13:12] - - Undefined Read as undefined. Write as zero. [11] SoftBReq11 R/W 0y0 DMA burst request of I S0 by software 2 0y0: Invalid when data write 0y1: Generate a DMA burst request [10] SoftBReq10 R/W 0y0 2 DMA burst request of I S1 by software 0y0: Invalid when data write 0y1: Generate a DMA burst request [9] Reserved R/W 0y0 Read as undefined. Write as zero. [8] Reserved R/W 0y0 Read as undefined. Write as zero. [7] Reserved R/W 0y0 Read as undefined. Write as zero. [6] Reserved R/W 0y0 Read as undefined. Write as zero. [5] SoftBReq5 R/W 0y0 DMA burst request of CMSI by software 0y0: Invalid when data write 0y1: Generate a DMA burst request [4] SoftBReq4 R/W 0y0 DMA burst request of NANDC0 by software 0y0: Invalid when data write 0y1: Generate a DMA burst request [3:2] - - Undefined [1] SoftBReq1 R/W 0y0 Read as undefined. Write as zero. DMA burst request of UART0 receive by software 0y0: Invalid when data write 0y1: Generate a DMA burst request [0] SoftBReq0 R/W 0y0 DMA burst request of UART0 transmit by software 0y0: Invalid when data write 0y1: Generate a DMA burst request [Description] a. <SoftBReq[14:0]> This register is used to set DMA burst transfer requests by software. Upon completion of a DMA burst transfer, the corresponding bit of SoftBReq [14:0] is cleared. The state of the burst-request is led when leading. (The demand by the peripheral circuitry is included. ). Note: Making DMA request by software and a hardware peripheral simultaneously is prohibited. TMPA910CRA- 110 2010-06-02 TMPA910CRA 10. DMACSoftSReq (DMAC Software Single Request Register ) Address = (0xF410_0000) + (0x0024) Bit Bit Symbol Type Reset Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15] Reserved - Undefined Read as undefined. Write as zero. [14] SoftSReq14 R/W 0y0 DMA single request by software for LCDDA 0y0: Invalid when data write 0y1: Generate a DMA single request [13:12] - - Undefined Read as undefined. Write as zero. [11:4] - - Undefined Read as undefined. Write as zero. [3:2] - - Undefined Read as undefined. Write as zero. [1] SoftSReq1 R/W 0y0 DMA single request by software for UART0 receive 0y0: Invalid when data write 0y1: Generate a DMA single request [0] SoftSReq0 R/W 0y0 DMA single request b software for UART0 transmit 0y0: Invalid when data write 0y1: Generate a DMA single request [Description] a. <SoftSReq[14:0]> This register is used to configure the DMA single transfer requests by software. Upon completion of a DMA single transfer, the corresponding bit of SoftSReq [14:0] is cleared. The state of a single request is led when leading. (The demand by the peripheral circuitry is included. ). Note: Making DMA request by software and a hardware peripheral simultaneously is prohibited. TMPA910CRA- 111 2010-06-02 TMPA910CRA 11. DMACConfiguration (DMAC Configuration Register) Address = (0xF410_0000) + (0x0030) Bit Bit Symbol Type Reset Description Value [31:3] - - Undefined [2] M2 R/W 0y0 Read as undefined. Write as zero. DMA2 endianness 0y0 Little endian mode 0y1 Reserved [1] M1 R/W 0y0 DMA1 endianness 0y0 Little endian mode 0y1 Reserved [0] E R/W 0y0 DMA circuit control 0y0: Stopped 0y1: Active [Description] a. <E> Write/read operation can be executed to any of the DMAC registers only when the DMA circuit is active. To perform DMA operation, the DMA circuit must always be active. TMPA910CRA- 112 2010-06-02 TMPA910CRA 12. DMACC0SrcAddr (DMAC Channel0 Source Address Register) Address = (0xF410_0000) + (0x0100) Bit Bit [31:0] Symbol SrcAddr Type R/W Reset Description Value 0x00000000 Set the DMA transfer source address [Description] a. <SrcAddr> Software configures each register directly before the channel is enabled. When the DMAchannel is enabled, the register is updated as the destination address is incremented and by following the linked list when a complete packet of data has been transferred. Reading the register when the channel is active does not provide useful information. This is because by the time the software has processed the value read, the channel might have progressed. It is intended to be read-only when a channel has stopped. In this case, it shows the destination address of the last item read. When transfer is taking place, don't update this register. If you want to change the channel configurations, you must disable the channel first with the DMACCxConfiguration register and then reconfigure the relevant register. * DMACCxSrcAddr (DMAC Channel x Source Address Register) (x = 0 to 7) The DMACCxSrcAddr regusters have the same structure as DMACC0SrcAddr. Please refer to the descriptions of DMACC0SrcAddr. For the names and addresses of these registers, please refer to Table 3.8.3. TMPA910CRA- 113 2010-06-02 TMPA910CRA 13. DMACC0DestAddr (DMAC Channel0 Destination Address Register) Address = (0xF410_0000) + (0x0104) Bit Bit [31:0] Symbol DestAddr Type R/W Reset Description Value 0x00000000 Set the DMA transfer destination address [Description] a. <DestAddr> When transfer is taking place, don't update this register. If you want to change the channel configuration, you must disable the channel first with the DMACCxConfiguration register and then reconfigure the relevant registers. * DMACCxDestAddr (DMAC Channel x Destination Address Register) (x = 0 to 7) The DMACCxDestAddr registers have the same structure as DMACC0DestAddr. Please refer to the description of DMACC0DestAddr. The name and address of these registers, please refer to Table 3.8.3. TMPA910CRA- 114 2010-06-02 TMPA910CRA 14. DMACC0LLI (DMAC Channel0 Linked List Item Register) Address = (0xF410_0000) + (0x0108) Bit Bit Symbol Type Reset Description Value [31:2] LLI R/W 0x00000000 Set the start address of the next transfer information [1] - - Undefined Read as undefined. Write as zero. [0] LM R/W 0y0 AHB master for storing LLI: 0y0: DMA1 0y1: DMA2 [Description] a. <LLI> The value set to <LLI> must be within 0xFFFF_FFF0. If the LLI is 0, then the current LLI is the last in the chain, and the DMA channel is disabled after all DMA transfers associated with it are completed. * DMACCxLLI (DMAC Channel x Linked List Item Register) (x = 0 to 7) The DMACCxLLI registers have the same structure as DMACC0LLI. Please refer to the description of DMACC0LLI. The names and addresses of these registers, please refer to Table 3.8.3. TMPA910CRA- 115 2010-06-02 TMPA910CRA 15. DMACC0Control (DMAC Channel0 Control Register) Address = (0xF410_0000) + (0x010C) Bit Bit Symbol Type Reset Description Value [31] I R/W 0y0 [30] Prot[3] R/W 0y0 [29] Prot[2] R/W 0y0 [28] Prot[1] R/W 0y0 [27] DI R/W 0y0 [26] SI R/W 0y0 [25] D R/W 0y0 [24] S R/W 0y0 [23:21] Dwidth[2:0] R/W 0y000 [20:18] Swidth[2:0] R/W 0y000 [17:15] DBSize[2:0] R/W 0y000 [14:12] SBSize[2:0] R/W 0y000 [11:0] TransferSize R/W 0x000 Terminal count interrupt enable register when using the scatter/gather function 0y0: Disable 0y1: Enable Control cache permission HPROT[3] 0y0: Noncacheable 0y1: Cacheable Control buffer permission HPROT[2] 0y0: Nonbufferable 0y1: Bufferable Control privileged mode HPROT[1] 0y0: User mode 0y1: Privileged mode Increment the transfer destination address 0y0: Do not increment 0y1: Increment Increment the transfer source address 0y0: Do not increment 0y1: Increment Transfer destination AHB Master 0y0: DMA1 0y1: DMA2 Transfer source AHB Master 0y0: DMA1 0y1: DMA2 Transfer destination bit width 0y000: Byte (8 bits) 0y001: Half-word (16 bits) 0y010: Word (32 bits) other: Reserved Transfer source bit width 0y000: Byte (8 bits) 0y001: Half-word (16 bits) 0y010: Word (32 bits) other: Reserved Transfer destination burst size: 0y000 1 beat 0y001 4 beats 0y010: 8 beats 0y011: 16 beats 0y100: 32 beats 0y101: 64 beats 0y110: 128 beats 0y111: 256 beats Transfer source burst size: 0y000: 1 beat 0y001: 4 beats 0y010: 8 beats 0y011: 16 beats 0y100: 32 beats 0y101: 64 beats 0y110: 128 beats 0y111: 256 beats Set the total transfer count TMPA910CRA- 116 2010-06-02 TMPA910CRA [Description] The description below applies to all channels. a. <I> It is enable register of terminal count interrupt. Terminal count interrupt is generated by setting <I>=1 and DAMCCxConfiguration Register<ITC>=1.This bit is set to enable in DMAC configuration flow of the final transfer when using Scatter/gather function, and it is possible to generate terminal count interrupt when the only final transfer is performed. To generate an interrupt at transferring, this bit also must be set to enable by setting to "1". b. Prot[3] Control cache permission HPROT[3] 0y0: Noncacheable 0y1: Cacheable c. Prot[2] Control buffer permission HPROT[2] 0y0: Nonbufferable 0y1: Bufferable d. Prot[1] Control privileged mode HPROT[1] 0y0: User mode 0y1: Privileged mode e. DI Increment the transfer destination address 0y0: Do not increment 0y1: Increment f. SI Increment the transfer source address 0y0: Do not increment 0y1: Increment g. D Transfer destination AHB Master 0y0: DMA1 0y1: DMA2 TMPA910CRA- 117 2010-06-02 TMPA910CRA h. S Transfer source AHB Master 0y0: DMA1 0y1: DMA2 i. Dwidth[2:0] Transfer destination bit width 0y000: Byte (8 bits) 0y001: Half-word (16 bits) 0y010: Word (32 bits) other: Reserved j. <Swidth[2:0]> The transfer source bit width must be an integral multiple of the transfer destination bit width. k. <DBSize[2:0]> Note: The burst size set in DBsize is unrelated to HBURST of the AHB bus. l. <SBSize[2:0]> Note: The burst size set in SBsize is unrelated to HBURST of the AHB bus. m. <TransferSize> Specifies the total number of transfers when the DMAC is operating as a flow controller. The <TransferSize> value decrements with respect to each DMA transfer until it reaches 0. On read, the number of transfers yet to be performed is read. The total transfer count should be specified in units of the transfer source bit width. Examples: <Swidth> Note: Transfer count unit 8 bits byte 16 bits half-word 32 bits word If the transfer source bit length is smaller than the transfer destination bit length, caution is required in specifying the total transfer count. Make sure that the following equation is satisfied. Transfer source bit length x Total transfer count = Transfer destination bit length x N N: Integer TMPA910CRA- 118 2010-06-02 TMPA910CRA * DMACCxControl (DMAC Channel x Control Register) (x = 0 to 7) The DMACCxControl registers have the same structure as DMACC0Control. Please refer to the description of DMACC0Control. For the names and addresses of these registers, please refer to Table 3.8.3. TMPA910CRA- 119 2010-06-02 TMPA910CRA 16. DMACC0Configuration (DMAC Channel0 Configuration Register) Address = (0xF410_0000) + 0x0110 Bit Bit Symbol Type Reset Description Value [31:19] - - Undefined [18] Halt R/W 0y0 Read as undefined. Write as zero. 0y0: DMA requests accepted 0y1: DMA requests ignored [17] Active RO 0y0 Read: 0y0: No data in the FIFO 0y1: The FIFO has data Write: [16] Lock R/W 0y0 Invalid 0y0: Disable lock transfers 0y1: Enable lock transfers [15] ITC R/W 0y0 Terminal count interrupt enable register 0y0: Disable interrupts 0y1: Enable interrupts [14] IE R/W 0y0 Error interrupt enable register 0y0: Disable interrupts 0y1: Enable interrupts [13:11] FlowCntrl R/W 0y000 FlowCntrl set value Transfer Mode 0y000 Memory to Memory 0y001 Memory to Peripheral 0y010 Peripheral to Memory 0y011 Peripheral to Peripheral 0y100-0y111: Reserved [10] - - Undefined Read as undefined. Write as zero. [9:6] DestPeripheral R/W 0y000 Transfer destination peripheral (Note1) [5] - - Undefined Read as undefined. Write as zero. [4:1] SrcPeripheral R/W 0y000 Transfer source peripheral (Note1) 0y000-0y1111 0y000-0y1111 [0] E R/W 0y0 Channel enable 0y0: Disable 0y1: Enable Note: Please refer to Table 3.8.2 DMA request number chart. [Description] a. ITC It is an enable register of terminal count interrupt. Terminal count interrupt is generated by setting <ITC>=1 and DMACCxControl Register<I>=1. TMPA910CRA- 120 2010-06-02 TMPA910CRA b. < FlowCntrl> This bit sets the transfer mode. 0y000: Memory to Memory 0y001: Memory to Peripheral 0y010: Peripheral to Memory 0y011: Peripheral to Peripheral 0y100 to 0y111: Reserved Note: When you selected Memory-to-Memory, hardware start triggered by DMA is not supported. Transfer is started by writing <E>= 1. c. <DestPeripheral> This is a DMA request peripheral number in binary. This setting will be ignored if memory is specified as the transfer destination. d. <SrcPeripheral> This is a DMA request peripheral number in binary. This setting will be ignored if memory is specified as the transfer source. e. <E> This bit is used to enable or disable the channel. If the channel is disabled during a transfer, the data in the channel's FIFO will be lost. To re-start, the channel must be reset. To temporarily stop DMA transfer, use the <Halt> bit to disable DMA requests, poll the <Active> bit until it becomes 0, and then clear the <E> bit to disable the channel. * DMACCxConfiguration (DMAC Channel x Configuration Register)(x = 0 to 7) The structure and description of these registers are same as DMACC0Configuration. Please refer to the description of DMACC0Configuration. The names and addresses of these registers, please refer to Table 3.8.3. TMPA910CRA- 121 2010-06-02 TMPA910CRA * DMAC configuration flow Ex: using DMAC ch1, transfer from Memory to built-in FIFO of I2S Total transfer data size: 32 words Transfer count unit: Swidth = Word Total transfer count: 32 counts DMACConfiguration 0x00000001 ; Set DMAC Active DMACC1SrcAddr Memory address ; Source address (DMAC ch1) ; Destination address DMACC1DestAddr I2STDAT DMACC1Control 0x04492020 ; Destination address fixed ; Source address increment ; Swidth = word, Dswidth = word ; DBSize= 8 bursts, SBSize= 8 bursts (Note) ; TransferSize = 32 counts DMACC1Configuration 0x00000a81 ; channel1 Enable, 2 ; Memory to Peripheral (I S1) I2STDMA1 2 ; I S configuration and Preparation 0x00000001 2 ; I S DMA Ready and request DMA transfer Note: Please set Burst size equivalent to the FIFO size of Peripheral. TMPA910CRA- 122 2010-06-02 TMPA910CRA 3.8.4 Special Function 1) Scatter/gather function When a part of image data is cut off and transferred, the image data is not be handled as consecutive data. The addresses of the image data to be transferred are scattered according to specific rule. Since DMA can only transfer data to consecutive addresses, the transfer settings must be reconfigured each time a gap occurs in the sequence of transfer addresses. Addresses are not continuous. A part of screen image is cut out. Screen data Screen image The scatter/gather function enables a continuous DMA operation without involving the CPU by allowing the transfer settings (source address, destination address, transfer count, transfer bus width) to be re-loaded each time a specified number of DMA transfers have been completed. This is done by using the linked lists (LLI).. The scatter/gather function is controlled by setting the DMACCxLLI register to 1. A linked list includes information comprised of the following four words: 1) DMACCxSrcAddr 2) DMACCxDestAddr 3) DMACCxLLI 4) DMACCxControl It is also possible to generate interrupt in conjunction with the scatter/gather function. Terminal count interrupt is generated by setting both DMACCxControl Register<I>=1 and DMACCxConfiguration Register<ITC>=1. In case that terminal count interrupt is generated only when the final DMA transfer using scatter/gather function is performed, set DMACCxControl Register<I>=0 and DMACCxConfiguration Register<ITC>=1 to start transfer, and set <I>=1 in the final DMA transfer configuration flow to generate e terminal count interrupt only during the final DMA transfer. TMPA910CRA- 123 2010-06-02 TMPA910CRA 2) Linked list operation To use the scatter/gather function, a series of linked lists should be created to define source and destination data areas. LLI enables to transfer unordered multiple blocks sequentially. Each LLI transfers data based on the configuration of normal DMA continuous transfer. Upon completion of each DMA transfer, the next LLI is loaded to continuously perform DMA operation (daisy-chained operation). The following shows a setting example: 1. Set the information for the first DMA transfer to the DMA registers. 2. Write the information for the second and subsequent transfers to the memory space of the address specified by "next LLI AddressX". 3. To finish the linked list operation with the Nth DMA transfer, set "next LLI AddressX" to 0x00000000. Directly specified in the LLI Address2 DMA setting registers LLI AddressN +0 Source Address1 Source Address2 +4 Destinaton Address1 Destination Address2 Source AddressN +8 Next LLI Address2 Next LLI Address2 0x00000000 +C Control register value Control register value Control register value Destination AddressN Source memory Destination memory image image TMPA910CRA- 124 2010-06-02 TMPA910CRA Example: When transferring data in the area enclosed by the square 0x00200 0x00E00 0x0A000 0x0B000 0x0C000 DMACCxSrcAddr: DMACCxDestAddr: DMACCxLLI: DMACCxControl: 0x0A200 Destination address 1 0x200000 Set the number of burst transfers, etc. Linked List 0x200000 0x0B200(SrcAddr) 0x200010 0x0C000(SrcAddr) +4 Dest Addr2 +4 Dest Addr3 +8 +C 0x200010 Control register value +8 +C 32'h00000000 Control register value TMPA910CRA- 125 Indicates that a sequence of transfers ends with this LLI. 2010-06-02 TMPA910CRA- 126 USB2 LCDD NANDF AVDD3C DVCC3LCD DVCC3IO RTCK RESETn NDD7 SV SW LPRG2 SU NDRB NDD6 LPRG1 NDCE0n NDD4 LCLLP NDCLE NDD3 LCLFP LD3 REXT TRSTn XT2 SMCCLK SMCOEn X2 DMCDCLKN DMCDDM1 X1 DMCSCLK DMCDCLKP DMCDDM0 DMCSDQM1 DMCSDQM0 DMCWEn A[24] NDALE NDD2 LCLLE LD2 TDI NDWEn NDD1 LCLAC LD1 DM TMS NDREn NDD0 LCLCP LD0 DP TCK SELJTAG SELDVCCM SELMEMC XT1 DMCAP DMCSDQM3 DMCSDQM2 DMCCASn DMCRASn A[25] Note 2: The alias "Sx" in the table above is only a symbol and does not have any general-purpose port function. NDCE1n NDD5 LPRG0 LD4 LD5 TDO TEST0n ST LD6 AM0 SMCWEn VSENS LD7 AM1 SMCBE1n SR SP SN SM SMCWAITn DMCCLKIN DMCDDQS1 DMCDDQS0 SL SMCBE2n SMCBE3n DMCBA0 SK DMCBA1 SMCAVDn DMCCKE SMCCS1n SMCCS0n SMCBE0n SJ SMCCS3n SMCCS2n DMCCSn SH 7 8 8 8 4 6 3 8 8 8 8 8 8 8 A[15:8] SF A[23:16] 8 A[7:0] SE SG 8 D[31:24] SD pads No. of 8 Bit 0 D[23:16] Bit 1 SC Bit 2 8 Bit 3 D[15:8] Bit 4 SB Bit 5 8 Bit 6 D[7:0] Bit 7 SA Alias Note 1: Dedicated pins (with no port function). JTAG DVCC3IO etc. mode setting, DVCC1C Clock, Memory DVCC3IO DVCCM Destination No. of external INT pins No. of internal INT I/O port vectors port Open-drain 3.9 Supply Power TMPA910CRA Port Functions The list of the port pin functions and input-output port programming show how to configure each pin. Information on power sources is also provided as different power sources are used for individual external pins. Table 3.9.1 TMPA910CRA pin assignment (dedicated pins) 2010-06-02 TMPA910CRA- 127 PT PR PP PN PM PL PK PJ PH PG PF PE PD PC I2C1CL CMSD6 CMSD5 MY AN5 INT8 MLDALMn KO5 KI5 Bit 5 MLDALM KO3 KI3 Bit 3 CMSD4 MX AN4 CMSVSY CMSD3 AN3 PWM2OUT PWM0OUT FSOUT KO4 KI4 Bit 4 CMSHBK CMSD2 AN2 PWE KO2 KI2 Bit 2 CMSHSY CMSD1 AN1 KO9 KO1 KI1 Bit 1 CMSPCKI CMSD0 AN0 KO8 KO0 KI0 Bit 0 X1USB U1CTSn INT6 U1RXD INT5 INTE INTF INT7 U0RIn U0DTRn LD21 LD13 INTG LD22 LD14 U0RTSn LD23 LD15 U1TXD INT4 INTD U0DSRn I2SSCLK LD20 LD12 LD18 LD10 SP1DO SP0DI INT3 U0DCDn SP0DO INTH INT2 U0CTSn I2S1MCLK I2S1DATO SP1DI I2S0MCLK I2S0DATI LD19 LD11 SP0CLK FCOUT SMCWPn, INT1 SIR0IN U0RXD I2S1CLK SP1CLK I2S0CLK LD17 LD9 SP0FSS RESETOUTn INT0 SIR0OUT U0TXD I2S1WS SP1FSS I2S0WS LD16 LD8 SDC1CLK SDC1CD SDC1WP SDC1CMD SDC1DAT3 SDC1DAT2 SDC1DAT1 SDC1DAT0 SDC0CLK SDC0CD SDC0WP SDC0CMD SDC0DAT3 SDC0DAT2 SDC0DAT1 SDC0DAT0 INTC I2C1DA CMSD7 PX INTA(TSI) PY I2C0CL KO6 KI6 Bit 6 INTB INT9 I2C0DA KO7 KI7 PA PB Bit 7 Alias Note 1: Dual-purpose pins (they have the port function.) Note 2: The alias "Px" in the table above indicates the general-purpose port function. UART1 USB SPIC0, Memory DVCCM DVCC3IO INT INT UART0 I2S1 SPIC1 DVCC3IO DVCC3IO DVCC3I2S LCDD DVCC3LCD I2S0 SDcard I2C1 CMOS-IS TSI,INT ADC Other INT I2C0 Key Destination DVCC3IO DVCC3CMS AVCC3AD DVC3IO Power Supply 8 1 8 8 3 4 8 4 5 8 1 1 8(I/O) 1(I/O) 2(O) 8(I/O) 8(I/O) 4(I/O) 5(I/O) 8(O) 8(O) 8(I/O) 2(I/O) 4(I) 8(I) 8(I) 3(I/O) 5(O) 8(O) 8(I) I/O port 8 1 1 1 1 1 No. of internal INT vectors 8(I/O) 1 2 2 8 No. of external INT pins 8 8 6 8 8 8 8 8 pads No. of 2 8 8 port Open-drain TMPA910CRA Table 3.9.2 TMPA910CRA pin assignment (dual-purpose pins) 2010-06-02 R/W RO RO WO R/W GPIOnIE GPIOnRIS GPIOnMIS GPIOnIC GPIOnODE R/W GPIOnIS R/W R/W GPIOnFR2 GPIOnIEV R/W GPIOnFR1 R/W R/W GPIOnDIR GPIOnIBE R/W GPIOnDATA Interrupt sensitivity register Function register 2 Function register 1 Data direction register Data register Description TMPA910CRA- 128 Interrupt enable register Interrupt event register 0x0C00 0x081C 0x0818 register Open-drain output enable Interrupt clear register register Masked interrupt status 0x0814 Raw interrupt status register 0x810 0x080C 0x0808 Interrupt-both-edge register 0x0804 0x0428 0x0424 0x0400 -0x03FC 0x0000 Register Name R/W Address Enable Interrupt requested Interrupt requested Clear Disable No interrupt requested No interrupt requested Open-drain output Rising edge or High level Falling edge or Low level Level Both-edge 3-state output Note Note 0x1F Note Note 0x00 0x00 0x00 Note Note 0x00 0x00 0x00 0x00 0x03 0x00 0xFF 0xFF 0xEF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0xFD 0XFF Port A Port B Port C Port D Port E Port F Port G Port H Port J Port K Port L Port M Port N Port P PortR PortT Initial Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 No register exists. Writes are prohibited depending on the bits. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Note: Reserved: Don't access this register. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Function 1 input or Note Note 0x00 0x3F 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Note 0x01 0x00 Output enable Function 2 input or Note Note 0x00 0x00 Note Note Note Note Note Note 0x00 Note 0x00 Note Note Note Output enable Output port 1 Single edge Edge GPIO GPIO Input port 0 Meaning TMPA910CRA Table 3.9.3 TMPA910CRA address and initial value table 2010-06-02 TMPA910CRA 3.9.1 Data Registers [Notes on data registers] All data registers allow all the 8 bits to be read or written simultaneously. It is also possible to mask certain bits in reading from or writing to the data registers. Data registers allow accesses to a 256-address space (0x0000 to 0x03FC). (Assume that addresses are shifted to the high-order side by 2 bits. The lower 2 bits have no meaning. Valid addresses exist at every 4 addresses, such as 0x000, 0x0004, and so on.) Accesses to the 256-address space are done through the same data register. Valid bits vary according to the address to be accessed. Bits [9:2] of the address to be accessed correspond to bits [7:0] of the data register. Address bits that are 1 are accessed in the data register and address bits that are 0 are masked. Address[9:2] Bit9 Bit8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit mask bm7 bm6 bm5 bm4 bm3 bm2 bm1 bm0 * Example: Writing 0x93 to address 0x00E8 of Port C by using bit masks bit mask bm7 0 GPIOCDATA Before write bm6 0 PC7 Write data bm5 1 PC6 1 0 1 bm4 1 PC5 0 0 1 bm3 1 PC4 0 0 1 bm2 0 PC3 1 bm1 1 PC2 0 0 1 0 1 bm0 0 PC1 0 0 1 PC0 1 1 0 1 0 1 GPIOCDATAPC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Retained Retained 0 Write 1 Write 0 Write Retained 1 Write Retained * Example: Reading 0x12 from address 0x00E8 of Port C by using bit masks bit mask GPIOCDATA Read data bm7 0 PC7 1 0 Read bm6 0 PC6 0 0 Read bm5 1 PC5 0 0 Read bm4 1 bm3 1 PC4 1 1 Read PC3 0 0 Read bm2 0 PC2 0 0 Read bm1 1 PC1 1 1 Read bm0 0 PC0 1 0 Read Note: All the bits are valid in accessing 0x03FC, and no bits are valid in accessing 0x0000. TMPA910CRA- 129 2010-06-02 TMPA910CRA 3.9.2 Port Function Settings This section describes the settings of Port A through Port T that can also function as general-purpose ports. Each port should basically be accessed in word (32-bit) units. 3.9.2.1 Port A Port A can be used not only as a general-purpose input pin with pull up but also as key input pin. By enabling interrupts, Port A is used as key input pins (K17-K10). General-purpose input and Key input function settings Function General-purpose input Data Value Interrupt Enable GPIOADATA GPIOAIE * 0/1 Key input Bit 7 KI7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KI6 KI5 K4 KI3 KI2 KI1 KI0 Note: All bits support the interrupt function. All bits are provided with pull up resisters. Base address = 0xF080_0000 Register Address Name (base+) Description GPIOADATA 0x03FC PortA Data Regsiter - 0x0400 Reserved - 0x0424 Reserved - 0x0428 Reserved GPIOAIS 0x0804 Port A Interrupt Select Register (Level and Edge) GPIOAIBE 0x0808 Port A Interrupt Select Register (Single edge and Both edge) GPIOAIEV 0x080C Port A Interrupt Select Register (Falling edge/Low level and Rising edge/High level) GPIOAIE 0x0810 Port A Interrupt Enable Register GPIOARIS 0x0814 Port A Interrupt Status Register (Raw) GPIOAMIS 0x0818 Port A Interrupt Status Register (Masked) GPIOAIC 0x081C Port A Interrupt Clear Register - 0x0C00 Reserved TMPA910CRA- 130 2010-06-02 TMPA910CRA 1. GPIOADATA (Port Data Regsiter) Address = (0xF080_0000) + (0x03FC) Bit Bit Reset Type Symbol Bit Mask Value Description [31:8] - - Undefined - Read as undefined. Write as zero. [7:0] PA[7:0] RO 0xFF Bm7:0 Port A data register [Description] a. <PA[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOAIS (Port A Interrupt Select Register (Level and Edge)) Address = (0xF080_0000) + (0x0804) Bit Bit Type Symbol Reset Value [31:8] - - Undefined [7:0] PA7IS to PA0IS R/W 0x00 Description Read as undefined. Written as zero. Port A interrupt sensitivity register (for each bit) 0y0: Edge-sensitive 0y1: Level-sensitive [Description] a. <PA7IS to PA0IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive TMPA910CRA- 131 2010-06-02 TMPA910CRA 3. GPIOAIBE (Port A Interrupt Select Register (Single edge and Both edge)) Address = (0xF080_0000) + (0x0808) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PA7IBE to A0IBE R/W 0x00 Port A interrupt both-edge register (for each bit) 0y0: Single edge 0y1: Both-edge [Description] a. <PA7IBE to PA0IBE> Interrupt both-edge register: Selects single edge or both-edge. 0y0: Single edge 0y1: Both-edge 4. GPIOAIEV (Port A Interrupt Select Register ("Falling edge/Low level" and "Rising edge/High level")) Address = (0xF080_0000) + (0x080C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PA7IEV to PA0IEV R/W 0x00 Port A interrupt event register (for each bit) 0y0: Falling edge/Low level 0y1: Rising edge/High level [Description] a. <PA7IEV to PAIEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and Low level or High level for level-sensitive interrupts. 0y0: Falling edge/Low level 0y1: Rising edge/High level 5. GPIOAIE (Port A Interrupt Enable Register) Address = (0xF080_0000) + (0x0810) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PA7IE to PA0IE R/W 0x00 Port A interrupt enable register (for each bit) 0y0: Disable 0y1: Enable [Description] a. <PA7IE to PA0IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disable 0y1: Enable TMPA910CRA- 132 2010-06-02 TMPA910CRA 6. GPIOARIS (Port A Interrupt Status Register (Raw)) Address = (0xF080_0000) + (0x0814) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. [7:0] PA7RIS to PA0RIS RO 0x00 Port A interrupt raw status register (for each bit) 0y0: Not requested 0y1: Requested [Description] a. <PA7RIS to PA0RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not requested 0y1: Requested 7. GPIOAMIS (Port A Interrupt Status Register (Masked)) Address = (0xF080_0000) + (0x0818) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. [7:0] PA7MIS to PA0MIS RO 0x00 Port A masked interrupt status register (for each bit) 0y0: Not requested 0y1: Requested [Description] a. <PA7MIS to PA0MIS> Masked interrupt status register: Monitors the interrupt status after masking. 0y0: Not requested 0y1: Requested 8. GPIOAIC (Port A Interrupt Clear Register) Address = (0xF080_0000) + (0x081C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PA7IC to PA0IC WO 0x00 Port A interrupt clear register (for each bit) 0y0: Invalid 0y1: Clear [Description] a. <PA7IC to PA0IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear TMPA910CRA- 133 2010-06-02 TMPA910CRA 3.9.2.2 Port B Port B can be used not only as general-purpose output pins but also as key output pins. By enabling open-drain output, Port B is used as key output (KO7-KO0). General-Purpose Output Setting Function Data Value General-purpose output Open-Drain Enable GPIOBDATA GPIOBODE * 0/1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output Note: All bits support open-drain mode. Key Output Setting Function Data Value Key output Open-Drain Enable GPIOBDATA GPIOBODE * 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 KO7 KO6 KO5 KO4 KO3 KO2 KO1 KO0 Note: All bits support open-drain mode. Base address = 0xF080_1000 Register Address Name (base+) Description GPIOBDATA 0x03FC Port B Data Register - 0x0400 Reserved - 0x0424 Reserved - 0x0428 Reserved - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved GPIOBODE 0x0C00 Port B Open-drain Output Enable Register TMPA910CRA- 134 2010-06-02 TMPA910CRA 1. GPIOBDATA (Port B Data Register) Address = (0xF080_1000) + (0x03FC) Bit Bit Reset Type Symbol Value Bit mask Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PB[7:0] R/W 0xFF Bm7:0 Port B data register [Description] a. <PB[7:0]> Data register: Stores data. See notes on data registers for bit masking. TMPA910CRA- 135 2010-06-02 TMPA910CRA 2. GPIOBODE (Port B Open-drain Output Enable Register) Address = (0xF080_1000) + (0x0C00) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] PB7ODE to PB0ODE R/W 0x00 Read as undefined. Written as zero. Port B open-drain output enable register (for each bit) 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output [Description] a. <PB7ODE to PB0ODE> Open-drain output enable register: Selects Push-Pull output or open-drain output. 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output TMPA910CRA- 136 2010-06-02 TMPA910CRA 3.9.2.3 Port C The upper 3 bits (bits [7:5]) of Port C can be used as general-purpose input/output pins and the lower 5 bits (bits [4:0]) can be used as general-purpose output pins. Port C can also be used as interrupt (INT9, INT8), I2C (I2C0DA, I2C0CL), low-frequency clock output (FSOUT), melody output (MLDALM, MLDALMn), external power supply control (PWE) pins, PWM output function (PWM0OUT, PWM2OUT), and Key output function (KO8, KO9). General-purpose input and Interrupt settings Input/Output Function Data Value General-purpose input GPIOCDATA Interrupt * Open-Drain Function Select 1 Function Select 2 Interrupt Enable GPIOCDIR GPIOCFR1 GPIOCFR2 GPIOCIE GPIOCODE 0 0 0 0/1 * Select Enable Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input/INT9 Input Input/INT8 - - - - - Note: Only bits 7 and 5 support the interrupt function. General-purpose output setting Function Input/Output Data Value General-purpose output Select Function Select 1 Function Select 2 Interrupt Enable Open-Drain Enable GPIOCDATA GPIOCDIR GPIOCFR1 GPIOCFR2 GPIOCIE GPIOCODE * 1 0 0 0 0/1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output Note: Bits 7 to 0 support open-drain mode. Key Output Setting Function Input/Output Data Value Key output Select Function Select 1 Function Select 2 Interrupt Enable Open-Drain Enable GPIOCDATA GPIOCDIR GPIOCFR1 GPIOCFR2 GPIOCIE GPIOCODE * 1 0 0 0 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - KO9 KO8 Note: Bits 7 to 0 support open-drain mode. I2C setting Function 2 IC Input/Output Data Value Select Function Select 1 Function Select 2 Interrupt Enable Open-Drain Enable GPIOCDATA GPIOCDIR GPIOCFR1 GPIOCFR2 GPIOCIE GPIOCODE * * 1 0 0 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2C0DA I2C0CL - - - - - - TMPA910CRA- 137 2010-06-02 TMPA910CRA MLDALM and PWE settings Function Data Value MLDALM GPIOCDATA PWE * Input/Output Open-Drain Function Select 1 Function Select 2 Interrupt Enable GPIOCDIR GPIOCFR1 GPIOCFR2 GPIOCIE GPIOCODE * 1 0 0 0 Select Enable Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - MLDALMn FSOUT MLDALM PWE - - PWM output setting Function Input/Output Data Value PWM Select Function Select 1 Function Select 2 Interrupt Enable Open-Drain Enable GPIOCDATA GPIOCDIR GPIOCFR1 GPIOCFR2 GPIOCIE GPIOCODE * * 0 1 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - PWM2OUT PWM0OUT - - - TMPA910CRA- 138 2010-06-02 TMPA910CRA Note: This MCU implements power management circuitry that can cut off power supply to circuit blocks other than some special circuits and I/O pins. For details, please refer to PMC chapter). Even if the power of some internal circuits is cut off, the statuses of external IO can be held. Care should be taken when controlling ports. Furthermore, please pay special attention to the PC2 port control due to its particular circuit configuration. The below chart shows an internal circuit connection diagram. TMPA910CRAXBG GPIOCFR1 GPIOCFR2 PMC circuit (Not used) PCDATA Initial value/ PCM state NC NC PWE GPO PC2 Initial value PMCCTL<PMCPWE> PWE (internal signal) * To use PC2 as a general port, please set PMCCTL<PMCPWE> = 0 * In PCM (Power Cut mode) mode, the general Port Function of PC2 can't be used. TMPA910CRA- 139 2010-06-02 TMPA910CRA Base address = 0xF080_2000 Register Address Name (base+) Description GPIOCDATA 0x03FC Port C Data Register GPIOCDIR 0x0400 Port C Data Direction Register GPIOCFR1 0x0424 Port C Function Register 1 GPIOCFR2 0x0428 Port C Function Register 2 GPIOCIS 0x0804 Port C Interrupt Select Register (Level and Edge) GPIOCIBE 0x0808 Port C Interrupt Select Register (Single edge and Both edge) GPIOCIEV 0x080C Port C Interrupt Select Register GPIOCIE 0x0810 Port C Interrupt Enable Register GPIOCRIS 0x0814 Port C Interrupt Status Register (Raw) GPIOCMIS 0x0818 Port C Interrupt Status Register (Masked) GPIOCIC 0x081C Port C Interrupt Clear Register GPIOCODE 0x0C00 Port C Open-drain Output Enable Register (Falling down edge/Low level and Rising edge/High level) 1. GPIOCDATA (Port C Data Register) Address = (0xF080_2000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PC[7:0] R/W 0xEF Bm7:0 Port C data register [Description] a. <PC[7:0]> Data register: Stores data. See notes on data registers for bit masking. 2. GPIOCDIR (Port C Data Direction Register) Address = (0xF080_2000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:5] PC7C to PC5C R/W 0y000 Port C data direction register (for each bit) 0y0: Input 0y1: Output [4:0] PC4C to PC0C - 0y11111 Must be written as 1. Read as 1. [Description] a. <PC7C to PC5C> Data direction register: Selects input or output when Port C is used as a general-purpose port. 0y0: Input 0y1: Output TMPA910CRA- 140 2010-06-02 TMPA910CRA 3. GPIOCFR1 (Port C Function Register 1) Address = (0xF080_2000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:2] PC7F1 to PC2F1 R/W 0y000000 Port C function register 1 [1:0] Reserved R/W 0y00 Must be written as 0. Read as 0. [Description] a. <PC7F1 to PC2F1> Function register 1: Controls the function setting. 4. GPIOCFR2 (Port C Function Register 2) Address = (0xF080_2000) + (0x0428) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:5] Reserved R/W 0y000 Read as undefined. Written as zero. Must be written as 0. Read as 0. [4:3] PC4F2 to PC3F2 R/W 0y00 Port C function register 2 [2:0] Reserved R/W 0y000 Must be written as 0. Read as 0. [Description] a. <PC4F2 to PC3F2> Function register 2: Controls the function setting. Note: 1 can be set to only one of the function register 1 or the function register 2 at a time. These registers must not be written as 1 simultaneously even for an instant. Table 3.9.4 Function register setting table Mode GPIOCFR1 GPIOCFR2 General-purpose 0 0 Function 1 1 0 Function 2 0 1 Prohibited 1 1 TMPA910CRA- 141 2010-06-02 TMPA910CRA 5. GPIOCIS (Port C Interrupt Select Register (Level and Edge)) Address = (0xF080_2000) + (0x0804) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined [7] PC7IS R/W 0y0 Read as undefined. Written as zero. Port C interrupt sensitivity register 0y0: Edge-sensitive 0y1: Level-sensitive [6] - - Undefined Read as undefined. Written as zero. [5] PC5IS R/W 0y0 Port C interrupt sensitivity register 0y0: Edge-sensitive 0y1: Level-sensitive - [4:0] - Undefined Read as undefined. Written as zero. [Description] a. <PC7IS, PC5IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIOCIBE (Port C Interrupt Select Register (Single edge and Both edge)) Address = (0xF080_2000) + (0x0808) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7] PC7IBE R/W 0y0 Port C interrupt both-edge register 0y0: Single edge 0y1: Both-edge [6] - - Undefined Read as undefined. Written as zero. [5] PC5IBE R/W 0y0 Port C interrupt both-edge register 0y0: Single edge 0y1: Both-edge [4:0] - - Undefined Read as undefined. Written as zero. [Description] a. <PC7IBE, PC5IBE> Interrupt both-edge register: Selects the trigger mode from single edge and both-edge. 0y0: Single edge 0y1: Both-edge TMPA910CRA- 142 2010-06-02 TMPA910CRA 7. GPIOCIEV (Port C Interrupt Select Register ("Falling edge/Low level" and "Rising edge/High level")) Address = (0xF080_2000) + (0x080C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7] PC7IEV R/W 0y0 Port C interrupt event register 0y0: Falling edge/Low level 0y1: Rising edge/High level [6] - - Undefined Read as undefined. Written as zero. [5] PC5IEV R/W 0y0 Port C interrupt event register 0y0: Falling edge/Low level 0y1: Rising edge/High level - [4:0] - Undefined Read as undefined. Written as zero. [Description] a. <PC7IEV, PC5IEV> Interrupt event register: Select falling edge or rising edge for edge-sensitive interrupts, and Low level or High level for level-sensitive interrupts. 0y0: Falling edge/Low level 0y1: Rising edge/High level 8. GPIOCIE (Port C Interrupt Enable Register) Address = (0xF080_2000) + (0x0810) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7] PC7IE R/W 0y0 Port C interrupt enable register 0y0: Disabled 0y1: Enabled [6] Reserved R/W 0y0 Must be written as 0. Read as 0. [5] PC5IE R/W 0y0 Port C interrupt enable register 0y0: Disabled 0y1: Enabled [4:0] Reserved R/W 0y0000 Must be written as 0. Read as0. [Description] a. <PC7IE, PC5IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disabled 0y1: Enabled TMPA910CRA- 143 2010-06-02 TMPA910CRA 9. GPIOCRIS (Port C Interrupt Status Register (Raw)) Address = (0xF080_2000) + (0x0814) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined [7] PC7RIS RO 0y0 Read as undefined. Port C interrupt raw status register 0y0: Not requested 0y1: Requested [6] - - Undefined Read as undefined. [5] PC5RIS RO 0y0 Port C interrupt raw status register 0y0: Not requested 0y1: Requested - [4:0] - Undefined Read as undefined. [Description] a. <PC7RIS, PC5RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not requested 0y1: Requested 10. GPIOCMIS (Port C Interrupt Status Register (Masked)) Address = (0xF080_2000) + (0x0818) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. [7] PC7MIS RO 0y0 Port C masked interrupt status register 0y0: Not requested 0y1: Requested [6] - - Undefined Read as undefined. [5] PC5MIS RO 0y0 Port C masked interrupt status register 0y0: Not requested 0y1: Requested [4:0] - - Undefined Read as undefined. [Description] a. <PC7MIS, PC5MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt enable. 0y0: Not requested 0y1: Requested TMPA910CRA- 144 2010-06-02 TMPA910CRA Following table is an example configurations of interrupt register. The configurations of each register and bit are shown below. Table 3.9.5 An example configurations of interrupt register (GPOnIS, GPIOnIBE, GPIOnIEV, GPIOnIE, GPIOnRIS, GPIOnMIS: x = A, C, D, F, N, P, R) 0 1 0 0 1 0 1 1 0 1 0 1 0 0 Rising edge detection Detection enabled Both edge detection 0 0 1 Rising edge detection disabled (0x00) INTS [Num] Detection disabled Detection Detection Detection enabled enabled enabled Both edge detection 0 Low level detection 1 High level detection Detection Low level detection enabled 0 1 High level detection 0 Low level detection 1 Detection Falling edge detection 1 0 GPIOxMIS ( Port x Interrupt Status Register (Masked)) Falling edge detection 1 1 Trigger Mode GPIOxRIS ( Port x Interrupt Status Register (Raw)) Output GPIOxIE ( Port x Interrupt Enable Register ) GPIOxIEV (Port x Interrupt Select Register (Falling down edge/Low level and Rising edge/High level)) GPIOxIS (Port x Interrupt Select Register (Level and Edge)) GPIOxIBE (Port x Interrupt Select Register (Single edge and Both edge) Register setting Detection disabled (0x00) Detection disabled High level detection Detection Detection Detection 0 Low level detection enabled enabled enabled 1 High level detection 1 TMPA910CRA- 145 2010-06-02 TMPA910CRA 11. GPIOCIC (Port C Interrupt Clear Register) Address = (0xF080_2000) + (0x081C) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7] PC7IC WO 0y0 Port C interrupt clear register 0y0: Invalid 0y1: Request cleared [6] - - Undefined Read as undefined. Written as zero. [5] PC5IC WO 0y0 Port C interrupt clear register 0y0: Invalid 0y1: Request cleared - [4:0] - Undefined Read as undefined. Written as zero. [Description] a. <PC7IC, PC5IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared 12. GPIOCODE (Port C Open-drain Output Enable Register) Address = (0xF080_2000) + (0x0C00) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] PC7ODE to PC0ODE R/W 0x00 Read as undefined. Written as zero. Port C open-drain output enable register (for each bit) 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output [Description] a. <PC7ODE to PC0ODE> Open-drain output enable register: Selects the output mode from Push-Pull output and Open-drain output. 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output TMPA910CRA- 146 2010-06-02 TMPA910CRA 3.9.2.4 Port D Port D can be used as general-purpose input Port D can also be used as interrupt (INTB, INTA), ADC (AN5-AN0), and touch screen control (PX, PY, MX, MY) pins. General-purpose input and Interrupt settings Function Data Value Function Select 1 Function Select 2 Interrupt Enable General-purpose input GPIODDATA GPIODFR1 GPIODFR2 GPIODIE Interrupt * 0 0 0/1 Bit 7 Input/INTB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input/INTA Input Input Input Input Input Input Note: Only bits 7 and 6 support the interrupt function. ADC settings Function ADC Data Value Function Select 1 Function Select 2 Interrupt Enable GPIODDATA GPIODFR1 GPIODFR2 GPIODIE * 1 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - AN5 AN4 AN3 AN2 AN1 AN0 TSI settings Function TSI Data Value Function Select 1 Function Select 2 Interrupt Enable GPIODDATA GPIODFR1 GPIODFR2 GPIODIE * 0 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PY PX/INTTSI MY MX - - - - TMPA910CRA- 147 2010-06-02 TMPA910CRA Base address = 0xF080_3000 Register Address Name (base+) Description GPIODDATA 0x03FC - 0x0400 Port D Data Register Reserved GPIODFR1 0x0424 Port D Function Register1 GPIODFR2 0x0428 Port D Function Register2 GPIODIS 0x0804 Port D Interrupt Select Register (Level and Edge) GPIODIBE 0x0808 Port D Interrupt Select Register (Single edge and Both edge) GPIODIEV 0x080C Port D Interrupt Select Register (Falling edge/Low level and Rising edge/High level) GPIODIE 0x0810 Port D Interrupt Enable Register GPIODRIS 0x0814 Port D Interrupt Status Register (Raw) GPIODMIS 0x0818 Port D Interrupt Status Register (Masked) GPIODIC 0x081C Port D Interrupt Clear Register - 0x0C00 Reserved 1. GPIODDATA (Port D Data Register) Address = (0xF080_3000) + (0x03FC) Bit Bit Reset Type Symbol Value Bit mask Description [31:8] - - Undefined - Read as undefined. [7:0] PD[7:0] RO 0xFF Bm7:0 Port D data register [Description] a. <PD[7:0]> Data register: Stores data. See notes on data registers for bit masking. TMPA910CRA- 148 2010-06-02 TMPA910CRA 2. GPIODFR1 (Port D Function Register 1) Address = (0xF080_3000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:6] Reserved R/W 0y00 Read as undefined. Written as zero. Must be written as 0. Read as 0. [5:0] PD5F1 to PD0F1 R/W 0y111111 Port D function register 1 [Description] a. <PD5F1 to PD0F1> Function register 1: Controls the function setting. 3. GPIODFR2 (Port D Function Register 2) Address = (0xF080_3000) + (0x0428) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:4] PD7F2 to PD4F2 R/W 0y0000 Port D function register 2 [3:0] Reserved R/W 0y0000 Must be written as 0. Read as 0. [Description] a. <PD7F2 to PD4F2> Function register 2: Controls the function setting. Note: 1 can be set to only one of the function register 1 or the function register 2 at a time. These registers must not be written as 1 simultaneously even for an instant. Table 3.9.6 Function register setting table Mode GPIODFR1 GPIODFR2 General-purpose 0 0 Function 1 1 0 Function 2 0 1 Prohibited 1 1 TMPA910CRA- 149 2010-06-02 TMPA910CRA 4. GPIODIS (Port D Interrupt Select Register (Level and Edge)) Address = (0xF080_3000) + (0x0804) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:6] PD7IS to PD6IS R/W 0y00 Read as undefined. Written as zero. Port D interrupt sensitivity register (for each bit) 0y0: Edge-sensitive 0y1: Level-sensitive [5:0] Reserved R/W 0y000000 Must be written as 0. Read as 0. [Description] a. <PD7IS to PD6IS> Interrupt sensitivity register: Selects the interrupt trigger mode from edge-sensitive and level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 5. GPIODIBE (Port D Interrupt Select Register (Single edge and Both-edge)) Address = (0xF080_3000) + (0x0808) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:6] PD7IBE to D6IBE R/W 0y00 Port D interrupt both-edge register (for each bit) 0y0: Single edge 0y1: Both-edge [5:0] Reserved R/W 0y000000 Must be written as 0. Read as0. [Description] a. <PD7IBE to PD6IBE> Interrupt both-edge register: Selects the trigger edge from single edge or both-edge. 0y0: Single edge 0y1: Both-edge TMPA910CRA- 150 2010-06-02 TMPA910CRA 6. GPIODIEV (Port D Interrupt Select Register ("Falling edge/Low level" and "Rising edge/High level")) Address = (0xF080_3000) + (0x080C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:6] PD7IEV to PD6IEV R/W 0y00 Port D interrupt event register (for each bit) 0y0: Falling edge/Low level 0y1: Rising edge/High level [5:0] Reserved R/W 0y000000 Must be written as 0. Read as 0. [Description] a. <PD7IEV to PD6IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and Low level or High level for level-sensitive interrupts. 0y0: Falling edge/Low level 0y1: Rising edge/High level 7. GPIODIE (Port D Interrupt Enable Register) Address = (0xF080_3000) + (0x0810) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:6] PD7IE to PD6IE R/W 0y00 Read as undefined. Written as zero. Port D interrupt enable register (for each bit) 0y0: Disable 0y1: Enable [5:0] Reserved R/W 0y000000 Must be written as 0. Read as 0. [Description] a. <PD7IE to PD6IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disable 0y1: Enable TMPA910CRA- 151 2010-06-02 TMPA910CRA 8. GPIODRIS (Port D Interrupt Status Register (Raw)) Address = (0xF080_3000) + (0x0814) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:6] PD7RIS to PD6RIS RO 0y00 Read as undefined. Port D interrupt raw status register (for each bit) 0y0: Not requested 0y1: Requested - [5:0] - Undefined Read as undefined. [Description] a. <PD7RIS to PD6RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not requested 0y1: Requested 9. GPIODMIS (Port D Interrupt Status Register (Masked)) Address = (0xF080_3000) + (0x0818) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read undefined. [7:6] PD7MIS to PD6MIS RO 0y00 Port D masked interrupt status register (for each bit) 0y0: Not requested 0y1: Requested [5:0] - - Undefined Read undefined. [Description] a. <PD7MIS to PD6MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt enable register. 0y0: Not requested 0y1: Requested Note: Refer to Table 3.9.5 for the configurations of each external interrupt register. TMPA910CRA- 152 2010-06-02 TMPA910CRA 10. GPIODIC (Port D Interrupt Clear Register) Address = (0xF080_3000) + (0x081C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:6] PD7IC to PD6IC WO 0y00 Port D interrupt clear register (for each bit) 0y0: Invalid 0y1: Request cleared [5:0] - - Undefined Read as undefined. Written as zero. [Description] a. <PD7IC to PD6IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared TMPA910CRA- 153 2010-06-02 TMPA910CRA 3.9.2.5 Port E Port E can be used as general-purpose input. Port E can also be used as data input pins for the CMOS image sensor (CMSD7-CMSD0). General-purpose input setting Function General-purpose input Data Value Function Select 1 GPIOEDATA GPIOEFR1 * 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Input Input Input Input Input Input Input CMOS-IS setting Function CMOS-IS Data Value Function Select 1 GPIOEDATA GPIOEFR1 * 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMSD7 CMSD6 CMSD5 CMSD4 CMSD3 CMSD2 CMSD1 CMSD0 Base address = 0xF080_4000 Register Address Name (base+) Description GPIOEDATA 0x03FC Port E Data Register - 0x0400 Reserved - 0x0424 Reserved - 0x0428 Reserved - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved GPIOEFR1 0x0424 Port E Function Register1 TMPA910CRA- 154 2010-06-02 TMPA910CRA 1. GPIOEDATA (Port E Data Register) Address = (0xF080_4000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. [7:0] PE[7:0] RO 0xFF Bm7:0 Port E data register [Description] a. <PE[7:0]> Data register: Stores data. See notes on data registers for bit masking. 2. GPIOEFR1 (Port E Function Register 1) Address = (0xF080_4000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PE7F1 to PE0F1 R/W 0x00 Port E function register 1 [Description] a. <PE7F1 to PE0F1> Function register 1: Controls the function setting. TMPA910CRA- 155 2010-06-02 TMPA910CRA 3.9.2.6 Port F The upper 2 bits (bits [7:6]) of Port F can be used as general-purpose input/output pins and the lower 4 bits (bits [3:0]) can be used as general-purpose input pins. (Bits [5:4] are not used.) Port F can also be used as interrupt (INTC), I2C (I2C1DA, I2C1CL), and CMOS image sensor control (CMSVSY, CMSHBK, CMSHSY, CMSPCK) pins. General-purpose Input and Interrupt settings Input/Output Function Data Value General-purpose Input GPIOFDATA GPIOFDIR Interrupt * 0 Bit 7 Bit 6 Input/INTC Bit 5 Interrupt Open-Drain Enable Enable GPIOFFR1 GPIOFIE GPIOFODE 0 0/1 * Function Select Select Bit 4 Input Bit 3 Bit 2 Bit 1 Bit 0 Input Input Input Input Note: Only Bit 7 supports the interrupt function. General-purpose Output setting Function Input/Output Data Value General-purpose output Select Function Select 1 Interrupt Open-Drain Enable Enable GPIOFDATA GPIOFDIR GPIOFFR1 GPIOFIE GPIOFODE * 1 0 0 0/1 Bit 7 Bit 6 Bit 5 Output Output Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - Note 3: Only bits 7 and 6 support open-drain mode. I2C and CMOS-IS settings Function 2 Input/Output Data Value Select Function Select 1 Interrupt Open-Drain Enable Enable IC GPIOFDATA GPIOFDIR GPIOFFR1 GPIOFIE GPIOFODE CMOS-IS * * 1 0 0/1 Bit 7 Bit 6 I2C1DA I2C1CL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMSVSY CMSHBK CMSHSY CMSPCK TMPA910CRA- 156 2010-06-02 TMPA910CRA Base address = 0xF080_5000 Register Address Name (base+) Description GPIOFDATA 0x03FC Port F Data Register GPIOFDIR 0x0400 Port F Data Direction Register GPIOFFR1 0x0424 Port F Function Register 1 - 0x0428 Reserved GPIOFIS 0x0804 Port F Interrupt Select Register (Level and Edge) GPIOFIBE 0x0808 Port F Interrupt Select Register (Single edge and Both-edge) GPIOFIEV 0x080C Port F Interrupt Select Register GPIOFIE 0x0810 Port F Interrupt Enable Register GPIOFRIS 0x0814 Port F Interrupt Status Register (Raw) GPIOFMIS 0x0818 Port F Interrupt Status Register (Masked) (Falling edge/Low level and Rising edge/High level) GPIOFIC 0x081C Port F Interrupt Clear Register GPIOFODE 0x0C00 Port F Open-drain Output Enable Register 1. GPIOFDATA (Port F Data Register) Address = (0xF080_5000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:6] PF[7:6] R/W 0y11 Bm7:6 Port F data register [5:4] - - Undefined - Read as undefined. Written as zero. [3:0] PF[3:0] RO 0y1111 Bm3:0 Port F data register [Description] a. <PF[7:6], [3:0]> Data register: Stores data. See notes on data registers for bit masking. 2. GPIOFDIR (Port F Data Direction Register) Address = (0xF080_5000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:6] PF7C to PF6C R/W 0y00 Read as undefined. Written as zero. Port F data direction register (for each bit) 0y0: Input 0y1: Output [5:0] - - Undefined Read as undefined. Write as zero [Description] a. <PF7C to PF6C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output TMPA910CRA- 157 2010-06-02 TMPA910CRA 3. GPIOFFR1 (Port F Function Register 1) Address = (0xF080_5000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:6] PF7F1 to PF6F1 R/W 0y00 Port F function register 1 [5:4] - - Undefined Read as undefined. Write as zero [3:0] PF3F1 to PF0F1 R/W 0y0000 Port F function register 1 [Description] a. <PF7F1:PF6F1, PF7F3:PF0F1> Function register 1: Controls the function setting. 4. GPIOFIS (Port F Interrupt Select Register (Level and Edge)) Address = (0xF080_5000) + (0x0804) Bit Bit Reset Type Symbol Value [31:8] - - Undefined [7] PF7IS R/W 0y0 Description Read as undefined. Written as zero. Port F interrupt sensitivity register 0y0: Edge-sensitive 0y1: Level-sensitive [6:0] - - Undefined Read as undefined. Written as zero. [Description] a. <PF7IS> Interrupt sensitivity register: Selects the interrupt mode from edge-sensitive and level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive TMPA910CRA- 158 2010-06-02 TMPA910CRA 5. GPIOFIBE (Port F Interrupt Select Register (Single edge and Both edge)) Address = (0xF080_5000) + (0x0808) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7] PF7IBE R/W 0y0 Port F interrupt both-edge register 0y0: Single edge 0y1: Both-edge - [6:0] - Undefined Read as undefined. Written as zero. [Description] a. <PFF7IBE> Interrupt both-edge register: Selects the trigger edge from single edge and both-edge. 0y0: Single edge 0y1: Both-edge 6. GPIOFIEV (Port F Interrupt Select Register ("Falling edge/Low level" and "Rising edge/High level")) Address = (0xF080_5000) + (0x080C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7] PF7IEV R/W 0y0 Port F interrupt event register 0y0: Falling edge/Low level 0y1: Rising edge/High level [6:0] Reserved - 0y0000000 Must be written as 0. Read as 0. [Description] a. <PF7IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and Low level or High level for level-sensitive interrupts. 0y0: Falling edge/Low level 0y1: Rising edge/High level TMPA910CRA- 159 2010-06-02 TMPA910CRA 7. GPIOFIE (Port F Interrupt Enable Register) Address = (0xF080_5000) + (0x0810) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined [7] PF7IE R/W 0y0 Read as undefined. Written as zero. Port F interrupt enable register 0y0: Disabled 0y1: Enabled [6:0] Reserved R/W 0y0000000 Must be written as 0. Read as 0. [Description] a. <PF7IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disabled 0y1: Enabled 8. GPIOFRIS (Port F Interrupt Status Register (Raw)) Address = (0xF080_5000) + (0x0814) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. [7] PF7RIS RO 0y0 Port F interrupt raw status register 0y0: Not requested 0y1: Requested [6:0] - - Undefined Read undefined. [Description] a. <PF7RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not requested 0y1: Requested TMPA910CRA- 160 2010-06-02 TMPA910CRA 9. GPIOFMIS (Port F Interrupt Status Register (Masked)) Address = (0xF080_5000) + (0x0818) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined [7] PF7MIS RO 0y0 Read as undefined. Port F masked interrupt status register 0y0: Not requested 0y1: Requested - [6:0] - Undefined Read undefined. [Description] a. <PF7MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt register. 0y0: Not requested 0y1: Requested Note: Refer to Table 3.9.5 for the configurations of each external interrupt register. 10. GPIOFIC (Port F Interrupt Clear Register) Address = (0xF080_5000) + (0x081C) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7] PF7IC WO 0y0 Port F interrupt clear register 0y0: Invalid 0y1: Request cleared [6:0] - - Undefined Read as undefined. Written as zero. [Description] a. <PF7IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared TMPA910CRA- 161 2010-06-02 TMPA910CRA 11. GPIOFODE (Port F Open-drain Output Enable Register) Address = (0xF080_5000) + (0x0C00) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:6] PF7ODE to PF6ODE R/W 0y00 Port F open-drain output enable register (for each bit) 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output [5:4] - - Undefined Read as undefined. Written as zero. [3:0] PF3ODE to PF0ODE R/W 0y0000 Port F open-drain output enable register (for each bit) 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output [Description] a. <PF7ODE to PF6ODE, PF3ODE to PF0ODE > Open-drain output enable register: Selects the output mode from Push-Pull output and Open-drain output. 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output TMPA910CRA- 162 2010-06-02 TMPA910CRA 3.9.2.7 Port G Port G can be used as general-purpose input/output pins. Port G can also be used as SD host controller function pins (SDC0CLK, SDC0CD, SDC0WP, SDC0CMD, SDC0DAT3, SDC0DAT2, SDC0DAT1 and SDC0DAT0). General-purpose input setting Function Input/Output Data Value General-purpuse input Function Select 1 Select GPIOGDATA GPIOGDIR GPIOGFR1 * 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Input Input Input Input Input Input Input General-purpuse output settings Function Input/Output Data Value General-purpose output Function Select 1 Select GPIOGDATA GPIOGDIR GPIOGFR1 * 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output SDFHC (ch0) setting Function SDHC(ch0) Input/Output Data Value Select Function Select 1 GPIOGDATA GPIOGDIR GPIOGFR1 * * 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SDC0CLK SDC0CD SDC0WP SDC0CMD SDC0DAT3 SDC0DAT2 SDC0DAT1 SDC0DAT0 Base address = 0xF080_6000 Register Address Name (base+) Description GPIOGDATA 0x03FC GPIOGDIR 0x0400 Port G Data Register Port G Data Direction Register GPIOGFR1 0x0424 Port G Function Register1 - 0x0428 Reserved - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved - 0x0C00 Reserved TMPA910CRA- 163 2010-06-02 TMPA910CRA 1. GPIOGDATA (Port G Data Register) Address = (0xF080_6000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PG[7:0] R/W 0xFF Bm7:0 Port G data register [Description] a. <PG[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOGDIR (Port G Data Direction Register) Address = (0xF080_6000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] PG7C to PG0C R/W 0x00 Read as undefined. Written as zero. Port G data direction register (for each bit) 0y0: Input 0y1: Output [Description] a. <PG7C to PG0C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output 3. GPIOGFR1(Port G Function Register 1) Address = (0xF080_6000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PG7F1 to PG0F1 R/W 0x00 Port G function register 1 [Description] a. <PG7F1 to PG0F1> Function register 1: Controls the function setting. TMPA910CRA- 164 2010-06-02 TMPA910CRA 3.9.2.8 Port H Port H can be used as general-purpose input/output pins. Port H can also be used as SD host controller function pins (SDC1CLK, SDC1CD, SDC1WP, SDC1CMD, SDC1DAT3, SDC1DAT2, SDC1DAT1 and SDC1DAT0). General-purpose input setting Function Input/Output Data Value General-purpose input Function Select 1 Select GPIOHDATA GPIOHDIR GPIOHFR1 * 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Input Input Input Input Input Input Input General-purpose output setting Function Input/Output Data Value General-purpose output Function Select 1 Select GPIOHDATA GPIOHDIR GPIOHFR1 * 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output SDHC(ch1) setting Function SDHC(ch1) Input/Output Data Value Select Function Select 1 GPIOHDATA GPIOHDIR GPIOHFR1 * * 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SDC1CLK SDC1CD SDC1WP SDC1CMD SDC1DAT3 SDC1DAT2 SDC1DAT1 SDC1DAT0 Base address = 0xF080_7000 Register Address Name (base+) Description GPIOHDATA 0x03FC Port H Data Register GPIOHDIR 0x0400 Port H Data Direction Register GPIOHFR1 0x0424 Port H Function Register1 - 0x0428 Reserved - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved - 0x0C00 Reserved TMPA910CRA- 165 2010-06-02 TMPA910CRA 1. GPIOHDATA (Port H Data Register) Address = (0xF080_7000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PH[7:0] RW 0xFF Bm7:0 Port H data register [Description] a. <PH[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOHDIR (Port H Data Direction Register) Address = (0xF080_7000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] PH7C to PH0C R/W 0x00 Read as undefined. Written as zero. Port H data direction register (for each bit) 0y0: Input 0y1: Output [Description] a. <PH7C to PH0C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output 3. GPIOHFR1 (Port H Function Register 1) Address = (0xF080_7000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PH7F1 to PH0F1 R/W 0x00 Port H function register 1 [Description] a. <PH7F1 to PH0F1> Function register 1: Controls the function setting. TMPA910CRA- 166 2010-06-02 TMPA910CRA 3.9.2.9 Port J Port J can be used as general-purpose output pins. Port J can also be used as LCD controller function pins (LD15-LD8). General-purpose output setting Function General-purpose output Data Value Function Select 1 GPIOJDATA GPIOJFR1 * 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output LCDC setting Function LCDC Data Value Function Select 1 GPIOJDATA GPIOJFR1 * 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 Base address = 0xF080_8000 Register Address Name (base+) Description GPIOJDATA 0x03FC Port J Data Register - 0x0400 Reserved GPIOJFR1 0x0424 Port J Function Register1 - 0x0428 Reserved - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved - 0x0C00 Reserved TMPA910CRA- 167 2010-06-02 TMPA910CRA 1. GPIOJDATA (Port J Data Register) Address = (0xF080_8000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PJ[7:0] R/W 0x00 Bm7:0 Port J data register [Description] a. <PJ[7:0]> Data Register: Stores data. See notes on data registers for the bit mask function. 2. GPIOJFR1 (Port J Function Register 1) Address = (0xF080_8000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PJ7F1 to PJ0F1 R/W 0x00 Port J function register 1 [Description] a. <PJ7F1 to PJ0F1> Function register 1: Controls the function setting. TMPA910CRA- 168 2010-06-02 TMPA910CRA 3.9.2.10 Port K Port K can be used as general-purpose output pins. Port K can also be used as LCD controller function pins (LD23-LD16). General-purpose output settings Function General-purpose output Data Value Function Select 1 GPIOKDATA GPIOKFR1 * 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output LCDC setting Function LCDC Data Value Function Select 1 GPIOKDATA GPIOKFR1 * 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LD23 LD22 LD21 LD20 LD19 LD18 LD17 LD16 Base address = 0xF080_9000 Register Address Name (base+) GPIOKDATA Description 0x03FC Port K Data Register 0x0400 Reserved GPIOKFR1 0x0424 Port K Function Register1 - 0x0428 Reserved - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved - 0x0C00 Reserved - TMPA910CRA- 169 2010-06-02 TMPA910CRA 1. GPIOKDATA (Port K Data Regsiter) Address = (0xF080_9000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PK[7:0] R/W 0x00 Bm7:0 Port K data register [Description] a. <PK[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOKFR1 (Port K Function Register 1) Address = (0xF080_9000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PK7F1 to PK0F1 R/W 0x00 Port K function register 1 [Description] a. <PK7F1 to PK0F1> Function register 1: Controls the function setting. TMPA910CRA- 170 2010-06-02 TMPA910CRA 3.9.2.11 Port L Port L can be used as general-purpose input/output pins. (Bits [7:5] are not used.) In addition, Port L can also be used as I2S function (I2SSCLK, I2S0MCLK, I2S0DATI, I2S0CLK and I2S0WS) and SPI function (SP1DI, SP1DO, SP1CLK and SP1FSS) pins. General-purpose input setting Function Data Value General-purpose input Bit 7 Input/Output Select Function Select 1 Function Select 2 GPIOLDATA GPIOLDIR GPIOLFR1 GPIOLFR2 * 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Input Input Input Input General-purpose output setting Function Data Value General-purpose output Bit 7 Input/Output Select Function Select 1 Function Select 2 GPIOLDATA GPIOLDIR GPIOLFR1 GPIOLFR2 * 1 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output I2S (ch0) setting Function Input/Output Data Value I2S(ch0) Bit 7 Select Function Select 1 Function Select 2 GPIOLDATA GPIOLDIR GPIOLFR1 GPIOLFR2 * * 1 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2SSCLK I2S0MCLK I2S0DATI I2S0CLK I2S0WS SPI (ch1) setting Function SPI(ch1) Bit 7 Input/Output Data Value Select Function Select 1 Function Select 2 GPIOLDATA GPIOLDIR GPIOLFR1 GPIOLFR2 * * 0 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - SP1DI SP1DO SP1CLK SP1FSS TMPA910CRA- 171 2010-06-02 TMPA910CRA Base address = 0xF080_A000 Register Address Name (base+) Description GPIOLDATA 0x03FC Port L Data Register GPIOLDIR 0x0400 Port L Data Direction Register GPIOLFR1 0x0424 Port L Function Register1 GPIOLFR2 0x0428 Port L Function Register2 - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved - 0x0C00 Reserved 1. GPIOLDATA (Port L Data Register) Address = (0xF080_A000) + (0x3FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:5] - - Undefined - Read as undefined. Written as zero. [4:0] PL[4:0] R/W 0y11111 Bm4:0 Port L data register [Description] a. <PL[4:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOLDIR (Port L Data Direction Register) Address = (0xF080_A000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:5] - - Undefined Read as undefined. Written as zero. [4:0] PL4C to PL0C R/W 0y00000 Port L data direction register (for each bit) 0y0: Input 0y1: Output [Description] a. <PL4C to PL0C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output TMPA910CRA- 172 2010-06-02 TMPA910CRA 3. GPIOLFR1 (Port L Function Register 1) Address = (0xF080_A000) + (0x0424) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:5] - - Undefined Read as undefined. Written as zero. [4:0] PL4F1 to PL0F1 R/W 0y00000 Port L function register 1 [Description] a. <PL4F1 to PL0F1> Function register 1: Controls the function setting. 4. GPIOLFR2 (Port L Function Register 2) Address = (0xF080_A000) + (0x0428) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:5] - - Undefined Read as undefined. Written as zero. [4] Reserved - 0y0 Must be written as 0. Read as 0. [3:0] PL3F2 to PL0F2 R/W 0y0000 Port L function register 2 [Description] a. <PL3F2 to PL0F2> Function register 2: Controls the function setting. Note: The function register 1 and function register 2 can only be set exclusively of each other. These registers must not simultaneously be written as 1 even for an instant. Table 3.9.7 Function register setting table Mode GPIOLFR1 GPIOLFR2 General-purpose 0 0 Function 1 1 0 Function 2 0 1 Prohibited 1 1 TMPA910CRA- 173 2010-06-02 TMPA910CRA 3.9.2.12 Port M Port M can be used as general-purpose input/output pins. (Bits [7:4] are not used.) Port M can also be used as I2S function pins (I2S1MCLK, I2S1DATO, I2S1CLK and I2S1WS). General-purpose input setting Function General-purpose input Bit 7 Data Value Input/Output Select Function Select 1 GPIOMDATA GPIOMDIR GPIOMFR1 * 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Input Input Input Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Bit 3 Bit 2 Bit 1 Bit 0 I2S1MCLK I2S1DATO I2S1CLK I2S1WS Function-specific settings 2 Function General-purpose output Bit 7 Data Value Input/Output Select Function Select 1 GPIOMDATA GPIOMDIR GPIOMFR1 * 1 0 Bit 6 Bit 5 Bit 4 I2S (ch1) setting Function I2S(ch1) Bit 7 Input/Output Data Value Select Function Select 1 GPIOMDATA GPIOMDIR GPIOMFR1 * * 1 Bit 6 Bit 5 Bit 4 Base address = 0xF080_B000 Register Address Name (base+) Description GPIOMDATA 0x03FC Port M Data Register GPIOMDIR 0x0400 Port M Data Direction Register GPIOMFR1 0x0424 Port M Function Register1 - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved - 0x0C00 Reserved TMPA910CRA- 174 2010-06-02 TMPA910CRA 1. GPIOMDATA (Port M Data Register) Address = (0xF080_B000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:4] - - Undefined - Read as undefined. Written as zero. [3:0] PM[3:0] R/W 0y1111 Bm3:0 Port M data register [Description] a. <PM[3:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOMDIR (Port M Data Direction Register) Address = (0xF080_B000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:4] - - Undefined Read as undefined. Written as zero. [3:0] PM3C to PM0C R/W 0y0000 Port M data direction register (for each bit) 0y0: Input 0y1: Output [Description] a. <PM3C to PM0C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output 3. GPIOMFR1 (Port M Function Register 1) Address = (0xF080_B000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:4] - - Undefined Read as undefined. Written as zero. [3:0] PM3F1 to PM0F1 R/W 0y0000 Port M function register 1 [Description] a. <PM3F1 to PM0F1> Function register 1: Controls the function setting. TMPA910CRA- 175 2010-06-02 TMPA910CRA 3.9.2.13 Port N Port N can be used as general-purpose input/output pins. Port N can also be used as UART function (U0RTSn, U0DTRn, U0RIn, U0DSRn, U0DCDn, U0CTSn, U0RXD, U0TXD, SIR0IN, SIR0OUT) and interrupt function (INTD, INTE, INTF, INTG) pins. General-purpose input and interrupt configurations Function Data Value General-purpose input GPIONDATA Interrupt * Input/Output Function Select 1 Function Select 2 Interrupt Enable GPIONDIR GPIONFR1 GPIONFR2 GPIONIE 0 0 0 0/1 Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input/INTG Input/INTF Input/INTE Input/INTD Input Input Input Input Note: Only bits 7 to 4 support the interrupt function. General-purpose output setting Function Input/Output Data Value General-purpose output Select Function Select 1 Function Select 2 Interrupt Enable GPIONDATA GPIONDIR GPIONFR1 GPIONFR2 GPIONIE * 1 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output UART (ch0) setting Function Input/Output Data Value UART(ch0) Select Function Select 1 Function Select 2 Interrupt Enable GPIONDATA GPIONDIR GPIONFR1 GPIONFR2 GPIONIE * * 1 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 U0RTSn U0DTRn U0RIn U0DSRn U0DCDn U0CTSn - U0TXD UART (ch0/IrDA) setting Function Data Value UART GPIONDATA (ch0/IrDA) * Input/Output Function Select 1 Function Select 2 Interrupt Enable GPIONDIR GPIONFR1 GPIONFR2 GPIONIE * 0 1 0 Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - - - - - - U0RXD/ TMPA910CRA- 176 SIR0IN Bit 0 SIR0OUT 2010-06-02 TMPA910CRA Base address = 0xF080_C000 Register Address Name (base+) Description GPIONDATA 0x03FC Port N Data Register GPIONDIR 0x0400 Port N Data Direction Register GPIONFR1 0x0424 Port N Function Register1 GPIONFR2 0x0428 Port N Function Register2 GPIONIS 0x0804 Port N Interrupt Selecti Register (Level and Edge) GPIONIBE 0x0808 Port N Interrupt Select Register (Single edge and Both edge) GPIONIEV 0x080C Port N Interrupt Select Register (Falling edge/Low level and Rising edge/High level) GPIONIE 0x0810 Port N Interrupt Enable Register GPIONRIS 0x0814 Port N Interrupt Status Register (Raw) GPIONMIS 0x0818 Port N Interrupt Status Register (Masked) GPIONIC 0x081C Port N Interrupt Clear Register - 0x0C00 Reserved 1. GPIONDATA (Port N Data Register) Address = (0xF080_C000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PN[7:0] R/W 0xFF Bm7:0 Port N data register [Description] a. <PN[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIONDIR (Port N Data Direction Register) Address = (0xF080_C000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PN7C to PN0C R/W 0x00 Port N data direction register (for each bit) 0y0: Input 0y1: Output [Description] a. <PN7C to PN0C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output TMPA910CRA- 177 2010-06-02 TMPA910CRA 3. GPIONFR1 (Port N Function Register 1) Address = (0xF080_C000) + (0x0424) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:2] PN7F1 to PN2F1 R/W 0y000000 Port N function register 1 [1] Reserved - 0y0 Must be written as 0. Read as 0. [0] PN0F1 R/W 0y0 Port N function register 1 [Description] a. <PN7F1 to PN2F1,PN0F1> Function register 1: Controls the function setting. 4. GPIONFR2 (Port N Function Register 2) Address = (0xF080_C000) + (0x0428) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:2] Reserved - 0y000000 Must be written as 0. Read as 0. [1:0] PN1F2 to PN0F2 R/W 0y00 Port N function register 2 [Description] a. <PN1F2 to PN0F2> Function register 2: Controls the function setting. Note: The function register 1 and function register 2 can only be set exclusively of each other. These registers must not simultaneously be written as 1 even for an instant. Table 3.9.8 Function register setting table Mode GPIONFR1 GPIONFR2 General-purpose 0 0 Function 1 1 0 Function 2 0 1 Prohibited 1 1 TMPA910CRA- 178 2010-06-02 TMPA910CRA 5. GPIONIS (Port N Interrupt Select Register (Level and Edge)) Address = (0xF080_C000) + (0x0804) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:4] PN7IS to PN4IS R/W 0y0000 Read as undefined. Written as zero. Port N interrupt sensitivity register (for each bit) 0y0: Edge-sensitive 0y1: Level-sensitive [3:0] Reserved - 0y0000 Must be written as 0. Read as 0. [Description] a. <PN7IS to PN4IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIONIBE (Port N Interrupt Select Register (Single edge and Both edge)) Address = (0xF080_C000) + (0x0808) Bit Bit [31:8] [7:4] Type Symbol Reset Description Value - - Undefined Read as undefined. Written as zero. PN7IBE to R/W 0y0000 Port N interrupt both-edge register (for each PN4IBE bit) 0y0: Single edge 0y1: Both-edge [3:0] Reserved - 0y0000 Must be written as 0. Read as 0. [Description] a. <PN7IBE to PN4IBE> Interrupt both-edge register: Selects single edge or both-edge. 0y0: Single edge 0y1: Both-edge TMPA910CRA- 179 2010-06-02 TMPA910CRA 7. GPIONIEV (Port N Interrupt Select Register("Falling edge/Low level" and "Rising edge/High level")) Address = (0xF080_C000) + (0x080C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:4] PN7IEV to PN4IEV R/W 0y0000 Port N interrupt event register (for each bit) 0y0: Falling edge/Low level 0y1: Rising edge/High level [3:0] - Reserved 0y0000 Must be written as 0. Read as 0. [Description] a. <PN7IEV to PN4IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and Low level or High level for level-sensitive interrupts. 0y0: Falling edge/Low level 0y1: Rising edge/High level 8. GPIONIE (Port N Interrupt Enable Register) Address = (0xF080_C000) + (0x0810) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:4] PN7IE to PN4IE R/W 0y0000 Read as undefined. Written as zero. Port N interrupt enable register (for each bit) 0y0: Disable 0y1: Enable [3:0] Reserved - 0y0000 Must be written as 0. Read as 0. [Description] a. <PN7IE to PN4IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disable 0y1: Enable TMPA910CRA- 180 2010-06-02 TMPA910CRA 9. GPIONRIS (Port N Interrupt Status Register (Raw)) Address = (0xF080_C000) + (0x0814) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. [7:4] PN7RIS to PN4RIS RO 0y0000 Port N interrupt raw status register (for each bit) 0y0: Not requested 0y1: Requested - [3:0] - Undefined Read undefined. [Description] a. <PN7RIS to PN4RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not requested 0y1: Requested 10. GPIONMIS (Port N Interrupt Status Register (Masked)) Address = (0xF080_C000) + (0x0818) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read undefined. [7:4] PN7MIS to PN4MIS RO 0y0000 Port N masked interrupt status register (for each bit) 0y0: Not requested 0y1: Requested [3:0] - - Undefined Read undefined. [Description] a. <PN7MIS to PN4MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt enable register. 0y0: Not requested 0y1: Requested Note: Refer to Table 3.9.5 for each external interrupt configuration. TMPA910CRA- 181 2010-06-02 TMPA910CRA 11. GPIONIC (Port N Interrupt Clear Register) Address = (0xF080_C000) + (0x081C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:4] PN7IC to PN4IC WO 0y0000 Port N interrupt clear register (for each bit) 0y0: Invalid 0y1: Clear [3:0] - - Undefined Read as undefined. Written as zero. [Description] a. <PN7IC to PN4IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear TMPA910CRA- 182 2010-06-02 TMPA910CRA 3.9.2.14 Port P Port P can be used as general-purpose input/output pins. Port P can also be used as interrupt function pins (INT7 to INT0). General-purpose input and Interrupt settings Input/Output Interrupt Enable Function Data Value General-purpose input GPIOPDATA GPIOPDIR GPIOPIE Interrupt * 0 0/1 Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input/INT7 Input/INT6 Input/INT5 Input/INT4 Input/INT3 Input/INT2 Input/INT1 Input/INT0 Note: All bits support the interrupt function. General-purpose output setting Input/Output Interrupt Enable Function Data Value General-purpose GPIOPDATA GPIOPDIR GPIOPIE output * 1 0 Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output Base address = 0xF080_D000 Register Address Name (base+) GPIOPDATA 0x03FC Description Port P Data Register GPIOPDIR 0x0400 Port P Data Direction Register - 0x0424 Reserved - 0x0428 Reserved GPIOPIS 0x0804 Port P Interrupt Select Register (Level and Edge) GPIOPIBE 0x0808 Port P Interrupt Select Register (Single edge and Both edge) GPIOPIEV 0x080C Port P Interrupt Select Register (Falling edge/Low level and Rising edge/High level) GPIOPIE 0x0810 GPIOPRIS 0x0814 Port P Interrupt Enable Register Port P Interrupt Status Register (Raw) GPIOPMIS 0x0818 Port P Interrupt Status Register (Masked) GPIOPIC 0x081C Port P Interrupt Clear Register - 0x0C00 Reserved TMPA910CRA- 183 2010-06-02 TMPA910CRA 1. GPIOPDATA (Port P Data Register) Address = (0xF080_D000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PP7 to PP0 R/W 0xFF Bm7:0 Port P data register [Description] a. <PP7 to PP0> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOPDIR (Port P Data Direction Register) Address = (0xF080_D000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] PP7C to PP0C R/W 0x00 Read as undefined. Written as zero. Port P data direction register (for each bit) 0y0: Input 0y1: Output [Description] a. <PP7C to PP0C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output 3. GPIOPIS (Port P Interrupt Select Register (Level and Edge)) Address = (0xF080_D000) + (0x0804) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] PP7IS to PP0IS R/W 0x00 Read as undefined. Written as zero. Port P interrupt sensitivity register (for each bit) 0y0: Edge-sensitive 0y1: Level-sensitive [Description] a. <PP7IS to PP0IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive TMPA910CRA- 184 2010-06-02 TMPA910CRA 4. GPIOPIBE (Port P Interrupt Select Register (Single edge and Both edge)) Address = (0xF080_D000) + (0x0808) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PP7IBE to PP0IBE R/W 0x00 Port P interrupt both-edge register (for each bit) 0y0: Single edge 0y1: Both-edge [Description] a. <PP7IBE to PP0IBE> Interrupt both-edge register: Selects single edge or both-edge. 0y0: Single edge 0y1: Both-edge 5. GPIOPIEV (Port P Interrupt Select Register ("Falling edge/Low level" and "Rising edge/High level")) Address = (0xF080_D000) + (0x080C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PC7IEV to PC0IEV R/W 0x00 Port C interrupt event register (for each bit) 0y0: Falling edge/Low level 0y1: Rising edge/High level [Description] a. <PP7IEV to PP0IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and Low level or High level for level-sensitive interrupts. 0y0: Falling edge/Low level 0y1: Rising edge/High level 6. GPIOPIE (Port P Interrupt Enable Register) Address = (0xF080_D000) + (0x0810) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PP7IE to PP0IE R/W 0x00 Port P interrupt enable register (for each bit) 0y0: Disable 0y1: Enable [Description] a. <PP7IE to PP0IE > Interrupt enable register: Enables or disables interrupts. 0y0: Disable 0y1: Enable TMPA910CRA- 185 2010-06-02 TMPA910CRA 7. GPIOPRIS (Port P Interrupt Status Register (Raw)) Address = (0xF080_D000) + (0x0814) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] PP7RIS to PP0RIS RO 0x00 Read as undefined. Port P interrupt raw status register (for each bit) 0y0: Not requested 0y1: Requested [Description] a. <PP7RIS to PP0RIS > Interrupt raw status register: Monitors the interrupt status before masking. 0y0: Not requested 0y1: Requested 8. GPIOPMIS (Port P Interrupt Status Register (Masked)) Address = (0xF080_D000) + (0x0818) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read undefined. [7:0] PP7MIS to PP0MIS RO 0x00 Port P interrupt masked status register (for each bit) 0y0: Not requested 0y1: Requested [Description] a. <PP7MIS to PP0MIS> Masked interrupt status register: Monitors the interrupt status after masking. 0y0: Not requested 0y1: Requested Note: Refer to Table 3.9.5 for each external interrupt configuration. TMPA910CRA- 186 2010-06-02 TMPA910CRA 9. GPIOPIC (Port P Interrupt Clear Register) Address = (0xF080_D000) + (0x081C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PP7IC to PP0IC WO 0x00 Port P interrupt clear register (for each bit) 0y0: Invalid 0y1: Clear request [Description] a. <PP7IC to PP0IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear TMPA910CRA- 187 2010-06-02 TMPA910CRA 3.9.2.15 Port R Bit 2 of Port R can be used as a general-purpose input/output pin and bits [0:1] can be used as general-purpose output pins. (Bits [7:3] are not used.) Port R can also be used as reset output (RESETOUTn), high-frequency clock output (FCOUT), interrupt function (INTH) and write protect output function for memory (SMCWPn). General-purpose input and Interrupt settings Function Data Value General-purpose input GPIORDATA Interrupt * Bit 7 Bit 6 Bit 5 Input/Output Function Select 1 Function Select 2 Interrupt Enable GPIORDIR GPIORFR1 GPIORFR2 GPIORIE 0 0 0 0/1 Select Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input/INTH - - Note: Only Bit 2 supports the interrupt function. Setting of General-purpose output and write protect output function Input/Output Function Select Function Select Select 1 2 GPIORDATA GPIORDIR GPIORFR1 GPIORFR2 GPIORIE * 1 0 0 0 Function Data Value General-purpose output write protect output function for memory Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Interrupt Enable Bit 2 Bit 1 Bit 0 Output SMCWPn Output Reset output setting Function Reset output Bit 7 Input/Output Function Select Function Select Select 1 2 GPIORDATA GPIORDIR GPIORFR1 GPIORFR2 GPIORIE * * 1 0 0 Data Value Bit 6 Bit 5 Bit 4 Bit 3 Interrupt Enable Bit 2 Bit 1 Bit 0 - - RESETOUTn High-frequency clock output setting Input/Output Function Select Function Select Select 1 2 GPIORDATA GPIORDIR GPIORFR1 GPIORFR2 GPIORIE * * 0 1 0 Function Data Value High-frequency clock (FCOUT)output Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Interrupt Enable Bit 2 Bit 1 Bit 0 - FCOUT - Note: FCOUT is fOSCH output. TMPA910CRA- 188 2010-06-02 TMPA910CRA Base address = 0xF080_E000 Register Address Name (base+) Description GPIORDATA 0x03FC PortR Data Register GPIORDIR 0x0400 PortR Data Direction Register GPIORFR1 0x0424 PortR Function Register1 - GPIORFR2 0x0428 Reserved 0x0428 PortR Function Register2 GPIORIS 0x0804 PortR Interrupt Select Register (Level and Edge) GPIORIBE 0x0808 PortR Interrupt Select Register (Single edge and Both edge) GPIORIEV 0x080C PortR Interrupt Select Register (Falling edge/Low level and Rising edge/High level) GPIORIE 0x0810 PortR Interrupt Enable Register GPIORRIS 0x0814 PortR Interrupt Status Register (Raw) GPIORMIS 0x0818 PortR Interrupt Status Register (Masked) GPIORIC 0x081C PortR Interrupt Clear Register - 0x0C00 Reserved 1. GPIORDATA (Port R Data Register) Address = (0xF080_E000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PR7 to PR0 R/W 0xFD Bm7:0 Port R data register [Description] a. <PR7 to PR0> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIORDIR (Port R Data Direction Register) Address = (0xF080_E000) + (0x0400) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2] PR2C R/W 0y0 Port R data direction register 0y0: Input 0y1: Output [1:0] Reserved - 0y11 Read as undefined. Written as 0y11. [Description] a. <PR2C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output TMPA910CRA- 189 2010-06-02 TMPA910CRA 3. GPIORFR1 (Port R Function Register 1) Address = (0xF080_E000) + (0x0424) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2:1] Reserved - 0y00 Read as undefined. Written as zero. [0] PR0F1 R/W 0y1 Port R function register 1 [Description] a. <PR0F1> Function register 1: Controls the function setting. 4. GPIORFR2 (Port R Function Register 2) Address = (0xF080_E000) + (0x0428) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2] Reserved - 0y0 Read as undefined. Written as zero. [1] PR1F2 R/W 0y0 Port R function register 2 [0] Reserved - 0y0 Read as undefined. Written as zero. [Description] a. <PR1F2> Function register 2: Controls the function setting. Note: The function register 1 and function register 2 can only be set exclusively of each other. These registers must not simultaneously be written as 1 even for an instant. Table 3.9.9 Function register setting table Mode GPIORFR1 GPIORFR2 General-purpose 0 0 Function 1 1 0 Function 2 0 1 Prohibited 1 1 TMPA910CRA- 190 2010-06-02 TMPA910CRA 5. GPIORIS (Port R Interrupt Select Register (Level and Edge)) Address = (0xF080_E000) + (0x0804) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2] PR2IS R/W 0y0 Port R interrupt sensitivity register 0y0: Edge-sensitive 0y1: Level-sensitive [1:0] Reserved - 0y00 Read as undefined. Written as zero. [Description] a. <PR2IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIORIBE (Port R Interrupt Select Register (Single edge and Both edge)) Address = (0xF080_E000) + (0x0808) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2] PR2IBE R/W 0y0 Port R interrupt both-edge register 0y0: Single edge 0y1: Both-edge [1:0] Reserved - 0y00 Read as undefined. Written as zero. [Description] a. <PR2IBE> Interrupt both-edge register: Selects single edge or both-edge. 0y0: Single edge 0y1: Both-edge TMPA910CRA- 191 2010-06-02 TMPA910CRA 7. GPIORIEV (Port R Interrupt Select Register("Falling edge/Low level" and "Rising edge/High level")) Address = (0xF080_E000) + (0x080C) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2] PR2IEV R/W 0y0 Port R interrupt event register 0y0: Falling edge/Low level 0y1: Rising edge/High level [1:0] Reserved - 0y00 Read as undefined. Written as zero. [Description] a. <PR2IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and Low level or High level for level-sensitive interrupts. 0y0: Falling edge/Low level 0y1: Rising edge/High level 8. GPIORIE (Port R Interrupt Enable Register) Address = (0xF080_E000) + (0x0810) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2] PR2IE R/W 0y0 Port R interrupt enable register 0y0: Disable 0y1: Enable [1:0] Reserved - 0y00 Read as undefined. Written as zero. [Description] a. <PR2IE > Interrupt enable register: Enables or disables interrupts. 0y0: Disable 0y1: Enable TMPA910CRA- 192 2010-06-02 TMPA910CRA 9. GPIORRIS (Port R Interrupt Status Register (Raw)) Address = (0xF080_E000) + (0x0814) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. [7:3] - - Undefined Read undefined. [2] PR2RIS RO 0y0 Port R interrupt raw status register 0y0: Not requested 0y1: Requested - [1:0] - Undefined Read undefined. [Description] a. <PR2RIS > Interrupt raw status register: Monitors the interrupt status before masking. 0y0: Not requested 0y1: Requested 10. GPIORMIS (Port R Interrupt Status Register (Masked)) Address = (0xF080_E000) + (0x0818) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. [7:3] - - Undefined Read undefined. [2] PR2MIS RO 0y0 Port R masked interrupt status register 0y0: Not requested 0y1: Requested [1:0] - - Undefined Read undefined. [Description] a. <PR2MIS> Masked interrupt status register: Monitors the interrupt status after masking. 0y0: Not requested 0y1: Requested Note: Refer to Table 3.9.5 for each external interrupt configuration. TMPA910CRA- 193 2010-06-02 TMPA910CRA 11. GPIORIC (Port R Interrupt Clear Register) Address = (0xF080_E000) + (0x081C) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:3] - - Undefined Read as undefined. Written as zero. [2] PR2IC WO 0y0 Port R interrupt clear register 0y0: Invalid 0y1: Clear request [1:0] - - Undefined Read as undefined. Written as zero. [Description] a. <PR2IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear request TMPA910CRA- 194 2010-06-02 TMPA910CRA 3.9.2.16 Port T Port T can be used as general-purpose input/output pins. Port T can also be used as USB external clock input (X1USB), UART function (U1CTSn, U1RXD, U1TXD), and SSP function (SP0DI, SP0DO, SP0CLK, SP0FSS) pins. General-purpose input setting Function General-purpose input Data Value Input/Output Select Function Select 1 GPIOTDATA GPIOTDIR GPIOTFR1 * 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Input Input Input Input Input Input Input General-purpose output setting Function General-purpose output Data Value Input/Output Select Function Select 1 GPIOTDATA GPIOTDIR GPIOTFR1 * 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output Output Output Output Output Output Output Output UARTSSP settings Function Data Value Input/Output Select Function Select 1 UART GPIOTDATA GPIOTDIR GPIOTFR1 SSP * * 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X1USB U1CTSn U1RXD U1TXD SP0DI SP0DO SP0CLK SP0FSS TMPA910CRA- 195 2010-06-02 TMPA910CRA Base address = 0xF080_F000 Register Address Name (base+) Description GPIOTDATA 0x03FC PortT Data Register GPIOTDIR 0x0400 PortT Data Direction Register GPIOTFR1 0x0424 PortT Function Register1 - 0x0428 Reserved - 0x0804 Reserved - 0x0808 Reserved - 0x080C Reserved - 0x0810 Reserved - 0x0814 Reserved - 0x0818 Reserved - 0x081C Reserved - 0x0C00 Reserved 1. GPIOTDATA (Port T Data Register) Address = (0xF080_F000) + (0x03FC) Bit Bit Reset Type Symbol Bit mask Value Description [31:8] - - Undefined - Read as undefined. Written as zero. [7:0] PT7 to PT0 R/W 0xFF Bm7:0 Port T data register [Description] a. <PT7 to PT0> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOTDIR (Port T Data Direction Register) Address = (0xF080_F000) + (0x0400) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PT7C to PT0C R/W 0x00 Port T data direction register (for each bit) 0y0: Input 0y1: Output [Description] a. <PT7C to PT0C> Data direction register: Selects input or output for each pin used as a general-purpose port. 0y0: Input 0y1: Output TMPA910CRA- 196 2010-06-02 TMPA910CRA 3. GPIOTFR1 (Port T Function Register 1) Address = (0xF080_F000) + (0x0424) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Written as zero. [7:0] PT7F1 to PT0F1 R/W 0x00 Port T function register 1 [Description] a. <PT7F1 to PT0F1> Function register 1: Controls the function setting. TMPA910CRA- 197 2010-06-02 TMPA910CRA 3.9.3 Notes * Procedure for using the interrupt function Interrupts can be detected in various modes depending on the sensitivity setting. The following procedure should be observed when the interrupt function is enabled (GPIOnIE = 1) or the interrupt mode settings are modified by GPIOnIS, GPIOnIBE, GPIOnIEV. 1. Disable interrupts in a relevant bit of the GPIOnDIR register (GPIOnDIR = 0). 2. Disable interrupts in a relevant bit of the GPIOnIE register (GPIOnIE = 0). 3. Set a relevant bit of the interrupt mode setting registers (GPIOnIS, GPIOnIBE and GPIOnIEV). 4. Clear the interrupt in a relevant bit of the GPIOnIC register (GPIOnIC = 1). 5. Enable interrupts in a relevant bit of the GPIOnIE register (GPIOnIE = 1). TMPA910CRA- 198 2010-06-02 TMPA910CRA 3.10 MPMC This LSI contains two types of memory controller with different specifications. Depending on the connected external memory, one of two types of controllers (MPMC0/MPMC1) can be selected by setting the external pin SELMEMC (port SN0). By setting the external pin SELDVCCM (port SN1) and the internal PMCDRV register, the power supply voltage of memory interface DVCCM can be selected to correspond to 1.8 V or 3.3 V. In the case of using SDRAM, special settings for special pins and registers are required. Required settings are shown in the table below. Table 3.10.1 Memory controller and Voltage Configurations Supply Voltage for External memory Memory controller configuration 1.8 V 0.1 V SELMEMC (Note1) MPMC0 SDRAM is used Pin configuration 0 input SELDVCCM (Note1) 1 input configuration 0 input PMCDRV<DRV_MEM1:0> 16bit_bus 32bit_bus 0y11 0y01 0x00000010 dmc_user_config3 SELMEMC (Note1) 0x00000011 1 input SELDVCCM (Note1) MPMC1 0 input DMCCLKIN Register 3.3 V 0.3 V 0 input DMCDCLKP Pin configuration connect to DMCCLKIN External Memory N/A (Note2) SDRAM is used Register PMCDRV<DRV_MEM1:0> configuration 16bit_bus 32bit_bus dmc_user_config_5 0y11 0x00000048 N/A Note1: The SELMEMC and SELDVCCM pins derive power from DVCC3IO. Therefore, 0 input voltage must be 0 V and 1 input voltage must be 3.3 V. Note 2: When using MPMC1 to control DDR SDRAM, the feedback clock DMCCLKP for MPMC1 data latch must be input. DMCCLKP must be connected to DMCCLKIN (input pin) as short as possible in designing a board. When using MPMC0 to control SDR SDRAM or not using SDRAM, take a precaution to avoid leak current (e. g. fixing DMCCLKIN pin to GND). TMPA910CRA- 199 2010-06-02 TMPA910CRA The following shows differences in supported memory between MPMC0 and MPMC1. Select MPMC0 or MPMC1 depending on SDRAM to use. MPMC0: 32-bit/16-bit Standard type SDR SDRAM 32-bit/16-bit Mobile type SDR SDRAM 32-bit/16-bit NOR Flash (Separate bus only) 32-bit/16-bit SRAM (Separate bus only) MPMC1: 16-bit LVCMOS type DDR SDRAM 32-bit/16-bit NOR Flash (Separate bus only) 32-bit/16-bit SRAM (Separate bus only) Mode setting pin Operation mode SELMEMC 0 Use MPMC0 1 Use MPMC1 Note 1: SDR SDRAM and DDR SDRAM cannot be used concurrently. Note 2: The two memory controllers cannot be used by dynamically switching between them. The memory controller to be used must be fixed. Refer to chapters on respective circuits for details. The following shows the MPMC block diagram. MPMC MPMC1 DMC LVCMOS type DDR SDRAM Controller External Bus Interface SMC Static Memory Controller fHCLK /2 MPMC0 EBI SMC CLKCR5 <SEL_SMC_MCLK> Static Memory Controller SELMEMC DMC Standard/Mobile type SDR SDRAM Controller SELMEMC TMPA910CRA- 200 2010-06-02 TMPA910CRA According to the voltage of the connected external memory, set pin and register as follows. Note: The two memory controllers cannot be used by dynamically switching between them. The memory controller to be used must be fixed. Mode setting pin Operation mode SELDVCCM 0 1 Control pin of external memory except NAND Flash operate in the DVCCM = 1.8 0.1 V. Control pin of external memory operate in the DVCCM = 3.3 0.3 V. According to power voltage, adjust drive power of related ports. In the case of using SDRAM, related pin connections and the constant value setting register need be set. The following table shows the required setting. Port drive power set register Operation mode PMCDRV<DRV_MEM1:0> 0y11 0y01 control pin of external memory except NAND Flash operate in the DVCCM = 1.8 0.1 V control pin of external memory operate in the DVCCM = 3.3 0.3 V Note: The PMCDRV register should be set during low-speed operation (PLL = OFF) after reset is released. [SDR SDRAM] Bus width setting register Operation mode dmc_user_config_3 0x00000010 16bit bus 0x00000011 32bit bus Note: The dmc_user_config_3 register should be set after reset is released and before SDRAM is initialized. This also applies after HOT_RESET by the PMC is released. Pin treatment Operation mode DMCCLKIN This pin isn't used. 16/32 bit bus (Fix DMCCLKIN to GND) [DDR SDRAM] Bus width setting register Operation mode dmc_user_config_5 0x00000048 6bit bus (32bit bus DDR type SDRAM isn't supported) Note: The dmc_user_config_5 register should be set after reset is released and before SDRAM is initialized. This also applies after HOT_RESET by the PMC is released. pin treatment Operation mode DMCCLKIN Connect DMCCLKIN to DMCCLKP 16bit bus (32bit bus DDR type SDRAM isn't supported) TMPA910CRA- 201 2010-06-02 TMPA910CRA 3.10.1 EBI (External Bus Interface) Memory controllers (MPMC0 and MPMC1) have a built-in SMC (Static Memory Controller) circuit and DMC (Dynamic Memory Controller) circuit. The external bus of SMC is used also as the external bus of DMC in the TMPA910CRA. However, SMC and DMC function as independent circuits in memory controller. DMC and SMC circuits are controlled by EBI (External Bus Interface). ARM926EJ-S Data Cache 16 Kbyte Instruction Cache 16 Kbyte (Bus Master 1&2) Bus Interface CPU Inst. LCD Controller CPU Data. DMA Controller DMA1 LCDC DMA2 (Bus Master 3) (Bus Master 5&6) LCD Data Process Accelerator LCDDA USB Device Controller USB (Bus Master 4) (Bus Master 7) CPU Data Other Peripheral Circuit DMA1 DMA2 DMA1 DMA2 CPU Inst. CPU Data. LCDDA LCDC USB Multi Layer Bus Matrix 0 SELMEMC Internal RAM0 16 KB Internal RAM1 16 KB Internal RAM2 16 KB Internal RAM3 8 KB Multi Layer Multi Layer Bus Matrix Bus Matrix MPMC0 SMC DMC MPMC1 SMC DMC Boot ROM 16 KB EBI External Bus Interface TimeOut Counter Bus switcher SDRAM Memory TMPA910CRA- 202 NORF Memory 2010-06-02 TMPA910CRA EBI shifts the bus according to the access request from memory controller (DMC and SMC). If two Access requests of DMC and SMC are generated, EBI keeps the one Access request wait, when the other is accessing. To avoid the one Access request is made to wait for a long time when one Access request is generated continuously, EBI manage the overlapped time, also it has a "Timeout counter"; the bus is released forcibly. In the TMPA910CRA, the higher the access speed and the frequency become, the higher the priority of the DMC becomes.. Therefore, it has function to prioritize DMC request by setting Timeout cycle of SMC side to register. Table 3.10.2 Timeout for EBI DMC time out cycle SMC time out cycle 1024 clocks (Fixed) to 1024 clocks (configurable with register) SMC timeout cycle setting register Base address = 0xF00A_0000 Register Address Name (base+) smc_timeout 0x0050 Type R/W Reset value 0x000000FF Description SMC Timeout Register Note: "0x00000000" cannot be set. "0x00000001 to 0x000000FF" only is effective. The smc_timeout cycle is controlled by a 10 bit counter, however, the effective bits in control register are Low-order 8bits only. The most significant bit (bit 7) of effective bits controls High-order 3bits of the 10 bit counter. smc_timeout register bit31 to bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TIMEOUT Counter Note: To avoid an underflow in LCDC when setting DMC memory (SDRAM) to VRAM of LCDC,It is recommended to set this register to 0y01.Please use this function together with the QOS function (refer to "DMC" section) TMPA910CRA- 203 2010-06-02 TMPA910CRA 3.10.2 Overview of MPMC0 MPMC0 contains both a DMC (Dynamic Memory Controller) that controls SDRAM and SMC (Static Memory Controller) that controls NOR Flash and SRAM. Features of a DMC (Dynamic Memory Controller): (a) Supports 32-bit/16-bit SDR SDRAM (b) Supports 1 channel Chip Select (c) Supports clock-basis adjusting function for SDRAM request timing. Features of an SMC (Static Memory Controller): (a) Supports synchronous and asynchronous, 32-bit/16-bit SRAM and NOR Flash (only separate buses are supported, and multiplex buses are not supported) (b) Supports 4 channels Chip Select (c) Cycle timings and memory data bus widths can be programmed for each Chip Select TMPA910CRA- 204 2010-06-02 TMPA910CRA 3.10.3 Functions of MPMC0 Figure 3.10.1 is a simplified block diagram of MPMC0 circuits. MPMC0 M CPU Data AHB0 interface M S CPU Inst AHB1 interface M S LCDC AHB2 interface M S S M S Multi layer Bus matrix3 USB DMAC1 AHB3 interface M SDR 1chip SMC SRAM/NOR 4chips APB S Bus matrix LCDDA DMC APB S S DMAC2 M Round-Robin M AHB to APB bridge S AHB Figure 3.10.1 MPMC0 Block Diagram (a) Bus matrix 1. Bus matrix of AHB0, AHB1, AHB2 and AHB3 supports Round-Robin arbitration scheme. The following diagram shows the priority of bus requests. CPU Inst (AHB0) bus request CPU Data (AHB1) bus request LCDC (AHB2) bus request AHB3 bus request (Bus request from the bus matrix 3 output of LCDDA, USB, DMAC1, and DMAC2) AHB2 AHB0 AHB1 Handling Handling Handling AHB3 AHB0 Handling Handling A dotted line is the point of handling end where bus is released. Handling priority : TMPA910CRA- 205 2010-06-02 TMPA910CRA 2. Bus matrix 2 of LCDDA, DMAC1, DMAC2 and USB handles the earliest bus request first. If multiple bus requests are accepted simultaneously, they are prioritized as shown below. LCDDA > USB > DMAC1 > DMAC2 Following diagram show the priority of bus request. LCDDA bus request USB bus request DMAC1 bus request END LCDDA USB DMAC1 LCDDA DMAC2 handling handling handling handling handling dotted line is the point of handling endbus is released Handling priority : (b) Clock Variety Control clock is controlled in PLLCG circuit. 1. Dynamic memory clock: Use HCLK clock 2. Static memory clock: Use HCLK or 1/2 HCLK (Set CLKCR5<SEL_SMC_MCLK>) TMPA910CRA- 206 2010-06-02 TMPA910CRA 3.10.3.1 DMC (Dynamic Memory Controller) (1) DMC function outline Table 3.10.3 shows features of DMC. Table 3.10.3 Features of DMC Features Support memory SDR SDRAM Support separate bus only Data bus width 16 bit/ 32 bit data bus width Access areas Max 512MB access area Timing adjustment Adjustable AC timing by register Command Mode Register setting, Auto refresh, Self Refresh, Active, Precharge, Read/Write command, Clock Powerdown etc. DMCSCLK frequency fHCLK Chip select: DMCCSn only Fixed to GND (Input clock pin DMCCLKIN can not be used) External control pin D31 to D0, A25 to A0, DMCSDQM3, DMCSDQM2, DMCSDQM1, DMCSDQM0, DMCCSn, DMCWEn, DMCRASn, DMCCASn, DMCBA0, DMCBA1, DMCCKE, DMCSCLK, DMCDCLKN, DMCAP TMPA910CRA- 207 2010-06-02 TMPA910CRA (2) DMC block diagram Figure 3.10.2 is a DMC block diagram. AHB Domain APB Domain APB I/F Memory APB Slave I/F Manager Memory Domain Arbiter EBI I/F Memory I/F DMC I/F PAD I/F External memory I/F Figure 3.10.2 DMC Block Diagram (a) Arbiter The arbiter receives access commands from the DMC I/F and the memory manager, and after access arbitration, it passes the highest priority command to the memory I/F. Data is read from the memory I/F to the DMC I/F. (b) Memory manager The memory manager monitors and controls status of DMC block. TMPA910CRA- 208 2010-06-02 TMPA910CRA (3) DMC Function operation (a) Arbiter operation 1. read/write access arbitration 2. For read accesses, QoS (Quality of Service) is provided. 3. Hazard processing When selfsame stand-alone bus master access to an external memory, the actual access procedure to memory is executed in the instruction order. However, if multiple bus master access to an external memory, the read and write data will be stored temporary into independent buffer and be executing by priority circuit. Therefore, the read and the write instruction may switch execution sequence. So please coordinate a variety of sequences, e.g. making an enough time for next instruction, checking whether or not previous execution is finished, the common-use memory data uses the internal memory and so on. 4. Monitoring the state machine and select an entry of the proper pipeline. (b) Memory manager operation 1. Monitor and control DMC circuit 2. Issuing direct commands * NOP * Prechargeall * Autorefresh * Modereg * Extended modereg 3. Auto Refresh function is provided Set Auto Refresh timing by 15bit counter (c) Memory interface operation According to use, there are three kinds of built-in FIFOs 1. command FIFO: 2 words 2. read data FIFO: 10 words 3. write data FIFO: 10 words * As the FIFO sizes of either read or write FIFO is 10 words, the max size for one transfer is 8 words. (1word = 32 bit data) When you use SDRAM of 32bit bus, it can not be set to Burst16. (d) Low_power function DMC provide 2 kinds of Low_power modes. 1. By setting dmc_memc_cmd_3 register, Self Refresh Mode is available. 2. By setting dmc_memory_cfg_3 register, either of the two modes is available: Clock Suspend Mode to stop memory clock (DMCCLK) or Power Down Mode to make the CKE pin (CKE = low) invalid automatically when there is no memory access. Note: Clock Suspend Mode function and Power Down mode cannot be used concurrently. TMPA910CRA- 209 2010-06-02 TMPA910CRA (e) QoS Function The QoS function is available in read-accessing only. The QoS function is the service function for exception handling at Round-Robin which is controlled by Bus matrix for MPMC. dmc_id_x_cfg_3<qos_max> is set by a register within the DMC on a port by port basis. dmc_id_x_cfg_3<qos_max> indicates a required read maximum latency. A QoS_max timeout causes the transaction to be raised to a higher priority. You can also set dmc_id_x_cfg_3<qos_min> to enable for a specific port so that its transfers are serviced with a higher priority. This impacts the overall memory band width because it limits the options of the scheduling algorithm. If dmc_id_x_cfg_3<qos_enable> enable bit for the port is set in the register bank, the qos_max latency value is decremented every cycle until it reaches zero. If the entry is still in the queue when the Internal counter value reaches zero then the entry becomes the highest priority. This is called a time-out. If qos_min is set to enable, qos_max value is ignored and it always becomes the highest priority. TMPA910CRA- 210 2010-06-02 TMPA910CRA Table 3.10.4 SDR Memory Setup Example Base address = 0xF430_0000 Register address Write data Description 0x0014 0x00000006 Set cas_Latency to 3 0x0018 0x00000000 Set t_dqss to 0 0x001C 0x00000002 Set t_mrd to 2 0x0020 0x00000007 Set t_ras to 7 0x0024 0x0000000B Set t_rc to 11 0x0028 0x00000015 Set t_rcd to 5 and schedule_rcd to 2 0x002C 0x000001F2 Set t_rfc to 18 and schedule_rfc to 15 0x0030 0x00000015 Set t_rp to 5 and schedule_rp to 2 0x0034 0x00000002 Set t_rrd to 2 0x0038 0x00000003 Set t_wr to 3 0x003C 0x00000002 Set t_wtr to 2 0x0040 0x00000001 Set t_xp to 1 0x0044 0x0000000A Set t_xsr to 10 0x0048 0x00000014 Set t_esr to 20 0x000C 0x00010020 Set memory configuration 0x0010 0x00000A60 Set auto refresh period to be every 2656 DMCSCLK periods 0x0200 0x000000FF Set chip select for chip 0 to be 0x00XXXXXX, rbc configuration 0x0008 0x000C0000 Carry out chip 0 Nop command 0x0008 0x00000000 Carry out chip 0 Prechargeall command 0x0008 0x00040000 Carry out chip 0 Autorefresh command 0x0008 0x00040000 Carry out chip 0 Autorefresh command 0x0008 0x00080032 Carry out chip 0 Mode Reg command 0x32 mapped to low add bits 0x0004 0x00000000 Change DMC state to Ready TMPA910CRA- 211 2010-06-02 TMPA910CRA (4) DMC register description of MPMC0 Table 3.10.5 DMC SFR list of MPMC0 Base address = 0xF430_0000 Register Address Name (base +) Type Reset Value Description dmc_memc_status_3 0x0000 RO 0x00000380 DMC Memory Controller Status Register dmc_memc_cmd_3 0x0004 WO - DMC Memory Controller Command Register dmc_direct_cmd_3 0x0008 WO - DMC Direct Command Register dmc_memory_cfg_3 0x000C R/W 0x00010020 DMC Memory Configuration Register dmc_refresh_prd_3 0x0010 R/W 0x00000A60 DMC Refresh Period Register dmc_cas_latency_3 0x0014 R/W 0x00000006 DMC CAS Latency Register dmc_t_dqss_3 0x0018 R/W 0x00000001 DMC t_dqss Register dmc_t_mrd_3 0x001C R/W 0x00000002 DMC t_mrd Register dmc_t_ras_3 0x0020 R/W 0x00000007 DMC t_ras Register dmc_t_rc_3 0x0024 R/W 0x0000000B DMC t_rc Register dmc_t_rcd_3 0x0028 R/W 0x0000001D DMC t_rcd Register dmc_t_rfc_3 0x002C R/W 0x00000212 DMC t_rfc Register dmc_t_rp_3 0x0030 R/W 0x0000001D DMC t_rp Register dmc_t_rrd_3 0x0034 R/W 0x00000002 DMC t_rrd Register dmc_t_wr_3 0x0038 R/W 0x00000003 DMC t_wr Register dmc_t_wtr_3 0x003C R/W 0x00000002 DMC t_wtr Register dmc_t_xp_3 0x0040 R/W 0x00000001 DMC t_xp Register dmc_t_xsr_3 0x0044 R/W 0x0000000A DMC t_xsr Register dmc_t_esr_3 0x0048 R/W 0x00000014 DMC t_esr Register dmc_id_0_cfg_3 0x0100 R/W 0x00000000 DMC id_<0-3>_cfg Registers dmc_id_1_cfg_3 0x0104 dmc_id_2_cfg_3 0x0108 dmc_id_3_cfg_3 0x010C dmc_chip_0_cfg_3 0x0200 R/W 0x0000FF00 DMC chip_0_cfg Registers Reserved 0x0204 - Undefined Read undefined. Write as zero. Reserved 0x0208 - Undefined Read undefined. Write as zero. Reserved 0x020C - Undefined Read undefined. Write as zero. Reserved 0x0300 - Undefined Read undefined. Write as zero. dmc_user_config_3 0x0304 WO Undefined DMC user_config Register Reserved 0x0E00 - Undefined Read undefined. Write as zero. Reserved 0x0E04 - Undefined Read undefined. Write as zero. Reserved 0x0E08 - Undefined Read undefined. Write as zero. Reserved 0x0FE0-0x0FEC - Undefined Read undefined. Write as zero. Reserved 0x0FF0-0x0FFC -- Undefined Read undefined. Write as zero. Note: The APB supports only single-word 32-bit accesses. Read from or write to registers at single-word 32-bit mode. TMPA910CRA- 212 2010-06-02 TMPA910CRA MPMC0 The status of register read/write access (dmc_memc_status_3 status) :permitted Register Name x:prohibited Type Read Write dmc_memc_status_3 dmc_memc_status_3 config Ready Paused Low_power config Ready Paused Low_power dmc_memc_status_3 RO - - - - dmc_memc_cmd_3 WO - - - - dmc_direct_cmd_3 WO - - - - dmc_memory_cfg_3 R/W dmc_refresh_prd_3 R/W x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x dmc_t_xsr_3 R/W dmc_t_esr_3 R/W dmc_id_0_cfg_3 R/W dmc_chip_0_cfg_3 R/W dmc_user_config_3 WO - - - - dmc_cas_latency_3 R/W dmc_t_dqss_3 R/W dmc_t_mrd_3 R/W dmc_t_ras_3 R/W dmc_t_rc_3 R/W dmc_t_rcd_3 R/W dmc_t_rfc_3 R/W dmc_t_rp_3 R/W dmc_t_rrd_3 R/W dmc_t_wr_3 R/W dmc_t_wtr_3 R/W dmc_t_xp_3 R/W dmc_id_1_cfg_3 dmc_id_2_cfg_3 dmc_id_3_cfg_3 TMPA910CRA- 213 2010-06-02 TMPA910CRA 1. dmc_memc_status_3 (DMC Memory Controller Status Register) Address = (0xF430_0000) + (0x0000) Bit Bit Type Symbol Reset Description Value [31:10] - - Undefined Read as undefined. [9] memory_banks RO 0y1 Setting value of the maximum number of banks that the DMC supports: (Fixed to 4 banks) [8:7] Reserved - Undefined Read as undefined. [6:4] memory_ddr RO 0y000 Types of SDRAM that the DMC supports: 0y000 = SDR SDRAM 0y001 = Reserved 0y011 = Reserved 0y010 = Reserved 0y1xx = Reserved [3:2] memory_width RO 0y01 External memory bus width: 0y00 = 16-bit 0y01 = 32-bit 0y10 = Reserved 0y11 = Reserved [1:0] memc_status RO 0y00 Memory controller status: 0y00 = Config 0y01 = Ready 0y10 = Paused 0y11 = Low-power [Description] a. <memory_banks> Setting value of the maximum number of banks that the DMC supports: Fixed to 4 banks. b. <memory_ddr> Types of SDRAM that the DMC supports. Fixed to 0y000 (SDR SDRAM). c. <memory_width> External memory bus width: 0y00 = 16-bit 0y01 = 32-bit 0y10 = Reserved 0y11 = Reserved. d. <memc_status> Memory controller status: 0y00 = Config 0y01 = Ready 0y10 = Paused 0y11 = Low-power TMPA910CRA- 214 2010-06-02 TMPA910CRA 2. dmc_memc_cmd_3 (DMC Memory Controller Command Register) Address = (0xF430_0000) + (0x0004) Bit Bit Symbol Reset Type Description Value [31:3] - - Undefined Read as undefined. Write as zero. [2:0] memc_cmd WO - Change the memory controller status: 0y000 = Go 0y001 = Sleep 0y010 = Wakeup 0y011 = Pause 0y100 = Configure [Description] a. <memc_cmd> Settings of this register can change the DMC state machine. If a previously issued command for changing the states is being executed, a new command is issued after the previous command is completed. The following diagram shows DMC state transitions. Low power POR Sleep Pause Reset Pause config Wakeup Configure Go Go Ready DMC State Transitions When the DMC exits the Reset state, it automatically enters the Config state. The state transition from Pause to Config is effected by a Config command. Register settings must be made during the Config state. When the DMC state is shifted to Ready, reads from and writes to the SDRAM are allowed. When a read or write is executed, the SDRAM will change from IDLE to ACTIVE. When the DMC state is Ready, a Pause command shifts the DMC to Pause. The SDRAM state at this time varies depending on the immediately preceding command executed on the SDRAM. If a Read or Write has been executed, the SDRAM will be shifted to ACTIVE. If AutoRefresh has been executed, the SDRAM will be shifted to IDLE (Note). TMPA910CRA- 215 2010-06-02 TMPA910CRA When the DMC state is shifted from Pause to Low power by a Sleep command, after All Bank Precharge is executed, CKE will be driven "L" and the SDRAM will automatically enter the Self-refresh state. When the DMC state is shifted from Low power to Pause by a Wakeup command, a Self-refresh Exit command will be issued. The SDRAM then automatically exists the Self-refresh state and enters the IDLE state. Note: The SDRAM can be shifted from ACTIVE to IDLE by either of the following two settings: dmc_direct_cmd_3< memory_cmd>0y00 = Prechargeall or 0y01 = Autorefresh TMPA910CRA- 216 2010-06-02 TMPA910CRA 3. dmc_direct_cmd_3 (DMC Direct Command Register) This register sets each command for external memory and external memory mode register. This register sets the initial setting of external memory. Address = (0xF430_0000) + (0x0008) Bit Bit Symbol Reset Type Description Value [31:22] - - Undefined Read as undefined. Write as zero. [21:20] chip_nmbr WO - Always write 0y00. [19:18] memory_cmd WO - Determines the command required: 0y00 = Prechargeall 0y01 = Autorefresh 0y10 = Modereg or Extended Modereg 0y11 = NOP [17:16] bank_addr WO - Bits mapped to external memory bank address bits when command is Modereg access. 0y00 = bank0 0y01 = bank1 0y10 = bank2 0y11 = bank3 [15:14] - - Undefined Read as undefined. Write as zero. [13:0] addr_13_to_0 WO - Bits mapped to external memory address bits [13:0] when command is Modereg access. a. <memory_cmd> Determines the command required: 0y00 = Prechargeall 0y01 = Autorefresh 0y10 = Modereg or Extended modereg 0y11 = NOP b. <bank_addr> Bits mapped to external memory bank address bits when command is Modereg access. 0y00 = bank0 0y01 = bank1 0y10 = bank2 0y11 = bank3 c. <addr_13_to_0> Bits mapped to external memory address bits [13:0] when command is Modereg access. TMPA910CRA- 217 2010-06-02 TMPA910CRA 4. dmc_memory_cfg_3 (DMC Memory Configuration Register) Address = (0xF430_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value [31:23] - - Undefined Read as undefined. Write as zero. [22:21] active_chips R/W 0y00 Always write 0y00 [20:18] - - Undefined Read as undefined. Write as zero. [17:15] memory_burst R/W 0y010 Set the read/write access burst length for the SDRAM 0y000 = Burst 1 0y001 = Burst 2 0y010 = Burst 4 0y011 = Burst 8 0y100 = Burst 16 (Note) Other = Reserved [14] stop_mem_clock R/W 0y0 memory clock stop: 0y0 = Disable 0y1 = Enable [13] auto_power_down R/W 0y0 SDRAM auto Power down Enable: 0y0 = Disable 0y1 = Enable [12:7] power_down_prd R/W 0y000000 Number of SDRAM automatic power-down memory clocks: (Min. value = 1) 0y000001 to 0y111111 [6] ap_bit R/W 0y0 The position of the auto-precharge bit in the memory address: 0y0 = address bit 10 0y1 = address bit 8 [5:3] row_bits R/W 0y100 The number of row address bits: 0y000 = 11 bits 0y001 = 12 bits 0y010 = 13 bits 0y011 = 14 bits 0y100 = 15 bits 0y101 = 16 bits Other = Reserved [2:0] column_bits R/W 0y000 The number of column address bits: 0y000 = 8 bits 0y001 = 9 bits 0y010 = 10 bits 0y011 = 11 bits 0y100 = 12 bits Other = Reserved [Description] a. <memory_burst> Set the read/write access burst length for the controller. You must program this value to match the memory burst length set in dmc_direct_cmd_3. Note: When you use SDRAM of 32bit bus, it can not be set to Burst 16. TMPA910CRA- 218 2010-06-02 TMPA910CRA b. <stop_mem_clock> The clock supply to the SDRAM can be stopped while it is not being accessed. When an SDRAM access request occurs again, the clock is automatically restarted. Note 1: Depending on the SDRAM type, it may not be possible to stop the clock supply to the SDRAM while it is not being accessed. When using this function, be sure to carefully check the specifications of the SDRAM to be used. Note 2: The memory clock stop function and the SDRAM auto powerdown function cannot be used concurrently. Use only either of the two. c. <auto_power_down> When no SDRAM access request is present and the command FIFO of the memory controller becomes empty, the SDRAM can be placed into Powerdown mode by automatically disabling CKE after the number of clock cycles specified in the power_down_prd field. When an SDRAM access request occurs again, CKE is automatically enabled to exit the Powerdown mode. Note: The memory clock stop function and the SDRAM auto powerdown function cannot be used concurrently. Use only either of the two. d. <row_bits>, <column_bits> These bits set the row and column addresses. Supported selectable memory is limited by the summation of column address and row address. In case of 32bit bus, less than R+C=25 bits (128Mbytes) then 512Mbytes for 4 banks In case of 16bit bus, less than R+C=26 bits (128Mbytes) then 512Mbytes for 4 banks TMPA910CRA- 219 2010-06-02 TMPA910CRA 5. dmc_refresh_prd_3 (DMC Refresh Period Register) Address = (0xF430_0000) + (0x0010) Bit Bit Symbol Type Reset Description Value [31:15] - - Undefined [14:0] refresh_prd R/W 0x0A60 Read as undefined. Write as zero. Auto-refresh cycle (number of memory clocks): 0x0000 to 0x7FFF [Description] a. <refresh_prd> The value of the refresh counter decrements from the value set in the dmc_refresh_prd_3 (the number of Memory clocks), and when the counter reaches zero, auto-refresh requests are occured to external memory. DMCSCLK Auto Auto-refresh DMCSDQMx Auto-refresh Auto-refresh DMCSCSn DMCRASn DMCCASn DMCWEn Figure 3.10.3 Auto-refresh Cycles Operation Example TMPA910CRA- 220 2010-06-02 TMPA910CRA 6. dmc_cas_latency_3 (DMC CAS Latency Register) Address = (0xF430_0000) + (0x0014) Bit Bit Symbol Type Reset Description Value [31:4] - - Undefined Read as undefined. Write as zero. [3:1] cas_latency R/W 0y011 CAS latency setting (number of memory clocks): [0] - - Undefined 0y000 to 0y111 Read as undefined. Write as zero. [Description] a. <cas_latency> CAS latency setting (number of memory clocks): 0y000 to 0y111 DMCSCLK CAS latency READ command Data access DMCSDQMx DMCSCSn DMCRASn DMCCASn READ CMD 1'st Access DMCWEn A0 to A15 DMCAP D0 to D31 Figure 3.10.4 CAS Latency Example (CL = 2) TMPA910CRA- 221 2010-06-02 TMPA910CRA 7. dmc_t_dqss_3 (DMC t_dqss Register) Address = (0xF430_0000) + (0x0018) Bit Bit Symbol Type Reset Description Value [31:2] - - Undefined Read as undefined. Write as zero. [1:0] t_dqss R/W 0y01 DQS setting (number of memory clocks) In the initial state (before operation), fix to 0y00 [Description] * The DQS signal is not available in MPMC0. <t_dqss> must be set to 0y00 in initial setting. TMPA910CRA- 222 2010-06-02 TMPA910CRA 8. dmc_t_mrd_3 (DMC t_mrd Register) Address = (0xF430_0000) + (0x001C) Bit Bit Symbol Reset Type Description Value [31:7] - - Undefined [6:0] t_mrd R/W 0y0000010 Read as undefined. Write as zero. Mode register command time (Number of memory clocks): 0x00 to 0x7F [Description] a. <t_mrd> Set time (memory clocks) from mode register dmc_direct_cmd_3<addr_13_to_0>) to other command: 0x00 to 0x7F * command (set by Depending on other AC settings and operations, the actual delay time may be longer than the specified time. Set the minimum number of clocks in this register. DMCSCLK Command time cycle Mode register command command DMCSDQMx DMCSCSn DMCRASn Command Register SET Any CMD DMCCASn DMCWEn A0 to A15 DMCAP Figure 3.10.5 Example of transition from mode register write to other commands TMPA910CRA- 223 2010-06-02 TMPA910CRA 9. dmc_t_ras_3 (DMC t_ras Register) Address = (0xF430_0000) + (0x0020) Bit Bit Symbol Reset Type Description Value [31:4] - - Undefined [3:0] t_ras R/W 0x7 Read as undefined. Write as zero. Time between RAS and Precharge (number of memory clocks): 0x0 to 0xF [Description] a. <t_ras> Time between RAS and Precharge (number of memory clocks): 0x0 to 0xF * Depending on other AC settings and operations, the actual delay time may be longer than the specified time. Set the minimum number of clocks in this register. DMCSCLK RAS-Precharge period RAS Precharge DMCSDQMx DMCSCSn DMCRASn RAS ACTIVE Pre Charge DMCCASn DMCWEn A0 to A15 DMCAP Figure 3.10.6 Time from Active to Precharge TMPA910CRA- 224 2010-06-02 TMPA910CRA 10. dmc_t_rc_3 (DMC t_rc Register) Address = (0xF430_0000) + (0x0024) Bit Bit Type Symbol Reset Description Value [31:4] - - Undefined [3:0] t_rc R/W 0y1011 Read as undefined. Write as zero. Delay between Active bank A and next Active bank A(Number of memory clocks) 0x0 to 0xF [Description] a. <t_rc> The delay time from Active bank command to Active bank command in the same BANK. (memory clocks) 0x0 to 0xF * Depending on other AC settings and operations, the actual delay time may be longer than the specified time. Set the minimum number of clocks in this register. DMCSCLK ACTIVE-ACTIV DMCSDQMx ACTIVE ACTIVE DMCSCSn DMCRASn ACT ACT BANK A BANK A DMCCASn DMCWEn A0~A15 DMCAP BA[1:0] Figure 3.10.7 Delay Time between Two Successive Active Bank As TMPA910CRA- 225 2010-06-02 TMPA910CRA 11. dmc_t_rcd_3 (DMC t_rcd Register) Address = (0xF430_0000) + (0x0028) Bit Bit Symbol Type Reset Description Value [31:6] - - Undefined Read as undefined. Write as zero. [5:3] schedule_rcd R/W 0y011 Set min delay from RAS to CAS. [2:0] t_rcd R/W 0y101 Set to (t_rcd setting value -3) Set min delay from RAS to CAS. (Number of memory clocks): 0y000 to 0y111 [Description] a. <schedule_rcd> Set min delay from RAS to CAS. Set to (t_rcd setting value -3). b. <t_rcd> Set min delay from RAS to CAS (number of memory clocks): 0y000 to 0y111 DMCSCLK RAS-CAS time RAS CAS DMCSDQMx DMCSCSn DMCRASn ACTIVE CMD DMCCASn R/W CMD DMCWEn A0~A15 DMCAP Figure 3.10.8 Time from Active to read command TMPA910CRA- 226 2010-06-02 TMPA910CRA 12. dmc_t_rfc_3 (DMC t_rfc Register) Address = (0xF430_0000) + (0x002C) Bit Bit Symbol Type Reset Description Value [31:10] - - Undefined Read as undefined. Write as zero. [9:5] schedule_rfc R/W 0y10000 Autorefresh command time setting [4:0] t_rfc R/W 0y10010 Set to (t_rfc setting value -3) Autorefresh command time setting (Number of memory clocks) 0y00000 to 0y11111 [Description] a. <schedule_rfc> Autorefresh command time setting. Set to (t_rfc setting value -3). b. <t_rfc> Autorefresh command time setting (Number of memory clocks): 0y00000 to 0y11111 DMCSCLK Command time cycle Autorefresh Command Command DMCSCSn DMCRASn Auto Refresh CMD Any CMD DMCCASn DMCWEn A0 to A15 DMCAP Figure 3.10.9 Time from Autorefresh Command to Other Command TMPA910CRA- 227 2010-06-02 TMPA910CRA 13. dmc _t_rp_3 (DMC t_rp Register) Address = (0xF430_0000) + (0x0030) Bit Bit Symbol Reset Type Description Value [31:6] - - Undefined Read as undefined. Write as zero. [5:3] schedule_rp R/W 0y011 Precharge delay setting to RAS. Set to (t_rp setting value -3). [2:0] t_rp R/W 0y101 Set the time from Precharge to RAS (number of memory clocks): 0y000 to 0y111 [Description] a. <schedule_rp> Set the time from Precharge to RAS. Set to (t_rp setting value -3). c. <t_rp> Set the time from Precharge to RAS (number of memory clocks): 0y000 to 0y111 DMCSCLK Precahrge-RAS time Precharge RAS DMCSDQMx DMCSCSn DMCRASn Pre Charge RAS ACTIVE DMCCASn DMCWEn A0 to A15 DMCAP Figure 3.10.10 Time from Precharge to Other Command (including Autorefresh) TMPA910CRA- 228 2010-06-02 TMPA910CRA 14. dmc_t_rrd_3 (DMC t_rrd Register) Address = (0xF430_0000) + (0x0034) Bit Bit Symbol Type Reset Description Value [31:4] - - Undefined [3:0] t_rrd R/W 0y0010 Read as undefined. Write as zero. Delay time from Active bank A to Active bank B (Number of memory clocks): 0x0 to 0xF [Description] a. <t_rrd> Delay time from Active bank A to Active bank B (number of memory clocks): 0x0 to 0xF DMCSCLK ACTIVE-ACTIVE time ACTIVE ACTIVE DMCSDQMx DMCSCSn DMCRASn ACT ACT BANK A BANK B DMCCASn DMCWEn A0 to A15 DMCAP BA[1:0] Figure 3.10.11 Time between Active bank A and other Active bank B TMPA910CRA- 229 2010-06-02 TMPA910CRA 15. dmc_t_wr_3 (DMC t_wr Register) Address = (0xF430_0000) + (0x0038) Bit Bit Symbol Type Reset Description Value [31:3] - - Undefined [2:0] t_wr R/W 0y011 Read as undefined. Write as zero. Delay from the last write data to Precharge (Number of memory clocks): 0y000 to 0y111 [Description] a. <t_wr> Delay from the last write data to Precharge (number of memory clocks). Actual time (memory clocks): <t_wr> + 1. When <t_wr> = 0y000, actual time (memory clocks) = 9 memory clocks. DMCSCLK DMCSDQMx DMCSCSn Write Command Precharge Write data Precharge DMCRASn DMCCASn DMCWEn t_wr (Single transfer) D31~D0 (single transfer) t_wr (Burst transfer) D31~D0 (Burst transfer) DMCAP Figure 3.10.12 Time between Last Data of Write and Precharge TMPA910CRA- 230 2010-06-02 TMPA910CRA 16. dmc_t_wtr_3 (DMC t_wtr Register) Address = (0xF430_0000) + (0x003C) Bit Bit Type Symbol Reset Description Value [31:3] - - Undefined [2:0] t_wtr R/W 0y010 Read as undefined. Write as zero. Setting value from the last write data to read command (memory clocks) 0y000 to 0y111 [Description] a. <t_wtr> Delay from the last write data to read command (memory clocks). When <t_wtr> = 0y000, actual time (memory clocks) = 8 memory clocks. DMCSCLK DMCSDQMx Write Command Read Command DMCSCSn DMCRASn Write data Read Command DMCCASn DMCWEn t_wtr (Single transfer) D31 to D0 (single transfer) t_wtr (Burst transfer) D31 to D0 (burst transfer) DMCAP Figure 3.10.13 Time between Last data of write and Read command TMPA910CRA- 231 2010-06-02 TMPA910CRA 17. dmc _t_xp_3 (DMC t_xp Register) Address = (0xF430_0000) + (0x0040) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] t_xp R/W 0x01 Set the exit power-down command time (Number of memory clocks) 0x00 to 0xFF [Description] a. <t_xp> Time between Powerdown Exit command and other command (memory clocks) Actual time (memory clocks): <t_xp> + 1 DMCSCLK DMCSDQMx t_xp DMCSCSn Powerdown Exit command command DMCRASn Any CMD DMCCASn DMCWEn A0 to A15 DMCCKE Powerdown Exit Figure 3.10.14 Time between Powerdown Exit Command and Other Command TMPA910CRA- 232 2010-06-02 TMPA910CRA 18. dmc_ t_xsr_3 (DMC t_xsr Register) Address = (0xF430_0000) + (0x0044) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] t_xsr R/W 0x0A Time from Self-refresh Exit command to other command (memory clocks) 0x00 to 0xFF [Description] a. <t_xsr> Time from Self-refresh Exit command to other command (memory clocks) DMCSCLK DMCSDQMx t_xsr DMCSCSn Self-refresh Exit command command DMCRASn Any CMD DMCCASn DMCWEn A0 to A15 DMCCKE Self-Refresh Exit Figure 3.10.15 Time between Self-refresh Exit command and other command TMPA910CRA- 233 2010-06-02 TMPA910CRA 19. dmc_t_esr_3 (DMC t_esr Register) Address = (0xF430_0000) + (0x0048) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7:0] t_esr R/W 0x14 Read as undefined. Write as zero. The minimum time from Self-refresh Entry to Exit: (memory clocks) 0x00 to 0xFF Note: Self-refersh Exit have to use Wakeup direct command ,this register is only to set the the minimum time from Self-refresh Entry to Exit [Description] a. <t_esr> The minimum time from Self-refresh Entry to Exit (memory clocks) 0x00 to 0xFF DMCSCLK DMCSDQMx Self-refresh Entry commnad Self-refresh Exit commnad DMCSCSn DMCRASn DMCCASn DMCWEn t_esr A0 to A15 DMCCKE Figure3.10.16 Minimum execution time between Self-refresh Entry and Exit TMPA910CRA- 234 2010-06-02 TMPA910CRA 20. dmc_id_<0-3>_cfg_3 Registers Address = (0xF430_0000) + (0x0100) Address = (0xF430_0000) + (0x0104) Address = (0xF430_0000) + (0x0108) Address = (0xF430_0000) + (0x010C) Bit Bit Type Symbol Reset Description Value [31:10] - - Undefined Read as undefined. Write as zero. [9:2] qos_max R/W 0x00 maximum QoS: [1] qos_min R/W 0y0 minimum QoS selection: 0x00 0xFF 0y0 = QoS max mode 0y1 = QoS min mode [0] qos_enable R/W 0y0 Enable QoS 0y0 = Disable 0y1 = Enable [Description] QoS setting register list Register Address Correspond to AHB dmc_id_0_cfg_3 (0xF430_0000) + (0x0100) dmc_id_1_cfg_3 (0xF430_0000) + (0x0104) AHB0 : CPU Data AHB1 : CPU Inst dmc_id_2_cfg_3 (0xF430_0000) + (0x0108) AHB2 : LCDC dmc_id_3_cfg_3 (0xF430_0000) + (0x010C) AHB3 : multilayer bus matrix2 (LCDDA,USB,DMAC1,DMAC2) a. <qos_max> QoS maximum value setting: 0x00 to 0xFF b. <qos_min> Minimum QoS selection: 0y0 = QoS max mode 0y1 = QoS min mode, QoS minimum has priority over QoS maximum. c. <qos_enable> Enable QoS: 0y0 = Disable 0y1 = Enable TMPA910CRA- 235 2010-06-02 TMPA910CRA 21. dmc_chip_0_cfg_3 (DMC chip_0_cfg Registers) Address = (0xF430_0000) + (0x0200) Bit Bit Symbol Type Reset Description Value [31:17] - - Undefined [16] brc_n_rbc R/W 0y0 Read as undefined. Write as zero. SDRAM address structure: 0y0 = row, bank, column 0y1 = bank, row, column [15:8] address_match R/W 0xFF Set the start address [31:24]: 0x00 to 0xFF [7:0] address_mask R/W 0x00 Set the mask value of the start address [31:24]: The bit for the value 1 is a bit for address comparison 0x00 to 0xFF [Description] a. <brc_n_rbc> SDRAM address structure: 0y0 = row, bank, column 0y1 = bank, row, column b. <address_match> Set the start address [31:24]. Do not access DMC area (Not used) except for configured CS area, if you accessed to memory less than 512 MB. Note: When you set the start address, refer to the section 3.3 Memory Map, and confirm valid areas. c. <address_mask> Set the CS areas. Determine which bit in the start address should be or should not be compared. 0y0 = Not compare 0y1 = Compare TMPA910CRA- 236 2010-06-02 TMPA910CRA 22. dmc_user_config_3 (DMC user_config Register) Address = (0xF430_0000) + (0x0304) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] Reserved - Undefined Read as undefined. Write as zero. [6:4] dmclk_out1 WO 0y000 SDR SDRAM constant value setting: [3:1] Reserved - Undefined Read as undefined. Write as zero. [0] sdr_width WO 0y0 Set the memory data bus width of corresponding Read as undefined. Write as zero. must fix to 0y001 external SDR memory: 0y0: 16-bit 0y1: 32-bit [Description] a. <sdr_width> Set the memory data bus width of corresponding external SDR memory: 0y0 = 16-bit 0y1 = 32-bit TMPA910CRA- 237 2010-06-02 TMPA910CRA 3.10.3.2 SMC (Static Memory Controller) This device contains SMC (Static Memory Controller) that controls the external memory (NOR Flash memory, Mask ROM SRAM and etc.). (1) SMC function outline Table 3.10.6 shows features of SMC. Table 3.10.6 Features of SMC Features Support memory External Static memory (NOR Flash memory and SRAM, etc.) Support separate bus only Data bus width 16bit/32bit data bus width Access areas 4 areas supported by Chip select. Max access area: SMCCS0n: 512 MB SMCCS1n: 512 MB SMCCS2n: 512 MB SMCCS3n: 256 MB Timing adjustment Adjustable AC timing by register Support external wait request (only in Synchronous mode) Clock Selectable clock for external pin (fHCLK or fHCLK /2) by the clock controller register CLKCR5<SEL_SMC_MCLK> External control pin D31 to D0, A25 to A0, SMCBE0n, SMCBE1n, SMCBE2n, SMCBE3n, SMCCS0n, SMCCS1n, SMCCS2n, SMCCS3n, SMCOEn,SMCWEn, SMCCLK , SMCWAITn, SMCAVDn TMPA910CRA- 238 2010-06-02 TMPA910CRA (2) SMC block diagram Figure 3.10.17 is a SMC block diagram. Memory Domain AHB Domain APB slave Memory I/F Manager EBI I/F Arbiter Memory I/F PAD I/F SRAM memory I/F SMC I/F Figure 3.10.17 SMC block diagram (a) Arbiter The Arbiter receives accesses from the SMC I/F and memory manager. Read/Write requests are arbitrated on a Round-Robin basis. Requests from the manager have the highest priority. (b) Memory manager Updates timing registers and controls commands issued to memory TMPA910CRA- 239 2010-06-02 TMPA910CRA (3) SMC Function (a) APB slave I/F The APB slave I/F adds a wait state for all reads and writes More than one wait state is generated in the following case: Outstanding direct commands A memory command is received, but the previous memory command has not been completed. (b) Format 1. Hazard processing When selfsame stand-alone bus master access to an external memory, the actual access procedure to memory is executed in the instruction order. However, if multiple bus master access to an external memory, the read and write data will be stored temporary into independent buffer and be executing by priority circuit. Therefore, the read and the write instruction may switch execution sequence. So please coordinate a variety of sequences, e.g. making an enough time for next instruction, checking whether or not previous execution is finished, the common-use memory data uses the internal memory and so on. 2. Access to the SRAM memory * Standard SRAM access * Memory address shifting * Memory burst alignment The burst align settings are necessary in order to support asynchronous page mode memory. Refer to SMC register of MPMC, smc_set_opmode_3 (SMC Set Opmode Register) Note: In case of not having any page mode methods, e.g. NOR Flash, it is unnecessary to set burst align. Memory burst length: Supported memory burst transfer length is 4 beats. TMPA910CRA- 240 2010-06-02 TMPA910CRA (c) Memory manager operation The memory manager controls the SMC state and manages update of chip configuration registers. (d) Memory I/F operation The memory I/F issues commands and controls their timings. Table 3.10.7 Static Memory Setup Example Base address = 0xF430_1000 Register address Write data Description 0x0014 0x00029266 smc_set_cycles_3 0x0018 0x00000809 smc_set_opmode_3 0x0010 0x00400000 smc_direct_cmd_3 TMPA910CRA- 241 2010-06-02 TMPA910CRA (4) SMC Registers for MPMC0 Table 3.10.8 MPMC0 SMC SFR list base address = 0xF430_1000 Register Address Name (base+) Type Reset value Description Reserved 0x0000 - Undefined Read undefined. Write as zero.. Reserved 0x0004 - Undefined Read undefined. Write as zero. Reserved 0x0008 - - Write prohibited Reserved 0x000C - - Write prohibited smc_direct_cmd_3 0x0010 WO - SMC Direct Command Register smc_set_cycles_3 0x0014 WO - SMC Set Cycles Register smc_set_opmode_3 0x0018 WO - SMC Set Opmode Register Reserved 0x0020 - Undefined Read undefined. Write as zero. smc_sram_cycles0_0_3 0x0100 smc_sram_cycles0_1_3 0x0120 smc_sram_cycles0_2_3 0x0140 RO 0x0002B3CC SMC SRAM Cycles Registers <0-3> smc_sram_cycles0_3_3 0x0160 smc_opmode0_0_3 0x0104 smc_opmode0_1_3 0x0124 smc_opmode0_2_3 0x0144 smc_opmode0_3_3 0x0164 0x20E00802 RO 0x60E00802 0xA0E00802 SMC Opmode Registers <0-3> 0xE0E00802 Reserved 0x0200 - Undefined Read undefined. Write as zero. Reserved 0x0204 - Undefined Read undefined. Write as zero. Reserved 0x0E00 - Undefined Read undefined. Write as zero. Reserved 0x0E04 - Undefined Read undefined. Write as zero. Reserved 0x0E08 - Undefined Read undefined. Write as zero. Reserved 0x0FE0-0x0FEC - Undefined Read undefined. Write as zero. Reserved 0x0FF0-0x0FFC - Undefined Read undefined. Write as zero. Note: The APB supports only single-word 32-bit accesses. Read from or write to registers at single-word 32-bit mode. TMPA910CRA- 242 2010-06-02 TMPA910CRA 1. smc_direct_cmd_3 (SMC Direct Command Register) Address = (0xF430_1000) + (0x0010) Bit Bit Symbol Reset Type Description Value [31:26] [25:23] - chip_select - WO Undefined - Read as undefined. Write as zero. CS selection: 0y000 = CS0 0y001 = CS1 0y010 = CS2 0y011 = CS3 0y100 to 0y111 = Reserved [22:21] cmd_type WO - Current command: 0y00 = Reserved 0y01 = Reserved 0y10 = UpdateRegs 0y11 = Reserved [20:0] - - Undefined Reserved [Description] a. <chip_select> Intended CS selection for updating: 0y000 = CS0 0y001 = CS1 0y010 = CS2 0y011 = CS3 0y100 to 0y111 = Reserved b. <cmd_type> Update method: 0y00 = Reserved 0y01 = Reserved 0y10 = UpdateRegs 0y11 = Reserved TMPA910CRA- 243 2010-06-02 TMPA910CRA Start Set smc_set_cycle register as timing parameter and set smc_set_opmode as operation mode Select the external ChipSelect and smc_direct_cmd register then updating set END TMPA910CRA- 244 2010-06-02 TMPA910CRA 2. smc_set_cycles_3 (SMC Set Cycles Register) Address = (0xF430_1000) + (0x0014) Bit Bit Symbol Reset Type Description Value [31:23] - - Undefined Read as undefined. Write as zero. [22:20] Reserved - Undefined Read as undefined. Write as zero. [19:17] Set_t5 WO - Set value of tTR (holding register) 0y000 to 0y111 [16:14] Set_t4 WO - Set value of tPC (holding register) 0y000 to 0y111 [13:11] Set_t3 WO - Set value of tWP (holding register) 0y000 to 0y111 [10:8] Set_t2 WO - Set value of tCEOE (holding register) 0y000 to 0y111 [7:4] Set_t1 WO - Set value of tWC (holding register) 0y0000 to 0y1111 [3:0] Set_t0 WO - Set value of tRC (holding register) 0y0000 to 0y1111 This register is provided to adjust the access cycle of static memory and should be set to satisfy the A.C. specifications of the memory to be used. If the wait signal by an external pin is also used, the access cycle is determined to satisfy the settings of both this register and the external wait signal. Note that the external wait signal is only effective in synchronous mode. It cannot be used in asynchronous mode. This is a holding register for enabling setting values. By executing of the following operations, the settings values of this register will be updated to the configuration register of the memory manager and enabled. The smc_direct_cmd Register indicates only a register update is taking place. [Description] a. <Set_t5> Set value of tTR (holding register). 0y000 to 0y111 b. <Set_t4> Set value of tPC (holding register). 0y000 to 0y111 c. <Set_t3> Set value of tWP (holding register). 0y000 to 0y111 d. <Set_t2> Set value of tCEOE (holding register). 0y000 to 0y111 TMPA910CRA- 245 2010-06-02 TMPA910CRA e. <Set_t1> Set value of tWC (holding register). 0y0000 to 0y1111 f. <Set_t0> Set value of tRC (holding register). 0y0000 to 0y1111 Example of setting timing Setting Example: SMC Set Cycles Register = 0x0002B1C3 Register setting value 0x0002B1C3 tPC tTR tWP tCEOE 1 TWC tRC 3 don't care smcclk (Internal clock) tRC SMCCS0n SMCOEn tCEOE SMCWEn A[25:0] D[31:0] Addr Data XXXX Figure 3.10.18 XXXX Asynchronous Read TMPA910CRA- 246 2010-06-02 TMPA910CRA Setting Example: SMC Set Cycles Register = 0x0002934C Register setting value 0x0002934C tTR tPC tWP 2 tCEOE TWC 4 tRC don't care smcclk (Internal clock) tWC SMCCS0n SMCOEn tWP SMCWEn Addr A[25:0] D[31:0] XXXX XXXX Data BE[0:3]n Figure 3.10.19 Asynchronous Write Setting Example: SMC Set Cycles Register = 0x000272C3 Register setting value 0x000272C3 tTR tPC 1 smcclk (Internal clock) tRC SMCCS0n SMCOEn tWP tCEOE 2 tPC TWC tRC 3 don't care tPC tPC tCEOE SMCWEn D[31:0] XXXX D A+3 A+2 A+1 A D+1 D+2 A[25:0] D+3 Figure 3.10.20 Asynchronous Page Read TMPA910CRA- 247 2010-06-02 TMPA910CRA Setting Example: SMC Set Cycles Register = 0x00029143 Register setting value 0x00029143 tPC tTR 1 tWP 2 tCEOE 1 TWC 4 tRC 3 don't care smcclk (Internal clock) SMCCS0n tTR SMCOEn SMCWEn D[31:0] Addr2 Addr1 A[25:0] XXXX D1 XXXX D2 Figure 3.10.21 Asynchronous Write after Asynchronous Read TMPA910CRA- 248 2010-06-02 TMPA910CRA 3. smc_set_opmode_3 (SMC Set Opmode Register) Address = (0xF430_1000) + (0x0018) Bit Bit Symbol Reset Type Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15:13] set_burst_align WO - Memory burst boundary split setting: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] set_bls WO - Byte Enable (SMCBE0-3) timing setting: 0y0 = SMCCSn timing 0y1 = SMCWEn timing [11] set_adv WO - Address valid (adv) field set value 0y0 = Memory address valid signal SMCAVDn not used 0y1 = Memory address valid signal SMCAVDn used [10] - - Undefined Read undefined. Write as zero. [9:7] set_wr_bl WO - Write burst length 0y000 = 1 beat 0y001 = 4 beats other = Reserved [6] set_wr_sync WO - Write synchronization mode setting: 0y0 = asynchronous write mode 0y1 = synchronous write mode [5:3] set_rd_bl WO - Read burst length 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] set_rd_sync WO - Read synchronization mode setting: 0y0 = asynchronous read mode 0y1 = synchronous read mode [1:0] set_mw WO - Holding register of the memory data bus width set value: 0y00 = Reserved 0y01 = 16 bits 0y10 = 32 bits 0y11 = Reserved This is a holding register for enabling setting values. By executing of the following operations, the settings values of this register will be updated to the configuration register of the memory manager and enabled. The smc_direct_cmd Register indicates only a register update is taking place. [Description] a. < set_burst_align > Memory burst boundary split setting: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved TMPA910CRA- 249 2010-06-02 TMPA910CRA b. < set_bls > Byte Enable (SMCBE0-3) timing setting: 0y0 = SMCCSn timing 0y1 = SMCWEn timing c. < set_adv > Address valid (adv) field set value 0y0 = Memory address valid signal SMCAVDn not used 0y1 = Memory address valid signal SMCAVDn used d. < set_wr_bl > Write burst length 0y000 = 1 beat 0y001 = 4 beats other = Reserved e. < set_wr_sync > Write synchronization mode setting: 0y0 = asynchronous write mode 0y1 = synchronous write mode f. < set_rd_bl > Read burst length 0y000 = 1 beat 0y001 = 4 beats other = Reserved g. < set_rd_sync > Read synchronization mode setting: 0y0 = asynchronous read mode 0y1 = synchronous read mode h. < set_mw > Holding register of the memory data bus width set value: 0y00 = Reserved 0y01 = 16 bits 0y10 = 32 bits 0y11 = Reserved TMPA910CRA- 250 2010-06-02 TMPA910CRA 4. smc_sram_cycles0_0_3 (SMC SRAM Cycles Registers 0 <0>) Address = (0xF430_1000) + (0x0100) Bit Bit Symbol Type Reset Description Value [31:20] - - Undefined [19:17] t_tr RO 0y001 Read as undefined. Write as zero. Turnaround time for SRAM chip configuration 0y000 to 0y111 [16:14] t_pc RO 0y010 page cycle time: 0y000 to 0y111 [13:11] t_wp RO 0y110 delay time for smc_we_n_0: 0y000 to 0y111 [10:8] t_ceoe RO 0y011 delay time for smc_oe_n_0: 0y000 to 0y111 [7:4] t_wc RO 0y1100 write cycle time: 0y0000 to 0y1111 [3:0] t_rc RO 0y1100 read cycle time: 0y0000 to 0y1111 [Description] a. <t_tr> Turnaround time for SRAM chip configuration: 0y000 to 0y111 b. <t_ pc> Page cycle time: 0y000 to 0y111 c. <t_wp> Delay time for s smc_we_n_0: 0y000 to 0y111 d. <t_ceoe> Delay time for smc_oe_n_0: 0y000 to 0y111 e. <t_wc> Write cycle time: 0y0000 to 0y1111 f. <t_rc> Read cycle time: 0y0000 to 0y1111 * smc_sram_cycles0_x_3 (SMC SRAM Cycles Registers 0 <x>) (x = 0 to 3) The structure and description of these registers are same as smc_sram_cycles0_0_3. Please refer to the description of smc_sram_cycles0_0_3. The name and address of these registers, please refer to Table 3.10.8 MPMC0 SMC SFR list. TMPA910CRA- 251 2010-06-02 TMPA910CRA 5. smc_opmode0_0_3 (SMC Opmode Registers 0<0>) Address = (0xF430_1000) + (0x0104) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0x20 Read as 0x20. [23:16] Reserved RO 0xE0 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined Read undefined. [9:7] wr_bl RO 0y000 Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved TMPA910CRA- 252 2010-06-02 TMPA910CRA 6. smc_opmode0_1_3 (SMC Opmode Registers 0 <1>) Address = (0xF430_1000) + (0x0124) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0x60 Read as 0x60. [23:16] Reserved RO 0xE0 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined Read undefined. [9:7] wr_bl RO 0y000 Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved TMPA910CRA- 253 2010-06-02 TMPA910CRA 7. smc_opmode0_2_3 (SMC Opmode Registers 0 <2>) Address = (0xF430_1000) + (0x0144) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0xA0 Read as 0xA0. [23:16] Reserved RO 0xE0 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined Read undefined. [9:7] wr_bl RO 0y000 Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved TMPA910CRA- 254 2010-06-02 TMPA910CRA 8. smc_opmode0_3_3 (SMC Opmode Registers 0 <3>) Address = (0xF430_1000) + (0x0164) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0xE0 Read as 0xE0. [23:16] Reserved RO 0xE0 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined Read undefined. [9:7] wr_bl RO 0y000 Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved [Description] a. <burst_align> Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary Other = Reserved TMPA910CRA- 255 2010-06-02 TMPA910CRA b. <bls> It shows the timing of bls (byte-lane strobe) output. 0y0 = chip select 0y1 = Reserved c. <adv> Use address Advance signal (address valid) 0y1 = use address Advance signal d. <wr_bl> Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats Other = Reserved e. <wr_sync> Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation f. <rd_bl> Read memory burst length: 0y000 = 1-beat 0y001 = 4-beats Other = Reserve g. <rd_sync> Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation h. <mw> Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved TMPA910CRA- 256 2010-06-02 TMPA910CRA 3.10.4 Overview of MPMC1 MPMC1 contains both a DMC (Dynamic Memory Controller) that controls SDRAM and SMC (Static Memory Controller) that controls NOR Flash and SRAM. Features of a DMC (Dynamic Memory Controller): (a) Supports 16-bit DDR SDRAM(only supports LVCMOS type memory I/O power) (b) Supports 1 channel Chip Select signal (c) Supports adjusting function in each clock for SDRAM each timing. Features of an SMC (Static Memory Controller): (a) Supports synchronous and asynchronous, 32-bit/16-bit SRAM and NOR Flash (only separate buses are supported, and multiplex buses are not supported) (b) Supports 4-channels Chip Select signals (c) Cycle timings and memory data bus widths can be programmed for each Chip Select signal TMPA910CRA- 257 2010-06-02 TMPA910CRA 3.10.5 Function of MPMC 1 Figure 3.10.22 is a simplified block diagram of MPMC1 circuits. MPMC1 M CPU Data AHB0 interface M S CPU Inst AHB1 interface M S LCDC AHB2 interface M S S DMC APB S M S SMC DDR 1 chip SRAM/NOR 4chips APB S Multi layer USB Bus matrix 2 Busmatrix LCDDA AHB3 interface M S M Round Robin DMAC1 AHB4 interface M DMAC2 AHB5 interface M M AHB to APB bridge S AHB Figure 3.10.22 MPMC1block diagram TMPA910CRA- 258 2010-06-02 TMPA910CRA (a) Bus matrix 1. Bus matrix of AHB0, AHB1, AHB2, AHB3, AHB4 and AHB5 supports Round-Robin arbitration scheme. The following diagram shows the priority of bus requests. CPU Inst (AHB0) bus request CPU Data (AHB1) bus request LCDC (AHB2) bus request AHB3 bus request (Bus request from the bus matrix output of LCDDA2, USB) DMAC1 (AHB4) bus request DMAC2 (AHB5) bus request AHB0 AHB1 AHB2 AHB3 AHB4 handling handling handling handling handling handling AHB5 AHB0 handling A dotted line is the point of handling end where bus is released. Priority of handling : TMPA910CRA- 259 2010-06-02 TMPA910CRA 2. Bus matrix 2 of LCDDA and USB handles the earliest bus request first. If multiple bus requests are accepted simultaneously, they are handled according to hardware priority. Hardware priority is shown following Hardware priority is shown following LCDDA (high) C1 USB (low) LCDDAbus request USB bus request LCDDA USB handling handling LCDDA USB handling handling A dotted line is the point of handling end, where bus is released. Handling priority : (b) Clock Variety Control clock is controlled in PLLCG circuit: 1. Dynamic memory clock: Use HCLK clock 2. Static memory clock: Use HCLK or 1/2 HCLK TMPA910CRA- 260 2010-06-02 TMPA910CRA 3.10.5.1 DMC (Dynamic Memory Controller) (1) DMC block diagram AHB Domain APB Domain APB I/F Memory Manager APB Slave I/F Memory Domain Arbiter EBI I/F Memory I/F DMC I/F PAD I/F Figure 3.10.23 External memory I/F DMC block diagram (a) Arbiter The arbiter receives access commands from the DMC I/F and the memory manager, and after access arbitration, it passes the highest priority command to the memory I/F. Data is read from the memory I/F to the DMC I/F. (b) Memory manager The memory manager monitors and controls the DMC current. TMPA910CRA- 261 2010-06-02 TMPA910CRA (2) DMC Function operation (a) Arbiter operation 1. read/write access arbitration 2. For read accesses, QoS (Quality of Service) is provided. 3. Hazard processing When selfsame stand-alone bus master access to an external memory, the actual access procedure to memory is executed in the instruction order. However, if multiple bus master access to an external memory, the read and write data will be stored temporary into independent buffer and be executing by priority circuit. Therefore, the read and the write instruction may switch execution sequence. So please coordinate a variety of sequences, e.g. making an enough time for next instruction, checking whether or not previous execution is finished, the common-use memory data uses the internal memory and so on. 4. Monitoring the state machine and select an entry of the proper pipeline. (b) Memory manager operation 1. Monitor and control DMC circuit 2. Issuing direct comand * NOP * Prechargeall * Autorefresh * Modereg * Extended modereg 3. Auto Refresh function is provided Set Auto Refresh timing by 15bit counter. (c) Memory interface operation According to use, there are three kinds of built-in FIFOs. 1. command FIFO: 2 words 2. read data FIFO:10 words 3. write data FIFO:10 words * As the FIFO sizes of either read or write FIFO is 10 words. For one transfer, the max size is 8 words. (d) Low Power function DMC provide 2 kinds of Low Power modes. 1. Set dmc_memc_cmd_3 register to realize Low_power (Self Refresh Mode). 2. Set dmc_memory_cfg_3 register, stop memory clock (DMCCLK) or as no memory access, CKE is set to invalid (CKE = low). Note: Clock Suspend Mode function and Power Down mode cannot be used concurrently. TMPA910CRA- 262 2010-06-02 TMPA910CRA (e) QoS Function The QoS function is available in read-accessing only. The QoS function is the service function for exception handling at Round-Robin which is controlled by Bus matrix for MPMC. dmc_id_x_cfg_5<qos_max> is set by a register within the DMC on a port by port basis. dmc_id_x_cfg_5<qos_max> indicates a required read maximum latency. A QoS_max timeout causes the transaction to be raised to a higher priority. You can also set dmc_id_x_cfg_5<qos_min> to enable for a specific port so that its transfers are serviced with a higher priority. This impacts the overall memory band width because it limits the options of the scheduling algorithm. TMPA910CRA- 263 2010-06-02 TMPA910CRA Table 3.10.9 Example DDR memory setup Base address = 0xF431_0000 Register address Write data Description 0x0014 0x00000004 Set cas_latency to 2 0x0018 0x00000001 Set t_dqss to 1 0x001C 0x00000002 Sett_mrd to 2 0x0020 0x00000007 Sett_ras to 7 0x0024 0x0000000B Set t_rc to 11 0x0028 0x00000015 Set t_rcd to 5 and schedule_rcdto 2 0x002C 0x000001F2 Set t_rfc to 18 and schedule_rfcto 15 0x0030 0x00000015 Set t_rp to 5 and schedule_rpto 2 0x0034 0x00000002 Set t_rrd to 2 0x0038 0x00000003 Set t_wrto 3 0x003C 0x00000002 Set t_wtr to 2 0x0040 0x00000001 Set t_xp to 1 0x0044 0x0000000A Set t_xsr to 10 0x0048 0x00000014 Set t_esr to 20 0x000C 0x00010009 Set memory configuration 0x0010 0x00000640 Set auto refresh time to be every 1600 DMCSCLK periods 0x0200 0x000000FF Set chip select for chip 0 to be 0x00XXXXXX, rbc configuration 0x0008 0x000C0000 Carry out chip 0 Nopcommand 0x0008 0x00000000 Carry out chip 0 Prechargeall command 0x0008 0x00090000 Extended mode register setup 0x0008 0x00080122 Mode register setup 0x0008 0x00000000 Precharge all 0x0008 0x00040000 Carry out chip 0 Autorefresh command 0x0008 0x00040000 Carry out chip 0 Autorefresh command 0x0008 0x00080032 Carry out chip 0 Mode Reg command 0x32 mapped to low add bits 0x0004 0x00000000 Change DMC state to ready TMPA910CRA- 264 2010-06-02 TMPA910CRA (3) MPMC1 DMC register Table 3.10.10 SFR list Base address = 0xF431_0000 Register Address Name (base+) Type Reset value Description dmc_memc_status_5 0x0000 RO 0x00000390 DMC Memory Controller Status Register dmc_memc_cmd_5 0x0004 WO - DMC Memory Controller Command Register dmc_direct_cmd_5 0x0008 WO - DMC Direct Command Register dmc_memory_cfg_5 0x000C R/W 0x00010020 DMC Memory Configuration Register dmc_refresh_prd_5 0x0010 R/W 0x00000A60 DMC Refresh Period Register dmc_cas_latency_5 0x0014 R/W 0x00000006 DMC CAS Latency Register dmc_t_dqss_5 0x0018 R/W 0x00000001 DMC t_dqss Register dmc_t_mrd_5 0x001C R/W 0x00000002 DMC t_mrd Register dmc_t_ras_5 0x0020 R/W 0x00000007 DMC t_ras Register dmc_t_rc_5 0x0024 R/W 0x0000000B DMC t_rc Register dmc_t_rcd_5 0x0028 R/W 0x0000001D DMC t_rcd Register dmc_t_rfc_5 0x002C R/W 0x00000212 DMC t_rfc Register dmc_t_rp_5 0x0030 R/W 0x0000001D DMC t_rp Register dmc_t_rrd_5 0x0034 R/W 0x00000002 DMC t_rrd Register dmc_t_wr_5 0x0038 R/W 0x00000003 DMC t_wr Register dmc_t_wtr_5 0x003C R/W 0x00000002 DMC t_wtr Register dmc_t_xp_5 0x0040 R/W 0x00000001 DMC t_xp Register dmc_t_xsr_5 0x0044 R/W 0x0000000A DMC t_xsr Register dmc_t_esr_5 0x0048 R/W 0x00000014 DMC t_esr Register dmc_id_0_cfg_5 0x0100 R/W 0x00000000 DMC id_<0-5>_cfg Registers dmc_id_1_cfg_5 0x0104 dmc_id_2_cfg_5 0x0108 dmc_id_3_cfg_5 0x010C dmc_id_4_cfg_5 0x0110 dmc_id_5_cfg_5 0x0114 dmc_chip_0_cfg_5 0x0200 R/W 0x0000FF00 DMC chip_0_cfg Registers Reserved 0x0204 - Undefined Read undefined. Write as zero. Reserved 0x0208 - Undefined Read undefined. Write as zero. Reserved 0x020C - Undefined Read undefined. Write as zero. Reserved 0x0300 - Undefined Read undefined. Write as zero. dmc_user_config_5 0x0304 WO Undefined DMC user_config Register Reserved 0x0E00 - Undefined Read undefined. Write as zero. Reserved 0x0E04 - Undefined Read undefined. Write as zero. Reserved 0x0E08 - Undefined Read undefined. Write as zero. Reserved 0x0FE0-0x0FEC - Undefined Read undefined. Write as zero. Reserved 0x0FF0-0x0FFC - Undefined Read undefined. Write as zero. Note: The APB supports only single-word 32-bit accesses. Read from or write to registers at single-word 32-bit mode. TMPA910CRA- 265 2010-06-02 TMPA910CRA MPMC1 The permission status of Register Read/Write access (dmc_memc_status_5 status) : permitted Register Name x: prohibited Type Read Write dmc_memc_status_5 dmc_memc_status_5 Config Ready Paused Low_power Config Ready Paused Low_power dmc_memc_status_5 RO - - - - dmc_memc_cmd_5 WO - - - - dmc_direct_cmd_5 WO - - - - dmc_memory_cfg_5 R/W dmc_refresh_prd_5 R/W x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x dmc_t_xsr_5 R/W dmc_t_esr_5 R/W dmc_id_0_cfg_5 R/W dmc_chip_0_cfg_5 R/W dmc_user_config_5 WO - - - - dmc_cas_latency_5 R/W dmc_t_dqss_5 R/W dmc_t_mrd_5 R/W dmc_t_ras_5 R/W dmc_t_rc_5 R/W dmc_t_rcd_5 R/W dmc_t_rfc_5 R/W dmc_t_rp_5 R/W dmc_t_rrd_5 R/W dmc_t_wr_5 R/W dmc_t_wtr_5 R/W dmc_t_xp_5 R/W dmc_id_1_cfg_5 dmc_id_2_cfg_5 dmc_id_3_cfg_5 dmc_id_4_cfg_5 dmc_id_5_cfg_5 MPMC1 registers can't be read/write in reset status. TMPA910CRA- 266 2010-06-02 TMPA910CRA 1. dmc_memc_status_5 (DMC Memory Controller Status Register) Address = (0xF431_0000) + (0x0000) Bit Bit Type Symbol Reset Description Value [31:10] - - Undefined Read as undefined. Write as zero. [9] memory_banks RO 0y1 Setting value of the maximum number of banks that the DMC supports: Fixed to 4 banks. [8:7] - - Undefined Read as undefined. [6:4] memory_ddr RO 0y001 Types of SDRAM that the DMC supports: 0y000 = Reserved 0y001 = DDR SDRAM 0y011 = Reserved 0y010 = Reserved 0y1xx = Reserved [3:2] memory_width RO 0y00 External memory bus width: 0y00 = 16-bit 0y01 = Reserved 0y10 = Reserved 0y11 = Reserved [1:0] memc_status RO 0y00 Memory controller status: 0y00 = Config 0y01 = Ready 0y10 = Paused 0y11 = Low-power [Description] a. <memory_banks> Setting value of the maximum number of banks that the DMC supports: Fixed to 4 banks. b. <memory_ddr> Types of SDRAM that the DMC supports. Fixed to 0y001. c. <memory_width> External memory bus width: 0y00 = 16-bit 0y01 = Reserved 0y10 = Reserved 0y11 = Reserved d. <memc_status> Memory controller status: 0y00 = Config 0y01 = Ready 0y10 = Paused 0y11 = Low-power TMPA910CRA- 267 2010-06-02 TMPA910CRA 2. dmc_memc_cmd_5 (DMC Memory Controller Command Register) Address = (0xF431_0000) + (0x0004) Bit Bit Symbol Reset Type Description Value [31:3] - - Undefined Read as undefined. Write as zero. [2:0] memc_cmd WO - Change the memory controller status: 0y000 = Go 0y001 = Sleep 0y010 = Wakeup 0y011 = Pause 0y100 = Configure [Description] a. <memc_cmd> Settings of this register can change the DMC state machine. If a previously issued command for changing the states is being executed, a new command is issued after the previous command is completed. The following diagram shows DMC state transitions. Low power POR Sleep Pause Reset Pause config Wakeup Configure Go Go Ready External memory state transitions When the DMC exits the Reset state, it automatically enters the Config state. The state transition from Pause to Config is effected by a Config command. Register settings must be made during the Config state. When the DMC state is shifted to Ready, reads from and writes to the SDRAM are allowed. When a read or write is executed, the SDRAM will change from IDLE to ACTIVE. When the DMC state is Ready, a Pause command shifts the DMC to Pause. The SDRAM state at this time varies depending on the immediately preceding command executed on the SDRAM. If a Read or Write has been executed, the SDRAM will be shifted to ACTIVE. If a AutoRefresh has been executed, the SDRAM will be shifted to IDLE (Note). TMPA910CRA- 268 2010-06-02 TMPA910CRA When the DMC state is shifted from Pause to Low power by a Sleep command, after All Bank Precharge is executed, CKE will be driven "L" and the SDRAM will automatically enter the Self-refresh state. When the DMC state is shifted from Low power to Pause by a Wakeup command, a Self-refresh Exit command will be issued. The SDRAM then automatically exists the Self-refresh state and enters the IDLE state. Note: The SDRAM can be shifted from ACTIVE to IDLE by either of the following two settings: dmc_direct_cmd_5< memory_cmd>0y00 = Prechargeall or 0y01 = Autorefresh TMPA910CRA- 269 2010-06-02 TMPA910CRA 3. dmc_direct_cmd_5 (DMC Direct Command Register) This register sets each command for external memory and external memory mode register. This register sets the initial setting of external memory. Address = (0xF431_0000) + (0x0008) Bit Bit Symbol Reset Type Description Value [31:22] - - Undefined Read as undefined. Write as zero. [21:20] chip_nmbr WO - Always write 0y00 [19:18] memory_cmd WO - Determines the command required: 0y00 = Prechargeall 0y01 = Autorefresh 0y10 = Modereg or Extended modereg 0y11 = NOP [17:16] bank_addr WO - Bits mapped to external memory bank address bits when command is Modereg access. 0y00 = bank0 0y01 = bank1 0y10 = bank2 0y11 = bank3 [15:14] - - Undefined Read as undefined. Write as zero. [13:0] addr_13_to_0 WO - Bits mapped to external memory address bits [13:0] when command is Modereg access. Note: Use dmc_direct_cmd_5 to configure cas latency of DDR_SDRAM memory, The setting of cas latency(CL) is different from SDR_SDRAM. The CL setting value of memory controler must be 1 smaller than the CL setting value of DDR_SDRAM memory. Examples: dmc_cas_latency_5 0x00000004 dmc_direct_cmd_5 0x00080033 (set memory controller CL = 2) (set DDR SDRAM memory CL = 3) [Description] a. <memory_cmd> Determines the command required: 0y00 = Prechargeall 0y01 = Autorefresh 0y10 = Modereg or Extended modereg 0y11 = NOP TMPA910CRA- 270 2010-06-02 TMPA910CRA b. <bank_addr> Bits mapped to external memory bank address bits when command is Modereg access. 0y00 = bank0 0y01 = bank1 0y10 = bank2 0y11 = bank3 c. <addr_13_to_0> Bits mapped to external memory address bits [13:0] when command is Modereg access. TMPA910CRA- 271 2010-06-02 TMPA910CRA 4. dmc_memory_cfg_5 (DMC Memory Configuration Register) Address = (0xF431_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value [31:23] - - Undefined Read as undefined. Write as zero. [22:21] active_chips R/W 0y00 Always write 0y00 [20:18] - - Undefined Read as undefined. Write as zero. [17:15] memory_burst R/W 0y010 Set the read and write burst length for the SDRAM 0y000 = Reserved 0y001 = Burst 2 0y010 = Burst 4 0y011 = Burst 8 0y100 = Burst 16 other = Reserved [14] stop_mem_clock R/W 0y0 memory clock stop: 0y0 = Disable 0y1 = Enable [13] auto_power_down R/W 0y0 SDRAM auto Powerdown Enable: 0y0 = Disable 0y1 = Enable [12:7] power_down_prd R/W 0y000000 Number of SDRAM automatic Powerdown memory clocks: (Min. value = 1) 0y000001 0y111111 [6] ap_bit R/W 0y0 The position of the auto-precharge bit in the memory address: 0y0 = address bit 10 0y1 = address bit 8 [5:3] row_bits R/W 0y100 The number of row address bits: 0y000 = 11 bits 0y001 = 12 bits 0y010 = 13 bits 0y011 = 14 bits 0y100 = 15 bits 0y101 = 16 bits other = Reserved [2:0] column_bits R/W 0y000 The number of column address bits: 0y000 = 8 bits 0y001 = 9 bits 0y010 = 10 bits 0y011 = 11 bits 0y100 = 12 bits other = Reserved [Description] a. <memory_burst> Set the burst length of the memory access controller. This needs to correspond with the burst length of the memory configured in the dmc_direct_cmd_5 register. TMPA910CRA- 272 2010-06-02 TMPA910CRA b. <stop_mem_clock> The clock supply to the SDRAM can be stopped while it is not being accessed. When an SDRAM access request occurs again, the clock is automatically restarted. Note1: Depending on the SDRAM type, it may not be possible to stop the clock supply to the SDRAM while it is not being accessed. When using this function, be sure to carefully check the specifications of the SDRAM to be used. Note2: The memory clock stop function and the SDRAM auto Powerdown function cannot be used concurrently. Use only either of the two. c. <auto_power_down> When no SDRAM access request is present and the command FIFO of the memory controller becomes empty, the SDRAM can be placed into Powerdown mode by automatically disabling CKE after the number of clock cycles specified in the power_down_prd field. When an SDRAM access request occurs again, CKE is automatically enabled to exit the Powerdown mode. Note: The memory clock stop function and the SDRAM auto Powerdown function cannot be used concurrently. Use only either of the two. d. <row_bits><column_bits> These bits set the row and column addresses. Supported selectable memory is limited by the summation of column address and row address. In case of 32bit bus, less than R+C=25 bits (128Mbytes) then 512Mbytes for 4 banks In case of 16bit bus, less than R+C=26 bits (128Mbytes) then 512Mbytes for 4 banks TMPA910CRA- 273 2010-06-02 TMPA910CRA 5. dmc_refresh_prd_5 (DMC Refresh Period Register) Address = (0xF431_0000) + (0x0010) Bit Bit Symbol Type Reset Description Value [31:15] - - Undefined [14:0] refresh_prd R/W 0x0A60 Read as undefined. Write as zero. Auto-refresh cycle (number of memory clocks): 0x0000 to 0x7FFF [Description] a. <refresh_prd> The value of the refresh counter decrements from the value set in the dmc_refresh_prd_5 (the number of memory clocks), and when the counter reaches zero, the Autorefresh command is issued to external memory. DMCDCLKP DMCDCLKN Auto refresh cycle DMCCSn Auto refresh Auto refresh DMCRASn DMCCASn DMCWEn DMCDDMx TMPA910CRA- 274 2010-06-02 TMPA910CRA 6. dmc_cas_latency_5 (DMC CAS Latency Register) Address = (0xF431_0000) + (0x0014) Bit Bit Symbol Type Reset Description Value [31:4] - - Undefined [3:1] cas_latency R/W 0y11 Read as undefined. Write as zero. CAS latency setting (number of memory clocks) 0y000 to 0y111 [0] cas_half_cycle R/W 0y0 set CAS latency offset 0y0 = 0 offset 0y1 = Half cycle offset Note: Use dmc_cas_latency_5 to configure cas latency of memory controler, The setting of cas latency(CL) is different from SDR_SDRAM. The CL setting value of memory controler is 1 smaller than the CL setting value of DDR_SDRAM memory. Example: dmc_cas_latency_5 0x00000004 dmc_direct_cmd_5 0x00080033 (set memory controller CL = 2) (set DDR SDRAM memory CL = 3) [Description] a. <cas_latency> CAS latency setting (number of memory clocks): 0y000 to 0y111 b. <cas_half_cycle> CAS latency offset setting: 0y0 = 0 offset 0y1 = Half-cycle offset TMPA910CRA- 275 2010-06-02 TMPA910CRA DMCDCLKP DMCDCLKN Memory controller CL = 2 DMCCSn DMCRASn DMCCASn DMCWEn ACT READ CMD A0 to A15 DMCAP DMCDDMx DMCDDQSx Input D0 to D15 Input Input Figure 3.10.24 CAS latency example (CL=2) TMPA910CRA- 276 2010-06-02 TMPA910CRA 7. dmc_t_dqss_5 (DMC t_dqss Register) Address = (0xF431_0000) + (0x0018) Bit Bit Symbol Type Reset Description Value [31:2] - - Undefined Read as undefined. Write as zero. [1:0] t_dqss R/W 0y01 DQS setting (number of memory clocks): 0y00 to 0y11 [Description] a. <t_dqss> Set DQS (memory clocks): 0y00 to 0y11 DMCDCLKP DMCDCLKN DMCCSn DMCRASn ACT DMCCASn DMCWEn WRITE CMD A0 to A15 DMCAP DMCDDMx Output Selec tDQSS DMCDDQSx Output D0 to D15 Output TMPA910CRA- 277 Output 2010-06-02 TMPA910CRA 8. dmc_t_mrd_5 (DMC t_mrd Register) Address = (0xF431_0000) + (0x001C) Bit Bit Symbol Type Reset Description Value [31:7] - - Undefined [6:0] t_mrd R/W 0y0000010 Read as undefined. Write as zero. Mode register command time (Number of memory clocks) 0x00 to 0x7F [Description] a. <t_mrd> Set time from the mode register command time set by the direct command register (dmc_direct_cmd_5<addr_13_to_0>) to all other commands (memory clocks): 0x00 to 0x7F Depending on other AC settings and operations, the actual delay time may be longer than the specified time. Set the minimum number of clocks in this register. DMCDCLKP DMCDCLKN t_mrd Mode register command command DMCDDMx DMCSCSn DMCRASn Command Register SET Any CMD DMCCASn DMCWEn A0 to A15 DMCAP Figure 3.10.25 <t_mrd> set the time from mode register write to other command TMPA910CRA- 278 2010-06-02 TMPA910CRA 9. dmc_t_ras_5 (DMC t_ras Register) Address = (0xF431_0000) + (0x0020) Bit Bit Symbol Reset Type Description Value [31:4] - - Undefined [3:0] t_ras R/W 0x7 Read as undefined. Write as zero. Time between RAS and Precharge (number of memory clocks) 0x0 to 0xF [Description] a. <t_ras> Time between RAS and Precharge (number of memory clocks) 0x0 to 0xF Depending on other AC settings and operations, the actual delay time may be longer than the specified time. Set the minimum number of clocks in this register. DMCDCLKP DMCDCLKN RAS-Precahrge period RAS Precharge DMCDDMx DMCSCSn DMCRASn RAS ACTIVE Pre Charge DMCCASn DMCWEn A0 to A15 DMCAP Figure 3.10.26 Time from Active to Precharge TMPA910CRA- 279 2010-06-02 TMPA910CRA 10. dmc_t_rc_5 (DMC t_rc Register) Address = (0xF431_0000) + (0x0024) Bit Bit Type Symbol Reset Description Value [31:4] - - Undefined [3:0] t_rc R/W 0y1011 Read as undefined. Write as zero. Delay between Active bank A and Active bank A (Number of memory clocks) 0x0 to 0xF [Description] a. <t_rc> Set delay time from Active bank command to Active command time in the same bank (memory clocks): 0x0 0xF Depending on other AC settings and operations, the actual delay time may be longer than the specified time. Set the minimum number of clocks in this register. DMCDCLKP DMCDCLKN ACTIVE-ACTIVE DMCDDQMx ACTIVE ACTIVE DMCCSn DMCRASn ACT ACT BANK A BANK A DMCCASn DMCWEn A0~A15 DMCAP BA[1:0] Figure 3.10.27 from Active bank A to Active bank A TMPA910CRA- 280 2010-06-02 TMPA910CRA 11. dmc_t_rcd_5 (DMC t_rcd Register) Address = (0xF431_0000) + (0x0028) Bit Bit Symbol Type Reset Description Value [31:6] - - Undefined Read as undefined. Write as zero. [5:3] schedule_rcd R/W 0y011 Set min delay from RAS to CAS: [2:0] t_rcd R/W 0y101 Set to (t_rcd setting value -3) Set min delay from RAS to CAS (number of memory clocks): 0y000 to 0y111 [Description] a. <schedule_rcd> Set min delay from RAS to CAS (number of memory clocks): Set to (t_rcd setting value -3) b. <t_rcd> Set min delay from RAS to CAS (number of memory clocks): 0y000 to 0y111 DMCDCLKP DMCDCLKN RAS-CAS time DMCDDMx RAS CAS DMCSCSn DMCRASn ACTIVE CMD DMCCASn R/W CMD DMCWEn A0~A15 DMCAP Figure 3.10.28 Timing from Active to Read/Write Command TMPA910CRA- 281 2010-06-02 TMPA910CRA 12. dmc_t_rfc_5 (DMC t_rfc Register) Address = (0xF431_0000) + (0x002C) Bit Bit Symbol Type Reset Description Value [31:10] - - Undefined Read as undefined. Write as zero. [9:5] schedule_rfc R/W 0y10000 Autorefresh command time setting [4:0] t_rfc R/W 0y10010 Set to (t_rfc setting value -3) Autorefresh command time setting (Number of memory clocks): 0y00000 to 0y11111 [Description] a. <schedule_rfc> Autorefresh command time setting Set to (t_rfc setting value -3) b. <t_rfc> Autorefresh command time setting (number of memory clocks): 0y00000 to 0y11111 DMCDCLKP DMCDCLKN Command-Command time Auto Refresh Command Command DMCSCSn DMCRASn Auto Refresh CMD Any CMD DMCCASn DMCWEn A0~A15 DMCAP Figure 3.10.29 Time from Autorefresh command to other command TMPA910CRA- 282 2010-06-02 TMPA910CRA 13. dmc _t_rp_5 (DMC t_rp Register) Address = (0xF431_0000) + (0x0030) Bit Bit Symbol Reset Type Description Value [31:6] - - Undefined Read as undefined. Write as zero. [5:3] schedule_rp R/W 0y011 Precharge delay setting to RAS [2:0] t_rp R/W 0y101 Set the time from Precharge to RAS (number of memory Set to (t_rp setting value -3) clocks): 0y000 to 0y111 [Description] a. <schedule_rp> Set the time from Precharge to RAS Set to (t_rp setting value -3) b. <t_rp> Set the time from Precharge to RAS (number of memory clocks) 0y000 to 0y111 DMCDCLKP DMCDCLKN Precahrge-RAS time Precharge RAS DMCDDMx DMCSCSn DMCRASn Pre Charge RAS ACTIVE DMCCASn DMCWEn A0 to A15 DMCAP Figure 3.10.30 Precharge to command, Autorefresh time TMPA910CRA- 283 2010-06-02 TMPA910CRA 14. dmc_t_rrd_5 (DMC t_rrd Register) Address = (0xF431_0000) + (0x0034) Bit Bit Type Symbol Reset Description Value [31:4] - - Undefined [3:0] t_rrd R/W 0y0010 Read as undefined. Write as zero. Delay time from Active bank A to Active bank B (Number of memory clocks): 0x0 to 0xF [Description] a. <t_rrd> Delay time from Active bank A to Active bank B (number of memory clocks): 0x0 to 0xF DMCDCLKP DMCDCLKN ACTIVE-ACTIVE time DMCDDMx ACTIVE ACTIVE DMCSCSn DMCRASn ACT ACT BANK A BANK B DMCCASn DMCWEn A0 to A15 DMCAP BA[1:0] Figure 3.10.31 Time between Active bank A and other Active bank B TMPA910CRA- 284 2010-06-02 TMPA910CRA 15. dmc_t_wr_5 (DMC t_wr Register) Address = (0xF431_0000) + (0x0038) Bit Bit Symbol Type Reset Description Value [31:3] - - Undefined [2:0] t_wr R/W 0y011 Read as undefined. Write as zero. Delay from write last data to Precharge (Number of memory clocks): 0y000 to 0y111 [Description] a. <t_wr> Delay from write last data to Precharge (Number of memory clocks). Actual time (memory clocks): <t_wr> + 1. But when <t_wr> = 0y000, actual time (memory clocks) = 9 memory clocks. DMCDCLKP DMCDCLKN DMCCSn DMCRASn Write data Precharge DMCCASn ACT DMCWEn WRITE CMD Precharge A0~A15 DMCAP DMCDDMx Output Output tDQSS DMCDDQSx D0~D15 Output TMPA910CRA- 285 Output 2010-06-02 TMPA910CRA 16. dmc_t_wtr_5 (DMC t_wtr Register) Address = (0xF431_0000) + (0x003C) Bit Bit Reset Type Symbol Description Value [31:3] - - Undefined Read as undefined. Write as zero. [2:0] t_wtr R/W 0y010 Setting value from the last write data to read command (memory clocks): 0y000 to 0y111 [Description] a. <t_wtr> Setting value from write last data to read command (memory clocks) Note: When <t_wtr> = 0y000, Actual time (memory clocks) = 8 memory clocks. DMCDCLKP DMCDCLKN DMCSDQMx Write Command Read Command DMCCSn DMCRASn DMCCASn Write data Read Command DMCWEn t_wtr (Single transfer) D15~D0 (single transfer) t_wtr (Burst transfer) D15~D0 (burst transfer) DMCAP TMPA910CRA- 286 2010-06-02 TMPA910CRA 17. dmc _t_xp_5 (DMC t_xp Register) Address = (0xF431_0000) + (0x0040) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] t_xp R/W 0x01 Setting value of the exit power-down command time (Number of memory clocks): 0x00 to 0xFF [Description] a. <t_xp> Set time from Powerdown Exit command to other command (memory clocks): Actual time (memory clocks): t_xp set value + 1 DMCSCLK DMCSDQMx t_xp DMCSCSn PowerDown Exit command command DMCRASn Any CMD DMCCASn DMCWEn A0~A15 DMCCKE Power down Exit Figure 3.10.32 Time from Powerdown entry to Exit TMPA910CRA- 287 2010-06-02 TMPA910CRA 18. dmc_ t_xsr_5 (DMC t_xsr Register) Address = (0xF431_0000) + (0x0044) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] t_xsr R/W 0x0A Set the Self-refresh Exit command time: (memory clocks): 0x00 to 0xFF [Description] a. <t_ xsr> Set time from Self-refresh Exit command to other command (memory clocks): 0x00 to 0xFF DMCDCLKP DMCDCLKN DMCSDQMx t_xsr DMCCSn Self-refresh Exit command command DMCRASn Any CMD DMCCASn DMCWEn A0~A15 DMCCKE Self-Refresh Exit TMPA910CRA- 288 2010-06-02 TMPA910CRA 19. dmc_t_esr_5 (DMC t_esr Register) Address = (0xF431_0000) + (0x0048) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7:0] t_esr R/W 0x14 Read undefined. Write as zero. The minimum time from Self-refresh Entry to Exit: (memory clocks) 0x00 to 0xFF Note: Self-refersh Exit is triggered by Wakeup direct command. This register is to set the minimum time from Self-refresh Entry to Exit. [Description] a. <t_ esr> The minimum time from Self-refresh Entry to Exit (memory clocks) 0x00 to 0xFF DMCDCLKP DMCDCLKN DMCDDQMx Self-refresh Entry command Self-refresh Exit command DMCDCSn DMCRASn DMCCASn DMCWEn t_esr A0~A15 DMCCKE Figure 3.10.33 SelfRefresh Entry and Exit TMPA910CRA- 289 2010-06-02 TMPA910CRA 20. dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg Registers) Address = (0xF431_0000) + (0x0100) Address = (0xF431_0000) + (0x0104) Address = (0xF431_0000) + (0x0108) Address = (0xF431_0000) + (0x010C) Address = (0xF431_0000) + (0x0110) Address = (0xF431_0000) + (0x0114) Bit Bit Reset Type Symbol Description Value [31:10] - - Undefined [9:2] qos_max R/W 0x00 Read as undefined. Write as zero. maximum QoS: 0x00 0xFF [1] qos_min R/W 0y0 minimum QoS selection: 0y0 = QoS max mode 0y1 = QoS min mode [0] qos_enable R/W 0y0 QoS setting: 0y0 = Disable 0y1 = Enable QoS setting register list Register Address Correspond to AHB dmc_id_0_cfg_5 (0xF431_0000) + (0x0100) dmc_id_1_cfg_5 (0xF431_0000) + (0x0104) AHB0 : CPU Data AHB1 : CPU Inst dmc_id_2_cfg_5 (0xF431_0000) + (0x0108) AHB2 : LCDC dmc_id_3_cfg_5 (0xF431_0000) + (0x010C) AHB3 : multilayer bus matrix2 dmc_id_4_cfg_5 (0xF431_0000) + (0x0110) AHB4 : DMA1 dmc_id_5_cfg_5 (0xF431_0000) + (0x0114) AHB5 : DMA2 (LCDDA, USB) [Description] a. <qos_max> QoS maximum value setting: 0x00 to 0xFF b. <qos_min> Minimum QoS selction: 0y0 = QoS max mode 0y1 = QoS min mode, QoS minimum have priority over QoS maximum c. <qos_enable> Enable QoS: 0y0 = Disable 0y1 = Enable TMPA910CRA- 290 2010-06-02 TMPA910CRA 21. dmc_chip_0_cfg_5 (DMC chip_0_cfg Registers) Address = (0xF431_0000) + (0x0200) Bit Bit Symbol Type Reset Description Value [31:17] - - Undefined [16] brc_n_rbc R/W 0y0 Read as undefined. Write as zero. SDRAM address structure: 0y0 = row, bank, column 0y1 = bank, row, column [15:8] address_match R/W 0xFF Set the start address [31:24] [7:0] address_mask R/W 0x00 Set the mask value of the start address [31:24] 0x00 to 0xFF 0y0 = Do not compare 0y1 = Compare 0x00 to 0xFF [Description] a. <brc_n_rbc> SDRAM address structure 0y0 = row, bank, column 0y1 = bank, row, column b. <address_match> Set the start address [31:24]. If the size of connected memory is less than 512 bytes, do not access unused DMC area outside the specified CS area. Note: Before setting the start address, check the valid address area by referring to Chapter 3.3 Memory Map. c. <address_mask> This register specifies the CS area. Set whether or not each bit in the start address [31:24] should be compared. 0y0 = Do not compare 0y1 = Compare TMPA910CRA- 291 2010-06-02 TMPA910CRA 22. dmc_user_config_5 (DMC user_config Register) Address = (0xF431_0000) + (0x0304) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] Reserved - Undefined Read as undefined. Write as zero. [6:4] dqs_in WO 0y000 DDR SDRAM constant value setting: [3:1] dmc_clk_in WO 0y000 DDR SDRAM constant value setting: [0] sdr_width WO 0y0 data bus width of external DDR SDRAM : Read as undefined. Write as zero. Fix to 0y100 Fix to 0y100 0y0: 16-bit 0y1: Reserved [Description] a. <sdr_width> Set the memory data bus width of corresponding external SDR memory: 0y0 = 16bit 0y1 = Reserved TMPA910CRA- 292 2010-06-02 TMPA910CRA 3.10.5.2 SMC (Static Memory Controller) This device contains and SMC (Static Memory Controller) that controls the external memory (NOR Flash memory, Mask ROM SRAM and etc.). (1) SMC (Static Memory Controller) Table 3.10.11 shows Feature of SMC. Table 3.10.11 Feature of SMC Features Support memory Chip select 0/1 External Static memory (NOR Flash memory and SRAM, etc.) Support separate bus only Data bus width 16bit/32bit data bus width Access areas 4 areas support by Chip select. Max access area: SMCCS0n: 512 MB SMCCS1n: 512 MB SMCCS2n: 512 MB SMCCS3n: 256 MB Timing adjustment Adjustable AC timing by register Clock Selectable the clock for external pin (fHCLK or fHCLK /2) by the clock controller register External control pin D31 to D0, A25 to A0, Support external wait request (only in Synchronous mode) CLKCR5<SEL_SMC_MCLK> SMCBE0n, SMCBE1n, SMCBE2n, SMCBE3n, SMCCS0n, SMCCS1n, SMCCS2n, SMCCS3n, SMCOEn,SMCWEn, SMCCLK , SMCWAITn, SMCAVDn TMPA910CRA- 293 2010-06-02 TMPA910CRA (2) SMC (Static Memory Controller) Figure 3.10.34 is a SMC block diagram. Memory Domain AHB Domain APB slave Memory I/F Manager EBI I/F Arbiter Memory I/F PAD I/F SRAM memory I/F SMC I/F Figure 3.10.34 SMC Block Diagram (a) Arbiter The Arbiter receives accesses from the SMC I/F and memory manager. Read/Write requests are arbitrated on a Round-Robin basis. Requests from the manager have the highest priority. (b) Memory manager Updates timing registers and controls commands issued to memory. TMPA910CRA- 294 2010-06-02 TMPA910CRA (3) SMC Function (a) APB slave I/F The APB slave I/F adds a wait state for all reads and writes More than one wait state is generated in the following case: Outstanding direct commands A memory command is received, but the previous memory command has not been completed. (b) Format 1. Hazard processing When selfsame stand-alone bus master access to an external memory, the actual access procedure to memory is executed in the instruction order. However, if multiple bus master access to an external memory, the read and write data will be stored temporary into independent buffer and be executing by priority circuit. Therefore, the read and the write instruction may switch execution sequence. So please coordinate a variety of sequences, e.g. making an enough time for next instruction, checking whether or not previous execution is finished, the common-use memory data uses the internal memory and so on. 2. Access to the SRAM memory * Standard SRAM access * Memory address shifting * Memory burst alignment The burst align settings are necessary in order to support asynchronous page mode memory. Refer to SMC register of MPMC, smc_set_opmode_3 (SMC Set Opmode Register) Note: In case of not having any page mode methods, e.g. NOR Flash, it is unnecessary to set burst align. Memory burst length: Supported memory burst transfer length is 4 beats. TMPA910CRA- 295 2010-06-02 TMPA910CRA (c) Memory manager operation The memory manager controls the SMC state and manages update of chip configuration registers. (d) Memory I/F operation The memory I/F issues commands and control their timings. Table 3.10.12 Static Memory Setup Example Base address = 0xF431_1000 Register address Write data Description 0x0014 0x00029266 smc_set_cycles_5 0x0018 0x00000809 smc_set_opmode_5 0x0010 0x00400000 smc_direct_cmd_5 TMPA910CRA- 296 2010-06-02 TMPA910CRA (4) SMC Registers for MPMC1 Table 3.10.13 MPMC1 SMC SFR list Base address = 0xF431_1000 Register Address Name (base+) Type Reset value Description Reserved 0x0000 - Undefined Read as undefined. Write as zero. Reserved 0x0004 - Undefined Read as undefined. Write as zero. Reserved 0x0008 - - Writing prohibited Reserved 0x000C - - Writing prohibited smc_direct_cmd_5 0x0010 WO - SMC Direct Command Register smc_set_cycles_5 0x0014 WO - SMC Set Cycles Register smc_set_opmode_5 0x0018 WO - SMC Set Opmode Register - 0x0020 R/W - Reserved. smc_sram_cycles0_0_5 0x0100 smc_sram_cycles0_1_5 0x0120 smc_sram_cycles0_2_5 0x0140 RO 0x0002B3CC SMC SRAM Cycles Registers <0-3> smc_sram_cycles0_3_5 0x0160 smc_opmode0_0_5 0x0104 0x20E00802 smc_opmode0_1_5 0x0124 0x60E00802 smc_opmode0_2_5 0x0144 smc_opmode0_3_5 0x0164 RO 0xA0E00802 SMC Opmode Registers <0-3> 0xE0E00802 Reserved 0x0200 - Undefined Read undefined. Write as zero. Reserved 0x0204 - Undefined Read undefined. Write as zero. Reserved 0x0E00 - Undefined Read undefined. Write as zero. Reserved 0x0E04 - Undefined Read undefined. Write as zero. Reserved 0x0E08 - Undefined Read undefined. Write as zero. Reserved 0x0FE0-0x0FEC - Undefined Read undefined. Write as zero. Reserved 0x0FF0-0x0FFC - Undefined Read undefined. Write as zero. Note: The APB supports only single-word 32-bit accesses. Read from or write to registers at single-word 32-bit mode. TMPA910CRA- 297 2010-06-02 TMPA910CRA 1. smc_direct_cmd_5 (SMC Direct Command Register) Address = (0xF431_1000) + (0x0010) Bit Bit Symbol Reset Type Description Value [31:26] - - Undefined Read as undefined. Write as zero. [25:23] chip_select WO - CS selection: 0y000 = CS0 0y001 = CS1 0y010 = CS2 0y011 = CS3 0y100-0y111 = Reserved [22:21] cmd_type WO - current command: 0y00 = Reserved 0y01 = Reserved 0y10 = UpdateRegs 0y11 = Reserved [20:0]] - - Undefined Read as undefined. Write as zero. [Description] a. <chip_select> CS selection: 0y000 = CS0 0y001 = CS1 0y010 = CS2 0y011 = CS3 0y100 to 0y111 = Reserved b. <cmd_type> Current command: 0y00 = Reserved 0y01 = Reserved 0y10 = UpdateRegs 0y11 = Reserved TMPA910CRA- 298 2010-06-02 TMPA910CRA Start Set smc_set_cycle register as timing parameter and set smc_set_opmode as operation mode Select the external ChipSelect and smc_direct_cmd register then updating set END TMPA910CRA- 299 2010-06-02 TMPA910CRA 2. smc_set_cycles_5 (SMC Set Cycles Register) Address = (0xF431_1000) + (0x0014) Bit Bit Symbol Reset Type Description Value [31:23] - - Undefined Read as undefined. Write as zero. [22:20] Reserved - Undefined Read as undefined. Write as zero. [19:17] Set_t5 WO - Set value of tTR (holding register) 0y000 to 0y111 [16:14] Set_t4 WO - Set value of tPC (holding register) 0y000 to 0y111 [13:11] Set_t3 WO - Set value of tWP (holding register) 0y000 to 0y111 [10:8] Set_t2 WO - Set value of tCEOE (holding register) 0y000 to 0y111 [7:4] Set_t1 WO - Set value of tWC (holding register) 0y0000 to 0y1111 [3:0] Set_t0 WO - Set value of tRC (holding register) 0y0000 to 0y1111 This register is provided to adjust the access cycle of static memory and should be set to satisfy the AC specifications of the memory to be used. If the wait signal by an external pin is also used, the access cycle is determined to satisfy the settings of both this register and the external wait signal. Note that the external wait signal is only effective in synchronous mode. It cannot be used in asynchronous mode. This is a holding register for enabling setting values. By executing of the following operations, the settings values of this register will be updated to the configuration register of the memory manager and enabled. The smc_direct_cmd Register indicates only a register update is taking place. [Description] a. <Set_t5> Set value of tTR (holding register). 0y000 to 0y111 b. <Set_t4> Set value of tPC (holding register). 0y000 to 0y111 c. <Set_t3> Set value of tWP (holding register). 0y000 to 0y111 TMPA910CRA- 300 2010-06-02 TMPA910CRA d. <Set_t2> Set value of tCEOE (holding register). 0y000 to 0y111 e. <Set_t1> Set value of tWC (holding register). 0y0000 to 0y1111 f. <Set_t0> Set value of tRC (holding register). 0y0000 to 0y1111 Example of setting timing Setting Example: SMC Set Cycles Register = 0x0002B1C3 Register setting value 0x0002B1C3 tPC tTR tWP tCEOE 1 TWC tRC 3 don't care smcclk (Internal clock) tRC SMCCS0n SMCOEn tCEOE SMCWEn Addr A[25:0] D[31:0] XXXX Data XXXX Figure 3.10.35 Asynchronous Read TMPA910CRA- 301 2010-06-02 TMPA910CRA Setting Example: SMC Set Cycles Register = 0x0002934C Register setting value 0x0002934C tTR tPC tWP 2 tCEOE TWC 4 tRC don't care smcclk (Internal clock) SMCCS0n tWC SMCOEn SMCWEn tWP A[25:0] Addr D[31:0] XXXX Data XXXX BE[0:3]n Figure 3.10.36 Asynchronous Write Setting Example: SMC Set Cycles Register = 0x000272C3 Register setting value 0x000272C3 tTR smcclk (Internal clock) tRC SMCCS0n SMCOEn tPC 1 tWP tPC tCEOE 2 TWC tRC 3 don't care tPC tPC tCEOE SMCWEn D[31:0] XXXX D A+3 A+2 A+1 A A[25:0] D+1 D+2 D+3 Figure 3.10.37 Asynchronous Page Read TMPA910CRA- 302 2010-06-02 TMPA910CRA Setting Example: SMC Set Cycles Register = 0x00029143 Register setting value 0x00029143 tTR 1 tPC tWP 2 tCEOE 1 TWC 4 tRC 3 don't care smcclk (Internal clock) SMCCS0n tTR SMCOEn SMCWEn D[31:0] Addr2 Addr1 A[25:0] XXXX Figure 3.10.38 D1 XXXX D2 Asynchronous Write after Asynchronous Read TMPA910CRA- 303 2010-06-02 TMPA910CRA 3. smc_set_opmode_5 (SMC Set Opmode Register) Address = (0xF431_1000) + (0x0018) Bit Bit Symbol Reset Type Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15:13] set_burst_align WO - Memory burst boundary split setting: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] set_bls WO - Byte Enable (SMCBE0-3) timing setting: 0y0 = SMCCSn timing 0y1 = SMCWEn timing [11] set_adv WO - Address valid (adv) field set value 0y0 = Memory address valid signal SMCAVDn not used 0y1 = Memory address valid signal SMCAVDn used [10] - - Undefined Read as undefined. Write as zero. [9:7] set_wr_bl WO - Write burst length 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] set_wr_sync WO - Holding register of the wr_sync field set value: 0y0 = asynchronous write mode 0y1 = synchronous write mode [5:3] set_rd_bl WO - Read burst length 0y000 = 1-beat 0y001 = 4-beats other = Reserved [2] set_rd_sync WO - Holding register of the rd_sync field set value: 0y0 = asynchronous read mode 0y1 = synchronous read mode [1:0] set_mw WO - Holding register of the memory data bus width set value: 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved This is a holding register for enabling setting values. By executing of the following operations, the settings values of this register will be updated to the configuration register of the memory manager and enabled. The smc_direct_cmd Register indicates only a register update is taking place. [Description] a. <set_burst_align> For asynchronous transfers: When set_rd_sync = 0, MPMC1 always aligns read bursts to the memory burst boundary. When set_wr_sync = 0, MPMC1 always aligns write bursts to the memory burst boundary. TMPA910CRA- 304 2010-06-02 TMPA910CRA b. < set_bls > Byte Enable (SMCBE0-3) timing setting: 0y0 = SMCCSn timing 0y1 = SMCWEn timing c. < set_adv > Address valid (adv) field set value 0y0 = Memory address valid signal SMCAVDn not used 0y1 = Memory address valid signal SMCAVDn used d. < set_wr_bl > Write burst length 0y000 = 1 beat 0y001 = 4 beats other = Reserved e. < set_wr_sync > Write synchronization mode setting: 0y0 = asynchronous write mode 0y1 = synchronous write mode f. < set_rd_bl > Read burst length 0y000 = 1 beat 0y001 = 4 beats other = Reserved g. < set_rd_sync > Read synchronization mode setting: 0y0 = asynchronous read mode 0y1 = synchronous read mode h. < set_mw > Holding register of the memory data bus width set value: 0y00 = Reserved 0y01 = 16 bits 0y10 = 32 bits 0y11 = Reserved TMPA910CRA- 305 2010-06-02 TMPA910CRA 4. smc_sram_cycles0_0_5 (SMC SRAM Cycles Registers 0 <0>) Address = (0xF431_1000) + (0x0100) Bit Bit Symbol Type Reset Description Value [31:20] - - Undefined [19:17] t_tr RO 0y001 Read as undefined. Turnaround time for SRAM chip configuration 0y000 to 0y111 [16:14] t_pc RO 0y010 Page cycle time: 0y000 to 0y111 [13:11] t_wp RO 0y110 Delay time for smc_we_n_0: 0y000 to 0y111 [10:8] t_ceoe RO 0y011 Delay time for smc_oe_n_0: 0y000 to 0y111 [7:4] t_wc RO 0y1100 Write cycle time: 0y0000 to 0y1111 [3:0] t_rc RO 0y1100 Read cycle time: 0y0000 to 0y1111 [Description] a. <t_tr> Turnaround time for SRAM chip configuration 0y000 to 0y111 b. <t_ pc> Page cycle time: 0y000 to 0y111 c. <t_wp> Delay time for smc_we_n_0: 0y000 to 0y111 d. <t_ceoe> Delay time for smc_oe_n_0: 0y000 to 0y111 e. <t_wc> Write cycle time 0y0000 to 0y1111 f. <t_rc> Read cycle time 0y0000 to 0y1111 * smc_sram_cycles0_x_5 (SMC SRAM Cycles Registers 0 <x>) (x = 0 to 3) The structure and description of these registers are same as smc_sram_cycles0_0_5. Please refer to the description of smc_sram_cycles0_0_5. For the name and address of these registers, please refer to Table 3.10.13 MPMC1 SMC SFR list. TMPA910CRA- 306 2010-06-02 TMPA910CRA 5. smc_opmode0_0_5 (SMC Opmode Registers 0 <0>) Address = (0xF431_1000) + (0x0104) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0x00 Read as 0x20. [23:16] Reserved RO 0x00 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined Read undefined. [9:7] wr_bl RO 0y000 Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved TMPA910CRA- 307 2010-06-02 TMPA910CRA 6. smc_opmode0_1_5 (SMC Opmode Registers 0 <1>) Address = (0xF431_1000) + (0x0124) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0x60 Read as 0x60. [23:16] Reserved RO 0xE0 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined Read undefined. [9:7] wr_bl RO 0y000 Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved TMPA910CRA- 308 2010-06-02 TMPA910CRA 7. smc_opmode0_2_5 (SMC Opmode Registers 0 <2>) Address = (0xF431_1000) + (0x0144) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0xA0 Read as 0xA0. [23:16] Reserved RO 0xE0 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined Read undefined. [9:7] wr_bl RO 0y000 Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved TMPA910CRA- 309 2010-06-02 TMPA910CRA 8. smc_opmode0_3_5 (SMC Opmode Registers 0 <3>) Address = (0xF431_1000) + (0x0164) Bit Bit Symbol Type Reset Description Value [31:24] Reserved RO 0xE0 Read as 0xE0. [23:16] Reserved RO 0xE0 Read as 0xE0. [15:13] burst_align RO 0y000 Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary other = Reserved [12] bls RO 0y0 bls timing : 0y0 = chip select 0y1 = Reserved [11] adv RO 0y1 use address Advance signal (address valid) 0y1 = use address Advance signal [10] - - Undefined [9:7] wr_bl RO 0y000 Read as undefined. Write memory burst length: 0y000 = 1-beat 0y001 = 4-beats other = Reserved [6] wr_sync RO 0y0 Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation [5:3] rd_bl RO 0y000 Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats other = Reserved [2] rd_sync RO 0y0 Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation [1:0] mw RO 0y10 Memory data bus width : 0y00 = Reserved 0y01 = 16-bits 0y10 = 32-bits 0y11 = Reserved [Description] a. <burst_align> Memory burst boundary split set value: 0y000 = bursts can cross any address boundary 0y001 = split at the 32-beat burst boundary 0y010 = split at the 64-beat burst boundary 0y011 = split at the 128-beat burst boundary 0y100 = split at the 256-beat burst boundary Other = Reserved TMPA910CRA- 310 2010-06-02 TMPA910CRA b. <bls> Bls timing: 0y0 = chip select 0y1 = Reserved c. <adv> Use address Advance signal (address valid) 0y1 = use address Advance signal d. <wr_bl> Write memory burst length: 0y000 = 1beat 0y001 = 4beats Other = Reserved e. <wr_sync> Memory operation mode: 0y0 = asynchronous write operation 0y1 = synchronous write operation f. <rd_bl> Read memory burst length: 0y000 = 1 beat 0y001 = 4 beats Other = Reserved g. <rd_sync> Memory operation mode: 0y0 = asynchronous read operation 0y1 = synchronous read operation h. <mw> The Reset value depends on setting state. The CSx meomry data bus width can be set for Boot. TMPA910CRA- 311 2010-06-02 TMPA910CRA 3.11 NAND-Flash Controller (NDFC) 3.11.1 Overview The NAND-Flash Controller (NDFC) is provided with dedicated pins for connecting with the NAND-Flash memory. The NDFC also has an ECC calculation function for error correction. It supports the Hamming Code ECC calculation method for the NAND-Flash memory of SLC (Single Level Cell) type that is capable of correction (Note1) a single-bit error for every 256 bytes and the Reed-Solomon ECC calculation method for the NAND-Flash memory of MLC (Multi-Level Cell) type that is capable of correction (Note 1) four error addresses for every 512 bytes. The NDFC has the following features: a. Controls the NAND-Flash memory interface through registers. b. Supports 8-bit NAND-Flash memory devices (Does not support 16-bit devices). c. Supports page sizes of 512 bytes and 2048 bytes. d. Includes an ECC generation circuit using Hamming codes (for SLC type). e. Includes a 4-address (4-byte) error detection coding/encoding techniques (for MLC type). circuit using Reed-Solomon f. Provides an Autoload function for high-speed data transfer by using two 32bit x 4word FIFOs together with a DMA controller. Note 1: Error correction needs software processing. Note 2: The WPn (Write Protect) pin of the NAND Flash is not supported. When this function is needed, prepare it on an external circuit. TMPA910CRA- 312 2010-06-02 TMPA910CRA 3.11.2 Block Diagram NAND-Flash Controller RD/WR FIFO0/1 NDECCRD0-2 AHB-Bus I/F NDD7-NDD0 FIFO-0 RD/WR 16Byte FIFO-1 NDRSCA0-3 AHB-Bus NDRSCD0-3 NDFDTR 16Byte R/S ECC Generator/ Calculator 10Byte Buffer Hamming ECC Generator Auto Load Sequencer NDREn NDWEn NDFMCR0-2 NDRB NDALE NDCLE NDCE0n INTS [14] DMA request NDFINTC NDCE1n DMA clear TMPA910CRA- 313 2010-06-02 TMPA910CRA 3.11.3 Operation Description a. Setting the commands and addresses to the NAND-Flash memory The commands and addresses for executing instructions such as Page Read and Page Write to the NAND-Flash memory are set by software. The NDCExn, NDCLE, and NDALE pins are configured by the NDFMCR0<CEx, CLE, ALE> register. Reading/Writing of NAND-Flash memory are executed by reading/writing the NDFDTR register. The setting the AC timing can be adjusted by using the NDFMCR2 SPHW[2:0], SPLR[2:0], SPHR[2:0]> register. <SPLW[2:0], NDCLE NDALE NDCExn NDREn NDWEn NDRB NDD7-NDD0 NDFMCR0 <CLE> = 1 <CEx> = 1 <CLE> = 0 <ALE> = 1 TMPA910CRA- 314 <ALE> = 0 2010-06-02 TMPA910CRA b. Reading data from the NAND-Flash memory in page units and writing data to the built-in RAM In this section, a high-speed data read function with a smaller burden to the CPU is implemented by using the built-in DMA controller in addition to two 32bit x 4word FIFOs contained in the NDFC and the Autoload function. Note: Please use the DMA function for the data read that uses the Autoload function. Because the Autoload function at data read starts automatically after detection of a rising edge of the NDRB pin in the state of NDFMCR1<ALS>= 1, the settings of steps (1) and (2) below must be performed after command setting to the NAND-Flash before address setting. (1) Assign the NDFC to an arbitrary channel of the DMA controller and set the relevant registers. The following is an example in which the NDFC is assigned to DMAC channel 0: DMACC0SrcAddr Address of NDFDTR DMACC0DestAddr Address of the built-in RAM DMACC0Control <Swidth[2:0]> = 0y010 (32 bits), <Dwidth[2:0]> = 0y010 (32 bits), <SBSize[2:0]> = 0y001 (4 beats), <TransferSize[11:0]> = 0x80 (512 Bytes/ 4 Bytes) DMACC0Configuration <FlowCntrl[13:11]> = 0y010 (Peripheral to Memory), <ITC> = 1 (DMA termination interrupt is enabled.) (2) Write 0 to the NDFMCR1<SELAL> register and 1 to the NDFMCR1<ALS> register. When Step (2) is performed, the NDFC begins detecting a rising edge of the R/B pin, and after detecting a rising edge, starts a read cycle of 1-byte data. Each time the NDFC reads 1-byte data, it stores the read data in the first-stage 16-byte FIFO (FIFO-0) and generates the ECC by entering the data to either Hamming Code ECC calculator or Reed-Solomon ECC calculator depending on the setting of the NDFMCR1<ECCS> register. When FIFO-0 is filled up with data, the FIFO-1) takes over the data storage for continued data read. In addition, the NDFC asserts a DMA transfer request to the DMAC at the fill-up of FIFO-0 to request the transfer of the FIFO-0 data to the built-in RAM. Data can be read efficiently at a higher speed by switching between two 16-byte FIFOs in this way. When a total of 512 bytes of data has been read, the DMAC asserts a DMA termination interrupt and the CPU uses the interrupt to start the next process. TMPA910CRA- 315 2010-06-02 TMPA910CRA The following shows a conceptual timing chart of the data read timing by DMA. NDFMCR1<ALS> register NDRB NDREn 1 2 16 17 18 FIFO used for read from the FIFO to be read by the DMAC 33 34 1 0 NAND-Flash 32 0 48 497 498 0 1 512 1 0 1 DMAC end interrupt If DMAC cannot read the data from a FIFO of the NDFC when both FIFO-0 and FIFO-1 are full, the autoload function is suspended for that duration. c. Data writing from the built-in RAM to the NAND-Flash memory in page units The following is a description of data writing using the Autoload function that is performed similarly to data reading from the NAND-Flash. For execution, perform the settings described in steps (1) and (2) below. Note: Please use the DMA function for the data read that uses the autoload function. (1) Assign the NDFC to an arbitrary channel of the DMA controller and set the relevant registers. The following is an example in which the NDFC is assigned to DMAC channel 0: DMACC0SrcAddr Address of the built-in RAM DMACC0DestAddr Address of NDFDTR DMACC0Control <Swidth[2:0]> = 0y010 (32 bits), <Dwidth[2:0]> = 0y010 (32 bits), <SBSize[2:0]> = 0y001 (4 beats), <TransferSize[11:0]> = 0x80 (512 Byte/4 Byte) DMACC0Configuration <FlowCntrl> = 0y001(Memory to Peripheral), <ITC> = 1 (DMA termination interrupt is enabled.) TMPA910CRA- 316 2010-06-02 TMPA910CRA (2) Write 1 to the NDFMCR1<SELAL> register and 1 to the NDFMCR1<ALS> register. When step (2) is performed, the NDFC asserts a DMA request, because both FIFO-0 and FIFO-1 are empty, to have the DMA controller transfer data from the built-in RAM to FIFO-0 and FIFO-1. When the data transfer from the DMA controller to FIFO-0 and FIFO-1 is terminated, the NDFC uses the FIFO-0 data to start a data write cycle to NAND-Flash. Each time the NDFC writes data, it generates the ECC by entering the data to either Hamming Code ECC calculator or Reed-Solomon ECC calculator depending on the setting of the NDFMCR1<ECCS> register. When FIFO-0 becomes empty, the FIFO-1 takes over the data extraction for continued data write. In addition, the NDFC asserts a DMA transfer request to the DMAC at the time of FIFO-0's becoming empty to request the data transfer from the built-in RAM to FIFO-0. Data can be written efficiently at a higher speed by switching between two 16-byte FIFOs in this way. When a total of 512 bytes of data has been written, the DMAC asserts a DMA termination interrupt and the CPU uses the interrupt to start the next process. The following shows a conceptual timing chart of the data write timing by DMA. NDFMCR1<ALS> register 1 2 16 17 18 32 33 34 48 497 498 512 NDWEn FIFO used for write to the 1 0 0 1 NAND-Flash FIFO to be writen by the DMAC 0 1 0 1 1 DMAC end interrupt Note: Write operation to the NAND-Flash memory is not terminated by the Autoload function of the NDFC at the time of assertion of a DMAC end interrupt. Ensure that the NDFMCR1<ALS> = 0 during the DMAC end interrupt processing and then execute the next process (processing of the ECC). If DMAC cannot be write the data to FIFO of the NDFC when FIFO-0 and FIFO-1 are full, the Autoload function is suspended for that duration. TMPA910CRA- 317 2010-06-02 TMPA910CRA d. ECC read or write to or from the redundant area The Autoload function cannot be used. Execute read or write to or from NAND-Flash by software as in the case of setting a command or address. e. Waveform adjusting function for NDREn and NDWEn When setting of a command and address, data read, or data write is performed to the NDFDTR register, the NDFC generates waveforms for the NDREn and NDWEn pins. At this time, the Low width and High width for the NDREn and NDWEn pins can be adjusted. Adjustment should be done in accordance with the AC specifications including the NDFC operation clock, HCLK (up to 100 MHz) and the NAND-Flash access time. (For details, refer to the electrical characteristics.) The following figure shows a timing chart example in which continuous accesses are made when NDFMCR2<SPLW[2:0]> = 0y011, NDFMCR2<SPLR[2:0]> = 0y011, NDFMCR2<SPHW[2:0]> = 0y010, and NDFMCR2<SPHR[2:0]> = 0y010. (The data drive time becomes longer at data write.) HCLK 3clk 2clk NDREn NDD7-NDD0 NDWEn NDD7-NDD0 IN (NAND-Flash) 3clk IN (NAND-Flash) 2clk OUT (NAND-Flash) TMPA910CRA- 318 OUT (NAND-Flash) 2010-06-02 TMPA910CRA 3.11.4 ECC Control This section describes ECC control. NAND-Flash memory devices may inherently include error bits. It is therefore necessary to implement the error correction processing using ECC (Error Correction Code). Figure 3.11.1 shows a basic flowchart for ECC control. Data Write Data Read Valid data write to NAND-Flash Valid data read from NAND-Flash Valid data write to Valid data write to ECC generator ECC generator ECC read ECC read from ECC generator from NAND-Flash Write ECC to ECC read NAND-Flash from ECC circuit END Is there Error? Yes Error correct process No END Figure 3.11.1 Basic Flow of ECC Control Write: 1. When data is written to the actual NAND-Flash memory, the ECC generator in the NDFC simultaneously generates ECC for the written data. 2. The ECC is written to the redundant area in the NAND-Flash separately from the valid data. Read: 1. When data is read from the NAND-Flash memory, the ECC generator in the NDFC simultaneously generates ECC for the read data as in the case of data writing. 2. The ECC written to the redundant area from the NAND-Flash memory is read. The ECC at the time of data writing and that at the time of data reading are used to calculate error bits for correction. TMPA910CRA- 319 2010-06-02 TMPA910CRA 3.11.4.1 Difference between Hamming Code ECC Calculation Method and Reed-Solomon ECC Calculation Method The NDFC includes an ECC generator supporting 2LC and 4LC. The ECC calculation using Hamming codes (supporting 2LC) generates 22 bits of ECC for every 256 bytes of valid data and is capable of detecting and correcting a single-bit error for every 256 bytes. Error bit detection calculation and correction must be implemented by software. When using Smart Media, Hamming codes should be used. The ECC calculation using Reed-Solomon codes (supporting 4LC) generates 80 bits of ECC for every 1 byte to 512 bytes of valid data and is capable of detecting and correcting error bits at 4-symbol for every 512 bytes. Although the Reed-Solomon ECC calculation method needs error bit correction to be implemented by software as in the case of the Hamming Code ECC calculation method, error bit detection calculation is supported by hardware. The differences between Hamming Code ECC calculation method Reed-Solomon ECC calculation method are summarized in Table 3.11.1 and Table 3.11.1 Differences between Hamming Code ECC Calculation Method and Reed-Solomon ECC Calculation Method Hamming Reed Solomon Maximum number of correctable errors 1-bit Number of ECC bits 22 bits/256 bytes 80 bits / up to 512 bytes Error bit detection method Supported by software. Detected by hardware. Error bit correction method Supported by software. Supported by software. Error bit detection time Supported by software, so it depends on how the software is made. See the table below. Others Supports SmartMedia. Number of Error Bits 4-symbol (All the 8 bits at one symbol are correctable.) Reed-Solomon Error Bit Detection Time (Units: HCLK) 4 813 (max) 3 648 (max) 2 358 (max) 1 219 (max) 0 1 Remarks These values indicate the total number of clocks for detecting error bit(s) but do not include the register read/write time by the CPU. TMPA910CRA- 320 2010-06-02 TMPA910CRA 3.11.4.2 Error Correction Methods Hamming ECC * The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error correction process must be performed in units of 256 bytes (22 bits of ECC). The following explains how to implement error correction on 256 bytes of valid data using 22 bits of ECC. * If the NAND-Flash memory to be used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated several times to cover the entire page. 1. The calculated ECC and the ECC in the redundant area (Note 1) are rearranged, so that the lower 2 bytes of each ECC represent line parity (LPR15: 0) and the upper 1 byte (of which the upper 6 bits are valid) represents column parity (CPR7: 2). 2. The two rearranged ECCs are XORed. 3. If the XOR result is 0, indicating an ECC match, the error correction process ends normally (no error). If the XOR result is other than 0, it is checked whether or not the error data can be corrected. 4. If the XOR result contains only one ON bit, it is determined that a single-bit error exists in the ECC data itself and the error correction process terminates here (error not correctable). 5. If every two bits of bits 0 to 15 and bits 18 to 23 of valid data in the XOR result are either 0y01 or 0y10, it is determined that the error data is correctable and error correction is performed accordingly. If the XOR result contains either 0y00 or 0y11, it is determined that the error data is not correctable and the error correction process terminates abnormally. Example of Correctable XOR Result Binary Example of Uncorrectable XOR Result 10 01 10 00 Column parity 10 11 10 00 Column parity 10 10 01 10 Line parity 10 10 01 10 Line parity 01 01 10 10 01 01 10 10 6. For correction of the data, the line information in error is created from the line parity of the XOR result and the bit information is created from the column parity and then the error bit is inverted. The error correction is now completed. Example: When the XOR result is 0y10_01_10_00_10_10_01_10_01_01_10_10 Convert two bytes of line parity into one byte. (101, 010) Convert six bits of column parity into three bits. (101010) Line parity: 10 10 01 10 01 01 10 10 1 1 0 1 0 0 1 1 = 0xD3 In this case, an error exists at address 0xD3. Note that this address is not an absolute address but a relative address in 256 bytes. Due care must be used when correcting this error. Column parity: 10 01 10 1 0 1 =5 Error in bit 5 Error correction is performed by inverting the data in bit 5 at address 0xD3. TMPA910CRA- 321 2010-06-02 TMPA910CRA Reed-Solomon ECC * The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND-Flash memory to be used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated several times to cover the entire page. * Basically no calculation is needed for error correction. If error detection is performed properly, the NDFC only needs to refer to the error address and error bit. However, it may be necessary to convert the error address, as explained below. 1. If the error address indicated by the NDRSCAn register is in the range of 0x000 to 0x007, this error exists in the ECC area and no correction is needed in this case. (It is not able to correct the error in the ECC area. Note, however, that if the error exists in the ECC area, this LSI has only the ability to correct errors up to 4 symbols including the error in the ECC area. 2. If the error address indicated by the NDRSCAn register is in the range of 0x008 to 0x207, the error address is obtained by subtracting this address from 0x207. Example 1: When NDRSCAn = 0x005 and NDRSCDn = 0x04 = 0y0000_0100 Because the error address is in the range of 0x000 to 0x007, no correction is needed. (Although an error exists in bit 2, no correction is needed.) Example 2: When NDRSCAn = 0x083 and NDRSCDn = 0x81 = 0y1000_0001 Error correction is performed by inverting the data in bits 7 and 0 at address 0x184 (0x207 - 0x083). Note : If the error address (after conversion) is in the range of 0x000 to 0x007, it indicates that an error bit exists in redundant area (ECC). In this case, no error correction is needed. If the number of error bits is not more than 4 symbols, the Reed-Solomon ECC calculation method calculates each error bit precisely even if it is in the redundant area (ECC). TMPA910CRA- 322 2010-06-02 TMPA910CRA 3.11.5 Description of Registers The following lists the SFRs: Table 3.11.2 SFR List Register Address Name (base+) Base address = 0xF201_0000 Description NDFMCR0 0x0000 NAND-Flash Control Register 0 NDFMCR1 0x0004 NAND-Flash Control Register 1 NDFMCR2 0x0008 NAND-Flash Control Register 2 NDFINTC 0x000C NAND-Flash Interrupt Control Register NDFDTR 0x0010 NAND-Flash Data Register NDECCRD0 0x0020 NAND-Flash ECC Read Register 0 NDECCRD1 0x0024 NAND-Flash ECC Read Register 1 NDECCRD2 0x0028 NAND-Flash ECC Read Register 2 NDRSCA0 0x0030 NAND-Flash Reed-Solomon Calculation Result Address Register 0 NDRSCD0 0x0034 NAND-Flash Reed-Solomon Calculation Result Data Register 0 NDRSCA1 0x0038 NAND-Flash Reed-Solomon Calculation Result Address Register 1 NDRSCD1 0x003C NAND-Flash Reed-Solomon Calculation Result Data Register 1 NDRSCA2 0x0040 NAND-Flash Reed-Solomon Calculation Result Address Register 2 NDRSCD2 0x0044 NAND-Flash Reed-Solomon Calculation Result Data Register 2 NDRSCA3 0x0048 NAND-Flash Reed-Solomon Calculation Result Address Register 3 NDRSCD3 0x004C NAND-Flash Reed-Solomon Calculation Result Data Register 3 TMPA910CRA- 323 2010-06-02 TMPA910CRA 1. NDFMCR0 (NAND-Flash Control Register 0) Address = (0xF201_0000) + (0x0000) Bit Bit Symbol Reset Type Description Value [31:12] - - Undefined [11] RSECCL R/W 0y0 Read as undefined. Write as zero. Reed Solomon ECC-Latch 0y0: Disable (Enable 80-bit F/F update.) 0y1: Enable (Disable 80-bit F/F update.) [10] RSEDN R/W 0y0 Reed-Solomon operation select 0y0: Read 0y1: Write [9] RSESTA WO 0y0 Reed-Solomon error calculation start 0y0: - 0y1: Start [8] RSECGW R/W 0y0 Reed-Solomon ECC-Generator write enable 0y0: Disable 0y1: Enable [7] WE R/W 0y0 Write operation enable 0y0: Disable 0y1: Enable [6] ALE R/W 0y0 NDALE pin control 0y0: Output 0 0y1: Output 1 [5] CLE R/W 0y0 NDCLE pin control 0y0: Output 0 0y1: Output 1 [4] CE0 R/W 0y0 NDCE0n pin control 0y0: Output 1 0y1: Output 0 [3] CE1 R/W 0y0 NDCE1n pin control 0y0: Output 1 0y1: Output 0 [2] ECCE R/W 0y0 ECC circuit enable 0y0: Disable 0y1: Enable [1] BUSY RO 0y0 NAND-Flash status Read: 0y0: Ready 0y1: Busy Write: [0] ECCRST WO 0y0 Invalid ECC circuit reset 0y0: - 0y1: Reset TMPA910CRA- 324 2010-06-02 TMPA910CRA [Description] a. <RSECCL> The <RSECCL> bit is used only for Reed-Solomon codes. When Hamming codes are used, this bit should be set to 0. The Reed-Solomon processing unit is comprised of two circuits: an ECC generating circuit and a circuit to calculate the error address and error bit position from the ECC. No special care is needed if ECC generation and error calculation are performed in series. If these operations need to be performed in parallel, the intermediate code used for error calculation must be latched while the calculation is being performed. The <RSECCL> bit is provided to enable the latch operation for the intermediate code generated from the ECC for written data and the ECC for read data to calculate the error address and error bit position. When <RSECCL> is set to 1, the intermediate code is latched so that no ECC is transferred to the error calculator even if the ECC generator updates the ECC, thus allowing the ECC generator to generate the ECC for another page while the ECC calculator is calculating the error address and error bit position. At this time, the ECC generator can perform both Write and Read operations. When <RSECCL> is set to 0 the latch is released and the contents of the ECC calculator are updated sequentially as the data in the ECC generator is updated. Reed-Solomon ECC NDECCRDn register Flow of data F/F 80 bits <RSECCL> = 1 Latch_ON Reed-Solomon <RSECCL> = 0 Latch_OFF ECC b. <RSEDN> The <RSEDN> bit is used only for Reed-Solomon codes. When Hamming codes are used, this bit should be set to 0. For a write operation, this bit should be set to 1 (for write) to generate ECC. The ECC read from the NDECCRDn register is written to the redundant area of the NAND-Flash memory. For a read operation, this bit should be set to 0 (for Read). Then, valid data is read from the NAND-Flash memory and the ECC written in the redundant area of the NAND-Flash memory is read to generate an intermediate code for calculating the error address and error bit position. TMPA910CRA- 325 2010-06-02 TMPA910CRA c. <RSESTA> The <RSESTA> bit is used only for Reed-Solomon codes. The error address and error bit position are calculated using an intermediate code generated from the ECC for written data and the ECC for read data Writing 1 to <RSESTA> starts this calculation. d. <RSECGW> The <RSECGW> bit is used only for Reed-Solomon codes. When Hamming codes are used, this bit should be set to 0. Since the valid data part and the ECC are processed differently in this circuit, reading the valid data part and reading the ECC should be managed separately by software. To read valid data from the NAND-Flash memory, set <RSECGW> to 0 (Disable). To read the ECC written in the redundant area of the NAND-Flash, set <RSECGW> to 1 (Enable). Note 1: Valid data that use the DMAC and ECC cannot be read continuously. After valid data has been read, data transfer should be stopped once to change the <RSECGW> bit from 0 to 1 before ECC is read. Note 2: Immediately after ECC is read from the NAND-Flash memory, accesses (read/write) to the NAND-Flash memory or error bit calculation cannot be performed for a duration of 20 system clocks that is used for internal processing. Wait processing or other by software is needed. e. <WE> The <WE> bit is used for both Hamming and Reed-Solomon codes. This bit is used to control activation of the NDWEn pin. This is a protective register to prevent the NDWEn pin from being activated inadvertently for the NAND-Flash memory. f. <ALE>, <CLE>, <CE0>, <CE1> The <ALE>, <CLE>, <CE0> and <CE1> bits are used for both Hamming and Reed-Solomon codes. These pins are used to control the pins of the NAND-Flash memory. g. <ECCE> The <ECCE> bit is used for both Hamming and Reed-Solomon codes. This bit is used to control the ECC circuit. To reset the ECC (to write 1 to <ECCRST>), this bit must have been enabled (1). TMPA910CRA- 326 2010-06-02 TMPA910CRA h. <BUSY> The <BUSY> bit is used for both Hamming and Reed-Solomon codes. This bit is used to check the state of the NAND-Flash memory (NDRB pin). It is set to 1 when the NAND-Flash is "busy" and to 0 when it is "ready". Since the NDFC incorporates a noise filter of several clocks, a change in the NDR/B pin state is reflected on the <BUSY> flag after some delay. Delay Read command Address input Sensing <BUSY> flag NDWEn pin NDCLE pin NDALE pin NDRB pin <BUSY> flag i. <ECCRST> The <ECCRST> bit is used for both Hamming and Reed-Solomon codes. To reset the Hamming ECC, set NDFMCR1<ECCS> = 0 (to reset the Reed-Solomon ECC, set NDFMCR1<ECCS> = 1), then write 1 once to this bit, and the ECC in this circuit is reset (reset is released automatically). The contents of the NDECCRDn register are also reset at the same time. When you reset ECC, set <ECCE> to 1. TMPA910CRA- 327 2010-06-02 TMPA910CRA 2. NDFMCR1 (NAND-Flash Control Register 1) Address = (0xF201_0000) + (0x0004) Bit Bit Symbol Type Reset Description Value [31:16] - - Undefined [15:12] STATE[3:0] RO 0y0000 Read as undefined. Write as zero. Read: Status of the Reed-Solomon ECC calculator (Valid after calculation processing is started.) 0y0000: Calculation ended with no error. 0y0001: Calculation ended with errors of more than 5 symbols (uncorrectable). 0y0010, 0y0011: Calculation ended with errors of 4 symbols or less (correctable). 0y0100-0y1111: Calculating [11:10] SERR[1:0] RO Undefined Write: Invalid Read: Number of errors in the Reed-Solomon ECC calculator (Valid after calculation processing ended.) 0y00: 1-address error 0y01 : 2-address error 0y10: 3-address error Write: [9] SELAL R/W 0y0 0y11: 4-address error Invalid Autoload function select 0y0: Data read from the NAND-Flash 0y1: Data write to the NAND-Flash [8] ALS R/W 0y0 Autoload start (at write time) 0y0: - 0y1: Start Autoload status (at read time) 0y0: Before or after execution 0y1: Being executed [7:2] - - Undefined Read as undefined. Write as zero. [1] ECCS R/W 0y0 ECC circuit select 0y0: Hamming 0y1: Reed-Solomon [0] - - Undefined Read as undefined. Write as zero. TMPA910CRA- 328 2010-06-02 TMPA910CRA [Description] a. <STATE[3:0]>, <SERR[1:0]>, The <STATE3:0> and <SEER1:0> bits are used only for Reed-Solomon codes. When Hamming codes are used, these bits have no meaning. These bits are used as flags to indicate the states of error address and error bit calculation results. b. <SELAL> The <SELAL> bit is used for both Hamming and Reed-Solomon codes. This bit is used to select data read or data write for the NAND-Flash when the Autoload function is executed. c. <ALS> The <ALS> bit is used for both Hamming and Reed-Solomon codes. This is the register that controls the function to transfer data read/write for the NAND-Flash at high speed by using the DMAC. Writing 1 to <ALS> enables the 16-byte FIFO0/FIFO1. In addition, a read operation allows the user to know the status of the Autoload function. (When 512-byte read or write is executed by the Autoload function, this register is cleared to 0.) d. <ECCS> The <ECCS> bit is used to select whether to use Hamming codes or Reed-Solomon codes. This bit is set to 0 for using Hamming codes and to 1 for using Reed-Solomon codes. It is also necessary to set this bit for resetting ECC. TMPA910CRA- 329 2010-06-02 TMPA910CRA 3. NDFMCR2 (NAND-Flash Control Register 2) Address = (0xf201_0000) + (0x0008) Bit Bit Symbol Type Reset Description Value [31:15] - - Undefined Read as undefined. Write as zero. [14:12] SPLW R/W 0y000 NDWEn Low pulse width setting 0y000: Reserved 0y001: 1 cycle of HCLK 0y010: 2 cycles of HCLK 0y011: 3 cycles of HCLK 0y100: 4 cycles of HCLK 0y101: 5 cycles of HCLK 0y110-0y111: Reserved [11] - - Undefined Read as undefined. Write as zero. [10:8] SPHW R/W 0y000 NDWEn High pulse width setting 0y000: Reserved 0y001: 1 cycle of HCLK 0y010: 2 cycles of HCLK 0y011: 3 cycles of HCLK 0y00: 4 cycles of HCLK 0y101: 5 cycles of HCLK 0y110-0y111: Reserved [7] - - Undefined Read as undefined. Write as zero. [6:4] SPLR R/W 0y000 NDREn Low pulse width setting 0y000: Reserved 0y001: 1 cycle of HCLK 0y010: 2 cycles of HCLK 0y011: 3 cycles of HCLK 0y100: 4 cycles of HCLK 0y101: 5 cycles of HCLK 0y110-0y111: Reserved [3] - - Undefined Read as undefined. Write as zero. [2:0] SPHR R/W 0y000 NDREn High pulse width setting 0y000: Reserved 0y001: 1 cycle of HCLK 0y010: 2 cycles of HCLK 0y011: 3 cycles of HCLK 0y100: 4 cycles of HCLK 0y101: 5 cycles of HCLK 0y110-0y111: Reserved [Description] a. <SPLW>, <SPHW>, <SPLR>, <SPHR> These are registers to set the Low and High pulse width of the NDREn and NDWEn pins. The pulse width is given by the set value x the period of HCLK. Setting 0y000, 0y110 and 0y111 are prohibited. TMPA910CRA- 330 2010-06-02 TMPA910CRA 4. NDFINTC (NAND-Flash Interrupt Control Register) Address = (0xF201_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] RSEIC WO 0y0 Read as undefined. Write as zero. Read: Reed-Solomon calculator end interrupt clear register 0y0: - 0y1: Clear [6] RSEEIS RO 0y0 Write: Invalid Read: Reed-Solomon calculator end interrupt masked status 0y0: Interrupt not requested 0y1: Interrupt requested [5] RSERIS RO 0y0 Write: Invalid Read: Reed-Solomon calculator end interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested Write: [4] RSEIE R/W 0y0 Invalid Reed-Solomon calculator end interrupt enable register 0y0: Disable interrupt requests 0y1: Enable interrupt requests [3] RDYIC WO 0y0 NAND-Flash ready interrupt clear register 0y0: - 0y1: Clear [2] RDYEIS RO 0y0 Read: NAND-Flash ready interrupt masked status 0y0: Interrupt not requested 0y1: Interrupt requested [1] RDYRIS RO 0y0 Write: Invalid Read: NAND-Flash ready interrupt raw status 0y0: Interrupt not requested 0y1: Interrupt requested Write: [0] RDYIE R/W 0y0 Invalid NAND-Flash ready interrupt enable register 0y0: Disable interrupt requests 0y1: Enable interrupt requests TMPA910CRA- 331 2010-06-02 TMPA910CRA [Description] a. <xxxIC>, <xxxEIS>, <xxxRIS>, <xxxIE> These are 4-bit registers to support two types of interrupts: a READY interrupt that occurs when the status of the monitored NDRB pin changes from Busy to Ready and a Reed-Solomon calculation end interrupt that occurs when Reed-Solomon calculation of address and data ends. The NDFC asserts one interrupt request obtained by ORing these two interrupt requests to the interrupt controller. Therefore, the register contents check during interrupt processing and the processing appropriate to the individual interrupt source are required. The following figure shows the relationship between these registers: <***IE> : Enable register (R/W) <***EIS> : Masked interrupt request status (RO) D Q D Q Interrupt request signal D Q (1 shot) <***RIS> : Raw interrupt request status (RO) D Q <***IC> : Clear register (WO) TMPA910CRA- 332 2010-06-02 TMPA910CRA 5. NDFDTR (NAND-Flash Data Register) Address = (0xF201_0000) + (0x0010) Bit [31:0] Bit Symbol DATA[31:0] Type R/W Reset Description Value Undefined Data register [Description] a. <DATA[31:0]> This register is accessed when reading or writing data to or from the NAND-Flash memory or setting commands and addresses to the memory. When data is written to this register, the data is written to the NAND-Flash memory. When a read operation is made to this register, data is read from the NAND-Flash memory. One-word transfer can be used through the DMA operation. Note: Although this register is readable and writable, it contains no F/F. If reading is done after writing, the written data is not held because the operations for writing and reading are different. TMPA910CRA- 333 2010-06-02 TMPA910CRA 6. NDECCRD0 (NAND-Flash ECC Read Register 0) Address = (0xF201_0000) + (0x0020) Bit Bit Symbol [31:0] CODE0[31:0] Type RO Reset Description Value 0x00000000 Register to store ECC 7. NDECCRD1 (NAND-Flash ECC Read Register 1) Address = (0xF201_0000) + (0x0024) Bit Bit Symbol [31:0] CODE1[31:0] Type RO Reset Description Value 0x00000000 Register to store ECC 8. NDECCRD2 (NAND-Flash ECC Read Register 2) Address = (0xF201_0000) + (0x0028) Bit Bit Symbol Type Reset Description Value [31:16] - - Undefined Read as undefined. [15:0] CODE2[15:0] RO 0x0000 Register to store ECC [Description] a. <CODE0[31:0]>, <CODE1[31:0]>, <CODE2[15:0]> This register is used to read the ECC calculated in this circuit. When 0 is written to NDFMCR0<ECCE> after read/write ends, ECC is prepared in this register (when the value of NDFMCR0<ECCE> changes from 1 to 0 the ECC in this register is updated). The Hamming ECC calculation generates 22 bits of ECC for every 256 bytes of valid data and the Reed-Solomon ECC calculation generates 80 bits of ECC for every 1 byte to 512 bytes of valid data. Three 32-bit width registers are provided to store 80 bits. The table below shows the format for storing ECC. Note: Before reading ECC from the NAND Flash ECC register, be sure to set NDFMCR0<ECCE> to 0. The ECC in the NAND Flash ECC register is updated when NDFMCR0<ECCE> changes from 1 to 0. Also note that when the ECC in the ECC generator is reset by NDFMCR0<ECCRST>, the contents of this register are not reset. TMPA910CRA- 334 2010-06-02 TMPA910CRA Register Name NDECCRD0<15:0> NDECCRD0<31:16> NDECCRD1<15:0> NDECCRD1<31:16> NDECCRD2<15:0> Hamming Reed-Solomon [15:0] Line parity [15:0] (for the first 256 bytes) R/S ECC 79:64 [23:18] Column parity [31:16] (for the first 256 bytes) R/S ECC 63:48 [15:0] Line parity [15:0] (for the second 256 bytes) R/S ECC 47:32 [23:18] Column parity [31:16] (for the second 256 bytes) R/S ECC 31:16 Not used [15:0] R/S ECC 15:0 The table below shows examples of writing ECC on the redundant area of the NAND-Flash memory. When using Hamming codes with SmartMedia, the addresses of the redundant area are specified by the physical format of SmartMedia. For details, refer to the SmartMedia Physical Format Specifications. Reed-Solomon NDECCRD0 [31:0] NAND-Flash Address Upper 8 bits [79:72] address 518 R/S ECC 79:48 8 bits [71:64] address 519 8 bits [63:56] address 520 Lower 8 bits [55:48] address 521 NDECCRD1 Upper 8 bits [47:40] address 522 [31:0] R/S ECC 47:16 8 bits [39:32] address 523 8 bits [31:24] address 524 Lower 8 bits [23:16] address 525 NDECCRD2 [15:0] Upper 8 bits [15:8] address 526 R/S ECC 15:0 Lower 8 bits [7:0] address 527 TMPA910CRA- 335 2010-06-02 TMPA910CRA 9. NDRSCA0 (NAND-Flash Reed-Solomon Calculation Result Address Register 0) Address = (0xF201_0000) + (0x0030) Bit Bit Symbol Type Reset Description Value [31:10] - - Undefined Read as undefined. [9:0] AL RO 0x000 Register to store Reed-Solomon error 0 address 10. NDRSCD0 (NAND-Flash Reed-Solomon Calculation Result Data Register 0) Address = (0xF201_0000) + (0x0034) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. [7:0] DATA RO 0x00 Register to store Reed-Solomon error 0 data [Description] a. <AL>,<DATA> If an error is found at only one address, the error address is stored in the NDRSCA0 register and the error data in the NDRSCD0 register. If errors are found at two addresses, the error addresses are stored in the NDRSCA0 and NDRSCA1 registers and the error data in the NDRSCD0 and NDRSCD1 registers. Valid error addresses are stored in this way when error bits are found at four or less addresses. For the number of error addresses, read the contents of NDFMCR1<SEER[1:0]>. * NDRSCAx (NAND-Flash Reed-Solomon Calculation Result Address Register-x) (x = 0 to 3) * NDRSCDx (NAND-Flash Reed-Solomon Calculation Result Data Register-x) (x = 0 to 3) As for the above registers, the structure and description are same as NDRSCA0 and NDRSCD0. Please refer to the description of NDRSCA0 and NDRSCD0. About the name and address of registers, please refer to Table 3.11.2. TMPA910CRA- 336 2010-06-02 TMPA910CRA 3.11.6 Examples of Accessing the NAND-Flash The following example shows the example of NAND Flash memory accessing. This example is showing the set-up procedure. Please note that we do not warrant the operation shown below. Please use it as a guide in programming. (1) Page write (2LC type) Main Program ; ; ***** Initialize NDFC ***** ; Condition: 8bit-bus, CE0, SLC, 512 Byte/Page, Hamming ; NDFMCR0 0x0000_0010 ; NDCE0n pin = 0, ECC-disable NDFMCR1 0x0000_0000 ; ECC = Hamming NDFMCR2 0x0000_3343 ; NDWEn L = 3clks,H =3clks, ; NDREn L = 4clks,H = 3clks NDFINTC 0x0000_0000 ; ALL Interrupt Disable ; ***** Setting Command, Address to NAND-Flash ***** ; NDFMCR0 0x0000_00b0 ;NDCE0n pin = 0, NDCLE = 1, NDALE = 0 NDFDTR 0x80 ; Write Command (1 cycle of Page-Program) st- NDFMCR0 0x0000_00d0 ;NDCE0n pin = 0, NDCLE = 0, NDALE = 1 NDFDTR 0x?? ; Write Address (n-times) NDFMCR0 0x0000_0095 ;NDCE0n pin = 0, NDCLE = 0, NDALE = 0 ; ECC Enable and Reset ; ***** Writing 512Byte Valid data ***** ; Have the DMAC and INTC support the Autoload function of 512-byte write data. (Details are omitted.) (Including INTTC interrupt enable) NDFMCR1 0x0000_0300 ; <SELALS> = 1, Start Auto-Load ; INTTC Interrupt Processing Program NDFMCR1 Read and check ; Check that <ALS> = 0 (end). If not, perform polling. NDFMCR0 0x0000_0090 ; ECC-Disable Return to the main program Main Program ; ***** Reading ECC from NDFC ***** NDECCRD0 Read ; ECC for the first 256 bytes NDECCRD1 Read ; ECC for the second 256 bytes ; ***** Writing Dummy data & ECC code***** ; NDFDTR 0x?? ; Write dummy data (1 byte x 8 times) NDFDTR ECC ; Write ECC (1 byte x 3 times) ; Write to D520: LPR7:0 ; Write to D521: LPR15:8 For second 256 bytes For second 256 bytes ; Write to D522: CPR5:0+11b For second 256 bytes ; NDFDTR 0x?? ; Write dummy data (1 byte x 2 times) NDFDTR ECC ; Write ECC (1byte x 3 times) ; Write to D525:LPR7:0 ; Write to D526:LPR15:8 For first 256 bytes ; Write to D527:CPR5:0+11b For first 256 bytes TMPA910CRA- 337 For first 256 bytes 2010-06-02 TMPA910CRA ; ***** Set Page program command ***** ; NDFMCR0 0x0000_00b0 ;NDCEn pin = 0, NDCLE = 1, NDALE = 0 NDFDTR 0x10 ; Write Command(2nd cycle of Page-Program) NDFMCR0 0x0000_0010 ;NDCEn pin = 0, NDCLE = 0, NDALE = 0 ; ***** Wait till Page-Program End ***** ; ; Wait for the page program to end. Whether or not the program has ended can be checked by two methods: ; 1) write a read status command to read the status from the NDD7 to NDD0 pins (polling method), and : 2) use a Ready interrupt by detection of NDRB pin rising edge. The following describes a case in which the ; second method is used. ; NDFINTC 0x0000_0009 ; Clear/enable RDY interrupt Have the INTC enable an NDFC interrupt (Details are omitted) INTNDFC Interrupt Processing Program End processing Return to the main program TMPA910CRA- 338 2010-06-02 TMPA910CRA (2) Page read (2LC type) Main Program ; ; ***** Initialize NDFC ***** ; condition: 8bit-bus, CE0, SLC, 512 Bytes/Page, Hamming ; NDFMCR0 0x0000_0010 ; NDCEn pin = 0, ECC-disable NDFMCR1 0x0000_0000 ; ECC = Hamming NDFMCR2 0x0000_3343 ; NDWEn L = 3clks,H = 3clks, ; NDREn L = 4clks,H = 3clks NDFINTC 0x0000_0000 ; ALL Interrupt Disable ; ***** Setting Command, Address to NAND-Flash ***** ; NDFMCR0 0x0000_00b0 ;NDCEn pin = 0, NDCLE = 1, NDALE = 0 NDFDTR 0x00 ; Write Command (1 cycle of Page-Read) st- ; ***** Reading 512Byte Valid data ***** Have the DMAC and INTC support the Autoload function of 512-byte read data. (Details are omitted.) (Including INTTC interrupt enable) NDFMCR1 0x0000_0100 ; <SELALS> = 0, Start Auto-Load NDFMCR0 0x0000_00d0 ; NDCEn pin = 0, NDCLE = 0, NDALE = 1 NDFDTR 0x?? ; Write Address (n-times) NDFMCR0 0x0000_00b0 ; NDCEn pin = 0, NDCLE = 1, NDALE = 0 NDFDTR 0x030 ; Read Command(2nd cycle of Page-Read) NDFMCR0 0x0000_0015 - ; NDCEn pin = 0, NDCLE = 0, NDALE = 0 ; ECC Enable and Reset INTTC Interrupt Processing Program NDFMCR0 0x0000_0010 ; Disable ECC ; ***** Reading Dummy data & ECC from NAND-Flash ***** ; NDFDTR Read ; Read dummy data (1 byte x 8 times) NDFDTR Read ; Read ECC NDFDTR Read ; Read dummy data (1 byte x 2 times) NDFDTR Read ; Read ECC (1 byte x 3 times) (1 byte x 3 times) ; ; ***** Reading ECC code from NDFC ***** ; NDECCRD0 Read ; ECC for the first 256 bytes NDECCRD1 Read ; ECC for the second 256 bytes Software processing The ECC generated for the read operation and the ECC read from the memory are compared. If any error is found, the error processing routine is executed to correct the error data. For details, see Section 3.11.4.2 "Error Correction Methods". Return to the main program TMPA910CRA- 339 2010-06-02 TMPA910CRA (3) Page write (4LC type) Main Program ; ; ***** Initialize for NDFC ***** ; condition: 8bit-bus, CE0, MLC, 512 Bytes/Page, Reed Solomon ; NDFMCR0 0x0000_0410 ; NDCEn pin = 0, ECC-disable NDFMCR1 0x0000_0002 ; ECC=Reed-Solomon NDFMCR2 0x0000_3343 ; NDWEn L = 3clks,H = 3clks, ; NDWEn L = 4clks,H = 3clks NDFINTC 0x0000_0000 ; ALL Interrupt Disable ; ***** Setting Command, Address to NAND-Flash ***** ; NDFMCR0 0x0000_04b0 ; NDCEn pin = 0, NDCLE = 1, NDALE = 0 stNDFDTR 0x80 ; Write command (1 cycle of Page-Program) NDFMCR0 0x0000_04d0 ; NDCEn pin = 0, NDCLE = 0, NDALE = 1 NDFDTR 0x?? ; Write Address (n-times) NDFMCR0 0x0000_0495 ; NDCEn pin = 0, NDCLE = 0, NDALE = 0 ; ECC enable and reset ; ***** Writing 512Byte Valid data ***** Have the DMAC and INTC support the Autoload function of 512-byte write data. (Details are omitted.) (Including INTTC interrupt enable) NDFMCR1 0x0000_0302 ; <SELALS> = 1, Start Auto-Load ; INTTC Interrupt Processing Program NDFMCR1 Read and check NDFMCR0 0x0000_0490 Return to the main program ; Check that <ALS> = 0 (end). If not, perform polling. ; Disable ECC Main Program ; ***** Reading ECC from NDFC ***** NDECCRD0 Read NDECCRD1 Read NDECCRD2 Read ; ECC (1/3) ; ECC (2/3) ; ECC (3/3) ; ***** Writing Dummy data & ECC ***** ; NDFDTR ECC NDFDTR 0x?? ; Write ECC (1 byte x 10 times) ; Write dummy data (1 byte x 6 times) ; ***** Set Page program command ***** ; NDFMCR0 0x0000_04b0 NDFDTR 0x10 NDFMCR0 0x0000_0410 ; NDCEn pin = 0, NDCLE = 1, NDALE = 0 ; Write Command(2nd cycle of Page-Program) ; NDCEn pin = 0, NDCLE = 0, NDALE = 0 ; ***** Wait till Page-Program End ***** ; ; wait for the page program to end. Whether or not the program has ended can be checked by two ; methods: 1) write a read status command to read the status from the NDD7 to NDD0 pins (polling) ; method), and 2) use a Ready interrupt by detection of NDRB pin rising edge. The following describes a ; case in which the second method is used. ; NDFINTC 0x0000_0009 ; Clear/enable RDY interrupt Have the INTC enable an NDFC interrupt. (Details are omitted.) INTNDFC Interrupt Processing Program End processing Return to the main program TMPA910CRA- 340 2010-06-02 TMPA910CRA (4) Page Read (4LC type) Main Program ; ; ***** Initialize for NDFC ***** ; condition: 8bit-bus, CE0, MLC, 512 Bytes/Page, Reed Solomon ; NDFMCR0 0x0000_0010 ; NDCEn pin = 0, ECC-disable NDFMCR1 0x0000_0002 ; ECC = Reed-Solomon NDFMCR2 0x0000_3343 ; NEWEn L = 3clks,H = 3clks, ; NDWEn L = 4clks,H = 3clks NDFINTC 0x0000_0000 ; ALL Interrupt Disable ; ***** Setting Command, Address to NAND-Flash ***** ; NDFMCR0 0x0000_00b0 ; NDCEn pin = 0, NDCLE = 1, NDALE = 0 NDFDTR 0x00 ; Write Command(1 cycle of Page-Read) st- ; ***** Reading 512Byte Valid data ***** Have the DMAC and INTC support the Autoload function of 512-byte read data. (Details are omitted.) (Including INTTC interrupt enable) NDFMCR1 0x0000_0102 ; <SELALS> = 0, Start Auto-Load NDFMCR0 0x0000_00d0 ; NDCEn pin = 0, NDCLE = 0, NDALE = 1 NDFDTR 0x?? ; Write Address (n-times) NDFMCR0 0x0000_00b0 ; NDCEn pin = 0, NDCLE = 1, NDALE = 0 NDFDTR 0x030 ; Read Command(2nd cycle of Page-Read) NDFMCR0 0x0000_0015 - ; NDCEn pin = 0, NDCLE = 0, NDALE = 0 ; ECC Enable and Reset, <RSECGW> = 0 INTTC Interrupt Processing Program NDFMCR0 0x0000_0114 ; ECC-Enable, <RSECGW>=1 Return to the main program Main Program ; ***** Reading Dummy data & ECC from NAND-Flash ***** ; NDFDTR Read ; Read ECC (1 byte x 10 times) ; ; ***** Calculation Error Address and Data ***** ; NDFINTC 0x0000_0090 ; Clear/enable R/S calculation end interrupt Have the INTC enable an NDFC interrupt. (Details are omitted.) NDFMCR0 0x0000_0310 ; Disable ECC, <RSECGW> = 1, <RSESTA> = 1 INTNDFC Interrupt Processing Program NDFMCR1 Read and check ; Check the <STATE> and <SERR> flags. Software processing If any error is found, the error processing routine is executed to correct the error data. For details, see Section 3.11.4.2 "Error Correction Methods". Return to the main program TMPA910CRA- 341 2010-06-02 TMPA910CRA 3.11.7 Example of Connection with the NAND-Flash TMPA910CRA NAND-Flash 0 NDCLE NDALE NDREn NDWEn NAND-Flash 1 CLE CLE ALE ALE REn WEn REn R/B (open drain) R/B (open drain) I/O[7:0] I/O[7:0] WEn 2k NDRB NDD[7:0] CEn WPn CEn WPn NDCE0n NDCE1n Note 1: The pull-up resistor value for the NDRB pin must be set appropriately according to the NAND Flash memory to be used and the capacity of the board (typical: 2 k). Note 2: The WPn (Write Protect) pin of the NAND Flash is not supported. When this function is needed, prepare it on an external circuit. Figure 3.11.2 Example of Connection with the NAND-Flash TMPA910CRA- 342 2010-06-02 TMPA910CRA 3.12 16-Bit Timers/PWM 3.12.1 General Description of Functions The TMPA910CRA contains six channels of 16-bit timers. They operate in the following two modes: 1) Free-running mode 2) Periodic timer mode PWM function support The circuit consists of three blocks, each associated with two channels. Of the three blocks, Block 1 and Block 2 support PWM (Pulse Width Modulation) output. Block 1 Block 2 Block 3 Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 Free-Running Periodic timer N/A N/A x PWM2OUT (PC4) x PWM Interrupt source signal PWM0OUT (PC3) INTS[2] INTS[3] N/A x x INTS[4] Since all blocks are of the same specifications (except for the PWM function and Interrupt source) only the circuit of Block 1 is described here. TMPA910CRA- 343 2010-06-02 TMPA910CRA 3.12.2 Block Diagrams Each timer block, containing two channels of timer circuits, is comprised of two programmable 16-bit free-running decrement counters. The TIMCLK input is used for counter operation. This clock can be selected from the internal system clock divided by two (fPCLK/2) and fs (32.768 kHz). Figure 3.12.1 shows a diagram of the timer block (Timer 0 and Timer 1). PLLCG Timer 0 32kHz TIMCLK fPCLK/2 TIMCLK Divide by 16 CLKCR5 register Timer 0 Load Timer 0 Control T0 T16 Divide Timer 0 Compare 16-bit down counter T256 by 16 Interrupt Generation Timer0 interrupt INTS [2] Timer 0 Value PWM Out Timer1 interrupt Timer 1 TIMCLK Address Decoder Divide by 16 APB T0 T16 Read data generation Divide Timer 1 Load Timer 1 Control 16-bit down counter T256 by 16 Interrupt Generation Timer 1 Value Figure 3.12.1 Timer Block Diagram (Timer 0 and Timer 1) The timer clock (TIMCLK) is generated by a prescale unit. T0: fPCLK/2 T16: fPCLK/2 divided by 16, generated by a 4-bit prescaler. T256: fPCLK/2 divided by 256, generated by an 8-bit prescaler. TMPA910CRA- 344 2010-06-02 TMPA910CRA 3.12.3 Operation Descriptions The following descriptions are based on setting examples for Timer 0. The timers of other channels operate identically to Timer 0. 1) Free-running mode When the timer starts counting, the counter value decrements from the initially set value. When the counter value reaches 0, an interrupt is generated. For the One-shot-operation (Timer0Control<TIM0OSCTL> = 1), the interrupt is generated once. Upon reaching 0, the counter is reloaded with the maximum value and continues decrementing if Wrapping-operation is enabled (Timer0Control<TIM0OSCTL> = 0). The maximum value is 0x000000FF for the 8-bit counter and 0x0000FFFF for the 16-bit counter. The following shows an example where the 8-bit timer counter and timer value is set to 0x0000003F. (1) One-shot-operation Timer counter value 0x003F Time 0x0000 Timer interrupt is generated when the counter value is cleared. INTS [2] Cleared by setting interrupt clear register TimerxIntClr (2) Wrapping-operation Timer counter value 0x00FF 0x003F Time 0x0000 Timer interrupt is generated when the counter value is cleared. INTS [2] Cleared by setting interrupt clear register TimerxIntClr TMPA910CRA- 345 2010-06-02 TMPA910CRA The following shows an example where the timer value is set to 0x0000001F. fPCLK TIMCLK 1F COUNT [7:0] 1E ... 1D 2 1 0 FF FE FD 8-bit counter continues Timer0Load = 0x0000001F decrementing from 0xFF. Result of Compare (Internal signal) INTS [2] Example of settings for free-running mode (Wrapping-Operation) Bits Register MSB LSB Function [31:8] 7 6 5 4 3 2 1 0 Timer0Control 0x000000 0 x x 0 x x x x [7]: Stops Timer 0. Timer0Load 0x000000 0 0 0 1 1 1 1 1 [15:0]: Timer 0 period = 0x0000001F Timer0Control 0x000000 1 0 1 0 0 0 0 0 [7]: Enables Timer 0 (Starts counting). [6]: Selects free-running mode. [5]: Enables timer interrupts. [3:2]: Selects input clock T0. [1]: Selects 8-bit counter. [0]: Selects Wrapping-operation. x: Don' t care TMPA910CRA- 346 2010-06-02 TMPA910CRA 2) Periodic timer mode When the timer starts counting, the counter value decrements from the initially set value. When the counter value reaches 0, an interrupt is generated. If setting to the One-shot-operation (Timer0Control<TIM0OSCTL> = 1), the interrupt is generated once. Upon reaching 0, the counter is reloaded with the initially set value and continues decrementing if Wrapping-operation is enabled (Timer0Control<TIM0OSCTL> = 0). Therefore, interrupts are generated at fixed intervals. The following shows an example where the 8-bit counter and timer value is set to 0x0000003F. (1) One-shot-operation Timer counter value 0x003F 0x0000 Time Timer interrupt is generated when the counter value is cleared. INTS [2] Cleared by setting interrupt clear register TimerxIntClr (2) Wrapping-operation Timer counter value 0x00FF 0x003F 0x0000 Time Timer interrupt is generated when the counter value is cleared. INTS [2] Cleared by setting interrupt clear register TimerxIntClr TMPA910CRA- 347 2010-06-02 TMPA910CRA The following shows an example where the timer value is set to 0x0000001F. fPCLK TIMCLK 1F COUNT [15:0] 1E ... 1D 2 1 0 1F 1E 1D Timer0Load = 0x0000001F INTS [2] Example of settings for periodic timer mode (Wrapping-Operation) Bits MSB Register Function LSB [31:8] 7 6 5 4 3 2 1 0 Timer0Control 0x000000 0 x x 0 x x x x [7]: Stops Timer 0. Timer0Load 0x000000 0 0 0 1 1 1 1 1 [15:0]: Timer 0 period = 0x0000001F Timer0Control 0x000000 1 1 1 0 0 0 1 0 [7]: Enables Timer 0 (Starts counting). [6]: Selects periodic timer mode. [5]: Enables timer interrupts. [3:2]: Selects input clock T0. [1]: Selects 16-bit counter. [0]: Selects Wrapping-operation. x: Don' t care TMPA910CRA- 348 2010-06-02 TMPA910CRA * One-shot operation When One-shot operation is selected, a new value must be set in the Timer0Load register before the timer can be restarted. If Timer0Control<TIM0EN> is set to 1 without setting a new value in the Timer0Load register, the timer cannot be restarted. fPCLK TIMCLK 1F COUNT [7:0] ... 1E 1 0 0F Timer0Load = 0x0000001F 0E Timer0Load = 0x0000000F Result of Compare (Internal signal) INTS [2] Example of settings for Free-Running mode (One-shot operation) Bits MSB Register LSB Function [31:8] 7 6 5 4 3 2 1 0 Timer0Control 0x000000 0 x x 0 x x x x [7]: Stops Timer 0. Timer0Load 0x000000 0 0 0 1 1 1 1 1 [15:0]: Timer 0 period = 0x0000001F Timer0Control 0x000000 1 0 1 0 0 0 0 1 [7]: Enables Timer 0 (Starts counting). [6]: Selects Free-running mode. [5]: Enable timer interrupts. [3:2]: Selects input clock T0. [1]: Selects 8-bit counter. [0]: Selects one-shot operation. Timer0IntClr x x x x x x x x x [32:0]: Writing any value clears the interrupt. x: Don' t care TMPA910CRA- 349 2010-06-02 TMPA910CRA * PWM function support Block 1 and Block 2 are provided with two channels of the 16-bit PWM function. The two channels of PWM output are output on the PWM0OUT (PC3) and PWM2OUT (PC4) pins. The PWM0OUT output is inverted when the value of the decrement counter matches the value set in the Timer0Compare1 register or when the counter value set in Timer0Mode<PWM Period> decrements to 0. The Timer0Compare1 register can be set in a range of duty 0% to 100%. When the decrement counter value reaches 0, the counter resumes counting down from "2n2". The two channels have the same specifications and the above explanation also applies to Timer 2. Note1: When using PWM function, be sure to select "periodic timer mode", "16-bit counter" and "wrapping operation" in the control register. Note2: The status of PWM output is kept, if PMD function is stopped by setting TIMER0 Control<TIM0EN> to "0" to stop the timer. If 1 is set to " Timer0Control<TIM0EN> " in this state and the timer is made to work again, the output of PWM starts from the state when the timer stopped before. Therefore, if PWM output is High when timer is stoppedthe phase reverses because it is output from High level. Output data is initialized by disabling the PWM function, therefore, Timer0Mode<PWM Mode> must be set "disable" to make the PWM function work again. Example: Outputting the following PWM waveform on the PWM0OUT pin by using Timer 0 with fPCLK = 100 MHz and TIMCLK = 50 MHz 1.1s 4.0s 5.1s (1) To realize the PWM period of 5.1s with T0 = 0.02 s: 5.1s / 0.02 s = 255 = 2n1 Therefore, n=8. (2) Since the Low level period is 4.0 s, the value to be set in Timer0Compare1 is calculated as follows with T0 = 0.02 s: (5.1s - 4.0 s) / 0.02 s = 55 = 0x37 Bits Register MSB [31:8] LSB Function 7 6 5 4 3 2 1 0 Timer0Control 0x000000 0 x x 0 x x x x [7]: Stops Timer 0. Timer0Mode 0x000000 0 1 0 0 0 0 0 0 [6], [5:4]: Selects PWM mode 8 Sets PWM period to 2 1. Timer0Compare1 0x000000 0 0 1 1 0 1 1 1 [7:0]: Sets the compare value 0x37. Timer0CmpEn 0x000000 0 0 0 0 0 0 0 1 [0]: Enables compare. Timer0Control 0x000000 1 1 1 0 0 0 1 0 [7]: Enables Timer 0 (Starts counting). [6]: Selects periodic timer mode. [5]: Enables timer interrupts. [3:2]: Selects input clock T0. [1]: Selects16-bit counter without exception. [0]: Selects wrapping operation. x: Don' t care TMPA910CRA- 350 2010-06-02 TMPA910CRA The following describes PWM minimum resolutions and duty. Table 3.12.1 PWM Minimum Resolutions (TIMCLK = 50 MHz) PWM period Prescaler 281 291 2101 2161 T0 5.1 s 10.22 s 20.46 s 1.31 ms T16 81.6 s 163.52 s 327.36 s 20.97 ms T256 1.305 ms 2.62 ms 5.24 ms 335.54 ms Count --- 0 FE FD --- 1 0 FE FD --- TIM0CPDT 0x00 0x01 0xFE 0xFF Figure 3.12.2 PWM output waveform example Example: Duty settings when the PWM counter period is 281 (255 counts) The initial value of PWM output is always Low output. Duty 0% is always Low output, and duty 100% is always High output. Timer0Compare1 = 0x00: Duty = 0/255 x 100 = 0 % Timer0Compare1 = 0x01: Duty = 1/255 x 100 = 0.39 % : : Timer0Compare1 = 0xFE: Duty = 254/255 x 100 = 99.6 % Timer0Compare1 = 0xFF: Duty = 255/255 x 100 = 100 % * When the PWM period is 2n - 1, setting 2n1 to Timer0Compare1 sets the flip-flop for PWM output to High . To start PWM output by modifying only the PWM period from this state, PWM mode must be disabled once to modify the setting. * The following requirements must be met when PWM mode is used. 0 (Setting value of TimerxCompare1) 2n1 TMPA910CRA- 351 2010-06-02 TMPA910CRA 3.12.4 Register Descriptions The following lists the SFRs. Table 3.12.2 SFR (1/3) Register Address Name (base +) Description Timer0Load 0x0000 Timer0 Load value Timer0Value 0x0004 The current value for Timer0 Timer0Control 0x0008 Timer0 control register Timer0IntClr 0x000C Timer0 interrupt clear Timer0RIS 0x0010 Timer0 raw interrupt status Timer0MIS 0x0014 Timer0 masked interrupt status Timer0BGLoad 0x0018 Background load value for Timer0 Timer0Mode 0x001C Timer0 mode register - 0x0020 Reserved - 0x0040 Reserved - 0x0060 Reserved - 0x0064 Reserved - 0x0068 Reserved Timer0Compare1 0x00A0 Timer0 Compare value Timer0CmpIntClr1 0x00C0 Timer0 Compare Interrupt clear Timer0CmpEn 0x00E0 Timer0 Compare Enable Timer0CmpRIS 0x00E4 Timer0 Compare raw interrupt status Timer0CmpMIS Timer0BGCmp - 0x00E8 Timer0 Compare masked int status 0x00EC Background compare value for Timer0 0x00F0 Reserved 0x0100 Timer1 Load value Timer1Value 0x0104 The current value for Timer1 Timer1Control 0x0108 Timer1 control register Timer1Load Base address = 0xF004_0000 Timer1IntClr 0x010C Timer1 interrupt clear Timer1RIS 0x0110 Timer1 raw interrupt status Timer1MIS 0x0114 Timer1 masked interrupt status Timer1BGLoad 0x0118 Background load value for Timer1 - 0x0120 Reserved - 0x0140 Reserved - 0x0160 Reserved - 0x0164 Reserved - 0x0168 Reserved - 0x01A0 Reserved - 0x01C0 Reserved - 0x01E0 Reserved - 0x01E4 Reserved - 0x01E8 Reserved TMPA910CRA- 352 2010-06-02 TMPA910CRA Table 3.12.2 SFR (2/3) Register Address Name (base +) Base address = 0xF004_1000 Description Timer2Load 0x0000 Timer2 Load value Timer2Value 0x0004 The current value for Timer2 Timer2Control 0x0008 Timer2 control register Timer2IntClr 0x000C Timer2 interrupt clear Timer2RIS 0x0010 Timer2 raw interrupt status Timer2MIS 0x0014 Timer2 masked interrupt status Timer2BGLoad 0x0018 Background load value for Timer2 Timer2Mode 0x001C Timer2 mode register - 0x0020 Reserved - 0x0040 Reserved - 0x0060 Reserved - 0x0064 Reserved - 0x0068 Reserved Timer2Compare1 0x00A0 Timer2 Compare value Timer2CmpIntClr1 0x00C0 Timer2 Compare Interrupt clear Timer2CmpEn 0x00E0 Timer2 Compare Enable Timer2CmpRIS 0x00E4 Timer2 Compare raw interrupt status Timer2CmpMIS 0x00E8 Timer2 Compare masked int status Timer2BGCmp 0x00EC Background compare value for Timer2 : : : Timer3Load 0x0100 Timer3 Load value Timer3Value 0x0104 The current value for Timer3 Timer3Control 0x0108 Timer3 control register Timer3IntClr 0x010C Timer3 interrupt clear Timer3RIS 0x0110 Timer3 raw interrupt status Timer3MIS 0x0114 Timer3 masked interrupt status Timer3BGLoad 0x0118 Background load value for Timer3 - 0x0120 Reserved - 0x0140 Reserved - 0x0160 Reserved - 0x0164 Reserved - 0x0168 Reserved - 0x01A0 Reserved - 0x01C0 Reserved - 0x01E0 Reserved - 0x01E4 Reserved - 0x01E8 Reserved TMPA910CRA- 353 2010-06-02 TMPA910CRA Table 3.12.2 SFR (3/3) Register Address Name (base +) Timer4Load Timer4Value Description 0x0000 Timer4 Load value 0x0004 The current value for Timer4 Timer4Control 0x0008 Timer4 control register Timer4IntClr 0x000C Timer4 interrupt clear Timer4RIS 0x0010 Timer4 raw interrupt status Timer4MIS 0x0014 Timer4 masked interrupt status Timer4BGLoad 0x0018 Background load value for Timer4 - 0x001C Reserved - 0x0020 Reserved - 0x0040 Reserved - 0x0060 Reserved - 0x0064 Reserved - 0x0068 Reserved - 0x00A0 Reserved - 0x00C0 Reserved - 0x00E0 Reserved - 0x00E4 Reserved - 0x00E8 Reserved - 0x00EC Reserved : : : 0x0100 Timer5 Load value Timer5Value 0x0104 The current value for Timer5 Timer5Control 0x0108 Timer5 control register Timer5IntClr 0x010C Timer5 interrupt clear Timer5RIS 0x0110 Timer5 raw interrupt status Timer5MIS 0x0114 Timer5 masked interrupt status Timer5BGLoad 0x0118 Background load value for Timer5 - 0x0120 Reserved - 0x0140 Reserved - 0x0160 Reserved - 0x0164 Reserved - 0x0168 Reserved - 0x01A0 Reserved - 0x01C0 Reserved - 0x01E0 Reserved - 0x01E4 Reserved - 0x01E8 Reserved Timer5Load Base address = 0xF004_2000 TMPA910CRA- 354 2010-06-02 TMPA910CRA 1. Timer0Load Register Address = (0xF004_0000) + (0x0000) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read undefined. Write as zero. [15:0] TIM0SD[15:0] R/W 0x0000 Set the interval value of Timer 0. [Description] a. <TIMxSD[15:0]> This register is used to set the timer period. The counter is a decrement counter and the counter value can be set in a range of 0x0001-0xFFFF. (The value to be set here should be the desired counter value decremented by one.). Note: 0x0000 setting is invalid. 0x0000 setting is started decrement from 0xFFFF. When the 8-bit counter is used, the upper 8 bits are ignored. When the counter runs in periodic timer mode and Wrapping-operation is enabled, the value set in this register is reloaded into the counter when the counter value reaches 0x0000. The value written in this register is immediately reflected in the counter. To renew the counter value when the counter value reaches 0x0000, the Timer0BGLoad register described later can be used. * TimerxLoad (Timer x Load value register) (x = 0 to 5) The structure and description of these registers are same as Timer0Load. Please refer to the description of Timer0Load. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 355 2010-06-02 TMPA910CRA 2. Timer0Value Register Address = (0xF004_0000) + 0x0004 Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. [15:0] TIM0CD[15:0] RO 0xFFFF Current counter value of Timer 0 [Description] a. <TIMxCD[15:0]> This register is used to read the current timer value. It indicates the current value of the decrement counter. * TimerxValue (Timerx value register) (x = 0 to 5) The structure and description of these registers are same as Timer0Value. Please refer to the description of Timer0Value. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 356 2010-06-02 TMPA910CRA 3. Timer0Control Register Address = (0xF004_0000) + (0x0008) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] TIM0EN R/W 0y0 Timer 0 enable bit 0y0: Disable 0y1: Enable [6] TIM0MOD R/W 0y0 Timer 0 mode setting 0y0: Free-running mode 0y1: Periodic timer mode [5] TIM0INTE R/W 0y1 Timer 0 interrupt control 0y0: Disable interrupts 0y1: Enable interrupts [4] - - Undefined Read as undefined. Write as zero. [3:2] TIM0PRS R/W 0y00 Timer 0 prescaler setting 0y00: No division 0y01: Divide by 16 0y10: Divide by 256 0y11: Setting prohibited [1] TIM0SIZE R/W 0y0 8-bit/16-bit counter select for Timer 0 0y0: 8-bit counter 0y1: 16-bit counter [0] TIM0OSCTL R/W 0y0 One-shot/Wrapping operation select for Timer 0 0y0: Wrapping operation 0y1: One-shot operation [Description] a. <TIMxEN> This bit is used to enable or disable timer operation. 0y0: Disable 0y1: Enable Re-enabling timer operation after the timer is stopped in the middle of counting If the timer is stopped in the middle of counting, the timer retains the count value and resumes decrementing from this value when re-enabled. However, if a new value is set in the TimerxLoad register before timer operation is re-enabled, the timer starts decrementing from the value set in the TimerxLoad register. b. <TIMxMOD> This bit is used to switch timer operation modes. c. <TIMxINTE> This bit is used to control masking of timer interrupts. d. <TIMxPRS> This bit is used to set the prescale value for dividing the timer source clock. TMPA910CRA- 357 2010-06-02 TMPA910CRA e. <TIMxSIZE> This bit is used to select the 8-bit or 16-bit counter. f. <TIMxOSCTL> This bit is used to select one-shot or wrapping operation. * TimerxControl (Timerx Control register) (x = 0 to 5) The structure and description of these registers are same as Timer0Control. Please refer to the description of Timer0Control. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 358 2010-06-02 TMPA910CRA 4. Timer0IntClr Register Address = (0xF004_0000) + (0x000C) Bit Bit [31:0] Symbol TIM0INTCLR Type WO Reset Description Value Undefined Timer 0 interrupt clear [Description] a. <TIMxINTCLR> This register is used to clear timer interrupts. Writing any value in this register causes the corresponding interrupt to be cleared. (The bus widths of 8, 16 and 32 bits are supported.) * TimerxIntClr (Timerx Interrupt Clear register) (x = 0 to 5) The structure and description of these registers are same as Timer0IntClr. Please refer to the description of Timer0IntClr. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 359 2010-06-02 TMPA910CRA 5. Timer0RIS Register Address = (0xF004_0000) + (0x0010) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read as undefined. [0] TIM0RIF RO 0y0 Timer 0 interrupt flag 0y0: No interrupt 0y1: Interrupt requested [Description] a. <TIMxRIF> This register indicates the interrupt status of the internal counter, regardless of the interrupt enabled/disabled status specified in IMxCR<TIMxINTE>. * TimerxRIS (Timerx Interrupt Raw Flag register) (x = 0 to 5) The structure and description of these registers are same as Timer0RIS. Please refer to the description of Timer0RIS. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 360 2010-06-02 TMPA910CRA 6. Timer0MIS Register Address = (0xF004_0000) + (0x0014) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read as undefined. [0] TIM0MIF RO 0y0 Timer 0 interrupt flag 0y0: No interrupt 0y1: Interrupt requested [Description] a. <TIMxMIF> This register indicates the masked interrupt status, reflecting the interrupt enabled/disabled status specified in TIMxCR< TIMxINTE>. (This register is always 0 when TIMxCR< TIMxINTE> = 0.) * TimerxMIS (Timerx Interrupt Masked Flag register) (x = 0 to 5) The structure and description of these registers are same as Timer0MIS. Please refer to the description of Timer0MIS. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 361 2010-06-02 TMPA910CRA 7. Timer0BGLoad Register Address = (0xF004_0000) + (0x0018) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15:0] TIM0BSD[15:0] R/W 0x00 Set the interval value of the background counter for Timer 0. [Description] a. <TIMxBSD[15:0]> This register is used to set the value of the background counter for the TimerxLoad register. When the counter runs in periodic timer mode and Wrapping-operation is enabled, this register is used to reload the counter value. Unlike a write to the TimerxLoad register, a write to the TimerxBGLoad register is not immediately reflected in the counter. The counter is reloaded with the new value when it reaches 0x0000. The Read/Write operating relation of the TimerxLoad register and the TimerxBGLoad register is shown below. * When writing : When writing to the TimerxLoad register, same data is written into both the TimerxLoad register and the TimerxBGLoad register. However, when writing to the TimerxBGLoad register, the data is written into the TimerxBGLoad register only. * When reading : When reading either the TimerxLoad register or the TimerxBGLoad register, the data is read from the TimerxBGLoad register and the latest setting value of the timer period can be read. * TimerxBGLoad (Timer x Back Ground Counter Data register) (x = 0 to 5) The structure and description of these registers are same as Timer0BGLoad. Please refer to the description of Timer0BGLoad. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 362 2010-06-02 TMPA910CRA 8. Timer0Mode Register Address = (0xF004_0000) + (0x001C) Bit Bit Reset Type Symbol Description Value [31:7] - - Undefined Read as undefined. Write as zero. [6] PWM Mode R/W 0y0 PWM mode select: 0y0: PWM disabled 0y1: PWM enabled [5:4] PWM Period R/W 0y00 PWM mode period select: 8 0y00: 2 - 1 9 0y01: 2 - 1 10 0y10: 2 - 1 16 0y11: 2 - 1 [3:0] - - Undefined Read as undefined. Write as zero. [Description] a. <PWM Mode> This register is used to enable or disable PWM mode. b. <PWM Period> This register is used to specify the PWM mode period. * TimerxMode (Timerx mode register) (x = 0, 2) The structure and description of these registers are same as Timer0Mode. Please refer to the description of Timer0Mode. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 363 2010-06-02 TMPA910CRA 9. Timer0Compare1 Register Address = (0xF004_0000) + (0x00A0) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15:0] TIM0CPD R/W 0x00 Set the value to be compared with the counter value of Timer 0: 0x0001-0xFFFF [Description] a. <TIMxCPD> Set the value to be compared with the counter value of Timer. * TimerxCompare1 (Timer x Compare Value register) (x = 0 to 5) The structure and description of these registers are same as Timer0Compare1. Please refer to the description of Timer0Compare1. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 364 2010-06-02 TMPA910CRA 10. Timer0CmpIntClr1 Register Address = (0xF004_0000) + (0x00C0) Bit Bit [31:0] Symbol TIM0CMINTCLR Type WO Reset Description Value Undefined Timer 0 compare interrupt clear [Description] a. <TIMxCMINTCLR> This register is used to clear timer compare interrupts. Writing any value in this register causes the corresponding interrupt to be cleared. (The bus widths of 8, 16 and 32 bits are supported.) * TimerxCmpIntClr1 (Timer x Compare Interrupt Clear register) (x = 0 to 5) The structure and description of these registers are same as Timer0CmpIntClr. Please refer to the description of Timer0 CmpIntClr. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 365 2010-06-02 TMPA910CRA 11. Timer0CmpEn Register Address = (0xF004_0000) + (0x00E0) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read as undefined. Write as zero. [0] TIM0CPE RO 0y0 Timer 0 compare operation enable 0y0: Disable 0y1: Enable [Description] a. <TIMxCPE> This register is used to enable compare operation of the timer. It is also used to mask interrupts. * TimerxCmpEn (Timer x Compare Enable register) (x = 0 to 5) The structure and description of these registers are same as Timer0CmpEn. Please refer to the description of Timer0CmpEn. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 366 2010-06-02 TMPA910CRA 12. Timer0CmpRIS Register Address = (0xF004_0000) + (0x00E4) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read as undefined. [0] TIM0CRIF RO 0y0 Timer 0 compare raw interrupt status before enabled compare operation 0y0: No interrupt 0y1: Interrupt requested [Description] a. <TIMxCRIF> This register indicates the status of the raw compare interrupt before enabled compare operation, regardless of the interrupt enabled/disabled status specified in TIMxCPMIS. * TimerxCmpRIS (Timer x Compare raw interrupt status register) (x = 0 to 5) The structure and description of these registers are same as Timer0CmpRIS. Please refer to the description of Timer0CmpRIS. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 367 2010-06-02 TMPA910CRA 13. Timer0CmpMIS Register Address = (0xF004_0000) + (0x00E8) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read as undefined. Write as zero. [0] TIM0CMIF RO 0y0 Timer 0 compare interrupt flag 0y0: No interrupt 0y1: Interrupt requested [Description] a. <TIMxCMIF> This register indicates the status of the masked compare interrupt. * TimerxCmpMIS (Timerx Compare Masked interrupt status register) (x = 0 to 5) The structure and description of these registers are same as Timer0CmpMIS. Please refer to the description of Timer0CmpMIS. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 368 2010-06-02 TMPA910CRA 14. Timer0BGCmp Register Address = (0xF004_0000) + (0x00EC) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15:0] TIM0BGCPD R/W 0x0000 Set the background value to be compared with the counter value of Timer 0: 0x0001-0xFFFF When the compare value to be reloaded is written in the TimerxBGCmp register while the timer is running in periodic timer mode, the timer continues counting until the counter value reaches 0. Then, the value set in the TimerxBGCmp register is shifted to the TimerxCompare1 register. The following requirements must be met when PWM mode is used. 0 (Setting value of TIMxBGCPD) 2n1 The Read/Write operating relation of the TimerxLoad register and the TimerxBGLoad register is shown below. * When writing : When writing to the TimerxCompare1 register, same data is written into both the TimerxCompare1 register and the TimerxBGCmp register. However, when writing to the TimerxBGCmp register, the data is written into the TimerxBGCmp register only. * When reading : When reading either the TimerxCompare1 register or the TimerxBGCmp register, the data is read from the TimerxBGCmp register and the latest setting value of the timer compare can be read. * TimerxBGCmp (Timer x Back Ground Compare register) (x = 0, 2, 4) The structure and description of these registers are same as Timer0BGCmp. Please refer to the description of Timer0BGCmp. For the name and address of these registers, please refer to Table 3.12.2. TMPA910CRA- 369 2010-06-02 TMPA910CRA 3.13 UART This LSI contains two UART channels. The feature of each channel is shown below. Channel 0 Channel 1 Transmit FIFO 8-bit width / 16 location deep Receive FIFO 12-bit width /16location deep Transmit/Receive data format DATA bits : 5,6,7,8bits can be selected PARITY: use / no use STOP bit:1bit / 2bits FIFO ON/OFF ON (FIFO mode)/ OFF (characters mode) Interrupt (1) Combined interrupt factors are output to interrupt controller. (2) The permission of each interrupt factor is programmable. baud rate generator Generates a common transmit and receive internal clock from the UART internal reference clock input. DMA support Not support IrDA 1.0 Function (1) Max data rate: 115.2kbps(half-duplex) Not support Supports baud rates of up to 6.15Mbps at fPCLK = 100MHz. (2) support low power mode Control pins U0RXD U1RXD U0TXD U1TXD U0CTSn U1CTSn U0CTSn (Clear To Send) U0DCDn (Data Carrier Detect) U0DSRn (Data Set Ready) U0RIn (Ring Indicator) U0RTSn(Request To Send) U0DTRn (Data Terminal Ready) Hardware flow control RTS support CTS support CTS support (1) UART transmit/receive data format Transmit/receive data format START DATA AE (LSB PARITY STOP MSB) (2) Receive FIFO data format Receive data AE (LSB Bit Number Receive 8-bit data Receive 7-bit data Receive 6-bit data Receive 5-bit data 0 1 1 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1 MSB) 4 1 1 1 1 5 1 1 1 0 6 1 1 0 0 Framing error flag Parity error flag Break error flag Overrun error flag 7 1 0 0 0 TMPA910CRA- 370 2010-06-02 TMPA910CRA 3.13.1 Block Diagrams Read data [11:0] Write data [7:0] 8bit x16 12bit x16 transmit receive FIFO FIFO APB APB TXD [7:0] RXD[11:0] interface and register Transmitter block U0TXD / SIR0OUT Baud rate divisor UARTCLK PCLK Baud rate generator Baud16 U0RXD / SIR0IN Receiver UART0 receive Clearing DMA request UART0 transmit Clearing DMA request DMA Interface UART0 receive DMA request (single) Transmit FIFO status Receive FIFO Status U0RIn FIFO Flags UART0 transmit DMA request (single) FIFO status and interrupt generation U0CTSn U0DSRn UART0 receive DMA request (burst) U0DCDn U0DTRn UART0 transmit DMA request (burst) U0RTSn UART0 INTS [10] interrupt request Figure 3.13.1 UART Channel 0 Block Diagram TMPA910CRA- 371 2010-06-02 TMPA910CRA Read data [11:0] Write data [7:0] 8bit x 16 12bit x 16 transmit receive FIFO FIFO APB APB RXD [11:0] TXD [7:0] interface and register Transmitter block U1TXD Baud rate divisor UARTCLK PCLK Baud rate Baud16 generator U1RXD Receiver Transmit FIFO status FIFO flags Receive FIFO status FIFO status and interrupt generation U1CTSn UART1 INTS [11] interrupt request Figure 3.13.2 UART Channel 1 Block Diagram TMPA910CRA- 372 2010-06-02 TMPA910CRA 3.13.1.1 Operation Description (1) Baud rate generator The baud rate generator contains the internal Baud16 clock circuit which controls the timing of UART transmit and receive, and the internal IrLPBaud16 circuit which generates the pulse width of the IrDA encoded transmit bit stream when in low-power mode. (2) Transmit FIFO The transmit FIFO is an 8-bit wide, 16-location deep, FIFO memory buffer. CPU data written across the APB interface is stored in the FIFO until it is read out by the transmit logic. You can disable the transmit FIFO to act like a one-byte holding register. (3) Receive FIFO The receive FIFO is a 12-bit wide, 16 locations deep, FIFO memory buffer. Received data and corresponding error bits are stored in the receive FIFO by the receive logic until they are read out by the CPU across the APB interface. The receive FIFO can be disabled to act like a one-byte holding register. (4) Transmit logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream beginning with a start bit, data bits with the Least Significant Bit (LSB) first, followed by the parity bit, and then the stop bits according to the programmed configuration in control registers. (5) Receive logic The receive logic performs serial-to-parallel conversion on the received bit stream after a start bit has been detected. Error check for overrun, parity and frame and line break detection are also performed. Their error bit data is written to the receive FIFO. (6) Interrupt generation logic UART outputs a maskable combined interrupt for every interrupt sources. (7) Interrupt timing Interrupt type Interrupt timing Overrun error After receiving the stop bit of Overflow data Break error After receiving STOP bit Parity error After receiving parity data Frame error After receiving frame over bit Receive timeout error After 511 clocks (Baud16) from Receive FIFO data storage. Transmit interrupt After transmitting the last data (MSB data). Receive interrupt After receiving STOP bit Note:The number of STOP bit can be selected as 1 bit or 2 bits by setting UARTxLCR_H<STP2>. The term STOP bit here means the last STOP bit. TMPA910CRA- 373 2010-06-02 TMPA910CRA (8) UART interrupt block 1) UART0 interrupt block UART0MIS<OEMIS> UART0RIS<OERIS> UART0MIS<BEMIS> UART0RIS<BERIS> UART0IMSC<OEIM> (Enable signal) UART0IMSC<BEIM> (Enable signal) UART0MIS<PEMIS> UART0RIS<PERIS> UART0IMSC<PEIM> (Enable signal) UART0MIS<FEMIS> UART0RIS<FERIS> UART0IMSC<FEIM> (Enable signal) UART0MIS<RTMIS> UART0RIS<RTRIS> UART0IMSC<RTIM> (Enable signal) INTS [10] UART0MIS<TXMIS> UART0RIS<TXRIS> UART0IMSC<TXIM> (Enable signal) UART0MIS<RXMIS> UART0RIS<RXRIS> UART0IMSC<RXIM> (Enable signal) UART0MIS<DSRMMIS> UART0RIS<DSRRMIS> UART0MIS<DCDMMIS> UART0RIS<DCDRMIS> UART0MIS<CTSMMIS> UART0IMSC<DCDMIM> (Enable signal) UART0RIS<CTSRMIS> UART0IMSC<DSRMIM> (Enable signal) UART0IMSC<CTSMIM> (Enable signal) UART0MIS<RIMMIS> UART0RIS<RIRMIS> UART0IMSC<RIMIM> (Enable signal) 2) UART1 interrupt block UART1MIS<OEMIS> UART1RIS<OERIS> UART1IMSC<OEIM> (Enable signal) UART1MIS<BEMIS> UART1RIS<BERIS> UART1IMSC<BEIM> (Enable signal) UART1MIS<PEMIS> UART1RIS<PERIS> UART1IMSC<PEIM> (Enable signal) UART1MIS<FEMIS> UART1RIS<FERIS> UART1IMSC<FEIM> (Enable signal) UART1MIS<RTMIS> UART1RIS<RTRIS> UART1IMSC<RTIM> (Enable signal) INTS [11] UART1MIS<TXMIS> UART1RIS<TXRIS> UART1IMSC<TXIM> (Enable signal) UART1MIS<RXMIS> UART1RIS<RXRIS> UART1IMSC<RXIM> (Enable signal) UART1MIS<CTSMMIS> UART1RIS<CTSRMIS> UART1IMSC<CTSMIM> (Enable signal) TMPA910CRA- 374 2010-06-02 TMPA910CRA (9) DMA interface The UART0 supports DMA controller. (The UART1 does not support it) (10) IrDA circuit description The IrDA is comprised of: * IrDA SIR transmit encoder * IrDA SIR receive decoder Note: The transmit encoder output (SIROUT) has the opposite polarity to the receive decoder input (SIRIN). Please refer to Figure 3.13.4. Figure 3.13.3 shows a block diagram of the IrDA circuit. TXD OR UARTTXD SIR Transmit Encoder SIROUT SIR Receive Decoder SIRIN SIREN UART core 1 RXD 0 UARTRXD Figure 3.13.3 IrDA Circuit Block Diagram Start bit TXD Data bit 0 1 0 1 0 0 1 1 Stop bit 1 0 3/16 bit cycle SIROUT SIRIN RXD bit cycle 0 Start bit 1 0 1 0 0 1 1 0 1 Stop bit Data bit Figure 3.13.4 IrDA Data Modulation TMPA910CRA- 375 2010-06-02 TMPA910CRA (11) Hardware flow control The hardware flow control feature is fully selectable, and enables you to control the serial data flow by using the UxRTSn output and UxCTSn input signals. Figure 3.13.5 shows how the two devices can communicate with each other using hardware flow control. UART1 UART2 Rx FIFO and Flow Control UxRTSn Rx FIFO and Flow Control UxCTSn Tx FIFO and Flow Control UxRTSn Tx FIFO and Flow Control UxCTSn Figure 3.13.5 Hardware Flow Control RTS flow control The RTS flow control logic is linked to the programmable receive FIFO watermark levels. When RTS flow control is enabled, the UxRTSn is asserted until the receive FIFO is filled up to the watermark level. When the amount of data stored in the receive FIFO exceeds watermark level, the UxRTSn signal is deasserted, indicating that there is no more room to receive. The UxRTSn signal is reasserted when data has been read out of the receive FIFO and it is filled to less than the watermark level. Even if RTS flow control is disabled, communication can be enabled. If UART is enabled, data is received until the receive FIFO is full, or no more data is transmitted to it. CTS flow control If CTS flow control is enabled, then the transmitter checks the UxCTSn signal before transmitting. If the UxCTSn signal is asserted, it transmits the byte, otherwise transmission does not occur. The data transmission continues while UxCTSn is asserted and the transmit FIFO is not empty. If the transmit FIFO is empty, no data is transmitted even when the UxCTSn signal is asserted. If the UxCTSn signal is deasserted while CTS flow control is enabled, the current data transmission is completed before stopping. Even if CTS flow control is disabled, communication can be enabled. If UART is enabled, the data transmission continues until the transmit FIFO is empty. TMPA910CRA- 376 2010-06-02 TMPA910CRA Table 3.13.1 Control Bits to Enable and Disable Hardware Flow Control UARTxCR CTSEn RTSEn 1 1 1 0 0 1 0 0 nUARTRTS Description 0 Note 1 Only CTS flow control enabled 0 Note Only RTS flow control enabled 1 Both RTS and CTS flow controls disabled Both RTS and CTS flow controls enabled Note: The nUARTRTS = 0 (Enable) until the receive FIFO is filled up to the watermark level when RTSEn = 1 (Enable). TMPA910CRA- 377 2010-06-02 TMPA910CRA 3.13.2 Register Descriptions The following lists the SFRs.: UART0 Base address = 0xF200_0000 Register Address Name (base +) UART0DR 0x000 UART0SR/ UART0ECR 0x004 Description UART0 Data register UART0 Receive status register/ UART0 error clear register - 0x008-0x014 Reserved UART0FR 0x018 UART0 Flag register - 0x01C Reserved UART0ILPR 0x020 UART0 IrDA low-power counter register UART0IBRD 0x024 UART0 Integer baud rate register UART0FBRD 0x028 UART0 Fractional baud rate register UART0LCR_H 0x02C UART0 Line control register UART0CR 0x030 UART0 Control register UART0IFLS 0x034 UART0 Interrupt FIFO level select register UART0IMSC 0x038 UART0 Interrupt mask set/clear register UART0RIS 0x03C UART0 Raw interrupt status register UART0MIS 0x040 UART0 Masked interrupt status register UART0ICR 0x044 UART0 Interrupt clear register UART0DMACR 0x048 UART0 DMA control register - 0x04C-0x07C Reserved - 0x080-0x08C Reserved - 0x090-0xFCC Reserved - 0xFD0-0xFDC Reserved - 0xFE0 Reserved - 0xFE4 Reserved - 0xFE8 Reserved - 0xFEC Reserved - 0xFF0 Reserved - 0xFF4 Reserved - 0xFF8 Reserved - 0xFFC Reserved Note: You must disable the UART before any of the control registers are reprogrammed. When the UART is disabled in the middle of transmit or receive operation, it stops after the transmission of the current character is completed. TMPA910CRA- 378 2010-06-02 TMPA910CRA UART1 Base address = 0xF200_1000 Register Address Name (base +) Description UART1DR 0x0000 UART1SR/ UART1ECR 0x0004 UART1 Data register - 0x0008-0x0014 Reserved UART1FR 0x0018 UART1 Flag register - 0x001C Reserved - 0x0020 Reserved UART1IBRD 0x0024 UART1 Integer baud rate register UART1FBRD 0x0028 UART1 Fractional baud rate register UART1LCR_H 0x002C UART1 Line control register UART1CR 0x0030 UART1 Control register UART1 Receive status register/ UART1 error clear register UART1IFLS 0x0034 UART1 Interrupt FIFO level select register UART1IMSC 0x0038 UART1 Interrupt mask set/clear register UART1RIS 0x003C UART1 Raw interrupt status register UART1MIS 0x0040 UART1 Masked interrupt status register UART1ICR 0x0044 UART1 Interrupt clear register - 0x0048 Reserved - 0x004C-0x007C Reserved - 0x0080-0x008C Reserved - 0x0090-0x0FCC Reserved - 0x0FD0-0x0FDC Reserved - 0x0FE0 Reserved - 0x0FE4 Reserved - 0x0FE8 Reserved - 0x0FEC Reserved - 0x0FF0 Reserved - 0x0FF4 Reserved - 0x0FF8 Reserved - 0x0FFC Reserved Note: You must disable the UART before any of the control registers are reprogrammed. When the UART is disabled in the middle of transmit or receive operation, it stops after the transmission of the current character is completed. TMPA910CRA- 379 2010-06-02 TMPA910CRA 1. UART0DR (UART0 Data Register) Address = (0xF200_0000) + (0x0000) Bit Bit Type Symbol Reset Description Value [31:12] - - Undefined [11] OE RO Undefined Read as undefined. Write as zero. Overrun error Read : 0y0: There is an empty space in the FIFO. 0y1: Overrun error flag Write: [10] BE RO Undefined Invalid Break error Read : 0y0: No error detected 0y1: Error detected Write: [9] PE RO Undefined Invalid Parity error Read : 0y0: No error detected 0y1: Error detected Write: [8] FE RO Undefined Invalid Framing error Read : 0y0: No error detected 0y1: Error detected Write: [7:0] DATA R/W Undefined Invalid Read: Receive data Write: Transmit data 2. UART1DR (UART1 Data Register) Address = (0xF200_1000) + (0x0000) Bit Bit Type Symbol Reset Description Value [31:12] - - Undefined Read as undefined. Write as zero. [11] OE RO Undefined Overrun error Read: 0y0: There is an empty space in the FIFO. 0y1: Overrun error flag Write: [10] BE RO Undefined Invalid Break error Read: 0y0: No error detected 0y1: Error detected Write: [9] PE RO Undefined Invalid Parity error Read: 0y0: No error detected 0y1: Error detected Write: [8] FE RO Undefined Invalid Framing error Read: 0y0: No error detected 0y1: Error detected Write: [7:0] DATA R/W Undefined Invalid Read: Receive data Write: Transmit data TMPA910CRA- 380 2010-06-02 TMPA910CRA [Description] a. <OE> This bit is set to 1 if data is received and the receive FIFO is already full. In this case, the received data is not stored in the FIFO and is discarded. The bit is cleared to 0 once an empty space is made in the FIFO and a new data can be written to it. b. <BE> This bit is set to 1 if a break condition was detected, indicating that the receive data input (defined as start, data parity, and stop bits) was held Low for a period longer than a full-word transmission time. c. <PE> When this bit is set to 1, it indicates that the parity of the received data does not match the parity defined by bits 2 and 7 of the UARTxLCR_H register. d. <FE> When this bit is set to 1, it indicates that the received data did not have a valid stop bit (a valid stop bit is 1). TMPA910CRA- 381 2010-06-02 TMPA910CRA 3. UART0SR/UART0ECR (UART0 Receive status register/ UART0 error clear register) UART0SR and UART0ECR are mapped to same address. These functions differ in read and write operations. Address = (0xF200_0000) + (0x0004) Bit Bit Reset Type Symbol Description Value [31:4] - - - Read as undefined. [3] OE RO 0y0 Overrun error: 0y0: There is an empty space in the FIFO. 0y1: Overrun error flag [2] BE RO 0y0 Break error 0y0: No error detected 0y1: Error detected [1] PE RO 0y0 Parity error 0y0: No error detected 0y1: Error detected [0] FE RO 0y0 Framing error 0y0: No error detected 0y1: Error detected Address = (0xF200_1000) + (0x0004) Bit Bit [31:0] Symbol - Reset Type WO Value - TMPA910CRA- 382 Description A write to this register clears framing, parity, break, and overrun errors. The data value has no significance. The address of this register is the same as that of the UART0SR register. 2010-06-02 TMPA910CRA 4. UART1SR/ UART1ECR (UART1 Receive status register/ UART1 error clear register) Address = (0xF200_0000) + (0x0004) Bit Bit Reset Type Symbol Description Value [31:4] - - - Read as undefined. [3] OE RO 0y0 Overrun error: 0y0: There is an empty space in the FIFO. 0y1: Overrun error flag [2] BE RO 0y0 Break error 0y0: No error detected 0y1: Error detected [1] PE RO 0y0 Parity error 0y0: No error detected 0y1: Error detected [0] FE RO 0y0 Framing error 0y0: No error detected 0y1: Error detected Address = (0xF200_0000) + (0x0004) Bit Bit [31:0] Symbol - Reset Type WO Description Value - A write to this register clears framing, parity, break, and overrun errors. The data value has no significance. The address of this register is the same as that of the UART1SR register. Note 1: The UARTxSR/UARTxECR register is the receive status register/error clear register. Receive status can also be read from UARTxSR. If the status is read from this register, the status information for break, framing and parity corresponds to the data read from UARTxDR prior to reading UARTxSR. The status information for overrun is set immediately when an overrun condition occurs. A write to UARTxECR clears the framing, parity, break and overrun errors. All the bits are cleared to 0 on reset. Note 2: The receive data must be read first from UARTxDR before the error status associated with that data is read from UARTxSR. This read sequence cannot be reversed because the status register UARTxSR is updated only when the data is read from the data register UARTxDR. The status information can also be read directly from the UARTxDR register. TMPA910CRA- 383 2010-06-02 TMPA910CRA [Description] a. <OE> This bit is set to 1 if data is received and the FIFO is already full. In this case, the received data is not stored in the FIFO and is discarded. The bit is cleared to 0 once an empty space is made in the FIFO and new data can be written to it. b. <BE> This bit is set to 1 if a break condition was detected, indicating that the receive data input (defined as start, data parity, and stop bits) was held Low for longer than a full-word transmission time. c. <PE> When this bit is set to 1, it indicates that the parity of the received data does not match the parity defined by bits 2 and 7 of the UARTxLCR_H register. d. <FE> When this bit is set to 1, it indicates that the received data did not have a valid stop bit (a valid stop bit is 1). TMPA910CRA- 384 2010-06-02 TMPA910CRA 5. UART0FR (UART0 Flag register) The <TXFE>, <RXFF>, <TXFF>, and <RXFE> bits differ depending on the state of the <FEN> of the UART0LCR_H register. (1) Transmit FIFO The transmit FIFO is an 8-bit wide, 16-location deep FIFO memory buffer. CPU data written across the APB interface is stored in the FIFO until it is read out by the transmit logic. The transmit FIFO can be disabled to act like a one-byte holding register. (2) Receive FIFO The receive FIFO is a 12-bit wide, 16-location deep, FIFO memory buffer. Received data and corresponding error bits are stored in the receive FIFO by the receive logic until they are read out by the CPU across the APB interface. The receive FIFO can be disabled to act like a one-byte holding register. Address = (0xF200_0000) + (0x0018) Bit Bit Symbol Description Reset Type Value FIFO mode (FEN = 1) Character mode (FEN = 0) [31:9] - - Undefined Read as undefined. Read as undefined. [8] RI RO Undefined Ring indicator flag Ring indicator flag 0y1: Modem status input = 0 0y1: Modem status input = 0 [7] TXFE RO 0y1 Transmit FIFO empty flag Transmit hold register empty flag 0y0: Not empty 0y1: Empty 0y0: Not empty 0y1: Empty Receive FIFO full flag Receive hold register full flag 0y0: Not full 0y1: Full 0y0: Not full 0y1: Full Transmit FIFO full flag Transmit hold register full flag 0y0: Not full 0y1: Full 0y0: Not full 0y1: Full Receive FIFO empty flag Receive hold register empty flag [6] [5] [4] [3] [2] [1] [0] RXFF TXFF RXFE BUSY DCD DSR CTS RO RO RO RO RO RO RO 0y0 0y0 0y1 0y0 Undefined Undefined Undefined 0y0: Not empty 0y1: Empty 0y0: Not empty 0y1: Empty BUSY flag BUSY flag: 0y0: The UART has stopped transmitting data.0y1: The UART is transmitting data. (BUSY) 0y0: The UART has stopped transmitting data.0y1: The UART is transmitting data. (BUSY) Data carrier detect (DCD) flag Data carrier detect (DCD) flag 0y1: Modem status input = 0 0y1: Modem status input = 0 Data set ready (DSR) flag Data set ready (DSR) flag 0y1: Modem status input = 0 0y1: Modem status input = 0 Clear To Send (CTS) flag Clear To Send (CTS) flag 0y1: Modem status input = 0 0y1: Modem status input = 0 TMPA910CRA- 385 2010-06-02 TMPA910CRA 6. UART1FR (UART1 Flag register) Address = (0xF200_1000) + (0x0018) Bit Bit Type Symbol Description Reset Value FIFO mode (FEN = 1) Character mode (FEN = 0) [31:8] - - Undefined Read as undefined. Read as undefined. [7] TXFE RO 0y1 Transmit FIFO empty flag Transmit hold register empty flag [6] RXFF RO 0y0 [5] TXFF RO 0y0 [4] RXFE RO 0y1 0y0: Not empty 0y1: Empty 0y0: Not empty 0y1: Empty Receive FIFO full flag Receive hold register full flag 0y0: Not full 0y1: Full 0y0: Not full 0y1: Full Transmit FIFO full flag Transmit hold register full flag 0y0: Not full 0y1: Full 0y0: Not full 0y1: Full Receive FIFO full flag Receive hold register empty flag 0y0: Not empty 0y1: Empty 0y0: Not empty 0y1: Empty [3] BUSY RO 0y0 BUSY flag BUSY flag 0y0: The UART has stopped transmitting data. 0y1: The UART is transmitting data. (BUSY) 0y0: The UART has stopped transmitting data 0y1: The UART is transmitting data. (BUSY) [2:1] - - Undefined Read as undefined. Read as undefined. [0] CTS RO Undefined Clear To Send (CTS) flag Clear To Send (CTS) flag 0y1: Modem status input = 0 0y1 : Modem status input = 0 [Description] a. <RI> Ring indicator (nUART1RI): This bit is set to 1 when the modem status input is 0. b. <BUSY> This bit is set to 1 when the UART is transmitting data. This bit remains set until the complete data, including all the stop bits, has been sent from the shift register. c. <DCD> Data carrier detect (U0DCDn): This bit is set to 1 when the modem status input is 0. d. <DSR> UART data set ready (U0DSRn): This bit is set to 1 when the modem status input is 0. e. <CTS> Clear to send (U0CTSn): This bit is set to 1 when the modem status input is 0. TMPA910CRA- 386 2010-06-02 TMPA910CRA 7. UART0ILPR (UART0 IrDA low-power counter register) Address = (0xF200_0000) + (0x0020) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined [7:0] ILPDVSR R/W 0x00 Read as undefined. Write as zero. IrDA low-power divisor: 0x01 to 0xFF [Description] a. <ILPDVSR> Low-power divisor (ILPDVSR) = (fUARTCLK / fIrLPBaud16) 0 is an illegal value. If a 0 value is programmed, IrLPBaud16 pulses are not generated. The UART0ILPR register is the IrDA low-power counter register. This is an 8-bit read/write register that stores the low-power counter divisor value used to generate the IrLPBaud16 signal by dividing down of UARTCLK. All the bits are cleared to 0 when reset. Note 1: Set this register before the UART0CR<SIRLP> is set to 1. Note 2: 0x00 value is invalid. (the IrLPBaud16 pulse is not generated) 8. UART0IBRD (UART0 Integer baud rate register) Address = (0xF200_0000) + (0x0024) Bit Bit Reset Type Symbol Description Value [31:16] - - Undefined [15:0] BAUD DIVINT R/W 0x0000 Read as undefined. Write as zero. Integer part of baud rate divisor: 0x0001 to 0xFFFF 9. UART1IBRD (UART1 Integer baud rate register) Address = (0xF200_1000) + (0x0024) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined [15:0] BAUD DIVINT R/W 0x0000 Read as undefined. Write as zero. Integer part of baud rate divisor: 0x0001 to 0xFFFF [Description] a. <BAUD DIVINT> This register, when put together with the fractional baud rate divisor described next, provides the baud rate divisor BAUDDIV. Note 1: To update the contents of UARTxIBRD internally, the write to UARTxLCR_H must always be executed last. For details, refer to the description of UARTxLCR_H. Note 2: Set this register before the UARTxCR<UARTEN> is set to 1. Note 3: 0x00 value is invalid. TMPA910CRA- 387 2010-06-02 TMPA910CRA 10. UART0FBRD (UART0 Fractional baud rate register) Address = (0xF200_0000) + (0x0028) Bit Bit Reset Type Symbol Description Value [31:6] - - Undefined [5:0] BAUD DIVFRAC R/W 0x00 Read as undefined. Write as zero. Fractional part of baud rate divisor: 0x00 to 0x3F 11. UART1FBRD (UART1 Fractional baud rate register) Address = (0xF200_1000) + (0x0028) Bit Bit Reset Type Symbol Description Value [31:6] - - Undefined [5:0] BAUD DIVFRAC R/W 0x00 Read as undefined. Write as zero. Fractional part of baud rate divisor: 0x00 to 0x3F [Description] a. <BAUDDIVFRAC> The baud rate divisor is calculated as follows: Baud rate divisor BAUDDIV = (fUARTCLK)/ (16 x baud rate) where fUARTCLK is the UARTCLK reference clock frequency. The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD DIVFRAC). Note 1: To update the contents of UARTxFBRD internally, the write to UARTxLCR_H must always be executed last. For details, refer to the description of UARTxLCR_H. Note 2: Set this register before the UARTxCR<UARTEN> is set to 1. Note 3: The Integer part of baud rate divisor setting is invalid to 0. Therefore, the baud rate setting can not be set only the fractional baud rate divisor. And please pay attention that the minimum baud rate divisor setting are "1" as the integer and also "1" as the decimal fraction ( which can not set to "0" when the integer baud rate value is "1" ). Example: Calculating the divisor value When the required baud rate is 230400 and fUARTCLK = 4 MHz: Baud rate divisor = (4 x 106)/ (16 x 230400) = 1.085 Therefore, BRDI = 1 and BRDF = 0.085 Fractional part is ((0.085 x 64) + 0.5) = 5.94. The integer part of this, 0x5, should be set as the fractional baud rate divisor value. Generated baud rate divisor = 1 + 5/64 = 1.078 Generated baud rate = (4 x 106)/ (16 x 1.078) = 231911 Error = (231911 - 230400)/ 230400 x 100 = 0.656 % The maximum error using a 6-bit UARTxFBRD register = 1/64 x 100 = 1.56 % This error occurs when m = 1, and it is cumulative over 64 clock ticks. TMPA910CRA- 388 2010-06-02 TMPA910CRA Typical baud rate setting examples fUARTCLK = 100 MHz Programmed divisor (integer) Programmed divisor (fraction) Required bit rate (bps) Generated bit rate (bps) Error (%) 0x1 0x1 6153846 (fastest) 0xD 0x24 460800 460829.493 0.0064 0x1B 0x8 230400 230414.747 0.0064 0x36 0x10 115200 115207.373 0.0064 0x51 0x18 76800 76804.916 0.0064 0x6C 0x20 57600 57603.687 0.0064 0xA2 0x31 38400 38398.771 -0.0032 0x145 0x21 19200 19200.307 0.0016 0x1B2 0x2 14400 14399.885 -0.0008 0x28B 0x3 9600 9599.923 -0.0008 0xA2C 0xB 2400 2399.995 -0.0002 0x1458 0x15 1200 1200.001 0.0001 0xDDF2 0xC 110 109.99999 -1.00E-05 Programmed divisor (integer) Programmed divisor (fraction) Required bit rate (bps) Generated bit rate (bps) Error (%) 0x1 0x1 5907692 (fastest) fUARTCLK = 96 MHz 0xD 0x1 460800 460984.394 0.0400 0x1A 0x3 230400 230353.929 -0.0200 0.0100 0x34 0x5 115200 115211.521 0x4E 0x8 76800 76800.000 0 0x68 0xB 57600 57597.120 -0.0050 0x9C 0x10 38400 38400.000 0 0x138 0x20 19200 19200.000 0 0x1A0 0x2B 14400 14399.820 -0.0012 0x271 0x1 9600 9599.760 -0.0025 0x9C4 0x1 2400 2399.985 -0.0006 0x1388 0x1 1200 1199.996 -0.0003 0xD511 0x1D 110 110.000 2.60E-06 TMPA910CRA- 389 2010-06-02 TMPA910CRA fUARTCLK = 25MHz Programmed divisor (integer) Programmed divisor (fraction) Required bit rate (bps) Generated bit rate (bps) Error (%) 0x1 0x1 1538461(fastest) 0x3 0x19 460800 460829.493 0.0064 0x6 0x32 230400 230414.747 0.0064 0xD 0x24 115200 115207.373 0.0064 0x14 0x16 76800 76804.916 0.0064 0x1B 0x8 57600 57603.687 0.0064 0x28 0x2C 38400 38402.458 0.0064 0x51 0x18 19200 19201.229 0.0064 0x6C 0x20 14400 14400.922 0.0064 0xA2 0x31 9600 9599.693 -0.0032 0x28B 0x3 2400 2399.981 -0.0008 0x516 0x5 1200 1200.005 0.0004 0x377C 0x23 110 110.000 -1.00E-05 TMPA910CRA- 390 2010-06-02 TMPA910CRA 12. UART0LCR_H (UART0 Line control register) Address = (0xF200_0000) + (0x002C) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined [7] SPS R/W 0y0 Read as undefined. Write as zero. Stick parity select: Refer to Table 3.13.2 for the truth table. [6:5] WLEN R/W 0y00 Word length: 0y00: 5 bits, 0y01: 6 bits 0y10: 7 bits, 0y11: 8 bits [4] FEN R/W 0y0 FIFO control 0y0: Character mode(FIFO invalidity) 0y1: FIFO mode [3] STP2 R/W 0y0 Stop bit select 0y0: 1 bit 0y1: 2 bits [2] EPS R/W 0y0 Even parity select (Refer to Table 3.13.2 for the truth table.) 0y0: Odd 0y1: Even [1] PEN R/W 0y0 Parity control (Refer to Table 3.13.2 for the truth table.) 0y0: Disable 0y1: Enable [0] BRK R/W 0y0 Send break 0y0: No effect 0y1: Send break 13. UART1LCR_H (UART1 Line control register) Bit Bit Reset Type Symbol Address = (0xF200_1000) + (0x002C) Description Value [31:8] - - Undefined [7] SPS R/W 0y0 Read as undefined. Write as zero. Stick parity select: Refer to Table 3.13.2 for the truth table. [6:5] WLEN R/W 0y00 Word length: 0y00: 5 bits, 0y01: 6 bits 0y10: 7 bits, 0y11: 8 bits [4] FEN R/W 0y0 FIFO control 0y0: Character mode(FIFO invalidity) 0y1: FIFO mode [3] STP2 R/W 0y0 Stop bit select 0y0: 1 stop bit 0y1: 2 stop bits [2] EPS R/W 0y0 Even parity select (Refer to Table 3.13.2 for the truth table.) 0y0: Odd 0y1: Even [1] PEN R/W 0y0 Parity control (Refer to Table 3.13.2 for the truth table.) 0y0: Disable 0y1: Enable [0] BRK R/W 0y0 Send break 0y0: No effect 0y1: Send break TMPA910CRA- 391 2010-06-02 TMPA910CRA [Description] a. <SPS> When bits 1, 2, and 7 of the UARTxLCR_H register are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this bit is cleared, the stick parity is disabled. Refer to Table 3.13.2 for the truth table of SPS, EPS, and PEN bits. b. <WLEN> This bit indicates the number of data bits transmitted or received in a frame. c. <FEN> When this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When this bit is cleared to 0, the FIFOs are disabled (character mode) and they become 1-byte deep holding registers. d. <STP2> When this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for the second stop bit being received. e. <EPS> When this bit is set to 1, even parity generation and checking are performed during transmission and reception. This function checks whether the number of 1s contained in the data bits and parity bit is even. When this bit is cleared to 0, odd parity check is performed to check whether the number of 1s is odd. This bit has no effect when parity is disabled by Parity Enable (bit 1) being cleared to 0. Refer to Table 3.13.2 for the truth table. f. <PEN> When this bit is set to 1, parity check and generation are enabled. Otherwise, parity is disabled and no parity bit is added to data frames. Refer to Table 3.13.2 for the truth table of SPS, EPS, and PEN bits. TMPA910CRA- 392 2010-06-02 TMPA910CRA g. <BRK> When this bit is set to 1, the UxTXD output remains LOW after the current character is transmitted. For generation of the break condition, this bit must be asserted while at least one frame is being transmitted. Even when the break condition is generated, the contents of the transmit FIFO are not affected. Note: UARTxLCR_H, UARTxIBRD, and UARTxFBRD are updated on a single write strobe generated by a write to UARTxLCR_H. So, in order to internally update the contents of UARTxIBRD or UARTxFBRD, a write to UARTxLCR_H must always be performed at the end. Therefore, the following two sequences are conceivable to update these three registers: * UARTxIBRD write, UARTxFBRD write, and UARTxLCR_H write * UARTxFBRD write, UARTxIBRD write, and UARTxLCR_H write To update only UARTxIBRD or UARTxFBRD: * UARTxIBRD write (or UARTxFBRD write) and UARTxLCR_H write Table 3.13.2 is the truth table of the <SPS>, <EPS> and <PEN> bits of the UARTxLCR_H register. Table 3.13.2 Truth table of UARTxLCR_H <SPS>, <EPS> and <PEN> Parity enable(PEN) Stick parity Even parity select(EPS) select Parity bit (transmitted or checked) (SPS) 0 x x Not transmitted or checked 1 1 0 Even parity 1 0 0 Odd parity 1 0 1 1 1 1 1 0 TMPA910CRA- 393 2010-06-02 TMPA910CRA 14. UART0CR (UART0 Control register) Address = (0xF200_0000) + (0x0030) Bit Bit Type Reset Symbol Description Value [31:16] - - Undefined [15] CTSEn R/W 0y0 Read as undefined. Write as zero. CTS hardware flow control enable 0y0: Disable 0y1: Enable [14] RTSEn R/W 0y0 RTS hardware flow control enable 0y0: Disable 0y1: Enable [13:12] - - Undefined Read as undefined. Write as zero [11] RTS R/W 0y0 Complement of the UART Request To Send (UxRTSn) modem status output 0y0: Modem status output is 1. 0y1: Modem status output is 0. [10] DTR R/W 0y0 Complement of the UART Data Set Ready (UxDTRn) modem status output 0y0: Modem status output is 1. 0y1: Modem status output is 0. [9] RXE R/W 0y1 UART receive enable 0y0: Disable 0y1: Enable [8] TXE R/W 0y1 UART transmit enable 0y0: Disable 0y1: Enable [7] Reserved R/W 0y0 Write as zero. [6:3] Reserved - Undefined Read as undefined. Write as zero [2] SIRLP R/W 0y0 IrDA encoding mode select for transmitting 0 bits 0y0: 0 bits are transmitted as an active high pulse of 3/16th of the bit period. 0y1:0 bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal. [1] SIREN R/W 0y0 SIR enable 0y0: Disable 0y1: Enable [0] UARTEN R/W 0y0 UART enable 0y0: Disable 0y1: Enable TMPA910CRA- 394 2010-06-02 TMPA910CRA 15. UART1CR (UART1 control register) Address = (0xF200_1000) + (0x0030) Bit Bit Type Reset Symbol Description Value [31:16] - - Undefined [15] CTSEn R/W 0y0 Read as undefined. Write as zero. CTS hardware flow control enable 0y0: Disable 0y1: Enable [14:10] - - Undefined [9] RXE R/W 0y1 Read as undefined. Write as zero. UART receive enable 0y0: Disable 0y1: Enable [8] TXE R/W 0y1 UART transmit enable 0y0: Disable 0y1: Enable [7] Reserved R/W 0y0 Write as zero. [6:1] Reserved - Undefined Read as undefined. Write as zero. [0] UARTEN R/W 0y0 UART enable 0y0: Disable 0y1: Enable [Description] a. <CTSEn> When this bit is set to 1, CTS hardware flow control is enabled. Data is transmitted only after the UxCTSn signal has been asserted. b. <RTSEn> When this bit is set to 1, RTS hardware flow control is enabled. Data is transmitted only when there is an empty space in the receive FIFO. c. <RTS > This bit is the UART Request To Send (UxRTSn) modem status output signal. When this bit is programmed to a 1, the output is 0. TMPA910CRA- 395 2010-06-02 TMPA910CRA d. <DTR> This bit is the UART Data Transmit Ready (UxDTRn) modem status output signal. When this bit is programmed to a 1, the output is 0. e. <RXE> When this bit is set to 1, the receive circuit of the UART is enabled. Data reception occurs for either UART signals or SIR signals according to the setting of SIR Enable (bit 1). When the UART is disabled in the middle of receive operation, it completes current reception and the subsequent receptions are disabled. f. <TXE> When this bit is set to 1, the transmit circuit of the UART is enabled. Data transmission occurs for either UART signals or SIR signals according to the setting of SIR Enable (bit 1). When the UART is disabled in the middle of transmit operation, it completes the current transmission before stopping. g. <SIRLP> <SIRLP> selects IrDA encoding mode. When this bit is cleared to 0, 0 bits are transmitted as an active high pulse with a width of 3/16th of the bit period. When this bit is set to 1, 0 bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal. Setting this bit can reduce power consumption but might decrease transmission distances. h. <SIREN> When this bit is set to 1, the IrDA circuit is enabled. To use the UART, the <UARTEN> bit must be set to 1. When the IrDA circuit is enabled, the SIR0OUT and SIR0IN pins are enabled. The U0TXD pin remains in the marking state (set to 1). Signal transitions on the U0RXD pin or modem status input have no effect. When IrDA circuit is disabled, SIR0OUT remains cleared to 0 (no light pulse is generated) and the SIR0IN pin has no effect. i. <UARTEN> When this bit is set to 1, the UART is enabled. Data transmission and reception occur for either UART signals or SIR signals according to the setting of SIR Enable (bit 1). When the UART is disabled in the middle of transmit or receive operation, it completes current transmission or reception before stopping. TMPA910CRA- 396 2010-06-02 TMPA910CRA 16. UART0IFLS (UART0 Interrupt FIFO level select register) Address = (0xF200_0000) + (0x0034) Bit Bit Type Symbol Reset Description Value [31:6] - - Undefined [5:3] RXIFLSEL R/W 0y010 Read as undefined. Write as zero. Receive interrupt FIFO level select (1 word = 12 bits): 0y000: When the 2nd word has been stored in receive FIFO 0y001: When the 4th word has been stored in receive FIFO 0y010: When the 8th word has been stored in receive FIFO 0y011: When the 12th word has been stored in receive FIFO 0y100: When the 14th word has been stored in receive FIFO 0y101to 0y111: Reserved [2:0] TXIFLSEL R/W 0y010 Transmit FIFO level select (1 word = 8 bits): 0y000: When transmit FIFO has space for 2 words left 0y001: When transmit FIFO has space for 4 words left 0y010: When transmit FIFO has space for 8 words left 0y011: When transmit FIFO has space for 12 words left 0y100: When transmit FIFO has space for 14 words left 0y101 to 0y111: Reserved 17. UART1IFLS (UART1 Interrupt FIFO level select register) Address = (0xF200_1000) + 0x0034 Bit Bit Type Symbol Reset Description Value [31:6] - - Undefined [5:3] RXIFLSEL R/W 0y010 Read as undefined. Write as zero. Receive interrupt FIFO level select (1 word = 12 bits ): 0y000: When the 2nd word has been stored in receive FIFO 0y001: When the 4th word has been stored in receive FIFO 0y010: When the 8th word has been stored in receive FIFO 0y011: When the 12th word has been stored in receive FIFO 0y100: When the 14th word has been stored in receive FIFO 0y101 to 0y111: Reserved [2:0] TXIFLSEL R/W 0y010 Transmit interrupt FIFO level select ( 1 word = 8 bits): 0y000: When transmit FIFO has space for 2 words left 0y001: When transmit FIFO has space for 4 words left 0y010: When transmit FIFO has space for 8 words left 0y011: When transmit FIFO has space for 12 words left 0y100: When transmit FIFO has space for 14 words left 0y101 to 0y111: Reserved [Description] The UARTxIFLS register is the interrupt FIFO level select register. This register is used to define the FIFO level at which UARTTXINTR and UARTRXINTR are generated. The interrupts are generated based on a transition through a level rather than based on the level. For example, an interrupt is generated at a point when the third word has been stored in the receive FIFO which contained two words. TMPA910CRA- 397 2010-06-02 TMPA910CRA 18. UART0IMSC (UART0 Interrupt mask set/clear register) Address = (0xF200_0000) + (0x0038) Bit Bit Reset Type Symbol Value Description [31:11] - - Undefined Read as undefined. Write as zero. [10] OEIM R/W 0y0 Overrun error interrupt mask 0y0: Clear the mask 0y1: Set the mask [9] BEIM R/W 0y0 Break error interrupt mask 0y0: Clear the mask 0y1: Set the mask [8] PEIM R/W 0y0 Parity error interrupt mask 0y0: Clear the mask 0y1: Set the mask [7] FEIM R/W 0y0 Framing error interrupt mask 0y0: Clear the mask 0y1: Set the mask [6] RTIM R/W 0y0 Receive timeout interrupt mask 0y0: Clear the mask 0y1: Set the mask [5] TXIM R/W 0y0 Transmit FIFO interrupt mask 0y0: Clear the mask 0y1: Set the mask [4] RXIM R/W 0y0 Receive FIFO interrupt mask 0y0: Clear the mask 0y1: Set the mask [3] DSRMIM R/W 0y0 U0DSRn modem interrupt mask 0y0: Clear the mask 0y1: Set the mask [2] DCDMIM R/W 0y0 U0DCDn modem interrupt mask 0y0: Clear the mask 0y1: Set the mask [1] CTSMIM R/W 0y0 U0CTSn modem interrupt mask 0y0: Clear the mask 0y1: Set the mask [0] RIMIM R/W 0y0 U0RIn modem interrupt mask 0y0: Clear the mask 0y1: Set the mask TMPA910CRA- 398 2010-06-02 TMPA910CRA 19. UART1IMSC (UART1 Interrupt mask set/clear register) Address = (0xF200_1000) + (0x0038) Bit Bit Reset Type Symbol Value Description [31:11] - - Undefined Read as undefined. Write as zero. [10] OEIM R/W 0y0 Overrun error interrupt mask 0y0: Clear the mask [9] BEIM R/W 0y0 Break error interrupt mask 0y0: Clear the mask [8] PEIM R/W 0y0 Parity error interrupt mask 0y0: Clear the mask 0y1: Set the mask 0y1: Set the mask 0y1: Set the mask [7] FEIM R/W 0y0 [6] RTIM R/W 0y0 Framing error interrupt mask0y0: Clear the mask 0y1: Set the mask Receive timeout interrupt mask 0y0: Clear the mask 0y1: Set the mask [5] TXIM R/W 0y0 Transmit interrupt mask0y0: Clear the mask 0y1: Set the mask [4] RXIM R/W 0y0 Receive interrupt mask 0y0: Clear the mask 0y1: Set the mask [3:2] - - Undefined Read as undefined. Write as zero. [1] CTSMIM R/W 0y0 U0CTSn interrupt mask0y0: Clear the mask [0] - - Undefined 0y1: Set the mask TMPA910CRA- 399 Read as undefined. Write as zero. 2010-06-02 TMPA910CRA z UART interrupt generation block diagrams (1) Block diagram of the break error (BE), parity error (PE) and framing error (PE) flags Interrupt prior to masking Interrupt after masking F/F Interrupt request flag UARTCLK Interrupt mask signal The interrupt request flag state changes in real time and is retained in the F/F. Each flag can be cleared by a write to the corresponding bit in the interrupt clear register. (2) Block diagram of the overrun error (OE) flag Interrupt prior to masking Interrupt after masking Interrupt request flag Interrupt mask signal The overrun error (OE) flag changes in real time and its state is not retained. The OE flag is cleared by a read of the receive FIFO. TMPA910CRA- 400 2010-06-02 TMPA910CRA 20. UART0RIS (UART0 Raw interrupt status register) Address = (0xF200_0000) + (0x003C) Bit Bit Type Symbol Reset Description Value [31:11] - - Undefined Read as undefined. [10] OERIS RO 0y0 Overrun error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [9] BERIS RO 0y0 Break error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [8] PERIS RO 0y0 Parity error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [7] FERIS RO 0y0 Framing error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [6] RTRIS RO 0y0 Receive timeout raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [5] TXRIS RO 0y0 Transmit raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [4] RXRIS RO 0y0 Receive raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [3] DSRRMIS RO Undefined U0DSRn modem raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [2] DCDRMIS RO Undefined U0DCDn modem raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [1] CTSRMIS RO Undefined U0CTSn modem raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [0] RIRMIS RO Undefined U0RIn modem raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. Note: All the bits, except the modem raw status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status bits are undefined after reset. TMPA910CRA- 401 2010-06-02 TMPA910CRA 21. UART1RIS (UART1 Raw interrupt status register) Address = (0xF200_1000) + (0x003C) Bit Bit Type Symbol Reset Description Value [31:11] - - Undefined Read as undefined. [10] OERIS RO 0y0 Overrun error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [9] BERIS RO 0y0 Break error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [8] PERIS RO 0y0 Parity error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [7] FERIS RO 0y0 Framing error raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [6] RTRIS RO 0y0 Receive timeout raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [5] TXRIS RO 0y0 Transmit raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [4] RXRIS RO 0y0 Receive raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [3:2] - - Undefined Read as undefined. [1] CTSRMIS RO Undefined U0CTSn modem raw interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [0] - - Undefined Read as undefined. Note: All the bits, except the modem raw status interrupt bits (bits 1), are cleared to 0 when reset. The modem status bits are undefined after reset. TMPA910CRA- 402 2010-06-02 TMPA910CRA 22. UART0MIS (UART0 Masked interrupt status register) Address = (0xF200_0000) + (0x0040) Bit Bit Type Symbol Reset Description Value [31:11] - - Undefined Read as undefined. [10] OEMIS RO 0y0 Overrun error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [9] BEMIS RO 0y0 Break error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [8] PEMIS RO 0y0 Parity error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [7] FEMIS RO 0y0 Framing error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [6] RTMIS RO 0y0 Receive timeout masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [5] TXMIS RO 0y0 Transmit masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [4] RXMIS RO 0y0 Receive masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [3] DSRMMIS RO Undefined U0DSRn modem masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [2] DCDMMIS RO Undefined U0DCDn modem masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [1] CTSMMIS RO Undefined U0CTSn modem masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [0] RIMMIS RO Undefined U0RIn modem masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. Note: All the bits, except the modem masked status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status bits are undefined after reset. TMPA910CRA- 403 2010-06-02 TMPA910CRA 23. UART1MIS (UART1 Masked interrupt status register) Address = (0xF200_1000) + (0x0040) Bit Bit Type Symbol Reset Description Value [31:11] - - Undefined Read as undefined. [10] OEMIS RO 0y0 Overrun error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [9] BEMIS RO 0y0 Break error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [8] PEMIS RO 0y0 Parity error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [7] FEMIS RO 0y0 Framing error masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [6] RTMIS RO 0y0 Receive timeout masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [5] TXMIS RO 0y0 Transmit masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [4] RXMIS RO 0y0 Receive masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [3:2] - - Undefined [1] CTSMMIS RO Undefined Read as undefined. U0CTSn masked interrupt status 0y0: Interrupt not requested. 0y1: Interrupt requested. [0] - - Undefined Read as undefined. TMPA910CRA- 404 2010-06-02 TMPA910CRA 24. UART0ICR (UART0 Interrupt clear register) Address = (0xF200_0000) + (0x0044) Bit Bit Type Symbol Reset Description Value [31:11] - - Undefined Read as undefined. Write as zero. [10] OEIC WO Undefined Overrun error interrupt clear 0y0: Do nothing 0y1: Clear [9] BEIC WO Undefined Break error interrupt clear 0y0: Do nothing 0y1: Clear [8] PEIC WO Undefined Parity error interrupt clear 0y0: Do nothing 0y1: Clear [7] FEIC WO Undefined Framing error interrupt clear 0y0: Do nothing. 0y1: Clear. [6] RTIC WO Undefined Receive timeout interrupt clear 0y0: Do nothing 0y1: Clear [5] TXIC WO Undefined Transmit interrupt clear 0y0: Do nothing 0y1: Clear [4] RXIC WO Undefined Receive interrupt clear 0y0: Do nothing 0y1: Clear [3] DSRMIC WO Undefined U0DSRn modem interrupt clear 0y0: Do nothing 0y1: Clear [2] DCDMIC WO Undefined U0DCDn modem interrupt clear 0y0: Do nothing 0y1: Clear [1] CTSMIC WO Undefined U0CTSn modem interrupt clear 0y0: Do nothing 0y1: Clear [0] RIMIC WO Undefined U0RIn modem interrupt clear 0y0: Do nothing 0y1: Clear Note: The UART0ICR register is a write-only interrupt clear register. When a bit of this register is set to 1, the associated interrupt is cleared. A write of 0 to any bit of this register is invalid. TMPA910CRA- 405 2010-06-02 TMPA910CRA 25. UART1ICR (UART1 Interrupt clear register) Address = (0xF200_1000) + (0x0044) Bit Bit Type Symbol Reset Description Value [31:11] - - Undefined Read as undefined. Write as zero. [10] OEIC WO Undefined Overrun error interrupt clear [9] BEIC WO Undefined Break error interrupt clear 0y0: Do nothing0y1: Clear 0y0: Do nothing 0y1: Clear [8] PEIC WO Undefined Parity error interrupt clear 0y0: Do nothing 0y1: Clear [7] FEIC WO Undefined Framing error interrupt clear 0y0: Do nothing 0y1: Clear [6] RTIC WO Undefined Receive timeout interrupt clear 0y0: Do nothing 0y1: Clear [5] TXIC WO Undefined Transmit interrupt clear 0y0: Do nothing 0y1: Clear [4] RXIC WO Undefined Receive interrupt clear 0y0: Do nothing 0y1: Clear [3:2] - - Undefined Read as undefined. Write as zero. [1] CTSMIC WO Undefined U0CTSn interrupt clear 0y0: Do nothing 0y1: Clear [0] - - Undefined Read as undefined. Write as zero. Note: The UART1ICR register is a write-only interrupt clear register. When a bit of this register is set to 1, the associated interrupt is cleared. A write of 0 to any bit of this register is invalid. TMPA910CRA- 406 2010-06-02 TMPA910CRA 26. UART0DMACR (UART0 DMA control register) Address = (0xF200_0000) + (0x0048) Bit Bit Reset Type Symbol Description Value [31:3] - - - Read as undefined. Write as zero. [2] DMAONERR R/W 0y0 DMA on error 0y1: Available 0y0: Not available [1] TXDMAE R/W 0y0 Transmit FIFO DMA enable 0y0: Disable 0y1: Enable [0] RXDMAE R/W 0y0 Receive FFO DMA enable 0y0: Disable 0y1: Enable Note1: For example, if 19 characters have to be received and the watermark level is programmed to be four, then the DMA controller transfers four bursts of four characters and three single transfers to complete the stream. Note2: The bus width must be set to 8-bits, if you transfer the data of tranmit/ receive FIFO by using DMAC. [Description] a. <DMAONERR> When this bit is set to 1, the DMA receive request output, UARTxRXDMASREQ or UARTxRXDMABREQ, is disabled on assertion of a UART error interrupt. TMPA910CRA- 407 2010-06-02 TMPA910CRA 3.14 I2C 3.14.1 Overview This module operates in I2C bus mode compliant with the typical I2C bus standard (Philips specifications). (Note 1) The main features are as follows: * Contains two channels (ch0 and ch1). * Allows selection between master and slave. * Allows selection between transmission and reception. * Supports multiple masters (arbitration, clock synchronization recognition). * Supports standard mode and fast mode (fastest baud rate in master mode: 89.91 kHz and 357.14 KHz, respectively, at fPCLK = 100 MHz) * Supports the addressing format of 7 bits only. * Supports transfer data sizes of 1 to 8 bits. * Provides one transfer (transmit or receive) complete interrupt (level-sensitive). * Can enable or disable interrupts. (Interrupt source for I2C ch0: INTS[6], Interrupt source for I2C ch1: INTS[7]) This module also supports Toshiba's proprietary data format called "free data format". 2 Note 1: Compliant with the I C bus standard (Philips specifications) in fast communication mode except those shown below. 2 Note 2: This module does not support some of the features in the I C bus standard. I2C bus feature I2C specifications This IP Standard mode (up to 100 kHz) Required Supported Fast mode (up to 400 kHz) Required Supported High-speed mode (up to 3.4 Mbps) Required Not supported -bit addressing Required Supported 10-bit addressing Required Not supported START byte Required Not supported Noise canceller Required Supported (digital) Slope control Required Not supported I/O at power off Schmitt (VIH/VIL) Output current at VOL = 0.4V, VDD2 V Required Not supported VDDx0.3 / VDDx0.7 Supported 3 mA Supported TMPA910CRA- 408 2010-06-02 TMPA910CRA 2 3.14.1.1 I C Bus Mode The I2C bus is connected to devices via the I2C0DA and I2C0CL pins and can communicate with multiple devices. VDD SDA SDA SDA SCL SCL SCL Device 1 Device 2 Device n Figure 3.14.1 Device connections This module operates as a master or slave device on the I2C bus. The master device drives the serial clock line (SCL) of the bus, sends 8-bit addresses, and sends or receives data of 1 to 8 bits. The slave device sends 8-bit addresses and sends or receives serial data of 1 to 8 bits in synchronization with the serial clock on the bus. The device that operates as a receiver can output an acknowledge signal after reception of serial data and the device that operates as a transmitter can receive that acknowledge signal, regardless of whether the device is a master or slave. The master device can output a clock for the acknowledge signal. In multimaster mode in which multiple masters exist on the same bus, serial clock synchronization and arbitration lost to maintain consistency of serial data are supported. TMPA910CRA- 409 2010-06-02 TMPA910CRA 3.14.2 Data Formats for I2C Bus Mode The data formats for I2C bus mode are shown below. 3.14.2.1 Addressing Format (a) Addressing format 1 8 bits S Slave address R A / C W K 1 to 8 bits 1 1 to 8 bits Data A C K Data 1 1 A C P K 1 or more (b) Addressing format (with restart) 1 8 bits S Slave address 1 to 8 bits R A / C W K 1 S: A C S K Data 1 8 bits 1 R A / C W K Slave address 1 or more 1 to 8 bits 1 Data 1 A C P K 1 or more Start condition R/W: Direction bit ACK: Acknowledge bit P: Stop condition 2 Figure 3.14.2 Data Format for I C Bus Mode 3.14.2.2 Free Data Format The free data format is for communication between one master and one slave. In the free data format, slave addresses and direction bits are processed as data. (a) Free data format (for transferring data from a master device to a slave device) 8 bits S Data 1 1 to 8 bits 1 1 to 8 bits A C K Data A C K Data 1 S: 1 A C P K 1 or more Start condition R/W: Direction bit ACK: Acknowledge bit P: Stop condition 2 Figure 3.14.3 Free Data Format for I C Bus Mode TMPA910CRA- 410 2010-06-02 TMPA910CRA 3.14.3 Block Diagram I2CINT0 interrupt request (INTS [6]) Noise canceller Tprsck Transfer control Input/ output control circuit Software Clock control reset circuit circuit Shift register I2C0CR2 Data control Noise canceller circuit I2C0DA Prescaler I2C0PRS I2C0CR1 I2C0AR I2C0IR I2C0IE I2C0DBR LRB AL/AAS/AD0 MST/TRX/ BB/PIN ALS SA BC ACK SCK NOACK N divider PRSCK[4:0] SWRES [1:0] MST/TRX/BB/PIN PCLK I2C0CL I2C0SR 2 Figure 3.14.4 I C Channel 0 TMPA910CRA- 411 2010-06-02 TMPA910CRA 3.14.4 Operational Descriptions 3.14.4.1 Data Transfer Procedure in I2C Bus Mode 1. Device Initialization After ensuring that the I2C0DA and I2C0CL pins are high (bus free), set I2C0CR2<I2CM> to 1 to enable I2C. Next, set I2C0CR1<ACK> to 1, I2C0CR1<NOACK> to 0 and I2C0CR1<BC> to 0y000. These settings enable acknowledge operation, slave address match detection and general call detection and set the data length to 8 bits. Set tHIGH and tLOW in I2C0CR1<SCK>. Then, set the slave address in I2C0AR<SA> and set I2C0AR<ALS> to 0 to select the addressing format. Finally, set I2C0CR2<MST>, I2C0CR2<TRX> and I2C0CR2<BB> to 0, I2C0CR2<PIN> to 1 and I2C0CR2<SWRES[1:0]> to 0y00 to configure the device as a slave receiver. 2 Note: The initialization of I C must be completed within a certain period of time in which no start condition is generated by any device after all the devices connected to the bus have been initialized. If this constraint is 2 not observed, another device may start a transfer before the initiaization of I C has been completed and data may not be received properly. Programming example: Initializing the device CHK _ PORT: r1 (GPIOCDATA ; Check whether the external pins are high. CMP r1, #0xC0 BNE (I2C0CR2) CHK _ PORT 0x18 ; Enable I C. (I2C0CR1) 0x16 ; Enable acknowledge operation and set I2C0CR1<SCK> = 0y110. 0xA0 ; Set the slave address to 1010000 and select addressing format. (I2C0CR2) 0x18 ; Select slave receiver mode. (I2C0AR) 2 TMPA910CRA- 412 2010-06-02 TMPA910CRA 2. Start Condition and Slave Address Generation Check that the bus is free (I2C0SR<BB> = 0). Set I2C0CR1<ACK> to 1 and write the slave address and direction bit to be transmitted to I2C0DBR. Writing 1 to I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<BB> and I2C0CR2<PIN> causes a start condition, the slave address and direction bit to be sent out on the bus. After a start condition is generated, it takes the tHIGH period for the I2C0CL pin to fall. Then, an I2CINT0 interrupt request is generated on the falling edge of the 9th clock of I2C0CL and I2C0SR<PIN> is cleared to 0. While I2C0SR<PIN> is 0, I2C0CL is pulled low. Only when the acknowledge signal is returned from the slave device, I2C0SR<TRX> is changed by hardware according to the direction bit upon generation of an I2CINT0 interrupt request. Note 1: Before writing a slave address to I2C0DBR, make sure that the bus is free by software. Note 2: After a slave address is written and before a start condition is generated, another master may initiate transfer operation. Therefore, after writing a slave address to I2C0DBR, check a bus free state again by software within 98.0 s (the shortest transfer time in standard mode according to the I C bus standard) or 23.7s (the 2 2 shortest transfer time in fast mode according to the I C bus standard). A start condition should be generated only after a bus free state is confirmed. Programming example: Generating a start condition CHK _ BB: I2C0CL pin r1 (I2C0SR) AND r1, #0x20 ; Check that the bus is free. CMP r1, #0x00 BNE (I2C0DBR) CHK _ BB 0xCB ; Set the slave address to 0x65 and direction bit to 1. (I2C0CR2) 0xF8 ; Set I2C0CR2<MST>, <TRX>, <BB>, <PIN> to 1. 1 3 2 4 5 6 7 8 9 I2C0DA pin ACK from slave Start condition Slave address + direction bit I2C0SR<PIN> Interrupt request I2C0SR<TRX> When the direction bit is 1 and ACK is returned, I2C0SR<TRX> is cleared to 0. Figure 3.14.5 Start condition and Slave address generation TMPA910CRA- 413 2010-06-02 TMPA910CRA 3. 1-Word Data Transfer Check I2C0SR<MST> in the interrupt routine after a 1-word data transfer is completed, and determine whether master or slave mode is selected. (1) When I2C0SR<MST> = 1 (Master mode) Check I2C0SR<TRX> to determine whether transmitter or receiver mode is selected. a. When I2C0SR<TRX>=1 (Transmitter mode) Check the acknowledge status from the receiver with the I2C0SR<LRB> flag. When I2C0SR<LRB> is 0, the receiver is requesting the next data. Write the data to be transmitted to I2C0DBR. If it is necessary to change the transfer data size, change I2C0CR1<BC>, set I2C0CR1<ACK> to 1, and then write the data to be transmitted to I2C0DBR. After the transmit data is written, I2C0SR<PIN> is set to 1 and serial clocks are generated to transmit from I2C0CL the data from I2C0DA. After the transmission is completed, an I2CINT0 interrupt request is generated. I2C0SR<PIN> is cleared to 0 and I2C0CL is pulled low. If more than one word of data needs to be transferred, repeat the procedure by checking I2C0SR<LRB>. When I2C0SR<LRB> is 1, the receiver is not requesting the next data, so a stop condition should be generated to terminate the data transfer. I2C0CL pin Write to I2C0DBR I2C0DA pin 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Acknowledge signal from Receiver <PIN> I2CINT0 Interrupt request Master output Slave output Figure 3.14.6 When I2C0CR1<BC> = 0y000 and I2C0CR1<ACK> = 1 b. When I2C0SR<TRX> = 0 (Receiver mode) Writing dummy data (0x00) to I2C0DBR or setting I2C0CR2<PIN> to 1 causes clocks for 1-word transfer and acknowledge to be output. After an I2CINT0 interrupt request is generated to indicate the end of receive operation, read the received data from I2C0DBR. If it is necessary to change the receive data size, change I2C0CR1<BC>, set I2C0CR1<ACK> to 1 and then write dummy data (0x00) to I2C0DBR or set I2C0CR2<PIN> to 1. (The data that is read immediately after slave address transmission is undefined.) TMPA910CRA- 414 2010-06-02 TMPA910CRA I2C0DBR read Dummy data written to I2C0DBR I2C0CL pin 9 I2C0DA pin 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 9 Next D7 ACK signal to transmitter I2C0CR2<PIN> I2CINT0 interrupt I2C0IR<IR> = 1 write Figure 3.14.7 When I2C0CR1<BC> = 0y000 and I2C0CR1<ACK> = 1 c. When I2C0SR<TRX> = 0 (when receiving the last word) The last word of the transfer is determined by pseudo communication without acknowledge. The flow of this operation is explained below. To make the transmitter terminate transmission, perform the following operations before the last data bit is received: 1. Read the received data from I2C0DBR. 2. Clear I2C0CR1<ACK> to 0 and set I2C0CR1<BC> to 0y000. 3. Write dummy data (0x00) to I2C0DBR to set I2C0CR2<PIN> to 1. After I2C0CR2<PIN> is set to 1, 1-word transfer with no acknowledge operation is performed. After 1-word transfer is completed, perform the following operations: 1. Read the received data from I2C0DBR. 2. Clear I2C0CR1<ACK> to 0 and set I2C0CR1<BC> to 0y001 (negative acknowledge). 3. Write dummy data (0x00) to I2C0DBR to set I2C0CR2<PIN> to 1. When I2C0CR2<PIN> is set to 1, 1-bit transfer is performed. Since the master is acting as a receiver, the SDA line on the bus remains high. The transmitter receives this high-level signal as the negative acknowledge signal. The receiver can thus indicate the transmitter that the data transmission is completed. After 1-bit data is received and an interrupt request is generated, generate a stop condition to terminate the data transfer. TMPA910CRA- 415 2010-06-02 TMPA910CRA I2C0CL pin 9 I2C0DA pin 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 1 Negative ACK to transmitter I2C0SR<PIN> I2CINT0 interrupt request I2C0IR<IR> = 1 write After reading the received data, clear I2C0CR1<ACK> to 0 and write dummy data (0x00). I2C0IR<IR> = 1 write After reading the received data, set I2C0CR1<BC> to 0y001 and write dummy data (0x00). Figure 3.14.8 Terminating data transmission in master receiver mode TMPA910CRA- 416 2010-06-02 TMPA910CRA (2) When I2C0SR<MST> = 0 (Slave mode) The following explains normal slave mode operations and the operations to be performed when I2C changes to slave mode after losing arbitration on the bus. In slave mode, an I2CINT0 interrupt request is generated by the following conditions: * When I2C0CR1<NOACK> is 0, after the acknowledge signal is output to indicate that the received slave address has matched the slave address set in I2C0AR<SA> * When I2C0CR1<NOACK> is 0, after the acknowledge signal is output to indicate that a general call has been received * When data transfer is completed after a matched slave address or general call is received. I2C changes to slave mode if it loses arbitration while operating in master mode. After completion of the word transfer in which arbitration lost occurred, an I2CINT0 interrupt request is generated. Table 3.14.1 shows the I2CINT0 interrupt request and I2C0SR<PIN> operations when arbitration lost occurs. TMPA910CRA- 417 2010-06-02 TMPA910CRA Table 3.14.1 I2CINT0 interrupt request and I2C0SR<PIN> operations after arbitration lost I2CINT0 When arbitration lost occurs during When arbitration lost occurs during transmission of transmission of slave address as master data as master transmitter An I2CINT0 interrupt request is generated after the current word of data has been transferred. interrupt request I2C0SR<PIN> I2C0SR<PIN> is cleared to 0. When an I2CINT0 interrupt request occurs, I2C0SR<PIN> is reset to 0, and I2C0CL is pulled low. Either writing data to I2C0DBR or setting I2C0CR2<PIN> to 1 releases I2C0CL after the tLOW period. Check I2C0SR<AL>, I2C0SR<TRX>, I2C0SR<AAS> and I2C0SR<AD0>, and implement required operations, as shown in Table 3.14.2. Table 3.14.2 Operations in slave mode I2C0SR I2C0SR I2C0SR I2C0SR <TRX> <AL> <AAS> <AD0> 1 Condition 1 0 The device loses arbitration during slave address transmission, and receives a slave address with direction bit set to 1 from another master. 1 0 In slave receiver mode, the device receives a slave address with direction bit set to 1 from the master. 1 0 0 0 In slave transmitter mode, the device completes the transmission of 1-word data. Operation Set the number of bits in 1 word to I2C0CR1<BC> and write the data to be transmitted to I2C0DBR. Check I2C0SR<LRB>. If it is set to 1, the receiver is not requesting the next data, so set I2C0CR2<PIN> to 1. Then, clear I2C0CR2<TRX> to 0 to release the bus. If I2C0SR<LRB> = 0, the receiver is requesting the next data, so set the number of bits in 1 word in I2C0CR1<BC> and write the data to be transmitted to I2C0DBR. 1/0 The device loses arbitration during slave address transmission, and receives a slave address with direction bit set to 0 from another master or receives a general call. Write dummy data (0x00) to I2C0DBR to set I2C0SR<PIN> to 1, or write 1 to I2C0CR2<PIN>. 0 The device loses arbitration when transmitting a slave address or data, and completes transferring the current word of data. The device is set as a slave. Clear I2C0SR<AL> to 0 and write dummy data (0x00) to I2C0DBR to set I2C0SR<PIN> to 1. 1 1/0 In slave receiver mode, the device receives a slave address with direction bit set to 0 from another master or receives a general call. Write dummy data (0x00) to I2C0DBR to set I2C0SR<PIN> to 1, or write 1 to I2C0CR2<PIN>. 0 1/0 In slave receiver mode, the device completes the receipt of 1-word data. Set the number of bits in 1 word to I2C0CR1<BC>, read the received data from I2C0DBR and write dummy data (0x00). 1 1 0 0 0 2 Note: In slave mode, if I2C0AR<SA> is set to 0x00 and a START byte (0x01) of the I C bus standard is received, a slave address match is detected and I2C0SR<TRX> is set to 1. Do not set I2C0AR<SA> to 0x00. TMPA910CRA- 418 2010-06-02 TMPA910CRA 4. Stop Condition Generation When I2C0SR<BB> is 1, writing 1 to I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<PIN> and 0 to I2C0CR2<BB> initiates the sequence for generating a stop condition on the bus. Do not change the contents of I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<BB> and I2C0CR2<PIN> until a stop condition is generated on the bus. If the I2C0CL line is pulled low by another device when the sequence for generating a stop condition is started, a stop condition will be generated after the I2C0CL line is released. It takes the tHIGH period for a stop condition to be generated after the I2C0CL line is released. Programming example: Generating a stop condition I2C0CR2 0xD8 ; Set I2C0CR2<MST>,<TRX>,<PIN> to 1 and I2C0CR2<BB> to 0. CHK _ BB: r1 (I2C0SR) AND r1, #0x20 CMP r1, #0x00 BNE CHK _ BB ; Check that the bus is free. If I2C0CL is pulled low by another device, a I2C0CR2<MST> = 1 I2C0CR2<TRX> = 1 stop condition is generated after I2C0CL is released. I2C0CR2<BB> = 0 I2C0CR2<PIN> = 1 Stop condition I2C0CL (Actual signal state) I2C0CL (Master drive request) I2C0DA I2C0CR2<PIN> I2C0SR<BB> Figure 3.14.9 Stop condition generation TMPA910CRA- 419 2010-06-02 TMPA910CRA 5. Restart Procedure Restart is used to change the direction of data transfer without the master device terminating data transfer to the slave device. The restart procedure is explained below. First, write 0 to I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<BB> and 1 to I2C0CR2<PIN>. The I2C0DA line remains high and the I2C0CL line is released. Since this is not a stop condition, the bus remains busy for other devices. Next, check I2C0SR<BB> until it is cleared to 0 to make sure that the I2C0CL line is released. Then, check I2C0SR<LRB> until it becomes 1 to make sure that the I2C0CL line is not pulled low by another device. After making sure that the bus is free by these steps, generate a start condition as explained earlier in "2. Start Condition and Slave Address Generation". In order to satisfy the setup time requirement for restart, it is necessary to insert, by software, a wait period of 4.7 s or longer in the case of standard mode and 0.6 s or longer in the case of fast mode. Note: When the master device is operating as a receiver, it is necessary to terminate the data transfer from the slave transmitter before the restart procedure can be started. To do so, the master device makes the slave device receive the negative acknowledge signal (high). Therefore, I2C0SR<LRB> is set to 1 before the restart procedure is started. The SCL line level cannot be determined by checking I2C0SR<LRB> = 1 in the restart procedure. The state of the I2C0CL line shold be checked by reading the port. Programming example: Generating a restart condition (I2C0CR2) 0x18 ; Set I2C0CR2<MST>, <TRX>,<BB> to 0 and I2C0CR2<PIN> to 1. CHK _ BB: CHK _ LRB: r1 (I2C0SR) AND r1, #0x20 CMP r1, #0x00 BNE r1 ; Wait until I2C0SR<BB> is cleared to 0. CHK _ BB (I2C0SR) AND r1, #0x01 CMP r1, #0x01 BNE CHK _ LRB ; Wait until I2C0SR<LRB> becomes 1. ; Wait by software (I2C0CR2) 0xF8 ; Set I2C0CR2<MST>, <TRX>, <BB>, <PIN> to 1. TMPA910CRA- 420 2010-06-02 TMPA910CRA 0 <MST> 0 <TRX> 0 <BB> 1 <PIN> 1 <MST> 1 <TRX> 1 <BB> 1 <PIN> 4.7 s (min.) Start condition I2C0CL (Actual signal state) I2C0CL (Master drive request) I2C0DA I2C0SR<LRB> I2C0SR<BB> I2C0SR<PIN> Figure 3.14.10 Restart timing chart Note: When <MST> = 0, do not write 0 to <MST>. (Restart cannot be performed.) TMPA910CRA- 421 2010-06-02 TMPA910CRA 3.14.5 Register Descriptions The following lists the SFRs. Base address = 0xF007_0000 Register Address Name (base +) Description 2 I2C0CR1 0x0000 I C0 Control Register 1 I2C0DBR 0x0004 I C0 Data Buffer Register I2C0AR 0x0008 I C0 (Slave) Address Register I2C0CR2 I2C0SR 2 2 2 0x000C I C0 Control Register 2 2 I C0 Status Register 2 I2C0PRS 0x0010 I C0 Prescaler Clock Set Register I2C0IE 0x0014 I C0 Interrupt Enable Register I2C0IR 0x0018 I C0 Interrupt Register 2 2 Base address = 0xF007_1000 Register Address Name (base +) Description 2 I2C1CR1 0x0000 I C1 Control Register 1 I2C1DBR 0x0004 I C1 Data Buffer Register I2C1AR 0x0008 I C1 (Slave) Address Register I2C1CR2 I2C1SR 2 2 2 0x000C I C1 Control Register 2 2 I C1 Status Register 2 I2C1PRS 0x0010 I C1 Prescaler Clock Set Register I2C1IE 0x0014 I C1 Interrupt Enable Register I2C1IR 0x0018 I C1 Interrupt Register 2 2 TMPA910CRA- 422 2010-06-02 TMPA910CRA Note: This module contains two channels of the identical structure. Therefore, the registers of channel 0 only are described. 1. I2C0CR1 (I2C0 Control Register 1) Address = (0xF007_0000) + (0x0000) Bit Bit Symbol Reset Type Description Value [31:8] - - Undefined [7:5] BC[2:0] R/W 0y000 Read as undefined. Write as zero. Number of transfer bits 0y000: 8 bits [4] ACK R/W 0y0 0y100: 4 bits 0y001: 1 bit 0y101: 5 bits 0y010: 2 bits 0y110: 6 bits 0y011: 3 bits 0y111: 7 bits Acknowledge clock generation and recognition 0y0: Disable 0y1: Enable [3] NOACK R/W 0y0 Slave address match detection and general call detection 0y0: Enable 0y1: Disable [2:0] SCK[2:0] R/W 0y000 Serial clock frequency 0y000: n=0 0y100: n=4 0y001: n=1 0y101: n=5 0y010: n=2 0y110: n=6 0y011: n=3 0y111: n=7 [Description] a. <BC[2:0]> These bits select the number of transfer bits. 0y000: 8 bits 0y100: 4 bits 0y001: 1 bit 0y101: 5 bits 0y010: 2 bits 0y110: 6 bits 0y011: 3 bits 0y111: 7 bits b. <ACK> This bit specifies whether to disable or enable acknowledge clock generation and recognition. 0y0: Disable 0y1: Enable TMPA910CRA- 423 2010-06-02 TMPA910CRA c. <NOACK> This bit specifies whether to enable or disable the slave address match detection and general call detection when this module is a slave. 0y0: Enable 0y1: Disable When I2C0AR<ALS> = 1, this bit has no meaning. When <NOACK> = 0, the slave address match detection and general call detection are enabled. When a slave address match or general call is detected, the slave pulls the SDA line low during the 9th (acknowledge) clock output from the master to return an acknowledge signal. Setting <NOACK> = 1 disables the slave address match detection and general call detection. When a slave address match or general call is detected, the slave releases (holds high) the SDA line during the 9th (acknowledge) clock output from the master to return no acknowledge signal. d. <SCK[2:0]> These bits are used to set the rate of serial clock to be output from the master. The prescaler clock divided according to I2C0PRS<PRSCK[4:0]> is used as the reference clock for serial clock generation. The prescaler clock is further divided according to I2C0CR1<SCK[2:0]> to generate the serial clock. The default setting of the prescaler clock is "divide by 1" (= fPCLK). Note: Refer to Section 3.14.5 6. I2C0PRS (I2C0 Prescaler Clock Set Register)" and Section 3.14.6.3 "Serial Clock". Writes to this register must be done before a start condition is generated or after a stop condition is generated or between the instant when an address or data transfer interrupt occurs and the instant when the internal interrupt is released. Do not write to this register during address or data transfer. TMPA910CRA- 424 2010-06-02 TMPA910CRA I2C0DBR (I2C0 Data Buffer Register) 2. Address = (0xF007_0000) + (0x0004) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. [7:0] DB[7:0] RO 0x00 Read: Receive data is read (Note) Address = (0xF007_0000) + (0x0004) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] DB[7:0] WO 0x00 Write: Transmit data is written (Note) Note: This register is initialized only after a hardware reset. It is not initialized by a software reset. (The most recent data is retained.) [Description] a. <DB[7:0]> These bits are used to store data for serial transfer. When this module is a transmitter, the data to be transmitted is written into DB[7:0] aligned on the left side. When this module is a receiver, the received data is stored into DB[7:0] aligned on the right side. When the master needs to transmit a slave address, the transfer target address is written to I2C0DBR<DB[7:1]> and the transfer direction is specified in I2C0DBR<DB[0]> as follows: 0y0: Master (transmitter) Slave/receiver 0y1: Master (receiver) Slave/transmitter When all the bits in the I2C0DBR register are written as 0, a general call can be sent out on the bus. In both transmitter and receiver modes, a write to the I2C0DBR register releases the internal interrupt after the current transfer and initiates the next transfer. Although I2C0DBR is provided as a transmit/receive buffer, it should be used as a dedicated transmit buffer in transmit mode and as a dedicated receive buffer in receive mode. This register should be accessed on a transfer-by-transfer basis. Note: In receive mode, if data is written to I2C0DBR before the received data is read out, the received data will be corrupted. TMPA910CRA- 425 2010-06-02 TMPA910CRA 3. I2C0AR (I2C0 (Slave) Address Register) Address = (0xF007_0000) + (0x0008) Bit Bit Symbol Reset Type Description Value [31:8] - - Undefined [7:1] SA[6:0] R/W 0y0000000 Set the slave address. [0] ALS R/W 0y0 Address recognition enable/disable 2 0y0: Enable (I C bus mode) 0y1: Disable (Free data format) Read as undefined. Write as zero. [Description] a. <SA[6:0]> These bits are used to set the slave device address (7 bits) when this module is a slave. When slave address recognition is enabled in I2C0AR<ALS>, the data transfer operation to be performed is determined by the 7-bit address (plus one direction bit) that the master sends immediately after a start condition. b. <ALS> This bit is used to enable or disable slave address recognition. 0y0: Enable (I2C bus mode) 0y1: Disable (Free data format) When this module is a slave, this bit specifies whether or not to recognize the 8-bit data that the master sends immediately after a start condition as a 7-bit address plus one direction bit. When <ALS> = 0, I2 C bus mode is selected. When <ALS> = 1, transfer operation is performed based on the free data format. When <ALS> = 0, the device compares the 7-bit address sent from the master against the slave address set in I2C0AR<SA[6:0]>. If the 7-bit address matches the slave address, the device uses the direction bit to determine whether to act as a transmitter or receiver. At this time, if I2C0CR1<NOACK> = 0, the device pulls the SDA line low during the 9th (acknowledge) clock output from the master. Thereafter, the device continues to perform transmit or receive operation as a slave until a stop condition or a start condition by the restart procedure appears on the bus. If the 7-bit address does not match the slave address, the device continues to leave the SDA line and SCL line high and does not participate in transfer operation until a stop condition or a start condition by the restart procedure appears on the bus. If the 7-bit address plus one direction bit sent from the master are all 0s (indicating a general call) and I2C0CR1<NOACK> = 0, the device returns an acknowledge signal and acts as a slave receiver regardless of the slave address set in I2C0AR<SA[6:0]>. When I2C0CR1<NOACK> = 1, the device does not return any acknowledge signal nor operate as a slave device even if the 7-bit address matches the slave address or a general call is detected. When <ALS> = 1, the device receives the 7-bit address plus one direction bit sent from the master as data and pulls the SDA line low during the 9th (acknowledge) clock output from the master. Thereafter the device continues to perform receive operation as a slave until a stop condition or a start condition by the restart procedure appears on the bus (free format operation). In this case, the I2C0CR1<NOACK> value has no effect. Writes to this register must be done before a start condition is generated or after a stop condition is generated. Writes cannot be performed during transfer. TMPA910CRA- 426 2010-06-02 TMPA910CRA I2C0CR2 (I2C0 Control Register 2) 4. (Write Only) Address = (0xF007_0000) + (0x000C) Bit Bit Symbol Reset Type Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] MST WO 0y0 Selects master or slave mode. 0y0: Slave 0y1: Master [6] TRX WO 0y0 Selects transmit or receive operation. 0y0: Receiver 0y1: Transmitter [5] BB WO 0y0 Selects whether to generate a start or stop condition. 0y0: Generate a stop condition. 0y1: Generate a start condition. [4] PIN WO 0y1 Service request clear 0y0: No effect 0y1: Clear service request [3] I2CM WO 0y0 2 I C operation control 0y0: Disable 0y1: Enable [2] - - Undefined Read as undefined. Write as zero. [1:0] SWRES[1:0] WO 0y00 Software reset A software reset is generated by writing 0y10 and then 0y01 to these bits. [Description] a. <MST> This bit selects master or slave mode. 0y0: Slave 0y1: Master Note: Refer to Section 3.14.6.3 "Serial CLock". b. <TRX> This bit selects transmitter or receiver mode. 0y0: Receiver 0y1: Transmitter Note: Refer to Section 3.14.6.3 "Serial Clock". c. <BB> This bit is used to generate a start or stop condition. 0y0: Generate a stop condition. 0y1: Generate a start condition. Note: Refer to Section 3.14.6.3 "Serial Clock". TMPA910CRA- 427 2010-06-02 TMPA910CRA d. <PIN> This bit is used to clear a service request for I2C communication. 0y0: Invalid 0y1: Clear service request Note: Refer to Section 3.14.6.3 "Serial Clock". e. <I2CM> This bit enables or disables I2C operation. 0y0: Disable 0y1: Enable The <I2CM> bit cannot be cleared to 0 to disable I2C operation while transfer operation is being performed. Before clearing this bit, make sure that transfer operation is completely stopped by reading the status register. f. <SWRES[1:0]> Writing 0y10 and then 0y01 to these bits generates a software reset (reset width = one fPCLK clock pulse). If a software reset occurs, the SCL and SDA lines are forcefully released (driven high) to abort any ongoing transfer operation. All the settings except I2C0CR2<I2CM> are initialized. (I2C0DBR is not initialized.) When generating a software reset, be sure to write 0 to I2C0CR2[7:4]. TMPA910CRA- 428 2010-06-02 TMPA910CRA 5. I2C0SR (I2C0 Status Register) (Read Only) Address = (0xF007_0000) + (0x000C) Bit Bit Symbol Reset Type Description Value [31:8] - - Undefined [7] MST RO 0y0 Read as undefined. Write as zero. Master/slave selection state monitor 0y0: Slave 0y1: Master [6] TRX RO 0y0 Transmit/receive selection state monitor 0y0: Receiver 0y1: Transmitter [5] BB RO 0y0 Bus state monitor 0y0: The bus is free. 0y1: The bus is busy. [4] PIN RO 0y1 Service request state and SCL line state monitor 0y0: Service request present, SCL line = low 0y1: No service request, SCL line = free [3] AL RO 0y0 Arbitration lost detection monitor 0y0: Invalid 0y1: Detected [2] AAS RO 0y0 Slave address match detection monitor 0y0: Invalid 0y1: Detected [1] AD0 RO 0y0 General call detection monitor 0y0: Invalid 0y1: Detected [0] LRB RO 0y0 Last received bit monitor 0y0: The bit received last is 0. 0y1: The bit received last is 1. [Description] a. <MST> This bit monitors whether master or slave mode is selected. 0y0: Slave 0y1: Master b. <TRX> This bit monitors whether transmitter or receiver mode is selected. 0y0: Receiver 0y1: Transmitter TMPA910CRA- 429 2010-06-02 TMPA910CRA c. <BB> This bit monitors the bus status. 0y0: The bus is free. 0y1: The bus is busy. This bit is set to 1 after a start condition is detected on the bus. It is cleared to 0 on detection of a stop condition. When the device is operating as a slave, this bit is set to 1 to monitor the generation of a stop condition even if the device is not selected by the master and is not involved in transfer operation. While this bit is set to 1, the start condition cannot be generated. d. <PIN> This bit monitors the service request state and SCL state. 0y0: Service request present, SCL line = low 0y1: No service request, SCL line = free e. <AL> This bit monitors the detection of arbitration lost. 0y0: Invalid 0y1: Detected f. <AAS> This bit monitors the detection of a slave address match. 0y0: Invalid 0y1: Detected When the device is operating as a slave, this bit is set to 1 if the slave address sent from the master matches the slave address set in I2C0AR<SA[6:0]>. This bit is then cleared to 0 after the internal interrupt is released and remains 0 until a stop condition or a start condition by the restart procedure appears on the bus and it is again set to 1 by a slave address match in address transfer after that start condition. g. <AD0> This bit monitors the detection of a general call. 0y0: Invalid 0y1: Detected This bit is set to 1 on detection of a general call (the SDA line is held low during address transfer after a start condition) and remains set until a stop condition or a start condition by the restart procedure appears on the bus. I2C0SR<AAS> is also set to 1 on detection of a general call. However, this bit is cleared to 0 at the next data transfer as described earlier. TMPA910CRA- 430 2010-06-02 TMPA910CRA h. <LRB> This bit monitors the last received bit. 0y0: The bit received last is 0. 0y1: The bit received last is 1. When acknowledge operation is enabled, this bit can be used to check whether or not the receiver has output an acknowledge signal (low) by reading the bit in the interrupt routine after the transfer. This monitor is effective regardless of whether the device is set as a transmitter or receiver. Note: Rerer to Section 3.14.6.15 Register Values after a Software Reset ". TMPA910CRA- 431 2010-06-02 TMPA910CRA 6. I2C0PRS (I2C0 Prescaler Clock Set Register) Address = (0xF007_0000) + (0x0010) Bit Bit Symbol Type Reset Description Value [31:5] - - Undefined Read as undefined. Write as zero. [4:0] PRSCK[4:0] R/W 0y00001 Prescaler clock frequency for generating the serial clock 0y00000: p = Divide by 32 0y00001: p = Divide by 1 ~ 0y11111: p = :Divide by 31 [Description] a. <PRSCK[4:0]> These bits are used to select the prescaler clock frequency for generating the serial clock. 0y00000: p = Divide by 32 0y00001: p = Divide by 1 ~ : 0y11111: p = Divide by 31 Note: Refer to Section 3.14.5 "1. I2C0CR1 (I2C0 Control Register 1)" and Section 3.14.6.3 "Serial Clock". TMPA910CRA- 432 2010-06-02 TMPA910CRA I2C0IE (I2C0 Interrupt Enable Register) 7. Address = (0xF007_0000) + (0x0014) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined Read as undefined. Write as zero. [0] IE R/W 0y0 I C interrupts 2 0y0: Disable 0y1: Enable [Description] a. <IE> This bit is used to enable or disable I2C interrupts. 0y0: Disable 0y1: Enable TMPA910CRA- 433 2010-06-02 TMPA910CRA 8. I2C0IR (I2C0 Interrupt Register) Address = (0xF007_0000) + (0x0018) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined Read as undefined. Write as zero. [0] IS/IC R/W 0y0 (Read) 2 Indicates I C interrupt status (before being disabled). 0y0: No interrupt 0y1: Interrupt generated (Write) 2 Clears the I C interrupt. 0y0: Invalid 0y1: Clear [Description] a. <IS/IC> (Read) This bit indicates the I2C interrupt status prior to masking by I2C0IE<IE>. 0y0: No interrupt 0y1: Interrupt generated (Write) This bit is used to clear the I2C interrupt. 0y0: Invalid 0y1: Clear Writing 1 to this bit clears the I2C interrupt output (I2CINT0). Writing 0 is invalid. TMPA910CRA- 434 2010-06-02 TMPA910CRA 3.14.6 Functions 3.14.6.1 Slave Address Match Detection and General Call Detection For a slave device, the following setting is made for slave address match detection and general call detection. I2C0CR1<NOACK> enables or disables the slave address match detection and general call detection in slave mode. Clearing I2C0CR1<NOACK> to 0 enables the slave address match detection and general call detection. Setting I2C0CR1<NOACK> to 1 disables the slave address match detection and general call detection. The slave device ignores slave addresses and general calls sent from the master and returns no acknowledgement. I2CINT0 interrupt requests are not generated. In master mode, I2C0CR1<NOACK> is ignored and has no effect on operation. Note: If I2C0CR1<NOACK> is cleared to 0 during data transfer in slave mode, it remains 1 and an acknowledge signal is returned for the transferred data. 3.14.6.2 Number of Clocks for Data Transfer and Acknowledge Operation (1) Number of clocks for data transfer The number of clocks for data transfer is set through I2C0CR1<BC> and I2C0CR1<ACK>. Setting I2C0CR1<ACK> to 1 enables acknowledge operation. The master device generates clocks for the number of data bits to be transferred, and then generates an acknowledge clock and an I2CINT0 interrupt request. The slave device counts clocks for the number of data bits, and then counts an acknowledge clock and generates an I2CINT0 interrupt request. Clearing I2C0CR1<ACK> to 0 disables acknowledge operation. The master device generates clocks for the number of data bits to be transferred, and then generates an I2CINT0 interrupt request. The slave device counts clocks for the number of data bits, and then generates an I2CINT0 interrupt request. When acknowledge operation is enabled in receiver mode, the device pulls I2C0DA low during the acknowledge clock period from the master to request the transfer of the next word. Conversely, by holding I2C0DA high during the acknowledge clock period from the master, the receiver device can indicate that it is not requesting the next word. During address transmission (before a start condition is generated), both the master and slave must be configured for 8-bit transfer with acknowledge enabled. I2C0CR1<BC> = 0y011, I2C0CR1<ACK> = 1 I2C0CR1<BC> = 0y110, I2C0CR1<ACK> = 0 I2C0CL 1 2 3 4 5 6 1 2 3 4 I2CINT0 interrupt request Figure 3.14.11 Number of clocks for data transfer according to I2C0CR1<BC> and I2C0CR1<ACK> TMPA910CRA- 435 2010-06-02 TMPA910CRA Table 3.14.3 shows the relationship between the number of clocks for data transfer and the I2C0CR1<BC> and I2C0CR1<ACK> settings. Table 3.14.3 Number of clocks for data transfer Acknowledge operation (I2C0CR1<ACK>) 0y0: Disabled BC[2:0] Data length Number of clocks 0y1: Enabled Data length Number of clocks 000 8 8 8 9 001 1 1 1 2 010 2 2 2 3 011 3 3 3 4 100 4 4 4 5 101 5 5 5 6 110 6 6 6 7 111 7 7 7 8 I2C0CR1<BC> is cleared to 0y000 by a start condition. This means that the slave address and direction bit are always transferred as 8-bit data. At other times, <BC> retains the set value. Note: A slave address must be transmitted/received with I2C0CR1<ACK> set to 1. If I2C0CR1<ACK> is cleared, the slave address match detection and direction bit detection cannot be performed properly. TMPA910CRA- 436 2010-06-02 TMPA910CRA (2) Acknowledge output When acknowledge operation is enabled, I2C0DA changes during the acknowledge clock period as explained below. * Master mode The master transmitter releases I2C0DA during the acknowledge clock period to receive the acknowledge signal from the slave receiver. The master receiver pulls I2C0DA low during the acknowledge clock period and to generate the acknowledge signal. * Slave mode When the received slave address matches the slave address set in I2C0AR<SA> or when a general call is received, the slave pulls I2C0DA low during the acknowledge clock period to generate the acknowledge signal. In data transfer after a slave address match or a general call, the slave transmitter releases I2C0DA during the acknowledge clock period to receive the acknowledge signal from the master receiver. The slave receiver pulls I2C0DA low during the acknowledge clock period to generate the acknowledge signal. Table 3.14.4 shows the I2C0CL and I2C0DA states when acknowledge operation is enabled. Note: When acknowledge operation is disabled, no acknowledge clock is generated or counted and no acknowledge signal is output. Table 3.14.4 I2C0CL and I2C0DA states when acknowledge is enabled Mode Master Pin I2C0CL I2C0DA Condition - - Transmitter Receiver Adds the acknowledge Adds the acknowledge clock pulse. clock pulse. Releases the pin to Pulls the pin low as the receive the acknowledge acknowledge signal. signal. Slave I2C0CL I2C0DA - Counts the acknowledge When a slave address Counts the acknowledge clock pulse. clock pulse. - Pulls the pin low as the match is detected or a acknowledge signal. general call is received. During transfer after a Releases the pin to Pulls the pin low as the slave address match is receive the acknowledge acknowledge signal. detected or a general call signal. is received TMPA910CRA- 437 2010-06-02 TMPA910CRA 3.14.6.3 Serial Clock (1) Clock source I2C0CR1<SCK> is used to set the high and low periods of the serial clock to be output in master mode. tHIGH (i / Tprsck) tLOW(j / Tprsck) i j 0y000 8 12 0y001 10 14 0y010 14 18 0y011 22 26 0y100 38 42 0y101 70 74 0y110 134 138 0y111 262 266 SCK tHIGH tLOW 1/fscl I2CxCL signal tHIGH = (i/Tprsck) tLOW = (j/Tprsck) fscl = 1/(tHIGH + tLOW) Figure 3.14.12 I2CxCL output Note: The tHIGH period may differ from the specified value if the rising edge becomes blunt depending on the combination of bus load capacitance and pull-up resistor. If the clock synchronization function for synchronizing clocks from multiple clocks is used, the actual clock period may differ from the specified setting. In master mode, the hold time when a start condition is generated and the setup time when a stop condition is generated are defined as tHIGH [s]. When I2C0CR2<PIN> is set to 1 in slave mode, the time to the release of I2C0CL is defined as tLOW [s]. In both master and slave modes, the high level period must be 4/Tprsck [s] or longer and the low level period must be 5/Tprsck [s] or longer for externally input serial clocks, regardless of the I2C0CR1<SCK> setting. tHIGH tLOW tHIGH > = (4/Tprsck) tLOW > = (5/Tprsck) Figure 3.14.13 SCLK input TMPA910CRA- 438 2010-06-02 TMPA910CRA The serial clock rate to be output from the master is set through I2C0CR1<SCK[2:0]> and I2C0PRS<PRSCK[4:0]>. The prescaler clock which is divided according to I2C0PRS<PRSCK[4:0]> is used as the reference clock for generating the serial clock. The prescaler clock is further divided according to I2C0CR1<SCK[2:0]> and used as the serial clock. The default setting of the prescaler clock is "divide by 1 ( PCLK)". <Serial transfer rate> The serial clock rate (Fscl) is determined by prescaler setting value "p" (I2C0PRS <PRSCK[4:0]>, p = 1-32) and serial clock setting value "n" (2C0CR1<SCK[2:0]>, n = 0-7) based on the operating frequency (PCLK) as follows: PCLK(MHz) Serial clock rate Fscl (kHz) p x( 2 Note: n2 x 1000 16 ) The allowed range of prescaler setting value "p" (I2C0PRS<PRSCK[4:0]>) varies depending on the operating frequency (PCLK) and must satisfy the following condition: 50 ns < Prescaler clock width Tprsck (ns) 150ns Note: Setting the prescaler clock width out of this range is prohibited in both master and slave modes. The serial clock rate may not be constant due to the clock synchronization function. PRSCK [4:0] = (p) SCK[2:0] = (n) 0y00001 (divide by 1) 0y01101 (divide by 13) 0y00000 (divide by 32) (Ratio to PCLK) 0 0 0 20 260 640 0 0 1 24 312 768 0 1 0 32 416 1024 0 1 1 48 624 1536 1 0 0 80 1040 2560 1 0 1 144 1872 4608 1 1 0 272 3536 8704 1 1 1 528 6864 16896 Writes to these bits must be done before a start condition is generated or after a stop condition is generated. Writes during transfer will cause unexpected operation. <Prescaler clock width (= noise cancellation width)> The prescaler clock width (Tprsck) (= noise cancellation width) is determined by prescaler setting value "p" (I2C0PRS<PRSCK[4:0]>, p = 1-32) based on the operating frequency (PCLK) as follows: Prescaler clock width Tprsck (ns) (= Noise cancellation width) TMPA910CRA- 439 1 x 1000 x p PCLK (MHz) 2010-06-02 TMPA910CRA (2) Clock synchronization The I2C bus is driven by the wired AND method, and a master device that first pulls down the clock line low invalidates the clock outputs from other masters on the bus. Masters who are keeping the clock line high need to detect this situation and act as required. I2C has a clock synchronization function to ensure proper transfer operation even when multiple masters exist on the bus. The clock synchronization procedure is explained below using an example where two masters simultaneously exist on the bus. High period count standby High period count start Internal SCL output (Master A) High period count reset Internal SCL output (Master B) SCL line a b c Figure 3.14.14 Example of clock synchronization As Master A pulls I2C0CL low at point "a", the SCL line of the bus becomes low. After detecting this situation, Master B resets the high level period count and pulls I2C0CL low. Master A finishes counting the low level period at point "b" and sets I2C0CL to high. Since Master B is still holding the SCL line low, Master A does not start counting the high level period. Master A starts counting the high level period after Master B sets I2C0CL to high at point "c" and the SCL line of the bus becomes high. Then, after counting the high level period, Master A pulls I2C0CL low and the SCL line of the bus becomes low. The clock operation on the bus is determined by the master device with the shortest high level period and the master device with the longest low level period among master devices connected to the bus. 3.14.6.4 Master/Slave Selection When I2C0CR2<MST> is set to 1, I2C is configured as a master device. When I2C0CR2<MST> is cleared to 0, it is configured as a slave device. I2C0SR<MST> is cleared to 0 by hardware when a stop condition or arbitration lost is detected on the bus. TMPA910CRA- 440 2010-06-02 TMPA910CRA 3.14.6.5 Transmitter/Receiver Selection When I2C0CR2<TRX> is set to 1, I2C is configured as a transmitter. When I2C0CR2<TRX> is cleared to 0, it is configured as a receiver. In I2C data transfer in slave mode, I2C0SR<TRX> is set to 1 by hardware if the direction bit (R/W) sent from the master is 1, and is cleared to 0 if the direction bit is 0. In master mode, I2C0SR<TRX> is cleared to 0 by hardware, after acknowledge is returned from the slave device, if the transmitted direction bit is 1, and is set to 1 if the direction bit is 0. If no acknowledge is returned, I2C0SR<TRX> remains unchanged. I2C0SR<TRX> is cleared to 0 by hardware when a stop condition or arbitration lost is detected on the bus. Table 3.14.5 summarizes the operation of I2C0SR<TRX> in slave and master modes. Note: When I2C0CR1<NOACK> = 1, the slave address detection and general call detection are disabled, and thus I2C0SR<TRX> remains unchanged. Table 3.14.5 I2C0SR<TRX> operation in slave and master modes Mode Slave mode Master mode Direction bit Condition for state change 0 When the received slave address matches the slave address set in I2C0AR<SA> 1 0 1 When the ACK signal is returned. Changed <TRX> state 0 1 1 0 When I2C is used with the free data format, the slave address and direction bit are not recognized and bits immediately following a start condition are handled as data. Therefore, I2C0SR<TRX> is not changed by hardware. TMPA910CRA- 441 2010-06-02 TMPA910CRA 3.14.6.6 Generation of Start and Stop Conditions When I2C0SR<BB> = 0, writing 1 to I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<BB> and I2C0CR2<PIN> causes a start condition, the slave address written in the data buffer register and direction bit to be sent out on the bus. I2C0CR1<ACK> must be set to 1 before a start condition is generated. SCL line 1 2 3 4 5 6 7 SDA line A6 A5 A4 A3 A2 A1 A0 Start condition 8 9 R/W Slave address and direction bit ACK signal I2CINT0 interrupt request Figure 3.14.15 Start condition and slave address generation When I2C0SR<BB> = 1, writing 1 to I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<PIN> and 0 to I2C0CR2<BB> initiates a sequence for sending out a stop condition on the bus. At this time, if the SCL line is pulled low by another device, a stop condition is generated after the SCL line is released. SCL line SDA line Stop condition SCL (line) Internal SDA output (Master A) Internal SDA output (Master B) Arbitration lost Internal SDA output = "1" SDA line a b Figure 3.14.16 Stop condition generation The bus status can be checked by reading I2C0SR<BB>. I2C0SR<BB> is set to 1 (bus busy) when a start condition is detected on the bus, and is cleared to 0 (bus free) when a stop condition is detected. TMPA910CRA- 442 2010-06-02 TMPA910CRA The following table shows typical setting examples according to the I2C0SR state. Although the I2C0CR2<MST>, <TRX>, <BB> and <PIN> bits are given independent functions, they are used in typical combinations, as shown below, according to the I2C0SR setting. I2C0SR I2C0CR2 [7]MST [5]BB [4]PIN 0 0 1 1 1 0 Operation [7]MST [6]TRX [5]BB [4]PIN 0 0 0 0 Wait for a start condition as a slave. 1 1 1 1 Generate a start condition. 1 1 0 1 Generate a stop condition. 0 0 0 1 Release the internal interrupt for restart. When writing to these bits, be careful not to inadvertently change I2C0CR2<I2CM>. TMPA910CRA- 443 2010-06-02 TMPA910CRA 3.14.6.7 Interrupt Service Request and Cancel In master mode, after the number of bits specified by I2C0CR1<BC> and I2C0CR1<ACK> have been transferred, an I2CINT0 interrupt request is generated. In slave mode, an I2CINT0 interrupt request is also generated by the following conditions in addition to the above condition: * When I2C0CR1<NOACK> is 0, after the acknowledge signal is output to indicate that the received slave address has matched the slave address set in I2C0AR<SA> * When I2C0CR1<NOACK> is 0, after the acknowledge signal is output to indicate that a general call has been received. * When data transfer is completed after a matched slave address or a general call is received. When an I2CINT0 interrupt request is generated, I2C0SR<PIN> is cleared to 0. While I2C0SR<PIN> is 0, I2C0CL is pulled low. tLOW 1 2 3 7 8 I2C0CL 9 I2C0CL is pulled low while I2C0SR<PIN> = 0. 1 I2CINT0 interrupt request signal I2C0SR<PIN> Figure 3.14.17 I2C0SR<PIN> and I2C0CL I2C0CR2<PIN> = 1 or a write to I2C0DBR Writing data into I2C0DBR sets I2C0SR<PIN> to 1. It takes the tLOW period for I2C0CL to be released after I2C0SR<PIN> is set to 1. I2C0CR2<PIN> can be set to 1 by writing 1 whereas it cannot be cleared to 0 by writing 0. TMPA910CRA- 444 2010-06-02 TMPA910CRA 3.14.6.8 I2C Bus Mode When I2C0CR2<I2CM> is set to 1, I2C bus mode is selected. Before enabling I2C bus mode, make sure that the I2C0DA and I2C0CL pins are high and then set I2C0CR2<I2CM> to 1. Before initializing I2C, make sure that the bus is free and then clear I2C0CR2<I2CM> to 0. Note: When I2C0CR2<I2CM> = 0, no value can be written to bits in the I2C0CR2 register other than 2 I2C0CR2<I2CM>. Before setting I2C0CR2, write 1 to I2C0CR2<I2CM> to select I C bus mode. 3.14.6.9 Software Reset I2C has a software reset function. If I2C locks up due to noise, etc., it can be initialized by this function. A software reset can I2C0CR2<SWRES[1:0]>. be generated by writing 0y10 and then 0y01 to After a software reset, I2C is initialized except the I2C0CR2<I2CM> bit and the I2C0DBR register. TMPA910CRA- 445 2010-06-02 TMPA910CRA 3.14.6.10 Arbitration Lost Detection Monitor Since the I2C bus allows multiple masters to exist simultaneously, the bus arbitration feature must be implemented to ensure the integrity of transferred data. The I2C bus uses data on the SDA line for bus arbitration. The following shows an example of the bus arbitration procedure when two master devices exist on the bus simultaneously. Master A and Master B output the same data until point "a", where Master B outputs 1 and Master A outputs 0. This causes the SDA line to be pulled low by Master A since the SDA line is driven by the wired AND method. When the SCL line rises at point "b", the slave device captures the data on the SDA line, i.e., the data from Master A. At this time, the data output from Master B becomes invalid. This is called "arbitration lost". Master B that lost arbitration must release I2C0DA and I2C0CL so that Master A can use the bus without any hindrance. If more than one master outputs identical data on the first word, the arbitration procedure is continued on the second word. SCL (line) Internal SDA output (Master A) Internal SDA output (Master B) Arbitration lost Internal SDA output = 1 SDA line a b Figure 3.14.18 Arbitration lost Master B compares the level of I2C0DA with the level of the SDA line on the bus on the rising edge of the SCL line. If the two levels do not match, arbitration lost is determined and I2C0SR<AL> is set to 1. When I2C0SR<AL> is set to 1, I2C0SR<MST> and I2C0SR<TRX> are cleared to 0, thereby selecting slave receiver mode. Thus, after I2C0SR<AL> is set to 1, Master B stops clock output. After the data transfer on the bus is completed, I2C0SR<PIN> is cleared to 0 and I2C0CL is pulled low. I2C0SR<AL> is cleared to 0 when data is written to or read from I2C0DBR or when data is written to I2C0CR2. TMPA910CRA- 446 2010-06-02 TMPA910CRA Internal SCL output 1 2 3 4 5 6 7 8 9 Master A Internal SDA output Clock output stopped from here Internal SCL output 1 2 3 4 Master B Arbitration lost Internal SDA output is fixed to high. Internal SDA output I2C0SR<AL> I2C0SR<MST> I2C0SR<TRX> Access to I2C0DBR or I2C0CR2 Figure 3.14.19 Arbitration lost operation (with internal flags associated with Master B) 3.14.6.11 Slave Address Match Detection Monitor I2C bus mode (I2C0AR<ALS> = 0) allows slave address match detection when slave mode is selected. Clearing I2C0CR1<NOACK> to 0 enables the slave address match detection. When a general call is received or the slave address sent from the master matches the slave address set in I2C0AR<SA>, I2C0SR<AAS> is set to 1. Setting I2C0CR1<NOACK> to 1 disables the slave address match detection. Even if a general call is received or the salve address sent from the master matches the slave address set in I2C0AR<SA>, I2C0SR<AAS> remains 0. When the free data format is used (I2C0AR<ALS> = 1), it is not used as address match detection, and I2C0SR<AAS> is set to 1 upon receipt of the first word of data. It is cleared to 0 when data is written to or read from I2C0DBR. SCL (bus) SDA (bus) 1 2 3 4 5 6 7 8 SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/ W Start condition 9 Slave address + direction bit I2C0DA ACK output I2C0SR<AAS> I2C0DBR write or read I2CINT0 interrupt request Figure 3.14.20 Changes in the slave address match monitor TMPA910CRA- 447 2010-06-02 TMPA910CRA 3.14.6.12 General Call Detection Monitor I2C bus mode (I2C0AR<ALS> = 0) also allows the detection of a general call as well as slave address match in slave mode. When I2C0CR1<NOACK> = 0, I2C0SR<AD0> is set to 1 when a general call (8 bits received immediately after a start condition are all 0s) is received. (At this time, I2C0SR<AAS> is also set to 1.) Setting I2C0CR1<NOACK> to 1 disables the slave address match detection and general call detection. I2C0SR<AD0> remains 0 even if a general call is received. (At this time, I2C0SR<AAS> also remains 0.) I2C0SR<AD0> is cleared to 0 when a start or stop condition is detected on the bus. SCL 1 2 3 4 5 6 7 8 9 SDA Start condition Stop condition General call I2C0DA ACK output I2C0SR<AD0> I2C0SR<AAS> I2C0DBR write or read I2CINT0 interrupt request Figure 3.14.21 Changes in the general call detection monitor TMPA910CRA- 448 2010-06-02 TMPA910CRA 3.14.6.13 Last Received Bit Monitor I2C0SR<LRB> stores the SDA line value captured on every rising edge of the SCL line. When acknowledge operation is enabled, the acknowledge signal is read from I2C0SR<LRB> immediately after generation of an I2CINT0 interrupt request. SCL (bus) 1 SDA (bus) D7 2 3 4 5 6 7 8 D6 D5 D4 D3 D2 D1 D0 9 ACK D7 I2C0SR<LRB> D6 D5 D4 D3 D2 D1 D0 ACK I2CINT0 interrupt request Figure 3.14.22 Changes in the last received bit monitor 3.14.6.14 Setting the Slave address and Address Recognition Mode To use I2C in I2C bus mode, clear I2C0AR<ALS> to 0 and set a slave address in I2C0AR<SA>. To use the free data format in which slave addresses are not recognized, set I2C0AR<ALS> to 1. When I2C is used with the free data format, the slave address and direction bit are not recognized and bits immediately following a start condition are handled as data. TMPA910CRA- 449 2010-06-02 TMPA910CRA [Notes on Specifications] 3.14.6.15 Register Values after a Software Reset A software reset initializes the I2C registers other than I2C0CR2<I2CM> and internal circuitry and releases the SCL and SDA lines. (Refer to Section 3.14.6.3 "(2) Clock synchronization".) However, depending on read timing after a software reset, reading I2C0SR<LRB> may return a value other than the initial value (0). <When a software reset releases SCL (01) while SDA = 1 > SCL SDA Software reset <I2CM> Other register bits <LRB> Initialized by a software reset After SCL is released, rising is recognized and <LRB> is set to 1. <LRB> = 0 (initial value) on read TMPA910CRA- 450 <LRB> =1 on read 2010-06-02 TMPA910CRA 3.15 SSP (Synchronous Serial Port) This LSI contains the SSP (SSP: Synchronous Serial Port) comprised of two channels. The SSP has the following features: Channel 0 Channel 1 Communication protocol Synchronous serial communication that includes SPI : 3 types Operation mode Master/ Slave mode support Transmit FIFOs 16-bit wide, 8 locations deep Receive FIFOs 16-bit wide, 8 locations deep Transmit/Receive data size 4 to 16 bits Interrupt type Transmit interrupt Receive interrupt Receive overrun interrupt Timeout interrupt Baud rate Master mode: fPCLK/2 (Max 20 Mbps) Slave mode: fPCLK/12 (Max 8.33 Mbps) Internal test function Control pins Internal loopback test mode available SP0CLK SP1CLK SP0FSS SP1FSS SP0DO SP1DO SP0DI SP1DI TMPA910CRA- 451 2010-06-02 TMPA910CRA 3.15.1 Block Diagrams SSP channel 0 PCLK Clock Tx/Rx param prescaler APB APB SSPCLKDIV Write data [15:0] 16 bit x 8 transmit TXD [15:0] FIFO interface and Transmit /receive register block 16 bit x 8 Read data [15:0] RXD [15:0] logic SP0DI SP0DO SP0CLK SP0FSS receive FIFO Transmit buffer servicing request FIFO status Receive buffer servicing request and interrupt generation Timeout Overrun INTS [12] Enabled interrupts SSP channel 1 PCLK SP1DI SP1DO SP1CLK SP1FSS APB INTS [13] Figure 3.15.1 Block diagram of SSP TMPA910CRA- 452 2010-06-02 TMPA910CRA 3.15.2 SSP Overview This LSI contains the SSP comprised of two channels (channel 0 and channel 1). Since the two channels operate identically, operational descriptions are provided for channel 0 only. The SSP is an interface for serial communication with peripheral devices that have three types of synchronous serial interfaces. The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with a 16-bit wide, 8 locations deep independent transmit FIFO and receive FIFO in transmit mode and receive mode, respectively. Serial data is transmitted on SP0DO and received on SP0DI. The SSP contains a programmable prescaler to generate the serial output clock SP0CLK from the input clock PCLK. The SSP operating mode, frame format and size are programmed through the control registers SSP0CR0 and SSP0CR1. (1) Clock prescaler When configured as a master, a clock prescaler comprising two serially linked free-running counters is used to provide the serial output clock SP0CLK. This clock prescaler can be programmed, through the SSP0CPSR register, to divide PCLK by a factor of 2 to 254 in steps of two. By not using the least significant bit of the SSP0CPSR register, division by an odd number cannot be programmed. The output of the prescaler is further divided by a factor of 1 to 256, obtained by adding one to the value programmed in the SSP0CR0 control register, to give the master output clock SP0CLK. Bit rate = fPCLK / (CPSDVSR x (1 + SCR)) PCLK CPSDVSR [7:1] SSPCLKDIV Clock prescaler (SCR [7:0] + 1) Divide circuit Clock inversion trigger Clock initial value (Depends on the setting.) Toggle circuit SPxCLK Figure 3.15.2 Block diagram of Clock prescaler TMPA910CRA- 453 2010-06-02 TMPA910CRA (2) Transmit FIFO The transmit FIFO buffer of 16-bit wide, 8 locations deep are shared with Master mode and Slave mode. (3) Receive FIFO The receive FIFO buffer of 16-bit wide, 8 locations deep are shared with Master mode and Slave mode. (4) Interrupt Four individual maskable interrupts are supported by the SSP. A combined interrupt output is also generated as an OR function of the individual interrupt requests. * * * * Transmit interrupt: Indicates that TxFIFO is more than half empty. (Number of valid entries in TxFIFO 4) Receive interrupt: Indicates that RxFIFO is more than half full. (Number of valid entries in RxFIFO 4) Timeout interrupt: Indicates that data is present in RxFIFO and has not been read before a timeout period expires. Receive overrun interrupt: Indicates that data is written to RxFIFO when it is full. Each of the four individual maskable interrupts can be masked by setting the appropriate bit in the interrupt mask set and clear register. Setting the appropriate mask bit High enables the interrupt. TMPA910CRA- 454 2010-06-02 TMPA910CRA (a) Transmit interrupt The transmit interrupt is asserted when there are four or less valid entries in the transmit FIFO. The transmit interrupt is generated even when SSP operation is disabled (SSPxCR1<SSE> = 0). The initial transmit data can be written into the transmit FIFO by using this interrupt. (b) Receive interrupt The receive interrupt is asserted when there are four or more valid entries in the receive FIFO. The transmit and receive interrupt requests are generated and cleared dynamically by monitoring the number of valid entries in the transmit and receive FIFOs. No interrupt request clear register is available. TMPA910CRA- 455 2010-06-02 TMPA910CRA (c) Timeout interrupt The receive timeout interrupt is asserted when the receive FIFO is not empty and the SSP has remained idle for a fixed duration of 32-bit period (bit rate). This mechanism ensures that the user is aware that data is still present in the receive FIFO and requires servicing. The timeout interrupt is generated both in master and slave modes. When the timeout interrupt is generated, read all the data in the receive FIFO. Data can be transmitted/received without reading all the data in the receive FIFO provided that the receive FIFO has empty space for receiving the data to be transmitted. The timeout interrupt is cleared when a transfer is started. If a transfer is performed when the receive FIFO is full, the timeout interrupt is cleared and the overrun interrupt is generated. SP0CLK Transfering data Receive FIFO Empty flag (RNE) Internal counter enable Bit rate x 32 Receive time out interrupt enable (RTIM) Receive time out interrupt (RTINTR) (d) Receive overrun interrupt When the receive FIFO is already full and an additional (9th) data frame is received, the receive overrun interrupt is asserted immediately after the completion of the current transfer. Once the receive overrun error occurs, any subsequent data received (including the 9th data frame) is invalid and discarded. However, if the data in the receive FIFO is read while the 9th data frame is being received (before the receive overrun interrupt occurs), the 9th data frame is written into the receive FIFO as valid data. To perform proper transfer operation after the receive overrun error occurred, write 1 to the receive overrun interrupt clear register and then read all the data in the receive FIFO. Data can be transmitted/received without reading all the data in the receive FIFO provided that the receive FIFO has empty space for receiving the data to be transmitted. If the receive FIFO is not read (when it is not empty) for a fixed duration of 32-bit period (bit rate) after the receive overrun interrupt has been cleared, the timeout interrupt is generated. (e) Combined interrupt The individual masked sources of the above four interrupts are also combined into a single interrupt. The combined interrupt INTS [12] is asserted if any of the four interrupts is asserted. TMPA910CRA- 456 2010-06-02 TMPA910CRA 3.15.3 SPP Operation (1) Configuring the SSP The SSP communication protocol must be configured while the SSP is disabled. Select master or slave mode by setting the control register SSPOCR0 and SSP0CR1 under either of the following rotocols.. The communication rate need also be set by programming the prescale register SSP0CPSR and SSP0CR0<SCR>. This SSP supports the following frame formats: * SPI * SSI * Microwire (2) Enabling the SSP Transmission of data begins when SSP operation is enabled after transmit data has been written into the transmit FIFO or when transmit data is written into the transmit FIFO after SSP operation has been enabled. However, if the transmit FIFO has four entries or less when SSP operation is enabled, the transmit interrupt will be generated. It is possible to use this interrupt to write the initial transmit data. Note: When using the SPI slave mode without using the FSS pin, be sure to write 1 byte or more of data into the transmit FIFO before enabling SSP operation. If SSP operation is enabled while the transmit FIFO is empty, transfer data cannot be output properly. (3) Clock ratios The PCLK frequency setting must satisfy the following conditions: [Master mode] fSP0CLK (max): fPCLK / 2 fSP0CLK (min): fPCLK / (254 x 256) [Slave mode] fSP0CLK (max): fPCLK / 12 fSP0CLK (min): fPCLK / (254 x 256) (4) Frame format Each frame format is between 4 to 16 bits long depending on the size of data programmed, and is transmitted starting with the MSB. * Serial clock (SP0CLK) For SSI and Microwire frame formats, the serial clock (SP0CLK) is held Low while the SSP is idle. For SPI frame format, the serial clock (SP0CLK) is held inactive while the SSP is idle. SP0CLK is output at the specified bit rate only while data is being transmitted. TMPA910CRA- 457 2010-06-02 TMPA910CRA * Serial frame (SP0FSS) For SPI and Microwire frame formats, the serial frame (SP0FSS) pin is active Low, and is asserted during the entire transmission of the frame. For SSI frame format, the SP0FSS pin is asserted for one bit rate period prior to the transmission of each frame. For this frame format, output data is transmitted on the rising edge of SP0CLK, and input data is received on the falling edge. * Microwire frame format The Microwire format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the slave. During this transmission, no incoming data is received by the SSP. After the message has been sent, the slave decodes it and, after waiting one serial clock period after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. The details of each frame format are described below. 1) SSI frame format In this mode, SP0CLK and SP0FSS are forced Low and the transmit data line SP0DO is put in the Hi-Z state whenever the SSP is idle. When data is written into the transmit FIFO, the master pulses the SP0FSS line High for one SP0CLK period. The transmit data is transferred from the transmit FIFO to the transmit serial shift register. On the next rising edge of SP0CLK, the MSB of the 4 to 16-bit data frame is shifted onto the SP0DO pin. Likewise, the MSB of the received data is input to the SP0DI pin on the falling edge of SP0CLK. The received data is transferred from the serial shift register to the receive FIFO on the first rising edge of SP0CLK after the LSB has been latched. SSI frame format (single transfer) SP0CLK SP0FSS SP0DO SP0DI Hi-Z(Note1) Hi-Z(Note2) MSB LSB MSB LSB Hi-Z(Note1) Hi-Z(Note2) 4 to 16bit Note1) When transmission is disable , SP0DO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. TMPA910CRA- 458 2010-06-02 TMPA910CRA Note2) SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. SSI frame format (continuous transfer) SP0CLK SP0FSS MSB SP0DO/SP0DI LSB MSB 4 to16 bits Note1) When transmission is disable , SP0DO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. Note2) SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. TMPA910CRA- 459 2010-06-02 TMPA910CRA 2) SPI The SPI interface is a four-wire interface where the SP0FSS signal behaves as a slave select. The main feature of the SPI format is that the operation timing of SP0CLK is programmable through the <SPO> and <SPH> bits in the SSP0CR0 control register. SSP0CR0<SPO> SSP0CR0<SPO> specifies the SP0CLK level during idle periods. <SPO> = 1: SP0CLK is held High. <SPO> = 0: SP0CLK is held Low. SSP0CR0<SPH> SSP0CR0<SPH> selects the clock edge for latching data. SSP0CR0<SPH> = 0: Data is latched on the first clock edge. SSP0CR0<SPH> = 1: Data is latched on the second clock edge. SPI operation examples: SPI (single transfer, <SPO> = 0 & <SPH> = 0) SP0CLK SP0FSS SP0DI Hi-Z(Note1) SP0DO Hi-Z(Note2) Note1) MSB MSB LSB LSB Hi-Z(Note1) Hi-Z(Note2) When transmission is disable , SP0DO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. Note2) SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. TMPA910CRA- 460 2010-06-02 TMPA910CRA SPI (continuous transfer, <SPO> = 0 & <SPH> = 0) SP0CLK SP0FSS SP0DO LSB SP0DI LSB Hi-Z(Note2) MSB LSB MSB LSB MSB Hi-Z(Note2) MSB 4 to 16bit Note1) When transmission is disable , SP0DO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. Note2) SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. With this setting, during the idle period: * The SP0CLK signal is forcedly set to LOW. * SP0FSS is forcedly set to HIGH. * The transmit data line SP0DO is arbitrarily set to LOW. If the SSP is enabled and valid data exists in the transmit FIFO, the SP0FSS master signal driven by LOW notifies of the start of transmission. This enables the slave data in the SP0DI input line of the master. When a half of the SP0CLK period has passed, valid master data is transferred to the SP0DO pin. Both the master data and slave data are now set. When another half of SP0CLK has passed, the SP0CLK master clock pin becomes HIGH. After that, the data is captured at the rising edge of the SP0CLK signal and transmitted at its falling edge. In the single word transfer, the SP0FSS line will return to the idle HIGH state when all the bits of that data word have been transferred, and then one cycle of SP0CLK has passed after the last bit was captured. However, for continuous transfer, the SP0FSS signal must be pulsed at HIGH between individual data word transfers. This is because change is not enabled when the slave selection pin freezes data in its peripheral register and the <SPH> bit is logical 0. Therefore, to enable writing of serial peripheral data, the master device must drive the SP0FSS pin of the slave device between individual data transfers. When the continuous transfer is complete, the SP0FSS pin will return to the idle state when one cycle of SP0CLK has passed after the last bit is captured. TMPA910CRA- 461 2010-06-02 TMPA910CRA 3) Microwire frame format Microwire frame format (single transfer) SP0CLK SP0FSS SP0DO LSB MSB Hi-Z(Note1) Hi-Z(Note1) 8bit SP0DI Hi-Z(Note2) LSB MSB Hi-Z(Note2) 4 to 16bit Note1) When transmission is disable , SP0DO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. Note2) SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. Though the Microwire format is similar to the SPI format, it uses the master/slave message transmission method for half-duplex communications. Each serial transmission is started by an 8-bit control word, which is sent to the off-chip slave device. During this transmission, the SSP does not receive input data. After the message has been transmitted, the off-chip slave decodes it, and after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. With this configuration, during the idle period: * The SP0CLK signal is forcedly set to LOW. * SP0FSS is forcedly set to HIGH. * The transmit data line SP0DO is set to LOW. A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SP0FSS causes the value stored in the bottom entry of the transmit FIFO to be transferred to the serial shift register for the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SP0DO pin. SP0FSS remains LOW and the SP0D1 pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SP0CLK. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSP. Each bit is driven onto SP0DI line on the falling edge of SP0CLK. The SSP in turn latches each bit on the rising edge of SP0CLK. At the end of the frame, for single transfers, the SP0FSS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note) The off-chip slave device can tristate the receive line either on the falling edge of SP0CLK after the LSB has been latched by the receive shifter, or when the SP0FSS pin goes HIGH. TMPA910CRA- 462 2010-06-02 TMPA910CRA Microwire frame format (continuous transfer) SP0CLK SP0FSS SP0DO LSB LSB MSB Hi-Z(Note1) Hi-Z(Note1) 8bit SP0DI Hi-Z(Note2) LSB MSB Hi-Z(Note2) MSB 4 to 16bit Note1) When transmission is disable , SP0DO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. Note2) SP0DI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SP0FSS line is continuously asserted (held LOW) and transmission of data occurs back to back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SP0CLK, after the LSB of the frame has been latched into the SSP. Note) [Example of connection] The SSP does not support dynamic switching between the master and slave in the system. Each sample SSP is configured and connected as either a master or slave. TMPA910CRA- 463 2010-06-02 TMPA910CRA 3.15.4 Description of Registers The following lists the SFRs: * Base address = 0xF200_2000 SSP0 Register Address Name (base +) Description SSP0CR0 0x0000 SSP0 Control register 0 SSP0CR1 0x0004 SSP0 Control register 1 SSP0DR 0x0008 SSP0 Data register SSP0SR 0x000C SSP0 Status register SSP0CPSR 0x0010 SSP0 Clock prescale register SSP0IMSC 0x0014 SSP0 Interrupt mask set and clear register SSP0RIS 0x0018 SSP0 Raw interrupt status register SSP0MIS 0x001C SSP0 Masked interrupt status register SSP0ICR 0x0020 SSP0 Interrupt clear register - 0x0024 Reserved - 0x0028 to 0xFFC Reserved * SSP1 Base address = 0xF200_3000 Register Address Name (base +) Description SSP1CR0 0x0000 SSP1 Control register 0 SSP1CR1 0x0004 SSP1 Control register 1 SSP1DR 0x0008 SSP1 Data register SSP1SR 0x000C SSP1 Status register SSP1CPSR 0x0010 SSP1 Clock prescale register SSP1IMSC 0x0014 SSP1 Interrupt mask set and clear register SSP1RIS 0x0018 SSP1 Raw interrupt status register SSP1MIS 0x001C SSP1 Masked interrupt status register SSP1ICR 0x0020 SSP1 Interrupt clear register - 0x0024 Reserved - 0x0028 to 0xFFC Reserved TMPA910CRA- 464 2010-06-02 TMPA910CRA 1. SSP0CR0 (SSP0 Control register 0) Address = (0xF200_2000) + (0x0000) Bit Bit Reset Type Symbol Description Value [31:16] - - Undefined [15:8] SCR R/W 0y0 Read as undefined. Write as zero. Parameter for setting the serial clock rate: 0x00 to 0xFF (See [Description] below.) [7] SPH R/W 0y0 SPCLK phase 0y0: Data is latched on the first clock edge 0y1: Data is latched on the second clock edge (Applicable to SPI frame format only. See "2) SPI".) [6] SPO R/W 0y0 SPCLK polarity 0y0: SP0CLK is held Low 0y1: SP0CLK is held High (Applicable to SPI frame format only. See "2) SPI".) [5:4] FRF R/W 0y00 Frame format: 0y00: SPI frame format 0y01: SSI frame format 0y10: Microwire frame format 0y11: Reserved, undefined operation [3:0] DSS R/W 0y0000 Data size select: 0y0000: Reserved. undefined operation 0y0001: Reserved. undefined operation 0y0010: Reserved, undefined operation 0y0011: 4-bit data 0y0100: 5-bit data 0y0101: 6-bit data 0y0110: 7-bit data 0y0111: 8-bit data 0y1000: 9-bit data 0y1001: 10-bit data 0y1010: 11-bit data 0y1011: 12-bit data 0y1100: 13-bit data 0y1101: 14-bit data 0y1110: 15-bit data 0y1111: 16-bit data TMPA910CRA- 465 2010-06-02 TMPA910CRA 2. SSP1CR0 (SSP1 Control register 0) Address = (0xF200_3000) + (0x0000) Bit Bit Type Reset Symbol Description Value [31:16] - - Undefined [15:8] SCR R/W 0y0 Read as undefined. Write as zero. Parameter for setting the serial clock rate: 0x00 to 0xFF [7] SPH R/W 0y0 SPCLK phase (Applicable to SPI frame format only. See "2) SPI".) [6] SPO R/W 0y0 SPCLK polarity (Applicable to SPI frame format only. See "2) SPI". [5:4] FRF R/W 0y00 Frame format: 0y00: SPI frame format 0y01: SSI frame format 0y10: Microwire frame format 0y11: Reserved, undefined operation [3:0] DSS R/W 0y0000 Data size select: 0y0000: Reserved, undefined operation 0y0001: Reserved, undefined operation 0y0010: Reserved, undefined operation 0y0011: 4-bit data 0y0100: 5-bit data 0y0101: 6-bit data 0y0110: 7-bit data 0y0111: 8-bit data 0y1000: 9-bit data 0y1001: 10-bit data 0y1010: 11-bit data 0y1011: 12-bit data 0y1100: 13-bit data 0y1101: 14-bit data 0y1110: 15-bit data 0y1111: 16-bit data [Description] a. <SCR> The <SCR> value is used to generate the transmit and receive bit rate of the SSP. The bit rate is: Bit rate = fPCLK / (<CPSDVSR> x (1 + <SCR>)) Please refer to SSPxCPSR register about <CPSDVSR>. TMPA910CRA- 466 2010-06-02 TMPA910CRA 3. SSP0CR1 (SSP0 Control register 1) Address = (0xF200_2000) + (0x0004) Bit Bit Reset Type Symbol Description Value [31:4] - - Undefined [3] SOD R/W 0y0 Read as undefined. Write as zero. Slave mode SP0DO output disable: 0y0: Enable 0y1: Disable [2] MS R/W 0y0 Master/slave mode select: 0y0: The device is a master. 0y1: The device is a slave. [1] SSE R/W 0y0 SSP enable: 0y0: Disable 0y1: Enable [0] Reserved R/W 0y0 Write as zero. 4. SSP1CR1 (SSP1 control register 1) Address = (0xF200_3000) + (0x0004) Bit Bit Reset Type Symbol Description Value [31:4] - - Undefined [3] SOD R/W 0y0 Read as undefined. Write as zero. Slave mode SP0DO output disable: 0y0: Enable 0y1: Disable [2] MS R/W 0y0 Master/slave mode select: 0y0: The device is a master. 0y1: The device is a slave. [1] SSE R/W 0y0 SSP enable: 0y0: Disable 0y1: Enable [0] Reserved R/W 0y0 Write as zero. [Description] a. <SOD> Slave mode output disable. This bit is relevant only in the slave mode (<MS> = 0y1). b. <MS> Master/slave mode select. When transmit mode with Slave mode, must be set it in the following order. 1. Set to Slave mode (<MS> = 1) 2. Set transmit data to FIFO 3. Set SSP to enable (<SSE> = 1) TMPA910CRA- 467 2010-06-02 TMPA910CRA 5. SSP0DR (SSP0 Data register) Address = (0xF200_2000) + (0x0008) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined [15:0] DATA R/W 0x0000 Read as undefined. Write as zero. Transmit/receive FIFO data: 0x00 to 0xFF 6. SSP1DR (SSP1 Data register) Address = (0xF200_3000) + (0x0008) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined [15:0] DATA R/W 0x0000 Read as undefined. Write as zero. Transmit/receive FIFO data: 0x00 to 0xFF [Description] a. <DATA> Read: Receive FIFO Write: Transmit FIFO You must right-justify data when the SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies. TMPA910CRA- 468 2010-06-02 TMPA910CRA 7. SSP0SR (SSP0 Status register) Address = (0xF200_2000) + (0x000C) Bit Bit Reset Type Symbol Description Value [31:5] - - Undefined Read as undefined. [4] BSY RO 0y0 Busy flag: 0y0: IDLE 0y1: Busy [3] RFF RO 0y0 Receive FIFO full flag: 0y0: Receive FIFO is not full. 0y1: Receive FIFO is full. [2] RNE RO 0y0 Receive FIFO empty flag: 0y0: Receive FIFO is empty. 0y1: Receive FIFO is not empty. [1] TNF RO 0y1 Transmit FIFO full flag: 0y0: Transmit FIFO is full. 0y1: Transmit FIFO is not full. [0] TFE RO 0y1 Transmit FIFO empty flag: 0y0: Transmit FIFO is not empty. 0y1: Transmit FIFO is empty. 8. SSP1SR (SSP1 Status register) Address = (0xF200_3000) + (0x000C) Bit Bit Reset Type Symbol Description Value [31:5] - - Undefined Read as undefined. [4] BSY RO 0y0 Busy flag: 0y0: IDLE 0y1: Busy [3] RFF RO 0y0 Receive FIFO full flag: 0y0: Receive FIFO is not full. 0y1: Receive FIFO is full. [2] RNE RO 0y0 Receive FIFO empty flag: 0y0: Receive FIFO is empty. 0y1: Receive FIFO is not empty. [1] TNF RO 0y1 Transmit FIFO full flag: 0y0: Transmit FIFO is full. 0y1: Transmit FIFO is not full. [0] TFE RO 0y1 Transmit FIFO empty flag: 0y0: Transmit FIFO is not empty. 0y1: Transmit FIFO is empty. [Description] a. <BSY> This bit indicates, when set to 1 (BSY = 1), that a frame is currently being transmitted or received or the transmit FIFO is not empty. TMPA910CRA- 469 2010-06-02 TMPA910CRA 9. SSP0CPSR (SSP0 Clock prescale register) Address = (0xF200_2000) + (0x0010) Bit Bit Type Symbol Reset Value Description [31:8] - - Undefined Read as undefined. Write as zero. [7:0] CPSDVSR R/W 0x0000 Clock prescale divisor: Must be an even number from 2 to 254. 10. SSP1CPSR (SSP1 Clock prescale register) Address = (0xF200_3000) + (0x0010) Bit Bit Type Symbol Reset Value Description [31:8] - - Undefined Read as undefined. Write as zero. [7:0] CPSDVSR R/W 0x0000 Clock prescale divisor: Must be an even number from 2 to 254. [Description] a. <CPSDVSR> Clock prescale divisor. Must be an even number from 2 to 254, depending on the frequency of PCLK. The least significant bit always returns 0 on reads. TMPA910CRA- 470 2010-06-02 TMPA910CRA 11. SSP0IMSC (SSP0 Interrupt mask set and clear register) Address = (0xF200_2000) + (0x0014) Bit Bit Reset Type Symbol Description Value [31:4] - - Undefined Read as undefined. Write as zero. [3] TXIM R/W 0y0 Transmit FIFO interrupt enable: 0y0: Disable 0y1: Enable [2] RXIM R/W 0y0 Receive FIFO interrupt enable: 0y0: Disable 0y1: Enable [1] RTIM R/W 0y0 Receive timeout interrupt enable: 0y0: Disable 0y1: Enable [0] RORIM R/W 0y0 Receive overrun interrupt enable: 0y0: Disable 0y1: Enable [Description] a. <TXIM> Enables or disables interrupts that are generated when TxFIFO is half empty or less. b. <RXIM> Enables or disables interrupts that are generated when RxFIFO is half full or less. c. <RTIM> Enables or disables interrupts that are generated when the data in RxFIFO is not read out before the timeout period expires. d. <RORIM> Enables or disables interrupts that are generated when data is written to RxFIFO while it is full. TMPA910CRA- 471 2010-06-02 TMPA910CRA 12. SSP1IMSC (SSP1 Interrupt mask set and clear register) Address = (0xF200_3000) + (0x0014) Bit Bit Reset Type Symbol Description Value [31:4] - - Undefined Read as undefined. Write as zero. [3] TXIM R/W 0y0 Transmit FIFO interrupt enable: 0y0: Disable 0y1: Enable [2] RXIM R/W 0y0 Receive FIFO interrupt enable: 0y0: Disable 0y1: Enable [1] RTIM R/W 0y0 Receive timeout interrupt enable: 0y0: Disable 0y1: Enable [0] RORIM R/W 0y0 Receive overrun interrupt enable: 0y0: Disable 0y1: Enable [Description] a. <TXIM> Enables or disables interrupts that are generated when TxFIFO is half empty or less. b. <RXIM> Enables or disables interrupts that are generated when RxFIFO is half full or less. c. <RTIM> Enables or disables interrupts that are generated when the data in RxFIFO is not read out before the timeout period expires. d. <RORIM> Enables or disables interrupts that are generated when data is written to RxFIFO while it is full. TMPA910CRA- 472 2010-06-02 TMPA910CRA 13. SSP0RIS (SSP0 Raw interrupt status register) Address = (0xF200_2000) + (0x0018) Bit Bit Reset Type Symbol Description Value [31:4] - - Undefined Read as undefined. [3] TXRIS RO 0y0 Transmit interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested [2] RXRIS RO 0y0 Receive interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested [1] RTRIS RO 0y0 Receive timeout interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested [0] RORRIS RO 0y0 Receive overrun interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested 14. SSP1RIS (SSP1 Raw interrupt status register) Address = (0xF200_3000) + (0x0018) Bit Bit Type Symbol Reset Description Value [31:4] - - Undefined Read as undefined. [3] TXRIS RO 0y0 Transmit interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested [2] RXRIS RO 0y0 Receive interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested [1] RTRIS RO 0y0 Receive timeout interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested [0] RORRIS RO 0y0 Receive overrun interrupt status prior to enable gate: 0y0: No interrupt 0y1: Interrupt requested TMPA910CRA- 473 2010-06-02 TMPA910CRA 15. SSP0MIS (SSP0 Masked interrupt status register) Address = (0xF200_2000) + (0x001C) Bit Bit Type Symbol Reset Description Value [31:4] - - Undefined Read as undefined. [3] TXMIS RO 0y0 Transmit interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested [2] RXMIS RO 0y0 Receive interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested [1] RTMIS RO 0y0 Receive timeout interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested [0] RORMIS RO 0y0 Receive overrun interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested TMPA910CRA- 474 2010-06-02 TMPA910CRA 16. SSP1MIS (SSP1 Masked interrupt status register) Address = (0xF200_3000) + (0x001C) Bit Bit Type Symbol Reset Description Value [31:4] - - Undefined Read as undefined. [3] TXMIS RO 0y0 Transmit interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested [2] RXMIS RO 0y0 Receive interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested [1] RTMIS RO 0y0 Receive timeout interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested [0] RORMIS RO 0y0 Receive overrun interrupt status after enable gate: 0y0: No interrupt 0y1: Interrupt requested TMPA910CRA- 475 2010-06-02 TMPA910CRA 17. SSP0ICR (SSP0 Interrupt clear register) Address = (0xF200_2000) + (0x0020) Bit Bit Type Symbol Reset Description Value [31:2] - - Undefined Read as undefined. Write as zero. [1] RTIC WO Undefined Receive timeout interrupt flag clear: 0y0: Invalid 0y1: Clear [0] RORIC WO Undefined Receive overrun interrupt flag clear: 0y0: Invalid 0y1: Clear 18. SSP1ICR (SSP1 Interrupt clear register) Address = (0xF200_3000) + (0x0020) Bit Bit Type Symbol Reset Description Value [31:2] - - Undefined Read as undefined. Write as zero. [1] RTIC WO Undefined Receive timeout interrupt flag clear: 0y0: Invalid 0y1: Clear [0] RORIC WO Undefined Receive overrun interrupt flag clear: 0y0: Invalid 0y1: Clear TMPA910CRA- 476 2010-06-02 TMPA910CRA 3.16 USB Device Controller 3.16.1 System Overview 1) Conforming to Universal Serial Bus Specification Rev. 2.0 2) Supports both High-Speed and Full-Speed (Low-Speed is not supported). 3) Supports Chirp. 4) USB protocol processing 5) Detects SOF/USB_RESET/SUSPEND/RESUME. 6) Generates and checks packet IDs. 7) Generates and checks data synchronization bits (DATA0/DATA1/DATA2/MDATA). 8) Checks CRC5, generates and checks CRC16. 9) Supports PING. 10) Supports 4 transfer modes (Control/Interrupt/Bulk/Isochronous). 11) Supports 4 endpoints: Endpoint 0: Control 64 bytes x 1 FIFO Endpoint 1: Bulk (IN) 512 bytes x 2 FIFOs Endpoint 2: Bulk (OUT) 512 bytes x 2 FIFOs Endpoint 3: Interrupt (IN) 64 bytes x 1 FIFO 12) Supports Dual Packet Mode (except for Endpoint 0). 13) Interrupt source signal to Interrupt controller: INTS[21] TMPA910CRA- 477 2010-06-02 TMPA910CRA 3.16.1.1 System Structure The USB device controller consists of the core part called UDC2 and the bus bridge part called UDC2AB which enables connection with the AHB bus. In this section, the circuit function is outlined first. Then, section 3.16. 2 describes the configuration of the UDC2AB bus bridge, and section 3.16.3 describes the configuration of UDC2. AHB UDC2AB PVCI Ctrl EP0 2.0 PHY IFM USB SIEC USB AHB Slave EPINT EPRX AHB Slave I/F DMAC_W0 DMAC_R0 AHB Master UDC2 AHB Master I/F EPTX Figure 3.16.1 Block diagram of the USB device controller TMPA910CRA- 478 2010-06-02 TMPA910CRA 3.16.1.2 Example of Connection USB Host USB Device USB Host TMPA910CRA USB USB Connector Connector AVDD3Tx, AVDD3C GND X1 AVSS3Tx, AVSS3C INTx (rise detection) VBUS R6 X2 24 MHz R7 USB Cable X1USB 24 MHz DP R8 DM R9 REXT R10 VSENS The above diagram shows the connections required for using the USB controller in the TMPA910CRA. (1) Pulling up of the DP pin The USB specification requires that the DP pin be pulled up for Full-Speed communication. An internal pull-up resistor is provided, and no external circuit is required. (2) Insertion of series resistance for the DP and DM pins The USB specification requires that series resistance be inserted for each of the DP and DM pins. Internal series resistance is provided for each of these pins, and no external circuit is required. (3) Detection of connector connection How to detect connector connection with VBUS (5 V) is explained as an example. As shown in the connection example above, R6 and R7 for dividing resistance should be connected to the VBUS pin in such a way as to assert the interrupt pin High (3.3 V) when power is connected. By detecting this interrupt by software, connector connection can be detected. Note: If the waveform rises slowly, it is recommended to insert appropriate buffering for waveform shaping. Recommended values: R6 = 60 k, R7 = 100 k (VBUS consumption current in suspended state < 500 A) (4) 24-MHz clock input The USB device controller requires a 24-MHz clock. This clock input can be implemented in two ways. One is to connect a 24-MHz resonator to the X1 and X2 pins and the other is to input a 24-MHz clock from the X1USB pin. SYSCR0<USBCLKSEL> is used to select either of these methods. In whichever case, the clock precision must be 100 ppm or less. TMPA910CRA- 479 2010-06-02 TMPA910CRA (5) Pull-down resistors on the USB host The USB specification requires that the DP and DM pins be pulled down at the USB host end. Recommended values: R8 = 15 k, R9 = 15 k (6) Resistor for USB_PHY It is necessary to connect a resistor between the REXT pin and the VSENS pin. R10 should be 12 k (with an error within 1.0%). Note: The above connections, resistor values and other information are provided as examples and their operations are not guaranteed. Please be sure to check the latest USB specification and to perform operation checks on the actual set. TMPA910CRA- 480 2010-06-02 TMPA910CRA 3.16.2 UDC2AB AHB Bus Bridge UDC2AB (UDC2 AHB Bridge) is the bridge circuit between Toshiba USB-Spec 2.0 Device Controller (hereinafter "UDC2") and AHB. UDC2AB has the DMA controller that supports the AHB master transfer and controls transfer between the specified address on AHB and the Endpoint-FIFO (Endpoint I/F) inside UDC2. AHB UDC2 UDC2AB EP0 2.0 PHY IFM USB SIEC USB AHB Slave DMAC_W0 EPINT EPRX AHB Slave I/F DMAC_R0 AHB Master PVCI Ctrl AHB Master I/F EPTX Figure 3.16.2 UDC2AB block diagram 3.16.2.1 Functions and Features UDC2AB has the following functions and features: (1) Connection with UDC2 There is no specific restriction on the endpoint configuration for the UDC2 to be connected. However, the DMA controller in UDC2AB (AHB master function) can be connected with only one Rx-EP and one Tx-EP. Accesses to other endpoints (including EP0) should be made through PVCI I/F of UDC2 using the AHB slave function. Please note the EPx_FIFO register of a UDC2 endpoint in master transfer with the DMA controller cannot be accessed through PVCI I/F. If the maximum packet size of the endpoint to be connected with the AHB master read function will be an odd number, there will be some restrictions on the usage. See section 3.16.2.9 "(3)Setting the maximum packet size in Master Read transfers" for more information. (2) AHB functions AHB Master and AHB Slave functions are provided. TMPA910CRA- 481 2010-06-02 TMPA910CRA (a) AHB Master function Specifications of the AHB Master function: * Has two DMA channels; one each is allocated to the Rx-EP and the Tx-EP. * Single and Burst (INCR/INCR8) transactions are supported. * Split transaction is not supported. * Little Endian is supported. * Protection Control is not supported. * Early Burst Termination is supported. * Address width and data width are both 32 bits. * Transaction sizes in bytes or words are supported. The image of Endian conversion is as shown below. Little Endian WORD Access HWDATA[31:0]/HRDATA[31:0] Data 0 +3 +2 +1 Address 44 33 22 11 BYTE Access HWDATA[31:0]/HRDATA[31:0] Data +3 +2 +1 0 Address 11 22 33 44 Figure 3.16.3 Image of Endian conversion in AHB Master function TMPA910CRA- 482 2010-06-02 TMPA910CRA (b) AHB Slave function Specifications of the AHB Slave function: * Used for accessing the internal register. * Little Endian is supported. * Only single transactions are supported. * Address width and data width are both 32 bits. * Transaction sizes in bytes or words are supported. The image of Endian conversion is as shown below. Little Endian WORD Access HWDATA[31:0]/HRDATA[31:0] Data 0 Address 44 33 22 11 BYTE Access HWDATA[31:0]/HRDATA[31:0] Data +3 +2 +1 0 Address 11 22 33 44 Figure 3.16.4 Image of Endian conversion in AHB Slave function TMPA910CRA- 483 2010-06-02 TMPA910CRA 3.16.2.2 Overall Composition UDC2AB mainly consists of the AHB Slave function that controls the access to the UDC2AB internal registers and UDC2 registers and the AHB Master function that controls the DMA access to the UDC2 Endpoint I/F. The AHB Master function has two built-in channels; Master Read Channel (AHB to UDC2) and Master Write Channel (UDC2 to AHB), which enable DMA transfer between the Endpoint I/F of Rx-EP and Tx-EP of UDC2. Each channel has two built-in 8-word buffers (four in total). 3.16.2.3 Clock Domain CLK_U: 30 MHz (to be supplied by USB 2.0 PHY) CLK_H: HCLK TMPA910CRA- 484 2010-06-02 TMPA910CRA 3.16.2.4 Terms and Presentation Assert : Indicates the signal is active. Deassert : Indicates the signal is inactive. Word : 32 bits Byte : 8 bits UDC2 : Indicates the USB2.0 device controller to be connected to UDC2AB. UDC2AB : This IP: Abbreviation of UDC2-AHB-Bridge Endpoint : FIFO held by UDC2 for communication with the USB host. Abbreviated as "EP". Rx-EP : Receive endpoint. For the OUT transfer of USB transfer (USB host to USB device). Tx-EP : Transmit endpoint. For the IN transfer of USB transfer (USB device to USB host). Endpoint I/F : DMA interface dedicated to the endpoints held by UDC2. PVCI I/F : Common interface held by UDC2. Used for accessing the internal registers of UDC2 Master transfer : Indicates that UDC2AB acquires the bus right to make transfer. Target device : Indicates the device (such as memories) to be accessed by UDC2AB with master transfer. Master Write transfer : Indicates the transfer with Rx-EP made by UDC2AB. Master Read transfer : Indicates the master transfer with Tx-EP made by UDC2AB. Slave transfer : Indicates the transfer made by other devices than UDC2AB targeted at UDC2AB. USB_RESET : Bus reset sent from the USB host. "Reset Signaling" in the USB specification. NULL packet : 0-length data to be transferred on USB. PHY : USB 2.0 PHY Interrupt : Indicates the INTS [21] output signal. Descriptions like "Assert xx interruption" in this document are based on the assumption that the relevant bit of the Interrupt Enable resistor is enabled. See section 3.16.2.7 "Interrupt Signal (INTS [21])" for more information. TMPA910CRA- 485 2010-06-02 TMPA910CRA 3.16.2.5 Registers The register map of UDC2AB consists of registers for setting UDC2AB and those for setting UDC2. When the registers for setting UDC2 are accessed, UDC2AB automatically accesses UDC2 via PVCI I/F. Each register has the width of 32 bits. (1) Register map The register map of UDC2AB is shown below. Table 3.16.1 UDC2AB/UDC2 register map (1/2) Base address = 0xF440_0000 UDC2AB Bridge Register Name Address (base +) Description UDINTSTS 0x0000 Interrupt Status Register UDINTENB 0x0004 Interrupt Enable Register UDMWTOUT 0x0008 Master Write Timeout Register UDC2STSET 0x000C UDC2 Setting Register UDMSTSET 0x0010 DMAC Setting Register DMACRDREQ 0x0014 DMAC Read Request Register DMACRDVL 0x0018 DMAC Read Value Register UDC2RDREQ 0x001C UDC2 Read Request Register UDC2RDVL 0x0020 Reserved 0x0024 to 0x0038 ARBTSET 0x003C Arbiter Setting Register UDMWSADR 0x0040 Master Write Start Address Register UDMWEADR 0x0044 UDMWCADR 0x0048 UDMWAHBADR 0x004C Master Write AHB Address Register UDMRSADR 0x0050 Master Read Start Address Register UDMREADR 0x0054 UDMRCADR 0x0058 UDC2 Read Value Register *4) Master Write End Address Register *1) Master Write Current Address Register Master Read End Address Register *1) Master Read Current Address Register UDMRAHBADR 0x005C Reserved 0x0060 to 0x007C Master Read AHB Address Register UDPWCTL 0x0080 Power Detect Control Register UDMSTSTS 0x0084 Master Status Register UDTOUTCNT 0x0088 Reserved 0x008C to 0x1FC *1) Timeout Count Register *4) TMPA910CRA- 486 2010-06-02 TMPA910CRA UDC2AB/UDC2 register map (2/2) Base address = 0xF440_0000 UDC2 *2), *3) Register Name Address (base +) Description UD2ADR 0x0200 UDC2 Address-State Register UD2FRM 0x0204 UDC2 Frame Register UD2TMD 0x0208 UDC2 USB-Testmode Register UD2CMD 0x020C UDC2 Command Register UD2BRQ 0x0210 UDC2 bRequest-bmRequestType Register UD2WVL 0x0214 UDC2 wValue Register UD2WIDX 0x0218 UDC2 wIndex Register UD2WLGTH 0x021C UDC2 wLength Register UD2INT 0x0220 UDC2 INT Register UD2INTEP 0x0224 UDC2 INT_EP Register UD2INTEPMSK 0x0228 UDC2 INT_EP_MASK Register UD2INTRX0 0x022C UDC2 INT_RX_DATA0 Register UD2EP0MSZ 0x0230 UDC2 EP0_MaxPacketSize Register UD2EP0STS 0x0234 UDC2 EP0_Status Register UD2EP0DSZ 0x0238 UDC2 EP0_Datasize Register UD2EP0FIFO 0x023C UDC2 EP0_FIFO Register UD2EP1MSZ 0x0240 UDC2 EP1_MaxPacketSize Register UD2EP1STS 0x0244 UDC2 EP1_Status Register UD2EP1DSZ 0x0248 UDC2 EP1_Datasize Register UD2EP1FIFO 0x024C UDC2 EP1_FIFO Register UD2EP2MSZ 0x0250 UDC2 EP2_MaxPacketSize Register UD2EP2STS 0x0254 UDC2 EP2_Status Register UD2EP2DSZ 0x0258 UDC2 EP2_Datasize Register UD2EP2FIFO 0x025C UDC2 EP2_FIFO Register UD2EP3MSZ 0x0260 UDC2 EP3_MaxPacketSize Register UD2EP3STS 0x0264 UDC2 EP3_Status Register UD2EP3DSZ 0x0268 UDC2 EP3_Datasize Register UD2EP3FIFO 0x026C UDC2 EP3_FIFO Register Reserved 0x0270 to 0x032C UD2INTNAK 0x0330 UDC2 INT_NAK Register UD2INTNAKMSK 0x0334 UDC2 INT_NAK_MASK Register Reserved 0x0338 to 0x03FC *1) Be sure to make Read accesses via DMAC Read Request Register. *2) Be sure to make Read accesses via UDC2 Read Request Register. *3)Though the registers of UDC2 are assigned to +0x200 to +0x3FC, no access should be made to the registers of endpoints not supported in the UDC2 to be connected or to any "Reserved" registers. *4) Those shown as "Reserved" and in addresses of 0x400 to 0xFFF above are prohibited to aceess. Read/Write is prohibited to those "Reserved" areas. TMPA910CRA- 487 2010-06-02 TMPA910CRA (2) Register descriptions The following subsections describe the registers in UDC2AB in detail. The descriptions of each bit have the following meanings: (Example) Address = (0xF440_0000) + (0xxxxx) Bit Bit Type Symbol (Note 1) (Note 2) Reset Value Description (Note 3) [31:30] - - Undefined [29] mw_rerror_en R/W 0y0, (-) [28] power_detect_en R/W 0y0, (-) [27:26] - - Undefined [25] dmac_reg_rd_en R/W 0y0, (-) [24] udc2_reg_rd_en R/W 0y0, (-) Read as undefined. Write as zero. Read as undefined. Write as zero. Note 1: Bit symbol Name of each bit. Those shown as "-" are reserved bits which cannot be written. 0 will be returned when read. Note 2: Register properties RO : Read only. Write is ignored. WO : Write only. 0 will be returned when read. R/W : Read/Write R/W1C : Read/Write 1 Clear. These bits can be both read and written. R/W1S : Read/Write 1 Set. These bits can be both read and written. When 1 is written, the corresponding bit is cleared. Writing 0 is invalid. When 1 is written, the corresponding bit is set. Writing 0 is invalid. Note 3: Reset value Initial values for the bit after resetting (1 or 0). Initial values for Hardware Reset and Software Reset (Power Detect Control <pw_resetb>) are identical. Those bits which will not be reset by Software Reset is shown with (-) TMPA910CRA- 488 2010-06-02 TMPA910CRA 1. UDINTSTS (Interrupt Status register) This register sets 1 to each corresponding bit when an interrupt source arises. The status can be cleared by writing 1 into bits [29:8]. Bits [7:0] corresponds to the output pins of UDC2 and read-only. It can be cleared by writing 1 into the appropriate bit of INT register in UDC2. Note: For the operation of interrupt signals, refer to "3.16.2.7 Interrupt Signal (INTS[21])". Address = (0xF440_0000) + (0x0000) Bit Bit Symbol Type Reset Description Value [31:30] - - Undefined Read as undefined. Write as zero. [29] int_mw_rerror R/W1C 0y0 Master Write Endpoint Read error 0y0: Not detected 0y1: Endpoint read error occurred in Master Write [28:26] - - Undefined Read as undefined. Write as zero. [25] int_dmac_reg_rd R/W1C 0y0 DMAC register access complete 0y0: Not detected 0y1: Register read completed [24] int_udc2_reg_rd R/W1C 0y0 UDC2 register access complete 0y0: Not detected 0y1: Register read/write completed [23] int_mr_ahberr R/W1C 0y0 Master Read transfer error status 0y0: Not detected 0y1: AHB error occurred [22] int_mr_ep_dset R/W1C 0y0 Master Read endpoint data set status 0y0: FIFO is not writable 0y1: FIFO is writable [21] int_mr_end_add R/W1C 0y0 Master Read transfer end status 0y0: Not detected 0y1: Master Read transfer finished [20] int_mw_ahberr R/W1C 0y0 Master Write transfer error status 0y0: Not detected 0y1: AHB error occurred [19] int_mw_timeout R/W1C 0y0 Master Write transfer time-out status 0y0: Not detected 0y1: Master Write transfer timed out [18] int_mw_end_add R/W1C 0y0 Master Write transfer end status 0y0: Not detected 0y1: Master Write transfer finished [17] int_mw_set_add R/W1C 0y0 Master Write transfer address request status 0y0: Not detected 0y1: Master Write transfer address request [16:11] [10] - - Undefined int_usb_reset_end R/W1C 0y0 Read as undefined. Write as zero. USB_RESET END 0y0: UDC2 has not deasserted the usb_reset signal after this bit was cleared. 0y1: Indicates UDC2 has deasserted the usb_reset signal. [9] int_usb_reset R/W1C 0y0 USB_RESET 0y0: UDC2 has not asserted the usb_reset signal after this bit was cleared. 0y1: Indicates UDC2 has asserted the usb_reset signal. [8] int_suspend_resume R/W1C 0y0 Suspend/resume interrupt status 0y0: Status has not changed 0y1: Status has changed TMPA910CRA- 489 2010-06-02 TMPA910CRA Bit Bit Type Symbol Reset Description Value [7] int_nak RO 0y0 UDC2_INT_NAK register [6] int_ep RO 0y0 UDC2 INT_EP register [5] int_ep0 RO 0y0 UDC2 INT_EP0 register [4] int_sof RO 0y0 UDC2 INT_SOF register [3] int_rx_zero RO 0y0 UDC2 INT_RXDATA0 register [2] int_status RO 0y0 UDC2 INT_STATUS register [1] int_status_nak RO 0y0 UDC2 INT_STATUS_NAK register [0] int_setup RO 0y0 UDC2 INT_STATUS register [Description] a. <int_mw_rerror> Will be set to 1 when the access to the endpoint has started Master Write transfer during the setting of common bus access (bus_sel bit of EPx_Status register is 0). 0y0: Not detected 0y1: Endpoint read error occurred in Master Write b. <int_dmac_reg_rd> Will be set to 1 when the register access executed by the setting of DMAC Read Request register is completed and the value read to DMAC Read Value register is set. 0y0: Not detected 0y1: Register read completed c. <int_udc2_reg_rd> Will be set to 1 when the UDC2 access executed by the setting of UDC2 Read Request register is completed and the value read to UDC2 Read Value register is set. Also set to 1 when Write access to the internal register of UDC2 is completed. 0y0: Not detected 0y1: Register read/write completed d. <int_mr_ahberr> This status will be set to 1 when the AHB error has occurred during the operation of Master Read transfer. After this interrupt has occurred, the Master Read transfer block needs to be reset by the mr_reset bit of DMAC Setting register. 0y0: Not detected 0y1: AHB error occurred TMPA910CRA- 490 2010-06-02 TMPA910CRA e. <int_mr_ep_dset > Will be set to 1 when the FIFO of EP for UDC2 Tx to be used for Master Read transfer becomes writable (not full). 0y0: FIFO is not writable 0y1: FIFO is writable f. <int_mr_end_add> Will be set to 1 when the Master Read transfer has finished. 0y0: Not detected 0y1: Master Read transfer finished g. <int_mw_ahberr> This status will be set to 1 when the AHB error has occurred during the operation of Master Write transfer. After this interrupt has occurred, the Master Write transfer block needs to be reset by the mw_reset bit of DMAC Setting register. 0y0: Not detected 0y1: AHB error occurred h. <int_mw_timeout> This status will be set to 1 when time-out has occurred during the operation of Master Write transfer. 0y0: Not detected 0y1: Master Write transfer timed out i. <int_mw_end_add> Will be set to 1 when the Master Write transfer has finished. 0y0: Not detected 0y1: Master Write transfer finished j. <int_mw_set_add> Will be set to 1 when the data to be sent by Master Write transfer is set to the corresponding EP of Rx while the Master Write transfer is disabled. 0y0: Not detected 0y1: Master Write transfer address request k. <int_usb_reset_end> Indicates whether UDC2 has deasserted the usb_reset signal. The timing in which UDC2 sets the UDC2 register to the initial value after USB_RESET is after the usb_reset signal is deasserted. To detect this timing, use this bit. The status of the usb_reset signal can be checked using the usb_reset bit of Power Detect Control register. 0y0: UDC2 has not deasserted the usb_reset signal after this bit was cleared. 0y1: Indicates UDC2 has deasserted the usb_reset signal. TMPA910CRA- 491 2010-06-02 TMPA910CRA l. <int_usb_reset> Indicates whether UDC2 has asserted the usb_reset signal. The status of the usb_reset signal can be checked using the usb_reset bit of Power Detect Control register. 0y0: UDC2 has not asserted the usb_reset signal after this bit was cleared. 0y1: Indicates UDC2 has asserted the usb_reset signal. m. <int_suspend_resume> Asserts 1 each time the suspend_x signal of UDC2 changes. The status can be checked using the suspend_x bit of Power Detect Control register. 0y0: Status has not changed 0y1: Status has changed n. <int_nak> The int_nak signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT or INT_NAK register of UDC2. o. <int_ep> The int_ep signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT or INT_EP register of UDC2. p. <int_ep0> The int_ep0 signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT register of UDC2. q. <int_sof> The int_sof signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT register of UDC2. r. <int_rx_zero> The int_rx_zero signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT or INT_RX_ZERO register of UDC2. s. <int_status> The int_status signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT register of UDC2. t. <int_status_nak> The int_status_nak signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT register of UDC2. u. <int_setup> The int_setup signal of UDC2 can be directly read. To clear it, clear the corresponding bit of INT register of UDC2. TMPA910CRA- 492 2010-06-02 TMPA910CRA The connection between the output signals of UDC2 and bits [9] and [7:0] of this register is shown below. UDC2AB Interrupt Statusregister UDC2 bit10 : int_usb_reset_end bit9 : int_usb _reset bit7 : int_nak bit6 : int_ep bit5 : int_ep0 bit4 : int_sof bit3 : int_rx_zero bit2 : int_status bit1 : int_setup_nak bit0 : int_setup usb_reset int_nak int_ep int_ep0 int_sof int_rx_zero int_status int_setup _nak int_setup Figure 3.16.5 Connection between the flag output signals and interrupt bits TMPA910CRA- 493 2010-06-02 TMPA910CRA 2. UDINTENB (Interrupt Enable register) By writing 0 into the corresponding bit of this register, the corresponding interrupt source of the interrupt signal (INTS[21] output signal) can be disabled. Writing 1 will enable the corresponding interrupt source. Since the corresponding bit of Interrupt Status register will be set regardless of the enabled or disabled status of each bit, an interrupt may occur at the same time as this register was enabled. If such behavior should be avoided, the corresponding bit of Interrupt Status register should be cleared in advance. The interrupt control register corresponding to bits [7:0] of the Interrupt Status register is bits [15:8] of the INT register of UDC2, not this register. See the section of UDC2. Note: For the operation of interrupt signals, refer to "3.16.2.7 Interrupt Signal (INTS[21])". Address = (0xF440_0000) + (0x0004) Bit Bit Type Symbol Reset Description Value [31:30] - - Undefined Read as undefined. Write as zero. [29] mw_rerror_en R/W 0y0, (-) Master Write endpoint read error 0y0: Disable 0y1: Enable [28:26] - - Undefined Read as undefined. Write as zero. [25] dmac_reg_rd_en R/W 0y0, (-) DMAC register read complete 0y0: Disable 0y1: Enable [24] udc2_reg_rd_en R/W 0y0, (-) UDC2 register read access complete 0y0: Disable 0y1: Enable [23] mr_ahberr_en R/W 0y0, (-) Master Read transfer error status interrupt enable 0y0: Disable 0y1: Enable [22] mr_ep_dset_en R/W 0y0, (-) Master Read endpoint data set status interrupt enable 0y0: Disable 0y1: Enable [21] mr_end_add_en R/W 0y0, (-) Master Read transfer end status interrupt enable 0y0: Disable 0y1: Enable [20] mw_ahberr_en R/W 0y0, (-) Master Write transfer error status interrupt enable 0y0: Disable 0y1: Enable [19] mw_timeout_en R/W 0y0, (-) Master Write transfer timeout status interrupt enable 0y0: Disable 0y1: Enable [18] mw_end_add_en R/W 0y0, (-) Master Write transfer end status interrupt enable 0y0: Disable 0y1: Enable [17] mw_set_add_en R/W 0y0, (-) Master Write transfer address request status interrupt enable 0y0: Disable 0y1: Enable TMPA910CRA- 494 2010-06-02 TMPA910CRA Bit Bit Type Symbol Reset Description Value [16:11] - - Undefined Read as undefined. Write as zero. [10] usb_reset_end_en R/W 0y0, (-) USB_RESET end interrupt enable 0y0: Disable 0y1: Enable [9] usb_reset_en R/W 0y0, (-) USB_RESET interrupt enable 0y0: Disable 0y1: Enable [8] suspend_resume_en R/W 0y0, (-) Suspend/resume interrupt enable 0y0: Disable 0y1: Enable [7:0] - - Undefined Read as undefined. Write as zero. [Description] a. <mw_rerror_en> Controls the int_mw_rerror interrupt. 0y0: Disable 0y1: Enable b. <dmac_reg_rd_en > Controls the int_dmac_reg_rd interrupt. 0y0: Disable 0y1: Enable c. <udc2_reg_rd_en > Controls the int_udc2_reg_rd interrupt. 0y0: Disable 0y1: Enable d. <mr_ahberr_en > Controls the int_mr_ahberr interrupt. 0y0: Disable 0y1: Enable e. <mr_ep_dset_en > Controls the int_mr_ep_dset interrupt. 0y0: Disable 0y1: Enable f. <mr_end_add_en> Controls the int_mr_end_add interrupt. 0y0: Disable 0y1: Enable TMPA910CRA- 495 2010-06-02 TMPA910CRA g. <mw_ahberr_en> Controls the int_mw_ahberr interrupt. 0y0: Disable 0y1: Enable h. <mw_timeout_en> Controls the int_mw_timeout interrupt. 0y0: Disable 0y1: Enable i. <mw_end_add_en> Controls the int_mw_end_add interrupt. 0y0: Disable 0y1: Enable j. <mw_set_add_en> Controls the int_mw_set_add interrupt. 0y0: Disable 0y1: Enable k. <usb_reset_end_en> Controls the int_usb_reset_end interrupt. 0y0: Disable 0y1: Enable l. <usb_reset_en> Controls the int_usb_reset interrupt. 0y0: Disable 0y1: Enable m. <suspend_resume_en> Controls the int_suspend_resume interrupt. 0y0: Disable 0y1: Enable TMPA910CRA- 496 2010-06-02 TMPA910CRA 3. UDMWTOUT (Master Write Timeout register) This register is provided for controlling timeout during the Master Write operation. Address = (0xF440_0000) + (0x0008) Bit Bit Symbol Reset Type Description Value [31:1] timeoutset R/W 0x7FFFFFFF Master Write timeout timer setting register [0] timeout_en R/W 0y1 Master Write timeout enable register 0y0: Disable 0y1: Enable [Description] a. <timeoutset> The setting should not be changed during the Master Write transfer. Timeout occurs when the number of times CLK_U was set is counted after the data of Master Write (Rx) endpoint is exhausted. The timeout counter comprises 32 bits of which upper 31 bits can be set by timeoutset [31:1] of this register, while the lowest bit of the counter is set to 1. As CLK_U is 30 MHz, approximately 33 [ns] to 143 [s] can be set as a timeout value. While CLK_U stopped (PHY is being suspended and so on), no timeout interrupt will occur as the counter does not work. b. <timeouten> Used to enable Master Write timeout. It is set to Enable by default. The setting should not be changed during the Master Write transfer. 0y0: Disable 0y1: Enable TMPA910CRA- 497 2010-06-02 TMPA910CRA 4. UDC2STSET (UDC2 Setting register) This register controls transfer operations of UDC2. Address = (0xF440_0000) + (0x000C) Bit Bit Reset Type Symbol Description Value [31:5] - - Undefined Read as undefined. Write as zero. [4] eopb_enable R/W 0y1 [3:1] - - Undefined Master Read EOP enable 0y0: Disable 0y1: Enable Read as undefined. Write as zero. [0] tx0 R/W1S 0y0 NULL packet transmission 0y0: No operation 0y1: Transmits NULL packets [Description] a. <eopb_enable> Used to enable Master Read EOP. It is set to Enable by default. The setting should not be changed during the Master Read transfer. If this bit is 0, the final data transfer to UDC2 will not take place when the last word is 1 byte. If the last word is 2 bytes, the final data transfer to UDC2 will take place when epx_w_eop = 0. If this bit is 1, the final data transfer to UDC2 will take place when epx_w_eop = 1 regardless of byte number of the last word. Note: See section 3.16.2.9 "(1) Master Read transfer" for more information. 0y0: Master Read EOP disabled 0y1: Master Read EOP enabled b. <tx0> Used to transmit NULL packets at an endpoint connected to the Master Read operation side. Only valid when the mrepempty bit of Master Status register is 1, otherwise this bit is ignored. It will be automatically cleared to 0 after writing. Setting 1 to this bit will assert the epx_tx0data signal of the UDC2 Endpoint-I/F and the value of 1 is retained during the transmission of NULL packets. After this bit is set, next data setting for Tx-EP should not be made until it is cleared. 0y0: No operation 0y1: Transmits NULL packets TMPA910CRA- 498 2010-06-02 TMPA910CRA 5. UDMSTSET (DMAC Setting register) This register controls transfers of the built-in DMAC. Address = (0xF440_0000) + (0x0010) Bit Bit Reset Type Symbol Description Value [31:9] - - Undefined Read as undefined. Write as zero. [8] m_burst_type R/W 0y0, (-) Master burst type 0y0: INCR8 (HBURST5h) 0y1: INCR (HBURST1h) [7] - - Undefined Read as undefined. Write as zero. [6] mr_reset R/W1S 0y0 [5] mr_abort WO 0y0 [4] mr_enable R/W1S 0y0 [3] - - Undefined Master Read reset 0y0: No operation 0y1: Reset Master Read abort 0y0: No operation 0y1: Abort Master Read enable 0y0: Disable 0y1: Enable Read as undefined. Write as zero. [2] mw_reset R/W1S 0y0 [1] mw_abort WO 0y0 [0] mw_enable R/W1S 0y0 Master Write reset 0y0: No operation 0y1: Reset Master Write abort 0y0: No operation 0y1: Abort Master Write enable 0y0: Disable 0y1: Enable [Description] a. <m_burst_type> Selects the type of HBURST[2:0] when making a burst transfer in Master Write/Read transfers. The type of burst transfer made by UDC2AB is INCR8 (burst of 8 beat increment type). Accordingly, 0 (initial value) should be set in normal situation. However, in case INCR can only be used as the type of burst transfer based on the AHB specification of the system, set 1 to this bit. In that case, UDC2AB will make INCR transfer of 8 beat. Please note the number of beat in burst transfers cannot be changed. Setting of this bit should be made in the initial setting of UDC2AB. The setting should not be changed after the Master Write/Read transfers started. Note: UDC2AB does not make burst transfers only in Master Write/Read transfers. It combines burst transfers and single transfers. This bit affects the execution of burst transfers only. 0y0: INCR8 0y1: INCR TMPA910CRA- 499 2010-06-02 TMPA910CRA b. <mr_reset> Initializes the Master Read transfer block of UDC2AB. However, as the FIFOs of endpoints are not initialized, you need to access the Command register of UDC2 to initialize the corresponding endpoint separately from this reset. This reset should be used after stopping the Master operation. This bit will be automatically cleared to 0 after being set to 1. Subsequent Master Read transfers should not be made until it is cleared. 0y0: No operation 0y1: Reset c. <mr_abort> Controls Master Read transfers. Master Read operations can be stopped by setting 1 to this bit. When aborted during transfers, transfer of buffers for Master Read to UDC2 is interrupted and the mr_enable bit is cleared, stopping the Master Read transfer. Aborting completes when the mr_enable bit is disabled to 0 after setting this bit to 1. 0y0: No operation 0y1: Abort d. <mr_enable> Controls Master Read transfers. Enabling should be made when setting the transfer address is completed. It will be automatically disabled as the master transfer finishes. Since Master Read operations cannot be disabled with this register, use the mr_abort bit if the Master Read transfer should be stopped. 0y0: Disable 0y1: Enable e. <mw_reset> Initializes the Master Write transfer block. However, as the FIFOs of endpoints are not initialized, you need to access the Command register of UDC2 to initialize the corresponding endpoint separately from this reset. This reset should be used after stopping the Master operation. This bit will be automatically cleared to 0 after being set to 1. Subsequent Master Write transfers should not be made until it is cleared. 0y0: No operation 0y1: Reset TMPA910CRA- 500 2010-06-02 TMPA910CRA f. <mw_abort> Controls Master Write transfers. Master Write operations can be stopped by setting 1 to this bit. When aborted during transfers, transfer of buffers for Master Write from UDC2 is interrupted and the mw_enable bit is cleared, stopping the Master Write transfer. Aborting completes when the mw_enable bit is disabled to 0 after setting this bit to 1. 0y0: No operation 0y1: Abort g. <mw_enable> Controls Master Write transfers. Enabling should be made when setting the transfer address is completed. It will be automatically disabled as the master transfer finishes. Since Master Write operations cannot be disabled with this register, use the mw_abort bit if the Master Write transfer should be stopped. 0y0: Disable 0y1: Enable TMPA910CRA- 501 2010-06-02 TMPA910CRA 6. DMACRDREQ (DMAC Read Request register) This register is used to issue read requests for reading the following registers: * Master Read Current Address register * Timeout Count register The read value will be saved in the DMAC Read Value register. Note: As accesses to this register become unavailable when the clock (= CLK_U) supply from PHY is stopped with UDC2 suspended, no access should be made. If this register is accessed when the phy_suspend bit of Power Detect Control register is set to 1, an AHB error will be returned. Address = (0xF440_0000) + (0x0014) Bit Bit Type Symbol Reset Description Value [31] dmardreq R/W1S 0y0 [30] dmardclr R/W1S 0y0 Register read request & busy 0y0: No operation 0y1: Issue read request Read request clear - Undefined 0y0: No operation 0y1: Issue forced clearing Read as undefined. Write as zero. R/W 0y000000 - Undefined [29:8] [7:2] [1:0] - dmardadr - Read request register address (upper 6 bits) select 0x48: Read the Master Write Current Address register 0x58: Read the Master Read Current Address register 0x88: Read the Timeout Count register Read as undefined. Write as zero. [Description] a. <dmardreq> The bit for requesting read access to the DMAC registers. Setting this bit to 1 will make a read access to the address specified by dmardadr. When the read access is complete and the read value is stored in the DMAC Read Value register, this bit will be automatically cleared and the int_dmac_reg_rd bit of Interrupt Status register will be set to 1. 0y0: No operation 0y1: Issue read request b. <dmardclr> The bit for forcibly clearing the register read access request associated with DMAC. Setting this bit to 1 will forcibly stop the register read access request by dmardreq and the value of dmardreq will be cleared to 0. After the forced clearing completes, this bit will be automatically cleared. 0y0: No operation 0y1: Issue forced clearing TMPA910CRA- 502 2010-06-02 TMPA910CRA c. <dmardadr> Sets the address of the register (upper 6 bits) to be read. It should be set in combination with the dmardreq bit mentioned above. Any one of the following addresses should be set: 0x48: Read the Master Write Current Address register 0x58: Read the Master Read Current Address register 0x88: Read the Timeout Count register TMPA910CRA- 503 2010-06-02 TMPA910CRA 7. DMACRDVL (DMAC Read Value register) The register in which the values read via DMAC Read Request register are stored. (Relevant registers) * Master Write Current Address register * Master Read Current Address register * Timeout Count register Address = (0xF440_0000) + (0x0018) Bit [31:0] Bit Symbol dmardata Type RO Reset Description Value 0x00000000 Register read data [Description] a. <dmardata> This register stores the data requested by DMAC Read Request register. This register should not be accessed when the dmardreq bit of DMAC Read Request register is set to 1. TMPA910CRA- 504 2010-06-02 TMPA910CRA 8. UDC2RDREQ (UDC2 Read Request register) The register for issuing read requests when reading UDC2 registers. The read value will be saved in the UDC2 Read Value register. Address = (0xF440_0000) + (0x001C) Bit Bit Type Symbol Reset Description Value [31] udc2rdreq R/W1S 0y0 [30] udc2rdclr R/W1S 0y0 [29:10] - - Undefined [9:2] udc2rdadr R/W 0x00 [1:0] - - Undefined Register read request & busy 0y0: No operation 0y1: Issue read request Read request clear 0y0: No operation 0y1: Issue forced clearing Read as undefined. Write as zero. The address of the UDC2 register that issues the read request Read as undefined. Write as zero. [Description] a. <udc2rdreq> The bit for requesting read access to the UDC2 registers. Setting this bit to 1 will make a read access to the address set in the udc2rdadr bit. When the read access is complete and the read value is set to UDC2 Read Value register, this bit will be automatically cleared and the UDINTSTS<int_udc2_reg_rd> bit of Interrupt Status register will be set to 1. During a write access to UDC2 registers, it works as a status bit which indicates the access being made to display the value of 1. Subsequent accesses to UDC2 registers should not be made while this bit is set to 1. 0y0: No operation 0y1: Issue read request b. <udc2rdclr> The bit for forcibly clearing the read/write access request of UDC2 registers. Setting this bit to 1 will forcibly stop the register read request/UDC2 write access by udc2rdreq and the value of udc2rdreq will be 0. After the forced clearing completes, this bit will be automatically cleared to 0. When interrupted, the read and write values during the access will not be secured. 0y0: No operation 0y1: Issue forced clearing c. <udc2rdadr> Sets the address of the UDC2 register (upper 8 bits) to be read. Regarding registor address, please refer to "Table 3.16.2 Register map".Between 0x0200 to 0x0334 that is the offset address of this register map corresponds.It should be set in combination with the udc2rdreq bit mentioned above. TMPA910CRA- 505 2010-06-02 TMPA910CRA 9. UDC2RDVL (UDC2 Read Value register) The register in which the values read via UDC2 Read Request register are stored. Address = (0xF440_0000) + (0x0020) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. [15:0] udc2rdata RO 0x0000 Register read data [Description] a. <udc2rdata> This register stores the data requested by UDC2 Read Request register. This register should not be accessed when the udc2rdreq bit of UDC2 Read Request register is set to 1. TMPA910CRA- 506 2010-06-02 TMPA910CRA 10. ARBTSET (Arbiter Setting register) The register for setting the priority when the internal arbiter accesses AHB. Setting of this register should be changed after stopping the Master operation. Please be sure to set the arbitration method with the following procedures (You need to make an access three times in total.): (1) Write 0 into the abt_en bit to disable the arbitration circuit. (2) Make settings for the abtmod and abtpri_* bits. The abtmod and abtpri_* bits cannot be set unless 0 is written into the abt_en bit in (1). Values of the register for setting the priority should not be overlapped regardless of the value of the abtmod bit. (3) Write 1 into the abt_en bit with the abtmod and abtpri_* bits set in (2) retained to enable the arbitration circuit. Address = (0xF440_0000) + (0x003C) Bit Bit Type Symbol Reset Description Value [31] abt_en R/W 0y1 [30:29] - - Undefined [28] abtmod R/W 0y0 [27:14] - - Undefined [13:12] abtpri_w1 R/W 0y11 [11:10] - - Undefined [9:8] abtpri_w0 R/W 0y10 [7:6] - - Undefined [5:4] abtpri_r1 R/W 0y01 [3:2] - - Undefined [1:0] abtpri_r0 R/W 0y00 Arbiter enable 0y0: Disable (DMA access not allowed) 0y1: Enable Read as undefined. Write as zero. Arbiter mode 0y0: Round-robin 0y1: Fixed priority Read as undefined. Write as zero. Master Write 1 priority 0y00 to 0y11 Read as undefined. Write as zero. Master Write 0 priority 0y00 to 0y11 Read as undefined. Write as zero. Master Read 1 priority 0y00 to 0y11 Read as undefined. Write as zero. Master Read 0 priority 0y00 to 0y11 [Description] a. <abt_en> Enables the arbiter operation when making an access between DMAC and AHB. 0 should be set to this bit when setting the abtmod and abtpri_* bits of this register. Please note that 1 cannot be set to this bit in case values set for abtpri_* overlap. Be sure to set this bit to 1 before starting a DMA access. 0y0: Disable (DMA access not allowed) 0y1: Enable TMPA910CRA- 507 2010-06-02 TMPA910CRA b. <abtmod> Sets the mode of arbiter. Write access is only available when the abt_en bit is set to 0. If 0 is set to this bit, access rights to the AHB bus will be given in a round-robin fashion regardless of the values set to each abtpri_* bit. If 1 is set to this bit, access rights to the AHB bus will be given in accordance with the access priority based on the values set to each abtpri_* bit. 0y0: Round-robin 0y1: Fixed priority c. <abtpri_w1> Set the priority of DMA accesses for Master Write 1 when the fixed priority mode is selected. Write access is only available when the abt_en bit is set to 0. Priority ranges from [0] (highest) to [3] (lowest). d. <abtpri_w0> Set the priority of DMA accesses for Master Write 0 when the fixed priority mode is selected. Write access is only available when the abt_en bit is set to 0. Priority ranges from [0] (highest) to [3] (lowest). e. <abtpri_r1> Set the priority of DMA accesses for Master Read 1 when the fixed priority mode is selected. Write access is only available when the abt_en bit is set to 0. Priority ranges from [0] (highest) to [3] (lowest). f. <abtpri_r0> Set the priority of DMA accesses for Master Read 0 when the fixed priority mode is selected. Write access is only available when the abt_en bit is set to 0. Priority ranges from [0] (highest) to [3] (lowest). TMPA910CRA- 508 2010-06-02 TMPA910CRA * Note: Be sure to set different priority values for the abtpri_w1, abtpri_w0, abtpri_r1, and abtpri_r0 bits. If the same priority values are set, you will not be able to set 1 to abt_en. <Relationship of DMAC and the priority area of the Arbiter Setting register> Current UDC2AB specification supports one DMAC for Master Write (DMAC_W0) and one DMAC for Master Read (DMAC_R0). The second DMAC for Master Write (DMAC_W1) and the second DMAC for Master Read (DMAC_R1) are not supported. Accordingly, setting priority for DMAC_W1 and DMAC_R1 has virtually no meaning, but you should be sure to set different priority values for the abtpri_w1, abtpri_w0, abtpri_r1, and abtpri_r0 bits as mentioned above. There will be no problem to set values for the corresponding register areas of an unpackaged DMAC. The priority areas of Arbiter Setting register correspond with DMAC as shown below. AHB Master Logical Block AHB Master DMAC_W0 DMAC_W1 DMAC_R0 DMAC_R1 EP1 EPx EP2 EPy abtpri_w0 abtpri_w1 abtpri_r0 abtpri_r1 Priority of Arbiter Setting register Figure 3.16.6 Relationship between DMAC and priority areas TMPA910CRA- 509 2010-06-02 TMPA910CRA 11. UDMWSADR (Master Write Start Address register) Sets the start address of Master Write transfer (UDC2 to AHB). Address = (0xF440_0000) + (0x0040) Bit [31:0] Bit Symbol mwsadr Type R/W Reset Description Value 0xFFFFFFFF Master Write start address [Description] a. <mwsadr> Set the start address of Master Write transfer. However, as this master operation only supports address increments, values lower than the Master Write End Address register should be set. TMPA910CRA- 510 2010-06-02 TMPA910CRA 12. UDMWEADR (Master Write End Address register) Sets the end address of Master Write transfer (UDC2 to AHB). Address = (0xF440_0000) + (0x0044) Bit [31:0] Bit Symbol mweadr Type R/W Reset Description Value 0xFFFFFFFF Master Write end address [Description] a. <mweadr> Set the end address of Master Write transfer. However, as this master only supports address increments, values above the Master Write Start Address register should be set. TMPA910CRA- 511 2010-06-02 TMPA910CRA 13. UDMWCADR (Master Write Current Address register) Displays the address to which transfers from endpoints to the Master Write buffers have been currently completed in Master Write transfers (UDC2 to AHB). This register cannot be read by directly specifying the address. In order to read it, set a value to the DMAC Read Request register and then read the value from the DMAC Read Value register. Address = (0xF440_0000) + (0x0048) Bit [31:0] Bit Symbol mwcadr Type RO Reset Description Value 0x00000000 Master Write current address [Description] a. <mwcadr> Displays the addresses to which transfers from endpoints to the Master Write buffers have been currently completed in Master Write transfers. This can be used in case a timeout interrupt has occurred or an error occurred during the transfer process. This address is incremented at the point when the data is set from the endpoint to the Master Write buffer, while the data will reside inside the target device or the Master Write buffer during the Master Write transfer process until the displayed address. TMPA910CRA- 512 2010-06-02 TMPA910CRA 14. UDMWAHBADR (Master Write AHB Address register) Displays the address where the transfer to the target device has completed in Master Write transfer (UDC2 to AHB). In some DMA transfers, accesses are made on a byte basis depending on the conditions. Please note that the address to be saved is the word border even when accessing by byte. Address = (0xF440_0000) + (0x004C) Bit [31:0] Bit Symbol mwahbadr Type RO Reset Description Value 0xFFFFFFFF Master Write AHB address [Description] a. <mwahbadr> Displays the address where the transfer to the target device has completed in Master Write transfer. This can be used in case a timeout interrupt has occurred or an error occurred during the transfer process. This address is incremented at the point when the data is set to the target device, while the data will reside inside the target device or during the Master Write transfer process until the displayed address. TMPA910CRA- 513 2010-06-02 TMPA910CRA 15. UDMRSADR (Master Read Start Address register) Sets the start address of Master Read transfer (AHB to UDC2). Address = (0xF440_0000) + (0x0050) Bit [31:0] Bit Symbol mrsadr Type R/W Reset Description Value 0xFFFFFFFF Master Read start address [Description] a. <mrsadr> Set the start address of Master Read transfer. However, as this master only supports address increments, values lower than the Master Read End Address register should be set. TMPA910CRA- 514 2010-06-02 TMPA910CRA 16. UDMREADR (Master Read End Address register) Sets the end address of Master Read transfer (AHB to UDC2). Address = (0xF440_0000) + (0x0054) Bit [31:0] Bit Symbol Mreadr Type R/W Reset Description Value 0xFFFFFFFF Master Read end address [Description] a. <Mreadr> Set the end address of Master Read transfer. However, as this master only supports address increments, values above the Master Read Start Address register should be set. TMPA910CRA- 515 2010-06-02 TMPA910CRA 17. UDMRCADR (Master Read Current Address register) Displays the address where the transfer from the target device to the endpoint has completed in Master Read transfer (AHB to UDC2). This register cannot be read by directly specifying the address. In order to read it, set a value to the DMAC Read Request register and then read the value from the DMAC Read Value register. Address = (0xF440_0000) + (0x0058) Bit [31:0] Bit Symbol mrcadr Type RO Reset Description Value 0x00000000 Master Read current address [Description] a. <mrcadr> Displays the address to which transfers from the target device to the endpoint have been currently completed in Master Read transfers. This address is incremented at the point when the data is set from the Master Read buffer to the endpoint, while the data will reside inside the FIFO for the endpoint during the Master Read transfer process until the displayed address. TMPA910CRA- 516 2010-06-02 TMPA910CRA 18. UDMRAHBADR (Master Read AHB Address register) Displays the address where the transfer from the target device to UDC2AB has completed in Master Read transfer (AHB to UDC2). In some DMA transfers, accesses are made on a byte basis depending on the conditions. The address to be saved is the word border when accessing by byte. Address = (0xF440_0000) + (0x005C) Bit [31:0] Bit Symbol mrahbadr Type RO Reset Description Value 0xFFFFFFFF Master read AHB address [Description] a. <mrahbadr> Displays the address where the transfer from the target device to UDC2AB has completed in Master Read transfer. This address is incremented at the point when the data is set from the target device, while the data will reside inside the buffer or the FIFO for the endpoint during the Master Read transfer process until the displayed address. TMPA910CRA- 517 2010-06-02 TMPA910CRA 19. UDPWCTL (Power Detect Control register) Controls UDC2AB when reset/suspended. Address = (0xF440_0000) + (0x0080) Bit Bit Reset Type Symbol Description Value [31:8] - Undefined - [7] wakeup_en R/W 0y0, (-) Read as undefined. Write as zero. Wakeup enable 0y0: Do not assert the WAKEUP_X signal 0y1: Assert the WAKEUP_X signal (Note 1) [6] phy_remote_wkup R/W1S 0y0, (-) Remote wakeup 0y0: No operation 0y1: Wakeup [5] phy_resetb R/W 0y1, (-) PHY reset 0y0: Reset asserted 0y1: Reset deasserted [4] suspend_x RO 0y1 Suspend detection 0y0: Suspended (suspend_x = 0) 0y1: Not suspended (suspend_x = 1) [3] phy_suspend R/W 0y0, (-) PHY suspend 0y0: Not suspended 0y1: Suspended [2] pw_detect RO 0y0, (-) USB bus power detect 0y0: USB bus disconnected (VBUSPOWER = 0) 0y1: USB bus connected (VBUSPOWER = 1) (Note 2) [1] pw_resetb R/W 0y1, (-) Power reset 0y0: Reset asserted 0y1: Reset deasserted [0] usb_reset RO 0y0 USB_RESET 0y0: usb_reset = 0 0y1: usb_reset = 1 Note 1: While UDC2AB originally has the function to assert the Wakeup signal, it is not supported for this LSI. Note 2: While UDC2AB originally has the function to assert the int_powerdetect interrupt when VBUS is detected, it is not supported for this LSI. Power Detect Control<pw_detect> always indicates 0. [Description] a. <wakeup_en> Set this bit to '1' if you want the system (AHB end) to sleep to stop CLK_H when the USB is suspended. If this bit is set to 1, the WAKEUP_X signal will be asserted to 0 asynchronously when the suspended status is cancelled (suspend_x = 1) or the system is disconnected (VBUSPOWER = 0), making it available for resuming the system. See also section 3.16.2.13 "(4) Signal operations when suspended and resumed (disconnected)" for more information on using this bit. 0y0: Do not assert the WAKEUP_X signal 0y1: Assert the WAKEUP_X signal Note: While UDC2AB originally has the function to assert the Wakeup signal, it is not supported for this LSI. TMPA910CRA- 518 2010-06-02 TMPA910CRA b. <phy_remote_wkup> This bit is used to perform the remote wakeup function of USB. Setting this bit to 1 makes it possible to assert the udc2_wakeup output signal (wakeup input pin of UDC2) to 1. However, since setting this bit to 1 while no suspension is detected by UDC2 (when suspend_x = 1) will be ignored (not to be set to 1), be sure to set it only when suspension is detected. It will be automatically cleared to 0 when resuming the USB is completed (when suspend_x is deasserted). See also section 3.16.2.13 "(4) Signal operations when suspended and resumed (disconnected)" for more information on using this bit. 0y0: No operation 0y1: Wakeup c. <phy_resetb> Setting this bit to 0 will make the PHYRESET output signal asserted to 1. The PHYRESET signal can be used to reset PHY. Since this bit will not be automatically released, be sure to clear it to 1 after the specified reset time of PHY. 0y0: Reset asserted 0y1: Reset deasserted d. <suspend_x> Detects the suspend signal (a value of the suspend_x signal from UDC2 synchronized). 0y0: Suspended (suspend_x = 0) 0y1: Unsuspended (suspend_x = 1) e. <phy_suspend> Setting this bit to 1 will make the PHYSUSPEND output signal asserted to 0 (CLK_H synchronization). It can be used as a pin for suspending PHY. Setting this bit to 1 makes the UDC2 register and DMAC Read Request register not accessible. It will be automatically cleared to 0 when resumed (when suspend_x of UDC2 is deasserted). See also section 3.16.2.13 "(4) Signal operations when suspended and resumed (disconnected)" for more information on using this bit. 0y0: Not suspended 0y1: Suspended f. <pw_detect> Indicates the status of the VBUSPOWER input pin. 0y0: USB bus disconnected (VBUSPOWER = 0) 0y1: USB bus connected (VBUSPOWER = 1) Note: While UDC2AB originally has the function to assert the int_powerdetect interrupt when VBUS is detected, it is not supported for this LSI. Power Detect Control<pw_detect> always indicates 0. TMPA910CRA- 519 2010-06-02 TMPA910CRA g. <pw_resetb> Software reset for UDC2AB. (See section 3.16.2.6 "Reset" for details.). Setting this bit to 0 will make the PW_RESETB output pin asserted to 0. Resetting should be made while the master operation is stopped. Since this bit will not be automatically released, be sure to clear it. 0y0: Reset asserted 0y1: Reset deasserted h. <usb_reset> The value of the usb_reset signal from UDC2 synchronized. 0y0: usb_reset = 0 0y1: usb_reset = 1 TMPA910CRA- 520 2010-06-02 TMPA910CRA 20. UDMSTSTS (Master Status register) This is a status register of UDC2AB. Address = (0xF440_0000) + (0x0084) Bit Bit Type Symbol Reset Description Value [31:5] - - Undefined Read as undefined. [4] mrepempty RO 0y0, (-) Master Read endpoint empty 0y0: Indicates the endpoint contains some data. 0y1: Indicates the endpoint is empty. [3] mrbfemp RO 0y1 Master Read buffer empty 0y0: Indicates the buffer for the Master Read DMA contains some data. 0y1: Indicates the buffer for the Master Read DMA is empty. [2] mwbfemp RO 0y1 Master Write buffer empty 0y0: Indicates the buffer for the Master Write DMA contains some data. 0y1: Indicates the buffer for the Master Write DMA is empty. [1] mrepdset RO 0y0, (-) Master Read endpoint DATASET 0y0: Data can be transferred into the endpoint. 0y1: There is no space to transfer data in the endpoint. [0] mwepdset RO 0y0, (-) Master Write endpoint DATASET 0y0: No data exists in the endpoint. 0y1: There is some data to be read in the endpoint. [Description] a. <mrepempty> This is a register that indicates the endpoint for UDC2Rx is empty. Ensure that this bit is set to 1 when sending a NULL packet using the tx0 bit of UDC2 Setting register. (This bit is the eptx_empty input signal with CLK_H synchronization.) 0y0: Indicates the endpoint contains some data. 0y1: Indicates the endpoint is empty. TMPA910CRA- 521 2010-06-02 TMPA910CRA b. <mrbfemp> Indicates whether or not the buffer for the Master Read DMA in UDC2AB is empty. 0y0: Indicates the buffer for the Master Read DMA contains some data. 0y1: Indicates the buffer for the Master Read DMA is empty. c. <mwbfemp> Indicates whether or not the buffer for the Master Write DMA in UDC2AB is empty. 0y0: Indicates the buffer for the Master Write DMA contains some data. 0y1: Indicates the buffer for the Master Write DMA is empty. d. <mrepdset> This bit will be set to 1 when the data to be transmitted is set to the Tx-EP of UDC2 by Master Read DMA transfer, making no room to write in the endpoint. It will turn to 0 when the data is transferred from UDC2 by the IN-Token from the host. While this bit is set to 0, DMA transfers to the endpoint can be made. (This bit is the eptx_dataset input signal with CLK_H synchronization.) 0y0: Data can be transferred into the endpoint. 0y1: There is no space to transfer data in the endpoint. e. <mwepdset> This bit will be set to 1 when the data received is set to the Rx-EP of UDC2. It will turn to 0 when the entire data was read by the DMA for Master Write. (This bit is the eprx_dataset input signal with CLK_H synchronization.) 0y0: No data exists in the endpoint. 0y1: There is some data to be read in the endpoint. TMPA910CRA- 522 2010-06-02 TMPA910CRA 21. UDTOUTCNT (Timerout Count register) This is a register to read the timeout count value. (for debugging) This register cannot be read by directly specifying the address. In order to read it, set a value to the DMAC Read Request register and then read the value from the DMAC Read Value register. Address = (0xF440_0000) + (0x0088) Bit [31:0] Bit Symbol tmoutcnt Type RO Reset Description Value 0x00000000 Timeout count [Description] a. <tmoutcnt> This is used for debugging. Values of the timer can be read when the timeout_en bit of Master Write Timeout register is enabled. It will be decremented each time CLK_U is counted after the endpoint for Master Write (Rx-EP) becomes empty. TMPA910CRA- 523 2010-06-02 TMPA910CRA 22. UDC2 (UDC2 register) (0x0200 to 0x03FC) The internal register of UDC2 (16 bits) can be accessed by making an access to the (0xF440_0000) + 0x200-0x3FC. AHB data bus of UDC2AB has 32 bits, of which bits 15-0 correspond with the UDC2 data bus. Bits 31-16 are reserved bits and read-only (read value: 0). Make a WORD (32-bit) access for both write and read. (However, a BYTE (8-bit) access may be made for Write accesses to the EPx_FIFO register. Details will be discussed later.) It will take some time to complete an access for both write and read (accessing period to UDC2). Be sure to begin subsequent accesses after the previous UDC2 register access is completed, using the int_udc2_reg_rd interrupt. (You can also use the udc2rdreq bit of UDC2 Read Request register to confirm the access status when reading.) * Write access When making a write access to the UDC2 register, write it directly in the relevant address. * Read access When making a read access to the UDC2 register, use UDC2 Read Request and UDC2 Read Value registers. First, you set the address to access to the UDC2 Read Request register and then read the data from the UDC2 Read Value register for reading. You cannot read the data directly from the address shown in the address map. * EPx_FIFO register When making a write access to the EPx_FIFO register, a lower 1-byte access may be required in UDC2 PVCI I/F. In such a case, make a BYTE access to the lower 1 byte for UDC2AB. If a lower 1-byte access is required when making a read access, make an access via UDC2 Read Request register as usual and read the data from UDC2 Read Value register. In that case, the access to UDC2 Read Value register can be either by WORD or BYTE. * Reserved registers in UDC2 Do not make any access to registers of endpoints not supported by UDC2 to be connected and to "Reserved" registers. (In case those registers are accessed, the access from UDC2AB to UDC2 itself will take place. It will be a Dummy write to UDC2 in case of write accesses. In case of read accesses, the read data from UDC2 (udc2_rdata) will be an indefinite value and the indefinite value will be set to the UDC2 Read Value register.) * Accesses when UDC2 is suspended When UDC2 is in the suspended status, register accesses to UDC2 become unavailable if the clock (= CLK_U) supply from PHY is stopped. Make no register accesses to UDC2 in such cases. If the UDC2 register is accessed when the phy_suspend bit of Power Detect Control register is set to 1, an AHB error will be returned. TMPA910CRA- 524 2010-06-02 TMPA910CRA Address = (0xF440_0000) + (0x0200-0x03FC) Bit Bit Reset Type Symbol Description Value [31:16] - - Undefined [15:0] udc2_data - - Read as undefined. Write as zero. UDC2 data register Refer to the section of UDC2 on the data values. Access flow diagram for UDC2 register is shown below. AHB UDC2AB UDC2AB UDC2 (1) Issues a Read request UDC2RDREQ (Write access to UDC2RDREQ) Register PVCI Read UDC2 Register access Address Relevant register (2) INTS[21] interrupt occurs (or refer to int_udc2_reg_rd bit of UDINTSTS) UDC2RDVL Register Access complete Read Value (3) Confirm result of Read (Read access to UDC2RDVL) Figure 3.16.7 Read access flow for UDC2 register TMPA910CRA- 525 2010-06-02 TMPA910CRA UDC2AB AHB UDC2AB UDC2 (1) Write access to relevant UDC2 address PVCI Write access Relevant register (2) INTS[21] interrupt occurs (Or refer to int_udc2_reg_rd bit of access UDINTSTS) complete Figure 3.16.8 Write access flow for UDC2 register TMPA910CRA- 526 2010-06-02 TMPA910CRA 3.16.2.6 Reset UDC2AB supports software reset by the Power Detect Control<pw_resetb>. It also supports master channel reset (mr_reset/mw_reset bit of DMAC Setting register) for DMAC master transfers. * Software reset ( Power Detect Control<pw_resetb> ) Some bits of each register are initialized by hardware reset but not initialized by software reset with the values retained. As details are provided in the descriptions of each register, refer to section 3.16.2.5 "Registers". When the USB bus power is detected, make software reset as initialization is needed. * Master channel reset (mr_reset/mw_reset bit of DMAC Setting register) While the mw_reset bit is provided for the Master Write transfer block and the mr_reset bit for the Master Read transfer block, only the relevant master blocks are initialized and the UDC2AB register will not be initialized. For more information on using each reset, see section 3.16.2.5 "(2) 5. UDMSTSET (DMAC Setting register)." TMPA910CRA- 527 2010-06-02 TMPA910CRA 3.16.2.7 Interrupt Signal (INTS[21]) The interrupt output signal of UDC2AB (INTS[21]) consists of interrupts generated by UDC2 and interrupts generated from other sources. Once the interrupt condition is met, UDC2AB sets the corresponding bit of its internal Interrupt Status register. When that bit is set, INTS[21] will be asserted if the relevant bit of Interrupt Enable register has been set to "Enable." When the relevant bit of Interrupt Enable register has been set to "Disable," 1 will be set to the corresponding bit of Interrupt Status register while INTS[21] will not be asserted. When the relevant bit of Interrupt Enable register is set to "Enable" with Interrupt Status register set, INTS[21] will be asserted immediately after the setting is made. Initial values for Interrupt Enable register are all 0 (Disable). The image of the aforementioned description is shown in the figure below. Interrupt Status Register INTS[21] Interrupt Enable Register Note: Refer to section of UDC2 for the UDC2 interrupt output signal masking. Figure 3.16.9 Relationship of INTS[21] and registers TMPA910CRA- 528 2010-06-02 TMPA910CRA 3.16.2.8 Overall Operation Sequence The overall operation sequence of UDC2AB is as follows: 1. Hardware reset 2. Set the interrupt signal In the Interrupt Enable register, set the required bit of the interrupt source to "Enable." See section 3.16.2.7 "Interrupt Signal (INTS[21])" for more information. 3. Detect the USB bus power supply (connect) and initialize See section 3.16.2.11 "USB Bus Power Detecting Sequence" for more information. Note: While UDC2AB originally has the function to assert the int_powerdetect interrupt when VBUS is detected, it is not supported for this LSI. Power Detect Control<pw_detect> always indicates 0. 4. USB enumeration response See section 3.16.3.4 "USB Device Response" in the section of UDC2. 5a. Master Read transfer Make a Master Read transfer corresponding to the receiving request from the USB host. See section 3.16.2.9 "(1) Master Read transfer" for more information. 5b. Master Write transfer Make a Master Write transfer corresponding to the sending request from the USB host. See section 3.16.2.9 "(4) Master Write transfer" for more information. 6. USB bus power supply disconnection It may be possible that USB bus power supply is disconnected at any timing. See section 3.16.2.11 "USB Bus Power Detecting Sequence" for more information. Note: While UDC2AB originally has the function to assert the int_powerdetect interrupt when VBUS is detected, it is not supported for this LSI. Power Detect Control<pw_detect> always indicates 0. Hardware reset 2. Set the interrupt signal 3. Detect the USB bus USB power supply (connect) () and initialize 6.USB USB bus power supply disconnection () USB enumeration response Receive request Transfer request 5a.a Master Read transfer 5b. Master Write transfer Figure 3.16.10 Overall operation sequence TMPA910CRA- 529 2010-06-02 TMPA910CRA 3.16.2.9 Master Transfer Operation This section describes the master transfer operation of UDC2AB. When you start a master transfer, be sure to set the transfer setting of the relevant endpoint of UDC2 (bus_sel of UDC2 EPx_Status register (bit14)) to the direct access mode. It is prohibited to start DMAC when it is set to "Common bus access." (1) Master Read transfer * EOP enable mode Master Read transfers when UDC2STSET<eopb_enable> is set to 1 (Master Read EOP enable) are described here. Master Read operations will be as follows: 1. Set Master Read Start Address and Master Read End Address registers. 2. Set the bits associated to the Master Read operation of DMAC Setting register and set 1 to the mr_enable. 3. UDC2AB starts the data transfer to the endpoint of UDC2. UDC2 transfers the data to the IN token from the USB host. 4. When the Master Read transfer reaches the Master Read end address, UDC2AB asserts the int_mr_end_add interrupt. 5. After the handling by the software ended, return to 1. Note 1: About short packets If the transfer size (Master Read End Address - Master Read Start Address + 1) is not the same size as the Max packet size, the last IN transfer will be the transfer of short packets. Example: In case Master Read transfer size: 1035 bytes, and Max packet size: 512 bytes, Transfers will take place in: 1st time: 512 bytes 2nd time: 512 bytes 3rd time: 11 bytes Note 2: About int_mr_end_add interrupt The int_mr_end_add interrupt occurs when the data transfer to the UDC2 endpoint is finished. In order to confirm whether the entire data has been transferred from UDC2 to the USB host, check the mrepempty bit of Master Status register. TMPA910CRA- 530 2010-06-02 TMPA910CRA * EOP Disable mode Master Read transfers when UDC2STSET<eopb_enable > is set to 0 (Master Read EOP disable) are described here. Master Read operations will be as follows: 1. Set Master Read Start Address and Master Read End Address registers. 2. Set the register associated to the Master Read operation of DMAC Setting register and set 1 to the mr_enable bit. 3. UDC2AB starts the data transfer to the endpoint of UDC2. UDC2 transfers the data to the IN token from the USB host. 4. When reached the Master Read end address, UDC2AB asserts the int_mr_end_add interrupt. If the FIFO of the endpoint is as full as the maximum packet size in a Master Read transfer, the data will be transferred to the IN token from the USB host. If not, the data will remain in the FIFO and will be carried over to the next transfer. 5. After the handling by the software ended, return to 1. Note: When UDC2AB is used in the EOP Disable mode, short packets will not be sent out even if the data string to be sent has been transferred. EOP Disable mode should be used only in case the size of the data string is a multiple of the maximum packet size. The mode can be used if the total size of data string is a multiple of the maximum packet size. For example, the following transfer may be allowed: Example: * Size of the first Master Read transfer: 1000 bytes * Size of the second Master Read transfer: 24 bytes (Total of first and second transfers = 1024 bytes) * Maximum packet size: 512 bytes A transfer of 512 bytes will be made twice for the IN transfer. TMPA910CRA- 531 2010-06-02 TMPA910CRA (2) Aborting of Master Read transfers You can abort Master Read transfers with the following operation: 1. Use UDC2 Command register to set the status of the relevant endpoint to Disabled (EP_Disable). (If aborted without making the endpoint disabled, unintended data may be sent to the USB host.) 2. In order to stop the Master Read transfer, set 1 (Abort) to UDMSTSET <mr_abort>. 3. In order to confirm that the transfer is aborted, check that the mr_enable bit of DMAC Setting register was disabled to 0. Subsequent operations should not be made while the mr_enable bit is 1. (Information on the address where the transfer ended when aborted can be confirmed with Master Read Current Address and Master Read AHB Address registers.) 4. In order to initialize the Master Read transfer block, set 1 (Reset) to UDMSTSET<mr_reset>. 5. Use the Command register (EP_FIFO_Clear) to initialize the FIFO for the relevant endpoint. 6. Use the Command register (EP_Enable) to enable the relevant endpoint. TMPA910CRA- 532 2010-06-02 TMPA910CRA (3) Setting the maximum packet size in Master Read transfers If the maximum packet size of the endpoint to be connected with the Master Read function of UDC2AB will be an odd number, there will be following restrictions to which you should pay attention: * Even if the maximum packet size of the endpoint should be handled as an odd number, the setting of the max_pkt bit of UDC2 EPx_MaxPacketSize register should be an even number. Note: Refer to the "section 3.16.4.2 "Appendix B About Setting an Odd Number of Bytes as MaxPacketSize" for more information on this setting. * Set the eopb_enable bit of UDC2 Setting register to 1 (Master Read EOP enable). * Make the transfer size to be specified for one Master Read transfer (Master Read End Address - Master Read Start Address + 1) not exceed the maximum packet size of an odd number. (Example) A setting satisfying the above conditions: * Set the maximum packet size of the endpoint (value to pass to the USB host) to be 63 bytes. * Make the setting of the max_pkt bit of UDC2 EPx_MaxPacketSize register to be 64 bytes. * Keep the transfer size to be specified for one Master Read transfer to 63 bytes or less. TMPA910CRA- 533 2010-06-02 TMPA910CRA (4) Master Write transfer * Master Write transfer sequence The operation of Master Write transfers are discussed here. Master Write operations will be as follows: 1. Set Master Write Start Address and Master Write End Address registers. 2. Set the bits associated to the Master Write operation of DMAC Setting register and set 1 to the mw_enable bit. 3. UDC2AB makes a Master Write transfer to the data in the endpoint received from the USB host. 4. Since the int_mw_end_add interrupt will be asserted when the writing ended to reach the Master Write End Address (with no timeout processed), you should make necessary arrangement with the software. UDC2 will return to 1 after receiving the correct packet. Note: UDC2AB will assert the int_mw_set_add interrupt when the packet is received normally from the USB host with the mw_enable bit of DMAC Setting register disabled. TMPA910CRA- 534 2010-06-02 TMPA910CRA (5) Timeout Master Write transfers would not finish if the OUT transfer from the USB host should stagnate before reaching the Master Write End Address during the transfer. In order to cope with such circumstances, you can set the timeout function. When this timeout function is used, all data stored in the buffer in UDC2AB at the point of timeout will be transferred to AHB. Timeout can be processed with the following operation: 1. Make an access to the Master Write Timeout register before starting a Master Write transfer and set timeoutset (timeout time) to make timeout_en enabled 1. 2. Start the Master Write transfer in accordance with the instruction in the preceding section. 3. When the timeout has occurred, the int_mw_timeout interrupt will be asserted. (The int_mw_end_add interrupt will not be asserted.) In that case, the Master Write transfer is not completed to reach the Master Write End Address. UDC2AB clears the mw_enable bit of DMAC Setting register to 0. 4. In Master Write Current Address register, the address to which the transfer has completed to the AHB end can be confirmed. Please note that the timeout counter advances during the Master Write transfer with the timeout function enabled, but the counter will be reset to the preset value when the OUT transfer from the USB host to the relevant endpoint is received and begin recounting (see the figure below). It means that the time until timeout is "from the point when the last transfer from the USB host to the relevant endpoint has occurred during the Master Write transfer to the preset time," rather than "from the point when the Master Write transfer has begun to the preset time." If you do not use the timeout function, be sure to set the timeout_en bit of Master Write Timeout register to "Disable 0" before starting the Master Write transfer. In that case, the transfer will not finish until reaching the preset Master Write End Address. OUT Transfer eprx_dataset UDMWTOUT 91 33 mw_enable UDTOUTCNT 33 32 31 30 29 33 32 31 30 29 28 91 90 Figure 3.16.11 Example of MW timeout count TMPA910CRA- 535 2010-06-02 TMPA910CRA (6) Aborting of Master Write transfers You can abort Master Write transfers with the following operation: 1. Use UDC2 Command register to set the status of the relevant endpoint to Disable (EP_Disable). 2. In order to stop the Master Write transfer, set 1 (Abort) to the mw_abort bit of DMAC Setting register. 3. In order to confirm the transfer is aborted, check the <mw_enable> of DMAC Setting register was disabled to 0. Subsequent operations should not be made while the <mw_enable> is 1. (Information on the address where the transfer ended when aborted can be confirmed with Master Write Current Address and Master Write AHB Address registers.) 4. In order to initialize the Master Write transfer block, set 1 (Reset) to the mw_reset bit of DMAC Setting register. 5. Use Command register (EP_FIFO_Clear) to initialize the FIFO for the relevant endpoint. 6. Use UDC2 Command register to set the status of the relevant endpoint to Enable (EP_Enable). TMPA910CRA- 536 2010-06-02 TMPA910CRA 3.16.2.10 USB Power Management Control In USB, operations related to power management including detection of USB bus power supply, suspending and resuming are also prescribed in addition to normal packet transfers. This section discusses about how to control those operations. Below is a connection diagram of signals related to power management control. Note 1: Be sure to see the USB 2.0 Specification for details of operations. UDC2AB PHYRESET USB DP/DM USB INTS [21] WAKEUP_X PHYSUSPEND_X The WAKEUP_X signal 2.0 is not connecteted in this LSI. PHY CLK_U UTMI UDC2 suspend_x UTMI: USB 2.0 Transceiver Macrocell Interface Figure 3.16.12 Connection diagram of control signals TMPA910CRA- 537 2010-06-02 TMPA910CRA 3.16.2.11 USB Bus Power Detecting Sequence (1) Connect This section describes the sequence when detecting the power supply. After detecting the bus power from the USB host (VBUS), initialize UDC2AB and UDC2 with the following procedures: 1. Use the pw_resetb bit of Power Detect Control register to make software reset. (The pw_resetb bit is not automatically released and should be cleared by software.) 2. Make an access to UDC2AB and UDC2 registers to make necessary initial settings. 3. Use UDC2 Command register to issue the USB Ready command. UDC2 notifies the USB host of the connection via PHY. This condition enables UDC2 to accept USB_RESET from the USB host. 4. Once USB_RESET from the USB host is detected, UDC2 initializes the registers inside UDC2 and enumeration with the USB host becomes available. When USB_RESET is detected, the int_usb_reset/int_usb_reset_end interrupt occurs. Note: While UDC2AB originally has the function to assert the int_powerdetect interrupt when VBUS is detected, it is not supported for this LSI. UDPWCTL<pw_detect> always indicates 0. (2) Disconnect When the USB bus power is disconnected, UDC2AB makes notification by an external interrupt. Since master transfers will not automatically stop in such circumstances, you need to make an abort process. Then use the pw_resetb bit of Power Detect Control register to make software reset. In case the system employs the control to stop CLK_H (AHB end) while USB is suspended, no interrupt will be notified even if the power is disconnected while CLK_H is stopped. In such cases, resuming of CLK_H is required using the WAKEUP_X output signal. See section 3.16.2.13 "(4) Signal operations when suspended and resumed (disconnected)" for more information. TMPA910CRA- 538 2010-06-02 TMPA910CRA 3.16.2.12 USB_RESET USB_RESET may be received not only when the USB host is connected but also at any timing. UDC2AB asserts the int_usb_reset/int_usb_reset_end interrupt when UDC2 has received USB_RESET and returns to the default state. At this time, master transfers will not automatically stop. Use the abort function to end the transfers. Values are initialized by USB_RESET for some registers of UDC2, while they are retained for other registers (refer to the section of UDC2). Resetting of UDC2 registers when USB_RESET is recognized should be made after the int_usb_reset_end interrupt has occurred. This is because UDC2 initializes UDC2 registers at the time it deasserts the usb_reset signal. TMPA910CRA- 539 2010-06-02 TMPA910CRA 3.16.2.13 Suspend/Resume (1) Shift to the suspended state UDC2AB makes notification of detecting the suspended state of UDC2 by the int_suspend_resume interrupt and the suspend_x bit of Power Detect Control register. Since master transfers will not automatically stop in this circumstance, you should use the aborting function of each master transfer to make forcible termination if needed. In case PHY needs to be suspended (clock stop) after the necessary processes finished by software, you can set the phy_suspend bit of Power Detect Control register to make UDC2AB assert PHYSUSPEND_X which will put PHY in suspended state. (2) Resuming from suspended state UDC2AB makes notification of detecting the resuming state from the USB host by the int_suspend_resume interrupt and the suspend_x bit of Power Detect Control register. (In case the wakeup_en bit of Power Control register is set to be enabled when CLK_H is stopped, notification is made by the WAKEUP_X output signal.) Note: While UDC2AB originally has the function to assert the Wakeup signal, it is not supported for this LSI. Since the suspend signal to PHY (PHYSUSPEND_X) is automatically deasserted when resuming, controlling by software is not necessary unlike the case of suspending. When resuming is recognized, make settings again for restarting master transfers. (3) Remote wakeup from suspended state When suspended, (in case PHY is in the suspended state) clocks for UDC2AB and UDC2 supplied by PHY (CLK_U) are stopped. Setting the phy_remote_wkup bit of Power Detect Control register to 1 in this state will make UDC2AB assert udc2_wakeup to UDC2 while deasserting the PHYSUSPEND_X signal. When the clock (CLK_U) output from PHY resumes after a certain period and the clock is supplied, UDC2 will automatically start the resuming operation. TMPA910CRA- 540 2010-06-02 TMPA910CRA (4) Signal operations when suspended and resumed (disconnected) Based on the above descriptions, the signal operations when suspended and resumed (disconnected) are illustrated below. Refer to "Figure 3.16.13 Operation of suspend/resume signals (when CLK_H is stopped)", "Figure 3.16.14 Operation of suspend/disconnect signals (when CLK_H is stopped)" if CLK_H should be stopped when resuming (disconnecting) from the USB host. Refer to "Figure 3.16.15 Operation of suspend/resume signals (when CLK_H is operating)" if CLK_H should be not stopped. Refer to "Figure3.16.16 Operation of suspend/remote wakeup signals" for remote wakeup from UDC2AB. Source of asserting WAKEUP_X: Resume suspend_x wakeup_en WAKEUP_X int_suspend_resume interrupt int_powerdetect interrupt "L" PHYSUSPEND_X CLK_U CLK_H Figure 3.16.13 Operation of suspend/resume signals (when CLK_H is stopped) TMPA910CRA- 541 2010-06-02 TMPA910CRA Source of asserting WAKEUP_X = Disconnect int_suspend_resume interrupt int_powerdetect interrupt Figure 3.16.14 Operation of suspend/disconnect signals (when CLK_H is stopped) Signal operation of Figure 3.16.13 and Figure 3.16.14: c The int_suspend_resume interrupt occurs by detecting the suspended state on the USB bus. d By the int_suspend_resume interrupt, the interrupt source is cleared by software and the phy_suspend bit of Power Detect Control register is set to 1. e Setting the phy_suspend bit will assert the PHYSUSPEND_X output signal to 0 which will stop the supply of CLK_U. f After setting the wakeup_en bit of Power Detect Control register to 1 by software, CLK_H can be stopped. g By detecting Resume on the USB bus or disconnecting (VBUS disconnected), the WAKEUP_X output signal will be asserted to 0 asynchronously. h Supply of CLK_H is started by the WAKEUP_X output signal. With the supply of CLK_H, the int_suspend_resume or the int_powerdetect interrupts will occur. (If the rise of suspend_x is detected, the PHYSUSPEND_X output signal will be automatically deasserted.) i 2.5 s after the interrupt is asserted (time required for the signal to stabilize when VBUS is disconnected), check the pw_detect bit of the Power Detect Control register. Depending on the external interrupt, proceed to j-a: WAKEUP_X is asserted by Resume. proceed to j-b: WAKEUP_X is asserted by Disconnect. TMPA910CRA- 542 2010-06-02 TMPA910CRA <When Resumed> j-a Software clears the interrupt source and the wakeup_en bit to deassert the WAKEUP_X output signal. k-a Resumes from suspended state <When Disconnected> j-b Clears the phy_suspend bit to 0 by software and deasserts the PHYSUSPEND_X output signal. Also clears the interrupt source and the wakeup_en bit to deassert the WAKEUP_X output signal. k-b Sets the pw_resetb bit of Power Detect Control register and initializes UDC2AB. Note: While UDC2AB originally has the function to assert the Wakeup signal, it is not supported for this LSI. TMPA910CRA- 543 2010-06-02 TMPA910CRA Interrupt Figure 3.16.15 Operation of suspend/resume signals (when CLK_H is operating) c The int_suspend_resume interrupt occurs by detecting the suspended state on the USB bus. d By the int_suspend_resume interrupt, the interrupt source is cleared and the phy_suspend bit of Power Detect Control register is set to 1 by software. e Setting the phy_suspend bit will assert the PHYSUSPEND_X output signal which will stop the supply of CLK_U. f The int_suspend_resume interrupt occurs by detecting Resume on the USB bus. By detecting the rise of suspend_x, the PHYSUSPEND_X output signal will be deasserted to 1. g By the int_suspend_resume interrupt, the interrupt source is cleared by Software. h Deasserting the PHYSUSPEND_X output signal will resume the supply of CLK_U. TMPA910CRA- 544 2010-06-02 TMPA910CRA suspend_x wakeup_en int_suspend_resume Interrupt PHYSUSPEND_X phy_remote_wkup CLK_U CLK_H Figure 3.16.16 Operation of suspend/remote wakeup signals c The int_suspend_resume interrupt occurs by detecting the suspended state on the USB bus. d By the int_suspend_resume interrupt, the interrupt source is cleared and the phy_suspend bit of Power Detect Control register is set to 1 by software. e Setting the phy_suspend bit will assert the PHYSUSPEND_X output signal to 0 which will stop the supply of CLK_U. f When requesting remote wakeup, set the <phy_remote_wkup> bit of Power Detect Control register to 1. Setting the phy_remote_wkup bit will cause UDC2 to make a remote wakeup request on the USB bus. Also, suspend_x will be deasserted to 1 asynchronously. g Deasserting suspend_x will cause the int_suspend_resume interrupt to occur and the PHYSUSPEND_X output signal to be deasserted to 1. h Deasserting the PHYSUSPEND_X output signal will resume CLK_U. The phy_remote_wkup bit will be automatically cleared. i Clears the int_suspend_resume interrupt source. TMPA910CRA- 545 2010-06-02 TMPA910CRA 3.16.3 Overview of UDC2 UDC2 is a core which controls connection of USB functions to the Universal Serial Bus. UDC2 automatically processes the USB protocol and its PHY-end interface can be accessed via UTMI. UDC2 has the following functions and features: * Supports Universal Serial Bus Specification Rev. 2.0. * Supports both High-Speed (HS) and Full-Speed (FS) (Low-Speed is not supported). * Supports Chirp. * Processes USB protocol. * Detects SOF/USB_RESET/SUSPEND/RESUME. * Generates and checks packet IDs. * Generates and checks data synchronization bits (DATA0/DATA1/DATA2/MDATA). * Checks CRC5, generates and checks CRC16. * Supports PING. * Supports 4 transfer modes (Control/Interrupt/Bulk/Isochronous). * Supports 4 endPoint. * Supports Dual Packet Mode (except for endpoint 0). * Endpoints 1 to 3 can directly access FIFO (Endpoint-I/F). * Supports USB 2.0 Transceiver Macrocell Interface (UTMI) (16 bits @ 30 MHz). TMPA910CRA- 546 2010-06-02 TMPA910CRA 3.16.3.1 Internal Block Structure of UDC2 The following are the block structure and outline of each block of UDC2. AHB UDC2AB UDC2 PVCI Ctrl EP0 AHB Slave DMAC_W0 EPINT EPRX DMAC_R0 AHB Master IFM USB 2.0 PHY SIEC USB AHB Slave I/F AHB Master I/F EPTX Figure 3.16.17 Block diagram of UDC2 TMPA910CRA- 547 2010-06-02 TMPA910CRA (1) SIEC (Serial Interface Engine Control) block This block manages the protocol in USB. Its major functions are: * Checks and generates PIDs. * Checks and generates CRCs. * Checks device addresses. * Manages transfer speed (HS/FS). * Controls PHY (transfer speed (HS/FS), mode, etc.). * Generates test modes. (2) IFM block This block controls SIEC and endpoints. Its major functions are: * Writes the received data to the relevant endpoints when received an OUT-Token. * Reads the transmit data from the relevant endpoints when an IN-Token is received. * Controls and manages the status of UDC2.0. (3) PVCIIF block This block controls reading and writing between IFM and external register access bus (PVCI). PVCI bus accesses via UDC2AB. (4) EP0 block This block controls sending and receiving data in Control transfers. When sending or receiving data with DATA-Stage of Control transfers, you should access the FIFO in this block via PVCI-I/F. (5) EPx block This block controls sending and receiving data of EPx (x = 1, 2, 3). FIFO can be directly accessed via the Endpoint-I/F. The Endpoint-I/F can make burst transfers. Please note there are two endpoints; one for sending and another for receiving. Direction of endpoints (send/receive) will be fixed on a hardware basis. TMPA910CRA- 548 2010-06-02 TMPA910CRA 3.16.3.2 Specifications of Flags The UDC2 core outputs various events on USB as flags when they occur. This section discusses those flags. (1) USB_RESET Asserts "H" while receiving USB_RESET. Since UDC2 returns to the Default-State by receiving USB_RESET, the application also needs to return to the Default-State. In Full-Speed operation, UDC2 asserts this flag when SE0 on the USB bus was recognized for 2.5 s or longer. In High-Speed operation, the flag is asserted when SE0 was recognized for 3 ms or longer, after determining whether USB_RESET or suspended state. Then, after UDC2 has driven Chirp-K for about 1.5 ms the flag will be deasserted when either one of the following states was recognized: 1. Chirp from the host (K-J-K-J-K-J) was recognized. 2. 2 ms or longer has passed without recognizing Chirp from the host (K-J-K-J-K-J). Note: While the time when the host begins Chirp and the driving time of Chirp-K and Chirp-J depend on the host, asserting period of the USB_RESET flag is around 1.74 ms to 3.5 ms. (2) INT_SETUP In Control transfers, asserts "H" after receiving the Setup-Token. When this interrupt is recognized, the software should read the Setup-Data storage register (8 bytes) to make judgment of request. This interrupt will be deasserted by writing 1 into the relevant bit (bit 0) of INT register. INT register should be cleared at the point the interrupt was recognized. (3) INT_STATUS_NAK In Control transfers, when the host proceeds to the STATUS-Stage and transmits packets while UDC2 is processing the DATA-Stage (before issuing the "Setup_Fin" command), UDC2 will return "NAK" and asserts this flag to "H". When this interrupt is recognized, the software should issue the "Setup_Fin" command from the Command register to make the STATUS-Stage of UDC2 end. This interrupt will be deasserted by writing 1 into the relevant bit (bit 1) of INT register. INT register should be cleared at the point the interrupt was recognized. (4) INT_STATUS In Control transfers, asserts "H" after finishing the STATUS-Stage normally. This interrupt will be deasserted by writing 1 into the relevant bit (bit 2) of INT register. INT register should be cleared at the point the interrupt was recognized. (5) INT_EP0 In the DATA-Stage of Control transfers, asserts "H" when "ACK" was sent or received (when the transaction finished normally). This interrupt will be deasserted by writing 1 into the relevant bit (bit 5) of INT register. INT register should be cleared at the point the interrupt was recognized. TMPA910CRA- 549 2010-06-02 TMPA910CRA (6) INT_EP In endpoints other than Endpoint 0, asserts "H" when "ACK" was sent or received (when the transaction finished normally). In that case, which endpoint the transfer was made can be identified by checking INT_EP register. This interrupt will be deasserted by writing 1 into the relevant bit (bit 6) of INT register, or by writing 1 into all bits set in INT_EP register. INT register should be cleared at the point the interrupt was recognized. (7) INT_RX_ZERO "H" is asserted when Zero-Length data is received. In Control transfers, however, "H" is asserted only when Zero-Length data is received in the DATA-Stage. It will not be asserted when Zero-Length data is received in the STATUS-Stage. Which endpoint has received the data can be identified by reading the bits [11:8] of Command register or checking INT_RX_DATA0 register. This interrupt will be deasserted by writing 1 into the relevant bit (bit 3) of INT register, or by writing 1 into all bits set in INT_RX_DATA0 register. INT_RX_DATA0 register should be cleared at the point the interrupt was recognized. (8) INT_SOF Asserts "H" when SOF was received. This interrupt will be deasserted by writing 1 into the relevant bit (bit 4) of INT register. INT register should be cleared at the point the interrupt was recognized. SOF is a packet indicating the start of a frame ( frame). It is transmitted from the host to devices every 1 ms in the Full-Speed transfers, and every 125 s in the High-Speed transfers. (9) INT_NAK In endpoints other than Endpoint 0, asserts "H" when NAK is transmitted. In that case, which endpoint has transmitted the NAK can be identified by checking INT_NAK register. This interrupt will be deasserted by writing 1 into the relevant bit (bit 7) of INT register, or by writing 1 into all bits set in INT_NAK register. By default, this flag will not be asserted when NAK was transmitted. Therefore, you should write 0 into the relevant endpoint of INT_NAK_MASK register to release the mask in order to use this flag. TMPA910CRA- 550 2010-06-02 TMPA910CRA 3.16.3.3 Registers UDC2 has the following registers: * Device Status Address-State register Frame register USB-Testmode register Command register * Setup Data Storage bRequest-bmRequestType register wValue register wIndex register wLength register * Interrupt Control INT register INT_EP register INT_EP_MASK register INT_RX_DATA0 register INT_NAK register INT_NAK_MASK register * EP0 Control Status EP0_MaxPacketSize register EP0_Status register EP0_Datasize register EP0_FIFO register * EPx Control Status EPx_MaxPacketSize register EPx_Status register EPx_Datasize register EPx_FIFO register TMPA910CRA- 551 2010-06-02 TMPA910CRA Table 3.16.2 shows the register map of UDC2. Table 3.16.2 Register map UDC2 *2), *3) Register Name Address (base +) Description UD2ADR 0x0200 UDC2 Address-State Register UD2FRM 0x0204 UDC2 Frame Register UD2TMD 0x0208 UDC2 USB-Testmode Register UD2CMD 0x020C UDC2 Command Register UD2BRQ 0x0210 UDC2 bRequest-bmRequestType Register UD2WVL 0x0214 UDC2 wValue Register UD2WIDX 0x0218 UDC2 wIndex Register UD2WLGTH 0x021C UDC2 wLength Register UD2INT 0x0220 UDC2 INT Register UD2INTEP 0x0224 UDC2 INT_EP Register UD2INTEPMSK 0x0228 UDC2 INT_EP_MASK Register UD2INTRX0 0x022C UDC2 INT_RX_DATA0 Register UD2EP0MSZ 0x0230 UDC2 EP0_MaxPacketSize Register UD2EP0STS 0x0234 UDC2 EP0_Status Register UD2EP0DSZ 0x0238 UDC2 EP0_Datasize Register UD2EP0FIFO 0x023C UDC2 EP0_FIFO Register UD2EP1MSZ 0x0240 UDC2 EP1_MaxPacketSize Register UD2EP1STS 0x0244 UDC2 EP1_Status Register UD2EP1DSZ 0x0248 UDC2 EP1_Datasize Register UD2EP1FIFO 0x024C UDC2 EP1_FIFO Register UD2EP2MSZ 0x0250 UDC2 EP2_MaxPacketSize Register UD2EP2STS 0x0254 UDC2 EP2_Status Register UD2EP2DSZ 0x0258 UDC2 EP2_Datasize Register UD2EP2FIFO 0x025C UDC2 EP2_FIFO Register Reserved 0x0260 to 0x03FC UD2INTNAK 0x0330 UDC2 INT_NAK Register UD2INTNAKMSK 0x0334 UDC2 INT_NAK_MASK Register Reserved 0x0338 to 0x03FC TMPA910CRA- 552 2010-06-02 TMPA910CRA The following sections describe the registers in UDC2 in detail. The descriptions of each bit have the following meanings: (Example) EPx_Datasize (EPx_Datasize register) Address = (0xF440_0000) + (0x0000) Bit Bit Symbol (Note 1) Reset Type (Note 2) Value Description (Note 3) [31:11] - - Undefined Read as undefined. [10:0] size[10:0] RO 0y00000000000, Indicates the number of valid data bytes stored in EPx_FIFO. In the Dual Packet mode, the number of data bytes to be accessed first will be shown. (-)(-)(-)(-)(-)(-) (-)(-)(-)(-) Note 1: Bit Symbol Name of each bit. Those shown as "-" are reserved bits which cannot be written. 0 will be returned when read. Note 2: Register properties RO : Read only. Write is ignored. WO : Write only. "0" will be returned when read. R/W : Read/Write Note 3: Reset value "Reset Value" is the initial value for the bit after resetting (1 or 0). Initial values after "USB_ RESET" are shown in parentheses and those bits which will not be reset by "USB_RESET" are indicated with a hyphen. The following subsections describe each register in detail. TMPA910CRA- 553 2010-06-02 TMPA910CRA (1) Device Status Registers 1. UD2ADR (Address-State register) Address = (0xF440_0000) + (0x0200) Bit Bit [31:16] Type Symbol - - Reset Description Value Undefined Read as undefined. Write as zero. [15] stage_err RO 0y0 [14] ep_bi_mode R/W 0y0, (-) [13:12] cur_speed[1:0] RO 0y01,(Note1) [11] Suspend RO 0y0 [10] Configured R/W 0y0 [9] Addressed R/W 0y0 [8] Default R/W 0y0,(1) [7] - - Undefined Indicates whether Control transfers finished normally up to the STATUS-Stage. 0y0: Other than below conditions 0y1: Received the Setup-Token in DATA-Stage/STATUS-Stage or "STALL" transmission. Selects whether to use the endpoint bidirectionally as a driver. (Note 2) 0y0: Single direction 0y1: Dual direction Indicates the present transfer mode on the USB bus. 0y00: Reserved 0y01: Full-Speed 0y10: High-Speed 0y11: Reserved Indicates whether or not UDC2 is in suspended state. 0y0: Normal, 0y1: Suspended Sets the present device state of UDC2. 0y001:Default (to be set when the DeviceAddress=0 was specified by the Set_address request in Default/Address state (this will be set by the hardware when USB_RESET is received)) 0y010:Addressed (to be set when ConfigurationVallue = 0 was specified by the Set_configuration request after the Set_address request finished normally and in the Address/Configured state) 0y100:Configured (to be set when the Set_config request is received) Read as undefined. Write as zero. [6:0] dev_adr[6:0] R/W 0y0000000 Sets the device address assigned by the host. Note 1: The initial value of cur_speed[1:0] (bits [13:12]) after USB_RESET is "0y10" (high-Speed) if the Chirp sequencehas been sucessful, and "0y01" (Full-Speed) if it has failed. Note 2 : About TMPA910CRA, EP0: single direction / dual direction . EP1, EP2 and EP3: single direction. only [Description] a. <stage_err> Indicates whether Control transfers finished normally up to the STATUS-Stage. 1 will be set when the Setup-Token is received in DATA-Stage/STATUS-Stage or in the case of "STALL" transmission. When set, it will be cleared when the next Control transfer has been finished normally. 0y0: Other than above conditions 0y1: Received the Setup-Token in DATA-Stage/STATUS-Stage or "STALL" transmission. TMPA910CRA- 554 2010-06-02 TMPA910CRA b. <ep_bi_mode> Selects whether to use the endpoint bidirectionally as a driver. Setting this bit to 1 will enable an endpoint number to be used bidirectionally in USB communication. 0y0: Single direction 0y1: Dual direction c. <cur_speed[1:0]> Indicates the present transfer mode on the USB bus. 0y00: Reserved 0y01: Full-Speed 0y10: High-Speed 0y11: Reserved d. <suspend> Indicates whether or not UDC2 is in suspended state. 0y0: Normal 0y1: Suspended e. <configured>, <addressed>, <default> Set the present device state of UDC2. This should be set in accordance with the request received from the host. Please note that you should not set 1 to more than one bit. 0y001: default (to be set when the DeviceAddress = 0 was specified by the Set_address request in Default/Address state (this will be set by the hardware when USB_RESET is received)) 0y010: addressed (to be set when ConfigurationVallue = 0 was specified by the Set_configuration request after the Set_address request finished normally and in the Address/Configured state) 0y100: configured (to be set when the Set_config request is received) f. <dev_adr[6:0]> Sets the device address assigned by the host. The device address should be set after Set_address has finished normally (after STATUS-Stage finished normally). TMPA910CRA- 555 2010-06-02 TMPA910CRA 2. UD2FRM (Frame register) Address = (0xF440_0000) + (0x0204) Bit Bit Reset Type Symbol Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15] create_sof R/W 0y0 [14] - - Undefined Sets whether to generate the SOF flag internally when the SOF from the host is unavailable due to a bus error. 0y0: Generates no flag 0y1: Generates a flag Read as undefined. Write as zero. [13:12] f_status[1:0] RO 0y10, (-)(-) [11] - - Undefined Indicates the status of the frame number. 0y00: Before 0y01: Valid 0y10: Lost Read as undefined. Write as zero. [10:0] frame[10:0] RO 0y00000000000 Indicates the frame number when SOF is received. [Description] a. <create_sof> Sets whether to generate the SOF flag internally when the SOF from the host is unavailable due to a bus error. This should be set if you wish to synchronize frames by SOF in Isochronous transfers. If enabled, the internal frame time counter will operate and the SOF flag will be output even when the SOF-Token could not be received successfully. 0y0: Generates no flag 0y1: Generates a flag b. <f_status[1:0]> Indicates the status of the frame number. 0y00: Before: Will be set if the Micro SOF/SOF was not received when 1frame-time (HS:125 s/FS:1 ms) has passed after receiving the Micro SOF/SOF when Create_sof is enabled. In the Frame register, the frame number received in the last Micro SOF/SOF has been set. 0y01: Valid: Will be set when the Micro SOF/SOF was received. Indicates a valid frame number is set in the Frame register. 0y10: Lost: Indicates that the frame number maintained by the host is not synchronized with the value of Frame register. Accordingly, this will be set in the following cases: 1. When the system was reset or suspended 2. If the next Micro SOF/SOF was not received when 2 frame-time (HS: 125 x 2 us/FS: 1 x 2 ms) has passed after receiving the previous Micro SOF/SOF when Create_sof is enabled. However, since the same frame number of Micro SOF will be sent eight times in a row in High-Speed transfers, the frame number sent from the host may seem to be synchronized with the value of Frame register even in the Lost status. Please note, however, they are not actually synchronized when considering the frame number and the number of times that frame number was sent. Also note that transition to the Lost status only happens after the system was reset or when it is suspended if Create_sof is disabled. TMPA910CRA- 556 2010-06-02 TMPA910CRA c. <frame[10:0]> Indicates the frame number when SOF is received. This will be valid when f_status is "Valid". Should not be used if f_status is "Before" or "Lost" as correct values are not set. TMPA910CRA- 557 2010-06-02 TMPA910CRA 3. UD2TMD (USB-Testmode register) Address = (0xF440_0000) + (0x0208) Bit Bit [31:13] Type Symbol - - Reset Description Value Undefined Read as undefined. Write as zero. [12] packet RO 0y0 [11] se0_nak RO 0y0 [10] test_k RO 0y0 [9] test_j RO 0y0 [8] - - Undefined Indicates the test mode currently set. 0y0001: test_j 0y0010: test_k 0y0100: se0_nak 0y1000: test_packet Read as undefined. Write as zero. [7:0] t_sel[7:0] R/W 0x00 Sets the test mode. [Description] a. <packet>, <se0_nak>, <test_k>, <test_j>, Indicates the test mode currently set. 0y0001: test_j 0y0010: test_k 0y0100: se0_nak 0y1000: test_packet b. <t_sel[7:0]> Sets the test mode. Set the value of TestModeSelectors specified by Set_Feature. TMPA910CRA- 558 2010-06-02 TMPA910CRA 4. UD2CMD (Command register) Address = (0xF440_0000) + (0x020C) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15] int_toggle R/W 0y0 [14:12] - - Undefined Makes the DATA-PID toggle when Handshake is not received in Interrupt-IN transfers. 0y0: Do not toggle when not received 0y1: Toggle when not received as well Read as undefined. Write as zero. [11:8] rx_nullpkt_ep[3:0] RO 0y0000, (-)(-)(-)(-) Indicates the receiving endpoint when Zero-Length data is received. [7:4] ep[3:0] R/W 0y0000 Sets the endpoint where the command to be issued will be valid. [3:0] com[3:0] R/W 0y0000 Sets the command to be issued for the endpoint selected in ep[3:0]. 0x0: Reserved 0x1: Setup_Fin 0x2: Set_DATA0 0x4: EP_Stall 0x5: EP_Invalid 0x6: Reserved 0x7: EP_Disable 0x8: EP_Enable 0x9: All_EP_Invalid 0xA: USB_Ready 0xB: Setup_Received 0xC: EP_EOP 0xD: EP_FIFO_Clear 0xE: EP_TX_0DATA 0xF: Reserved [Description] a. <int_toggle> Makes the DATA-PID toggle when Handshake is not received in Interrupt-IN transfers. 0y0: Do not toggle when not received 0y1: Toggle when not received as well b. <rx_nullpkt_ep[3:0]> Indicates the receiving endpoint when Zero-Length data is received. When the "int_rx_zero" flag is asserted, read this bit to check to which endpoint it was asserted. Once Zero-Length data is received and the endpoint number is retained, the value of this register will be retained until Zero-Length data is received next time or hardware reset (reset_x = 0) is made. If there is more than one endpoint of OUT direction, this bit will be renewed each time Zero-Length data is received. In that case, INT_RX_DATA0 register can be used to identify which endpoint has received the data. c. <ep[3:0]> Sets the endpoint where the command to be issued will be valid. (Do not specify an endpoint not existing.) TMPA910CRA- 559 2010-06-02 TMPA910CRA d. <com[3:0]> Sets the command to be issued for the endpoint selected in ep[3:0]. 0x0: Reserved Not to be specified. (Should be issued only for EP0.) 0x1: Setup_Fin This is a command for setting the end of DATA-Stage in Control transfers. As UDC2 continues to send back "NAK" to the STATUS-Stage until this command is issued, the command should be issued when the DATA-Stage finishes or INT_STATUS_NAK was received. Note: "Setup_Fin" command after reading all received data during data stage of Control-WR. 0x2: Set_DATA0 0x3: EP_Reset (Can be issued to EPs except EP0. Should not be issued to EP0.) A command for clearing toggling of endpoints. While toggling is automatically updated by UDC2 in normal transfers, this command should be issued if it needs to be cleared by software. (Can be issued to any EP.) A command for clearing the data and status of endpoints. Issue this command when you want to reset an endpoint in such cases as setting endpoints of Set_Configuration and Set_Interface or resetting the endpoint by Clear_Feature. This command will reset the following 5 points: 1. Clear the bits 13-12 (toggle) of EP0/EPx_Status register to DATA0 2.Clear the bits 11-9 (status) of EP0/EPx_Status register to Ready 3.Clear the bit 12 (dset) of EP0/EPx_MaxPacketSize register and clear the EP0/EPx_Datasize register 4.Clear the bit 15 (tx_0data) of EP0/EPx_MaxPacketSize register 5.Clear the bit 15 (tx_0data) of EP0/EPx_MaxPacketSize register 0x4: EP_Stall 0x5: EP_Invalid UDC2 makes toggling control by hardware for every transfer. If this command is issued when a transfer of endpoints is in progress, toggling of the relevant endpoint will also be cleared which may cause the synchronization with the host be lost. As in the case of receiving requests as mentioned above, the command should be issued when it is possible to make synchronization with the host. (Can be issued to any EP.) A command for setting the status of endpoints to "Stall". Issue this command when you want to set the status of an endpoint to "Stall" in such cases as stalling an endpoint by Set_Feature. When this command is issued, "STALL" will be always sent back for the endpoint set. However, the Stall status of EP0 will be cleared when the Setup-Token is received. This command should not be issued for endpoints where Isochronous transfers are used, since transfers are made without Handshake in Isochronous transfers. Even if this command is issued for endpoints where Isochronous transfers are set (by t_type (bits[3:2]) of EPx_Status register), "STALL" will not be sent back. (Can be issued to EPs except EP0. Should not be issued to EP0.) A command for setting the status of endpoints to "Invalid". Please issue this command when disabling endpoints that will not be used when using Set_Config or Set_Interface to set endpoints. When this command is issued, the endpoints set will make no response. This command should not be issued while transfers of each endpoint are in progress. TMPA910CRA- 560 2010-06-02 TMPA910CRA 0x6: Reserved 0x7: EP_Disable 0x8: EP_Enable 0x9: All_EP_Invalid 0xA: USB_Ready 0xB: Setup_Received 0xC: EP_EOP 0xD: EP_FIFO_Clear Not to be specified. (Can be issued to EPs except EP0. Should not be issued to EP0.) A command for making an endpoint disabled. When this command is issued, "NAK" will be always sent back from the endpoint set. This command should not be issued for endpoints where Isochronous transfers are used, since transfers are made without Handshake in Isochronous transfers. Even if this command is issued for endpoints where Isochronous transfers are set (by t_type (bits[3:2]) of EPx_Status register), "NAK" will not be sent back. (Can be issued to EPs except EP0. Should not be issued to EP0.) A command for making an endpoint enabled. Issue this command to cancel the disabled status set by "EP_Disable" command. (Setting for EP is invalid.) A command for setting the status of all endpoints other than EP0 to "Invalid". Issue this command when you want to apply the "EP_Invalid" command for all endpoints. Issue this command when processing Set_Configuration and Set_Interface like the "EP_Invalid" command. (Should be issued only for EP0.) A command for making connection with the USB cable. Issue this command at the point when communication with the host has become effective after confirming the connection with the cable. Pull-Up of DP will be made only after this command is issued, and the status of cable connection will be sent to the host. Please note that the device state of UDC2 (bits[10:8] of Address-state register) will be set to "Default" when this command was issued. (Should be issued only for EP0.) A command for informing UDC2 that the SETUP-Stage of a Control transfer was recognized. Issue this command after accepting the INT_SETUP interrupt and the request code was recognized. As UDC2 continues to send back "NAK" to the DATA-Stage/STATUS-Stage until this command is issued, the command should be issued at the end of the INT_SETUP interrupt processing routine. (Can be issued to any EP.) A command for informing UDC2 that the transmit data has been written. Issue this command when transmitting data with byte size smaller than the maximum transfer bytes (FIFO capacity of the endpoint or MaxPacketSize, whichever smaller). Issuing this command will set the Dataset flag and the data will be sent back to IN-Token from the host. It should not be used when setting Zero-Length data or data of MaxPacketSize. (Can be issued to any EP.) A command for clearing the data of an endpoint. The bit 12 (dset) of EPx_MaxPacketSize register and the EPx_Datasize register will be cleared at the same time. Issue this command when you want to clear the data currently stored in the FIFO before transmitting the data to the host and set the latest data, for instance in Interrupt transfers. If this command is issued while accessing the Endpoint-I/F, the FIFO of the endpoint will not be successfully cleared. When issuing this command, epx_val of Endpoint-I/F should be set to 0 before issuing. TMPA910CRA- 561 2010-06-02 TMPA910CRA 0xE: EP_TX_0DATA 0xF: Reserved (Can be issued to any EP.) A command for setting Zero-Length data to an endpoint. Issue this command when you want to transmit Zero-Length data. In the case of transmitting Zero-Length data in Bulk-IN transfers and others to indicate the final transfer, read EPx_Datasize register and confirm it is 0 (no data exists in the FIFO of EPx) before setting this command. In the case of writing data from Endpoint-I/F, set this command after the data was written and epx_val became 0. When this command was set, bit 15 (tx_0data) of EPx_MaxPacketSize register of the endpoint will be set. Ensure that this tx_0data becomes 0 before setting the next data. In Isochronous-IN transfers, Zero-Length data will be automatically transmitted to the IN-Token if no data is set in the FIFO of the endpoint. This command should not be issued in that case. Not to be specified. Settings for the following commands will be suspended when issued during a USB transfer, which will be executed after the USB transfer has finished. Suspension of the command will take place for each endpoint. 0x2: Set_DATA0 0x3: EP_Reset 0x4: EP_Stall 0x5: EP_Invalid 0x7: EP_Disable 0x8: EP_Enable 0x9: All_EP_Invalid 0xD: EP_FIFO_Clear 0xE: EP_TX_0DATA Therefore, when commands were issued successively for the same endpoint while a USB transfer is in progress, commands will be overwritten and only the one last issued will be valid. If you need to issue commands to an endpoint successively, poll Epx_Status/ Epx_Datasize register to confirm that the command has become valid before issuing next ones. Also, when making an access to the Endpoint-I/F immediately after clearing the FIFO using the EP_Reset/EP_FIFO_Clear command, poll EPx_Datasize register to confirm that the command has become valid before resuming the access to the Endpoint-I/F. For Endpoint 0, the following commands will be invalid until the Setup_Received command is issued after receiving the Setup-Token: 0x1: Setup_Fin 0x2: Set_DATA0 0x3: EP_Reset 0x4: EP_Stall 0xC: EP_EOP 0xD: EP_FIFO_Clear 0xE: EP_TX_0DATA TMPA910CRA- 562 2010-06-02 TMPA910CRA When the "EP_Stall" command was set to EPx, "Stall" will be set to the bits[11:9] (status) of EPx_Status register. When EP_Disable was set, 1 will be set to the bit 8 (disable) of EPx_Status register. When these two commands (EP_Stall and EP_Disable) were set to the same EPx and the status becomes "Stall" with disable = 1, "STALL" will be transmitted in the transfer. When the "EP_Invalid" command was set to EPx, "Invalid" will be set to the status of EPx_Status register. When the two commands (EP_Invalid and EP_Disable) were set to the same EPx and the status becomes "Invalid" with disable = 1, no response will be made in the transfer. When EPx_Status register has disable = 1 and EPx_MaxPacketSize register has bit 15 (tx_0data) = 1, Zero-Length data will be transmitted once in the transfer. After the Zero-Length data was successfully transferred, "NAK" will be transmitted. TMPA910CRA- 563 2010-06-02 TMPA910CRA (2) Setup-Data Storage Registers These registers overwrite the Setup-Data they received each time after receiving a Setup-Token. When the INT_SETUP interrupt has occurred, read these registers to determine the type of the request. 1. UD2BRQ (bRequest-bmRequestType register) Address = (0xF440_0000) + (0x0210) Bit Bit Reset Type Symbol Description Value [31:16] - - Undefined Read as undefined. [15:8] request[7:0] RO 0x00 [7] dir RO 0y0 Indicates the data of the second byte received with the Setup-Token (bRequest field). Indicates the data of the first byte received with the Setup-Token (bRequestType field). Direction of Control transfers [6:5] req_type[1:0] RO 0y00 Type of requests 0y0: Control-WR transfer [4:0] recipient[4:0] RO 0y00000 0y1: Control-RD transfer 0y00: Standard request 0y01: Class request 0y10: Vendor request 0y11: Reserved Requests are received by: 0y00000: Device 0y00001: Interface 0y00010: Endpoint 0y00011: etc. 0y00100-0y11111: Reserved [Description] a. <request[7:0]> Indicates the data of the second byte received with the Setup-Token (bRequest field). b. <dir> Indicates the data of the first byte received with the Setup-Token (bRequestType field). Direction of Control transfers 0y0: Control-WR transfer 0y1: Control-RD transfer c. <req_type[1:0]> Type of requests 0y00: Standard request 0y01: Class request 0y10: Vendor request 0y11: Reserved TMPA910CRA- 564 2010-06-02 TMPA910CRA d. <recipient[4:0]> Requests are received by: 0y00000: Device 0y00001: Interface 0y00010: Endpoint 0y00011: etc. 0y00100-0y11111: Reserved TMPA910CRA- 565 2010-06-02 TMPA910CRA 2. UD2WVL (wValue register) Address = (0xF440_0000) + (0x0214) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. [15:8] value[15:8] RO 0x00 [7:0] value[7:0] RO 0x00 Indicates the data of the fourth byte received with the Setup-Token (wValue (H) field). Indicates the data of the third byte received with the Setup-Token (wValue (L) field). [Description] a. <value[15:8]> Indicates the data of the fourth byte received with the Setup-Token (wValue (H) field). b. <value[7:0]> Indicates the data of the third byte received with the Setup-Token (wValue (L) field) TMPA910CRA- 566 2010-06-02 TMPA910CRA 3. UD2WIDX (wIndex register) Address = (0xF440_0000) + (0x0218) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. [15:8] index[15:8] RO 0x00 [7:0] index[7:0] RO 0x00 Indicates the data of the sixth byte received with the Setup-Token (wIndex (H) field). Indicates the data of the fifth byte received with the Setup-Token (wIndex (L) field). [Description] a. <index[15:8]> Indicates the data of the sixth byte received with the Setup-Token (wIndex (H) field). b. <index[7:0]> Indicates the data of the fifth byte received with the Setup-Token (wIndex (L) field). 4. UD2WLGTH (wLength register) Address = (0xF440_R0x021C) Bit Bit Type Symbol Reset Description Value [31:16] - - Undefined Read as undefined. [15:8] length[15:8] RO 0x00 [7:0] length[7:0] RO 0x00 Indicates the data of the eighth byte received with the Setup-Token (wLength (H) field). Indicates the data of the seventh byte received with the Setup-Token (wLength (L) field). [Description] a. <length[15:8]> Indicates the data of the eighth byte received with the Setup-Token (wLength (H) field). b. <length[7:0]> Indicates the data of the seventh byte received with the Setup-Token (wLength (L) field). TMPA910CRA- 567 2010-06-02 TMPA910CRA (3) Interrupt Control registers 1. UD2INT (INT register) Address = (0xF440_0000) + (0x0220) Bit Bit Reset Type Symbol Description Value [31:16] - - Undefined Read as undefined. Write as zero. [15] m_nak R/W 0y0 [14] m_ep R/W 0y0 [13] m_ep0 R/W 0y0 [12] m_sof R/W 0y0 [11] m_rx_data0 R/W 0y0 [10] m_status R/W 0y0 [9] m_status_nak R/W 0y0 [8] m_setup R/W 0y0 [7] i_nak R/W 0y0 Sets whether or not to output "i_nak (bit 7)" to the INT_NAK pin. 0y0: Enable (output) 0y1: Disable (no output) Sets whether or not to output "i_ep (bit 6)" to the INT_EP pin. 0y0: Enable (output) 0y1: Disable (no output) Sets whether or not to output "i_ep0 (bit 5)" to the INT_EP0 pin. 0y0: Enable (output) 0y1: Disable (no output) Sets whether or not to output "i_sof (bit 4)" to the INT_SOF pin. 0y0: Enable (output) 0y1: Disable (no output) Sets whether or not to output "i_rx_data0 (bit 3)" to the INT_RX_ZERO pin. 0y0: Enable (output) 0y1: Disable (no output) Sets whether or not to output "i_status (bit 2)" to the INT_STATUS pin. 0y0: Enable (output) 0y1: Disable (no output) Sets whether or not to output "i_status_nak(bit1)" to the INT_STATUS_NAK pin. 0y0: Enable (output) 0y1: Disable (no output) Sets whether or not to output "i_setup (bit 0)" to the INT_SETUP pin. 0y0: Enable (output) 0y1: Disable (no output) This will be set to 1 when NAK is transmitted by EPs except EP0. [6] i_ep R/W 0y0 [5] i_ep0 R/W 0y0 [4] i_sof R/W 0y0 [3] i_rx_data0 R/W 0y0 [2] i_status R/W 0y0 [1] i_status_nak R/W 0y0 [0] i_setup R/W 0y0 This will be set to 1 when transfers to EPs other than EP0 have successfully finished This will be set to 1 when the transfer to EP0 has successfully finished. This will be set to 1 when the SOF-token is received or after 1 frame-time was counted in the create_sof mode. This will be set to 1 when Zero-Length data is received. This will be set to 1 when the STATUS-Stage has successfully finished in Control transfers at EP0. This will be set to 1 when "NAK" is returned during packet reception of the STATUS-Stage during Control-RD transfer to EP0. This will be set to 1 when the Setup-Token was received in Control transfers at EP0. Note: The lower byte (bits 7-0) will be cleared by writing 1 to the relevant bits. [Description] a. <m_nak> Sets whether or not to output "i_nak (bit 7)" to the INT_NAK pin. 0y0: Enable (output) 0y1: Disable (no output) b. <m_ep> Sets whether or not to output "i_ep (bit 6)" to the INT_EP pin. 0y0: Enable (output) 0y1: Disable (no output) TMPA910CRA- 568 2010-06-02 TMPA910CRA c. <m_ep0> 0y0: Enable (output) 0y1: Disable (no output) d. <m_sof> Sets whether or not to output "i_sof (bit 4)" to the INT_SOF pin. 0y0: Enable (output) 0y1: Disable (no output) e. <m_rx_data0> Sets whether or not to output "i_rx_data0 (bit 3)" to the INT_RX_ZERO pin. 0y0: Enable (output) 0y1: Disable (no output) f. < m_status> Sets whether or not to output "i_status (bit 2)" to the INT_STATUS pin. 0y0: Enable (output) 0y1: Disable (no output) g. <m_status_nak> Sets whether or not to output "i_status_nak(bit1)" to the INT_STATUS_NAK pin. 0y0: Enable (output) 0y1: Disable (no output) h. <m_setup> Sets whether or not to output "i_setup (bit 0)" to the INT_SETUP pin. 0y0: Enable (output) 0y1: Disable (no output) i. <i_nak> This will be set to 1 when NAK is transmitted by EPs except EP0. (EPs to which you wish to output the INT_NAK flag can be selected using INT_NAK_MASK register). Writing 1 to this bit will make each bit of INT_NAK register cleared to 0. j. <i_ep> This will be set to 1 when transfers to EPs other than EP0 have successfully finished (EPs to which you wish to output the flag can be selected using INT_EP_MASK register). Writing 1 to this bit will make each bit of INT_EP register cleared to 0. TMPA910CRA- 569 2010-06-02 TMPA910CRA k. < i_ep0> This will be set to 1 when the transfer to EP0 has successfully finished. l. < i_sof> This will be set to 1 when the SOF-token is received or after 1 frame-time was counted in the create_sof mode. m. <i_rx_data0> This will be set to 1 when Zero-Length data is received. (EPs to which you wish to output the flag can be selected using INT_EP_MASK register). Writing 1 to this bit will make each bit of INT_RX_DATA0 register cleared to 0. This will not be set to 1 when Zero-Length data is received in the STATUS-Stage of Control-RD transfers. n. <i_status> This will be set to 1 when the STATUS-Stage has successfully finished in Control transfers at EP0. (This will be set to 1 when Zero-Length data is received in the STATUS-Stage and successfully finished in Control-RD transfers, and when Zero-Length data is transmitted in the STATUS-Stage and successfully finished in Control-WR transfers.) o. <i_status_nak> This will be set to 1 when the packet of STATUS-Stage is received in the Control-RD transfers at EP0. When this bit was set which means the DATA-Stage has finished, set the "Setup-Fin" command by the Command register to make the stage of UDC2 proceed to the STATUS-Stage. When receiving the data having the size of an integral multiple of MaxPacketSize (64 bytes: High-Speed) in the DATA-Stage of Control-WR transfers, Zero-Length data may be received to indicate the end of the DATA-Stage. After that, as the end of the DATA-Stage can be recognized by this i_status_nak when receiving the In-token in the STATUS-Stage, make UDC2 proceed to the STATUS-Stage. p. <i_status_nak> This will be set to 1 when the Setup-Token was received in Control transfers at EP0. TMPA910CRA- 570 2010-06-02 TMPA910CRA 2. UD2INTEP (INT_EP register) Address = (0xF440_0000) + (0x0224) Bit Bit Type Symbol Description Value - Undefined [15] Reserved R/W 0y0 [14] Reserved R/W 0y0 [13] Reserved R/W 0y0 [12] Reserved R/W 0y0 [11] Reserved R/W 0y0 [10] Reserved R/W 0y0 [9] Reserved R/W 0y0 [8] Reserved R/W 0y0 [7] Reserved R/W 0y0 [6] Reserved R/W 0y0 [5] Reserved R/W 0y0 [4] Reserved R/W 0y0 [3] i_ep3 R/W 0y0 [2] i_ep2 R/W 0y0 [1] i_ep1 R/W 0y0 [0] - - Undefined [31:16] - Reset Read as undefined. Write as zero. Flags to indicate the transmitting/receiving status of EPs (except for EP0) 0y0: No data transmitted/received 0y1: Some data transmitted/received Read as undefined. Write as zero. Note: Will be cleared by writing 1 to the relevant bits. [Description] a. <i_ep[3:1]> Flags to indicate the transmitting/receiving status of EPs (except for EP0) The relevant bit will be set to 1 when the transfer to EPs other than EP0 has successfully finished. (EPs to which you wish to output the int_ep flag can be selected using INT_EP_MASK register.) 0y0: No data transmitted/received 0y1: Some data transmitted/received TMPA910CRA- 571 2010-06-02 TMPA910CRA 3. UD2INTEPMSK (INT_EP_MASK register) Address = (0xF440_0000) + (0x0228) Bit Bit Symbol Type Reset Description Value [31:16] [15] - Reserved - R/W [14] Reserved R/W 0y0 [13] Reserved R/W 0y0 [12] Reserved R/W 0y0 [11] Reserved R/W 0y0 [10] Reserved R/W 0y0 [9] Reserved R/W 0y0 [8] Reserved R/W 0y0 [7] Reserved R/W 0y0 [6] Reserved R/W 0y0 [5] Reserved R/W 0y0 [4] Reserved R/W 0y0 [3] m_ep3 R/W 0y0 [2] m_ep2 R/W 0y0 [1] m_ep1 R/W 0y0 [0] m_ep0 R/W 0y0 Undefined 0y0 Read as undefined. Write as zero. Mask control of flag output 0y0: Enable (output) 0y1: Disable (no output) Note: Will be cleared by writing 1 to the relevant bits. [Description] a. <m_ep[3:0]> Mask control of flag output Sets whether or not to output flags of INT_EP and INT_RX_DATA0 registers to the int_ep pin and the int_rx_zero pin respectively. When an EP is masked, each bit of INT_EP register will be set when the transfer of the relevant EP has successfully finished, but the int_ep pin will not be asserted. Similarly, when an EP is masked, each bit of INT_RX_DATA0 register will be set when Zero-Length data is received at the relevant EP, but the int_rx_zero pin will not be asserted. However, bit 0 is only valid for INT_RX_DATA0 register. 0y0: Enable (output) 0y1: Disable (no output) TMPA910CRA- 572 2010-06-02 TMPA910CRA INT_EP_MASK_REG 15 14 13 12 11 INT_EP_REG 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 INT_REG m_ep i_ep INT_EP INT_EP_MASK_REG 15 14 13 12 11 INT_RX_DATA0_REG 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 INT_REG m_d0 i_d0 INT_RX_DATA0 TMPA910CRA- 573 2010-06-02 TMPA910CRA An example of using i_ep/INT_EP/INT_EP_MASK is provided below for Endpoints 1 to 3. 1. 2. When using Endpoint 1 and Endpoint 2 with DMA (Endpoint I/F) and using only Endpoint3 via PVCI-I/F After initialization, set 1 to the bits 1 and 2 of INT_EP_MASK register to mask them. Interrupt responses to EP3 will be identical whether bit 3 of INT_EP register or bit 6 of INT register is used. It may be better to use INT register alone in terms of efficiency since checking only one register will do. Use INT register for interrupt responses. INT bit 6: Used as the interrupt source of EP3. This bit is also used when clearing. bit Used as the mask of the interrupt source of EP3. 14: bit 1: Should be ignored. INT_EP bit 2: Should be ignored. bit 3: Should be ignored. INT_EP_MASK bit 1: Set 1 to mask the bit. bit 2: Set 1 to mask the bit. bit 3: Should be left as 0 without making any change. When you have more than one EPx to be controlled by PVCI-I/F in addition to EP0 The following descriptions are based on the assumption that EP2 and EP3 are controlled by PVCI-I/F, while EP1 uses DMA. After initialization, set 1 to INT_EP_MASK register of the EP to be used with DMA to mask it. When making interrupt responses for more than one EPs, be sure to use INT_EP register. Ignore i_ep of INT register and always enable m_ep as 0. Do not clear the source using i_ep of INT register. After the interrupt has occurred, you need to check INT and INT_EP registers to determine the source. When clearing the source, use each source bit of INT_EP interrupt to clear it. INT INT_EP bit 6: bit 14: bit 1: bit 2: bit 3: INT_EP_MASK bit 1: bit 2: bit 3: Should be ignored. Do not clear the source using this bit. Should be left as 0 without making any change. Should be ignored. Used as the interrupt source of EP2. This bit is also used when clearing. Used as the interrupt source of EP3. This bit is also used when clearing. Set 1 to mask the bit. Used as the mask of the interrupt source of EP2. Used as the mask of the interrupt source of EP3. TMPA910CRA- 574 2010-06-02 TMPA910CRA 4. UD2INTRX0 (INT_RX_DATA0 register) Address = (0xF440_0000) + (0x022C) Bit Bit Symbol Type Reset Description Value [31:16] [15] - Reserved - R/W [14] Reserved R/W 0y0 [13] Reserved R/W 0y0 [12] Reserved R/W 0y0 [11] Reserved R/W 0y0 [10] Reserved R/W 0y0 [9] Reserved R/W 0y0 [8] Reserved R/W 0y0 [7] Reserved R/W 0y0 [6] Reserved R/W 0y0 [5] Reserved R/W 0y0 [4] Reserved R/W 0y0 [3] rx_d0_ep3 R/W 0y0 [2] rx_d0_ep2 R/W 0y0 [1] rx_d0_ep1 R/W 0y0 [0] rx_d0_ep0 R/W 0y0 Undefined 0y0 Read as undefined. Write as zero. Flags for indicating Zero-Length data received at EP 0y0: No Zero-Length data received 0y1: Zero-Length data received Note: Will be cleared by writing 1 to the relevant bits. [Description] a. <rx_d0_ep[3:0]> Flags for indicating Zero-Length data received at EP The relevant bit will be set to 1 when EPs have received Zero-Length data. (EPs to which you wish to output the int_rx_zero flag can be selected using INT_EP_MASK register.) For bit 0 (Endpoint 0), it will be set to 1 only when Zero-Length data is received in the DATA-Stage while processing the request. Since it will not be set when Zero-Length data is received in the STATUS-Stage, use the int_status flag. 0y0: No Zero-Length data received 0y1: Zero-Length data received TMPA910CRA- 575 2010-06-02 TMPA910CRA 5. UD2INTNAK (INT_NAK register) Address = (0xF440_0000) + (0x0330) Bit Bit Reset Type Symbol Description Value [31:16] [15] - Reserved - R/W [14] Reserved R/W 0y0 [13] Reserved R/W 0y0 [12] Reserved R/W 0y0 [11] Reserved R/W 0y0 [10] Reserved R/W 0y0 [9] Reserved R/W 0y0 [8] Reserved R/W 0y0 [7] Reserved R/W 0y0 [6] Reserved R/W 0y0 [5] Reserved R/W 0y0 [4] Reserved R/W 0y0 [3] i_ep3 R/W 0y0 [2] i_ep2 R/W 0y0 [1] i_ep1 R/W 0y0 [0] - - Undefined Undefined 0y0 Read as undefined. Write as zero. Flags to indicate the status of transmitting NAK at EPs (except for EP0) 0y0: No NAK transmitted 0y1: NAK transmitted Read as undefined. Write as zero. Note: Will be cleared by writing 1 to the relevant bits. [Description] a. <i_ep[3:1]> Flags to indicate the status of transmitting NAK at EPs (except for EP0) The relevant bit will be set to 1 when NAK is transmitted by EPs other than EP0. (EPs to which you wish to output the INT_NAK flag can be selected using INT_NAK_MASK register.) 0y0: No NAK transmitted 0y1: NAK transmitted TMPA910CRA- 576 2010-06-02 TMPA910CRA 6. UD2INTNAKMSK (INT_NAK_MASK register) Address = (0xF440_0000) + (0x0334) Bit Bit Type Symbol Reset Description Value [31:16] [15] - Reserved - R/W [14] Reserved R/W 0y0 [13] Reserved R/W 0y0 [12] Reserved R/W 0y0 [11] Reserved R/W 0y0 [10] Reserved R/W 0y0 [9] Reserved R/W 0y0 [8] Reserved R/W 0y0 [7] Reserved R/W 0y0 [6] Reserved R/W 0y0 [5] Reserved R/W 0y0 [4] Reserved R/W 0y0 [3] m_ep3 R/W 0y0 [2] m_ep2 R/W 0y0 [1] m_ep1 R/W 0y0 [0] - - Undefined Undefined 0y0 Read as undefined. Write as zero. Mask control of flag output 0y0: Enable (output) 0y1: Disable (no output) Read as undefined. Write as zero. Note: Will be cleared by writing 1 to the relevant bits. [Description] a. <m_ep[3:1]> Mask control of flag output Sets whether or not to output flags of INT_NAK register to the int_nak pin respectively. When EPs are masked, each bit of INT_NAK register will be set when NAK is transmitted in the transfer of the relevant EP, but the int_nak pin will not be asserted. 0y0: Enable (output) 0y1: Disable (no output) TMPA910CRA- 577 2010-06-02 TMPA910CRA INT_NAK_MASK_REG 15 14 13 12 11 INT_NAK_REG 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT_REG m_nak i_nak INT_NAK TMPA910CRA- 578 2010-06-02 TMPA910CRA (4) EP0 Control/Status Registers 1. UD2EP0MSZ (EP0_MaxPacketSize register) Address = (0xF440_0000) + (0x0230) Bit Bit Symbol Reset Type Description Value [31:16] [15] - tx_0data - RO Undefined 0y0 [14:13] [12] - dset - R/W Undefined 0y0, (-) [11:7] [6:0] - max_pkt[6:0] - R/W Undefined 0y1000000, (-)(-)(-)(-)(-)(-)(-) Read as undefined. Write as zero. When the "EP_TX_0DATA" command is issued to EP0 by Command register, this bit will be set to 1 which will be cleared to 0 after the Zero-Length data has been transmitted. Read as undefined. Write as zero. Indicates the status of EP0_FIFO. It will be cleared to 0 when the Setup-Token is received. 0y0: No valid data exists 0y1: Valid data exists Read as undefined. Write as zero. Sets MaxPacketSize of EP0. [Description] a. <tx_0data> When the "EP_TX_0DATA" command is issued to EP0 by Command register, this bit will be set to 1 which will be cleared to 0 after the Zero-Length data has been transmitted. b. <dset> Indicates the status of EP0_FIFO. It will be cleared to 0 when the Setup-Token is received. 0y0: No valid data exists 0y1: Valid data exists c. <max_pkt[6:0]> Sets MaxPacketSize of EP0. TMPA910CRA- 579 2010-06-02 TMPA910CRA 2. UD2EP0STS (EP0_ Status register) Address = (0xF440_0000) + (0x0234) Bit Bit Reset Type Symbol Description Value [31:16] - - Undefined Read as undefined. [15] ep0_mask RO 0y0 [14] - - Undefined 0y0: Data can be written to EP0_FIFO. 0y1: No data can be written to EP0_FIFO. Read as undefined. Write as zero. [13:12] toggle[1:0] RO 0y00 [11:9] status[2:0] RO 0y000 [8:0] - - Undefined Indicates the present toggle value of EP0. 0y00: DATA0 0y01: DATA1 0y10: Reserved 0y11: Reserved Indicates the present status of EP0. It will be cleared to "Ready" when the Setup-Token is received. 0y000: Ready 0y001: Busy 0y010: Error 0y011: Stall 0y100-0y111: Reserved Read as undefined. [Description] a. <ep0_mask> Will be set to 1 after the Setup-Token is received. Will be cleared to 0 when the "Setup_Received" command is issued. No data will be written into the EP0_FIFO while this bit is 1. 0y0: Data can be written into EP0_FIFO 0y1: No data can be written into EP0_FIFO b. <toggle[1:0]> Indicates the present toggle value of EP0 0y00: DATA0 0y01: DATA1 0y10: Reserved 0y11: Reserved c. <status[2:0]> Indicates the present status of EP0. It will be cleared to "Ready" when the Setup-Token is received. 0y000: Ready (Indicates the status is normal) 0y001: Busy (To be set when returned "NAK" in the STATUS-Stage) 0y010: Error (To be set in case of CRC error in the received data, as well as when timeout has occurred after transmission of the data) 0y011: Stall (Returns "STALL" when data longer than the Length was requested in Control-RD transfers and the status will be set. It will be also set when "EP0-STALL" was issued by Command register.) 0y100-0y111: Reserved TMPA910CRA- 580 2010-06-02 TMPA910CRA 3. UD2EP0DSZ (EP0_Datasize register) Address = (0xF440_0000) + (0x0238) Bit [31:7] [6:0] Bit Type Symbol - size[6:0] - RO Reset Description Value Undefined 0y0000000, (-)(-)(-)(-)(-)(-)(-) Read as undefined. Indicates the number of valid data bytes stored in EP0_FIFO. It will be cleared to when the Setup-Token is received. [Description] a. <size[6:0]> Indicates the number of valid data bytes stored in EP0_FIFO. It will be cleared to when the Setup-Token is received. 4. UD2EP0FIFO (EP0_FIFO register) Address = (0xF440_0000) + (0x023C) Bit [31:16] [15:0] Bit Type Symbol - data[15:0] - R/W Reset Description Value Undefined Undefined Read as undefined. Write as zero. Used for accessing data from PVCI-I/F to EP0. [Description] a. <data[15:0]> Used for accessing data from PVCI-I/F to EP0. For the method of accessing this register, see section 3.16.3.5 "(1) Control-RD transfer", and section 3.16.3.5 "(3) Control-WR transfer (with DATA-Stage)." The data stored in this register will be cleared when the request is received (when the INT_SETUP interrupt is asserted). TMPA910CRA- 581 2010-06-02 TMPA910CRA (5) EP1 Control/Status Registers 1. UD2EP1MSZ (EP1_MaxPacketSize register) Address = (0xF440_0000) + (0x0240) Bit Bit Symbol Reset Type Description Value [31:16] [15] - tx_0data - RO Undefined 0y0 [14:13] [12] - dset - RO Undefined Note 1,Note 2 [11] [10:0] - max_pkt[10:0] - R/W Undefined 0y00000000000 (-)(-)(-)(-)(-)(-) (-)(-)(-)(-)(-) Read as undefined. Write as zero. When the "EP1_TX_0DATA" command is issued to EP1 by Command register or Zero-Length data has been set at Endpoint-I/F, this bit will be set to 1. It will be cleared to 0 after the Zero-Length data has been transmitted. Read as undefined. Write as zero. Indicates the status of EP1_FIFO. 0y0: No valid data exists 0y1: Valid data exists Read as undefined. Write as zero. Sets MaxPacketSize of EP1. Note: See 3.16.4.2 Appendix B About Setting an Odd Number of Bytes as MaxPacketSize for more information. Note 1: The initial value of dset (bit 12) after reset_x is 1 when the EPx is a transmit endpoint, while it is 0 when the EPx is a receive endpoint. Note 2: The initial value of dset (bit 12) after USB_RESET is 1 when the EPx is a transmit endpoint, while it is "Retain" when the EPx is a receive endpoint. Note 3: Since the register structure is identical for all EPs through EP1 and EP3, only EP1 is described here. Addresses of registers for EP2 and EP3 can be confirmed in the register map. [Description] a. <tx_0data> When the "EP1_TX_0DATA" command is issued to EP1 by Command register or Zero-Length data has been set at Endpoint-I/F, this bit will be set to 1. It will be cleared to 0 after the Zero-Length data has been transmitted. b. <dset> Indicates the status of EP1_FIFO. 0y0: No valid data exists 0y1: Valid data exists c. <max_pkt[10:0]> Sets MaxPacketSize of EP1. Set this when configuring the endpoint when Set_Configuration and Set_Interface are received. Set an even number for a transmit endpoint. On USB, when MaxPacketSize of a transmit endpoint is an odd number, set an even number to max_pkt and make the odd number of accesses to the endpoint. (For instance, set 1024 to max_pkt when the MaxPacketSize should be 1023 bytes.) Note: For details, refer to section 3.16.4.2 "Appendix B About Setting an Odd Number of Bytes as MaxPacketSize". TMPA910CRA- 582 2010-06-02 TMPA910CRA 2. UD2EP1STS (EP1_Status register) Address = (0xF440_0000) + (0x0244) Bit Bit Type Symbol - R/W Reset Description Value [31:16] [15] - pkt_mode [14] bus_sel R/W 0y0 [13:12] toggle[1:0] RO 0y00 [11:9] status[2:0] RO 0y111 [8] disable RO 0y0 [7] dir R/W 0y0 [6:4] - - Undefined [3:2] t_type[1:0] R/W 0y00 [1:0] num_mf[1:0] R/W 0y00 Undefined 0y0 Read as undefined. Write as zero. Select the packet mode of EP1. 0y0: Single mode 0y1: Dual mode Select the bus to access to the FIFO of EP1. 0y0: Common bus access 0y1: Direct access Indicates the present toggle value of EPx. 0y00: DATA0 0y01: DATA1 0y10: DATA2 0y11: MDATA Indicates the present status of EP1. By issuing EP_Reset from Command register, the status will be "Ready." 0y000: Ready 0y001: Reserved 0y010: Error 0y011: Stall 0y100-0y110: Reserved 0y111: Invalid Indicates whether transfers are allowed for EP1. 0y0: Allowed 0y1: Not Allowed Sets the direction of transfers for this endpoint. 0y0: OUT (Host-to-device) 0y1: IN (Device-to-host) Read as undefined. Write as zero. Sets the transfer mode for this endpoint. 0y00: Control 0y01: Isochronous 0y10: Bulk 0y11: Interrupt When the Isochronous transfer is selected, set how many times the transfer should be made in frames. 0y00: 1-transaction 0y01: 2-transaction 0y10: 3-transaction 0y11: Reserved Note 1: Setting for this register should be made when configuring the endpoint when Set_Configuration and Set_Interface are received. Note 2: Since the register structure is identical for EP1, EP2 and EP3, only EP1 is described here. Addresses of registers for EP2 and EP3 can be confirmed in the register map. Each EP depend on the produnct specification. For EP1 which is fixed for IN transfers, dir can be set to "1" only. For EP2 which is fixed for OUT transfers, dir can be set to "0" only. For EP3 which is fixed for IN transfers, dir can be set to "1" only. TMPA910CRA- 583 2010-06-02 TMPA910CRA [Description] a. <pkt_mode> Selects the packet mode of EP1. Selecting the Dual mode makes it possible to retain two pieces of packet data for the EPx. 0y0: Single mode 0y1: Dual mode b. <bus_sel> Select the bus to access to the FIFO of EP1. 0y0: Common bus access 0y1: Direct access c. <toggle[1:0]> Indicates the present toggle value of EPx. 0y00: DATA0 0y01: DATA1 0y10: DATA2 0y11: MDATA d. <status[2:0]> Indicates the present status of EP1. By issuing EP_Reset from Command register, the status will be "Ready." 0y000: Ready (Indicates the status is normal) 0y001: Reserved 0y010: Error (To be set in case a receive error occurred in the data packet, or when timeout has occurred after transmission. However, it will not be set when "Stall" or "Invalid" has been set.) 0y011: Stall (To be set when "EP-Stall" was issued by Command register.) 0y100-0y110: Reserved 0y111: Invalid (Indicates this endpoint is invalid) e. <disable> Indicates whether transfers are allowed for EP1. If "Not Allowed," "NAK" will be always returned for the Token sent to this endpoint. 0y0: Allowed 0y1: Not Allowed TMPA910CRA- 584 2010-06-02 TMPA910CRA f. <dir> Sets the direction of transfers for this endpoint. 0y0: OUT (Host-to-device) 0y1: IN (Device-to-host) Note 1: EP1 is fixed for IN transfers. Be sure to set to "1". Note 2: EP2 is fixed for OUT transfers. Be sure to set to "0". Note 3: EP3 is fixed for IN transfers. Be sure to set to "1". g. <t_type[1:0]> Sets the transfer mode for this endpoint. 0y00: Control 0y01: Isochronous 0y10: Bulk 0y11: Interrupt h. <num_mf[1:0]> When the Isochronous transfer is selected, set how many times the transfer should be made in frames. 0y00: 1-transaction 0y01: 2-transaction 0y10: 3-transaction 0y11: Reserved TMPA910CRA- 585 2010-06-02 TMPA910CRA 3. UD2EP1DSZ (EP1_Datasize register) Address = (0xF440_0000) + (0x0248) Bit [31:11] [10:0] Bit Type Symbol - size[10:0] - RO Reset Description Value Undefined 0y00000000000, (-)(-)(-)(-)(-)(-) (-)(-)(-)(-)(-) Read as undefined. Indicates the number of valid data bytes stored in EP1_FIFO. In the Dual Packet mode, the number of data bytes to be accessed first will be shown. Note: Since the register structure is identical for EP1, EP2 and EP3 only EP1 is described here. Addresses of registers for EP2 and EP3 can be confirmed in the register map. [Description] a. <size[10:0]> Indicates the number of valid data bytes stored in EP1_FIFO. In the Dual Packet mode, the number of data bytes to be accessed first will be shown. 4. UD2EP1FIFO (EP1_FIFO register) Address = (0xF440_0000) + (0x024C) Bit [31:16] [15:0] Bit Type Symbol - data[15:0] - - Reset Description Value Undefined Undefined Read as undefined. Write as zero. Used for accessing data from PVCI-I/F to EPx. Note: Since the register structure is identical for EP1, EP2 and EP3, only EP1 is described here. Addresses of registers for EP2 and EP3 can be confirmed in the register map. [Description] a. <data[15:0]> Used for accessing data from PVCI-I/F to EPx. TMPA910CRA- 586 2010-06-02 TMPA910CRA 3.16.3.4 USB Device Response UDC2 initializes the inside of UDC2 and sets various registers when hardware reset is detected, USB_RESET is detected, and an enumeration response is made. This section discusses the operations of UDC2 in each status as well as how to control them externally. (1) When hardware reset is detected Be sure to reset hardware for UDC2 after the power-on operation. After the hardware reset, UDC2 initializes internal registers and all endpoints are in the invalid status, which means the device itself is "Disconnected." In order to make the status of UDC2 to "Default," issue the "USB_Ready"" command. Issuing this command will put UDC2 in the "Full-Speed" mode, enable the Pull-Up resistance of DP and notify the host of "Connect." In this status, only the USB_RESET signal is accepted from the host. (2) When USB_RESET is detected UDC2 initializes internal registers when Bus Reset (USB_RESET) is detected on the USB signal, putting the device in the "Default" status. In this status only Endpoint 0 gets "Ready" enabling enumeration with the host. The mode of UDC2 will be "HS-Chirp" and Chirp operation with the host will start. When Chirp from the host is normally received, the mode of UDC2 turns to High-Speed (HS) and subsequent transfers between the hosts will be made in the HS mode. If Chirp from the host is not received, subsequent transfers between the hosts will be made in the Full-Speed (FS) mode. The current transfer mode can be judged by reading the bits[13:12] of Address-state register. (3) When "Set_address" request is received By setting 0y010 to the bits[10:8] and the received address value to the bits[6:0] of Address-state register after receiving the "Set_address" request, UDC2 will be in the "Addressed" status. Setting for this register should be made after the Control transfer has successfully finished (after the STATUS-Stage has ended). Transfers to endpoints other than Endpoint 0 cannot be made in this status. TMPA910CRA- 587 2010-06-02 TMPA910CRA (4) When "Set_configuration" and "Set_interface" requests are received By setting 0y100 to the bits[10:8] of Address-state register after receiving the "Set_configuration" and "Set_interface" requests, UDC2 will be in the "Configured" status. In the "Configured" status, you can make transfers to the endpoint to which status settings have been made. In order to make the endpoint "Ready," the following settings should be made: * Set the maximum packet size to EPx_MaxPacketSize register * Set the transfer mode to EPx_Status register * Issue the EP_Reset command to Command register Endpoints will be available for transmitting and receiving data after these settings have been made. Figure 3.16.18 shows the "Device State Diagram". ! reset_x Disconnect (Invalid) ! reset_x "usb_ready" command write Default (FS) "USB_RESET" Detect Default (HS-Chirp) Chirp Detect ? OK NG Default (HS) Default (FS) Address assigned Address assigned Addressed (HS) Device configured Addressed (FS) Device deconfigured Configured (HS) Device deconfigured Device configured Configured (FS) Figure 3.16.18 Device state diagram TMPA910CRA- 588 2010-06-02 TMPA910CRA 3.16.3.5 Flow of Control in Transfers of Endpoints * Endpoint 0 Endpoint 0 supports Control transfers and used to make enumeration and other device control operations. Please note that Endpoint 0 can be used in the single packet mode only. Control transfers consist of the following three stages: SETUP-Stage DATA-Stage STATUS-Stage The types of transfer are categorized into the following major types: * Control-RD transfer * Control-WR transfer (without DATA-Stage) * Control-WR transfer (with DATA-Stage) UDC2 makes control of those three stages by hardware. Flows in each type of transfer are described below. (1) Control-RD transfer The flow of control in Control-RD transfers is shown below. SETUP-Stage Data flow on USB cable Host SETUP DATA-StageIN DATA0 (8 bytes) UDC2 IN ACK IN IN NAK NAK ACK DATA1 STATUS-Stage IN ACK OUT DATA0/1 ACK (Transmission data) (Transmission data) DATA1 (0 byte) INT_SETUP INT_STATUS INT_EP0 EP0_DATASET Register access INT-Reg. Read INT-Reg. Write Issue Setup_Received Command Setup-Data storage Register Read (8 bytes) Figure 3.16.19 INT-Reg. Read EP0_FIFO Write (MaxPacketSize byte) INT-Reg. Write EP0_FIFO Write (Last Data) INT-Reg. Read INT-Reg. Write INT-Reg. Read INT-Reg. Write Issue Setup_Fin Command Flow of control in Control-RD transfer The following description is based on the assumption that the bit 12 (dset) of EP0_MaxPacketSize register is set to "EP0_DATASET flag". TMPA910CRA- 589 2010-06-02 TMPA910CRA 1. SETUP-Stage UDC2 asserts the INT_SETUP flag when it has received the Setup-Token. This flag can be cleared by writing 1 into the bit 0 (i_setup) of INT register. In case flags are combined externally, read the INT register to confirm which flag is asserted and write "1" into the relevant bit. Then read Setup-Data storage registers (bRequest-bmRequestType, wValue, wIndex, and wLength registers) to determine the request. Finally, issue the "Setup_Received" command to inform UDC2 that the SETUP-Stage has finished. Since UDC2 does not allow writing data into the Endpoint0-FIFO before this command is issued, it will keep returning "NAK" to the IN-Token from the host until the command is issued. 2. DATA-Stage Write the data to be transmitted to the IN-Token into the Endpoint0-FIFO. If the byte size of the data to send is larger than the MaxPacketSize, divide them into groups of MaxPacketSize before writing. When the number of data reached the MaxPacketSize, the EP0_DATASET flag is asserted. When the data have been transmitted to the IN-Token from the host with no problem, UDC2 deasserts the EP0_DATASET flag and asserts INT_EP0. Any data remaining to be transmitted should be written into the Endpoint0-FIFO. If the size of the data to be written is smaller than the MaxPacketSize, issue the "EP_EOP" command to EP0 to inform UDC2 that it is a short packet. With this command, UDC2 recognizes the end of the packet and transmits the short packet data. Finally, issue the "Setup_Fin" command to inform UDC2 that the DATA-Stage has finished. 3. STATUS-Stage When the "Setup_Fin" command is issued, UDC2 will automatically make Handshake for the STATUS-Stage. When the STATUS-Stage finished with no problem, the INT_STATUS flag is asserted. When received a packet of STATUS-Stage from the host before the "Setup_Fin" command is issued, UDC2 will return "NAK" and asserts the INT_STATUS_NAK flag. Therefore, if this flag is asserted, be sure to issue the "Setup_Fin" command. TMPA910CRA- 590 2010-06-02 TMPA910CRA (2) Control-WR transfer (without DATA-Stage) The flow of control in Control-WR transfer (without DATA-Stage) is shown below. SETUP-Stage Data flow on USB cable Host SETUP DATA0 (8 bytes) STATUS-Stage IN IN ACK UDC2 NAK ACK DATA1 (0 byte) INT_SETUP INT_STATUS INT_EP0 EP0_DATASET Register access INT-Reg. Read INT-Reg. Write Setup-Data storage Register Read (8 bytes) INT-Reg. Read Issue Setup_Received Command INT-Reg. Write Issue Setup_Fin Command Figure 3.16.20 Flow of control in Control-WR transfers (without DATA-Stage) 1. SETUP-Stage To be processed in the same way as in the SETUP-Stage described in (1). 2. STATUS-Stage After issuing the "Setup_Received" command, make register accesses to UDC2 based on each request. Issue the "Setup_Fin" command when all the register accesses to UDC2 have finished. Subsequent processes are basically the same as the STATUS-Stage described in (1). UDC2 will keep on returning "NAK" until the "Setup_Fin" command is issued. Note: While register accesses required for each request are made to UDC2 between 'Issuing the "Setup_Received" command' and 'Issuing the "Setup_Fin" command', register accesses are needed after the end of STATUS-Stage in some cases such as Set Address request and Set Feature (TEST_MODE). Processes required for the standard requests are described in (5). TMPA910CRA- 591 2010-06-02 TMPA910CRA (3) Control-WR transfer (with DATA-Stage) The flow of control in Control-WR transfer (with DATA-Stage) is shown below. SETUP-Stage Data flow on USB cable Host SETUP DATA-Stage OUT DATA0 (8 bytes) UDC2 OUT DATA1 PING (Received data) ACK NAK OUT DATA1 PING (Received data) ACK STATUS-Stage NYET OUT DATA0/1 IN (Received data) ACK ACK DATA1 (0 byte) NYET INT_SETUP INT_STATUS INT_EP0 EP0_DATASET Register access INT-Reg. Read INT-Reg. Write Issue Setup_Received Command Setup-Data storage Register Read (8 bytes) Figure 3.16.21 1. INT-Reg. Read INT-Reg. Write INT-Reg. Read INT-Reg. Write EP0_FIFO Read EP0_FIFO Read INT-Reg. Read INT-Reg. Write Issue Setup_Fin Command Flow of control in Control-WR transfers (with DATA-Stage) SETUP-Stage To be processed in the same way as in the SETUP-Stage described in (1). 2. DATA-Stage When the data is received from the host with no problem, UDC2 asserts the EP0_DATASET flag and asserts the INT_EP0 flag. When this flag is asserted, read the data from EP0_FIFO after confirming the received data size in the EP0_Datasize register, or read the data from EP0_FIFO polling the EP0_DATASET flag. When the byte size of received data has been read, UDC2 deasserts the EP0_DATASET flag. 3. STATUS-Stage To be processed in the same way as in the STATUS-Stage described in (1). Note: Figure 3.16.21 shows the flow in High-Speed transfers. In Full-Speed transfers, the "PING" packet shown in the figure is not issued. Also, the "NYET" packet is replaced by the "ACK" packet. TMPA910CRA- 592 2010-06-02 TMPA910CRA (4) Example of using the INT_STATUS_NAK flag When processing requests without DATA-Stage, the INT_STATUS_NAK flag may get asserted by receiving STATUS-Stage from the host before clearing the INT_SETUP flag after it has been asserted, especially in High-Speed transfers. In case such multiple interrupts should be avoided as much as possible, you can use a method to mask the INT_STATUS_NAK flag for request having no DATA-Stage. In such case, basically set 1 to "m_status_nak" of INT register, while 0 should be set only when requests having DATA-Stage are received. (An example for Control-RD transfers is provided below.) SETUP-Stage Data flow on USB cable Host SETUP DATA-StageIN DATA0 (8 bytes) UDC2 IN ACK IN IN NAK NAK ACK STATUS-Stage OUT DATA1 DATA1 (0 byte) OUT DATA1 (0 byte) ACK NAK (Transmission data) INT_SETUP INT_STATUS _NAK INT_STATUS INT_EP0 EP0_DATASET Register access INT-Reg. Read INT-Reg. Write INT-Reg. Write Setup-Data storage Register Read (8 bytes) EP0_FIFO Write (MaxPacketSize byte) INT-Reg. Read Issue Setup_Received Command INT-Reg. Write EP0_FIFO Write (MaxPacketSize byte) INT-Reg. Read INT-Reg. Write INT-Reg. Read INT-Reg. Write Issue Setup_Fin Command Figure 3.16.22 Example of using the INT_STATUS_NAK flag in Control-RD transfers 1. SETUP-Stage After the INT_SETUP flag was asserted, clear the bit 0 (i_setup) of INT register. If the bit 1 (i_status_nak) is set to 1, it should be also cleared. Then, if the request was judged to have DATA-Stage by reading Setup-Data storage registers, set the bit 9 (m_status_nak) of INT register to 0. Then issue the "Setup_Received" command. 2. DATA-Stage STATUS-Stage When the INT_STATUS_NAK flag was asserted, the device should also proceed to the STATUS-Stage. Clear the bit 1 (i_status_nak) of INT register and then issue the "Setup_Fin" command. Also, set 1 to the bit 9 (m_status_nak) of INT register in order to get ready for subsequent transfers. TMPA910CRA- 593 2010-06-02 TMPA910CRA (5) Processing when standard requests are received Examples of making register accesses to UDC when standard requests are received are provided below. Descriptions of each request are basically provided for each state of the device (Default, Address, and Configured). For the information on register accesses common to each request, see (1), (2) and (3). You should note, however, descriptions provided below do not include the entire details of standard requests in USB 2.0. Since methods to access registers may vary depending on each user's usage, be sure to refer to the USB 2.0 specifications. You should also refer to the USB 2.0 specifications for "Recipient," "Descriptor Types," "Standard Feature Selectors," "Test Mode Selectors" and other terms appear in the descriptions below. y y y Standard requests for " (1) Control-RD transfers" y Get Status y Get Descriptor y Get Configuration y Get Interface y Synch Frame Standard requests for " (2) Control-WR transfer (without DATA-Stage) " y Clear Feature y Set Feature y Set Address y Set Configuration y Set Interface Standard requests for " (3) Control-WR transfer (with DATA-Stage)" y Set Descriptor Note 1: Descriptions with double underlines refer to register accessed to UDC2. Note 2: Writing accesses to Command register are described in the following manner for simplicity: (Example 1) When writing 0x0 to bits 7-4 (ep) and 0x4 to bits 3-0 (com) of Command register Issue the EP-Stall command to EP0 (Example 2) When writing the relevant endpoint to bits 7-4 (ep) and 0x5 to bits 3-0 (com) of Command register Issue the EP-Invalid command to the relevant endpoint TMPA910CRA- 594 2010-06-02 TMPA910CRA (a) Get Status request To this request, the status of the specified recipient is returned. BmRequestType 0y10000000 0y10000001 0y10000010 BRequest wValue GET_STATUS Zero wIndex Zero Interface Endpoint wLength Two Data Device, Interface, or Endpoint Status * Common to all states: If the Endpoint/Interface specified by wIndex does not exist, issue the EP-Stall command to EP0. * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state: y Recipient = Device : y Recipient = Interface y Recipient = Endpoint : : Write the information on the device (Figure 3.16.23) to EP0_FIFO register. Issue the EP-Stall command to EP0. If wIndex = 0 (EP0), write the information on Endpoint 0 (Figure 3.16.25) to EP0_FIFO register. If wIndex 0 (EPx), issue the EP-Stall command to EP0. * Configured state: y Recipient = Device : y Recipient = Interface : y Recipient = Endpoint : Write the information on the device (Figure 3.16.23) to EP0_FIFO register. If the interface specified by wIndex exists, write the information on the interface (Figure 3.16.24) to EP0_FIFO register. If the endpoint specified by wIndex exists, write the information on the relevant endpoint (Figure 3.16.25) to EP0_FIFO register. TMPA910CRA- 595 2010-06-02 TMPA910CRA D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 Remote Wakeup Self Powered D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 Figure 3.16.23 Information on the device to be returned by Get Status request SelfPowered (D0) : RemoteWakeup (D1) : 0 indicates the bus power while 1 indicates the self power. 0 indicates the remote wakeup function is disabled while 1 indicates it is enabled. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 Figure 3.16.24 Information on the interface to be returned by Get Status request * Please note that all bits are 0. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 Halt D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 Figure 3.16.25 Information on the endpoint to be returned by Get Status request * Halt (D0): If this bit is 1, it indicates that the relevant endpoint is in the "Halt" state. TMPA910CRA- 596 2010-06-02 TMPA910CRA (b) Clear Feature request To this request, particular functions are cleared or disabled. bmRequestType 0y00000000 0y00000001 0y00000010 bRequest wValue wIndex CLEAR_FEATURE Feature Selector Zero Interface Endpoint wLength Data Zero None * Common to all states: If Feature Selector (wValue) which cannot be cleared (disabled) or does not exist is specified, issue the EP-Stall command to EP0. If the Endpoint/Interface specified by wIndex does not exist, issue the EP-Stall command to EP0. * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state: x Recipient = Device x Recipient = Interface x Recipient = Endpoint : : : If wValue = 1, disable the DEVICE_REMOTE_WAKEUP function at the user's end. No register access to UDC2 is required. Issue the EP-Stall command to EP0. If wIndex 0 (EPx), issue the EP-Stall command to EP0. If wValue = 0 and wIndex = 0 (EP0), clear the Halt state of Endpoint 0 but no register access to UDC2 is required. * Configured state: x Recipient = Device : x Recipient = Interface x Recipient = Endpoint : : If wValue = 1, disable the DEVICE_REMOTE_WAKEUP function at the user's end. No register access to UDC2 is required. Issue the EP-Stall command to EP0. (Note) If wValue = 0 and wIndex 0 (EPx), issue the EP-Reset command to relevant endpoint. If wValue = 0 and wIndex = 0 (EP0), clear the Halt state of Endpoint 0 but no register access to UDC2 is required. Note: Endpoint 0 is to be stalled based on the interpretation of the USB 2.0 specifications that "No Feature Selector exists for Interface" here. For more information, see the USB Specification. TMPA910CRA- 597 2010-06-02 TMPA910CRA (c) Set Feature request To this request, particular functions are set or enabled. bmRequestType 0y00000000 0y00000001 0y00000010 bRequest wValue wIndex SET_FEATURE Feature Selector Zero Interface Endpoint Test Selector wLength Data Zero None * Common to all states: When Recipient = Device and wValue = 2 are specified in a device supporting High-Speed, write the value of Test Selector (upper byte of wIndex) to the bits7-0(t_sel) of USB-testmode register within 3 ms after the STATUS-Stage has ended. If, however, an invalid value (other than test_j, test_k, se0_nak, and test_packet) is specified for the Test Selector value, issue the EP-Stall command to EP0. Note: When using a vendor-specific Test Selector other than standard ones, the appropriate operation should be made. * If Feature Selector (wValue) which cannot be set (enabled) or does not exist is specified, issue the EP-Stall command to EP0. * If the Endpoint/Interface specified by the lower byte of wIndex does not exist, issue the EP-Stall command to EP0. * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications except for the above-mentioned TEST_MODE. * Address state: x Recipient = Device : If wValue = 1, enable the DEVICE_REMOTE_WAKEUP function at the user's end. No register access to UDC2 is required. x Recipient = Interface : Issue the EP-Stall command to EP0. x Recipient = Endpoint : If the lower byte of wIndex 0 (EPx), issue the EP-Stall command to EP0. If wValue = 0 and the lower byte of wIndex = 0 (EP0), make Endpoint 0 halt. (Note 2) * Configured state: x Recipient = Device : x Recipient = Interface x Recipient = Endpoint Note 1: : : If wValue = 1, enable the DEVICE_REMOTE_WAKEUP function at the user's end. No register access to UDC2 is required. Issue the EP-Stall command to EP0. (Note 1) If wValue = 0 and the lower byte of wIndex 0 (EPx), issue the EP-Stall command to the relevant endpoint. If wValue = 0 and the lower byte of wIndex = 0 (EP0), make Endpoint 0 halt. (Note 2) Endpoint 0 is to be stalled based on the interpretation of the USB specifications that "No Feature Selector exists for Interface" here. For more information, see the USB specifications. Note 2: USB 2.0 specifications include such description that "Performing the Halt function for Endpoint 0 is neither necessary nor recommended." Accordingly, it can be interpreted that it is not necessary to set UDC2 to the Stall state in this case. TMPA910CRA- 598 2010-06-02 TMPA910CRA In order to actually make Endpoint 0 be in the Halt state, users have to manage the "Halt state." Then, when a request is received in the "Halt state", such processes as to issue the EP-Stall command to EP0 in DATA-Stage/STATUS-Stage will be required. (Even if Endpoint0 is set to the Stall state, UDC2 will cancel the Stall state when the Setup-Token is received and will return "ACK.") As such, the process when SetFeature/ClearFeature is received for Endpoint 0 varies depending on user's usage. TMPA910CRA- 599 2010-06-02 TMPA910CRA (d) Set Address request To this request, device addresses are set. bmRequestType bRequest wValue wIndex wLength Data 0y00000000 SET_ADDRESS Device Address Zero Zero None For this request, make register accesses shown below within 2 ms after the STATUS-Stage has ended. (The device address should not be changed before the Setup_Fin command is issued.) * Default state: When wValue = 0 Keeps the default state. No register access to UDC2 is required. When wValue 0 Set wValue to bits 6-0 (dev_adr) and 0y010 to bits 10-8 (Device_State) of Address-State register. UDC2 will be put in the address state. * Address state: When wValue = 0 Set 0x00 to bits 6-0 (dev_adr) and 0y001 to bits 10-8 (Device_State) of Address-State register. UDC2 will be put in the Default state. When wValue 0 Set wValue to bits 6-0 (dev_adr) of Address-State register. UDC2 will be set to the new device address. * Configured state: Nothing is specified for the operation of devices by the USB 2.0 specification. TMPA910CRA- 600 2010-06-02 TMPA910CRA (e) Get Descriptor request To this request, the specified descriptor is returned. bmRequestType bRequest wValue wIndex wLength Data 0y10000000 GET_DESCRIPTOR Descriptor Type and Descriptor Index Zero or Language ID Descriptor Length Descriptor * Common to all states: * Write the descriptor information specified by wValue to EP0_FIFO register for the byte size specified by wLength. If the byte size to write is larger than the MaxPacketSize of Endpoint 0, you need to divide the data to write it several times (see (1) Control-RD transfer for more information). (If the length of the descriptor is longer than wLength, write the information for wLength bytes from the beginning of the descriptor. If the length of the descriptor is shorter than wLength, write the full information for the descriptor.) * If the descriptor specified by wValue is not supported by the user, issue the EP-Stall command to EP0. (f) Set Descriptor request To this request, the descriptor is updated or added. bmRequestType bRequest 0y00000000 SET_DESCRIPTOR wValue wIndex wLength Data Descriptor Type and Descriptor Index Language ID or zero Descriptor Length Descriptor * Common to all states: When this request is not supported, issue the EP-Stall command to EP0. * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state & Configured state: Read the information on the descriptor received by UDC2 from EP0_FIFO register. TMPA910CRA- 601 2010-06-02 TMPA910CRA (g) Get Configuration request To this request, the Configuration value of the current device is returned. bmRequestType bRequest wValue wIndex wLength Data 0y10000000 GET_CONFIGURATION Zero Zero One Configuration Value * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state: Write 0x00 to EP0_FIFO register [7:0]. As this is not configured, 0 should be returned. * Configured state: Write the current Configuration value to EP0_FIFO register [7:0]. Since this has been configured, values other than 0 should be returned. TMPA910CRA- 602 2010-06-02 TMPA910CRA (h) Set Configuration request To this request, device configuration is set. bmRequestType bRequest wValue wIndex wLength Data 0y00000000 SET_CONFIGURATION Configuration Value Zero Zero None * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state: When wValue = 0 x Keeps the address state. No register access to UDC2 is required. When wValue 0 and the wValue is a Configuration value matching the descriptor x Set 0y100 to bits 10-8 (Device_State) of Address-State register. <For endpoints to use> x Set MaxPacketSize to bit10-0(max_pkt) of EPx_MaxPacketSize register. x Set respective values to bit 15 (pkt_mode), bit 14 (bus_sel), bit 7 (dir), bits 3-2 (t_type), and bits 1-0 (num_mf) of EPx_Status register. x Issue the EP-Reset command to the relevant endpoints. When wValue 0 and the wValue is a Configuration value not matching the descriptor x Issue the EP-Stall command to EP0. * Configured state: When wValue = 0 x Set 0y010 to bits 10-8 (Device_State) of Address-State register. x Issue the All-EP-Invalid command. When wValue 0 and it is a Configuration value matching the descriptor <For endpoints to use> x Set MaxPacketSize to bits 10-0 (max_pkt) of EPx_MaxPacketSize register. x Set respective values to bit 15 (pkt_mode), bit 14 (bus_sel), bit 7 (dir), bits 3-2 (t_type), and bits 1-0 (num_mf) of EPx_Status register. x Issue the EP-Reset command to the relevant endpoints. <For endpoints to become unused> x Issue the EP-Invalid command to the relevant endpoints. When wValue 0 and the wValue is a Configuration value not matching the descriptor x Issue the EP-Stall command to EP0. TMPA910CRA- 603 2010-06-02 TMPA910CRA (i) Get Interface request To this request, the AlternateSetting value set by the specified interface is returned. bmRequestType bRequest wValue wIndex wLength 0y10000001 GET_INTERFACE Zero Interface One Data Alternate Setting * Common to all states: If the interface specified by wIndex does not exist, issue the EP-Stall command to EP0. * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state: Issue the EP-Stall command to EP0. * Configured state: Write the current Alternate Setting value of the interface specified by wIndex to EP0_FIFO register [7:0]. TMPA910CRA- 604 2010-06-02 TMPA910CRA (j) Set Interface request To this request, the Alternate Setting value of the specified interface is set. bmRequestType bRequest wValue wIndex wLength Data 0y00000001 SET_INTERFACE Alternate Setting Interface Zero None * Common to all states: If the interface specified by wIndex does not exist or the Alternate Setting specified by wValue does not exist, issue the EP-Stall command to EP0. * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state: Issue the EP-Stall command to EP0. * Configured state: <For the endpoints to use in Alternate Setting of the specified interface> x Set MaxPacketSize to bits 10-0 (max_pkt) of EPx_MaxPacketSize register. x Set respective values to bit 15 (pkt_mode), bit 14 (bus_sel), bit 7 (dir), bits 3-2 (t_type), and bits 1-0 (num_mf) of EPx_Status register. x Issue the EP-Reset command to the relevant endpoints. <For endpoints to become unused> x Issue the EP-Invalid command to the relevant endpoints. TMPA910CRA- 605 2010-06-02 TMPA910CRA (k) Synch Frame request To this request, the Synch Frame of the endpoint is returned. bmRequestType bRequest wValue wIndex wLength Data 0y10000010 SYNCH_FRAME Zero Endpoint Two Frame Number * Common to all states: If this request is not supported by the endpoint specified by wIndex, issue the EP-Stall command to EP0. * Default state: Nothing is specified for the operation of devices by the USB 2.0 specifications. * Address state: Issue the EP-Stall command to EP0. * Configured state: Write the Frame Number of the endpoint specified by wIndex to EP0_FIFO register. TMPA910CRA- 606 2010-06-02 TMPA910CRA * Endpoints other than Endpoint 0 Endpoints other than Endpoint 0 support Bulk (send/receive), Interrupt (send/receive), and Isochronous (send/receive) transfers and are used to transmit and receive data. They also support the Dual Packet mode which enables high-speed data communication. TMPA910CRA- 607 2010-06-02 TMPA910CRA 3.16.3.6 Suspend/Resume States UDC2 enters into a suspended state based on the signal condition from the host. It also returns from the suspended state by resuming operation by the host or UDC2. Shifting between the states is described below. (1) Shift to the suspended state Though the host issues SOF with given intervals (HS: 125 s, FS: 1 ms) in the normal state, it will stop issuing this SOF to the device when it tries to make the device suspended and the data on the USB signal line will be unchanged keeping the idle state. UDC2 is always monitoring the "line_state" from PHY and makes judgment of whether it is in the suspended state or USB_RESET when the idle state is detected for 3 ms or longer. If judged to be in the suspended state, it will assert "suspend_x" to "L" and enter in the suspended state. Please note accesses to registers will be unavailable while UDC2 is suspended, since supply of CLK from PHY will stop. (2) Resuming from suspended state Resuming from the suspended state can be made in two ways; by outputting a resuming state from the host and by way of remote wakeup from UDC2 (outputting a resuming state). Resuming process in each case is described below. (3) Resuming by an output from the host When a resuming state is output by the host, UDC2 deasserts "suspend_x" to "H" to declare resuming from the suspended state. (4) Resuming by way of remote wakeup from UDC2 The remote wakeup function may not be supported by some applications, and it needs to be permitted by the USB host at the time of bus enumeration. You should not assert "wakeup" unless permitted by the system. If permitted by the system, asserting the "wakeup" pin will make UDC2 output a resuming state to the host to start resuming. Please note that the clock supply from PHY is stopped when UDC2 is suspended, so you should keep asserting wakeup until it resumes. The remote wakeup should be operated after 2 ms or more has passed after suspend_x was asserted to "L". TMPA910CRA- 608 2010-06-02 TMPA910CRA 3.16.4 USB-Spec2.0 Device Controller Appendix 3.16.4.1 Appendix A System Power Management In USB, operations related to the enumeration and power control signals (DP/DM signals) for reset and suspend from the host are also prescribed, in addition to normal transfer operations. This Appendix provides information about the specifications of USB 2.0 PHY to be connected and clock control on the system level required for processes related to the DP/DM signals. For details of each process, please be sure to check the USB Specification Revision 2.0, PHY Specification, and the UTMI Specification Version 1.05. *1) Reset: The operation of the DP/DM signals for initializing the USB device (hereafter called "the device") from the USB host (hereafter called "the host"). After reset, enumeration is performed and then normal transfer operations such as Bulk transfers begin. Upon being connected, the device is always reset. The device also needs to support reset operation at any other arbitrary timing. During the reset period, Chirp operation is performed to determine whether the device operates in High-Speed (HS) or Full-Speed (FS) mode. *2) Suspend: If no bus activity on the DP/DM lines including SOF is initiated by the host for 3 ms or longer, the device needs to be put in the suspend mode to reduce power consumption. In this case, the device is required to perform certain operations such as stopping the clock. *3) Resume: The operation of the DP/DM signals for resuming normal operation from the suspend mode. Resume operation can be initiated either by the host or the device. Resume operation from the device is called "remote wakeup". TMPA910CRA- 609 2010-06-02 TMPA910CRA 1. Connect/Disconnect Operations (1) Connect Operation T1 T2 VBUS reset_x (UDC2-Input) USB_Read (UDC2-PVCI Access) xcvr_select (UDC2-Output) (H) term_select (UDC2-Output) Idle(FS) SE0 Figure 3.16.26 Connect operation timing * T0: Vbus detection When Vbus is detected, a system reset (reset_x input) should be applied to UDC2. xcvr_select is "H" and term_select is "L". * T1: Device connect (no later than 100 ms after T0) *4) Based on the USB 2.0 Specification. The device must enable DP pull-up no later than 100 ms after Vbus detection (T0) to notify the host of the connected state. Therefore, when Vbus is detected and the device is ready to communicate with the host, the system should access the Command register in UDC2 to set the USB_Ready command. When USB_Ready is accepted, UDC2 drives term_select "H". This makes USB 2.0 PHY enable DP pull-up. * T2: USB reset start (more than 100 ms after T1) (2) Disconnect Operation When a disconnected state is detected, it is recommended to apply a system reset to UDC2. TMPA910CRA- 610 2010-06-02 TMPA910CRA 2. Reset Operation *1 * The "reset" here refers to the "Reset Signaling" defined in the USB 2.0 Specification, not the system reset (reset_x) to UDC2. (1) When Operating in HS Mode after Reset time T0 T1 T2 Device Chirp-K DP/DM J T3 Host Chirp-KJ SE0 SE0 SOF usb_reset (UDC2-Output) xcvr_select (UDC2-Output) term_select (UDC2-Output) Figure 3.16.27 Reset operation timing (HS mode after Chirp) * T0: Reset start Upon recognizing SE0 from the host, UDC2 starts counting to recognize the reset. * T1: Reset recognition (more than 2.5 s after T0) When UDC2 detects SE0 for more than approximately 68 s after T0, it recognizes the reset from the host and drives usb_reset "H". At the same time, UTMI starts the device Chirp-K operation. * T2 : HS operation start (approximately 1.74 ms to 2 ms after T1) When the host supports HS mode, UDC2 detects Chirp-KJ from the host and drives usb_reset "L" within 1.74 ms to 2 ms after T1. (The period in which rsb_reset remains "H" depends on the host.) From this point, UDC2 operates in HS mode. * T3 : Reset end (more than 10 ms after T0) After completion of Chirp-KJ from the host, SE0 and the packet (SOF) is transmitted. This is the end of reset operation. The reset period from the host lasts a minimum of 10 ms. TMPA910CRA- 611 2010-06-02 TMPA910CRA (2) When Operating in FS Mode after Reset time T0 T1 T2 T3 T4 Device Chirp-K DP/DM J SE0 SE0 J usb_reset (UDC2-Output) xcvr_select (UDC2-Output) term_select (UDC2-Output) (H) Figure 3.16.28 Reset operation timing (FS mode after Chirp) * T0: Reset start Upon recognizing SE0 from the host, UDC2 starts counting to recognize the reset. * T1: Reset recognition (more than 2.5 s after T0) When UDC2 detects SE0 for more than approximately 68 s after T0, it recognizes the reset from the host and drives usb_reset "H". At the same time, UTMI starts the device Chirp-K operation. * T2: Device Chirp-K complete (more than 1.0 ms after T1) UDC2 completes the device Chirp-K operation approximately 1.5 ms after T1. * T3: FS operation start (1.0 ms to 2.5 ms after T2) When the host supports FS mode, the host chirp-KJ operation is not performed. If no host Chirp-KJ is detected in approximately 2 ms after T2, UDC2 initiates FS mode. At this point, usb_reset is driven "L". The period in which usb_reset remains "H" is approximately 3.5 ms. * T4: Reset end (more than 10 ms after T0) When SE0 from the host finishes and the device enters an idle state, it indicates the end of reset operation. The reset period from the host lasts a minimum of 10 ms. TMPA910CRA- 612 2010-06-02 TMPA910CRA (3) Notes on Reset Operation * Initialization of registers after reset When the reset from the host is completed (when usb_reset changes from "H" to "L"), all the internal registers of UDC2 are initialized. (For the initial value of each register, refer to the Section 3.16.3.3 Registers.) Note that registers that are set while usb_reset is "H" are also initialized. Therefore, the UDC2 registers should be set after the reset period is completed. * DMA transfer (Endpoint-I/F access) after reset When a reset from the host occurs during DMA transfer, the EPx_Status register is initialized and the bus access mode is set to "common bus access". Therefore, DMA transfer cannot be continued properly. When a reset occurs, the DMA controller must also be initialized. In the enumeration operation after reset, configure each endpoint and then initialize the endpoints by setting the EP_Reset command in the Command register. TMPA910CRA- 613 2010-06-02 TMPA910CRA 3. Suspend Operation *2 (1) Suspend Operation in HS Mode time T0 T1 T2 T3 T4 Last Activity SE0 DP/DM "J" State suspend_x (UDC2-Output) xcvr_select (UDC2-Output) term_select (UDC2-Output) Figure 3.16.29 Suspend operation timing in HS mode * T0: End of bus activity When the end of bus activity from the host (the end of packet) is detected, UDC2 starts counting to recognize suspend/reset. * T1: Transition to FS mode (3.0 ms to 3.125 ms after T0) When SE0 is detected for more than 3 ms after T0, UDC2 enters FS mode and drives xcvr_select and term_select "H". (This makes USB 2.0 PHY enable DP pull-up.) At this point, UDC2 cannot determine whether the host is initiating suspend or reset operation. * T2: Recognition of suspend (100 s to 875 s after T1) When the "J" state is detected on the DP/DM line in approximately 110 s after T1, UDC2 recognizes suspend and drives suspend_x "L". When the line state does not change to "J" and remains "SE0", UDC2 prepares for reset instead of suspend. In this case, refer to "2. Reset Operation". * T3: Remote wakeup start enable (5 ms after T0) Resume operation from the device (remote wakeup) is enabled 5 ms after T0. For details, refer to section "4.(2) Resume Operation by the Device (Remote Wakeup)". * T4: Transition to suspend state (10 ms after T0) The device must enter the suspend state no later than 10 ms after T0. Processes required of the device system to enter the suspend state, such as stopping the clock supply from USB 2.0 PHY, must be performed during this period. TMPA910CRA- 614 2010-06-02 TMPA910CRA (2) Suspend Operation in FS Mode time T0 T1 T2 T3 Last Activity DP/DM "J" State suspend_x (UDC2-Output) Figure 3.16.30 Suspend operation timing in FS mode * T0: End of bus activity When the end of bus activity from the host (the end of packet) is detected, UDC2 starts counting to recognize suspend. * T1: Recognition of suspend (3 ms after T0) When the "FS-J" is detected for more than 3 ms after T0, UDC2 recognizes suspend and drives suspend_x "L". * T2: Remote wakeup start enable (5 ms after T0) Resume operation from the device (remote wakeup) is enabled 5 ms after T0. For details, refer to "4.(2) Resume Operation by the Device (Remote Wakeup)" * T3: Transition to suspend state (10 ms after T0) The device must enter the suspend state no later than 10 ms after T0. Processes required of the device system to enter the suspend state, such as stopping the clock supply from USB 2.0 PHY, must be performed during this period. TMPA910CRA- 615 2010-06-02 TMPA910CRA (3) Notes on Suspend Operation * Clock control in suspend operation When the SuspendM input (UTMI) to USB 2.0 PHY is enabled at suspend, the clock supply from PHY to UDC2 is stopped. If UDC2 needs to use the clock from PHY after suspend_x becomes "L", supend_x should not be directly connected to PHY. The SuspendM input to PHY should be enabled after the system determines that the clock supply from PHY can be stopped. (When the clock input (30 MHz) to UDC2 is stopped, the internal registers of UDC2 cannot be accessed across PVCI-I/F and Endpoint-I/F.) * USB 2.0 PHY clock control The SuspendM input (UTMI) to USB 2.0 PHY should not be directly connected to the suspend_x output of UDC2. It should be controlled by the system. As explained earlier, suspend_x of UDC2 is activated by communication with the USB host. Therefore, if the USB host is not connected, suspend_x retains the hardware reset value of "H". At this time, if suspend_x and SuspendM are directly connected, the clock supply from USB 2.0 PHY is not stopped and system power consumption cannot be saved. * Internal registers during the suspend state During the suspend state, UDC2 retains the internal register values, the contents of FIFOs, and the state of each flag. These values and states are also retained after the suspend state is exited by resume operation. TMPA910CRA- 616 2010-06-02 TMPA910CRA 4. Resume Operation *3 (1) Resume Operation by the Host time T0 DP/DM T1 FS Idle ("J") T2 "K" State T3 SE0 suspend_x (UDC2-Output) SuspendM (PHY-Input) CLK (PHY-Output) CLK-Stop Figure 3.16.31 Resume operation timing by the host * T0: suspend_x output of UDC2 = "L" * T1: Start of host resume (No timing specifications) The host starts resume operation ("FS-K") at arbitrary timing to wake up the device from the suspend state. At this point, UDC2 sets suspend_x to "H". (Even if the clock input to UDC2 is stopped, suspend_x becomes "H".) After checking that suspend_x = "H", disable the SuspendM (UTMI) input to PHY to resume the clock output from USB 2.0 PHY. * T2: Resuming of clock supply from USB 2.0 PHY (Depends on the PHY specifications.) * T3: End of host resume (more than 20 ms after T1) The host resume operation ("FS-K") lasts for more than 20 ms, and completes after "SE0". UDC2 resumes operating at the same speed (HS/FS) as before the suspend state was entered. TMPA910CRA- 617 2010-06-02 TMPA910CRA (2) Resume Operation by the Device (Remote Wakeup) time T0 T1 T2 T3 T4 Device Resume DP/DM FS Idle ("J") Host Resume "K" State SE0 wakeup (UDC2-Input) suspend_x (UDC2-Output) SuspendM (PHY-Input) CLK (PHY-Output) CLK-Stop Figure 3.16.32 Remote wakeup operation timing * T0: suspend_x output of UDC2 = "L" * T1: Remote wakeup start enable (more than 2 ms after T0) The device can be brought out of the suspend state by using the wakeup input of UDC2. This is called remote wakeup. Note that the USB specification prohibits remote wakeup for 5 ms after start of the suspend state. The wakeup signal should be set to "H" a minimum of 2 ms after T0 as 3 ms have already elapsed from the start of suspend operation to T0. * T2: Wakeup input to UDC2 = "H" (after T1) Set the wakeup signal to "H". No timing requirements are specified for this operation. At this point, UDC2 sets suspend_x to "H". (Even if the clock input to UDC2 is stopped, suspend_x becomes "H".) Because UDC2 requires the clock input to start resume operation ("FS-K"), the SuspendM (UTMI) input to USB 2.0 PHY should be disabled. Then, keep wakeup at "H" until clock supply is resumed. * T3: Start of device resume (Depends on the PHY specifications.) When the clock input from PHY to UDC2 is resumed, UDC2 starts the device resume ("FS2-K"). The device resume period is approximately 2 ms. After confirming the device resume, the host starts the host resume operation. * T4: End of host resume (more than 20 ms after T3) The host resume operation ("FS-K") lasts for more than 20 ms, and completes after "SE0". UDC2 resumes operating at the same speed (HS/FS) as before the suspend state was entered. TMPA910CRA- 618 2010-06-02 TMPA910CRA (3) Notes on Resume Operation * Restriction on use of remote wakeup To support remote wakeup as the device system, the device must notify the host in the Configuration descriptor that the remote wakeup function is enabled. Even if remote wakeup is supported, it is disabled by default. Remote wakeup can only be used after it is enabled by a request from the host. Use of remote wakeup using the wakeup input is allowed only when these conditions are satisfied. When using this function, be sure to refer to 3.16.3.6 of the USB 2.0 Specification which offers detailed description. TMPA910CRA- 619 2010-06-02 TMPA910CRA 3.16.4.2 Appendix B About Setting an Odd Number of Bytes as MaxPacketSize 1. Setting an odd number in the EPx_MaxPacketSize register The USB specification allows MaxPacketSize (hereafter referred to as MPS) of each endpoint to be set as either an odd or even number of bytes for Isochronous and Interrupt transfers. (For Control and Bulk transfers, only an even number can be set.) In UDC2, MPS is set through max_pkt (bits[10:0]) of the EPx_MaxPacketSize register. The endpoint FIFOs of UDC2 only support even numbers of bytes. It is therefore recommended that MSP be set as an even number of bytes as a general rule. When using MPS by odd bytes, it is possible to make "max_pkt" into odd number. However, there are restrictions shown in Table 3.16.3 by the access method of a bus. In the case of endpoint direct access, an odd number cannot be set in max_pkt for a transmit endpoint. In this case, an even number should be set in max_pkt and write accesses to the endpoint FIFO should be controlled to implement an odd number of maximum write bytes. (For example, when MPS = 1023 bytes, max_pkt should be set to 1024 bytes.) Table 3.16.3 Restrictions on the setting of max_pkt Receive endpoint Common bus access (PVCI-I/F) An odd or even number can be set. Transmit endpoint An odd or even number can be set. Endpoint direct access (Endpoint-I/F) An odd or even number can be set. Only an even number can be set. Based on the above, the following pages describe how to set an odd number of bytes as MPS for each bus access method. TMPA910CRA- 620 2010-06-02 TMPA910CRA 2. Receive endpoint & common bus access Either an odd or even number of bytes can be set in max_pkt. The access method is the same for both cases. 3. Transmit endpoint & common bus access Either an odd or even number of bytes can be set in max_pkt. However, the following points must be observed in making common bus accesses for writing the maximum number of bytes with max_pkt = odd number. The following shows an example in which max_pkt = 5 and the maximum number of bytes (5 bytes) are to be written. * In the last access (5th byte), make sure that udc_be = 0y01. * Because it is access of MPS, Do not issue the EP-EOP command in the Command register. Figure 3.16.33 MPS write access with max_pkt = odd number (common bus access) TMPA910CRA- 621 2010-06-02 TMPA910CRA 4. Receive endpoint & endpoint direct access Either an odd or even number can be set in max_pkt. The access method is the same for both cases. 5. Transmit endpoint & endpoint direct access Only an even number of bytes can be set in max_pkt. To use an odd number of bytes as MPS for a transmit endpoint, the following settings are required. (Example: MPS = 1023) * Set max_pkt = 1024. * The maximum number of bytes that can be written to the endpoint is 1023 bytes. (It is not allowed to write the 1024th byte.) * "wMaxPacketSize" of the Endpoint descriptor to be managed by firmware should be set to 1023. (This is the value to be sent to the USB host by the Get Descriptor request.) The following shows an example in which max_pkt = 1024 and the maximum number of bytes (1023 bytes) are to be written. * In the last access (1023rd byte), make sure that epx_w_be = 0y01. Figure 3.16.34 MPS (odd number) write access with max_pkt = even number (endpoint direct access) TMPA910CRA- 622 2010-06-02 TMPA910CRA 3.16.4.3 Appendix C Isochronous Transfers In Isochronous transfers, the isochronism of data is critical and transfers occur per frame. Therefore, accesses to an endpoint (FIFO) using Isochronous transfers require a certain level of performance (speed). In UDC2, the access method to each endpoint can be selected from PVCI-I/F and Endpoint-I/F. The FIFO configuration can be selected from Single mode and Dual mode. However, for an endpoint using Isochronous transfers, it is recommended to use Endpoint-IF and Dual mode. 1. Accessing an endpoint using Isochronous transfers The maximum data payload size is 1024 bytes in HS mode and 1023 bytes in FS mode. To transfer 1024 bytes using Dual mode, 2048 bytes of RAM are required. Transfers are performed per microframe (125 s) in HS mode and per frame (1 ms) in FS mode. In HS mode, up to three transactions can be made in one microframe. (Information such as the payload size and the number of transactions must be set in the relevant UDC2 register. This information must also be managed by software as the Endpoint descriptor information to be sent to the host.) The following shows an example of endpoint access in which three transactions are made in one microframe in HS mode. Figure 3.16.35 shows OUT transfers and Figure 3.16.36 shows IN transfers. It is nexessary for there to be a space in FIFO before the 1 packet received HOST packet SOF OUT MDATA Max: 1024 bytes 2nd packet 3rd packet reception. received in empty FIFO (It is necessary for Read to complete 1st packet) OUT MDATA Max: 1024 bytes OUT DATA2 SOF Max: 1024 bytes DEVICE packet UDC2-OUTPUT int_sof UDC2-OUTPUT epx_dataset UDC2-Endpoint-I/F Read access 1st packet read 2nd packet read 3 packet read Figure 3.16.35 Isochronous OUT transfers in HS mode (3 transactions) TMPA910CRA- 623 2010-06-02 TMPA910CRA Each transmit data must be set before each IN token is received. HOST packet SOF IN DEVICE packet IN IN SOF DATA2 DATA1 DATA0 Max: 1024 bytes Max: 1024 bytes Max: 1024 bytes UDC2-OUTPUT int_sof UDC2-OUTPUT epx_dataset UDC2-Endpoint-I/F Write access 1st packet write 2nd packet write 3rd packet write Write of transmit data begins when FIFO has empty space. Figure 3.16.36 Isochronous IN transfers in HS mode (3 transactions) 2. Restrictions on command usage to Endpoint when using Isochronous transfers Compared to other transfers, Isochronous transfers have certain restrictions on handshake, toggle, the number of transactions in a frame, etc., limiting the types of commands that can be used. As a general rule, commands must not be issued to endpoints during Isochronous transfers. While a request is being processed, the EP_Reset or EP_Invalid command may be used as necessary. (When using PVCI-I/F as the endpoint access method, use the EP_EOP command.) (About this Appendix) * For descriptions concerning the USB Specification, be sure to check the USB Specification (revision 2.0). TMPA910CRA- 624 2010-06-02 TMPA910CRA 3.17 I2S (Inter-IC Sound) The TMPA910CRA contains a serial input/output circuit compliant with the I2S format. By connecting an external audio LSI, such as an AD converter or DA converter, the I2S interface can support the implementation of a digital audio system. The I2S of this LSI has the following characteristics: Table 3.17.1 I2S operation characteristics Transmit master mode Transmit slave mode Receive master mode Modes Receive slave mode Full-duplex master mode Full-duplex slave mode Clock through mode Channel Channel 0 Channel 1 Transmit/Receive Receive only Transmit only 2 (1) I S format-compliant Data formats (2) Stereo/monaural (3) MSB first/LSB first selectable (4) Left-justified supported (synchronous to WS, no delay) 2 I2SSCLK (I S external source clock input) Pins used (1) I2S0SCLK (clock input/output) (1) I2S1SCLK (clock input/output) (2) I2S0DATI (data input) (2) I2S1DATO (data output) (3) I2S0WS (word select input/output) (3) I2S1WS (word select input/output) (4) I2S0MCLK (master clock output) (4) I2S1MCLK (master clock output) (1) I2SWS can be set to 1/256, 1/384 or 1/512 of the master clock. Clocks (2) Either an external clock or the internal clock (X1) can be selected as the source clock. (3) The master clock can be generated by dividing down the source clock to 1, 1/2 or 1/4. FIFO buffer 2 x 8 words 2 x 8 words Data length 16 bits only 16 bits only Interrupts FIFO overflow interrupt FIFO overflow interrupt FIFO underflow interrupt FIFO underflow interrupt TMPA910CRA- 625 2010-06-02 TMPA910CRA 3.17.1 Block diagram Prescaler Source clock for Audio I2SSCLK I2S0MCLK for Receive circuit I2S1MCLK for Transmit circuit Divide setting value AHB AHB_IF and register I2S0SCLK / I2S0WS for Receive circuit FIFO_write_data I2S1SCK/ I2S1WS for Transmit circuit FIFO_read_data I2S1 transmit DMA request clear I2S1 transmit DMA request (burst) INTS[23] (I2SINT) I2S0 receive DMA request (burst) I2S0 receive DMA request clear Tx_BUS_IF Tx_FIFO Side-A Side-B Audio data I2S1DATO Rx_BUS_IF Rx_FIFO Side-A Side-B Audio data I2S0DATI TMPA910CRA- 626 2010-06-02 TMPA910CRA 3.17.2 Operation Mode Descriptions The I2S circuit contains two channels: Channel 0 (receive only) and Channel 1 (transmit only). Each channel can be controlled and operated independently. The following pages explain the I2S operation modes. TMPA910CRA- 627 2010-06-02 TMPA910CRA 3.17.2.1 Mode Example 1 (Receive Master, Transmit Master, <I2SSCLK> = 0, <MCLKSEL0> = 0, <MCLKSEL1> = 0, <COMMON> = 0, <I2SRx_MASTER> = 1, <I2STx_MASTER> = 1) Receive: The receive logic (Ch0) is set as a master. Receive operations are performed in synchronization with I2S0WS and I2S0SCLK that are output from the receive logic. Transmit: The transmit logic (Ch1) is set as a master. Transmit operations are performed in synchronization with I2S1WS and I2S1SCLK that are output from the transmit logic. I2SRMS<I2SRx_MASTER> 1 PL0 I2S0DATI I2SCOMMON<MCLKSEL0> 10 I2S0MCLK PL3 I2S0SCLK PL1 01 Receive logic (CH0) 0 Divider I2S0WS PL2 0 1 I2SRMS<I2SRx_MASTER I2SCOMMON <I2SSCLK> I2SSCLK PL4 1 0 Original clock from fOSCH I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> 1 0 I2S1DATO 0 I2SCOMMON<MCLKSEL1> 0 I2S1MCLK PM3 I2S1SCLK PM1 1 0 1 1 Transmit logic (CH1) PM0 Divider I2S1WS 1 PM2 0 I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> TMPA910CRA- 628 2010-06-02 TMPA910CRA 3.17.2.2 Mode Example 2 (Receive Slave, Transmit Slave, <I2SSCLK> = 1, <MCLKSEL0> = 1, <MCLKSEL1> = 1, <COMMON> = 0, <I2SRx_MASTER> = 0, <I2STx_MASTER> = 0) Receive: The receive logic (Ch0) is set as a slave. Receive operations are performed in synchronization with I2S0WS and I2S0SCLK that are output from another master. Transmit:The transmit logic (Ch1) is set as a slave. Transmit operations are performed in synchronization with I2S1WS and I2S1SCLK that are output from another master. I2SRMS<I2SRx_MASTER> 1 PL0 I2S0DATI I2SCOMMON<MCLKSEL0> 10 I2S0MCLK PL3 I2S0SCLK PL1 01 Receive logic (CH0) 0 Divider I2S0WS PL2 0 1 I2SRMS<I2SRx_MASTER> I2SCOMMON <I2SSCLK> I2SSCLK PL4 1 0 Original clock from fOSCH I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> 1 PM0 0 I2S1DATO 0 Divider I2SCOMMON<MCLKSEL1> 0 I2S1MCLK PM3 I2S1SCLK PM1 1 0 1 Transmit logic (CH1) I2S1WS 1 PM2 1 0 I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> TMPA910CRA- 629 2010-06-02 TMPA910CRA 3.17.2.3 Mode Example 3 (Full-duplex Master, <I2SSCLK> = 0, <MCLKSEL0> = 0, <COMMON> = 1, <I2SRx_MASTER> = 1) The receive logic (Ch0) is set as a master. Transmit and receive operations are performed with the transmit logic (Ch1) synchronized to I2S0WS and I2S0SCLK that are output from the receive logic. I2SRMS<I2SRx_MASTER> 1 PL0 I2S0DATI I2SCOMMON<MCLKSEL0> 10 I2S0MCLK PL3 I2S0SCLK PL1 01 Receive logic (CH0) 0 Divider I2S0WS PL2 0 1 I2SRMS<I2SRx_MASTER> I2SCOMMON <I2SSCLK> I2SSCLK PL4 1 0 Original clock from fOSCH I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> 1 PM0 0 0 Divider I2SCOMMON<MCLKSEL1> 0 I2S1MCLK PM3 I2S1SCLK PM1 1 0 1 Transmit logic (CH1) I2S1WS 1 I2S1DATO PM2 1 0 I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> TMPA910CRA- 630 2010-06-02 TMPA910CRA 3.17.2.4 Mode Example 4 (Full-Duplex Slave, <I2SSCLK> = 1, <MCLKSEL0> = 1, <COMMON> = 1, <I2SRx_MASTER> = 0) The receive logic (Ch0) is set as a slave. Transmit and receive operations are performed with the transmit logic (Ch1) synchronized to I2S0WS and I2S0SCLK that are output from another master. I2SRMS<I2SRx_MASTER> 1 PL0 I2S0DATI I2SCOMMON<MCLKSEL0> 10 I2S0MCLK PL3 I2S0SCLK PL1 01 Receive logic (CH0) 0 Divider I2S0WS PL2 0 1 I2SRMS<I2SRx_MASTER> I2SCOMMON <I2SSCLK> I2SSCLK PL4 1 0 Original clock from fOSCH I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> 1 PM0 0 I2S1DATO 0 Divider I2SCOMMON<MCLKSEL1> 0 I2S1MCLK PM3 I2S1SCLK PM1 1 0 1 Transmit logic (CH1) I2S1WS 1 PM2 1 0 I2SCOMMON<COMMON> I2STMS<I2STx_MASTER> TMPA910CRA- 631 2010-06-02 TMPA910CRA 3.17.3 Operation Description 3.17.3.1 I2S Output format (I2STCON<I2STx_DELAYOFF> = 0, Delay from WS) Request to DMAC 2x8word 8word 8word A B A B Write to FIFO A B 1word 2word 4 3 5 8 1 8 Read FIFO 2nd word 1st word 16 th word I2SnWS pin I2SnSCLK pin I2S1DATO pin Whole Timing chart Left data (16bits) Right data (16bits) I2SnWS pin (I2STx_WSINV = 0) I2SnWS pin (I2STx_WSINV = 1) I2SnSCLK pin Delay from WS LSB LSB MSB MSB LSB MSB I2S1DATO pin Stereo Delay from WS I2S1DATO pin MSB MSB LSB Monaural No delay from WS I2S1DATO pin MSB LSB MSB LSB MSB LSB MSB Stereo No delay from WS I2S1DATO pin MSB Monaural Detailed Timing chart TMPA910CRA- 632 2010-06-02 TMPA910CRA 3.17.4 Register Descriptions The following lists the SFRs. Base address = 0xF204_0000 Register Address Name (base+) Description I2STCON 0x0000 Tx Control Register I2STSLVON 0x0004 Tx I S Slave Control Register I2STFCLR 0x0008 Tx FIFO Clear Register I2STMS 0x000C Tx Master/Slave Select Register I2STMCON 0x0010 Tx Master I2S1WS/I2S1SCLK Period Register I2STMSTP 0x0014 Tx Master Stop Register I2STDMA1 0x0018 Tx DMA Ready Register 2 - 0x001C Reserved I2SRCON 0x0020 Rx Control Register I2SRSLVON 0x0024 Rx I S Slave WS/SCK Control Register 2 I2SFRFCLR 0x0028 Rx FIFO Clear Register I2SRMS 0x002C Rx Master/Slave Select Register I2SRMCON 0x0030 Rx Master I2S1WS/I2S1SCLK Period Register I2SRMSTP 0x0034 Rx Master Stop Register I2SRDMA1 0x0038 Rx DMA Ready Register - 0x003C Reserved I2SCOMMON 0x0044 Common WS/SCK and Loop Setting Register I2STST 0x0048 I S Tx Status Register I2SRST 0x004C I S Rx Status Register I2SINT 0x0050 I S Interrupt Register I2SINTMSK 0x0054 I S Interrupt Mask Register I2STDAT 0x1000 to 0x1FFF Transmit FIFO Window DMA Target I2SRDAT 0x2000 to 0x2FFF Receive FIFO Window DMA Target 2 2 2 2 TMPA910CRA- 633 2010-06-02 TMPA910CRA 1. I2STCON (Tx Control Register) Address = (0xF204_0000) + (0x0000) Bit Bit Symbol Reset Type Description Value [31:14] - - Undefined Read as undefined. Write as zero. [13:12] I2STx_RLCH_CUT R/W 0y00 Stereo/Monaural output setting 0y00: Stereo setting (both channel output) 0y01: Monaural setting (Right-side channel output) 0y10: Monaural setting (Left-side channel output) 0y11:Don't setting [11:9] - - Undefined [8] I2STx_BITCNV R/W 0y0 Read as undefined. Write as zero. MSB sign bit inversion 0y0: Not inverted 0y1: Inverted [7:4] - [3] I2STx_UNDERFLOW - Undefined Read as undefined. Write as zero. R/W 0y0 Data output at FIFO underflow 0y0: 0 is output. 0y1: The current data is held. [2] I2STx_MSBINV R/W 0y0 [1] I2STx_WSINV R/W 0y0 LSB/MSB first 0y0: MSB first 0y1: LSB first WS channel definition inversion 0y0: WS = 1 (RCH), WS = 0 (LCH) 0y1: WS channel definition inverted WS = 0 (RCH), WS = 1 (LCH) [0] I2STx_DELAYOFF R/W 0y0 Relationship between Data output timing and WS 0y0: Delay of 1CLOCK from WS 0y1: No delay from WS [Description] a. <I2STx_RLCH_CUT> Stereo/monaural (Right-side channel output, Left-side channel output) output setting. 0y00: Stereo setting (both channel output) 0y01: Monaural setting (Right-side channel output) 0y10: Monaural setting (Left-side channel output) 0y11: Don't setting b. <I2STx_BITCNV> Specifies whether to invert the MSB (sign bit). 0y0: Not inverted 0y1: Inverted TMPA910CRA- 634 2010-06-02 TMPA910CRA c. <I2STx_UNDERFLOW> If the valid data of the internal output FIFO becomes empty states, the data output is kept. This bit defines that output data. (SD output data when FIFO UnderFlow). 0y0: 0 is output. 0y1: The current data is held. d. <I2STx_MSBINV> Selection from LSB/MSB first. 0y0: MSB first 0y1: LSB first e. <I2STx_WSINV> Specifies whether to invert the channel definition of WS. 0y0: WS = 1 (RCH), WS = 0 (LCH) WS signal is at High output, the WS is defined as Right Channel. WS signal is at Low output, the WS is defined as Left Channel. 0y1: WS = 0 (RCH), WS = 1 (LCH) WS signal is at Low output, the WS is defined as Right Channel. WS signal is at High output, the WS is defined as Left Channel. f. <I2STx_DELAYOFF> Selects Relationship between Data output timing and WS. 0y0: Delay of 1CLOCK from WS 0y1: No delay from WS TMPA910CRA- 635 2010-06-02 TMPA910CRA 2. I2SRCON (Rx Control Register) Address = (0xF204_0000) + (0x0020) Bit Bit Symbol Reset Type Description Value [31:14] - - Undefined Read as undefined. Write as zero. [13:12] I2SRx_RCH_CUT R/W 0y00 Stereo/Monaural output setting 0y00: Stereo setting (both channel output) 0y01: Monaural setting (Right-side channel output) 0y10: Monaural setting (Left-side channel output) 0y11:Don't setting [11:9] - - Undefined [8] I2SRx_BITCNV R/W 0y0 Read as undefined. Write as zero. MSB (sign bit) inversion 0y0: Not inverted 0y1: Inverted [7:3] - - Undefined [2] I2SRx_MSBINV R/W 0y0 Read as undefined. Write as zero. LSB/MSB first 0y0: MSB first 0y1: LSB first [1] I2SRx_WSINV R/W 0y0 WS channel definition inversion 0y0: WS= 1 (RCH), WS= 0 (LCH) 0y1: WS channel definition inverted WS= 0 (RCH), WS= 1 (LCH) [0] I2SRx_DELAYOFF R/W 0y0 Relationship between Data output timing and WS 0y0: Delay of 1CLOCK from WS 0y1: No delay from WS [Description] a. <I2SRx_RLCH_CUT> Stereo/monaural (Right-side channel output, left-side channel output) output setting. 0y00: Stereo setting (both channel output) 0y01: Monaural setting (Right-side channel output) 0y10: Monaural setting (Left-side channel output) 0y11: Don't setting b. <I2SRx_BITCNV> Specifies whether to invert the MSB (sign bit). 0y0: Not inverted 0y1: Inverted TMPA910CRA- 636 2010-06-02 TMPA910CRA c. <I2SRx_UNDERFLOW> Selects the data to be output when an underflow occurs in the FIFO. 0y0: 0 is output. 0y1: The current data is held. d. <I2SRx_MSBINV> Selection from LSB/MSB first. 0y0: MSB first 0y1: LSB first e. <I2SRx_WSINV> Specifies whether to invert the channel definition of WS. 0y0: WS = 1 (RCH), WS = 1 (LCH) 0y1: WS channel definition inverted WS = 0 (RCH), WS = 1 (LCH) f. <I2SRx_DELAYOFF> Selects Relationship between Data output timing and WS. 0y0: Delay of 1CLOCK from WS 0y1: No delay from WS TMPA910CRA- 637 2010-06-02 TMPA910CRA 3. I2STSLVON (Tx I2S Slave Control Register) Address = (0xF204_0000) + (0x0004) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined [0] I2STx_SLAVE R/W 0y0 Read as undefined. Write as zero. Transmit output enable 0y0: OFF 0y1: ON (FIFO read enabled) [Description] a. <I2STx_SLAVE> When this bit is set (0 1), the internal status (I2STST<I2STxSTATUS>) changes as follows: SBY (standby) PRE_ACT ACT In the ACT state, the data stored in the FIFO is output. When this bit is cleared (1 0), the internal status (I2STST<I2STxSTATUS>) changes as follows: ACT PRE_SBY SBY In the SBY state, no data is output from the FIFO even when it contains data. Transmission circuit State machine SBY WS cycle x 2 process Observe I2STSLVON = 0x1 WS edge PRE_ACT PRE_SBY I2STSLVON = 0x0 FIFO 1 set WS cycle x 2 process ACT State that can read FIFO of Transmission circuit Note: The current status of internal operation can be read by I2STST<I2STxSTATUS> TMPA910CRA- 638 2010-06-02 TMPA910CRA 4. I2SRSLVON (Rx I2S Slave Control Register) Address = (0xF204_0000) + (0x0024) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined [0] I2SRx_SLAVE R/W 0y0 Read as undefined. Write as zero. Write the FIFO for receiver 0y0: OFF 0y1: ON (FIFO write enabled) [Description] a. <I2SRx_SLAVE> When this bit is set (0 1), the internal status (I2SRST<I2SRxSTATUS>) changes as follows: SBY (standby) PRE_ACT ACT In the ACT state, data is captured into the FIFO. When this bit is cleared (1 0), the internal status (I2SRST<I2SRxSTATUS>) changes as follows: ACT PRE_SBY SBY In the SBY state, no data is captured into the FIFO even when input data is present. Receive circuit State machine SBY Observe I2SRSLVON = 0x1 WS edge WS cycle x 2 process PRE_ACT PRE_SBY I2SRSLVON = 0x0 FIFO 1 set WS cycle x 2 process ACT State that can write to FIFO of Transmission circuit Note: The current status of internal operation can be read by I2SRST<I2SRxSTATUS> TMPA910CRA- 639 2010-06-02 TMPA910CRA 5. I2STFCLR (Tx FIFO Clear Register) Address = (0xF204_0000) + (0x0008) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined [0] I2STx_FIFOCLR R/W 0y0 Read as undefined. Write as zero. FIFO Pointer clear 0y0: Invalid 0y1: FIFO Pointer clear [Description] a. <I2STx_FIFOCLR> Do not clear the FIFO during DMA transfer as it may destroy the transmit data. This bit is always read as 0. TMPA910CRA- 640 2010-06-02 TMPA910CRA 6. I2SFRFCLR (Rx FIFO Clear Register) Address = (0xF204_0000) + (0x0028) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined [0] I2SRx_FIFOCLR R/W 0y0 Read as undefined. Write as zero. FIFO Pointer clear 0y0: Invalid 0y1: FIFO Pointer clear [Description] a. <I2SRx_ FIFOCLR> Do not clear the FIFO during DMA transfer as it may destroy the receive data. This bit is always read as 0. TMPA910CRA- 641 2010-06-02 TMPA910CRA 7. I2STMS (Tx Master/Slave Select Register) Address = (0xF204_0000) + (0x000C) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined Read as undefined. Write as zero. [0] I2STx_MASTER R/W 0y0 Master/slave select 0y0: Slave 0y1: Master (Internally generated I2S1WS and I2S1SCLK are output to an external device.) [Description] a. <I2STx_MASTER> Selects between transmit master and transmit slave. When I2SCOMMON<COMMON> is set to 1, full-duplex mode is enabled and the setting of this register has no effect. TMPA910CRA- 642 2010-06-02 TMPA910CRA 8. I2SRMS (Rx Master/Slave Register) Address = (0xF204_0000) + (0x002C) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined Read as undefined. Write as zero. [0] I2SRx_MASTER R/W 0y0 Master/slave select 0y0: Slave 0y1: Master (Internally generated I2S0WS and I2S0SCLK are output to an external device.) [Description] a. <I2SRx_MASTER> Selects between receive master and receive slave. When I2SCOMMON<COMMON> is set to 1, this bit selects between full-duplex master and full-duplex slave. TMPA910CRA- 643 2010-06-02 TMPA910CRA 9. I2STMCON (Tx Master I2S1WS/I2S1SCLK Period Register) Address = (0xF204_0000) + (0x0010) Bit Bit Symbol Reset Type Description Value [31:4] - - Undefined [3:2] I2STx_WS_DIV[1:0] R/W 0y0 Read as undefined. Write as zero. Ratio source clock to I2S1MCLK 0y00: 1/1 0y01: 1/2 0y10: 1/4 0y11: Do not set [1:0] I2STx_SCLK_DIV[1:0] R/W 0y0 Ratio I2S1MCLK to I2S1SCLK0y00: 1/8 0y01: 1/12 0y10: 1/16 0y11: Do not set [Description] a. <I2STx_WS_DIV[1:0]>, <I2STx_SCLK_DIV[1:0]> When I2SCOMMON<COMMON> is set to 1, full-duplex mode is enabled and the settings in this register have no effect. I2SSCLK /1 1 0 /2 /4 fOSCH /8 00 01 10 /12 /16 I2SxMCLK 00 01 10 /32 I2SxSCLK I2SxWS I2SCOMMON<I2SSCLK> I2STMCON <I2STx_WS_DIV[1:0]> I2STMCON <I2STx_SCLK_DIV[1:0]> TMPA910CRA- 644 2010-06-02 TMPA910CRA 10. I2SRMCON (Rx Master I2S0WS/I2S0SCLK Period Register) Address = (0xF204_0000) + (0x0030) Bit Bit Symbol Reset Type Description Value [31:4] - - Undefined [3:2] I2SRx_WS_DIV[1:0] R/W 0y0 Read as undefined. Write as zero. Ratio source clock to I2S0MCLK 0y00: 1/1 0y01: 1/2 0y10: 1/4 0y11: Do not set [1:0] I2SRx_SCLK_DIV[1:0] R/W 0y0 Ratio I2S0MCLK to I2S0SCLK 0y00: 1/8 0y01: 1/12 0y10: 1/16 0y11: Do not set [Description] a. <I2SRx_WS_DIV[1:0]>, <I2SRx_SCLK_DIV[1:0]> When I2SCOMMON<COMMON> is set to 1, full-duplex mode is enabled. I2SSCLK /1 1 0 /2 /4 /8 00 01 10 fOSCH /12 /16 I2SxMCLK 00 01 10 /32 I2SxSCLK I2SxWS I2SCOMMON<I2SSCLK> I2SRMCON <I2SRx_WS_DIV[1:0]> I2SRMCON <I2SRx_SCLK_DIV[1:0]> TMPA910CRA- 645 2010-06-02 TMPA910CRA Table 3.17.2 Clock setting table I2STMCON I2STMCON I2STx_WS_DIV[1:0] I2STx_SCLK_DIV[1:0] or I2SRMCON Ratio of I2S0MCLK Ratio of I2S0SCLK to source clock to source clock I2SRx_WS_DIV[1:0] or I2SRMCON Ratio of I2S0WS to source clock I2SRx_SCLK_DIV[1:0] 0y00: (1/1) 1/1 1/8 0y00: (1/256) 1/256 0y01: (1/2) 1/2 1/16 0y00: (1/256) 1/512 0y10: (1/4) 1/4 1/32 0y00: (1/256) 1/1024 0y00: (1/1) 1/1 1/12 0y01: (1/384) 1/384 0y01: (1/2) 1/2 1/24 0y01: (1/384) 1/768 0y10: (1/4) 1/4 1/48 0y01: (1/384) 1/1536 0y00: (1/1) 1/1 1/16 0y10: (1/512) 1/512 0y01: (1/2) 1/2 1/32 0y10: (1/512) 1/1024 0y10: (1/4) 1/4 1/64 0y10: (1/512) 1/2048 TMPA910CRA- 646 2010-06-02 TMPA910CRA Table 3.17.3 Audio sampling setting examples based on 32 kHz I2STMCON I2STMCON Source clock I2STx_WS_DIV[1:0] I2STx_SCLK_DIV[1:0] I2SSCLK or frequency I2SRMCON I2S0MCLK frequency I2S0SCLK frequency (Ratio to source clock) (Ratio to source clock) I2SRx_WS_DIV[1:0] 0y00: (1/1) 8.192 MHz 0y01: (1/2) 0y10: (1/4) 0y00: (1/1) 12.288 MHz 0y01: (1/2) 0y10: (1/4) 0y00: (1/1) 16.384 MHz 0y01: (1/2) 0y10: (1/4) or I2SRMCON I2S0WS frequency (Ratio to source clock) I2SRx_SCLK_DIV[1:0] 8.192 MHz 1024 kHz (1/1) (1/8) 4.096 MHz 512 kHz (1/2) (1/16) 2.048 MHz 256 kHz (1/4) (1/32) 12.288 MHz 1024 kHz (1/1) (1/12) 6.144 MHz 512 kHz (1/2) (1/24) 3.072 MHz 256 kHz (1/4) (1/48) 16.384 MHz 1024 kHz (1/1) (1/16) 8.192 MHz 512 kHz (1/2) (1/32) 4.096 MHz 256 kHz (1/4) (1/64) 0y00: (1/256) 0y00: (1/256) 0y00: (1/256) 0y01: (1/384) 0y01: (1/384 ) 0y01: (1/384) 0y10: (1/512) 0y10: (1/512) 0y10: (1/512) 32 kHz (1/256) 16 kHz (1/512) 8 kHz (1/1024) 32 kHz (1/384) 16 kHz (1/768) 8 kHz (1/1536) 32kHz (1/512) 16 kHz (1/1024) 8 kHz (1/2048) Table 3.17.4 Audio sampling setting examples based on 48 kHz 2STMCON I2STMCON Source clock I2STx_WS_DIV[1:0] I2STx_SCLKS_DIV[1:0] I2SSCLK or frequency I2SRMCON I2S0MCLK frequency I2S0SCLK frequency (Ratio to source clock) (Ratio to source clock) I2SRx_WS_DIV[1:0] 0y00: (1/1) 12.288 MHz 0y01: (1/2) 0y10: (1/4) 0y00: (1/1) 18.432 MHz 0y01: (1/2) 0y10: (1/4) 0y00: (1/1) 24.576 MHz 0y01: (1/2) 0y10: (1/4) or I2SRMCON I2S0WS frequency (Ratio to source clock) I2SRx_SCLKS_DIV[1:0] 12.288 MHz 1536 kHz (1/1) (1/8) 6.144 MHz 768 kHz (1/2) (1/16) 3.072 MHz 384 kHz (1/4) (1/32) 18.432 MHz 1536 kHz (1/1) (1/12) 9.216 MHz 768 kHz (1/2) (1/24) 4.608 MHz 384 kHz (1/4) (1/48) 24.576 MHz 1536 kHz (1/1) (1/16) 12.288 MHz 768 kHz (1/2) (1/32) 6.144 MHz 384 kHz (1/4) (1/64) TMPA910CRA- 647 0y00: (1/256) 0y00: (1/256) 0y00: (1/256) 0y01: (1/384) 0y01: (1/384) 0y01: (1/384) 0y10: (1/512) 0y10: (1/512) 0y10: (1/512) 48 kHz (1/256) 24 kHz (1/512) 12 kHz (1/1024) 48 kHz (1/384) 24 kHz (1/768) 12 kHz (1/1536) 48 kHz (1/512) 24 kHz (1/1024) 12 kHz (1/2048) 2010-06-02 TMPA910CRA 11. I2STMSTP (Tx Master Stop Register) Address = (0xF204_0000) + (0x0014) Bit Bit Symbol Type Reset Value [31:1] - - Undefined [0] I2STx_MSTOP R/W 0y0 Description Read as undefined. Write as zero. I2STx master stop: 0y0: Generate I2S1WS/I2S1SCLK 0y1: Stop I2S1WS/I2S1SCLK [Description] a. <I2STx_MSTP> This bit is used to stop (=Fixed Low level) I2S1WS and I2S1SCLK from the master. Before setting this register, make sure that I2STx is in the SBY state (I2STST<I2STx_STATUS[1:0]>0y00). Operation is not guaranteed in other cases. The default setting is not to stop I2S1WS and I2S1SCLK. Therefore, after master-related settings are made, I2S1WS and I2S1SCLK are immediately output. When I2SCOMMON<COMMON> is set to 1, full-duplex mode is enabled and the setting of this register has no effect. TMPA910CRA- 648 2010-06-02 TMPA910CRA 12. I2SRMSTP (Rx Master Stop Register) Address = (0xF204_0000) + (0x0034) Bit Bit Symbol Type Reset Value [31:1] - - Undefined [0] I2SRx_MSTOP R/W 0y0 Description Read as undefined. Write as zero. I2SRx master stop: 0y0: Generate I2S0WS/I2S0SCLK 0y1: Stop I2S0WS/I2S0SCLK [Description] a. <I2SRx_MSTP> This bit is used to stop (= Fixed Low level) I2S0WS and I2S0SCLK from the master. It is not normally used. Before setting this register, make sure that I2SRx is in the SBY state (I2SRST<I2SRx_STATUS[1:0]>0y00). Operation is not guaranteed in other cases. The default setting is not to stop I2S0WS and I2S0SCLK. Therefore, after master-related settings are made, I2S0WS and I2S0SCLK are immediately output. TMPA910CRA- 649 2010-06-02 TMPA910CRA 13. I2STDMA1 (Tx DMA Ready Register) Address = (0xF204_0000) + (0x0018) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined [0] I2STx_DMAREADY1 R/W 0y0 Read as undefined. Write as zero. I2STx DMA ready: 0y0: Disable 0y1: Enable [Description] a. <I2STx_ DMAREADY1> This register indicates the DMA ready state to the hardware logic. This register should set to "1" by software after both the DMA and I2S operational configuration are completed, then the hardware logic can be recognized the DMA ready. And the hardware logic monitors the FIFO and starts DMA transfer. Note: To disable this register, make sure whether the DMA transfer is completed first and the I2STSLVON register set to 0y0, the I2STST<I2STx_STATUS> is SBY and then this register can be set to 0y0. TMPA910CRA- 650 2010-06-02 TMPA910CRA 14. I2SRDMA1 (Rx DMA Ready Register) Address = (0xF204_0000) + (0x0038) Bit Bit Symbol Reset Type Description Value [31:1] - - Undefined [0] I2SRx_DMAREADY1 R/W 0y0 Read as undefined. Write as zero. I2SRx DMA ready: 0y0: Disable 0y1: Enable [Description] a. <I2SRx_ DMAREADY1> This register indicates the DMA ready state to the hardware logic. This register should set to "1" by software after both the DMA and I2S operational configuration are completed, then the hardware logic can be recognized the DMA ready. And the hardware logic monitors the FIFO and starts DMA transfer. Note: To disable this register, make sure whether the DMA transfer is completed first and the I2STSLVON register set to 0y0, the I2STST<I2STx_STATUS> is SBY and then this register can be set to 0y0. TMPA910CRA- 651 2010-06-02 TMPA910CRA 15. I2SCOMMON (Common WS/SCK and Loop Setting Register) Address = (0xF204_0000) + (0x0044) Bit Bit Symbol Type Reset Description Value [31:6] - - Undefined Read as undefined. Write as zero. [5] Reserved WO 0y0 Read as undefined. Write as zero. [4] MCLKSEL0 WO 0y0 Master clock to be output from the receive logic: 0y0: Audio source clock 0y1: Divided-down audio source clock [3] MCLKSEL1 WO 0y0 Master clock to be output from the transmit logic: 0y0: Audio source clock 0y1: Divided-down audio source clock [2] I2SSCLK WO 0y0 Audio source clock: 0y0: PLLCG clock (fOSCH) 0y1: External clock [1] LOOP R/W 0y0 Loop setting 0y0: Loop disabled 0y1: Loop enabled [0] COMMON R/W 0y0 Common or separate SCK/WS for Tx and Rx: 0y0: Separate 0y1: Common [Description] a. <MCLKSEL0> Selects the master clock to be output from the receive logic. 0y0: Audio source clock 0y1: Divided-down audio source clock b. <MCLKSEL1> Selects the master clock to be output from the transmit logic. 0y0: Audio source clock 0y1: Divided-down audio source clock c. <I2SSCLK> Selects the audio source clock to be used. 0y0: PLLCG clock (fOSCH) 0y1: External clock TMPA910CRA- 652 2010-06-02 TMPA910CRA d. <LOOP> Specifies loop setting what the transmit pin outputs the data via transmit operation by inputting the serial data from receive pin. 0y0: Loop disabled 0y1: Loop enabled a. <COMMON> When this bit is set to 1, the SCK and WS input signals of I2SRx are also used by I2STx. In this case, the settings made for the transmit master have no effect. TMPA910CRA- 653 2010-06-02 TMPA910CRA 16. I2STST (I2S Tx Status Register) Address = (0xF204_0000) + (0x0048) Bit Bit Symbol Reset Type Description Value [31:4] - - Undefined Read as undefined. [3:2] I2STx_STATUS[1:0] RO 0y00 FIFO status: 0y00: SBY 0y01: PreACT 0y10: PreSBY 0y11: ACT [1] I2STx_FIFOFULL RO 0y0 FIFO full status: 0y0: Not full 0y1: Full [0] I2STx_FIFOEMPTY RO 0y1 FIFO empty status: 0y0: Not empty 0y1: Empty [Description] a. <I2STx_STATUS[1:0]> Indicates the FIFO status. 0y00: SBY 0y01: PreACT 0y10: PreSBY 0y11: ACT b. <I2STx_FIFOFULL> Indicates the FIFO full status. 0y0: Not full 0y1: Full c. <I2STx_FIFOEMPTY> Indicates the FIFO empty status. 0y0: Not empty 0y1: Empty TMPA910CRA- 654 2010-06-02 TMPA910CRA 17. I2SRST (I2S Rx Status Register) Address = (0xF204_0000) + (0x004C) Bit Bit Symbol Reset Type Description Value [31:4] - - Undefined [3:2] I2SRx_STATUS[1:0] RO 0y00 Read as undefined. FIFO write status: 0y00: SBY 0y01: PreACT 0y10: PreSBY 0y11: ACT [1] I2SRx_FIFOFULL RO 0y0 FIFO full status: 0y0: Not full 0y1: Full [0] I2SRx_FIFOEMPTY RO 0y1 FIFO empty status: 0y0: Not empty 0y1: Empty [Description] a. <I2SRx_STATUS [1:0]> Indicates the FIFO write status. 0y00: SBY 0y01: PreACT 0y10: PreSBY 0y11: ACT b. <I2SRx_FIFOFULL> Indicates the FIFO full status. 0y0: Not full 0y1: Full c. <I2SRx_FIFOEMPTY> Indicates the FIFO empty status. 0y0: Not empty 0y1: Empty TMPA910CRA- 655 2010-06-02 TMPA910CRA 18. I2SINT (I2S Interrupt Register) Address = (0xF204_0000) + (0x0050) Bit Bit Symbol Reset Type Description Value [31:4] - - Undefined Read as undefined. Write as zero. [3] I2SRx_OVERFLOW_INT R/W 0y0 Rx FIFO overflow interrupt: Read: 0y0: No interrupt 0y1: Interrupt generated Write: 0y0: Invalid 0y1: Clear [2] I2SRx_UNDERFLOW_INT R/W 0y0 Rx FIFO underflow interrupt: Read: 0y0: No interrupt 0y1: Interrupt generated Write: 0y0: Invalid 0y1: Clear [1] I2STx_OVERFLOW_INT R/W 0y0 Tx FIFO overflow interrupt: Read: 0y0: No interrupt 0y1: Interrupt generated Write: 0y0: Invalid 0y1: Clear [0] I2STx_UNDERFLOW_INT R/W 0y0 Tx FIFO underflow interrupt: Read: 0y0: No interrupt 0y1: Interrupt generated Write: 0y0: Invalid 0y1: Clear [Description] a. <I2SRx_OVERFLOW_INT>, <I2SRx_UNDERFLOW_INT>, <I2STx_OVERFLOW_INT>, <I2STx_UNDERFLOW_INT> This register indicates the interrupt status of each interrupt source. To monitor the FIFO status by using each interrupt source, the corresponding bit of the interrupt mask register (I2SINTMSK) must be set to 0. When an interrupt is generated from one of these sources, the interrupt controller generates an I2SINT interrupt. The interrupt source can be identified by monitoring each interrupt source bit of the I2SINT register. Each bit of this register is cleared by writing 1, and the interrupt status is cleared. Note: This register is corresponded when writing "0" to the corresponding bit of the interrupt mask register (I2SINTMSK). TMPA910CRA- 656 2010-06-02 TMPA910CRA 19. I2SINTMSK (I2S Interrupt Mask Register) Address = (0xF204_0000) + (0x0054) Bit Bit Symbol Type Reset Value [31:4] - - Undefined [3] I2SRx_OVERFLOW_INTMS R/W 0y1 Description Read as undefined. Write as zero. Rx FIFO overflow setting: 0y0: Enable 0y1: Disable [2] I2SRx_UNDERFLOW_INTM R/W 0y1 Rx FIFO underflow setting: 0y0: Enable 0y1: Disable [1] I2STx_OVERFLOW_INTMS R/W 0y1 Tx FIFO overflow setting: 0y0: Enable 0y1: Disable [0] I2STx_UNDERFLOW_INTM R/W 0y1 Tx FIFO underflow setting: 0y0: Enable 0y1: Disable [Description] a. <I2SRx_OVERFLOW_INTMS> The Rx FIFO overflow setting 0y0: Enable 0y1: Disable b. <I2SRx_FIFOFULL> The Rx FIFO underflow setting 0y0: Enable 0y1: Disable c. <I2SRx_FIFOEMPTY> The Tx FIFO overflow setting 0y0: Enable 0y1: Disable d. <I2SRx_FIFOFULL> The Tx FIFO underflow setting 0y0: Enable 0y1: Disable TMPA910CRA- 657 2010-06-02 TMPA910CRA 20. I2STDAT (Transmit FIFO Window DMA Target Register) Address = (0xF204_1000) + (0x0000) Bit Bit Symbol Type Reset Value Description [31:16] Left[15:0] WO 0x0000 I2STx left audio data [15:0] [15:0] Right[15:0] WO 0x0000 I2STx right audio data [15:0] [Description] a. <Left[15:0]>, <Right[15:0]> The data set to this register is written to the transmission FIFO. (Note2) Stereo audio data is set simultaneously with upper data as left channel data and lower data as right channel data. Data can be written to any address in a range of 0xF2041000 to 0xF2041FFF, and is sequentially stored in the FIFO as it is written. This register does not support read operations (always returns 0). Note1: This register is write-only. Note2: This register can be accessed from CPU/DMAC as Master. TMPA910CRA- 658 2010-06-02 TMPA910CRA 21. I2SRDAT (Receive FIFO Window Target Register) Address = (0xF204_2000) + (0x0000) Bit Bit Symbol Type Reset Description Value [31:16] Left[15:0] RO 0x0000 I2SRx left audio data [15:0] [15:0] Right[15:0] RO 0x0000 I2SRx right audio data [15:0] [Description] a. <Left[15:0]>, <Right[15:0]> The data of the receive FIFO is read from this register. (Note2) Stereo audio data is input simultaneously with upper data as left channel data and lower data as right channel data. Data can be read from any address in a range of 0xF2042000 to 0xF2042FFF, and is sequentially read out from the FIFO. This register is read-only. Note1: This register is read-only. Note2: This register can be accessed from CPU/DMAC as Master. TMPA910CRA- 659 2010-06-02 TMPA910CRA 3.17.5 Setting example * Setting example of Transmission master and Receive slave I2SCOMMON I2STCON I2SRCON I2SRMS I2STMS GPIOMFR1 GPIOLFR1 0xf8004000 0xf800403c 0x00000004 0x00000000 0x00000000 0x00000000 0x00000001 0x000000FF 0x000000FF 0x0000FFFF 0xFFFF0000 0xf8004040 0xf8004044 0xf8004048 0xf800404c DMACConfiguration DMACC0SrcAddr DMACC0DestAddr DMACC0Control DMACC0Configuration I2SRSLVON 0xf8004020 I2STDAT 0xf8004050 0x04492008 0x00000001 I2SRDAT 0xf8008000 0x08492008 0x00001017 0x00000001 I2SRST LDR r1, = 0xc AND r0,r0,r1 LDR r2, = 0xc CMP r0,r2 BNE i2sr_act I2SRDMA1 r0 ; I2S internal clock on ; label i2sr_act ; read I2SRST register data to r0 0x00000001 ; check I2S Active ; r0 r2 , jump to i2sr_act ;I2S DMA Ready DMACConfiguration DMACC1SrcAddr DMACC1DestAddr DMACC1Control DMACC1Configuration I2STSLVON 0x00000001 0xf8004000 I2STDAT 0x04492008 0x00000a81 0x00000001 I2SRST LDR r1, = 0xc AND r0,r0,r1 LDR r2, = 0xc CMP r0,r2 BNE i2st_act I2STDMA1 r0 0x00000001 DMACC0Control CMP r0,#0x0 BNE finish_DMA I2STDMA1 I2SRDMA1 I2STSLVON I2SRSLVON r0 0x00000000 0x00000000 0x00000000 0x00000000 I2STST LDR AND LDR CMP BNE r0 ; label ; read I2STST register data to r0 r0 ; check I2S Tx standby ; label ; read I2SRST register data to r0 0x00000001 0x00000001 ; check I2S Rx standby ; r0 r1 , jump to i2st_stop_r ; clear Tx FIFO ; clear Rx FIFO i2sr_act i2st_act finish_DMA i2s_stop_t r1, = 0xc r0,r0,r1 r1, = 0x0 r0,r1 i2s_stop_t i2s_stop_r I2SRST LDR r1, = 0xc AND r0,r0,r1 LDR r1, = 0x0 CMP r0,r1 BNE i2s_stop_r I2STFCLR I2SFRFCLR TMPA910CRA- 660 ; write 0x00000004 to Register ; Rx is slave ; Tx is master ; Set transfer data ; End of set data ; Use DMA scatter gather link ; source address ; destination address ; next address ; Set DMAC control register ; Set Rx DMAC ; Set Tx DMAC ; I2S internal clock on ; label i2st_act ; read I2SRST register data to r0 ; check I2S Active ; r0 r2 , jump to i2st_act ;I2S DMA Ready ; label ; read DMACC0Control data to r0 ; check the End of Rx DMAC ; r0 0x0 , jump to finish_DMA ; DMA Clear ; internal clock off 2010-06-02 TMPA910CRA 3.18 SD Host Controller 3.18.1 Function Overview Functions and characteristic of SD Host Controller are shown as follows. 1) Data transmission/reception in frame units 2) Error check: CRC7 (for commands), CRC16 (for Data) 3) Synchronous method: bit synchronous by SDCLK 4) SD Memory/IO Card Interface: COMMAND (1bit), Data (4 bits), INT (1bit) 5) Multiple port support: 2 card 6) 512byte x2 data buffer: 256wordsx16bitsx2 7) Card detect support (SDCxCD or SDCxDAT3) 8) Data write protect support 9) Detected below Status error * SDbuffer underflow/overflow * timeout (response, other) * END error, CRC error, CMD error 10) Recognizes the various response frame formats through the register settings 11) The SD_CLK cycle division ratio can be set from fPCLK/2 to fPCLK/512 12) The transfer data length can be either be set from 1byte to 512byte 13) Sector counter for multiple Read/Write operation (Read: single read only) 14) Buffer status mode transfer support Note: All control registers and Data access, are supported only 16bit-bus width.(Not support 32-bit bus access) This product contains an SD host controller for controlling SD cards. To use the SD host controller, you need to join the SD Association. Please also note that a non-disclosure agreement must be signed with us before the detailed specifications of the SD host controller can be disclosed. For details, please contact your local Toshiba sales representative. TMPA910CRA- 661 2010-06-02 TMPA910CRA 3.19 LCD Controller (LCDC) 3.19.1 Overview This LSI incorporates a color-capable LCD controller (LCDC). The LCDC has the following characteristics: Table 3.19.1 Characteristics of LCDC Type of LCD panel TFT STN (Dual/Single) ~ 256 colors 2,4,16,256 colors ~ 16.77 million colors 3,375 colors 1/2/4/8/16/24 bit 1/2/4/8/16 bit Displayable colors at same (Palette color change available) Displayable colors (Palette color change unavailable) Bit per Pixel (Data quantity per pixel) Number of available horizontal pixels 16x (PPL + 1)dot : PPL values take integers of 0 to 63 only. (Note) Number of available vertical lines 4 to 1,024 (integer)* Transfer-destination data bus width (LCD driver) Max. 24 bits 4/8 bit FIFO buffer for display data receive 32 bit x16 word x 2 Timing adjustment function Can program the front/back porch timings of vertical/horizontal sync signals. Display palette 256 entries, 16-bit palette RAM Connection terminal Data type Little endian support Terminals LD23 to LD0 Data buses for LCD driver LCLAC terminal Enable data "Enable" signal AC bias signal (frame signal) LCLLP terminal Horizontal sync signal Horizontal sync pulse LCLFP terminal Vertical sync signal Vertical sync pulse LCLCP terminal Clock for LCDD data latch (Panel clock) LCLLE terminal Line end signal LCLPOWER terminal LCD panel power control signal (Note: Not supported by this LSI) Not used basically Note: In the display size, limitations occur depending on display colors and operation clocks. This is reference as follows. LCD type Displayable Maximum dot number TFT 24bit Color Approximately 175000dot (around 480x320) TFT 16bit Color Approximately 350000dot (around 640x480) TFT 8bit Color Approximately 500000dot (around 800x600) TFT 4bit Color No particular limitations TFT 2bit Color No particular limitations STN 15bit Color Approximately 350000dot (around 640x480) STN 8bit Color Approximately 700000dot (around 960x640) STN 4bit Color No particular limitations STN 2bit Color No particular limitations STN 1bit Color(Monochrome) No particular limitations TMPA910CRA- 662 2010-06-02 TMPA910CRA 3.19.2 Function Figure 3.19.1 shows the schematic block diagram of the LCDC. AHB Bus CLOCK Generator AHB Slave I/F Control register LCD clock LCD control signal Timing Controller Higher-order STN Higher-order panel DMA FIFO AHB Master I/F Higher-order panel Formatter Pixel Serializer Input FIFO control FIFO Gray Scaler Pallet (128x32) STN/TFT Data select FIFO underflow Lower-order panel Formatter Lower-order panel DMA FIFO LCD Data FIFO Lower-order STN AHB Error TFT Interrupt control INTS[18] Figure 3.19.1 LCDC Block Diagram The description of each block is shown in the next and following pages: TMPA910CRA- 663 2010-06-02 TMPA910CRA 3.19.2.1 DMA FIFO and Related Control Logics The FIFO's input port is connected to the interface; and the output port is connected to the pixel serializer. In order to match the single/dual panel LCD types, display data read from the display RAM is buffered into the two DMA FIFOs that can control the data individually. 32 words of FIFO can be used. By the WATERMARK register setting, the FIFO requests data at the point when free space of 4 words or more, or 8 words or more occurs. If LCD data is output with the FIFO empty, an underflow condition results, which asserts an interrupt signal. TMPA910CRA- 664 2010-06-02 TMPA910CRA 3.19.2.2 Pixel Serializer This block reads LCD data of 32-bit width from the DMA FIFO's output port and converts it into 24-, 16-, 8-, 4-, 2-, or 1-bit data according to the operation mode. In the dual panel mode, data is divided into the higher DMA FIFO (16 words) and the lower DMA FIFO (16 words) and read alternately. Data converted into a suitable size is used as color/gray level values in the palette RAM or output directly without bypassing the palette. Table 3.19.2 LBLP: DMA FIFO output bits 31 to 16 bpp 1 2 4 8 16 24 DMA FIFO output bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P15 1 P14 0 1 P13 0 1 P12 0 P7 3 2 1 P11 0 1 P10 0 P6 1 0 3 2 1 P9 0 1 0 P5 1 0 3 2 0 P8 1 0 P4 1 0 P3 3 2 1 0 P2 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 P1 P0 - - - - - - - - Table3.19.3 LBLP: DMA FIFO output bits 15 to 0 bpp 1 2 4 8 16 24 DMA FIFO output bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 P7 1 P6 P5 P4 P3 3 2 P3 P2 P2 1 0 3 2 P1 P1 1 0 3 2 P0 1 0 P1 7 6 5 4 P0 3 2 1 0 P0 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 P0 15 14 13 12 11 10 9 8 P0 15 14 13 12 11 10 9 8 TMPA910CRA- 665 2010-06-02 TMPA910CRA 3.19.2.3 RAM Palette A palette of 16 bits x 256 entries is incorporated. 32bit Access AHB Slave I/F One-pixel portion 31 30,29,28,27,26 ------------------------------------------------------------------------------ 04,03,02,01,00 Pallet address AHB Bus 0x0200 I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] 0x0204 I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] 0x0208 I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] 0x03F4 I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] 0x03F8 I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] 0x03FC I B [4:0] G [4:0] R [4:0] I B [4:0] G [4:0] R [4:0] Original Display Data Direct (bypass) Replaced Display Data Pallet (128x32) Figure 3.19.2 Palette RAM Pixel data is replaced into data of in-palette 16 bits and then output. (Original Display Data is processed as palette addresses, and then this data that into address as Replaced Display data is outputted. Moreover, if it is 16/24bpp, Original Display Data is outputted as Replaced Display data) One word (32 bits) of palette RAM data equals to two pixels of data. Therefore, the lowest-order bit of pixel data is used to select either the higher 16 bits or lower 16 bits of the palette RAM. Example) If 0x00 pixel data is input in 8 bpp, the data is replaced into the lower 16-bit data for an address of 0xF420_0200. If 0xFF pixel data is input in 8 bpp, the data is replaced into the higher 16-bit data for an address of 0xF420_03FC. A palette structured with R:5 bits, G:5 bits, and B:5 bits is structured with a dual port RAM of 128x32 bits. Therefore, pixel data of two-pixel can be written in 1 word. TMPA910CRA- 666 2010-06-02 TMPA910CRA LCD Palette Bit [31] Address = (0xF420_0000) + ((0x0200) to (0x03FC)) Bit Symbol Type Reset Description Value I R/W 0y0 Brightness/unused [30:26] B[4:0] R/W 0y00000 Blue palette data setting [25:21] G[4:0] R/W 0y00000 Green palette data setting [20:16] R[4:0] - 0y00000 Red palette data [15] I R/W 0y0 Brightness/unused [14:10] B[4:0] R/W 0y00000 Blue palette data setting [9:5] G[4:0] R/W 0y00000 Green palette data setting [4:0] R[4:0] R/W 0y00000 Red palette data In the monochrome STN mode (include Gray display), only red palette R [4:1] is used (bit0 not used). In the STN color mode, red, green, and blue bits [4:1] are used (bit0 not used). To support the BGR data system, this red and blue pixel data can be swapped using the control register bit. In the 16 / 24 bpp TFT mode, palettes are bypassed so that the pixel serializer's output can be directly used as TFT panel data. A RAM palette supports 256 entries x 16 bits at maximum. Therefore, TFT and color STN palettes can support up to 8-bpp data. Note: The LCD data process accelerator (LCDDA) contained in this microcontroller only supports 64K (16 bpp) or 16M (24 bpp) colors. Therefore, the LCDDA does not allow the use of the palette or the swap function. 3.19.2.4 Gray Scaler The gray algorithm supports monochrome display 15 gray scale levels. For STN color display, three color components (red, green, and blue) are processed for gray scale level concurrently, allowing 3,375 (15 x 15 x 15) colors to be usable. 3.19.2.5 Higher-/Lower-Order Panel Formatter Divides higher and lower pixel data for using Dual Panel. RGB pixel data is shifted in to each of the unique registers per bit and concurrently to be configured in proper bit positions. TMPA910CRA- 667 2010-06-02 TMPA910CRA 3.19.2.6 Panel Clock Generator Can set the frequency division rate of data transfer clock (LCLCP signal) used in the internal clock (HCLK) and LCDC. The LCLCP signal can be programmed in the range of HCLK/2 to HCLK/1025 according to the data rate of the LCD panel. LCD Panel LCDCP VRAM TMPA910CRA LCDC TMPA910CRA- 668 Bus Speed HCLK 2010-06-02 TMPA910CRA 3.19.2.7 Timing Controller The main function of the timing controller block is to adjust horizontal/vertical timings. 3.19.2.8 Creating Interrupts The LCDC generates four types of interrupts that are maskable individually and one type of joint interrupt. TMPA910CRA- 669 2010-06-02 TMPA910CRA 3.19.3 Description of Registers The following lists the SFRs: Table3.19.4 List of registers Register Address Name (base+) base address = 0xF420_0000 Description LCDTiming0 0x000 LCDTiming1 0x004 Horizontal Axis Panel Control Register Vertical Axis Panel Control Register LCDTiming2 0x008 Clock and Signal Polarity Control Register LCDTiming3 0x00C Line End Control Register LCDUPBASE 0x010 Upper Panel Frame Base Address Register LCDLPBASE 0x014 Lower Panel Frame Base Address Register LCDIMSC 0x018 Interrupt Mask Set/Clear Register LCDControl 0x01C LCDC Control Register LCDRIS 0x020 Raw Interrupt Status Register LCDMIS 0x024 Masked Interrupt Status Register LCDICR 0x028 Interrupt Clear Register LCDUPCURR 0x02C Upper Panel Current Address Value Registers LCDLPCURR 0x030 Lower Panel Current Address Value Registers LCDPalette 0x200 to 0x3FC Color Palette Register TMPA910CRA- 670 2010-06-02 TMPA910CRA 1. LCDTiming0 (Horizontal Axis Panel Control Register) LCDTiming0 is the register to control the following: * Horizontal sync pulse width (HSW) * Horizontal front porch (HFP) period * Horizontal back porch (HBP) period * Number of pixels per line (PPL) Address = (0xF420_0000) + (0x0000) Bit Bit Symbol Type Reset Description Value [31:24] HBP R/W 0x00 [23:16] HFP R/W 0x00 [15:8] HSW R/W 0x00 [7:2] PPL R/W 0y000000 Value set for horizontal back porch width (Setting value + 1) 0x00 to 0xFF Value set for horizontal front porch width (Setting value + 1) 0x00 to 0xFF Horizontal sync pulse width (Setting value + 1) 0x00 to 0xFF Value set for pixels per line ((Setting value + 1) x 16) 0y000000 to 0y111111 [1:0] Reserved - Undefined Read as undefined. Write as zero. [Description] a. <HBP> Horizontal back porch refers to the number of LCLCP cycles from the LCLLP rising (or falling) edge to the active data start. The actual period counted is the value set in this field incremented by one. Therefore, a delay of 1 to 256 LCLCP cycles can be inserted. b. <HFP> Horizontal front porch refers to the number of LCLCP cycles from the active data end to the LCLLP falling (or rising) edge. The actual period counted is the value set in this field incremented by one. Therefore, a delay of 1 to 256 LCLCP cycles can be inserted. c. <HSW> Horizontal sync pulse width refers to the active pulse width of LCLLP. The actual period counted is the value set in this field incremented by one. Therefore, a delay of 1 to 256 LCLCP cycles can be inserted. d. <PPL> The PPL field is used to specify the number of pixels per line. The actual pixel count is calculated by the formula "(PPL value + 1) x 16". Therefore, 16 to 1024 pixels can be specified. TMPA910CRA- 671 2010-06-02 TMPA910CRA * Limitations on horizontal timing There is a restriction on the operation mode used. minimum values are HSW = 2, HBP = 2. STN single panel mode: * HSW = 3 * HBP = 5 * HFP = 5 * Panel clock divisor (PCD) = 1(HCLK/3) STN Dual panel mode: * HSW = 3 * HBP = 5 * HFP = 5 * PCD = 5(HCLK/7) Depending on usage conditions, setting enough time before the start point of line (example: HSW = 6, HBP = 10) prevents data from being corrupted even when PCD = 4 (minimum value). The figure below shows an example of operation mode settings (LCDTiming2<IHS> = 1, LCDTiming2<IPC> = 0, LCDTiming2<IOE> = 0): CPL Signal name Horizontal sync signal LCLLP (Number of clocks per line) HSW (Horizontal sync pulse) HBP (Horizontal back porch) 16*(PPL+1) (Number of valid data pixels) HFP (Horizontal front porch) Panel clock LCLCP Panel data LCD[23:0] Horizontal non-data area Horizontal non-data area LCLAC LCLLE 4-HCLK width LED (Delay of CLLE) Figure 3.19.3 Basic operation of horizontal control Note: For CPL, divide PPL by 1 (TFT), 4 or 8 (monochrome STN), or (2 + 2/3) (color STN) to set the division value. TMPA910CRA- 672 2010-06-02 TMPA910CRA 2. LCDTiming1 (Vertical Axis Panel Control Register) LCDTiming1 is the register to control the following: * Number of lines per panel (LPP) * Vertical sync pulse width (VSW) * Vertical front porch (VFP) period * Vertical back porch (VBP) period Address = (0xF420_0000) + (0x0004) Bit Bit Symbol [31:24] VBP Type R/W Reset Description Value 0x00 Setting the number of vertical back porch lines 0x00 to 0xFF [23:16] VFP R/W 0x00 Setting the number of vertical front porch lines 0x00 to 0xFF [15:10] VSW R/W 0y000000 Setting the number of vertical sync pulse lines (Setting value + 1) [9:0] LPP R/W 0y0000000000 Setting the number of lines per panel ( Setting value + 1) 0y000000 to 0y111111 0y0000000000 to 0y1111111111 [Description] a. <VBP> Vertical back porch refers to the number of non-active lines at the start of each frame after the vertical sync signal. This 8-bit VBP field is used to specify the number of line clocks inserted at the start point of each frame. VBP generates 0 to 255 line clock cycles. b. <VFP> Vertical front porch refers to the number of non-active lines at the end of each frame before the vertical sync signal. For STN displays, setting a value other than 0 reduces contrast. VFP generates 0 to 255 line clock cycles. c. <VSW> Vertical sync pulse width refers to the number of horizontal sync lines. For STN displays, a small value (such as 0) must be programmed. Setting a greater value results in lower contrast. d. <LPP> The LPP field specifies the number of active lines per LCD panel. The actual value counted is the value set in this field incremented by one. Therefore, 1 to 1024 lines can be specified. For dual-panel displays, this field should be programmed for the upper panel and the lower panel individually. TMPA910CRA- 673 2010-06-02 TMPA910CRA The figure below shows the operation mode setting (LCDTiming2<IVS> = 1, LCDTiming2<IHS> = 0) as an example: Signal name Vertical sync signal LCLFP VSW + 1 (Vertical sync pulse) VBP LPP + 1 VFP (Vertical back porch) (Number of lines per panel) (Vertical front porch) Panel clock LCLLP Panel data Vertical non-data area Vertical non-data area LCD[23:0] Figure 3.19.4 Basic operation of Vertical control TMPA910CRA- 674 2010-06-02 TMPA910CRA 3. LCDTiming2 (Clock and Signal Polarity Control Register) LCDTiming2 is the read/write register to control the LCDC timing. Address = (0xF420_0000) + (0x0008) Bit Bit Symbol Reset Type Description Value [31:27] PCD_HI R/W 0y00000 [26] Reserved R/W 0y0 [25:16] CPL R/W 0y0000000000 Value set for the higher 5 bits of panel clock frequency division 0y00000 to 0y11111 Read as undefined. Write as zero. Number of clocks per line 0y0000000000 to 0y1111111111 [15] - - Undefined [14] IOE R/W 0y0 Read as undefined. Write as zero. Data enable signal invert setting (Note1) 0y0: LCLAC output "H" active in TFT mode 0y1: LCLAC output "L" active in TFT mode [13] IPC R/W 0y0 Panel clock signal edge selection 0y0: LCLCP rising edge 0y1: LCLCP falling edge [12] IHS R/W 0y0 Horizontal synchronization signal Invert setting 0y0: LCLLP pin "H" active 0y1: LCLLP pin "L" active [11] IVS R/W 0y0 Vertical synchronization signal Invert setting 0y0: LCLFP pin "H" active 0y1: LCLFP pin "L" active [10:6] ACB R/W 0y00000 Bias invert frequency (Setting + 1) (Note2) 0y00000 to 0y11111 [5] Reserved - Undefined Read as undefined. Write as zero. [4:0] PCD_LO R/W 0y00000 Value set for the lower 5 bits of panel clock frequency division Note1: This bit is usable TFT mode only. Note2: This bit is usable STN mode only. [Description] a. <PCD_HI> The PCD_HI field is used to generate the LCD panel clock frequency by dividing the HCLK frequency. A 10-bit divisor can be specified by combining PCD_HI (upper 5 bits) and PCD_LO (lower 5 bits). LCLCP = HCLK/ (PCD + 2). TMPA910CRA- 675 2010-06-02 TMPA910CRA b. <CPL> The CPL field specifies the actual number of LCLCP clocks per line in the LCD panel. This value is obtained by dividing the number of pixels per line by 1, 4, 8 or 8/3, and then subtracting one from the quotient. To allow the LCD controller to function properly, this field needs to be programmed properly in addition to PLL. Panel Type TFT STN Bus Width Monochrome 4 8 Color 8 CPL Calculation Formula (Number of pixels per line) 1 1 (Number of pixels per line) CPL = 1 4 (Number of pixels per line) CPL = 1 8 (Number of pixels per line) CPL = 8 1 3 CPL = Note: Round up all digits to the right of the decimal point. c. <IOE> The IOE bit specifies the polarity of the data enable signal. The data enable signal is output on the LCLAC pin to notify the LCD panel when valid display data is available. It can be used only for TFT displays. d. <IPC> This bit set the panel clock edge. e. <IHS> This bit set the polarity of Horizontal sync signal. f. <IVS> This bit set the polarity of Vertical sync signal. TMPA910CRA- 676 2010-06-02 TMPA910CRA g. <ACB> The ACB field specifies the bias inversion period. For STN displays, the bias polarity needs to be inverted periodically to prevent degradation in the LCD due to the accumulation of DC electrical charge. The bias inversion period, which is specified in lines, is the value set in this field incremented by one. Therefore, it can be set to 1 to 32 lines. This field can be used only for STN displays. h. <PCD_LO> The lower 5 bits of the value set for panel clock frequency division setting (10 bits) Note: There are limitations on the minimum values usable for the panel clock divider in the STN mode. * Single panel color mode: PCD = 1 (LCLCP = HCLK/3) * Dual panel color mode: PCD = 4 (LCLCP = HCLK/6) * Single panel monochrome 4-bit interface mode: PCD = 2 (LCLCP = HCLK/4) * Dual panel monochrome 4-bit interface mode: PCD = 6 (LCLCP = HCLK/8) * Single panel monochrome 8-bit interface mode: PCD = 6 (LCLCP = HCLK/8) * Dual panel monochrome 8-bit interface mode: PCD = 14 (LCLCP = HCLK/16) TMPA910CRA- 677 2010-06-02 TMPA910CRA 4. LCDTiming3 (Line End Control Register) Address = (0xF420_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value [31:17] - - Undefined [16] LEE R/W 0x00 Read as undefined. Write as zero. Enable for Line end signal CLLE 0y0: Disable (Fixed to "L") 0y1: Enable [15:7] - - Undefined [6:0] LED R/W 0y000000 Read as undefined. Write as zero. Delay value for CLLE output (Setting value + 1) 0y000000 to 0y111111 [Description] a. <LEE> After this signal is enabled, CLLE outputs a positive pulse of 4-HCLK period after the end of each line. If the line end signal is disabled, this signal is held at "L" at all times. b. <LED> Sets the delay value for CLLE output. TMPA910CRA- 678 2010-06-02 TMPA910CRA 5. LCDUPBASE (Upper Panel Frame Base Address Register) This is the color LCD DMA base address register. Address = (0xF420_0000) + (0x0010) Bit Bit Symbol [31:2] LCDUPBASE Type R/W Reset Description Value 0x00000000 Register to set color LCD DMA base addresses. 0x00000000 to 0x3FFFFFFF - [1:0] 6. - Undefined Read as undefined. Write as zero. LCDLPBASE (Lower Panel Frame Base Address Register) Address = (0xF420_0000) + (0x0014) Bit Bit [31:2] Symbol LCDLPBASE Type R/W Reset Description Value 0x00000000 Register to set color LCD DMA base addresses. 0x00000000 to 0x3FFFFFFF [1:0] - - Undefined Read as undefined. Write as zero. LCDUPBASE and LCDLPBASE set the first address of display RAM. LCDUPBASE is used for the following: * TFT display * Single panel STN display * Higher-order panel of dual panel STN display LCDLPBASE is used for the lower-order panel of dual panel STN display. Programmers need to setting LCDUPBASE (and LCDLPBASE of dual panel) before enabling LCDC. Each address setting set to the full-address of 32-bit ([31:0]). However, its lower 2-bit are ignored, it is set as word unit (4-byte)setting. TMPA910CRA- 679 2010-06-02 TMPA910CRA 7. LCDIMSC (Interrupt Mask Set/Clear Register) Address = (0xF420_0000) + (0x0018) Bit Bit Symbol Type Reset Description Value [31:5] - - Undefined Read as undefined. Write as zero. [4] MBERRINTRENB R/W 0y0 AHB master error interrupt enable 0y0: Disable 0y1: Enable [3] VCOMPINTRENB R/W 0y0 Vertical sync. interrupt enable 0y0: Disable 0y1: Enable [2] LNBUINTRENB R/W 0y0 Next base address update interrupt enable 0y0: Disable 0y1: Enable [1] FUFINTRENB R/W 0y0 FIFO underflow interrupt enable 0y0: Disable 0y1: Enable [0] - - Undefined Read as undefined. Write as zero. LCDIMSC is the interrupt enable register. Setting the bits in this register passes the corresponding values in the original interrupt LCDRIS bit to the LCDMIS register. TMPA910CRA- 680 2010-06-02 TMPA910CRA 8. LCDControl (LCDC Control Register) Address = (0xF420_0000) + (0x001C) Bit Bit Symbol Type Reset Description Value [31:17] - - Undefined [16] WATERMARK R/W 0y0 Read as undefined. Write as zero. LCD DMA FIFO watermark level 0y0:Requests DMA when space of 4 words or more occurs in either of the two FIFOs. 0y1:Requests DMA when space of 8 words or more occurs in either of the two FIFOs. [15:14] - - Undefined Read as undefined. Write as zero. [13:12] LcdVComp R/W 0y00 Interrupt occurrence timing 0y00: At vertical sync start 0y01: At back porch start 0y10: At display data start 0y11: At front porch start [11] Reserved R/W 0y0 Write as 1. [10] Reserved R/W 0y0 Write as 0. [9] Reserved R/W 0y0 Write as 0. [8] BGR R/W 0y0 BGR system selected RGB 0y0: RGB normal output 0y1: BGR red/blue swap [7] LcdDual R/W 0y0 STN panel select 0y0: Single panel LCD 0y1: Dual panel LCD [6] LcdMono8 R/W 0y0 Selects the monochrome STN LCD parallel bit. 0y0: 4-bit interface for monochrome LCD 0y1: 8-bit interface for monochrome LCD [5] LcdTFT R/W 0y0 Selects the panel used for LCD. 0y0: STN panel 0y1: TFT panel [4] LcdBW R/W 0y0 Selects monochrome or color for STN LCD. 0y0: Color 0y1: Monochrome [3:1] LcdBpp R/W 0y000 Number of LCD bits per pixel: 0y000 = 1 bpp 0y001 = 2 bpp 0y010 = 4 bpp 0y011 = 8 bpp 0y100 = 16 bpp 0y101 = 24 bpp (TFT panel only) 0y110 = Reserved 0y111 = Reserved [0] LcdEn R/W 0y0 LCD controller enable: 0y0: Disable 0y1: Enable TMPA910CRA- 681 2010-06-02 TMPA910CRA [Description] a. <WATERMARK> LCD DMA FIFO watermark level 0y0: Requests DMA when space of 4 words or more occurs in either of the two FIFOs. 0y1: Requests DMA when space of 8 words or more occurs in either of the two FIFOs. b. <LcdVComp> 0y00: At vertical sync start 0y01: At back porch start 0y10: At display data start 0y11: At front porch start Following timing chart shows interrupt generation timing . Signal name Vertical sync signal LCLFP VSW + 1 (Vertical sync pulse) VBP LPP + 1 VFP (Vertical back porch) (Number of lines per panel) (Vertical front porch) Panel clock LCLLP Panel data Vertical non-data area Vertical non-data area LCD [23:0] LcdVcomp interrupt timing (This timing delay about 3 HCLK from LCLLP edge) Vertical sync start Back porch start Display data start Front porch start TMPA910CRA- 682 2010-06-02 TMPA910CRA c. <BGR> BGR system selected RGB 0y0: RGB normal output 0y1: BGR red/blue swap The swap function is to replace blue with red data as shown in following table. Intended bit <BGR>=0 <BGR>=1 [15] Brightness bits Brightness bits [14:10] B[4:0] R[4:0] [9:5] G[4:0] G[4:0] [4:0] R[4:0] B[4:0] However, this MCU has a LCDDA function. When using this function, the actual alignment of data is defined as shown in following table. Intended bit Data content [15:11] B[4:0] [10:5] G[5:0] [4:0] R[4:0] Therefore, the LCDDA does not allow the use of the swap function. d. <LcdDual> STN panel select 0y0: Single panel LCD 0y1: Dual panel LCD e. <LcdMono8> This shows that monochrome LCD uses the 8-bit interface. This bit controls which of 4-bit or 8-bit parallel interface is used for monochrome STN LCD. In other modes, 0 needs to be programmed. f. <Lcd TFT> 0y0 = Shows that LCD is STN display using the gray scaler. 0y1 = Shows that LCD is TFT using no gray scaler. g. <LcdBW> This shows that STN LCD is monochrome (black and white). 0y0 = Shows that STN LCD is color. 0y1 = Shows that STN LCD is monochrome. This bit has no meaning in the TFT mode. TMPA910CRA- 683 2010-06-02 TMPA910CRA h. <Lcd Bpp> This bit set the Number of LCD bits per pixel. 0y000 = 1 bpp 0y001 = 2 bpp 0y010 = 4 bpp 0y011 = 8 bpp 0y100 = 16 bpp 0y101 = 24 bpp (TFT panel only) 0y110 = Reserved 0y111 = Reserved i. <LcdEn> This bit set operation of the LCD controller. 0y0 = Stop The LCD signals LCLLP, LCLCP, LCLFP, LCLAC, and LCLLE are disabled (Fixed to "L"). 0y1 = Operate The LCD signals LCLLP, LCLCP, LCLFP, LCLAC, and LCLLE are enabled (active). Note1: After each regsiter of LCDC have been completely prepared, set <LcdEn> to 1. Note2: If you set to the stop state (set to 0), LCD signals (LCLLP, LCLCP, LCLFP, LCLAC and LCLLE) are always fixed to "L". Please note the signal set by negative-true logic. TMPA910CRA- 684 2010-06-02 TMPA910CRA 9. LCDRIS (Raw Interrupt Status Register) Address = (0xF420_0000) + (0x0020) Bit Bit Symbol Type Reset Description Value [31:5] - - Undefined Read as undefined. [4] MBERROR RO 0y0 Request for AMBA AHB master bus error interrupt 0y0: No 0y1: Yes [3] Vcomp RO 0y0 Request for vertical sync. interrupt 0y0: No 0y1: Yes [2] LNBU RO 0y0 Request for LCD next address base update interrupt 0y0: No 0y1: Yes [1] FUF RO 0y0 Request for FIFO underflow interrupt 0y0: No 0y1: Yes - [0] - Undefined Read as undefined. [Description] a. <MBERROR > AMBA AHB master bus error status. This is set if the AMBA AHB master detects a bus error response from a slave. b. <Vcomp> Vertical sync. This is set if any one of the four vertical areas selected from the LCDControl [13:12] register reaches the timing. c. <LNBU> LCD next address base update. This depends on the mode and is set when the current base address register is updated by the net address register properly. d. <FUF> FIFO underflow. This is set if either higher- or lower-order DMA FIFO is read and accessed when it is empty, which is the condition of triggering the underflow condition. TMPA910CRA- 685 2010-06-02 TMPA910CRA 10. LCDMIS (Masked Interrupt Status Register) LCDMIS is a read-only register. This register serves as the logical AND for each bit of the LCDRIS register and the LCDIMSC (Enable) register. The logical ORs of all interrupts are given to the system interrupt controller. Address = (0xF420_0000) + (0x0024) Bit Bit Symbol Reset Type Description Value [31:5] - - Undefined Read as undefined. Write as zero. [4] MBERRORINTR RO 0y0 AMBA AHB master bus error status bit 0y0: Clear 0y1: Interrupt requested [3] VCOMPINTR RO 0y0 Vertical sync. interrupt status bit 0y0: Clear 0y1: Interrupt requested [2] LNBUINTR RO 0y0 LCD next address base update status bit 0y0: Clear 0y1: Interrupt requested [1] FUFINTR RO 0y0 FIFO underflow status bit 0y0: Clear 0y1: Interrupt requested - [0] - Undefined Read as undefined. 11. LCDICR (Interrupt Clear Register) Address = (0xF420_0000) + (0x0028) Bit Bit Symbol Type Reset Description Value [31:5] - - Undefined Read as undefined. Write as zero. [4] Clear MBERROR WO 0y0 Clears AMBA AHB master bus error interrupt request flags Clear Vcomp WO 0y0: No change 0y1: Clear [3] 0y0 Clears vertical sync. interrupt request flags. 0y0: No change 0y1: Clear [2] Clear LNBU WO 0y0 Clears LCD next address base update interrupt request flags. 0y0: No change 0y1: Clear [1] Clear FUF WO 0y0 Clears FIFO underflow interrupt request flags. 0y0: No change 0y1: Clear [0] - - Undefined Read as undefined. Write as zero. TMPA910CRA- 686 2010-06-02 TMPA910CRA 12. LCDUPCURR (Upper Panel Current Address Value Registers) Address = (0xF420_0000) + (0x002C) Bit [31:0] Bit Symbol LCDUPCURR Type RO Reset Description Value 0x00000000 Approximate values of higher-order panel data DMA addresses 13. LCDLPCURR (Lower Panel Current Address Value Registers) Address = (0xF420_0000) + (0x0030) Bit [31:0] Bit Symbol LCDLPCURR Type RO Reset Description Value 0x00000000 Approximate values of lower-order panel data DMA addresses The LCDUPCURR register and the LCDLPCURR register retain the approximate values of higher- and lower-order panel data DMA addresses during read. These registers can change all the time. Be careful when using them. TMPA910CRA- 687 2010-06-02 TMPA910CRA 14. LCDPalette (Color Palette Register) One word (32 bits) of palette RAM data equals to two pixels of data. Therefore, the lowest-order bit of pixel data is used to select either the higher 16 bits or lower 16 bits of the palette RAM. A palette structured with R:5 bits, G:5 bits, B:5 bits , and brightness bits is structured with a dual port RAM of 128 x 32 bits. Therefore, two-pixel entry into the palette can be written in 1 word. In the TFT mode, all palette data is used; in the monochrome STN mode, only red palette R[4:1] is used (bit0 not used); in the STN color mode, red, green, and blue [4:1] are used (bit0 not used). To support the BGR data system, this red and blue pixel data can be swapped using the control register bit. In the 16 / 24 bpp TFT mode, palettes are bypassed so that the pixel serializer's output can be directly used as TFT panel data. A RAM palette supports 256 entries x 16 bits at maximum. Therefore, TFT and color STN palettes can support up to 8-bpp data. Address = (0xF420_0000) + ((0x0200) to (0x03FC)) Bit Bit Symbol [31] I Type R/W Reset Description Value 0y0 Brightness/unused [30:26] B[4:0] R/W 0y00000 Blue palette data setting [25:21] G[4:0] R/W 0y00000 Green palette data setting [20:16] R[4:0] R/W 0y00000 Red palette data setting [15] I R/W 0y0 Brightness/unused [14:10] B[4:0] R/W 0y00000 Blue palette data setting [9:5] G[4:0] R/W 0y00000 Green palette data setting [4:0] R[4:0] R/W 0y00000 Red palette data setting [Description] a. <I> Brightness bit. Using as the LSB of R, B, and B inputs to 6:6:6 TFT display, this bit can set two ways of brightness in each color. Doubling the number of colors, the data becomes 64 K. b. <B> Blue palette data. c. <G> Green palette data. d. <R> Red palette data. For STN display, only four MSB bits (bit 4:1) are used. For monochrome display, only red palette data is used. All palette registers are arranged with the same bits. TMPA910CRA- 688 2010-06-02 TMPA910CRA 3.19.3.1 Multiplexing LCD Panel Signals While LCLLP, LCLAC, LCLFP, LCLCP, and LCLLE are common, the LCLD [23:0] bus has the eight operation modes supporting the following: * TFT 24-bit interface * TFT 16-bit interface * Color STN single panel * Color STN dual panel * 4-bit monochrome STN single panel * 4-bit monochrome STN dual panel * 8-bit monochrome STN single panel * 8-bit monochrome STN dual panel Note: CUSTN = Color STN dual higher-order panel data signal / Color STN single panel data signal CLSTN = Color STN dual lower-order panel data signal MUSTN = Monochrome STN dual higher-order panel data signal / Monochrome STN single panel data signal MLSTN = Monochrome STN dual lower-order panel data signal TMPA910CRA- 689 2010-06-02 TMPA910CRA Table 3.19.5 LCD TFT panel signal multiplexing [TFT 24bit Interface] External pin Color bit allocation VRAM bit allocation Pallet & RGB-BGR conversion 32bit bus RAM Address 16bit bus RAM Data bit Address Data bit D31 (dummy) D15 (dummy) D30 (dummy) D14 (dummy) D29 (dummy) D13 (dummy) D28 (dummy) D12 (dummy) D27 (dummy) D11 (dummy) D26 (dummy) D10 (dummy) D25 (dummy) D9 (dummy) D24 (dummy) CLD[23] BLUE[7] D23 CLD[22] BLUE[6] D22 D6 CLD[21] BLUE[5] D21 D5 CLD[20] BLUE[4] D20 D4 n+2 D8 (dummy) D7 CLD[19] BLUE[3] D19 D3 CLD[18} BLUE[2] D18 D2 D17 D1 D16 D0 CLD[17] BLUE[1] CLD[16] BLUE[0] CLD[15] GREEN[7] CLD[14] GREEN[6] CLD[13] Color Pallet Bypass n D15 D15 D14 D14 GREEN[5] D13 D13 CLD[12] GREEN[4] D12 D12 CLD[11] GREEN[3] D11 D11 CLD[10] GREEN[2] D10 D10 CLD[9] GREEN[1] D9 D9 CLD[8] GREEN[0] D8 CLD[7] RED[7] D7 CLD[6] RED[6] D6 D6 CLD[5] RED[5] D5 D5 CLD[4] RED[4] D4 D4 CLD[3] RED[3] D3 D3 CLD[2] RED[2] D2 D2 CLD[1] RED[1] D1 D1 CLD[0] RED[0] D0 D0 RGB- BGR Support TMPA910CRA- 690 D8 n D7 2010-06-02 TMPA910CRA Table3.19.6 LCD TFT panel signal multiplexing [TFT 16bit Interface] External pin Color bit allocation VRAM bit allocation Pallet & RGB-BGR conversion 32bit bus RAM Address 16bit bus RAM Data bit Address Data bit CLD[0] BLUE[4] D31 D15 CLD[17] BLUE[3] D30 D14 CLD[16] BLUE[2] D29 D13 CLD[15] BLUE[1] D28 D12 CLD[14] BLUE[0] D27 D11 CLD[13] GREEN[5] D26 D10 CLD[11] GREEN[4] D25 D9 CLD[10] GREEN[3] D24 D8 n+2 CLD[9] GREEN[2] D23 D7 CLD[8] GREEN[1] D22 D6 CLD[7] GREEN[0] D21 D5 CLD[5] RED[4] D20 D4 CLD[4] RED[3] D19 D3 CLD[3] RED[2] D18 D2 CLD[2] RED[1] D17 D1 D16 D0 D15 D15 CLD[1] RED[0] Color Pallet Bypass n CLD[0] BLUE[4] CLD[17] BLUE[3] D14 D14 CLD[16] BLUE[2] D13 D13 CLD[15] BLUE[1] D12 D12 CLD[14] BLUE[0] D11 D11 CLD[13] GREEN[5] D10 D10 CLD[11] GREEN[4] D9 D9 CLD[10] GREEN[3] D8 RGB-BGR Not Support D8 n CLD[9] GREEN[2] D7 D7 CLD[8] GREEN[1] D6 D6 CLD[7] GREEN[0] D5 D5 CLD[5] RED[4] D4 D4 CLD[4] RED[3] D3 D3 CLD[3] RED[2] D2 D2 CLD[2] RED[1] D1 D1 CLD[1] RED[0] D0 D0 Note: In the case of using 16bitTFT, Intensity bit can't be used. And the swap of RGB and BGR isn't supported. TMPA910CRA- 691 2010-06-02 TMPA910CRA Table3.19.7 LCD STN panel signal multiplexing External Color Color 4-bit mono 4-bit mono 8-bit mono 8-bit mono pin STN STN STN single STN dual STN single STN dual single dual panel panel panel panel panel panel CLD[23] Reserved Reserved Reserved Reserved Reserved Reserved CLD[22] Reserved Reserved Reserved Reserved Reserved Reserved CLD[21] Reserved Reserved Reserved Reserved Reserved Reserved CLD[20] Reserved Reserved Reserved Reserved Reserved Reserved CLD[19] Reserved Reserved Reserved Reserved Reserved Reserved CLD[18} Reserved Reserved Reserved Reserved Reserved Reserved CLD[17] Reserved Reserved Reserved Reserved Reserved Reserved CLD[16] Reserved Reserved Reserved Reserved Reserved Reserved CLD[15] Reserved CLSTN[7] Reserved Reserved Reserved MLSTN[7] CLD[14] Reserved CLSTN[6] Reserved Reserved Reserved MLSTN[6] CLD[13] Reserved CLSTN[5] Reserved Reserved Reserved MLSTN[5] CLD[12] Reserved CLSTN[4] Reserved Reserved Reserved MLSTN[4] CLD[11] Reserved CLSTN[3] Reserved MLSTN[3] Reserved MLSTN[3] CLD[10] Reserved CLSTN[2] Reserved MLSTN[2] Reserved MLSTN[2] CLD[9] Reserved CLSTN[1] Reserved MLSTN[1] Reserved MLSTN[1] CLD[8] Reserved CLSTN[0] Reserved MLSTN[0] Reserved MLSTN[0] CLD[7] CUSTN[7] CUSTN[7] Reserved Reserved MUSTN[7] MUSTN[7] CLD[6] CUSTN[6] CUSTN[6] Reserved Reserved MUSTN[6] MUSTN[6] CLD[5] CUSTN[5] CUSTN[5] Reserved Reserved MUSTN[5] MUSTN[5] CLD[4] CUSTN[4] CUSTN[4] Reserved Reserved MUSTN[4] MUSTN[4] CLD[3] CUSTN[3] CUSTN[3] MUSTN[3] MUSTN[3] MUSTN[3] MUSTN[3] CLD[2] CUSTN[2] CUSTN[2] MUSTN[2] MUSTN[2] MUSTN[2] MUSTN[2] CLD[1] CUSTN[1] CUSTN[1] MUSTN[1] MUSTN[1] MUSTN[1] MUSTN[1] CLD[0] CUSTN[0] CUSTN[0] MUSTN[0] MUSTN[0] MUSTN[0] MUSTN[0] TMPA910CRA- 692 2010-06-02 TMPA910CRA 3.19.4 LCD Controller Option Function (LCDCOP) This LSI, which incorporates an LCD controller, is equipped with the following functions as option functions: Table 3.19.8 Option function table Function Description * PR0CR register function The internal signal CLFP (vertical sync signal) Can be outputed from LPRG0 pin by 1 to 16 clock s(LCLCP) Delay PR1CR register function * General-purpose port output function from LPRG0 pin * The internal signal CLLP (horizontal sync signal) Can be outputed from LPRG1 pin by 1 to 127 clocks (LCLCP) Delay * Line invert output * Frame invert output * General-purpose port output function from LPRG1 pin * The internal signal CLLP (horizontal sync signal) Can be outputed from LPRG2 Can output the signal inverted by 1 to 256 clocks (LCLLP) from LCLAC pin. Can output the signal inverted by every LCLFP from LCLAC pin. PR2CR register function pin by 1 to 255 clocks (LCLCP) Delay * 3.19.4.1 General-purpose port output function from LPRG2 pin Block Diagrams The block diagram of LCDC and LCDCOP is shown below: CLPOWER LCDC Open CLFP LCLFP CLLP LCLLP CLAC LCLAC CLCP LCLCP LCDCOP (Optional Circuit) CLLE CLD [23:0] LCLLE LD[23:0] LPRG0 LPRG1 LPRG2 AHB Bus APB Bus Figure 3.19.5 LCDCOP block diagram TMPA910CRA- 693 2010-06-02 TMPA910CRA 3.19.4.2 Description of Operation As an LCDC option function, additional signals of three terminals can be output. Using this circuit broadens the range of connectable LCD drivers (LCD modules) and can omit external circuits. First of all, as the biggest precondition, this LCDC option circuit, a circuit that operates independently from the main unit LCDC operation, may not operate normally (not output normal waveforms) depending on LCDC settings. Please use it after fully understanding operation limitations. Note that this chapter does not describe LCDC operation. Refer to the chapter on LCDC for LCDC operation. 3.19.4.3 Basic Operation / Basic Waveforms 1 (LPRG0 control) (1) A signal that is generated by delaying the LCLFP signal by 1 to 16 clocks (4 bits) of LCLLP can be output from the LPRG0 pin. (2) The LPRG0 pin can be used as a general-purpose output port. LCLFP LCLLP LCLAC LCLCP LCLCP' LCLLE LD [23:0] LCLFP' LPRG 0 (LCLFP Delay) Figure 3.19.6 Detailed timing TMPA910CRA- 694 2010-06-02 TMPA910CRA 3.19.4.4 Basic Operation / Basic Waveforms 2 (LPRG1 control) (1) A signal that is generated by delaying the LCLLP signal by 1 to 127 clocks (7 bits) of LCLCP can be output from the LPRG1 pin (This is valid when you use LCD panel that timing is difference). (2) An AC signal that is inverted (line inversion) every 1 to 256 clocks of LCLLP can be output from the LCLAC pin. (3) An AC signal that is inverted (frame inversion) based on LCLFP can be output from the LCLAC pin. LCLFP LCLLP LCLCP LCLLP LCLCP LPRG1 (LCLLP delay) LCLFP LCLLP LCLAC LCLAC' LCLAC'' LCLCP LCLLE LD [23:0] Figure 3.19.7 Detailed timing chart TMPA910CRA- 695 2010-06-02 TMPA910CRA 3.19.4.5 Basic Operation / Basic Waveforms 3 (LPRG2 control) (1) A signal that is generated by delaying the LCLLP signal by 1 to 255 clocks (8 bits) of LCLCP can be output from the LPRG2 pin (This is valid when you use LCD panel that timing is difference). LCLFP LCLLP LCLCP LCLLP LCLCP LPRG2 (LCLLP delay) TMPA910CRA- 696 2010-06-02 TMPA910CRA 3.19.4.6 Description of Registers The following lists the registers: Base address = 0xF00B_0000 Register Address Name (base+) Description PR0CR 0x0000 LPRG 0 signal Control register PR1CR 0x0004 LPRG 1 signal Control register PR2CR 0x0008 LPRG 2 signal Control register TMPA910CRA- 697 2010-06-02 TMPA910CRA 1. PR0CR (LPRG0 signal Control Register) Address = (0xF00B_0000) + (0x0000) Bit Bit [31:28] Symbol VERCODE Type RO Reset Description Value 0y0101 Read only Read data is always 0y0101. [27:10] - - Undefined Read as undefined. Write as zero. [9] LIPC R/W 0y0 LCLCP signal logic (Set to the same settings as LCDTiming2 [13] of LCDC.) 0y0: Rising sync 0y1: Falling sync [8] LIHS R/W 0y0 LCLLP signal logic (Set to the same settings as LCDTiming2 [12] of LCDC.) 0y0: "H" active 0y1: "L" active [7] LPR0FIX R/W 0y0 LPRG0 signal fixed output 0y0: Fixed data Disable 0y1: Fixed data Enable [6] LPR0FIXD R/W 0y0 LPRG0 fixed signal 0y0: Fixed at "L" 0y1: Fixed at "H" [5:2] DLY0TIME[3:0] R/W 0y0000 Delay time setting of LPRG0 signal(Number of LCLLP counts) 0y0000 to 0y1111 (1 count to 16 counts) [1] Reserved R/W 0y0 [0] LPR0EN R/W 0y0 Read as undefined. Write as zero. LPRG0 signal Enable 0y0: Invalid (Note) 0y1: Signal output after processed Note:Original LCPFP signal is delayed 3 HCLK, and output from LPRG0 pin. TMPA910CRA- 698 2010-06-02 TMPA910CRA 2. PR1CR (LPRG 1 signal Control Register) Address = (0xF00B_0000) + (0x0004) Bit Bit Symbol Type Reset Description Value [31:20] - - Undefined [19] LPR1FIX R/W 0y0 Read as undefined. Write as zero. LPRG1 signal fixed output 0y0: Fixed data Disable 0y1: Fixed data Enable [18] LPR1FIXD R/W 0y0 LPRG1 fixed signal data 0y0: Fixed at "L" 0y1: Fixed at "H" [17:10] EN1TIME[7:0] R/W 0x00 The invert time setting of LCLAC (Number of LCLLP counts) 0x00 to 0xFF (1 count to 256 counts) Line AC output of LCLAC [9:3] DLY1TIME[6:0] R/W 0x00 Delay time setting of LPRG1 (Number of LCLCP counts) 0x01 to 0x7F (1 count to 127 counts) Note: 0x00 setting is prohibited [2:1] ALTEN[1:0] R/W 0y00 AC signal output from LCLAC pin 0y00: normal LCLAC output 0y01: line invert output 0y10: Frame invert output 0y11: Reserved [0] LPR1EN R/W 0y0 LPRG1 signal Enable 0y0: Invalid (Note) 0y1: Signal output after processed Note: Original LCLLP signal is delayed 3 HCLK, and output from LPRG1 pin. TMPA910CRA- 699 2010-06-02 TMPA910CRA 3. PR2CR (LPRG 2 signal Control Register) Bit Bit Symbol Type Reset Address = (0xF00B_0000) + (0x0008) Description Value [31:22] - - Undefined Read as undefined. Write as zero. [21] Reserved RO 0y1 Read as undefined. Write as zero. [20] Reserved RO 0y1 Read as undefined. Write as zero. [19] LPR2FIX R/W 0y0 LPRG2 signal fixed output 0y0: Fixed data Disable 0y1: Fixed data Enable [18] LPR2FIXD R/W 0y0 LPRG2 fixed signal data 0y0: Fixed at "L" 0y1: Fixed at "H" [17] - - Undefined Read as undefined. Write as zero. [16] Reserved R/W 0y0 Read as undefined. Write as zero. [15] Reserved R/W 0y0 Read as undefined. Write as one. [14] Reserved R/W 0y0 [13] LPRGSEL R/W 0y0 Read as undefined. Write as zero. LPRG1/LPRG2 signal function selection 0y0: Output the CLLP signal that is delayed every CLCP 0y1: Output as PORT function [12] Reserved R/W 0y0 [11] LIVS R/W 0y0 Read as undefined. Write as zero. Set CLFP signal active phase 0y0: "H" is active 0y1: "L" is active [10] Reserved R/W 0y0 [9:2] DLY2TIME7:0 R/W 0x00 Read as undefined. Write as zero. Set the delay time of LPRG2 signal (LCLCP counts) 0x01 to 0xFF(1 count to 255 counts) Note: 0x00 setting is prohibited [1] Reserved R/W 0y0 [0] LPR2EN R/W 0y0 Read as undefined. Write as zero. LPRG2 signal Enable 0y0: Invalid (Note) 0y1: Signal output after processed Note: Original LCLLP signal is delayed 3 HCLK, and output from LPRG2 pin. TMPA910CRA- 700 2010-06-02 TMPA910CRA 3.20 LCD Data Process Accelerator (LCDDA) This microcontroller incorporates the LCD Data Process Accelerator function (LCDDA) as an auxiliary function for display. The LCDDA supports the scaler function that scales up/down display data including the filter (Bi-Cubic method) processing, and the image rotation function that rotates and mirror-inverts display data function, as well as the function of superimposing two images (Blend, Picture in Picture, Superimposing font). The following lists the functions: Table 3.20.1 LCDDA functions Function Description Scaler function Scale up: Can scale up to the magnification of 256/n: (n = 1 to 255). Can scale up independently in horizontal/vertical directions. Filtering by Bi-Cubic method is possible in scaled up images. Scale down: Can scale down to the magnification of 256/(n x m): (n = 1 to 255, m = 1 to 16). Image rotation function Can scale down independently in horizontal/vertical directions. Filtering by Bi-Cubic method is possible in scaled down images. 90 / 180 / 270 / horizontal mirror reversal / vertical mirror reversal possible Image Blend function Function of superimposing two images (Picture in Picture) Superimposing (-Blend) possible adjusting the gray level of two images Font Draw function for Font Data represented in two-valued data (monochrome) These circuits, which operate as other circuits completely separate from the LCD controller, all use the Copy Back (write back) method. Image data is processed and the data is written into the display Ram of the LCDC. Then the LCDC displays the processed data. LCD Panel (LCDD) READ VRAM area LCDC WRITE READ Source image 0 LCDDA Source image 1 READ TMPA910CRA RAM Figure 3.20.1 Image of LCDDA operation (Example of Blend function) TMPA910CRA- 701 2010-06-02 TMPA910CRA 3.20.1 Block Diagrams The block diagram of LCDDA is shown below: Interrupt request INTS[20] LCDDA Interrupt (0xF800_4000) Built-in RAM-0: 16KB control 128bit bus Expansion with filter (Read only) ReadFIFO 8wordx2 32bit bus Read/Write Write FIFO 8wordx2 BC_ Expander Signal Select Blend 32bit bus Read/Write Blender LCDDA AHB Master Rotation Reduction DMA request clear (Burst) Destination Address control circuit DMA request clear (Single) Control register DMA request (Burst) LCDDA AHB Slave DMA request (Single) 32bit bus Read/Write AHB bus Figure 3.20.2 LCDDA block diagram The LCDDA is mainly broken down into eight blocks: * "BC_Expander" where scaling up/down is performed using the Bi-Cubic method * "Blender" where Blend processing is performed * "Read FIFO buffer" where source data is accumulated * "Write FIFO buffer" where destination data is accumulated * "Transfer address control circuit" where rotation / simple scaling down processing is performed * "AHB slave block" where the access from the AHB bus to control registers is controlled * "AHB master block" where the data access to the AHB bus is controlled * "Interrupt control block" where interrupts are generated by monitoring processing completion and error occurrence TMPA910CRA- 702 2010-06-02 TMPA910CRA 3.20.2 Description of Operation This section describes the functions that the LCDDA has: 3.20.2.1 Scaler Function Table 3.20.2 Scaler function Function Details of function Description / Standard Scale-up function Scale-up rate/Interpolation data quantity 256/n: (Can set to the magnification of 256/N: N = 1 to 255: Setting to 0 is disabled.) Supportable data format Digital RGB Number of supportable image colors 64-K color (16 bpp) Can set independently in horizontal/vertical directions Note: YUV-format data is not supported. 16-M color (24 bpp) (For 24 bpp, the lower-order 24 bits of 32 bits contain valid data + the higher-order 8 bits contain dummy data.) Note: Monochrome, monochrome gray-level, and the color of other color numbers are not supported. Supportable image size ORG image Horizontal: Max. 510 pixels Vertical: No particular limitations Scale-up image Horizontal: Max. 1024 pixels Vertical: No particular limitations Note: The maximum display size supported by this microcontroller's LCDC differs with the display panel. Please refer to section 3.19 LCD controller. Scale-down function Correction function Period point correction function, termination point correction function provided Scale-down rate/Interpolation data quantity Can interpolate 255 points of data between original pixels. (Can set independently in horizontal/vertical directions) Can output 255 points of data between original pixels. (Can set to the magnification of 255/N/M: N = 1 to 255, M = 1 to 16) Supportable data format Digital RGB Number of supportable image colors 64-K color (16 bpp) Note: YUV-format data is not supported. 16-M color (24 bpp) (For 24 bpp, the lower-order 24 bits of 32 bits contain valid data + the higher-order 8 bits contain dummy data.) Monochrome, monochrome gray-level, and the color of other color numbers are not supported. Supportable image size ORG image Horizontal: Max. 511 pixels Vertical: No particular limitations Scale-up image Horizontal: Max. 1024 pixels Vertical: No particular limitations Note: The maximum display size supported by this microcontroller's LCDC differs with the display panel. Please refer to section 3.19 LCD controller. Correction function Period point correction function, termination point correction function provided TMPA910CRA- 703 2010-06-02 TMPA910CRA 3.20.2.2 Mechanism of Scaler Processing 1) Basic Configuration The scaler function of the LCDDA can insert interpolation data of 255 points at maximum between original pixels using the Bi-Cubic method. Original pixel Interpolated pixel Interpolation data is generated using the original pixels of 4 x 4 around the area to be interpolated. Figure 3.20.3 Data interpolation In this method, image data of 256-magnification (8 bits) at maximum is calculated automatically by the H/W, from the image data of the "4 x 4 point" pixels around the area to be interpolated. The pixels of 256 points (including the original pixels) generated from the original pixels can be output at every n_Step. 256Point nPoint 256Point nPoint nPoint nPoint 256Point Figure 3.20.4 Scaling method (Scaling up if the Step number is 1 to 255; scaling down if 257 or more) TMPA910CRA- 704 2010-06-02 TMPA910CRA Address n n+4k Dual Port RAM (16KB) Area0 (Data of SRC image's one line) Area4 Area1 Area5 PortB 128-bit connection n+8k Area2 Area6 Area3 Area7 Read Only LCDDA n+12k Normal Normal PortA 32-bit 32-bit connection Read/Write connection Read/Write AHB Bus Figure 3.20.5 Connection with memory, and basic operation To use the scaler function, original image data (RGB) needs to have been written into the dedicated DualPortRAM. As described earlier, to generate interpolation data, original pixels of 4 x 4 are required. Therefore, the BC_Expander circuit can start generating interpolation data at the point when four lines of original image data become available. The BC_Expander circuit of the LCDDA is connected with the 16-K-byte Dual Port RAM and the 128-bit-width bus (PortB). This 16-K-byte Dual Port RAM, which can be used as a normal RAM, is connected to the AHB bus with the 32-bit-width bus (PortA). In addition, this 16-K-byte Dual Port RAM is divided into 2-Kbyte x 8 areas in which one line of original image data is prepared. (Max 510 pixel: Dummy+510+Dummy). The BC_Expander circuit can start calculation at the point when four lines of data (For example, area 0 to area 3) become available. After that, every time one line of data is added (area 4), four lines of data are prepared again (area 1 to area 4) to start next calculation. In this manner, the area is looped to perform calculation. TMPA910CRA- 705 2010-06-02 TMPA910CRA 3.20.2.3 Correction Processing The scaler function supports the function of correcting sampling points for scaling up/down processing. Using this function can express more natural images. The correction function, if classified broadly, has two functions: the "edge data automatic addition" function and the "sampling correction" function. 1) Edge data automatic addition function As described in the previous section, the original pixels of 4 x 4 around an area to be interpolated are required in the scaler function. Therefore, original pixels cannot be prepared in the pixels' edge area. Dummy data of one line before the first line and one line after the last line or of one row before the first row and one row after the last row needs to be prepared. Dummy data before one row of the first row (Data copy) (Data copy) (Data copy) (Data copy) Data area required Original pixel for data interpolation (Data copy) Data interpolation area (Data copy) Dummy data before one column of the first column This function can prepare this dummy data automatically. TMPA910CRA- 706 2010-06-02 TMPA910CRA The following shows examples of how to set original image data to the dual-port RAM connected to the LCDDA. The dual-port RAM also needs to have dummy data areas for edge processing. Let us set original image data for 24-bit and 16-bit color displays with 510 pixels per line by using the edge data automatic addition function. * The first line is handled as a dummy data area. It is therefore not necessary to set image data at addresses 0xF800_4000 through 0xF800_47FF. * The first and last pixels in the second and subsequent lines are also handled as a dummy data area. Original data: 510 pixels, 24-bit color ; Internal RAM area 0 0xF800_4800 0xF800_4804 0xF800_4FF8 0xF800_4FFC ; Dummy data (no setting is required) ; Valid data (set the first pixel data) ; Valid data (set the last pixel data) ; Dummy data (no setting is required) Original data: 510 pixels, 16-bit color ; Internal RAM area 0 0xF800_4800 0xF800_4802 0xF800_4BFC 0xF800_4BFE 0xF800_4FFC ; Dummy data (no setting is required) ; Valid data (set the first pixel data) ; Valid data (set the last pixel data) ; Dummy data (no setting is required) Note: The maximum number of pixels per line is 510 pixels for both 16-bit color and 24-bit color displays. To scale up or down an image larger than 510 pixels, it is necessary to divide the image. First line (dummy data area) (0xF800_40000xF800_47FF) Last pixel (dummy data area) First pixel (dummy data area) (0xF800_4800) Original data (0xF800_4FFC) 510 x common size 24-bit color Data correction area Figure 3.20.6 Image representation of original data (510 x common size, 24-bit color) TMPA910CRA- 707 2010-06-02 TMPA910CRA 2) Sampling correction function In the scaler function, scaling up/down at a magnification of 256/(n x m) is possible to the number of original pixels (n = 1 to 255, m = 1 to 16). The scaling up method, set with the equation above, creates fractions of decimal places, which creates an error because the actual sampling point is set with integer. Therefore, the accumulated errors in the whole image need to be corrected at an appropriate point. This circuit supports the two correction functions: The "offset function" adds an offset to the first sampling point in the X direction; and the "period correction function," when a set sampling point comes to a certain point, the point is corrected to the original image point. When offset function OFF nPoint nPoint nPoint Sampling point that LCDDA selects Start Original pixel Point Point that LCDDA is possible to sampling The first sampling point is the first pixel of the original pixels When offset function ON Offset value nPoint nPoint nPoint Start Point The first sampling point is the fifth pixel including the interpolation data (4,0). Figure 3.20.7 Offset function TMPA910CRA- 708 2010-06-02 TMPA910CRA When period correction function OFF nPoint nPoint Midpoint The subsequent sampling points are also When period correction function ON nPoint calculated from the after-corrected sampling points. nPoint Midpoint Not selected Correct the sampling point to the original point forcedly. Figure 3.20.8 Period correction function TMPA910CRA- 709 2010-06-02 TMPA910CRA Scaling up processing examples The following describes the examples of how to establish the setting for scaling up processing including correction processing: * Number of original pixels in the X direction: OX pixel * Number of after-scaled-up pixels in the X direction: GX pixel (Sampling cycle) =(Maximum number of interpolatable pixels) / (Number of after-scaled-up pixels) = {(OX-1) x 256} / GX Example 1: For scaling up 128 pixels to 256 pixels (127 x 256) / 256 = (32512) / 256 = 127 Example 2: For scaling up 128 pixels to 255 pixels (127 x 256) / 255 = (32512) / 255 = 127.49... Sampling cycles are specified in integers by dropping the fractional portion. This results in the same sampling cycle (127 = 0x7F) for Examples 1 and 2. When data is sampled at every 127 pixels, sampling points occur as shown below. Example 1 sampling point First point: 0 Second point: 127 Third point: 254 254th point: 32258 255th point: 32385 -------------------------------------------256th point: 32512 In Example 1, the 256th sampling point is 32512, which is the last pixel of the original image. Since Example 2 uses the same sampling cycle, the 255th sampling point is 32385. Therefore, the pixels after 32385 are not used and discarded. TMPA910CRA- 710 2010-06-02 TMPA910CRA Example 2 Sampling points First point: 0 Second point: 127 Third point: 254 254th point: 32258 255th point: 32385 * Pixels 32386 to 32512 are not used. This produces a slightly off-center scaled-up image shifted to the left. To realize more natural-looking scaling up, the correction function is utilized. TMPA910CRA- 711 2010-06-02 TMPA910CRA [Offset correction example] The offset correction function adds an offset to the first sampling point so that unused pixel points are evened out from the center. Move the first sampling point to move all the sampling points to the center. Offset half of the difference between the last sampling point (255th point) and the last generable sampling point. Example of simple offset correction (using Example 2 described earlier) (Offset correction value) =Maximum number of interpolatable pixelsSampling cycle after dropping the fractional portionxGX/ 2 = (32512-32385) / 2 = 63.5 Since the offset value in the X direction must be an integer, it is set to 63 (oct) = 3F (hex). Likewise, the offset value in the Y direction is set to 63 (oct) = 3F (hex). TMPA910CRA- 712 2010-06-02 TMPA910CRA 3.20.2.4 Blend Processing Function Table 3.20.3 Blend function Function BLEND function Details of function BLEND Color + monochrome Description / Standard Settable in 256 levels (0 to 255) for each image and specifically for RGB BLEND Two-valued (monochrome) data, FONT (1) data, and data other than FONT (0) can be each converted into 16-bit color RGB on the palette. Font Superimposing monochrome font onto image Supportable data format Digital RGB Note: YUV-format data is not supported. Number of supportable image colors 64-K color (16 bpp) 16-M color (24 bpp) (For 24 bpp, the lower-order 24 bits of 32 bits contain valid data + the higher-order 8 bits contain dummy data.) Note: Monochrome, monochrome gray-level, and the color of other color numbers are not supported. Supportable image size Horizontal: Max. 1024 pixels Vertical: Max. 1024 pixels Note: The maximum display size supported by this microcontroller's LCDC differs with the display panel. Please refer to section 3.19 LCD controller. TMPA910CRA- 713 2010-06-02 TMPA910CRA 3.20.2.5 Mechanism of BLEND Processing The BLEND processing of the LCDDA first breaks each data of two images into the basis of pixels and then breaks them into the basis of RGB (8 bits each: 24 bits in total). This broken down RGB data is each weighted on a scale of 256 (0x00/0x100 to 0xFF/0x100) to output the addition result data. Source 0 pixel: RS0:, GS0:, BS0: Source 1 pixel: RS1:, GS1:, BS1: Weight assigned for Source 0 LDADRSRC0<RDRSRC0[7:0]>: RS0RATIO:, LDADRSRC0<GDRSRC0[7:0]>: GS0RATIO:, LDADRSRC0<BDRSRC0[7:0]>: BS0RATIO: Weight assigned for Source 1 LDADRSRC1<RDRSRC1[7:0]>: RS1RATIO:, LDADRSRC1<GDRSRC1[7:0]>: GS1RATIO:, LDADRSRC1<BDRSRC1[7:0]>: BS1RATIO: Calculation method: RDST: = (RS0: x RS0RATIO) + (RS1: x RS1RATIO) GDST: = (GS0: x GS0RATIO) + (GS1: x GS1RATIO) BDST: = (BS0: x BS0RATIO) + (BS1: x BS1RATIO) Thus, setting the sum of two images' weights (Case of R setting: <RDRSRC0[7:0]> <RDRSRC1[7:0]>) so as not to exceed 0x100 is required. Note: If added RGB data exceeds 0x100, correct BLEND cannot be achieved. SRC0 pixel x RS0RATIO x RS1RATIO SRC1 pixel RS0GS0BS0 x GS0RATIO x BS0RATIO x GS1RATIO x BS1RATIO RS1GS1BS1 DST pixel RDSTGDSTBDST Figure 3.20.9 BLEND processing TMPA910CRA- 714 2010-06-02 TMPA910CRA 3.20.2.6 Monochrome Blend Function The monochrome blend function is the function of overwriting the converted data to color data that data defined in monochrome (two-valued). The BLEND of rectangular area and the overwriting font (FONT DRAW) can be possible. An excellent automatic address calculation in continuous writing of font is supported. * Drawable "N x M" FONT defined with serialized addresses continuously in the direction of left right (Calculating the next FONT HOT_POINT (the address in the upper left top position) automatically) FONT data Color (16/24- bits) FONT data Monochrome (1 bit) Automatic calculation for the HOT POINT of the FONT continuing to the right Mdot Ndot TMPA910CRA- 715 2010-06-02 TMPA910CRA 3.20.2.7 Rotation Function Table 3.20.4 Rotation function Function Rotation function Details of function Description / Standard Rotation angle 90 / 180 / 270 / horizontal mirror reversal / vertical mirror reversal Supportable data format Digital RGB Note: YUV-format data is not supported. Number of supportable image colors 64-K color (16 bpp) 16-M color (24 bpp) For 24 bpp, the lower-order 24 bits of 32 bits contain valid data + the higher-order 8 bits contain dummy data. Note: Monochrome, monochrome gray-level, and the color of other color numbers are not supported. Supportable image size Horizontal: Max. 1024 pixels Vertical: Max. 1024 pixels Note: The maximum display size supported by this microcontroller's LCDC differs with the display panel. Please refer to section 3.19 LCD controller. 3.20.2.8 Rotation Processing To perform rotation, the rotation process calculates addresses when the LCDDA reads and copies back original images. A rotation shape is controlled by either incrementing (INCREMENT) or decrementing (DECREMENT) each of the transfer-destination address's start point, the X direction, and the Y direction. First read 90 rotation X-DEC Vertical mirror X-DEC Second read Y-INC Y-INC First write Second write 180 rotation Horizontal mirror Y-DEC Y-DEC X-INC 270 rotation X-DEC Vertical mirror + 90 rotation Y-DEC Y-DEC Horizontal mirror + 90 rotation X-DEC X-INC Y-INC Figure 3.20.10 Rotation processing Note: In Rotation function, all specificated rectangular area are rotated. Threfore, when using Font draw function and Rotation function together, all Fonts and backgrounds is rotated. When using this function, please be careful. TMPA910CRA- 716 2010-06-02 TMPA910CRA 3.20.3 Operation Description of Each Mode This section describes each operation mode of the image synthesis. The LCDDA realizes each mode by combining appropriate original image data and circuits to be used from data sources and circuits shown in the table below. Original Image Data Circuits Used Blender Mode Source0 Source1 Color Expander Converter Image data only Description used for superimposing (Note 2) Transfer BC Address Area Filter Superimposer Control Circuit Image data used for superimposing Scales up or and simple down display transfer data. Performs color conversion. Filters areas Performs to be superimposed. Performs rotation and simple superimposing. scaling down. (Note 2) Note 1: The BC_Expander and Blender cannot be used simultaneously. Note 2: Source0 and Source1 are not used in the scaler mode. The following operation LDACR1<OPMODE[4:0]>. modes are available, TMPA910CRA- 717 which can be selected through 2010-06-02 TMPA910CRA Overwriting image to image Normal mode Overwriting monochrome data to image Monochrome mode Scale up or down image Scaler mode Blend images Blend mode WALK 50% WALK 50% Monochrome reversing is supposed Blend font (binary data) to image Blend monochrome data to image Font draw mode Monochrome Blend mode WALK 50% WALK WALK WALK 50% Monochrome reversing is supposed TMPA910CRA- 718 2010-06-02 TMPA910CRA Operation Mode Description NORMAL mode Performs simple data transfer of image data without color conversion or blended. And the cutout image (rectangular area) is overwritten to the background image. Scaler mode Controls scale up or down image data. Monochrome mode The monochrome cutout image (rectangular area) is overwritten to the background image after expanded color data. Transfer mode that the monochrome (1bit) data is expanded to color data of 16bit/24bit Monochrome invert mode After inverting the monochrome cutout image (rectangular area) data, this data is expanded to the color data and overwriting to the background image. Transfer mode that the inverted monochrome (1bit) data is expanded to color data of 16bit/24bit BLEND mode Blends two color images (16bit/24bit) to Blend Monochrome BLEND mode Blends a monochrome data source and color data. Specified by the monochrome image is converted to color data then the color image is Blended to be used. Monochrome invert BLEND mode Inverting monochrome data, and blends two color images to Blend. This is same as the monochrome blend mode but when converting the monochrome data to color data, the monochrome data is inverted first then being processing. Font draw mode Two images of monochrome source and color data are blended onto color image which is converted only the data of "1" in monochrome data to gray-level This mode is convenient for processing the superimposing and so on. Each operation mode is described in detail on the pages that follow. TMPA910CRA- 719 2010-06-02 TMPA910CRA 1. NORMAL mode This is a simple data transfer mode. This mode is used for transfers including: Simple image transfer from S1 (source image 1) color original images Scaled-down transfer by simple thinning-out from S1 color original images Rotation transfer of image data from S1 color original images Original Image Data Circuits Used Blender NORMAL Source0 Color Expander Converter Description Used/Not used Transfer BC Source1 Image data only Image data used Scales up or used for for superimposing down display superimposing and simple transfer data. Not used (Internal or external Used Not used Performs color conversion. Not used Address Area Filter Superimposer Filters areas Performs to be superimposed. Not used superimposing. Control Circuit Performs rotation and simple scaling down. Not used Used RAM can be used.) Application example: The NORMAL mode can be used to display a color image in another color image (Picture In Picture). It can also be used for simple DMA transfer. LCD panel * Can be used with simple scaling down and rotation. * Cannot be used with BC Expander. Source image 1 READ VRAM area LCDC Source image 1 WRITE LCDDA Source image 1 READ TMPA910CRA RAM TMPA910CRA- 720 2010-06-02 TMPA910CRA 2. Scaler mode This mode scales up or down images by controlling the operation of the BC_Expander circuit. This mode is used such as for: Scaled-up image generation and transfer using Bi-Cubic from S1 color original images Scaled-down image generation and transfer using Bi-Cubic from S1 color original images Scaled-up image generation and rotation transfer using Bi-Cubic from S1 color original images Scaled-down image generation and rotation transfer using Bi-Cubic from S1 color original images Original Image Data Circuits Used Blender Scaler Source0 Source1 Color Expander Converter Image data only Description used for superimposing Used/Not used Not used Image data used for superimposing and simple Transfer BC Scales up or down display Performs color conversion. data. transfer Not used Used Address Area Filter Superimposer Filters areas to be superimposed. Performs superimposing. Cannot be Cannot be Cannot be used used used Control Circuit Performs rotation and simple scaling down. Used Note: In the scaler mode, Source0 and Source1 are not used. This mode assumes that original image data is stored in the dual port RAM (0xF800_4000 in internal RAM-0: 16 KB). Application example: The scaler mode can be used to scale up small images or scale down large images. The Picture In Picture function can also be used in this mode. LCD panel * Can be used with simple scaling down and rotation. * Cannot be used with Blender. READ VRAM area LCDC WRITE Internal RAM LCDDA Scaling up/down LCDC TMPA910CRA READ (Handled by RAM DMAC and CPU) TMPA910CRA- 721 2010-06-02 TMPA910CRA 3. Monochrome mode This mode transfers monochrome source data. This mode is used such as for: Image transfer after converting S1 monochrome data into color Scaled-down transfer by simple thinning-out after converting S1 monochrome data into color Rotation transfer of image data after converting S1 monochrome data into color Original Image Data Circuits Used Blender Monochrome Source0 Color Expander Converter Image data only Description used for superimposing Used/Not used Image data used for superimposing and simple Scales up or down display data. transfer Used Not used Transfer BC Source1 Performs color conversion. Cannot be (Internal or external Used used Address Area Filter Superimposer Filters areas Performs to be superimposing. superimposed. Not used Not used Control Circuit Performs rotation and simple scaling down. Used RAM can be used.) Application example: The monochrome mode can be used to overwrite monochrome onto a color image (Picture In Picture). LCD panel * Can be used with simple scaling down and rotation. Source image 1 * Cannot be used with BC_Expander. READ VRAM area LCDC Source image 1 Color WRITE LCDDA Color conversion Source image 1 READ Monochrome (1bpp) TMPA910CRA RAM TMPA910CRA- 722 2010-06-02 TMPA910CRA 4. Monochrome invert mode This mode inverts and transfers monochrome source data. It is the same as the monochrome mode except that monochrome data is inverted before being converted into color and transferred. This mode is used such as for: Image transfer after converting S1 monochrome data into color Scaled-down transfer by simple thinning-out after converting S1 monochrome data into color Rotation transfer of image data after converting S1 monochrome data into color Original Image Data Circuits Used Monochrome Invert Blender Source0 Color Expander Converter Image data only Description used for superimposing Used/Not used Image data used for superimposing and simple Scales up or down display data. transfer Used Not used Transfer BC Source1 Performs color conversion. Cannot be (Internal or external Used used Address Area Filter Superimposer Filters areas Performs to be superimposed. superimposing. Not used Not used Control Circuit Performs rotation and simple scaling down. Used RAM can be used.) Application example: The monochrome invert mode can be used to overwrite inverted monochrome onto a color image (Picture In Picture). LCD panel * Can be used with simple scaling down and rotation. Source image 1 * Cannot be used with BC_Expander. READ VRAM area LCDC Source image 1 Color WRITE LCDDA Inversion color conversion Source image 1 Monochrome (1bpp) READ TMPA910CRA RAM TMPA910CRA- 723 2010-06-02 TMPA910CRA 5. BLEND mode This mode blends two color (16 bpp/24 bpp) images. This mode is used such as for: Image transfer after blending two color data of S0 and S1 Scaled-down transfer by simple thinning-out after blending two color data of S0 and S1 Rotation transfer of image data after blending two color data of S0 and S1 Original Image Data Circuits Used Blender BLEND Source0 Source1 Color Expander Converter Image data only Description used for superimposing Used/Not used Image data used for superimposing and simple Scales up or down display data. transfer Used Used (Internal or external (Internal or external RAM can be used.) RAM can be used.) Transfer BC Cannot be used Performs color conversion. Not used Address Area Filter Superimposer Filters areas Performs to be superimposed. superimposing. Not used Used Control Circuit Performs rotation and simple scaling down. Used Application example: The BLEND mode enables gradual switching between two color images by gradually changing the blend ratio. LCD panel * Can be used with simple scaling down and rotation. (LCDD) * Cannot be used with BC_Expander. * The two images to be blended must have the same color mode. READ VRAM area LCDC WRITE LCDDA READ Source image 0 Color (16/24bpp) Blending Source image 1 READ Color (16/24bpp) TMPA910CRA RAM TMPA910CRA- 724 2010-06-02 TMPA910CRA 6. Monochrome BLEND mode This mode blends two images of monochrome source and color (16 bpp/24 bpp). This mode is used such as for: Image transfer after blending S0 color data and color-converted S1 monochrome data Scaled-down transfer by simple thinning-out after blending S0 color data and color-converted S1 monochrome data Rotation transfer after blending S0 color data and color-converted SI monochrome data Original Image Data Circuits Used Monochrome Blender BLEND Source0 Color Expander Converter Image data only Description Used/Not Used Transfer BC Source1 Image data used Scales up or used for for superimposing down display superimposing and simple transfer data. Used Used (Internal or external (Internal or external RAM can be used.) RAM can be used.) Performs color conversion. Cannot be Used used Address Area Filter Superimposer Control Circuit Performs rotation and superimposing. simple scaling Performs Filters areas to be superimposed. Not used down. Used Used Note: Monochrome data from Source1 must be used. Application example: The monochrome BLEND mode enables gradual switching between color and monochrome images by gradually changing the blend ratio. When converting monochrome, this mode can be possible to support the superimposing of FONT data but white color only, to set the color of part of data "1" to R:0xFF, G:0xFF and B:0xFF (white color) then 100% blend ratio and 0% blend ratio of converting "0" data. (When background is white color, this method is not corresponded.) LCD panel * Can be used with simple scaling down and rotation. (LCDD) * Cannot be used with BC_ Expander. READ VRAM area LCDC WRITE LCDDA READ Source image 0 Color (16/24bpp) Color conversion Blending Source image 1 READ TMPA910CRA Monochrome (1bpp) RAM TMPA910CRA- 725 2010-06-02 TMPA910CRA 7. Monochrome invert BLEND mode This mode blends two images of monochrome source inverted data and color (16 bpp/24bpp). This mode is the same as the monochrome BLEND mode except that monochrome data is inverted when converted into color. This mode is used such as for: Image transfer after blending S0 color data and color-converted S1 monochrome data Scaled-down transfer by simple thinning-out after blending S0 color data and color-converted S1 monochrome data Rotation transfer after blending S0 color data and color-converted S1 monochrome data Original Image Data Circuits Used Monochrome Blender Invert BLEND Source0 Source1 Color Expander Converter Image data used Image data only Description for superimposing used for and simple superimposing Used/Not used transfer Used Used (Internal or external (Internal or external RAM can be used.) RAM can be used.) Transfer BC Scales up or down display Performs color data. Cannot be used conversion. Used Address Area Filter Filters areas to be superimposed. Not used Superimposer Performs superimposing. Used Control Circuit Performs rotation and simple scaling down. Used Application example: The monochrome invert BLEND mode enables gradual switching between color and monochrome images by gradually changing the blend ratio. LCD panel * Can be used with simple scaling down and rotation. (LCDD) * Cannot be used with BC_ Expander. READ VRAM area LCDC WRITE LCDDA READ Inversion color conversion Source image 0 Color (16/24bpp) Source image 1 READ Monochrome (1bpp) TMPA910CRA RAM TMPA910CRA- 726 2010-06-02 TMPA910CRA 8. Font Draw mode This mode blends two images of monochrome source data and color (16bpp/24bpp). This mode blends that bit is expanded only data "1" which is specified by monochrome image data (S1). This mode is used such as for: Image transfer after blending S0 color data and expanded only data "1" is monochrome data of S1. Scaled-down transfer by simple thinning-out after blending S0 color data and expanded only data "1" is monochrome data of S1. Rotation transfer after blending S0 color data and expanded only data "1" is monochrome data of S1. Note: The expanded bit of color font is used to set the LDAFCPSRC1<RFONT[7:0]>, <GFONT[7:0]> and <BFONT[7:0]>, in this case, the setting must be set to <RFONT[7:0]>= <BFONT[7:0]>. Original Image Data Circuits Used Blender Font draw Source0 Description Used/Not used Source1 Transfer Address BC Expander Image data only Image data used for Scales up or used for superimposing and down display superimposing simple transfer data. Used Used (Internal or external (Internal or external RAM RAM can be used.) can be used.) Cannot be used Color Converter Area Filter Superimposer Performs color Filters areas Performs conversion. to be superimposed. superimposing. Used Not used Used Control Circuit Performs rotation and simple scaling down. Used Application example: The Font Draw mode can be used to overwrite only Font data onto a color image. Note: As this transfer is executed after blending, so please pay attention that the background Font is processed rotation but also the background image is rotated. LCD Panel * Can be used with simple scaling down and rotation. * Cannot be used with BC_ Expander. READ VRAM area LCDC WRITE LCDDA READ Source image 0 Color (16/24bpp) Color conversion Source image 1 Blending READ Monochrome (1bbp) TMPA910CRA RAM TMPA910CRA- 727 2010-06-02 TMPA910CRA 3.20.4 Description of Registers The following lists the SFRs: Base address = 0xF205_0000 Register Address Name (base+) Description LDACR0 0x0000 LCDDA Control Register 0 LDADRSRC1 0x0004 LCDDA Density Ratio of Source 1 Image LDADRSRC0 0x0008 LCDDA Density Ratio of Source 0 Image LDAFCPSRC1 0x000C LCDDA Replaced Font Area Color pallet of Source1 LDAEFCPSRC1 0x0010 LCDDA Replaced Except Font Area Color pallet of Source1 LDADVSRC1 0x0014 LCDDA Delta Value (Read Step) address Register of Source 1 LDACR2 0x0018 LCDDA Control Register 2 LDADXDST 0x001C LCDDA X-Delta Value (Write Step) address Register of Destination LDADYDST 0x0020 LCDDA Y-Delta Value (Write Step) address Register of Destination LDASSIZE 0x0024 LCDDA Source Image Size LDADSIZE 0x0028 LCDDA Destination Image Size LDAS0AD 0x002C LCDDA Source 0 Start Address LDADAD 0x0030 LCDDA Destination Start Address LDACR1 0x0034 LCDDA Control Register1 LDADVSRC0 0x0038 LCDDA Delta Value (Read Step) address Register of Source 0 The LCDDA has 14 types of registers. They are connected to the CPU with the 32-bit bus. TMPA910CRA- 728 2010-06-02 TMPA910CRA 1. LDACR0 (LCDDA Control Register 0) Address = (0xF205_0000) + (0x0000) Bit Bit Symbol Type Reset Description Value [31:22] - - Undefined Read as undefined. Write as zero. [21] ERRINTF RW 0y0 LCDDA processing error flag [20] EINTF RW 0y0 During READ During Write 0y0: No interrupt 0y0: Flag clear 0y1: With interrupt 0y1: Invalid Scaler 1-line processing end interrupt enable (Enabled by Scaler/Rotation function) [19:18] - - Undefined [17] ERRINTM RW 0y0 During READ During Write 0y0: No interrupt 0y0: Flag clear 0y1: With interrupt 0y1: Invalid Read as undefined. Write as zero. LCDDA processing error interrupt MASK 0y0: Interrupt mask 0y1: Interrupt enabled [16] EINTM RW 0y0 LCDDA 1-image processing end interrupt MASK (Enabled by scaler/Rotation function) 0y0: Interrupt mask 0y1: Interrupt enabled [15] BCENYB RW 0y0 Y-direction last LINE data correction (Last dummy line addition) 0y0: OFF 0y1: ON [14] AUTOHP RW 0y0 Automatic calculation of HOT point 0y0: OFF 0y1: ON [13] DMAMD RW 0y0 DMA select 0y0: Single transfer 0y1: Burst transfer [12] DMAEN RW 0y0 DMA enable. 0y0: OFF 0y1: Enable [11] BCENYT RW 0y0 Y-direction front LINE data correction (Front dummy line addition) 0y0: OFF 0y1: ON [10] DTFMT RW 0y0 Display color select 0y0: 16-M color (32 bits = 24 bits enabled + 8bit_dummy) 0y1: 64-K color (16 bits) [9] BCENX RW 0y0 X-direction edge data correction (Right-left dummy row addition) 0y0: OFF 0y1: ON [8] PCEN RW 0y1 Period correction 0y0: OFF 0y1: ON [7:0] S1ADR[31:24] RW 0x00 SRC1 image's front address (Higher 8 bits of 32 bits) TMPA910CRA- 729 2010-06-02 TMPA910CRA [Description] a. <ERRINTF > Shows the status of an interrupt that shows the occurrence of processing errors in the LCDDA circuit. Note that the meanings differ between during READ and during WRITE. During READ During WRITE 0y0: No interrupt 0y0: Flag clear 0y1: With interrupt 0y1: Invalid (No status change) b. <EINTF> Shows the status of an interrupt that shows the end of processing for one line in the LCDDA's scaler/filter circuit. This interrupt shows the end of internal processing of the LCDDA's scaler, BLEND and Rotation functions. This, however, requires a caution because this interrupt does not show the end of transfer of the data accumulated in the write buffer. Scaler is processed every original image's 1-line. Therefore, interrupt is generated more than once until the scale-up/scale-down of the one image is terminated. Note that the meanings differ between during READ and during WRITE. During READ During WRITE 0y0: No interrupt 0y0: Flag clear 0y1: With interrupt 0y1: Invalid (No status change) c. <ERRINTM> Sets the mask for a processing error occurrence interrupt in the LCDDA circuit. 0y0: Error interrupt mask 0y1: Error interrupt enabled d. <EINTM> Sets the mask for an interrupt that shows the end of processing for one line in the LCDDA's scaler circuit. 0y0: Mask for one-line processing interrupt 0y1: One-line processing interrupt enabled e. <BCENYB> Controls the function of automatically adding dummy sampling points in Y-direction last LINEs for using the interpolation scaler function. 0y0: OFF 0y1: ON f. <AUTOHP> Automatic calculation of HOT point 0y0: OFF 0y1: ON TMPA910CRA- 730 2010-06-02 TMPA910CRA g. <DMAMD> Sets the DMA transfer mode of the LCDDA. 0y0: Single transfer 0y1: Burst transfer h. <DMAEN> This is the signal that shows the end of processing for one image in the LCDDA and controls the enable of DMA transfer. 0y0: DMA disabled 0y1: DMA enabled i. <BCENYT> Controls the function of automatically adding dummy sampling points in Y-direction front LINEs for using the interpolation scaler function. 0y0: OFF 0y1: ON j. <DTFMT> Defines the format of RGB data handled by the LCDDA. 0y0: 16-M color (32-bit data: Valid data 24-bit + Higher-order invalid data 8 bits) 0y1: 64-K color (16-bit data) k. <BCENX> Controls the function of automatically adding dummy sampling points in X-direction left/right rows for using the interpolation scaler function. 0y0: OFF 0y1: ON l. <PCEN> Controls the function of correcting periodical sampling points for using the scaler function. 0y0: OFF 0y1: ON m. <S1ADR [31:24]> Shows the front address of the memory in which original images (Source image 1) processed on the LCDDA are stored. The higher 8 bits of the 32-bit address area are set. TMPA910CRA- 731 2010-06-02 TMPA910CRA 2. LDADRSRC1 (LCDDA Density Ratio of Source 1 Image) Address = (0xF205_0000) + (0x0004) Bit Bit Type Symbol Reset Description Value [31:24] - - Undefined [23:16] BDRSRC1[7:0] R/W 0x00 Read as undefined. Write as zero. Blue data gray level adjustment in SRC1 image (256 levels) 0x00: Light to 0xFF: Dark [15:8] GDRSRC1[7:0] R/W 0x00 Green data gray level adjustment in SRC1 image (256 levels) 0x00: Light to 0xFF: Dark [7:0] RDRSRC1[7:0] R/W 0x00 Red data gray level adjustment in SRC1 image (256 levels) 0x00: Light to 0xFF: Dark Adjust the gray level of Source 1 (foreground) image independently for R, G, B 3. LDADRSRC0 (LCDDA Density Ratio of Source 0 Image) Address = (0xF205_0000) + (0x0008) Bit Bit Type Symbol Reset Description Value [31:24] - - Undefined [23:16] BDRSRC0[7:0] R/W 0x00 Read as undefined. Write as zero. Blue data gray level adjustment in SRC0 image (256 levels) 0x00: Light to 0xFF: Dark [15:8] GDRSRC0[7:0] R/W 0x00 Green data gray level adjustment in SRC0 image (256 levels) 0x00: Light to 0xFF: Dark [7:0] RDRSRC0[7:0] R/W 0x00 Red data gray level adjustment in SRC0 image (256 levels) 0x00: Light to 0xFF: Dark Adjust the gray level of Source 0 (background) image independently for R, G, B. 4. LDAFCPSRC1 (LCDDA Replaced Font Area Color pallet of Source1) Address= (0xF205_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value - - Undefined Read as undefined. Write as zero. [23:16] BFONT[7:0] R/W 0x00 FONT area color in SRC1 image (Blue data) [15:8] GFONT[7:0] R/W 0x00 FONT area color in SRC1 image (Green data) [7:0] RFONT[7:0] R/W 0x00 FONT area color in SRC1 image (Red data) [31:24] Note: The expanded bit of color font is used to set the LDAFCPSRC1<RFONT[7:0]>, <GFONT[7:0]> and <BFONT[7:0]>, in this case, the setting must be set to <RFONT[7:0]>=<BFONT[7:0]>. 5. LDAEFCPSRC1 (LCDDA Replaced Except Font Area Color pallet of Source1) Address= (0xF205_0000) + (0x0010) Bit Bit Symbol Type Reset Description Value [31:24] - - Undefined Read as undefined. Write as zero. [23:16] BFONT[7:0] R/W 0x00 Area color other than FONT in SRC1 image (Blue data) [15:8] GFONT[7:0] R/W 0x00 Area color other than FONT in SRC1 image (Green data) [7:0] RFONT[7:0] R/W 0x00 Area color other than FONT in SRC1 image (Red data) Set the color of places other than FONT in Source 1 (foreground) independently for R, G, B. TMPA910CRA- 732 2010-06-02 TMPA910CRA 6. LDADVSRC0 (LCDDA Delta Value (Read Step) address Register of Source 0) Address = (0xF205_0000) + (0x0038) Bit Bit [31] Symbol OVWEN Reset Type RW Description Value 0y0 0y0: SRC0 start address DST start address 0y1: SRC0 start address = DST start address [30] INDSAEN RW 0y0 0y0: SRC0 DX, DY = SRC1 DX, DY 0y1: SRC0 DX, DY SRC1 DX, DY [29:19] - - Undefined [18:6] DYS0[12:0] R/W 0x000 Read Step address until the next line of SRC0 data [5:3] - - Undefined Read as undefined. Write as zero. [2:0] DXS0[2:0] R/W 0y000 Horizontal Read Step address of SRC0 data Read as undefined. Write as zero. [Description] a. <OVWEN> This bit is used when Source 0 image and the destination image are the same in a image processed on the LCDDA. Setting 1 uses the front address setting of the destination image into the front address of Source 0 image too. In circuitry, the blend is executed and used to change the display which is blended part of current displaying image. Overwriting to VRAM area LCD Panel for convenience when the start address is same READ VRAM area LCDC WRITE LCDDA READ Source image 0 Color (16/24bpp) Blending READ Source image 1 Color (16/24bpp) TMPA910CRA RAM b. <INDSAEN> This bit is used when increment steps differ between Source 0 image and Source 1 image in a image processed for BLEND on the LCDDA. Setting 1 can set the number of steps individually for each Source 0 image and Source 1 image. When 0 is set, the increment step set for Source 1 image is used for the increment step in Source 0 image. TMPA910CRA- 733 2010-06-02 TMPA910CRA c. <DYS0> Used to have increment step settings in Source 0 image differing from Source 1 image. Not setting 1 in the INDSAEN bit disables this setting, applying the increment step settings of Source 1 image to Source 0 image too. Set the Step for vertical increment addresses (during line feed) for reading data from the original image (Source image 0) processed on the LCDDA. Increment step in the X direction DXS0 LCDDA target image Picture image Increment step in the Y direction DYS0 Set address step values after calculating them for each display color used. d. <DXS0[2:0]> Used to have increment step settings in Source 0 image differing from Source 1 image. Not setting 1 in the INDSAEN bit disables this setting, applying the increment step settings of Source 1 image to Source 0 image too. Set the Step for horizontal increment addresses for reading data from the original image (Source image 0) processed on the LCDDA. For 16-bpp (64-K color) data, set 0y010 because the step used is 2-byte step. For 32-bpp (16-M color) data, set 0y100. TMPA910CRA- 734 2010-06-02 TMPA910CRA 7. LDADVSRC1 (LCDDA Delta Value (Read Step) address Register of Source 1) Address = (0xF205_0000) + (0x0014) Bit Bit Symbol Type Reset Description Value [31:24] OFSETX[7:0] R/W 0x0000 Offset value for horizontal sampling point during scaler use [23:18] - - Undefined Read as undefined. Write as zero. [17:6] DYS1[11:0] R/W 0x000 Read Step address until the next line of SRC1 data [5:3] - - Undefined Read as undefined. Write as zero. [2:0] DXS1[2:0] R/W 0y000 Horizontal Read Step address of SRC1 data [Description] a. <OFSETX[7:0]> Set the offset value for the horizontal pixel sampling steps in the scaler circuit. By setting a value of 0x01 to 0xFF, the set pixel point is sampled first. b. <DYS1[11:0]> Set the Step for vertical increment addresses (during line feed) for reading data from the original image (Source image 1) processed on the LCDDA. Increment step in the X direction DXS LCDDA target image Picture image c. Increment step in the Y direction DYS <DXS1[2:0]> Set the Step for horizontal increment addresses for reading data from the original image (Source image 1) processed on the LCDDA. For 16-bpp (64-K color) data, set 0y010 because the step used is 2-byte step. For 32-bpp (16-M color) data, set 0y100. TMPA910CRA- 735 2010-06-02 TMPA910CRA 8. LDACR2 (LCDDA Control Register 2) Address = (0xF205_0000) + (0x0018) Bit Bit Symbol Type Reset Description Value [31:24] OFSETY[7:0] R/W 0x0000 Offset value for vertical sampling point during scaler use [23:16] - - Undefined Read as undefined. Write as zero. [15:8] HCRCT[7:0] R/W 0x00 Horizontal period correction value [7:0] VCRCT[7:0] R/W 0x00 Vertical period correction value [Description] a. <OFSETY[7:0]> Sets the offset value for the vertical pixel sampling steps in the scaler circuit. By setting a value of 0x01 to 0xFF, the set pixel point is sampled first. b. <HCRCT[7:0]> Sets the horizontal period correction values in the scaler circuit. Setting the LDACR0<PCEN> to 0y1 enables this bit. By setting a value of 0x01 to 0xFF, the set pixel point is corrected to the point one point right-side to the original pixel. c. <VCRCT[7:0]> Sets the vertical period correction values in the scaler circuit. Setting the LDACR0<PCEN> to 0y1 enables this bit. By setting a value of 0x01 to 0xFF, the set pixel point is corrected to the point one line below the original pixel. TMPA910CRA- 736 2010-06-02 TMPA910CRA 9. LDADXDST (LCDDA X-Delta Value (Write Step) address Register of Destination) Address = (0xF205_0000) + (0x001C) Bit Bit Symbol Type Reset Description Value [31:28] XRDRATE[3:0] R/W 0y0000 Horizontal scale-down rate [27:25] - - Undefined Read as undefined. Write as zero. [24] DXDSIGN R/W 0y0 Horizontal heading direction in DST data [23:0] DXDST[23:0] R/W 0x000000 Number of horizontal steps in DST data [Description] a. <XRDRATE[3:0]> Sets horizontal scale-down values. By setting a value of 0x0 to 0xf, perform a scale down having a value of "set value + 1" as the denominator. Example: When set to 0x2: Results as 1/ (2 + 1) = 1/3, scaling down to 1/3 in the horizontal direction. b. <DXDSIGN> Sets the direction of horizontal destination step. Set this by deciding the address's heading direction according to the Rotation function's rotation angle and horizontal/vertical mirror. 0y0: Plus (Increment) 0y1: Minus (Decrement) c. <DXDST[23:0]> Sets horizontal destination step addresses. In order to control addresses and accomplish the Rotation function, 24 bits are provided for step addresses. Set step addresses according to the Rotation function's rotation angle and horizontal/vertical mirror. TMPA910CRA- 737 2010-06-02 TMPA910CRA 10. LDADYDST (LCDDA Y-Delta Value (Write Step) address Register of Destination) Address = (0xF205_0000) + (0x0020) Bit Bit Symbol Type Reset Description Value [31:28] YRDRATE[3:0] R/W 0y0000 Vertical scale-down rate [27:25] - - Undefined Read as undefined. Write as zero. [24] DYDSIGN R/W 0y0 Vertical write direction in DST data [23:0] DYDST[23:0] R/W 0x000000 Number of vertical steps in DST data [Description] a. <YRDRATE[3:0]> Sets vertical scale-down rate. By setting a value of 0x0 to 0xf, perform a scale down having a value of "set value + 1" as the denominator. Example: When set to 0xf, Results as 1/(15 + 1) = 1/16, scaling down to 1/16 in the vertical direction. b. <DYDSIGN> Sets the direction of vertical destination step. Set this by deciding the address's heading direction according to the Rotation function's rotation angle and horizontal/vertical mirror. 0y0: Plus (Increment) 0y1: Minus (Decrement) c. <DYDST[23:0]> Sets vertical destination step addresses. In order to control addresses and accomplish the Rotation function, 24 bits are provided for step addresses. Set step addresses according to the Rotation function's rotation angle and horizontal/vertical mirror. TMPA910CRA- 738 2010-06-02 TMPA910CRA 11. LDASSIZE (LCDDA Source Image Size) Address = (0xF205_0000) + (0x0024) Bit Bit Symbol Reset Type Description Value [31:24] XEXRATE[7:0] R/W 0x00 Horizontal scale-up rate during scaler use [23:22] - - Undefined Read as undefined. Write as zero. [21:12] SYSIZE[9:0] R/W 0x000 Vertical SRC image size (Dot-basis setting) [11:10] - - Undefined Read as undefined. Write as zero. [9:0] SXSIZE[9:0] R/W 0x000 Horizontal SRC image size (Dot-basis setting) Note1: Setting required in all functions Note2: The horizontal image max size is 511 dot when used in the scaler function. [Description] a. <XEXRATE[7:0]> Sets the horizontal scale-up rate. By setting a value of 0x01 to 0xff (Setting to 0x00 disabled), perform a scale up. Input values according to the equation below: * Number of original pixels in the X direction: m pixel(s) * Number of after-scaled-up pixels in the X direction: n pixel(s) (Maximum number of interpolatable pixels) / (Number of after-scaled-up pixels) = {(m - 1) x 256} / n b. <SYSIZE[9:0]> Sets vertical source image sizes. Sets an image size on a dot basis. A dot of "input size + 1" is specified for size. Example: For 200 dots, set as 199 (oct) = C7 (hex). c. <SXSIZE[9:0]> Sets horizontal source image sizes. Sets an image size on a dot basis. A dot of "input size + 1" is specified for size. Example: For 200 dots, set as 199 (oct) = C7 (hex). TMPA910CRA- 739 2010-06-02 TMPA910CRA 12. LDADSIZE (LCDDA Destination Image Size) Address = (0xF205_0000) + (0x0028) Bit Bit [31:24] [23:10] [9:0] Symbol YEXRATE[7:0] - Type R/W - DXSIZE[9:0] R/W Reset Description Value 0x00 Vertical scale-up rate during scaler use Undefined Read as undefined. Write as zero. 0x000 Horizontal DST image size (Dot-basis setting) Note: When used in the scaler function, vertical image size settings are invalid. Because the scaler function is processed on the basis of one line, the number of processes will result as the image size in the vertical direction directly. [Description] a. <YEXRATE[7:0]> Sets the vertical scale-up rate. By setting a value of 0x01 to 0xff (Setting to 0x00 disabled), perform a scale up. Input values according to the equation below: * Number of original pixels in the Y direction: k pixel(s) * Number of after-scaled-up pixels in the Y direction: l pixel(s) (Maximum number of interpolatable pixels) / (Number of after-scaled-up pixels) = {(k - 1) x 256} / l b. <DXSIZE[9:0]> Sets horizontal destination image sizes. Sets an image size on a dot basis. A dot of "input size + 1" is specified for size. Example: For 200 dots, set as 199(oct) = C7(hex). TMPA910CRA- 740 2010-06-02 TMPA910CRA 13. LDAS0AD (LCDDA Source 0 Start Address) Address = (0xF205_0000) + (0x002C) Bit [31:0] Bit Symbol S0ADR[31:0] Type R/W Reset Description Value 0x00000000 Start address of SRC0 image Note: While 32-bit addresses are set, the addresses in the higher 8 bits have no internal counter. Note that the setting of start address allowing the addresses in the higher 8 bits to change in the SRC image data area is unavailable. (Example: If set to 0x00FFFFFF, the LCDDA accesses in the order of 0x00FFFFFF 0x00000000 0x00000001: The addresses in the higher 8 bits cannot be incremented.) 14. LDADAD (LCDDA Destination Start Address) Address = (0xF205_0000) + (0x0030) Bit [31:0] Bit Symbol DSADR[31:0] Type R/W Reset Description Value 0x00000000 Start address of DST image Note: While 32-bit addresses are set, the addresses in the higher 8 bits have no internal counter. Note that the setting of start address allowing the addresses in the higher 8 bits to change in the DST image data area is unavailable. (Example: If set to 0x00FFFFFF, the LCDDA accesses in the order of 0x00FFFFFF 0x00000000 0x00000001: The addresses in the higher 8 bits cannot be incremented.) TMPA910CRA- 741 2010-06-02 TMPA910CRA 15. LDACR1 (LCDDA Control Register1) Address = (0xF205_0000) + (0x0034) Bit Bit Symbol [31] SYNRST Type Reset Description Value WO 0y0 S/W reset control [30] LDASTART WO 0y0 LCDDA START control [29] - - Undefined Read as undefined. Write as zero. [28:24] OPMODE[4:0] R/W 0y00000 LCDDA mode setting 0x000000 0y00000 : NORMAL mode 0y00001 : Scaler mode 0y00010 : Monochrome mode 0y00110 : Monochrome invert mode 0y10000 : BLEND mode 0y10010 : Monochrome BLEND mode 0y10110 : Monochrome invert BLEND mode 0y11010 : Font Draw mode * Other combination of bits (functions) than the above cannot be set. SRC1 image's front address (Lower 24 bits of 32 bits) [23:0] S1ADR[23:0] R/W [Description] a. <SYNRST> Controls the S/W reset. 0y1: Reset 0y0: Ignored b. <LDASTART> Controls the start of the LCDDA. 0y1: LCDDA start 0y0: Ignored c. <OPMODE[4:0]> Selects the LCDDA operation modes. 0y00000: 0y00001: 0y00010: NORMAL mode This is a simple data transfer mode. Used to transfer (rotation, scaling down) rectangular images with only Source 1 (S1) selected for source data (S0 settings disabled). Scaler mode The scaler mode is accomplished by controlling the operation of the BC-Expander circuit. The concurrent use with the BLEND function and the FONT function is unavailable. Monochrome mode This mode transfers monochrome sources. Used to transfer (rotation, scaling down) images after converting monochrome data into color data with only Source 1 (S1) selected for source data (S0 settings disabled). TMPA910CRA- 742 2010-06-02 TMPA910CRA 0y00110: 0y10000: 0y10010: 0y10110: 0y11010: Monochrome invert mode This mode inverts and transfers monochrome source data. Used to transfer (rotation, scaling down) images after inverting monochrome data to convert it into color data with only Source 1 (S1) selected for source data (S0 settings disabled). BLEND mode This mode blends two color (16 bpp/24 bpp) images. Used to transfer (rotation, scaling down) images after blending them, with Source 0 (S0) and Source 1 (S1) selected for source data. Monochrome BLEND mode This mode blends two images of monochrome source and color (16 bpp/24 bpp). Used to transfer (rotation, scaling down) images after blending two images of color data converted from a Source 1 (S1) image specified in monochrome, and Source 0 (S0) specified in color. Monochrome invert BLEND mode This mode blends two images of data inverted from monochrome-source data and color (16 bpp/24 bpp). Used to transfer (rotation, scaling down) images after blending two images of color data converted from a Source 1 (S1) image specified in monochrome, and Source 0 (S0) specified in color. Font Draw mode This mode blends two images of monochrome source data and color data (16bpp/24bpp). And blends two images which is converting the specified in monochrome source 1 (S1) image to color data and is specified by color source 0 (S0). Only "1" of monochrome data is valid and transfers (rotation/scaled-down) the expanded image. d. <S1ADR[23:0]> Sets the lower 24 bits for the start addresses of Source 1 image. While 32-bit setting is required for the addresses of Source 1 image, set the addresses in the higher 8 bits by LDACR0<S1ADR[31:24]>. TMPA910CRA- 743 2010-06-02 TMPA910CRA 3.21 Touch Screen Interface (TSI) An interface for 4-terminal resistor network touch-screen is built in. The TSI easily supports two procedures: touch detection and X/Y position measurement. Each procedure is performed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter. 3.21.1 TSI External Connection Diagram and Internal Block Diagram TMPA910CRA YMY X+ Touch Screen MX X- PY PX Y+ External Capacitors Figure 3.21.1 External connection of TSI Touch screen control AVCC3AD PXEN SPY SPX PD7 (PY) PD6/INTA (PX) PD5/AN5 (MY) PYEN MXEN INTA MYEN PTST INTA TSI7 PXD Typ.50k AD converter AN5 PD4/AN4 (MX) VREFH Dec. Interrupt controller Internal data bus AVSS3AD AN4 SMX SMY AVCC3AD AVSS3AD VREFH VREFL VREFL Figure 3.21.2 Internal block diagram of TSI TMPA910CRA- 744 2010-06-02 TMPA910CRA 3.21.2 SFR The following lists the SFRs: Base address = 0xF006_0000 Register Address Name (base+) Description TSICR0 0x01F0 TSI Control Register0 TSICR1 0x01F4 TSI Control Register1 TMPA910CRA- 745 2010-06-02 TMPA910CRA 1. TSICR0 (TSI Control Register0) Address = (0xF006_0000) + (0x01F0) Bit Bit Symbol Reset Type Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] TSI7 R/W 0y0 pull-down resistor(refer to Description) 0y0: Disable 0y1: Enable [6] INGE R/W 0y0 Input gate control of Port PD6, PD7 0y0: Enable 0y1: Disable [5] PTST RO 0y0 Detection condition Read: 0y0: No touch 0y1: Touch Write: [4] TWIEN R/W 0y0 Invalid INTA interrupt control 0y0: Disable 0y1: Enable [3] PYEN R/W 0y0 SPY 0y0: OFF 0y1: ON [2] PXEN R/W 0y0 SPX 0y0: OFF 0y1: ON [1] MYEN R/W 0y0 SMY 0y0: OFF 0y1: ON [0] MXEN R/W 0y0 SMX 0y0: OFF 0y1: ON Note: To avoid a flow-through current to the normal C-MOS input gate when converting analog input data by using the AD converter, TSICR0<INGE> can be controlled. If the intermediate voltage is input, cut the input signal to the C-MOS logic (PD6, PD7) by setting this bit. TSICR0<PTST> is to confirm the initial pen-touch. Note that, when the input to the C-MOS logic is blocked by TSICR0<INGE>, this bit is always 1. [Description] a. <TSI7> PXD (Internal pull-down resistor) ON/OFF <PXEN> <TSI7> 0 1 0 OFF OFF 1 ON OFF TMPA910CRA- 746 2010-06-02 TMPA910CRA 2. TSICR1 (TSI Control Register1) Address = (0xF006_0000) + (0x01F4) Bit Bit Symbol Reset Type Description Value [31:8] - - Undefined [7] DBC7 R/W 0y0 Read as undefined. Write as zero. 0y0: Disable 0y1: Enable [6] DB1024 R/W 0y0 1024 [5] DB256 R/W 0y0 256 "(N x 64-16)/fPCLK" formula. [4] DB64 R/W 0y0 64 "N" is the sum of the numbers obtained [3] DB8 R/W 0y0 8 when 1 is set in bit 6 to bit 0. (Note 2) [2] DB4 R/W 0y0 4 [1] DB2 R/W 0y0 2 [0] DB1 R/W 0y0 1 De-bounce time is set by the Note 1: Since several pulses of fPCLK are used to synchronize the PD6/INTA signal before it is input to the counter circuit for counting the debounce time, the actual debounce time is the above period plus an extra synchronization period. Note 2: For example, when TSICR1 = 0x95, N = 64 + 4 + 1 =69. In this case, the debouce time is 44 s plus an extra synchronization period when fPCLK = 100 MHz. TMPA910CRA- 747 2010-06-02 TMPA910CRA 3.21.3 Touch Detection Procedure The touch detection procedure includes the procedures starting from when the pen is touched onto the touch screen and until the pen-touch is detected. Touching the screen generates the interrupt INTA and terminates this procedure. After an X/Y position measuring at INTA interrupt routine, and an X/Y position measuring procedure is terminated, return to this procedure to wait for the next touch. When waiting for a touch with no contact, set only the SPY switch to ON and set all other three switches (SMY, SPX, SMX) to OFF. At this time, the pull-down resistor built in the PD6/INTA/PX pin is set to ON. In this state, because the internal X- and Y-direction resistors in the touch screen are not connected, the PD6/INTA/PX pin is set to Low by the internal pull-down resistor (PXD), generating no INTA interrupt. When a next pen-touch is given, the X- and Y-direction internal resistors in the touch screen are connected, which sets the PD6/INTA/PX pin to High and generates an INTA interrupt. To avoid generating more than one INTA interrupt by one pen-touch, the de-bounce circuit as shown below is provided. Setting de-bounce time in the TSICR1 register ignores pulses whose time equals to or is below the set time. The de-bounce circuit detects a rising of signal to count up a set de-bounce counter time and then captures the signal into the inside after counting. When the signal turns to "L" during counting, the counter is cleared, starting to wait for a rising edge again. GPIOD GPIOD Block AVCC3AD PMC OFF (SPX) INTTA PD6/INTA Block ON (Pull Down) To interrupt controller 0 TSICR0<TWIEN> 50k AVSS3AD 1 TSICR0<TSI7> Interrupt setting INTS [5] INTTSI De-bounce circuit TSICR0<PTST> TSICR1 Interrupt clear GPIODIC<PD6IC> TSICR1<DBC7> TSICR0<INGE> Input Enable 1 0 Note: Supportable INTTSI rising edge interrupt only by touch detection. Fixed low GPIODFR2<PD6F2> Figure 3.21.3 Block diagram of touch detection TMPA910CRA- 748 2010-06-02 TMPA910CRA PD6/INTSI pin Reset the de-bounce time counter. Start the de-bounce time counter. De-bounce time De-bounce time De-bounce time INTA The de-bounce time counter matches with a specified de-bounce time, which generates an INTA interrupt. After the pen is released, an INTA interrupt can be received again. No INTA interrupt is generated due to edge interrupt even though the de-bounce time counter matches a specified de-bouce time. Figure 3.21.4 Timing diagram of de-bounce circuit TMPA910CRA- 749 2010-06-02 TMPA910CRA 3.21.4 X/Y Position Measuring Procedure During the routine of pen-touch and INTA interrupt generation, execute a pen position measuring following the procedure below: <X-position coordinate measurement> Make the SPX and SMX switches ON, and the SPY and SMY switches OFF. With this setting, an analog voltage that shows the X position will be input to the PD5/MY/AN5 pin. The X-position coordinate can be measured by converting this voltage into digital code using the AD converter. <Y-position coordinate measurement> Make the SPY and SMY switches ON, and the SPX and SMX switches OFF. With this setting, an analog voltage that shows the Y position will be input to the PD4/MX/AN4 pin. The Y-position coordinate can be measured by converting this voltage into digital code using the AD converter. The analog voltage which is input to the AN5 and AN4 pins during the X and Y position measurement above can be determined with the ratio between the ON resistance value of the switch in the TMPA910CRA and the resistance value in the touch screen as shown in Figure3.21.5 Analog input voltage calculation values. . Therefore, even when touching an end area on the touch screen, the analog input voltage will be neither 3.3 V nor 0 V. Note that the rate of each resistance varies. Remember to take this into consideration during designing. It is also recommended that an average taken from several AD conversions performed if required be adopted as the final correct value. SPY(SPX) ON-resistor: Rpy (Rpx) 10 (typ.) Touch screen resistor : Rty (Rtx) The resistance depends on the touch screen. SMY (SMX) ON-resistor: Rmy (Rmx) 10 (typ.) [Analog input voltage to the AN4 and AN5 pins: Formula to calculate E1] AVCC3AD = 3.3 V R1 AN4 (AN5) pin R2 Touch point E1 = ((R2 + Rmy) / (Rpy + Rty + Rmy)) x AVCC3AD[V] Example) Where AVCC3AD = 3.3 V, Rpy = Rmy = 10 R1 = 400 and R2 = 100 E1 = ((100 + 10) / (10 + 400 + 100 + 10) x 3.3 = 0.698 V Note 1: An X-coordinate position can be calculated in the same way though above formula is for Y-coordinate position. Note 2: Rty = R1 + R2 Figure3.21.5 Analog input voltage calculation values TMPA910CRA- 750 2010-06-02 TMPA910CRA 3.21.5 Flow Chart of Touch Screen Interface (TSI) (1) Touch detection procedure (2) X/Y position measuring procedure Main Routine INTA Routine TSICR00x98 TSICR10xXX (voluntary) Execute the main routine (a) <X-coordinate position measurement> * TSICR00xC5 * AN5 AD conversion * Store the AD conversion result. <Y-coordinate position easurement> * TSICR00xCA * AN4 AD conversion * Store the AD conversion result. (b) (c) Execute the processes by using X/Y-coordinate position information Yes Still touched? TSICR00x88 TSICR0<PTST> == 1? No Return to the main routine. Figure 3.21.6 Flow example for TSI The following pages explain each circuit condition (a), (b) and (c) in the flow chart above: TMPA910CRA- 751 2010-06-02 TMPA910CRA (a) Main routine: condition of waiting for INTA interrupt GPIODFR1 GPIODFR2 GPIODIS GPIODIBE GPIODIE GPIODIEV TSICR0 0x00000030 0x000000C0 0x00000000 0x00000000 0x00000040 0x00000040 0x00000098 ;PD[6] INTA,PD[5]AN5 , PD[4]AN4 ;PD[7]PY , PD[6] PX ;set INTA edge interrupt ;set INTA single edge ;enable INTA ;set INTA positive edge ;[7] enable TSI / PXD ON ;[4] INTA enable ;[3] SPY:ON TMPA910CRA Touch screen control AVCC3AD PXEN ON SPY SPX PYEN MXEN PTST MYEN Y+ Touch Screen (PX/PD6/INTA) X+ INTA ON TSI7 Typ.50k PXD AD Converter (MY/PD5/AN5) Y- AN5 (MX/PD4/AN4) Internal data bus (PY/PD7) X- Dec. AN4 SMX SMY AVCC3AD AVSS3AD VREFH VREFL AVSS3AD VREFH VREFL TMPA910CRA- 752 2010-06-02 TMPA910CRA (b) INTA routine: X-position coordinate measurement (AD conversion start) GPIODIC TSICR0 TSICR0 0x00000040 0x00000085 0x000000C5 ADMOD1 ADMOD0 0x00000085 0x00000001 ;INT request clear ;Disable INTA ;[7] enable TSI ;[6] PD6/PD7 : disable input ;[2] SPX:ON , [0] SMX:ON ;Set AN5 ;Start AD conversion TMPA910CRA Touch screen control AVCC3AD ON SPY SPX Dec. PYEN MXEN PTST MYEN Y+ Touch Screen INTA (PX/PD6/INTA) TSI7 X+ Typ.50k PXD AD Converter (MY/PD5/AN5) Y(MX/PD4/AN4) AN5 ON Internal data bus (PY/PD7) XX- PXEN AN4 SMX SMY AVCC3AD AVSS3AD VREFH VREFL AVSS3AD VREFH VREFL TMPA910CRA- 753 2010-06-02 TMPA910CRA (c) INT4 routine: Y-position coordinate measurement (AD conversion start) TSICR0 0x000000CA ADMOD1 ADMOD0 0x00000084 0x00000001 ;[7] enable TSI ;[6] PD6/PD7 : disable input ;[3] SPY:ON , [1] SMY:ON ;set AN4 ;start AD conversion TMPA910CRA Touch screen control AVCC3AD PXEN ON SPY SPX PYEN MXEN PTST MYEN Y+ Touch Screen INTA (PX/PD6/INTA) TSI7 X+ Typ.50k PXD AD Converter (MY/PD5/AN5) YON (MX/PD4/AN4) AN5 Internal data bus (PY/PD7) X- Dec. AN4 SMX SMY AVCC3AD AVSS3AD VREFH VREFL AVSS3AD VREFH VREFL TMPA910CRA- 754 2010-06-02 TMPA910CRA 3.21.6 Considerations for Using the TSI 1Recovery from PCM state In PCM state, Power supply of TSI circuit is turned off. However, it can recover from PCM state because of the touch detection is inputted to PMC from PD6/INTA input pin directly. Setting example: BPDRINT 0x00000000 ; write 0x00000000 to Register ; INT status initial BPARINT 0x00000000 ; INT status initial BPPRINT 0x00000000 ; INT status initial BSMRINT 0x00000000 ; INT status initial BRTRINT 0x00000000 ; INT status initial BPDEDGE 0x00000000 ; Rising edge BPDOE 0x000000B0 ; PD7(SPY):ON ,PD6(SPX):OFF ; PD5(SMY):OFF , PD4(SMX):OFF BPDDATA 0x00000000 ; PD6(PXD):ON (pull down) BPDRELE ... 0x00000040 ... ; PCM release Enable by INTA ; and other setting before enter PCM ; refer to PMC chapter GPIOD AVCC3AD 1 OFF BPDOE<bit6> (Signal from PMC block 0 PD6/INTA PCM mode setting = 1 TSICR0<PXEN> 0 ON TSICR0<TSI7> 1 BPDDATA<bit6> (Signal from PMC block 50 k AVSS3AD Input enable PMC block Note: If it is waked up from PCM state by INTA, the interrupt edge is usable rising /falling both edges. However, if using with TSI, it recommends using rising edge. 3Port setting When an intermediate voltage between 0V and AVCC3AD is converted by the AD converter, the intermediate voltage is also applied to normal C-MOS input gates due to the circuit structure. Take measures against the flow-through current to PD6 and PD7 by setting TSICR0<INGE> = 1. When the input to the C-MOS logic is cut off, TSICR0<PTST> that indicates whether or not a pen touch is detected is always set to 1. TMPA910CRA- 755 2010-06-02 TMPA910CRA 3.22 CMOS Image Sensor Interface (CMSI) The interface to the CMOS image sensor is built in. The CMSI has the following features: Table 3.22.1 Characteristics of CMSI Number of supportable CMOS SXGA (1280 x 1024), 4VGA (1280 x 960), VGA (640 x 480), image sensor valid pixels QVGA (320 x 240), Special (320 x 180), QQVGA (160 x 120), CIF (352 x 288), QCIF(176x 144) Input data format YUV4:2:2 , RGB8:8:8, RGB5:6:5 Input data sampling ratio 8-bit YUV4:2:2 (RGB8:8:8 or RGB5:6:5 if no color space conversion) Pixel clock frequency Up to 27 MHz Color space conversion function For an external terminal input YUV4:2:2 RGB5:6:5/ RGB8:8:8 RGB8:8:8, RGB5:6:5 No conversion For an input from the CPU YUV RGB5:6:5/ RGB8:8:8 4VGA VGA, QVGA, QQVGA Downscaling function VGA QVGA, QQVGA QVGA QQVGA Trimming function 3.22.1 Data can be trimmed to a desired size. Block Diagrams The block diagram of CMSI is shown below: Read pointer Completion 32/48byte Write CMSVSY CMSHSY CMSHBK DMA I/F INTCMS Down Scaler /Trimmer CMSPCK Timing Generate INTCMSF Clearing DMA request DMA request Interrupt request (INTS[15]) CMSD [7:0] Buffer Color Space Converter (192Byte) FIFO Port Internal Data Bus FIFO Y data U data V data Control Register CMSACCTL0 CMSACCTL1 Figure 3.22.1 CMSI block diagram TMPA910CRA- 756 2010-06-02 TMPA910CRA 3.22.2 Description of Operation 3.22.2.1 Description The CMSI captures data sent from a CMOS image sensor in synchronization with the CMSPCK clock. When the downscaling or trimming function is used, only required pixel data is captured according to the specified setting. Next, when color-converting YUV422 into RGB, color space conversion is performed at the point when a pixel of YUV data has been captured, and then the converted RGB data is stored in the FIFO one after another. At the point when the FIFO contains data with a specified number of bytes, write completion interrupt (INTCMSF) is output. This write completion interrupt can be used as a trigger to start DMA data transfer. The color space conversion circuit is connected to the internal data bus, enabling only the color space conversion function to be used independently when the CMSI is not used to interface a CMOS image sensor. In this case, converted RGB data is stored in the FIFO. Note: When the CMSI is used to interface a CMOS image sensor, the relationship between CMSPCK and the system clock HCLK should be "CMSPCK x 2 fPCLK". CMSVSY (NEG) CMSVSY (POS) CMSHSY (NEG) CMSHSY (POS) CMSHBK (POS) Line1 Line2 Line3 Line4 Line5 LineE Line2 Line3 Line4 Line5 CMSHBK (NEG) Line1 Line2 Line3 Line4 Line5 LineE Line2 Line3 Line4 Line5 CMSVSY (Example of NEG) CMSHSY (Example of NEG) CMSHBK (Example of POS) CMSPCK (Example of FDE) CMSPCK (Example of RUE) CMSD[7:0] (Normal) CMSD[7:0] (Delay capture) Invalid Invalid Invalid Invalid Basis timing TMPA910CRA- 757 2010-06-02 TMPA910CRA 3.22.2.2 Data Capture CMSVSY CMSHSY CMSHBK Line1 Line2 Line3 Line4 Line5 LineE Line1 Line2 C CMSVSY CMSHSY CMSHBK CMSPCK CMSD[7:0] When YUV4:2:2 Blank U1 Y1 V1 Y2 U3 Y3 V3 Y4 U5 Yn Blank U1 Y1 V1 Y2 U3 Y3 When RGB8:8:8 (CMSCV<CRGBM> = 1 and No-dummy) Blank R1 G1 B1 R2 G2 B2 R3 G3 B3 Bn Blank R1 G1 B1 R2 G2 B2 Blank R1 G1 B1 du R2 G2 B2 du R3 du Blank R1 G1 B1 du R2 G2 When RGB8:8:8 or RGB5:6:5 (CMSCV<CRGBM> = 0, Dummy insert) du : dummy data Figure 3.22.2 CMSI timing example (When CMSVSY is set to Negative, CMSHSY is also set to Negative, and CMSPCK is set to rising edge) When set to CMSCR<CSRST> = 0 and the start of a frame is detected on the rising edge of the CMSVSY signal (when set to Negative), the CMSI starts capturing data. As valid data, data is captured in the High period of the CMSHBK signal. Capturing is taken place in synchronization with the rising edge of the CMSPCK signal (in the case of rising edge). The supported data format is the YUV format only. For the data sampling rate, only YUV422 is supported for external I/Fs (If no color space conversion is performed, RGB888 or RGB565). Note: Ensure 6 CMSPCK clocks or more between rising edge of CMSVSY (Negative setting) and rising edge of CMSHBK (Positive setting). Same applies to other edge combinations. TMPA910CRA- 758 2010-06-02 TMPA910CRA 3.22.2.3 Color Space Conversion Circuit The operation of CMSCV<CCVM1:0>. the color space conversion circuit is controlled by When <CCVM1:0> = 0y00, the data from the CMOS image sensor is directly stored in the FIFO without conversion. When <CCVM1:0> = 0y01, the color space conversion circuit converts data in synchronization with data captured from the CMOS image sensor. Each time one pixel of YUV data has been captured, the color space conversion circuit automatically converts the data into RGB format. When <CCVM1:0> = 0y10, the color space conversion circuit can be accessed from the CPU. In this case, the conversion-source YUV data is set in the CMSYD, CMSUD, and CMSVD registers. The trigger for starting conversion into RGB is set in CMSSCV<CSCVTRG1:0>. A write to the CMSYD/CMSUD/CMSVD register or a write of 0y1 to the conversion start bit (CMSSCV<CSCVST>) can start conversion. In this mode, arrange so that the data from the CMOS image sensor is not input. When <CCVM1:0> = 0y11, the color space conversion circuit can be accessed by DMA. Conversion-source YUV data is predicated to be ready for YUV of "8-bit Y + 8-bit U + 8-bit V + 8-bit Dummy." Writing 32 bits of data in the CMSSCDMA register starts conversion. Since the S/W is started only when CMSCV<CMCVTRG [1:0]> is set to 0y11, a write of 0y1 in the conversion start bit (CMSSCV<CSCVST>) can start conversion. By using the DMA function together, continuous writes (writing 32-bit data successively) can be given. In this mode, arrange so that the data from the CMOS image sensor is not input. Note: To access the color space conversion circuit from the CPU, set CMSPCK, CMSHBK, CMSVSY, CMSD[7:0] to function as ports. TMPA910CRA- 759 2010-06-02 TMPA910CRA (1) RGB color quality adjustment The RGB format to be used can be specified in CMSCV<CRGBM>. YUV data is converted into RGB data according to the specified conversion formula. The parameters can be adjusted by <CRYG[6:0]>, <CRVG[6:0]>, <CGYG[6:0]>, <CGVG[6:0]>, <CGUG[6:0]>, <CBYG[6:0]>, <CBUG[6:0]>, and <CYOFS[6:0]> in the CMSCVP0/CMSCVP1 register setting. The most significant bit of each register is designated as a sign bit. By setting a two's complement value (-26 to 26-1), the initial value of each parameter can be adjusted for increment and decrement. The CMSCVP0 and CMSCVP1 registers are initially set to 0. The calculation result of each RGB data is represented as unsigned 8-bit data. If the RGB calculation result is less than 0, it is treated as 0. If 256 or larger, it is treated as 255. If the calculation in (Y + CYOFS[6:0]) is less than 0, (Y + CYOFS[6:0]) is treated as 0. The formula can be selected from the following two types by using the CMSCV<CCVSMMS> bit. Mode 1 256 CRYG[6:0] R= 256 350 CRVG[6:0] x (Y CYOFS[6:0] ) 256 x ( V128) 86 CGUG[6:0] 180 CGVG[6:0] 256 CGYG[6:0] G= 256 x (Y CYOFS[6:0] ) 256 x ( V128) 256 CBYG[6:0] B= 256 256 x ( U128) 456 CBUG[6:0] x (Y CYOFS[6:0] ) 256 x ( U128) Mode 2 256 CRYG[6:0] R= 256 460 CRVG[6:0] x (Y CYOFS[6:0] ) 256 x ( V128) 86 CGUG[6:0] 180 CGVG[6:0] 256 CGYG[6:0] G= 256 x (Y CYOFS[6:0] ) 256 x ( V128) 256 CBYG[6:0] B= 256 256 x ( U128) 543 CBUG[6:0] x (Y CYOFS[6:0] ) 256 x ( U128) Figure 3.22.3 RGB conversion formula TMPA910CRA- 760 2010-06-02 TMPA910CRA An example (Mode 1 example) of how the color space conversion circuit converts data is shown in Table 3.22.2. At this time, the CMSCVP0 and CMSCVP1 registers are set as shown below: <CRYG[6:0]> = 0x2B(43), <CRVG[6:0]> = 0x3A(58), <CGYG[6:0]> = 0x2B(43), <CGVG[6:0]> = 0x1D(29), <CGUG[6:0]> = 0x0E(14), <CBYG[6:0]> = 0x2B(43), <CBUG[6:0]> = 0x3D(61) <CYOFS[6:0]> = 0x70 (-16) Table 3.22.2 Example of conversion by color space conversion circuit (Mode 1) Color YUV data example Y U RGB conversion result in color space conversion circuit V R G B White 0xEB 0x80 0x80 0xFF 0xFF 0xFF Black 0x10 0x80 0x80 0x00 0x00 0x00 Red 0x52 0x5A 0xF0 0xFF 0x00 0x00 Green 0x90 0x36 0x22 0x00 0xFF 0x00 0xFF Blue 0x29 0xF0 0x6E 0x 00 0x00 Yellow 0xD2 0x10 0x92 0xFF 0xFF 0x00 Cyan 0xA9 0x A6 0x10 0x00 0xFF 0xFF Magenta 0x6B 0x CA 0xDE 0xFF 0x00 0xFF TMPA910CRA- 761 2010-06-02 TMPA910CRA (2) Using the color space conversion circuit from the CPU The following shows an example of converting four pixels of data from the YUV4:4:4 to RGB565 format: Use example: (CMSCV) (CMSCR) 0x00000010 0x00000040 ; Used by the CPU, RGB5:6:5 ; Conversion start trigger = write to CMSYD ; CMOS image sensor operation status ; QQVGA, interrupt CMSVSY ; FIFO pointer clear (CMSSCTR) 0x00000000 ; No Down Scaling, No Trimming (CMSUD) 0x00000011 ; YUV color difference signal write (CMSVD) 0x00000012 ; YUV color difference signal write (CMSYD) 0x00000013 ; YUV brightness signal write & Conversion start first pixel (CMSUD) 0x00000021 ; YUV color difference signal write (CMSVD) 0x00000022 ; YUV color difference signal write (CMSYD) 0x00000023 ; YUV brightness signal write & Conversion start second pixel (CMSUD) 0x00000031 ; YUV color difference signal write (CMSVD) 0x00000032 ; YUV color difference signal write (CMSYD) 0x00000033 ; YUV brightness signal write & Conversion start third pixel (CMSUD) (CMSVD) 0x00000041 ; YUV color difference signal write 0x00000042 ; YUV color difference signal write (CMSYD) 0x00000043 ; YUV brightness signal write & Conversion start fourth pixel (CMSFPT) CPU register ; RGB data read Note: Before setting the CMSCR register, be sure to set the CMSCV register. TMPA910CRA- 762 2010-06-02 TMPA910CRA The following shows an example of converting four pixels of data from the YUV4:2:2 to RGB8:8:8 format: Use example: (CMSCV) (CMSCR) 0x00000030 0x00000040 ; Used by the CPU, RGB8:8:8 ; Conversion start trigger = write to CMSYD ; CMOS image sensor operation status ; QQVGA, interrupt CMSVSY ; FIFO pointer clear (CMSSCTR) 0x00000000 ; No Down Scaling, No Trimming (CMSUD) 0x00000011 ; YUV color difference signal write (CMSVD) 0x00000012 ; YUV color difference signal write (CMSYD) 0x00000013 ; YUV brightness signal write & Conversion start first pixel (CMSYD) 0x00000023 ; YUV brightness signal write & Conversion start second pixel (CMSUD) 0x00000031 ; YUV color difference signal write (CMSVD) 0x00000032 ; YUV color difference signal write (CMSYD) 0x00000033 ; YUV brightness signal write & Conversion start third pixel (CMSYD) 0x00000043 ; YUV brightness signal write & Conversion start fourth pixel (CMSFPT) CPU register ; RGB data read Note: Before setting the CMSCR register, be sure to set the CMSCV register. TMPA910CRA- 763 2010-06-02 TMPA910CRA (3) Using the color space conversion circuit from the CPU (using DMA) The following shows an example of converting data from the YUV to RGB format using the DMA function: In this mode, YUV data should have been ready being lined as 8 bits x 3 + 8-bit Dummy in the order of Y, U, and V in the DMA source memory in advance. YUV Data (CMSSCDMA register) 31 23 15 7 0 Dummy V-data U-data Y-data Dummy V-data U-data Y-data Dummy V-data U-data Y-data Dummy V-data U-data Y-data Dummy V-data U-data Y-data Dummy V-data U-data Y-data Dummy V-data U-data Y-data Dummy V-data U-data Y-data DMA CMOS Image Sensor Circuit FIFO Y data U data V data Color Space Converter (192Byte) FIFO Port RGB Data (CMSFPT register) 31 23 15 7 0 Dummy B-data G-data R-data Dummy B-data G-data R-data Dummy B-data G-data R-data Dummy B-data G-data R-data Dummy B-data G-data R-data Dummy B-data G-data R-data Dummy B-data G-data R-data Dummy B-data G-data R-data DMA Figure 3.22.4 YUV RGB888 conversion data flow image: FIFO Read window 4bytes By determining the period using tools such as Timer while considering the data amount and processing time of one DMA burst write, write YUV data successively by DMA started by Timer to perform a conversion YUV -> RGB by one clock. Each time 32 bytes or 48 bytes of RGB data has been stored in the FIFO, data read DMA is started from the FIFO. TMPA910CRA- 764 2010-06-02 TMPA910CRA 3.22.2.4 Reading Data from the FIFO (1) When the CMSI is used to interface a CMOS image sensor (CMSCV<CCVM1:0> =0y00 or 0y01) The RGB data generated by the color space conversion circuit is stored in the FIFO sequentially. INTCMSF is generated when 32 bytes or more of data are stored in the FIFO or when 48 bytes or more of data are stored in the FIFO. For details, see the table below. Data input from external pin (CMOS camera) Input Data Format YUV4:2:2 FIFO Output Format Output Data Format Without Dummy 32bytes RGB5:6:5 0 0 1 48bytes RGB8:8:8 1 0 1 32bytes RGB8:8:8 1 0 0 0 0 0 With Dummy *Note 1 RGB8:8:8 With Dummy *Note 1 RGB8:8:8 RGB8:8:8 +Dummy8 +Dummy8 or CMSCV Register Configuration CRGBM CCVM1 CCVM0 FIFO Interrupt Water_Mark Without Dummy 32bytes RGB5:6:5 or RGB5:6:5 Note : Dummy data is added only when the window of the FIFO buffer read register is configured to read 4 bytes of data at a time (CMCCR<CSFOW> = 0). Please note that dummy data is not added if CMCCR<CSFOW> = 1 (a byte of data reading). Refer to 3.22.2.4 (4) "Formats of RGB Storage from FIFO buffer into the CMSFPT register" for details. CMOS image sensor data is stored in the FIFO synchronously to the external CMSPCK clock. Therefore, the clock of DMA (internal HCLK) should be set appropriately to prevent the FIFO from overflowing. Reading the FIFO while valid data is not stored in it corrupts the FIFO pointer. If this happens, clear the FIFO pointer by resetting the CMSI circuit with CMSCR<CSRST> and start again.(When CMSCV<CCVM1:0> = 0y00 or 0y01, CMSCR<CFPCLR> is invalid.) TMPA910CRA- 765 2010-06-02 TMPA910CRA (2) When the color space conversion circuit is used by writing YUV data in internal registers without connecting a CMOS image sensor (CMSCV<CCVM1:0> = 0y10 or 0y11) The RGB data generated by the color space conversion circuit is stored in the FIFO sequentially. When used by the CPU, INTCMSF is also generated when 32 bytes or more of data are stored in the FIFO or when 48 bytes or more of data are stored in the FIFO, as in the case of connecting a CMOS image sensor. For details, see the table below. Reading the FIFO while valid data is not stored in it corrupts the FIFO pointer. If this happens, reset the FIFO pointer by using CMSCR<CFPCLR> and then write new YUV data. Data Input from Internal Registers CMSCV Register Configuration CRGBM CCVM1 CCVM0 Input Data Format FIFO Output Format FIFO interrupt Water_Mark Output Data Format 32bytes RGB5:6:5 0 1 0 48bytes RGB8:8:8 1 1 0 32bytes RGB5:6:5 0 1 1 48bytes RGB8:8:8 1 1 1 CMSYD Without Dummy CMSUD With Dummy CMSVD *Note Without Dummy CMSSCDMA With Dummy *Note Note : Dummy data is added only when the window of the FIFO buffer read register is configured to read 4 bytes of data at a time (CMCCR<CSFOW> = 0). Please note that dummy data is not added if CMCCR<CSFOW> = 1 (a byte of data reading). Refer to 3.22.2.4 (4) "Formats of RGB Storage from FIFO buffer into the CMSFPT register" for details. TMPA910CRA- 766 2010-06-02 TMPA910CRA (3) Precautions for using DMA When the RGB888 format (CMSCV<CRGBM> = 1) is used and color space conversion is not performed (CMSCV<CCVM1:0> = 0y00), the FIFO cannot be read with DMA requests. The CMSFPT register should be read by the CPU. DMA requests are generated with the same conditions as those for the INTCMSF interrupt. INTCMSF requests are cleared by software whereas DMA requests cannot be cleared by software. Each DMA request is cleared when 32 bytes or 48 bytes of data are read from the FIFO. For details, see Figure 3.22.5 below. 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes Empty INTCMSF Write 32 bytes DMA request Request Request 32 bytes are written Clear interrupt Cleared by S/W Read 8 bytes 8 bytes are read. *A write of 8 bytes brings the total number of bytes in the FIFO to 32 bytes. However, a new interrupt request is not generated because less than 32 bytes have been written. Write 8 bytes 8 bytes are written. Cleared Read 24 bytes 24 bytes are read. Write 24 bytes Request 24 bytes are written. Figure 3.22.5 Request *The DMA request is cleared when 32 bytes have been read. *A new DMA request is generated because 32 bytes have been written. Example of INTCMSF and DMA Request Generation When the Watermark Level Is 32 Bytes TMPA910CRA- 767 2010-06-02 TMPA910CRA (4) Formats of RGB Storage from FIFO buffer into the CMSFPT register The formats of storage into the FIFO are shown below: (a) For 4-byte read in No dummy (CMSCR<CSFOW>= 0, CMSCV<CRGBM> = 0) CMSFPT MSB 31 24 23 16 15 87 LSB 0 0xF2020020 FIFO MSB 7 LSB 0 Address0 G2G1G0 R4 R3 R2 R1 R0 Address1 B4 B3 B2 B1 B0 G5 G4 G3 Address2 G2G1G0 R4 R3 R2 R1 R0 Address3 B4 B3 B2 B1 B0 G5 G4 G3 Address4 G2G1G0 R4 R3 R2 R1 R0 Address5 B4 B3 B2 B1 B0 G5 G4 G3 : First time : Second time (b) For 4-byte read in Dummy (CMSCR<CSFOW> = 0, CMSCV<CRGBM> = 1) CMSFPT MSB 31 24 23 16 15 87 LSB 0 0xF2020020 FIFO MSB 7 LSB 0 R7 R6 R5 R4 R3 R2 R1 R0 Address0 Address1 G7G6G5 G4 G3 G2 G1 G0 1byte Address2 B7 B6 B5 B4 B3 B2 B1 B0 Address3 R7 R6 R5 R4 R3 R2 R1 R0 Address4 G7G6G5 G4 G3 G2 G1 G0 Address5 B7 B6 B5 B4 B3 B2 B1 B0 : First time : Second time (c) For 1-byte read (CMSCR<CSFOW> = 1, CMSCV<CRGBM> = 0 or 1) MSB 31 CMSFPT 24 23 16 15 87 LSB 0 0xF2020020 FIFO MSB 7 LSB 0 Address0 G2G1G0 R4 R3 R2 R1 R0 Address1 B4 B3 B2 B1 B0 G5 G4 G3 Address2 G2G1G0 R4 R3 R2 R1 R0 Address3 B4 B3 B2 B1 B0 G5 G4 G3 : First time : Second time : Third time : Forth time TMPA910CRA- 768 2010-06-02 TMPA910CRA 3.22.2.5 Color Space Conversion Circuit Bypassing Function for External Inputs This mode directly inputs the RGB format when inputting image data from external terminals. The internal color space conversion circuit is bypassed. The layout for FIFO buffer is shown below: CMSVSY CMOS Image Sensor Circuit CMSHSY Down Scaler CMSHBK Bypass CMSCV<CCVM1:0> = 0y00 /Trimmer CMSPCK Input sequence G0 R0 x B0 G0 R0 G1 R1 x B1 G1 R1 G2 R2 x B2 G2 R2 G3 R3 x B3 G3 R3 G4 R4 x B4 G4 R4 G5 R5 x B5 G5 R5 G6 R6 x B6 G6 R6 G7 R7 x B7 G7 R7 Second pixel MSB 31 FIFO CMSD [7:0] Buffer Y data U data V data Color Space Converter FIFO Port (192Byte) First pixel CMSFPT 24 23 16 15 87 FIFO LSB 0 MSB 7 0xF2020020 LSB 0 Address0 R7 R6 R5 R4 R3 R2 R1 R0 Address1 G7G6G5G4G3G2 G1 G0 First pixel Address2 B7 B6 B5 B4 B3 B2 B1 B0 Address3 x x x x x x x x Invalid Address4 R7 R6 R5 R4 R3 R2 R1 R0 Address5 G7G6G5G4G3G2 G1 G0 Second pixel Note: This example assumes that dammy data exists at input. When using 4-byte reads, set CMSCV<CRGBM>=0 to prevent the generation of dummy data when reading the FIFO. Figure 3.22.6 Data Flow When Using RGB888 and No Color Space Conversion Note: Before setting the CMSCR register, be sure to set the CMSCV register TMPA910CRA- 769 2010-06-02 TMPA910CRA 3.22.2.6 Interrupt The CMOS image sensor can generate two types of interrupts. * Interrupt in synchronization with external input signals (CMSHBK or CMSVSY) CMSVSY synchronization when CMSCR<CINTSEL> = 0 CMSHBK synchronization when CMSCR<CINTSEL> = 1 * At the point when a specified size written to the FIFO buffer 32 bytes or 48 bytes Note :Interrupts are generated not by the number of bytes stored in the FIFO buffer but by the number of bytes written to the FIFO buffer. For example, let us assume that 32 bytes have been written into the FIFO and an interrupt has been generated. In this case, if another byte is read and then another byte is written brinnging the total number of bytes in the FIFO buffer to 32 bytes, a new interrupt will not be generated. This is because only one byte has been written to the FIFO buffer. For details, see Figure 3.22.5 Mask bits and flags corresponding to each interrupt are available. Both interrupts are level-sensitive. Each interrupt flag is cleared by a write to the relevant register. TMPA910CRA- 770 2010-06-02 TMPA910CRA 3.22.2.7 Downscaling Function The original data from the CMOS image sensor can be downscaled to 1/2, 1/4 and 1/8 sizes. Downscaling is set in CMSSCTR<CSCL1:0>. Table 3.22.3 shows the relationship between each setting and the number of obtained pixels. This function is available only with 4VGA-, VGA-, QVGA-sized CMOS image sensor pixel count. Note that this function cannot be used at the same time as the trimming function. In the mode without color conversion (CMSCV<CCVM1:0> = 0y00), this function also cannot be used. Table 3.22.3 Downscaling correspondence table CMOS sensor size (number of pixels) 1/2 downscaling 1/4 downscaling 1/8 downscaling CMSSCTR<CSCL1:0> CMSSCTR<CSCL1:0> CMSSCTR<CSCL1:0> = 0y01 = 0y10 = 0y11 4VGA (1280 x 960) VGA (640 x 480) QVGA (320 x 240) QQVGA (160 x 120) VGA (640 x 480) QVGA (320 x 240) QQVGA (160 x 120) - QVGA (320 x 240) QQVGA (160 x 120) - - TMPA910CRA- 771 2010-06-02 TMPA910CRA The examples of data capturing when set to 1/2, 1/4, and 1/8 when using 4VGA (1280x960) are shown in Figure 3.22.7 below: 1280/2 Pixels 1280 Pixels P1278 P1279 P1280 LINE1 P1 P3 P5 P7 P9 P1279 LINE2 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 P1280 LINE3 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE3 P2 P4 P6 P8 P10 LINE5 P1 P3 P5 P7 P9 LINE1 P1 P2 P3 P4 P5 P6 P7 LINE4 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE5 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE6 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE7 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 P1279 LINE7 P2 P4 P6 P8 P10 LINE9 P1 P3 P5 P7 P9 P1280 P1279 LINE959 P2 P4 P6 P8 P10 P1280 After scaling LINE959 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE960 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 1280/4 Pixels P1278 P1279 P1280 LINE1 P1 P5 P9 P13 P17 P1277 LINE2 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 P1278 LINE3 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE5 P2 P6 P10 P14 P18 LINE9 P3 P7 P11 P15 P19 LINE13 P4 P8 P12 P16 P20 LINE17 P1 P5 P9 P13 P17 P1280 LINE957 P4 P8 P12 P16 P20 P1280 LINE1 P1 P2 P3 P4 P5 P6 P7 LINE4 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE5 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE6 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE7 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 P1279 P1277 LINE959 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE960 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE1 P1 P2 P3 P4 P5 P6 P7 LINE2 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 P1278 P1279 P1280 LINE3 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE1 P1 P9 P17 P25 P33 P1273 LINE4 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 P1274 LINE5 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE9 P2 P6 P18 P26 P34 LINE17 P3 P7 P19 P27 P35 P1276 P1280 1280/8 Pixels LINE6 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE7 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE25 P4 P8 P20 P28 P36 LINE33 P5 P9 P21 P29 P37 LINE959 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 LINE953 P8 P16 P24 P32 P40 LINE960 P1 P2 P3 P4 P5 P6 P7 P1278 P1279 P1280 Before scaling P1275 P1277 After scaling Figure 3.22.7 1/2 downscaling image TMPA910CRA- 772 2010-06-02 TMPA910CRA 3.22.2.8 Trimming Function The trimming function enables the CMOS image sensor data to be trimmed from a desired trimming start point to a desired size. The trimming function is enabled by setting CMSSCTR<CTREN> to 1. The start and end points are set in the CMSTS(Vertical/Horizontal) and CMSTE(Vertical/Horizontal) registers. The following shows an example of how to set the trimming function. Note that this function cannot be used at the same time as the scaling function. In the mode without color conversion (CMSCV<CCVM1:0> = 0y00), this function also cannot be used. Example of trimming setting CMOS sensor size (number of pixels) CIF (352 x 288) CMSCR1<CSIZE3:0> = 0y1000 Trimming size QVGA (320 x 240) CMSTS = 0x00100018 CMSTE = 0x00FF0157 P0 P1 P23 P24 P25 P26 P27 P28 P29 P338 P339 P340 P341 P342 P343 P344 P350 P351 LINE0 LINE15 LINE16 LINE17 LINE18 LINE253 LINE254 LINE255 LINE256 LINE287 Valid data Figure 3.22.8 Trimming function image TMPA910CRA- 773 2010-06-02 TMPA910CRA 3.22.3 Description of Registers The following lists the SFRs: Base address = 0xF202_0000 Register Address Name (base+) CMSCR 0x000 Description CMOS Image Sensor Control Register CMSCV 0x004 CMOS Image Sensor Color Space Conversion Register CMSCVP0 0x008 CMOS Image Sensor Color Conversion Parameter Register0 CMSCVP1 0x00C CMOS Image Sensor Color Conversion Parameter Register1 CMSYD 0x010 CMOS Image Sensor Soft Conversion Y-data Resister CMSUD 0x014 CMOS Image Sensor Soft Conversion U-data Resister CMSVD 0x018 CMOS Image Sensor Soft Conversion V-data Resister CMSFPT 0x020 CMOS Image Sensor FIFO Port Read Register CMSCSTR 0x024 CMOS Image Sensor Scaling & Trimming Control Register CMSTS 0x030 CMOS Image Sensor Trimming Space Start Point Setting Register CMSTE 0x034 CMOS Image Sensor Trimming Space End Point Setting Register CMSSCDMA 0x040 CMOS Image Sensor Soft Conversion DMA YUV-Data TMPA910CRA- 774 2010-06-02 TMPA910CRA The CMSI has 14 types of registers. They are connected to the CPU with the 32-bit bus. When the CMSI is used to interface a CMOS image sensor (CMSCV<CCVM1:0> = 0y01), the settings of the following registers take effect after detecting the first rising edge (when selected to Negative) of the CMSVSY signal after they have been changed. CMSCR<CSIZE3:0>, CMSCV<CRGBM> CMSRYG, CMSRUG, CMSGYG, CMSGUG, CMSGVG, CMSBYG, CMSBVG, CMSTOFS, CMSSCTR, CMSTSH, CMSTSV, CMSTEH, CMSTEV TMPA910CRA- 775 2010-06-02 TMPA910CRA 1. CMSCR (CMOS Image Sensor Control Register) Address = (0xF202_0000) + (0x0000) Bit Bit Symbol Type Reset Value [31:20] [19] [18] - Reserved CSFOW - R/W R/W Undefined 0y0 0y0 [17] CSINTF R/W 0y0 [16] CFINTF R/W 0y0 [15] CSINTM R/W 0y0 [14] CFINTM R/W 0y0 [13] CDEDLY R/W 0y0 [12] CVSYPH R/W 0y0 [11] CHSYPH R/W 0y0 [10] CHBKPH R/W 0y0 [9] CPCKPH R/W 0y0 [8] CFOVF R/W 0y0 [7] CFDEF RO 0y0 [6] CFPCLR WO 0y0 [5] CINTSEL R/W 0y0 [4:1] CSIZE3:0 R/W 0y0000 [0] CSRST R/W 0y0 Description Read as undefined. Write as zero. Read as undefined. Write as zero. FIFO Read Window "CMSFPT" switch 0y0: Use 4 bytes 0y1: Use 1 byte CMOS sync interrupt flag During READ During WRITE 0y0: No interrupt 0y0: Interrupt flag clear 0y1: With interrupt 0y1: Invalid FIFO interrupt flag During READ During WRITE 0y0: No interrupt 0y0: Interrupt flag clear 0y1: With interrupt 0y1: Invalid CMOS sync interrupt mask setting 0y0: Interrupt masked 0y1: Interrupt enabled FIFO interrupt mask setting 0y0: Interrupt masked 0y1: Interrupt enabled Enable data delay function 0y0: Disable 0y1: Enable VSYNC signal phase 0y0: Negative 0y1: Positive HSYNC signal phase 0y0: Negative 0y1: Positive HBK signal phase 0y0: Negative 0y1: Positive PCK signal data capture edge select 0y0: Rise Up 0y1: Fall Down FIFO Over Write Flag During READ During WRITE 0y0: No overwrite 0y0: Flag clear 0y1: No overwrite 0y1: Invalid FIFO Status Flag 0y0: No valid data 0y1: With valid data FIFO pointer clear 0y0: Invalid 0y1: Clear *Note 1 CMOS sync interrupt generation timing setting 0y0: CMSVSY 0y1: CMSHBK CMOS image sensor size (number of pixels) select 0y0000: QQVGA 0y0001: QVGA 0y0010: 320*180 0y0011: VGA 0y0100: Reserved 0y0101:4VGA 0y0110SXGA 0y0111: QCIF 0y1000: CIF 0y1001 to 0y1111: Reserved CMOS IS circuit reset 0y0: Invalid 0y1: Reset Note: Valid only when CMSCV<CCVM>[1] = 1. TMPA910CRA- 776 2010-06-02 TMPA910CRA [Description] a. <CSFOW> Switches the windows of the FIFO buffer read registers. 0y0: 4 bytes (However, the high-order 1 byte is invalid data when RGB888) 0y1: Byte (The high-order 3 bytes are invalid data) b. <CSINTF> Shows the state of CMOS input signal sync interrupts during read; and clears interrupt flags during write. During READ During WRITE 0y0: No sync interrupt 0y0: Interrupt flag clear 0y1: With sync interrupt 0y1: Invalid c. <CFINTF> Shows the state of FIFO interrupts during read; and clears interrupt flags during write. During READ During WRITE 0y0: No FIFO interrupt 0y0: Interrupt flag clear 0y1: With FIFO interrupt 0y1: Invalid d. <CSINTM> Sets the mask for CMOS input signal sync interrupts. 0y0: Sync interrupt masked 0y1: Sync interrupt enabled e. <CFINTM> Sets the mask for FIFO interrupts. 0y0: FIFO interrupt masked 0y1: FIFO interrupt enabled f. <CDEDLY> Captures a valid signal capture point after a delay of one clock. 0y0: Normal 0y1: 1-clock delay g. <CVSYPH> Selects the positive/negative logic of the vertical sync signal CMSVSY. 0y0: Negative logic (Negative) 0y1: Positive logic (Positive) h. <CHSYPH> Selects the positive/negative logic of the horizontal sync signal CMSHSY. 0y0: Negative logic (Negative) 0y1: Positive logic (Positive) TMPA910CRA- 777 2010-06-02 TMPA910CRA i. <CHBKPH> Selects the positive/negative logic of the valid data detection signal CMSHBK. 0y0: Negative logic (Negative): Understands data to be valid when the signal is "L". 0y1: Positive logic (Positive): Understands data to be valid when the signal is "H". j. <CPCKPH> Selects the rising/falling of the data capture edge in the clock CMSPCK signal that latches data. 0y0: Rising edge 0y1: Falling edge k. <CFOVF> This is the flag showing that the data accumulated in the FIFO is updated before read. This bit is not cleared automatically. Clear it by writing 0. During READ During WRITE 0y0: No overwrite 0y0: Flag clear 0y1: Overwrite occurred 0y1: Invalid l. <CFDEF> This is the flag showing that the FIFO contains valid data. This bit is read-only and cannot be cleared by an instruction. Until all data in the FIFO is read or <CFPCLR> = 0 is used to reset internally, 1 is retained. 0y0: No valid data 0y1: With valid data m. <CFPCLR> If data is input from internal register, writing 0y1 clears the FIFO read/write pointer. It is set to 0 when it is read. Writing is invalid if the data is input from external pin of CMOS image sensor. In this case, this bit must be cleared by using <CRST> bit. n. <CINTSEL> Selects the generation timing of the external signal sync interrupt which has two types. 0y0: Generates at CMSVSY rising edge (<CVSYPH> = 0: when set to NEGATIVE) or generates at CMSVSY falling edge ((<CVSYPH>=1: when set to POSITIVE) 0y1: Generates at CMSHBK rising edge (<CHBKPH> = 0: when set to NEGATIVE) or generates at CMSHBK falling edge (<CHBKPH> =1: when set to POSITIVE) o. <CSIZE3:0> Selects the number of valid pixels of the CMOS image sensor. TMPA910CRA- 778 2010-06-02 TMPA910CRA p. <CSRST> Resets the circuitry in the CMOS image sensor. When changing internal settings, reset the circuitry in the CMOS image sensor. Reset procedure: configure <CSRST> in order of 0, 1 (hold it for 2 CMSPCK clocks or more) and 0. 0y0: During normal operation 0y1: Internal circuit initialization (When redoing circuit settings, set this bit to 1.) Note: When read the FIFO by DMA , generated DMA request can be cleared only at the end of DMA burst transfer. This bit can not clear it. When reset CMSI circuit during reading FIFO by DMA, disable DMA channel after detecting the end of DMA burst transfer by DMASoftBReq[5] bit. Please refer to Section 3.22.5 5) Reset CMSI during requesting DMA. TMPA910CRA- 779 2010-06-02 TMPA910CRA 2. CMSCV (CMOS Image Sensor Color Space Conversion Register) Address = (0xF202_0000) + (0x0004) Bit Bit Symbol Reset Type Description Value [31:10] - - Undefined Read as undefined. Write as zero. [9] CSCVST WO 0y0 S/W conversion start 0y0: Invalid 0y1: Conversion start [8:7] CSCVTRG[1:0] R/W 0y0 S/W conversion start trigger select (Enabled only when CCVM1 = 0y1 and CCVM0 = 0y0) 0y00: Write to CMSYD 0y01: Write to CMSUD 0y10: Write to CMSVD 0y11: Write 1 to <CSCVST> [6] CCVSMMS R/W 0y0 Color space conversion factor mode select 0y0: Mode 1 0y1: Mode 2 [5] CRGBM R/W 0y0 RGB mode switching and FIFO Water Mark setting Refer to the following table for details. [4:3] CCVM[1:0] R/W 0y10 Color space conversion circuit input source Refer to the following table for details. [2] DMAEN R/W 0y0 DMA control 0y0: DMA request OFF 0y1: DMA request ON - [1:0] - Undefined Read as undefined. Write as zero. Note: When changing CMSCV<CCVM1:0>, keep CMSCR<CSRST>= 1 to be set. Configure CRGBM and CCVM [1:0] according to the following table. Data input from external pin (CMOS camera) Input Data Format YUV4:2:2 RGB8:8:8 RGB8:8:8 +Dummy8 or RGB5:6:5 CMSCV Register Configuration CRGBM CCVM1 CCVM0 0 0 1 FIFO Interrupt Water_Mark Output Data Format 32bytes RGB5:6:5 48bytes RGB8:8:8 1 0 1 32bytes RGB8:8:8 1 0 0 32bytes RGB8:8:8 +Dummy8 or RGB5:6:5 0 0 0 FIFO Output Format FIFO interrupt Water_Mark Output Data Format Without Dummy 32bytes RGB5:6:5 0 1 0 48bytes RGB8:8:8 1 1 0 32bytes RGB5:6:5 0 1 1 48bytes RGB8:8:8 1 1 1 FIFO Output Format Without Dummy With Dummy *Note 1 With Dummy *Note 1 Without Dummy Data Input from Internal Registers Input Data Format CMSYD CMSUD CMSVD CMSSCDMA With Dummy *Note Without Dummy With Dummy *Note CMSCV Register Configuration CRGBM CCVM1 CCVM0 Note : Dummy data is added only when the window of the FIFO buffer read register is configured to read 4 bytes of data at a time (CMCCR<CSFOW> = 0). Please note that dummy data is not added if CMCCR<CSFOW> = 1 (a byte of data reading). Refer to 3.22.2.4 (4) "Formats of RGB Storage from FIFO buffer into the CMSFPT register" for details. TMPA910CRA- 780 2010-06-02 TMPA910CRA 3. CMSCVP0 (CMOS Image Sensor Color Space Conversion Parameter Register0) Address = (0xF202_0000) + (0x0008) Bit Bit Symbol Type Reset Description Value [31] - - Undefined [30:24] CGVG[6:0] R/W 0y000000 Read as undefined. Write as zero. Color space conversion parameter V of Green Color Adjustment [23] - - Undefined Read as undefined. Write as zero. [22:16] CGYG[6:0] R/W 0y000000 Color space conversion parameter [15] - - Undefined Read as undefined. Write as zero. [14:8] CRVG[6:0] R/W 0y000000 Color space conversion parameter Y of Green Color Adjustment V of Red Color Adjustment [7] - - Undefined [6:0] CRYG[6:0] R/W 0y000000 Read as undefined. Write as zero. Color space conversion parameter Y of Red Color Adjustment 4. CMSCVP1 (CMOS Image Sensor Color Space Conversion Parameter Register1) Address = (0xF202_0000) + (0x000C) Bit Bit Symbol Type Reset Description Value [31] - - Undefined [30:24] CYOFS[6:0] R/W 0y000000 Read as undefined. Write as zero. Color space conversion parameter Y Offset of Red/Green/Blue Color Adjustment [23] - - Undefined Read as undefined. Write as zero. [22:16] CBUG[6:0] R/W 0y000000 Color space conversion parameter [15] - - Undefined Read as undefined. Write as zero. [14:8] CBYG[6:0] R/W 0y000000 Color space conversion parameter U of Blue Color Adjustment Y of Blue Color Adjustment [7] - - Undefined [6:0] CGUG[6:0] R/W 0y000000 Read as undefined. Write as zero. Color space conversion parameter U of Green Color Adjustment TMPA910CRA- 781 2010-06-02 TMPA910CRA 5. CMSYD (CMOS Image Sensor Soft Conversion Y-data Register) Address = (0xF202_0000) + (0x0010) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] CYD[7:0] WO Undefined Software color space conversion Y data setting Note: Although a 32-bit register, 8-bit access is also possible. Only when a write is given in the register of low-order 8 bits, color space conversion can be started. 6. CMSUD (CMOS Image Sensor Soft Conversion U-data Register) Address = (0xF202_0000) + (0x0014) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] CUD[7:0] WO Undefined Software color space conversion U data setting Note: Although a 32-bit register, 8-bit access is also possible. Only when a write is given in the register of low-order 8 bits, color space conversion can be started. 7. CMSVD (CMOS Image Sensor Soft Conversion V-data Register) Address = (0xF202_0000) + (0x0018) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:0] CVD[7:0] WO Undefined Software color space conversion V data setting Note: Although a 32-bit register, 8-bit access is also possible. Only when a write is given in the register of low-order 8 bits, color space conversion can be started. TMPA910CRA- 782 2010-06-02 TMPA910CRA (1) FIFO port register Reading this register can read the data accumulated in the FIFO. 1. CMSFPT (CMOS Image Sensor FIFO Port Read Register) Address = (0xF202_0000) + (0x0020) Bit [31:0] Bit Symbol CFIF[31:0] Type RO Reset Description Value Undefined FIFO Port Read Register TMPA910CRA- 783 2010-06-02 TMPA910CRA (2) Downscaling / trimming setting register This register selects downscaling sizes and sets trimming sizes. 1. CMSSCTR (CMOS Image Sensor Scaling & Trimming Control Register) Address = (0xF202_0000) + (0x0024) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] Reserved R/W 0y0 Always write 0. Read 0. [6:5] - - Undefined Read as undefined. Write as zero. [4] CTREN R/W 0y0 Trimming Enable 0y0: Disable 0y1: Enable [3:2] - - Undefined [1:0] CSCL[1:0] R/W 0y00 Read as undefined. Write as zero. Downscaling select 0y00: Disable(1/1) 0y01: 1/2 down scaling 0y10: 1/4 down scaling 0y11: 1/8 down scaling 2. CMSTS (CMOS Image Sensor Trimming Space Start point Setting Register) Address = (0xF202_0000) + (0x0030) Bit Bit Symbol Type Reset Description Value [31:26] - - Undefined [25:16] CTSV[9:0] R/W 0y0000000000 Trimming vertical start point setting register [15:11] - - Undefined Read as undefined. Write as zero. Read as undefined. Write as zero. [10:2] CTSH[10:2] R/W 0y000000000 Trimming horizontal start point setting register [1:0] CTSH[1:0] RO 0y00 Trimming horizontal start point setting register Since horizontal trimming is possible only at every four pixels, these two bits are always fixed to 0y00. 3. CMSTE (CMOS Image Sensor Trimming Space End point Setting Register) Address = (0xF202_0000) + (0x0034) Bit Bit Symbol Type Reset Description Value [31:26] - - Undefined [25:16] CTEV[9:0] R/W 0y0000000000 Trimming vertical endpoint setting register [15:11] - - Undefined Read as undefined. Write as zero. [10:2] CTEH[10:2] R/W 0y000000000 Trimming horizontal start point setting register [1:0] CTEH[1:0] RO 0y11 Trimming horizontal start point setting register Read as undefined. Write as zero. Since horizontal trimming is possible only at every four pixels, these two bits are always fixed to 0y11. TMPA910CRA- 784 2010-06-02 TMPA910CRA 4. CMSSCDMA (CMOS Image Sensor Soft Conversion DMA YUV-Data) Address = (0xF202_0000) + (0x0040) Bit Bit [31:24] Symbol - Type - Reset Description Value Undefined Read as undefined. Write as zero. [23:16] CVD[7:0] WO Undefined Software color space conversion V data setting [15:8] CUD[7:0] WO Undefined Software color space conversion U data setting [7:0] CYD[7:0] WO Undefined Software color space conversion Y data setting TMPA910CRA- 785 2010-06-02 TMPA910CRA 3.22.4 Connection Examples 1) Example of connection with CMSI TMPA910CRA CMSI SCL SCL SDA SDA CMSVSY VD CMSHBK HD CMSPCK DCLK CMSD [7:0] DOUT EXTCLK TMPA910CRA- 786 Clock Generator 2010-06-02 TMPA910CRA 3.22.5 Cautions during CMSI Use Before using the CMSI, please carefully read the following for proper use of the CMSI. 1) Relationship between CMSPCK and the system clock (fPCLK) When the CMSI is used to interface a CMOS image sensor (CMSCV<CCVM[1:0]> = 0y00 or 0y10), make sure that the relationship between the CMSPCK input clock and the system clock (fPCLK) is "CMSPCK x 2 fPCLK". 2) After completing all settings, set the CMSI to the normal operation state (CMSCR<CSRST> = 0). When changing settings, reset the CMSI first, and then set the CMSI again after completing the setting. 3) When the color space conversion circuit is accessed by the CPU When using the CMSI color space conversion circuit while being set to the setting which allows the circuit to be accessed by the CPU (CMSCV<CCVM1:0> = 0y11), CMSPCK, CMSHBK, CMSVSY, and CMSD[7:0] should be set as ports (PW0 to PW7, PV0 to PV2) in order to avoid the data from the CMOS sensor from being input. 4) The CMSI accumulates the data from a CMOS image sensor into the FIFO asynchronously with CPU operation. Therefore, decide the priority of DMA so that the FIFO will not overflow. 5) Reset CMSI during requesting DMA When read the FIFO (CMSFPT register) by DMA, generated DMA request can be cleared only at the end of DMA burst transfer. CMSCR<CSRST> bit can not clear it. When resetting CMSI circuit during reading FIFO by DMA, disable DMA channel after detecting the end of DMA burst transfer by DMASoftBReq[5] bit. Please refer to Figure 3.22.9 and Figure 3.22.10. TMPA910CRA- 787 2010-06-02 TMPA910CRA 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes INTCMSF DMA request Empty Write 32 bytes Request Request 32 bytes are written. Clear interrupt Cleared *The DMA request is not cleared because 32 bytes have not been transferred. Read 24 bytes 24 bytes are read. Reset CMSI (CMSCR<CSRST>=1) CMSCV<DMAEN>=0) *The read and write pointers are cleared. *The DMA request is not cleared. Disable DMA channel DMACCConfiguration<E>=0) *The DMA request is not cleared. Restart CMSI (CMSCR<CSRST>=0) CMSCV<DMAEN>=1) The DMA request still remains when the CMSI is restarted. This causes an erroneous transfer with no data written in the FIFO. Figure 3.22.9 Example of Problem When the Watermark Level is 32 Bytes and the CMSI is Reset during a DMA Burst Transfer (Transfer Width: 8 Bits, Burst Size: 32 Beats) TMPA910CRA- 788 2010-06-02 TMPA910CRA 16 bytes 16 bytes 16 bytes 16 bytes 16 bytes INTCMSF DMA request Empty Write 32 bytes Request Request 32 bytes are written. Cleared Clear Interrupt *The DMA request is not cleared because 32 bytes have not been transferred. Read 24 bytes 24 bytes are read. Reset CMSI (CMSCR<CSRST>=1) CMSCV<DMAEN>=0) *The read and write pointers are cleared. *The DMA request is not cleared. Wait until DMA bust transfer is complete DMASoftBReq[5]= 0 ? Cleared *The DMA request is cleared upon completion of the DMA burst transfer. Disable DMA channel DMACCConfiguration<E>=0) Restart CMSI (CMSCR<CSRST>=0) CMSCV<DMAEN>=1) *The DMA request has been cleared when the CMSI is restarted. So, no problem occurs. Figure 3.22.10 Example of Recommended Operation Flow when the Watermark Level is 32 Bytes and the CMSI is Reset during a DMA Burst Transfer (Transfer Width: 8 Bits, Burst Size: 32 Beats) TMPA910CRA- 789 2010-06-02 TMPA910CRA 3.23 Real-Time Clock/Melody Alarm Generator (RTCMLD) 3.23.1 Functional Overview The circuits include Real-Time Clock, Melody and Alarm generator block. The base clock is 32 kHz low frequent. Each circuit function is showed below. 1) Melody: * Can generate melody waveforms at any frequency from 4 Hz to 5461 Hz. * Can generate eight patterns of alarm output. * Can generate five types of fixed-interval interrupts (1 Hz, 2 Hz, 64 Hz, 512 Hz and 8192 Hz). * 32-bit counter that counts up every second * Compare 32-bits counter value, and generate interrupt requests (Resume request to the PMC is also corresponded) 2) Alarm: 3) RTC: TMPA910CRA- 790 2010-06-02 TMPA910CRA 3.23.2 Block Diagram MELODY block MLDFRQ<MLDF> APB bus MLDOUT Melody generator Comparator Clear APB I/F Clear 12-bit counter Stop & clear MLDCNTCR<MLDCC> XTIN ALARM block INTEN [1] (8192 Hz) 15-bit counter Interrupt detection INTEN [2] (512 Hz) INTEN [3] (64 Hz) INTEN [4] (2 Hz) XTIN INTEN [5] (1 Hz) ALMOUT Alarm waveform generation XTIN 4096Hz clock generation ALMPATERN<ALMPTSEL> ALMINTR INTS[1] RTCINTR RTC block XTIN 32768 divider 1 Hz Counter value RTCDATA RTCCOMP Control Update value RTCPRST A TMPA910CRA- 791 32bit Counter PWONREQ 2010-06-02 TMPA910CRA 3.23.3 Operational Description 3.23.3.1 Melody Generator (1) Operational overview Based on the low-speed clock (32.768 kHz), clock waveforms at any frequency from 4 Hz to 5461 Hz can be generated and output from the MLDALM pin (Inversion signal MLDALMn pin). By connecting buzzer etc outside, melody sounds can easily be played. The melody frequency is calculated as below. XTIN = 32.768 [kHz] Melody output waveform fMLD[Hz] = 32768 / (2 x N + 4) Melody setting value N = (16384/ fMLD) - 2 Note: The value N is set through the MLDFRQ<MLDF> register: N = 1 to 4095 (0x001 to 0xFFF) Setting N = 0 is prohibited. *For the above equation, see the waveform diagram below. (For reference: Basic tone scale setting table) Tone scale Frequency [Hz] MLDFRQ<MLDF> C 264 0x03C D 297 0x035 E 330 0x030 F 352 0x02D G 396 0x027 A 440 0x023 B 495 0x01F C 528 0x01D Register value: N XTIN Counter 00 01 N N + 1 00 01 02 03 Compare flag Counter cleared by the compare flag N + 2 clocks , Compare flag MELOUT 2N + 4 clocks Figure 3.23.1 Melody waveform TMPA910CRA- 792 2010-06-02 TMPA910CRA (2) Flowchart for melody setting START Yes Melody being output No Yes Stop Melody output Set MLDALMSEL<MLALMSEL> = 0y01 No Set MLDCNTCR<MLDCC>=0 Set Melody frequency No (MLDFRQ) Change Melody frequency Yes MLDCNTCR<MLDCC> 1 3 or more XTIN clocks Set melody frequency 1: Melody output No (MLDFRQ) 0: Melody stopped elapsed after setting MLDFRQL 0 Yes (Note) No 3 or more XTIN clocks Set MLDCNTCR<MLDCC> = 1 elapsed after setting MLDFRQ Yes MLDCNTCR<MLDCC> 0 1: Melody output 0: Melody stopped 1 END Note: The MLDFRQ in the flowchart can not read. Therefore, switch to the next step after the data was written and the 3-clocks of 32kHz (approx. 93 s) passed. In the other registers, switch to the next step after the data was written and confirmed the updated data by data polling. TMPA910CRA- 793 2010-06-02 TMPA910CRA 3.23.3.2 Alarm Generator (1) Operational overview At the frequency (4096 Hz) divided based on the low-speed clock (32.768 kHz), eight types of alarm waveforms can be generated and output from the MLDALM pin. By connecting buzzer etc outside, alarm sounds can easily be played. The free-running counter in the alarm generator can be used to generate five types of interval interrupts (1 Hz, 2 Hz, 64 Hz, 512 Hz and 8192 Hz). (Alarm pattern setting table) ALM register setting Alarm waveform 0x00 Fixed at 0 0x01 AL1 pattern 0x02 AL2 pattern 0x04 AL3 pattern 0x08 AL4 pattern 0x10 AL5 pattern 0x20 AL6 pattern 0x40 AL7 pattern 0x80 AL8 pattern Others Undefined (Do not set) TMPA910CRA- 794 2010-06-02 TMPA910CRA Example: Various alarm waveform patterns AL1 pattern Frequency (4096 Hz) (continuous output) 1 2 1 8 AL2 pattern (8 outputs/per second) 31.25 ms 31.25 ms 1 second 1 AL3 pattern (1 output) 500 ms 1 2 1 AL4 pattern (2 outputs/per second) 62.5 ms 62.5 ms 1 1 second 2 3 1 AL5 pattern (3 outputs/per second) 62.5 ms 62.5 ms 1 second 1 AL6 pattern (1 output) 62.5 ms 1 2 AL7 pattern (2 outputs) 62.5 ms 62.5 ms AL8 pattern (1 output) 250 ms TMPA910CRA- 795 2010-06-02 TMPA910CRA (2) Flowchart for alarm generator setting START Set ALMCNTCR<ALMCC> = 0 ALMCNTCR<ALMCC> Note 1 0: Clear and STOP 0 Set MLDALMSEL<MLALSEL> = 0y10 Set ALMPATERN Note 3 or more XTIN clocks elapsed after setting ALMPATERN Yes Set ALMCNTCR<ALMCC> = 1 ALMCNTCR<ALMCC> 0 1: Start 1 END Note: The ALMPATERN register in the flowchart can not read. Therefore, switch to the next step after the data was written and the 3-clocks of 32kHz (approx. 93 s) passed. In the other registers, switch to the next step after the data was written and confirmed the updated data by data polling. TMPA910CRA- 796 2010-06-02 TMPA910CRA 3.23.4 Real-Time Clock (1) Operational overview The real-time clock (32 bit counter) can count every second based on the frequency (1 Hz) divided from the low-speed clock (32.768 kHz). The current count value can be read from the RTCDATA register. Clock function can be easily realized By comparing the count value with the value set in the RTCCOMP register, an interrupt can be generated (can also be used as the resume signal from PCM (Power Cut Mode) state). The counter value can be changed arbitrarily by setting a value in the RTCPRST register. To keep counting time, power supply is always turned on. Even if there is no external factor to Wakeup from PCM mode, RTC can issue a power resume request to the PMC, the operation of the 1A power supply circuit can be resumed. TMPA910CRA- 797 2010-06-02 TMPA910CRA (2) Flowchart for real-time clock setting START RTCPRST updated No Yes Set RTCCOMP Set RTCCOMP (Note) Set RTCPRST No 3 or more XTIN clocks elapsed after setting RTCCOMP? Yes RTCPRST = RTCDATA? No Yes END Note: Switch to the next step after the data was written and the 3-clocks of 32 kHz (approx. 93 s) passed. TMPA910CRA- 798 2010-06-02 TMPA910CRA 3.23.5 Register descriptions The following lists the SFRs: Base address = 0xF003_0000 Register Address Name (base+) Description RTCDATA 0x0000 RTC Data Register RTCCOMP 0x0004 RTC Compare Register RTCPRST 0x0008 RTC Preset Register MLDALMINV 0x0100 Melody Alarm Invert Register MLDALMSEL 0x0104 Melody Alarm signal Select Register ALMCNTCR 0x0108 Alarm Counter Control Register ALMPATERN 0x010C Alarm Pattern Register MLDCNTCR 0x0110 Melody Counter Control Register MLDFRQ 0x0114 Melody Frequency Register RTCALMINTCTR 0x0200 RTC ALM Interrupt Control Register RTCALMMIS 0x0204 RTC ALM Interrupt Status Register TMPA910CRA- 799 2010-06-02 TMPA910CRA 1. RTCDATA (RTC Data Register) Address = (0xF003_0000) + (0x0000) Bit Bit [31:0] Symbol RTCCOUNT Type RO Reset Value Undefined Description 32-bit counter value [Description] a. <RTCCOUNT> Returns the RTC count value (32 bits) on read. 2. RTCCOMP (RTC Compare Register) Address = (0xF003_0000) + (0x0004) Bit Bit [31:0] Symbol RTCCP Type WO Reset Value Undefined Description Value to be compared with the RTC counter [Description] a. <RTCCP> A match between the counter value (in steps of 1 HZ) and the value in <RTCCP> generates an interrupt and power supply resume request. TMPA910CRA- 800 2010-06-02 TMPA910CRA 3. RTCPRST (RTC Preset Register) Address = (0xF003_0000) + (0x0008) Bit Bit [31:0] Symbol RTCPR Reset Type WO Description Value Undefined RTC counter preset value [Description] a. <RTCPR> Specifies the RTC counter preset value. 4. MLDALMINV (Melody Alarm signal Invert Register) Address = (0xF003_0000) + (0x0100) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read undefined. Write as zero. [0] MLALINV WO 0y0 MLDALM output signal inversion 0y0: Do not invert 0y1: Invert [Description] a. <MLALINV> Selects whether or not to invert the melody/alarm output. 5. MLDALMSEL (Melody Alarm Select Register) Address = (0xF003_0000) + (0x0104) Bit Bit Reset Type Symbol Description Value [31:2] - - Undefined Read undefined. Write as zero. [1:0] MLALSEL WO 0y00 Output signal select 0y00: Stop output 0y01: Melody 0y10: Alarm 0y11: Do not set [Description] a. <MLALSEL> Selects the melody or alarm output from MLDALM pin. TMPA910CRA- 801 2010-06-02 TMPA910CRA 6. ALMCNTCR (Alarm Counter Control Register) Address = (0xF003_0000) + (0x0108) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read undefined. Write as zero. [0] ALMCC R/W 0y0 Free-running counter control 0y0: Clear and stop 0y1: Start [Description] a. <ALMCC> Controls the 15-bit counter for alarm generation. 7. ALMPATERN (Alarm Pattern Register) Address = (0xF003_0000) + (0x010C) Bit Bit Reset Type Symbol Value Description [31:8] - - Undefined Read undefined. Write as zero. [7:0] ALMPTSEL WO 0x00 Alarm pattern setting (See the table below.) [Description] a. <ALMPTSEL> Selects the alarm pattern to be output. [Alarm pattern setting values] ALMPTSEL setting Alarm waveform 0x00 Fixed at 0 0x01 AL1 pattern 0x02 AL2 pattern 0x04 AL3 pattern 0x08 AL4 pattern 0x10 AL5 pattern 0x20 AL6 pattern 0x40 AL7 pattern 0x80 AL8 pattern Others Undefined (Setting prohibited) TMPA910CRA- 802 2010-06-02 TMPA910CRA 8. MLDCNTCR (Melody Counter Control Register) Address = (0xF003_0000) + (0x0110) Bit Bit Reset Type Symbol Description Value [31:1] - - Undefined Read undefined. Write as zero. [0] MLDCC R/W 0y0 Free-running counter control 0y0: Clear and stop 0y1: Start [Description] a. <MLDCC> Controls the 12-bit counter for melody generation. 9. MLDFRQ (Melody Frequency Register) Address = (0xF003_0000) + (0x0114) Bit Bit Reset Type Symbol Value Description [31:12] - - Undefined Read undefined. Write as zero. [11:0] MLDF WO 0x000 Melody output frequency setting value N: 0x001 to 0xFFF [Description] a. <MLDF > Specifies the counter value (N) for Melody output frequency setting. Formula: fMLD[Hz] = 32768/ (2N + 4) TMPA910CRA- 803 2010-06-02 TMPA910CRA 10. RTCALMINTCTR (RTC ALM Interrupt Control Register) Address = (0xF003_0000) + (0x0200) Bit Bit Reset Type Symbol Description Value [31:8] - - Undefined Read undefined. Write as zero. [7] ALMINTCLR WO 0y0 Alarm interrupt flag clear 0y0: Invalid 0y1: Clear [6] RTCINTCLR WO 0y0 RTC interrupt flag clear 0y0: Invalid 0y1: Clear [5] AINTEN1 R/W 0y0 Alarm (1 Hz) interrupt enable 0y0: Disable 0y1: Enable [4] AINTEN2 R/W 0y0 Alarm (2 Hz) interrupt enable 0y0: Disable 0y1: Enable [3] AINTEN64 R/W 0y0 Alarm (64 Hz) interrupt enable 0y0: Disable 0y1: Enable [2] AINTEN512 R/W 0y0 Alarm (512 Hz) interrupt enable 0y0: Disable 0y1: Enable [1] AINTEN8192 R/W 0y0 Alarm (8192 Hz) interrupt enable 0y0: Disable 0y1: Enable [0] RTCINTEN R/W 0y0 RTC interrupt enable 0y0: Disable 0y1: Enable [Description] a. <ALMINTCLR > Clears the enabled alarm interrupt flag. b. <RTCINTCLR> Clears the enabled RTC interrupt flag. c. <AINTEN1> Enables or disables the alarm (1 Hz) interrupt. d. <AINTEN2> Enables or disables the alarm (2 Hz) interrupt. e. <AINTEN64> Enables or disables the alarm (64 Hz) interrupt. f. <AINTEN512> Enables or disables the alarm (512 Hz) interrupt. g. <AINTEN8192> Enables or disables the alarm (8192 Hz) interrupt. h. <RTCINTEN> Enables or disables the RTC interrupt. TMPA910CRA- 804 2010-06-02 TMPA910CRA 11. RTCALMMIS (RTC ALM Masked Interrupt Status Register) Address = (0xF003_0000) + (0x0204) Bit Bit Reset Type Symbol Value Description [31:2] - - Undefined Read undefined. [1] ALMINT RO 0y0 Alarm interrupt enabled status 0y0: Interrupt not requested 0y1: Interrupt requested [0] RTCINT RO 0y0 RTC interrupt enabled status 0y0: Interrupt not requested 0y1: Interrupt requested RTCALMINTCTR<XXXINTEN> RTCALMMIS<XXXINT> XXXRIS (raw interrupt) TMPA910CRA- 805 2010-06-02 TMPA910CRA z Notes: (1) The RTC count-up control register always counts up. The 32 bit counter of RTC can't be stopped. (2) After power-on, The RTCCOMP and RTCPRST registers are undefined. So The RTCCOMP and RTCPRST registers must be confined, and confirm the right data, can be read from the RTCDATA register, then can set interrupt to Enable state. If the RTCCOMP, RTCPRST and other RTC relation registers are undefined state, don't set MCU to the PCM mode. Unexpected action resume from PCM maybe happen. Please pay attention to it. (3) The RTCDATA value is updated after the 1A power supply is resumed and the approximately one second elapsed. Therefore, do not display time or use time data until one second elapses after the power supply is resumed. TMPA910CRA- 806 2010-06-02 TMPA910CRA 3.24 Analog/Digital Converter A 10-bit serial conversion analog/digital converter (AD converter) having six channels of analog input is built in. Figure 3.24.1 shows the block diagram of the AD converter. The six channels of analog input pins (AN0 to AN5) are used also as input dedicated ports D (PD0 to PD5). Note 1: To reduce the power supply current by PCM mode, the standby state may be maintained with the internal comparator still being enabled, depending on the timing. Check that the AD converter operation is in a stop before executing mode switching. Note 2: Setting ADMOD1<DACON> = 0 while the AD converter is in a stop can reduce current consumption. Internal data bus ADS ADMOD1 ADMOD0 ADMOD3 ADMOD2 ITM ADMOD4 HPADCE ADS Scan repeat Channel select control circuit AD monitoring function interrupt ADCMINT AD monitoring function control INTS[8] AD start control End Busy Start Normal AD conversion control circuit End Busy Start Top-priority AD conversion control Top-priority AD conversion end interrupt (ADCHPINT) Normal AD conversion end interrupt (ADCNINT) AN3 (PD3) AN2 (PD2) AN1 (PD1) AN0 (PD0) Compare register Sampling Hold + - Comparator DACON Compare circuit AD conversion result register ADREG0L to 5L ADREG0H to 5H Internal data bus AN4 (PD4) Multiplexer AN5 (PD5) Top-priority AD conversion result register ADREGSPH/L VREF VREFH VREFL D/A converter Figure 3.24.1 Block diagram of AD converter TMPA910CRA- 807 2010-06-02 TMPA910CRA 3.24.1 Description of Registers The following lists the SFRs: Base address = 0xF008_0000 Register Address Name (base+) Description ADREG0L 0x0000 A/D conversion result lower-order register 0 ADREG0H 0x0004 A/D conversion result higher-order register 0 ADREG1L 0x0008 A/D conversion result lower-order register 1 ADREG1H 0x000C A/D conversion result higher-order register 1 ADREG2L 0x0010 A/D conversion result lower-order register 2 ADREG2H 0x0014 A/D conversion result higher-order register 2 ADREG3L 0x0018 A/D conversion result lower-order register 3 ADREG3H 0x001C A/D conversion result higher-order register 3 ADREG4L 0x0020 A/D conversion result lower-order register 4 ADREG4H 0x0024 A/D conversion result higher-order register 4 ADREG5L 0x0028 A/D conversion result lower-order register 5 ADREG5H 0x002C A/D conversion result higher-order register 5 - 0x0030 Reserved - 0x0034 Reserved - 0x0038 Reserved - 0x003C Reserved ADREGSPL 0x0040 Top-priority A/D conversion result lower-order register ADREGSPH 0x0044 Top-priority A/D conversion result higher-order register ADCOMREGL 0x0048 A/D conversion result comparison lower-order register ADCOMREGH 0x004C A/D conversion result comparison lower-order register ADMOD0 0x0050 A/D mode control register 0 ADMOD1 0x0054 A/D mode control register 1 ADMOD2 0x0058 A/D mode control register 2 ADMOD3 0x005C A/D mode control register 3 ADMOD4 0x0060 A/D mode control register 4 - 0x0064 Reserved - 0x0068 Reserved - 0x006C Reserved ADCLK 0x0070 A/D conversion clock setting register ADIE 0x0074 A/D interrupt enable register ADIS 0x0078 A/D interrupt status register ADIC 0x007C A/D interrupt clear register - 0x0080 Reserved - : Reserved - 0x0FFF Reserved Note: Notes for Description of Registers R/W: Read/Write possible RO: Readable / Write not reflected WO: Writable / 0 can be read when read TMPA910CRA- 808 2010-06-02 TMPA910CRA 3.24.1.1 Control Registers The A/D converter is controlled by the A/D mode control registers (ADMOD0, ADMOD1, ADMOD2, ADMOD3, and ADMOD4). A/D conversion results are stored in the six registers of A/D conversion result higher-order/lower-order registers ADREG0H/L to ADREG5H/L. Top-priority conversion results are stored in ADREGSPH/L. * ADMOD register 1. ADMOD0 (AD mode control register 0) Address = (0xF008_0000) + (0x0050) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined [7] EOCFN (Note) RO 0y0 Read as undefined. Write as zero. Normal AD conversion end flag Read: 0y0: Before conversion or being converted 0y1: End Write: [6] ADBFN RO 0y0 Invalid Normal AD conversion BUSY flag Read: 0y0: Conversion stop 0y1: Being converted Write: Invalid [5] - RO 0y0 Always read as 0 when read. [4] - R/W 0y0 Always write 0 [3] ITM R/W 0y0 Specifies the A/D conversion interrupt during channel fix and repeat conversion mode. ITM 0y0: Generates an interrupt per one conversion 0y1: Generates an interrupt per four conversions [2] REPEAT R/W 0y0 Specifies repeat mode. 0y0: Single conversion mode 0y1: Repeat conversion mode [1] SCAN R/W 0y0 Specifies scan mode. 0y0: Channel fix mode 0y1: Channel scan mode [0] ADS R/W 0y0 A/D conversion start 0y0: Don't care 0y1: Start Conversion Always read as 0 when read. R/W : Read/Write RO : Read Only WO : Write Only Note: As read this register, <EOCFN> is clear to 0. [Description] a. <EOCFN> They are the normal AD conversion end flag. 0y0: Before conversion or being converted 0y1: End TMPA910CRA- 809 2010-06-02 TMPA910CRA b. <ADBFN> They are the normal AD conversion BUSY flag. 0y0: Conversion stop 0y1: Being converted c. <ITM> Selects the A/D conversion interrupt during channel fix and repeat conversion mode. 0y0: Generates an interrupt per one conversion 0y1: Generates an interrupt per four conversions d. <REPEAT> Selects the repeat mode. 0y0: Single conversion mode 0y1: Repeat conversion mode e. <SCAN > Selects the scan mode. 0y0: Channel fix mode 0y1: Channel scan mode f. <ADS> Selects the A/D conversion start mode. 0y0: Don't care 0y1: Start Conversion mode Always read as 0 when read. TMPA910CRA- 810 2010-06-02 TMPA910CRA 2. ADMOD1 (AD mode control register 1) Address = (0xF008_0000) + (0x0054) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] DACON R/W 0y0 Read as undefined. Write as zero. VREF application control 0y0: OFF 0y1: ON [6] - RO 0y0 Always read as 0 when read. [5] ADSCN R/W 0y0 Operation mode setting during channel scan 0y0: 4-ch scan 0y1: 6-ch scan [4:3] - R/W 0y00 Always write 0. [2:0] ADCH[2:0] R/W 0y000 Analog input channel select SCAN 0 ADSCN 0/1 0 1 0y000 AN0 AN0 AN0 0y001 AN1 AN0 to AN1 AN0 to AN1 0y010 AN2 AN0 to AN2 AN0 to AN2 ADCH 0y011 AN3 AN0 to AN3 AN0 to AN3 [2:0] 0y100 AN4 AN4 AN0 to AN4 0y101 AN5 AN4 to AN5 AN0 to AN5 0y11x 1 Don't set R/W : Read/Write RO : Read Only WO : Write Only Note 1: To start AD conversion, be sure to write 1 in the ADMOD1<DACON>, and then wait for 3 s, which is the time taken until the internal reference voltage is stabilized, and then write 1 in the ADMOD0<ADS>. Note 2: To switch to standby mode after AD conversion end, set 0 in the ADMOD1<DACON>. [Description] a. <DACON> Controls the VREF application. 0y0: OFF 0y1: ON b. <ADSCN> Sets the operation mode during channel scan. 0y0: 4-ch scan 0y1: 6-ch scan TMPA910CRA- 811 2010-06-02 TMPA910CRA c. <ADCH[2:0]> Selects analog input channels. SCAN 0 ADSCN 0/1 0 1 0y000 AN0 AN0 AN0 0y001 AN1 AN0 to AN1 AN0 to AN1 0y010 AN2 AN0 to AN2 AN0 to AN2 0y011 AN3 AN0 to AN3 AN0 to AN3 0y100 AN4 AN4 AN0 to AN4 0y101 AN5 AN4 to AN5 AN0 to AN5 ADCH[2:0] 0y11x 1 Don't set TMPA910CRA- 812 2010-06-02 TMPA910CRA 3. ADMOD2 (AD mode control register 2) Address = (0xF008_0000) + (0x0058) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7] EOCFHP(Note) RO 0y0 Read as undefined. Write as zero. Top-priority AD conversion end flag Read: 0y0: Before conversion or being converted 0y1: End Write: [6] ADBFHP RO 0y0 Invalid Top-priority AD conversion BUSY flag Read: 0y0: Conversion stop 0y1: Being converted Write: [5] HPADCE R/W 0y0 Invalid Top-priority AD conversion start 0y0: Don't care 0y1: Conversion start. Always read as 0 when read. [4:3] - R/W 0y00 [2:0] HPADCH[2:0] R/W 0y000 Always write 0. Analog input channel select during top-priority conversion 0y000: AN0, 0y010: AN2, 0y100: AN4, 0y110: Reserved 0y001: AN1, 0y011: AN3, 0y101: AN5, 0y111: Reserved R/W : Read/Write RO : Read Only WO : Write Only Note: As read this register, <EOCFHP> is clear to 0. [Description] a. <EOCFHP> Used to set the top-priority AD conversion end flag. 0y0: Before conversion or being converted 0y1: End b. <ADBFHP> Used to set the top-priority AD conversion BUSY flag. 0y0: Conversion stop 0y1: Being converted c. <HPADCE> Controls the start of top-priority AD conversion. 0y0: Don't care 0y1: Conversion start Note: Always read as 0 when read. d. <HPADCH[2:0]> Analog input channel select during top-priority conversion 0y000: AN0 0y010: AN2 0y100: AN4 0y110: Reserved 0y001: AN1 0y011: AN3 0y101: AN5 0y111: Reserved TMPA910CRA- 813 2010-06-02 TMPA910CRA 4. ADMOD3 (AD mode control register 3) Address = (0xF008_0000) + (0x005C) Bit Bit Type Symbol - Reset Description Value [31:8] - [7] - R/W 0y0 Always write 0. [6] - RO 0y0 Always read as 0 when read. [5] ADOBIC R/W 0y0 Undefined Read as undefined. Write as zero. AD monitoring function interrupt setting 0y0: Smaller than the comparison register settings 0y1: Greater than the comparison register settings [4:1] REGS[3:0] R/W 0y0000 Bit to select the AD conversion result storage register to be compared with the settings of the comparison register during when the AD monitoring function is enabled REGS[3:0] 0y0000: ADREG0 0y0110: Reserved 0y0001: ADREG1 0y0111: Reserved 0y0010: ADREG2 0y0011: ADREG3 0y1xxx: ADREGSP 0y0100: ADREG4 0y0101: ADREG5 [0] ADOBSV R/W 0y0 AD monitoring function 0y0: Disable 0y1: Enable R/W : Read/Write RO : Read Only WO : Write Only [Description] a. <ADOBIC> Sets the AD monitoring function interrupt. 0y0: Smaller than the comparison register settings 0y1: Greater than the comparison register settings b. <REGS[3:0]> Selects the AD conversion result storage register to be compared with the settings of the comparison register during when the AD monitoring function is enabled. 0y0000: ADREG0 0y0110: Reserved 0y0001: ADREG1 0y0111: Reserved 0y0010: ADREG2 0y0011: ADREG3 0y1xxx: ADREGSP 0y0100: ADREG4 0y0101: ADREG5 c. <ADOBSV> Controls the AD monitoring function. 0y0: Disable 0y1: Enable TMPA910CRA- 814 2010-06-02 TMPA910CRA 5. ADMOD4 (AD mode control register 4) Address = (0xF008_0000) + (0x0060) Bit Bit Type Symbol Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] - R/W 0y0 Always write 0. [6] - R/W 0y0 Always write 0. [5] - R/W 0y0 Always write 0. [4] - R/W 0y0 Always write 0. [3:2] - RO 0y00 Always read as 0 when read. [1:0] ADRST[1:0] R/W 0y00 Resets the ADC software by the write of 0y10 0y01. Initializes all except the (ADCLK) register. R/W : Read/Write RO : Read Only WO : Write Only Note: Do not set top-priority AD conversion at the same time as normal AD conversion. [Description] a. <ADRST[1:0]> Resets the ADC software by the write of 0y10 0y01. Initializes all except the ADCLK register. TMPA910CRA- 815 2010-06-02 TMPA910CRA * AD conversion result register. A/D conversion results are stored in the six registers of A/D conversion result higher-order/lower-order registers ADREG0H/L to ADREG5H/L. Top-priority conversion results are stored in ADREGSPH/L. Since these registers are structured the same, ADREG0 that is the conversion result storage register for the 0 channel is shown below: 1. ADREG0L (AD conversion result lower-order register 0 Address = (0xF008_0000) + (0x0040) Bit Bit Symbol Reset Type Description Value [31:8] - - Undefined Read as undefined. [7] ADR01 RO 0y0 AD conversion result lower-order bit 1 [6] ADR00 RO 0y0 AD conversion result lower-order bit 0 [5:2] - RO 0y0000 Always read as 0 when read. [1] OVR0 RO 0y0 Overrun flag 0y0: No overrun occurred 0y1: Overrun occurred [0] ADR0RF RO 0y0 AD conversion result storage flag 0y0: No change result 0y1: With conversion result R/W : Read/Write RO : Read Only WO : Write Only [Description] a. <ADR0[1:0]> They are AD conversion result lower-order bits 1 to 0. b. <OVR0> Used for the overrun flag. 0y0: No overrun occurred 0y1: Overrun occurred c. <ADR0RF> Used for the AD conversion result storage flag. 0y0: No change result 0y1: With conversion result Note : As ADREG0L to ADREG5L and ADREGSPL Registers are the same composition. Explain Register ADREG0L only, the other Registers are same as ADREG0L. About the address of ADREG1L to ADREG5L and ADREGSPL Register, please check Register Map. TMPA910CRA- 816 2010-06-02 TMPA910CRA 2. ADREG0H (AD conversion result higher-order register 0)) Address = (0xF008_0000) + (0x0044) Bit Bit Symbol Reset Type Description Value [31:8] - - [7] ADR09 RO 0y0 AD conversion result higher-order bit 9 [6] ADR08 RO 0y0 AD conversion result higher-order bit 8 [5] ADR07 RO 0y0 AD conversion result higher-order bit 7 [4] ADR06 RO 0y0 AD conversion result higher-order bit 6 [3] ADR05 RO 0y0 AD conversion result higher-order bit 5 [2] ADR04 RO 0y0 AD conversion result higher-order bit 4 [1] ADR03 RO 0y0 AD conversion result higher-order bit 3 [0] ADR02 RO 0y0 AD conversion result higher-order bit 2 Undefined Read as undefined. R/W : Read/Write RO : Read Only WO : Write Only 9 8 7 6 5 4 3 2 1 0 Conversion setting of channel x ADREGxH 7 6 ADREGxL 5 4 3 2 1 0 * * * 7 6 5 4 3 2 1 0 Always read as 0 when bits 5 to 2 are read. Bit 0 is the AD conversion result storage flag <ADRxRF>. Set to 1 when AD conversion settings are stored. Cleared to 0 when the lower-order register (ADREGxL) is read. Bit 1 is the overrun flag <OVRx>. Set to 1 when conversion results are overwritten before reading the both conversion result storage registers (ADREGxH, ADREGxL). Cleared to 0 by flag read. [Description] a. <ADR0[9: 2]> They are AD conversion result higher-order bits 9 to 2. Note : As ADREG0H to ADREG5H and ADREGSPH Registers are the same composition. Explain Register ADREG0H only, the other Registers are same as ADREG0H. About the address of ADREG1H to ADREG5H and ADREGSPH Register, please check Register Map. TMPA910CRA- 817 2010-06-02 TMPA910CRA * AD conversion result comparison register 1. ADCOMREGL (A/D conversion result comparison lower-order register) Address = (0xF008_0000) + (0x0048) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined [7:6] ADRCOM[1:0] R/W 0y00 AD conversion result comparison lower-order bit 1 to 0 [5:0] - RO 0y00000 Always read as 0 when read. Read as undefined. Write as zero. R/W : Read/Write RO : Read Only WO : Write Only [Description] a. <ADRCOM[1:0]> They are AD conversion result comparison lower-order bits 1 to 0. 2. ADCOMREGH (A/D conversion result comparison higher-order register) Address = (0xF008_0000) + (0x004C) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] ADRCOM9 R/W 0y0 AD conversion result comparison higher-order bit 9 [6] ADRCOM8 R/W 0y0 AD conversion result comparison higher-order bit 8 [5] ADRCOM7 R/W 0y0 AD conversion result comparison higher-order bit 7 [4] ADRCOM6 R/W 0y0 AD conversion result comparison higher-order bit 6 [3] ADRCOM5 R/W 0y0 AD conversion result comparison higher-order bit 5 [2] ADRCOM4 R/W 0y0 AD conversion result comparison higher-order bit 4 [1] ADRCOM3 R/W 0y0 AD conversion result comparison higher-order bit 3 [0] ADRCOM2 R/W 0y0 AD conversion result comparison higher-order bit 2 R/W : Read/Write RO : Read Only WO : Write Only Note: When setting or changing values in this register, keep the AD monitoring function disabled (ADMOD3<ADOBSV> = 0). [Description] a. <ADRCOM[9:2]> They are AD conversion result comparison higher-order bits 9 to 2. TMPA910CRA- 818 2010-06-02 TMPA910CRA * AD Conversion Clock Setting Register 1. ADCLK (AD conversion clock setting register) Address = (0xF008_0000) + (0x0070) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7] - R/W 0y1 Always write 1. [6:4] - R/W 0y000 Always write 0. [3] - RO 0y0 Always read as 0 when read. [2:0] ADCLK[2:0] R/W 0y000 AD prescaler output select AD conversion 1-clock period = 0y000: PCLK 0y001: PCLK/2 0y010: PCLK/4 0y011: PCLK/8 0y1xx: PCLK/16 R/W : Read/Write RO : ReadOnly WO : WriteOnly Note 1: While AD conversion is executed with a clock selected in the register above, at this time, a conversion clock needs to be selected so that the AD conversion clock can be 33 MHz or less in order to meet the guaranteed accuracy. Note 2: During AD conversion, do not switch the conversion clock. [Description] a. <ADCLK[2:0]> Selects the AD prescaler output. AD conversion 1-clock period = 0y000: PCLK 0y001: PCLK/2 0y010: PCLK/4 0y011: PCLK/8 0y1xx: PCLK/16 TMPA910CRA- 819 2010-06-02 TMPA910CRA ADCLK [2:0] PCLK /1 /2 /4 /8 / 16 Conversion clock ADCLK PCLK 100MHz 96MHz <ADCLK2:0> ADCLK AD conversion speed Setting disabled 0y00x - 0y010 (PCLK/4) 25MHz 1.84 sec 0y00x - Setting disabled 0y010 (PCLK/4) 24MHz 1.92 sec AD conversion speed can be determined with the following formula. Conversion speed = 46 x (1/ADCLK) Note: In the period of AD conversion, Don't change the clock of ADCLK . TMPA910CRA- 820 2010-06-02 TMPA910CRA * Interrupt Register 1. ADIE (A/D interrupt enable register) Address = (0xF008_0000) + (0x0074) Bit Bit Symbol Type Reset Description Value [31:8] - - Undefined Read as undefined. Write as zero. [7:3] - RO 0y00000 Always read as 0 when read. [2] MIE R/W 0y0 AD monitoring interrupt enable 0y0: Disable 0y1: Enable [1] HPIE R/W 0y0 Top-priority AD conversion interrupt enable 0y0: Disable 0y1: Enable [0] NIE R/W 0y0 Normal AD conversion interrupt enable 0y0: Disable 0y1: Enable R/W : Read/Write RO : Read Only WO : Write Only [Description] a. <MIE> Controls the AD monitoring interrupt. 0y0: Disable 0y1: Enable b. <HPIE> Controls the top-priority AD conversion interrupt. 0y0: Disable 0y1: Enable c. <NIE> Controls the normal AD conversion interrupt. 0y0: Disable 0y1: Enable TMPA910CRA- 821 2010-06-02 TMPA910CRA 2. ADIS (AD interrupt status register) Address = (0xF008_0000) + (0x0078) Bit Bit Symbol [31:8] - [7:3] [2] Type Reset Description Value - Undefined - RO 0y00000 Always read as 0 when read. MIS RO 0y0 Status of before masking an AD monitoring interrupt Read as undefined. Write as zero. 0y0: No 0y1: Interrupt occurred [1] HPIS RO 0y0 Status of before masking a top-priority AD conversion interrupt 0y0: No 0y1: Interrupt occurred [0] NIS RO 0y0 Status of before masking a normal AD conversion interrupt 0y0: No 0y1: Interrupt occurred R/W : Read/Write RO : Read Only WO : Write Only [Description] a. <MIS> They are the status of before masking an AD monitoring interrupt. 0y0: No 0y1: Interrupt occurred b. <HPIS> They are the status of before masking a top-priority AD conversion interrupt. 0y0: No 0y1: Interrupt occurred c. <NIS> They are the status of before masking a normal AD conversion interrupt. 0y0: No 0y1: Interrupt occurred TMPA910CRA- 822 2010-06-02 TMPA910CRA 3. ADIC (AD interrupt clear register) Address = (0xF008_0000) + (0x007C) Bit Bit Symbol Type Reset Description Value [31:8] - - [7:3] - RO 0y00000 Always read as 0 when read. [2] MIC WO 0y0 AD monitoring interrupt clear Undefined Read as undefined. Write as zero. 0y0: - 0y1: Clear [1] HPIC WO 0y0 Top-priority AD conversion interrupt clear 0y0: - 0y1: Clear [0] NIC WO 0y0 Normal AD conversion interrupt clear 0y0: - 0y1: Clear R/W : Read/Write RO : Read Only WO : Write Only [Description] a. <MIC> Controls the AD monitoring interrupt. 0y0: - 0y1: Clear b. <HPIC> Controls the top-priority AD conversion interrupt. 0y0: - 0y1: Clear c. <NIC> Controls the normal AD conversion interrupt. 0y0: - 0y1: Clear Normal AD conversion End interrupt ADCNINT <NIE> <NIC> <NIS> Top-priority AD conversion End interrupt ADCHPINT <HPIE> AD conversion End interrupt ADCINT <HPIS> <HPIC> AD monitor interrupt ADCMINT <MIE> <MIC> <MIS> TMPA910CRA- 823 2010-06-02 TMPA910CRA 3.24.2 Description of Operation 3.24.2.1 Analog Reference Voltage Apply the analog reference voltage's "H" level side to the VREFH pin and the "L" level side to the VREFL pin. Writing 0 in the ADMOD1<DACON> can turn OFF the switch for VREFH - VREFL. To start AD conversion, be sure to write 1 in the DACON, and then wait for 3 s, which is the time taken until the internal reference voltage is stabilized, and then write 1in the ADMOD0<ADS>. 3.24.2.2 Selecting Analog Input Channels Selecting an analog input channel depends on the operation mode of the AD converter. (1) For normal AD conversion When using an analog input channel in fix mode, select one channel from the AN0 to AN5 pins by setting (ADMOD0<SCAN> = 0) ADMOD1<ADCH[2:0]>. When using an analog input channel in scan mode, select one scan mode from the six scan modes by setting (ADMOD0<SCAN> = 1) ADMOD1 <ADCH[2:0]>. (2) For top-priority AD conversion Select one channel from the analog input pins AN0 to AN5 by setting ADMOD2<HPADCH[2:0]>. After reset, ADMOD0<SCAN> is initialized to 0 and ADMOD1<ADCH[2:0]> to 0y000. Since these settings are used for channel selection, the channel fixed input with the AN0 pin will be selected. Pins not used as analog input channels can be used as normal ports. TMPA910CRA- 824 2010-06-02 TMPA910CRA 3.24.2.3 AD Conversion Start The AD conversion has the two types of normal AD conversion and top-priority AD conversion. Normal AD conversion can be started up by setting ADMOD0<ADS> to 1. Top-priority AD conversion can be started up by software by setting ADMOD2<HPADCE> to 1. For normal AD conversion, one operation mode is selected from the four types of operation modes specified by ADMOD0<REPEAT, SCAN>. The operation mode for top-priority AD conversion is only single conversion by channel fix mode. When normal AD conversion is started, the AD conversion BUSY (ADMOD0<ADBFN>) that shows the state for AD being converted is set to 1. flag When top-priority AD conversion is started, the AD conversion BUSY flag (ADMOD2<ADBFHP>) that shows the state for AD being converted is set to 1. In addition, when top-priority conversion is started during normal AD conversion, ADMOD0<ADBFN> is kept to 1. <EOCFHP> and <EOCFN> are set to 1 after conversion is completed. This flag is cleared to 0 only when read. Two type AD conversion can be used. During Normal AD conversion is executing, Top-priority AD conversion can be carried out first. When ADMOD2<HPADCE> is set to 1 during normal AD conversion, top-priority AD conversion's startup, normal AD conversion being converted currently is cancelled immediately. Then, top-priority AD conversion is started, starting the AD conversion (channel fix single conversion) for the channel specified by ADMOD2<HPADCH[2:0]>. When this result is stored into ADREGSPH/L, normal AD conversion is restarted from the cancelled channel. But during top-priority AD conversion, can't set top-conversion AD conversion again. If top-priority AD conversion need to be set again, have to check that top-priority AD conversion being converted currently is end (AD conversion End flag: ADMOD<ADBFHP>). Then top-priority conversion AD conversion can be started. TMPA910CRA- 825 2010-06-02 TMPA910CRA 3.24.2.4 AD Conversion Modes and AD Conversion End Interrupt For AD conversion, the following four operation modes are provided: For normal AD conversion, selection is available by setting ADMOD0<REPEAT and SCAN>. As for top-priority AD conversion, only single conversion mode by channel fix mode is available. a. Channel-fix single conversion mode b. Channel-scan single conversion mode c. Channel-fix repeat conversion mode d. Channel-scan repeat conversion mode (1) Normal AD conversion To select operation modes, use ADMOD0<REPEAT, SCAN>. After AD conversion is started, ADMOD0<ADBFN> is set to 1. When a specified AD conversion ends, the Normal AD conversion end interrupt is generated, ADMOD0<EOCFN> is set 1 , shows the end of the AD conversion sequence. a. Channel-fix single conversion mode Setting ADMOD0 <REPEAT, SCAN> to 0y00 selects the channel-fix single conversion mode. This mode performs a conversion only one time at one channel selected. After conversion ends, ADMOD0<EOCFN> is set to 1, generating Normal AD conversion End interrupt request. <EOCFN> is cleared to 0 only by being read. b. Channel-scan single conversion mode Setting ADMOD0 <REPEAT, SCAN> to 0y01 selects the channel-scan single conversion mode. This mode performs a conversion only one time at each scan channel selected. After scan conversion ends, ADMOD0<EOCFN> is set to 1, generating Normal AD conversion End interrupt request. <EOCFN> is cleared to 0 only by being read. c. Channel-fix repeat conversion mode Setting ADMOD0<REPEAT, SCAN> to 0y10 selects the channel-fix repeat conversion mode. This mode performs a conversion at one channel selected repeatedly. After conversion ends, ADMOD0<EOCFN> is set to 1. The timing of Normal AD conversion End interrupt request generation can be selected by setting ADMOD0 <ITM>. The timing of <EOCFN> being set is also linked to the interrupt timing. ADMOD0<EOCFN> is cleared to 0 only by being read. Setting <ITM> to 0 generates an interrupt request each time an AD conversion ends. In this case, conversion results are always stored into the storage register of ADREGxH/L. At the point of storage, <EOCFN> is set to 1. Setting <ITM> to 1 generates an interrupt request each time four AD conversions end. In this case, conversion results are stored into the storage registers of ADREG0H/L to ADREG3H/L one after another. After stored into ADREG3, <EOCFN> is set to 1, restarting storage from ADREG0. <EOCFN> is cleared to 0 only by being read. TMPA910CRA- 826 2010-06-02 TMPA910CRA d. Channel-scan repeat conversion mode Setting ADMOD0 <REPEAT, SCAN> to 0y11 selects the channel-scan repeat conversion mode. This mode performs a conversion at selected scan channels repeatedly. Each time after the conversion at a final channel ends, ADMOD0<EOCFN> is set to 1, generating Normal AD conversion End interrupt request. <EOCFN> is cleared to 0 only by being read. To stop the repeat conversion mode (mode of c and d) operation, write 0 in ADMOD1 <REPEAT>. At the point when a scan conversion being executed ends, the repeat conversion mode ends. (2) Top-priority AD conversion The operation mode is only single conversion by channel fix mode. The settings in ADMOD0<REPEAT, SCAN> are not involved. When startup conditions are established, a conversion at a channel specified by ADMOD2<HPADCH[2:0]> is performed only one time. When conversion ends, the top-priority AD conversion end interrupt is generated, which sets 1 in ADMOD2<EOCFHP>. The EOCFHP flag is cleared to 0 only by being read. Table 3.24.1 Relationship between AD conversion mode, interrupt generation timing, and flag operation Conversion mode Channel fix Single conversion Channel fix Repeat conversion Channel scan Single conversion Channel scan Repeat conversion Interrupt generation timing EOCFN set timing After conversion end ADMOD0 ITM REPEAT SCAN After conversion end - 0 0 Per one conversion Each time after one conversion ends 0 Per four conversions Each time after four conversions end 1 0 1 After scan conversion end After scan conversion end - 0 1 Each time after one scan conversion ends Each time after one scan conversion ends - 1 1 (Note) Note: EOCFN is cleared to 0 only by being read. TMPA910CRA- 827 2010-06-02 TMPA910CRA 3.24.2.5 Top-Priority Conversion Mode Top-priority AD conversion can be performed by interrupting into normal AD conversion. Top-priority AD conversion can be started up by software while setting ADMOD2<HPADCE> to 1 When top-priority AD conversion is started up during normal AD conversion, the AD conversion being converted currently is cancelled immediately to execute the single conversion at a channel specified by ADMOD2<HPADCH[2:0]>. The conversion result is stored into ADREGSPH/L, generating a top-priority AD conversion interrupt. After that, conversion is restarted from the channel where normal AD conversion was cancelled. Note that a top-priority AD conversion started up during another top-priority AD conversion is ignored. Example: When AN5 top-priority AD conversion is started up with ADMOD2 <HPADCH[2:0]> = 0y101 during repeat scan conversion at channels AN0 to AN3 with ADMOD0 <REPEAT,SCAN> = 0y11 and ADMOD1<ADCH[2:0]> = 0y011 Top-priority AD conversion start Conversion channel AN0 AN1 AN2 AN2 conversion canceled AN5 AN2 AN3 AN0 AN2 re-conversion started AN5 conversion started 3.24.2.6 AD Monitoring Function Setting ADMOD3<ADOBSV> to 1 enables the AD monitoring function. The value of Result storage register that is appointed by ADMOD3<REGS [3:0]> is compared with the value of AD conversion result register (H/L), ADMOD3<ADOIBC> can select greater or smaller of comparison format. As register ADIE<MIE> is Enable, This comparison operation is performed each time when a result is stored in the corresponding conversion result storage register. When conditions are met, the interrupt is generated. Be careful that the storage registers assigned for the AD monitoring function are usually not ready by software, which means that the overrun flag <OVRx> is always set and the conversion result storage flag <ADRxRF> is also set. 3.24.2.7 AD Conversion Time One AD conversion takes 46 clocks including sampling clocks. The AD conversion clock is selected from 1/1, 1/2, 1/4, 1/8 PCLK by <ADCLK[2:0]>. To meet the guaranteed accuracy, the AD conversion clock needs to be set from 0.625MHz to 33 MHz, or equivalently from 1.39s to 73.6s of AD conversion time. TMPA910CRA- 828 2010-06-02 TMPA910CRA 3.24.2.8 Storage and Read of AD Conversion Results A/D conversion results are stored in the A/D conversion result higher-order/lower-order registers (ADREG0H/L to ADRG5H/L) for the normal AD conversion (ADREG0H/L to ADREG5H/L are read-only registers) In the channel-fix repeat conversion mode, AD conversion results are stored into ADREG0H/L to ADREG3H/L one after another. In other modes, the conversion results of channels AN0, AN1, AN2, AN3, AN4, and AN5 are each stored into ADREG0H/L, ADREG1H/L, ADREG2H/L, ADREG3H/L, ADREG4H/L, and ADREG5H/L. Table 3.24.2 shows the correspondence between analog input channels and AD conversion result registers. Table 3.24.2 Correspondence between analog input channels and AD conversion result registers AD conversion result register Analog input channel (Port D) Other conversion modes than shown in the right AN0 ADREG0H/L AN1 ADREG1H/L AN2 ADREG2H/L AN3 ADREG3H/L AN4 ADREG4H/L AN5 ADREG5H/L Channel-fix repeat conversion mode (per 4 times) ADREG0H/L ADREG1H/L ADREG2H/L ADREG3H/L Note: In order to detect overruns without omission, read the conversion result storage register's higher-order bits first, and then read the lower-order bits next. As this result, receiving the result of OVRn = 0 and ADRnRF = 1 for overruns existing in the lower-order bits means that a correct conversion result has been obtained. 3.24.2.9 Data Polling To process AD conversion results by using data polling without using interrupts, perform a polling on ADMOD0<EOCFN>. After confirming that ADMOD0<EOCFN> is set to 1, read the AD conversion storage register. TMPA910CRA- 829 2010-06-02 TMPA910CRA 3.25 Watchdog Timer (WDT) (Runaway Detection Timer) The TMPA910CRA contains a watchdog timer (WDT) for runaway detection. The watchdog timer is provided for detecting a CPU malfunction (runaway) due to causes such as noise and for restoring the CPU to a normal state. When the watchdog timer detects a runaway condition, it generates an interrupt to notify the interrupt controller and CPU of this condition. (Interrupt source signal to Interrupt controller: INTS [0]) By connecting the watchdog timer output to the internal reset pin, a reset can be forcefully generated. Note: Stop WDT during a debugging, 3.25.1 Block diagram WDT reset System reset WDT INTS [0] Interrupt controller APB Bus WDT PCLK <RAWWDTINT> <WDTCNT [31:0]> WDT counter <WDTINT> INTS [0] <INTEN> APB Bus Control register <WDTINTCLR> <RESEN> TMPA910CRA- 830 WDT reset 2010-06-02 TMPA910CRA 3.25.2 Register Functions The following lists the SFRs: Base address = 0xF001_0000 Register Address Name (base +) Description WdogLoad 0x0000 Watchdog load register WdogValue 0x0004 The current value for the watchdog counter WdogControl 0x0008 Watchdog control register WdogIntClr 0x000C Clears the watchdog interrupt WdogRIS 0x0010 Watchdog raw interrupt status WdogMIS 0x0014 Watchdog masked interrupt status WdogLock 0x0C00 Watchdog Lock register TMPA910CRA- 831 2010-06-02 TMPA910CRA 1. WdogLoad (Watchdog load register) Address = (0xF001_0000) + (0x0000) Bit Bit [31:0] Type Symbol WDTCNT R/W Reset Description Value 0xFFFFFFFF WDT counter setting value 0x00000001 to 0xFFFFFFFF [Description] a. <WDTCNT> Specifies the value to be set to the WDT 32 bit counter (The clock of WDT counter is PCLK). After WdogControl <INTEN> is enabled, the value set in WdogLoad<WDTCNT> is loaded into the internal decrement counter. The value of counter can be set from 0x00000001 to 0xFFFFFFFF. (0 can't be set) When reading this register, the setting value is read out. 2. WdogValue (The current value for the watchdog counter) Address = (0xF001_0000) + (0x0004) Bit Bit [31:0] Type Symbol CWDTCNT RO Reset Description Value 0xFFFFFFFF Current value of the WDT counter [Description] a. <CWDTCNT> This bit can be read the current value of watch dog counter. TMPA910CRA- 832 2010-06-02 TMPA910CRA 3. WdogControl (Watchdog control register) Address = (0xF001_0000) + (0x0008) Bit Bit Reset Type Symbol Description Value [31:2] - - Undefined Read as undefined. Write as zero. [1] RESEN R/W 0y0 WDT reset output enable 0y0: Disable 0y1: Enable [0] INTEN R/W WDT counter and interrupt enable 0y0 0y0: Disable 0y1: Enable [Description] a. <RESEN> Controls the WDT reset output. Time until releasing reset is after PCLK 5 counts. b. <INTEN> 0y1: Enables the WDT counter and the WDT interrupt. When this bit is set to 1, the value set in the WdogLoad register is loaded into the WDT counter and the counter starts decrementing. 4. WdogIntClr (Clears the watchdog interrupt) Address = (0xF001_0000) + (0x000C) Bit Bit [31:0] Symbol WDTINTCLR Type WO Reset Value Undefined Description WDT interrupt clear (Writing any value clears the interrupt.) [Description] a. <WDTINTCLR> Writing any value to this register clears the WDT interrupt and loads the value set in the WdogLoad register into the WDT counter. TMPA910CRA- 833 2010-06-02 TMPA910CRA 5. WdogRIS (Watchdog raw interrupt status) Address = (0xF001_0000) + (0x0010) Bit Bit Reset Type Symbol Value Description [31:1] - - Undefined Read as undefined. [0] RAWWDTINT RO 0y0 WDT interrupt raw status 0y0: No interrupt 0y1: Interrupt requested [Description] a. <RAWWDTINT> Indicates the raw status of the WDT interrupt. The <RAWWDTINT> value is ANDed with the interrupt enable signal (WdogControl<INTEN>) to generate an interrupt (WdogMIS<WDTINT>). 6. WdogMIS (Watchdog masked interrupt status) Address = (0xF001_0000) + (0x0014) Bit Bit Reset Type Symbol Value Description [31:1] - - Undefined Read as undefined. [0] WDTINT RO 0y0 WDT interrupt enabled status 0y0: No interrupt 0y1: Interrupt requested [Description] a. <WDTINT> This bit is status bit of the interrupt from WDT counter. The AND value of WdogRIS <RAWWDTINT> and WdogControl <INTEN> is read. TMPA910CRA- 834 2010-06-02 TMPA910CRA 7. WdogLock (Watchdog Lock register) Address = (0xF001_0000) + (0x0C00) Bit Bit [31:0] Symbol REGWEN Reset Type WO Description Value undefined Enables/disables writes to other WDT registers. 0x1ACCE551: Enable Others: Disable (Initial value: Enable) Address = (0xF001_0000) + (0x0C00) Bit Bit Reset Type Symbol Value [31:1] Reserved - undefined [0] REGWENST RO 0y0 Description Read as undefined. Indicates the enabled/disabled status of writes to other WDT registers. 0y0: Enabled (Not locked) 0y1: Disabled (Locked) [Description] a. <REGWEN> Disables writes to other WDT registers to prevent the WDT registers from being inadvertently rewritten by runaway of program, etc. Write except 0x1ACCE551: Disabled writes to WDT register except this register. Write 0x1ACCE551: Enabled writes to WDT register except this register. b. <REGWENST> Indicates the enabled/disabled (not locked/locked) status of writes to other WDT registers. TMPA910CRA- 835 2010-06-02 TMPA910CRA 3.26 PMC (Power Management Circuit) This product contains a power management circuit that manages standby currents against current leaks from microprocessing products. The following ten systems of power supply are conceivable: * 3.3-V power supply for A/D converters (for A/D converters: AVCC3AD & AVSS3AD) * 3.3-V digital power supply (for general pins: DVCC3IO & DVSSCOM) * 3.3-V and 1.8-V power supplies for memory (for memory control: DVCCM & DVSSCOM) * 3.3-V and 1.8-V power supplies for CMOS cameras: (for CMOS camera control: DVCC3CMS & DVSSCOM) * 3.3-V and 1.8-V power supplies for LCDD (for LCDD control: DVCC3LCD & DVSSCOM) * 3.3-V and 1.8-V power supplies for I2S (for I2S control: DVCC3I2S & DVSSCOM) * 3.3-V power supply for USB (for USB control: AVDD3T/C & AVSS3T/C) * 1.5-V-A internal power supply (for general circuits: DVCC1A & DVSSCOM) * 1.5-V-B internal power supply (for RTC and PMC: DVCC1B & DVSSCOM) * 1.5-V-C power supply for oscillators (for high frequency oscillators and PLL: DVCC1C & DVSS1C) Each power supply is independent. (VSS is partially common.) In the power-cut mode, power supplies to most part of the internal circuits are cut off externally to reduce the leak current in a standby state. At this time, the state of each external pin can be fixed as "H output", "L output", "High-Z" or "input". (See the backup register output data register list later in this section). Of the ten power supplies, those that should be supplied in the PCM state are DVCC3IO, DVCCM, DVCC3CMS, DVCC3LCD, DVCC3I2S, AVCC3AD, and DVCC1B. The power supplies that should be cut off are DVCC1A, DVCC1C and AVDD3T/AVDD3C. Even if these power supplies are cut off after the TMPA910CRA enters the PCM state, no flow-through current will be generated in the TMPA910CRA. Reset On Reset (fOSCH/1) Release of reset Request for release Command Interrupt HALT state (CPU stops.) Command Interrupt PLL-OFF state (fOSCH/gear value) Command PLL-OFF state ((6 or 8)xfOSCH/ gear value) Command PCM state (Part of power supplies are ON) PCM(Power Cut Mode) Figure 3.26.1 State Transition Diagram of TMPA910CRA TMPA910CRA- 836 2010-06-02 TMPA910CRA INT, Port, ... others DVCC3IO DVCCM DVCC3I2S DVCC3CMS DVCC3LCD I/O PAD AVCC3AD XT1 Low- XT2 OSC ADC AN0-AN5 X1 X2 HighCPU, Other logic OSC AVCC3T & RAM 56kB DVCC1C AVCC3C USB DVCC1B D+ D- PMC RTC DVCC1A DVSS1C DVSSCOM AVSS3AD AVSS3T/C Figure 3.26.2 Power Supply System TMPA910CRA- 837 2010-06-02 TMPA910CRA 3.26.1 Example of Connection and System Application Regulator Regulator 1.5V 3.3V SW en Delay Circuit SW en SW en SW en 0 S 1 AVDD3T/C AVCC3 DVCC1C DVCC1A DVCC1B I/O power supply (5 types) Power On Reset Circuit TMPA910CRA RESETn USB ADC CPU Other Logic High_OSC AVSS3T/C AVSS3AD DVSS1C RTC PMC DVSSCOM XT1 Power supply management signal I/O XT2 PWE External interrupt INT0-7 (TSI is also supported.) INTKEY Main Power Figure 3.26.3 Power Supply System Figure 3.26.3 shows an example of the external circuit using this system. The power management pin (PWE) controls the power cutoff circuit or power circuit of pins. This circuit outputs "H" in normal status including system reset status, supplying power to all blocks. The circuit outputs "L" in power-cut mode, cutting off the power to most part of the internal circuits including CPU, high-frequency oscillators and power supply of USB to reduce consumption currents. The power-cut mode is released by a Wakeup request. Then, the PWE pin outputs "H" again and supplies power to the internal circuits. TMPA910CRA- 838 2010-06-02 TMPA910CRA 3.26.2 Description of Operation The following shows a flowchart for entering and exiting the PCM state. Execute the program in internal RAM Clear PCM release request Remove impediments to transit to PCM Enter PCM Set the backup registers in the PMC as required Wait NOP = 20? NO YES Stop internal cache PCM Select a wakeup trigger NO Wakeup requested? YES Set warm-up time Release PCM state Select BOOT mode and multi mode Stop PLL operation Resume normal operation Figure 3.26.4 Flowchart for Entering and Exiting the PCM state TMPA910CRA- 839 2010-06-02 TMPA910CRA 3.26.2.1 Entering the PCM state In the PCM state, power supplies to the internal circuits including the CPU are cut off. To enter the PCM state, the following procedure must be observed to prepare for operation after exiting the power-cut mode, to define the external pin states during the PCM state and to ensure proper mode transition. 1. Execution procedure (1) Program execution area For entering the PCM state, the program must be executing in the internal RAM. (2) Remove possible impediments to transition to the PCM mode Before entering the PCM mode, stop all functions that may interfere with the mode transition operation. a. Disable interrupts b. Stop the watchdog timer (The watchdog timer is initially stopped.) c. Stop the AD converter. d. Stop DMA operation * Stop the LCD controller. * Disable the SDRAM auto refresh function (so that the self refresh mode is enabled.) * Stop DMA transfer. (3) Set the pin states Set the backup registers to fix the state of each pin during the PCM state. In the PCM state, the port states are controlled by the backup registers in the PMC. PC2 should be set as the PWE pin. Only the CKE pin (which is controlled by SDRAM) allows the pin state on exiting the PCM state to be different from the pin state after system reset. For details, refer to 3.26.2.3. (4) Set the wakeup conditions Set the external pin for waking up from the PCM state. The enable register, edge selection register and wakeup interrupt flag register are provided for each external pin. The internal RTC, an external key or an external interrupt can be selected as a wakeup trigger. (Interrupts not used can be masked.) To use PD6 as the TSI interrupt pin (INTA), the debounce circuit must be disabled. For details, refer to the chapter on the TSI. TMPA910CRA- 840 2010-06-02 TMPA910CRA (5) Stop PLL operation. Stop the PLL circuit operation by setting high frequency clock to fOSCH. (6) Set the warm-up time: PMCCTL<WUTM1:0> The status of the external PWE signal changes from 0 to 1 2.5 XT1 (77 s) after the wakeup interrupt. Then, the period set by the warm-up timer is counted up, and after another approximately 3 XT1 (92s), the internal reset is released. Since power stabilization time depends on the response of the power source to be used and conditions on the set, determine the warm-up time in consideration of the period required until power is stabilized. (The warm-up time can be selected in the range between 15.625 ms and 125 ms.) (7) Disable the internal cache memory. (8) Clear the releasing request in PMC Before transition to PCM status, the PCM releasing request must be clear. (9) Move to the PCM status (PMCCTL<PCM_ON> = 1). Note: Register PMCCTL <PMCPWE>, <WMTM1>, and <WMTM0> those bits can't be changed at the same time of setting PMCCTL<PCM_ON> from 0 to 1 (becasuse setting PMCCTL<PCM_ON> from 0 to 1, enter PCM mode, internal circuit is stopped, and PMCCTL <PMCPWE>, <WMTM1>, and <WMTM0> those bits can't be updated). Register PMCCTL <PMCPWE>, <WMTM1>, and <WMTM0> should be changed at <PCM_ON> = 0 status. And when configure <PCM_ON> = 1, PMCCTL <PMCPWE>, <WMTM1>, and <WMTM0> those bits must be same setting value as the pre-setting value. (10)Insert dummy statements to fill the waiting time before transit to the PCM state. (Use of 20 NOP statements is recommended.) Note: Programs to be started after Warm-up Either the built-in BOOT_ROM or external memory (SMCCS0n) is selected and the program is started according to the settings of the external AM0/1 pins after Wakeup as in the case system reset is asserted. Whether system reset starting or Wakeup from the PCM state occurred can be known by checking the flag of PMCCTL<PMC_ON> in the PMC circuit in the initial routine of the starting program. * Wakeup from the PCM state: PMCCTL<PMC_ON> = 1 * System reset starting: PMCCTL<PMC_ON> = 0 The flag should be checked previously in the starting program to prepare a program branch mechanism. TMPA910CRA- 841 2010-06-02 TMPA910CRA 3.26.2.2 Wakeup from PCM status Wakeup from the PCM status is made by external interrupts or resetting. Whether system reset starting or Wakeup from the PCM status occurred can be known by checking the flag of PMCCTL<PMC_ON> in the PMC circuit in the initial routine of the starting program. Following wakeup from the PCM status, either the built-in BOOT_ROM or external memory (SMCCS0n) is selected and the program is started according to the settings of the external AM0/1 pins. (Recovery by resetting with DVCC1A cut off is inhibited. Resetting should be done after power is supplied to DVCC1A and the power is sufficiently stabilized.) Target interrupts include RTC interrupts, INT0 to INT7, INTA (TSI interrupts), and KI0 to KI7 interrupts. For details, refer to the later section "PCM Status Release Pins". The PWE pin is set to from 0 to 1 on receipt of Wakeup request, so that each power is supplied to each block in the power cut off condition. After the warm-up operation that time is set by PMCCTL<WUTM1:0>, HOT_RESET is automatically released. The status of the external pins is held as set in the PMC circuit in the PCM status. However, these pins except the DMCCKE pin (Note) assume the status similar to external system reset almost simultaneously with release of internal HOT_RESET. Whether system reset starting or wakeup from the PCM status occurred can be known by checking the <PMC_ON> in the PMC circuit in the initial routine of the start program. The PMCCTL<PCM_ON> in the PMC circuit is not initialized with wakeup from the PCM status. After wakeup, initialize PMCCTL<PCM_ON> (write 0 to it). The PMC circuit is provided with flag to check (BxxRINT) for checking the cause of wakeup of the PCM status. This flag tells the factor that caused wakeup of the PCM status. Note: The DMCCKE pin is started "H" status always. Therefore, if SDRAM is set to Self-refresh status before status transition to PCM status, Self-refresh state is released if DMCCKE pin is set to "H" state by releaseing PCM state. SDRAM Only the DMCCKE pin for SDRAM control can change its status after system resetting and that on release of the PCM status. Set the pin status in the register in the PMC circuit. DMCCKE pin status After system reset "H" status After releasing PCM status If set to "L" status; DMCCKECTL<DMCCKEHLD> = 1 BSJOE<BSJOE6> = 1 BSJDATA<BSJDATA6> = 0 TMPA910CRA- 842 2010-06-02 TMPA910CRA 3.26.2.3 Status Transition to PCM status to its Wakeup Status Transition to PCM status to its Wakeup Transition under Release under way PCM status way Power Cut Normal status DVCC1A Power ON Power OFF Power ON Power ON CPURAM, etc RESET Stop RESETRestart Operating DVCC1B Power ON Power ON Power ON Power ON PMC circuit Operating Operating Operating Operating RTC circuit Operating Operating Operating Operating DVCC1C Power ON Power OFF Power ON Power ON High-frequency oscillator Operating Stop Restart Operating DVCC3IO Power ON Power ON Power ON Power ON PWE pin "H" Output "L" Output "LH" Output "H" Output Low-frequency oscillator Operating Operating Operating Operating Operating Operating Operating Operating JTAG pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating NANDF pin Pin fixed (Special function) Pin fixed (PMC) RESETRestart Operating KEYOUT pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating KEYIN pin Input pin Input pin Input pin Input pin I C0 pin 2 Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating INT pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating SDCARD pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating Reset, AM pin, etc. Basic pins UART0/1 pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating SPIC0 pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating DVCCM Power ON Power ON Power ON Power ON Pins related to memory control Pin fixed (Exclusive function) Pin fixed (PMC) RESETRestart Operating DMCCKE pin Pin fixed (Exclusive function) Pin fixed (PMC) Pin fixed (PMC) Software processing Operating DVCC3CMS Power ON Power ON Power ON Power ON CMOSIS pin Input pin Input pin Input pin Input pin I C1 pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating DVCC3LCD Power ON Power ON Power ON Power ON LCDC pin Pin fixed (Exclusive function) Pin fixed (PMC) RESETRestart Operating AVCC3AD Power ON Power ON Power ON Power ON AN0-AN3 pin Input pin Input pin Input pin Input pin AN4-AN5 pin Input pin Pull-down (PMC) RESETRestart Operating TSI pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating 2 DVCC3I2S Power ON Power ON Power ON Power ON I S0/1 pin 2 Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating SPI1 pin Pin fixed (Port) Pin fixed (PMC) RESETRestart Operating AVDD3T/C Power ON Power OFF Power ON Power ON USB pin Operating STOP RESETRestart Operating Note 1: PMC cicuit has the confirming flag (BxxRINT) for confirming the factor for Wakeup from PCM status. The factor of PCM release can be confirmed in this flag. TMPA910CRA- 843 2010-06-02 TMPA910CRA Note 2: The PMCCTL<PCM_ON> is held in the 1 state. To set the power-cut mode again, once write 0 and then 1 again. Wait 31 s or more before writing 0 and then 1 again. Note 3: In the above table of Status Transition, "Pin fixed (PMC) " is that the external pins are fixed as the backup registers state of PMC even if the internal circuit power is cut. But some pins (PC2, SJ6) are special. Show in the below chart. TMPA910CRAXBG GPIOCFR1 GPIOCFR2 (not use) DVCC1A and others power PMC circuit DVCC1B PCDATA Initial value /PCM t Selector NC NC PWE GPO Selector PC2 Initial value PMCCTL<PMCPWE> PWE (internal signal) BSJDATA Selector DMCCKE SJ6 DMCCKE Except the initial value /PCM DMCCKECTL<DMCCKEHLD> BSxDATA Exclusive pins PCM state Selector Pins of Sx Except the initial value /PCM PCM sate (Internal signal) The initial value /PCM A BPxDATA PCM state Selector Pins of Px Selector B C D Except the initial value /PCM PCM state (Internal signal) GPIOxFR1 GPIOxFR2 TMPA910CRA- 844 2010-06-02 TMPA910CRA 3.26.3 Notes on Operation * Power ON/OFF sequence (initial power ON/complete power OFF) For the initial power ON, the internal power should be supplied first, and for the complete power OFF, the internal power should be cut off last. Power ON 1.5-V internal power supply Power OFF PCM status DVCC1A DVCC1B DVCC1C The 3.3-V power should rise after the 1.5-V power rises. External pin power supply Power should rise within 100 ms. Power should fall within 100 ms. The 1.5-V power should fall after the 3.3-V power falls. DVCC3IO DVCCM DVCC3CMS DVCC3LCD DVCC3I2S USB power supply AVDD3T/Sx AVCC3AD High-frequency oscillator stabilize time + 20 system clocks RESETn PWE pin Note 1: Simultaneous rising and falling of the internal 1.5-V power and the external pin power is possible. However, the external pins may become unstable momentarily at that time. Therefore, rising and falling of the external power should be made while the internal 1.5-V power is stable as shown by the thick line in the above figure if the devices connecting to the LSIs in the surrounding parts can be affected. Note 2: Do not allow the 3.3-V power to rise earlier than the 1.5-V power. In the same way, do not allow the 3.3-V power to fall after the 1.5-V power. TMPA910CRA- 845 2010-06-02 TMPA910CRA 3.26.4 PCM Status Release Pins The power-cut mode is reset on interrupt request. The table below shows the external pins for which the power-cut mode can be released. Note: When the pins in the table are not used, the power-cut mode can also be released on interrupt from the built-in RTC. Bit7 Bit6 Bit5 Bit4 SA Bit3 Bit2 Bit1 Bit0 A[25] A[24] D[7:0] SB D[15:8] SC D[23:16] SD D[31:24] SE A[7:0] SF A[15:8] SG A[23:16] SH DMCCSn SMCCS3n SMCCS2n SMCCS1n SMCCS0n SMCBE0n SJ SMCAVDn DMCCKE DMCBA1 DMCBA0 DMCCASn DMCRASn DMCWEn SMCOEn DMCSDQM0 DMCDDM0 SK SMCBE3n SMCBE2n SMCBE1n SMCWEn DMCSDQM3 DMCSDQM2 DMCSDQM1 DMCDDM1 SL SMCWAITn DMCCLKIN DMCDDQS1 DMCDDQS0 SMCCLK DMCAP DMCDCLKN SM AM1 AM0 TEST0n RESETn XT2 SN SP TDO SR DMCDCLKP DMCSCLK XT1 X2 X1 SELJTAG SELDVCCM SELMEMC TMS TCK RTCK TRSTn TDI VSENS REXT UMON DM DP ST LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 SU LPRG2 LPRG1 LPRG0 LCLLP LCLFP LCLLE LCLAC LCLCP SV NDD7 SW NDD6 NDD5 NDD4 NDD3 NDD2 NDD1 NDD0 NDRB NDCE1n NDCE0n NDCLE NDALE NDWEn NDREn Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 PA KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 PB KO7 KO6 KO5 KO4 KO3 KO2 KO1 KO0 PWE KO9 KO8 AN3 AN2 AN1 AN0 CMSD3 CMSD2 CMSD1 CMSD0 CMSVSY CMSHBK CMSHSY CMSPCK PC PD PE PF I2C0DA INT9 I2C0CL MLDALMn FSOUT MLDALM INT8 PWM2OUT PWM0OUT PY PX AN5 AN4 INTB INTA(TSI) MY MX CMSD7 CMSD6 CMSD5 CMSD4 I2C1DA INTC I2C1CL PG SDC0CLK SDC0CD SDC0WP SDC0CMD SDC0DAT3 SDC0DAT2 SDC0DAT1 SDC0DAT0 PH SDC1CLK SDC1CD SDC1WP SDC1CMD SDC1DAT3 SDC1DAT2 SDC1DAT1 SDC1DAT0 PJ LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 PK LD23 LD22 LD21 LD20 LD19 LD18 LD17 LD16 I2S0MCLK I2S0DATI I2S0CLK I2S0WS SP1DI SP1DO SP1CLK SP1FSS I2S1MCLK I2S1DATO I2S1CLK I2S1WS PL I2SSCLK PM PN PP U0RTSn U0DTRn U0RIn U0DSRn INTG INTF INTE INTD INT7 INT6 INT5 INT4 X1USB U1CTSn U1RXD U1TXD U0TXD SIR0IN SIR0OUT U0DCDn U0CTSn INT3 INT2 INT1 INT0 INTH SMCWPn, FCOUT RESETOUTn SP0DO SP0CLK SP0FSS PR PT U0RXD SP0DI TMPA910CRA- 846 2010-06-02 TMPA910CRA 3.26.5 Description of Registers The following lists the SFRs: Base address = 0xF002_0000 Register Address Name (base +) Description BPADATA 0x0000 PortA Data Set Register when Power Cut Mode BPBDATA 0x0004 PortB Data Set Register when Power Cut Mode BPCDATA 0x0008 PortC Data Set Register when Power Cut Mode BPDDATA 0x000C PortD Data Set Register when Power Cut Mode - 0x0010 Reserved BPFDATA 0x0014 PortF Data Set Register when Power Cut Mode BPGDATA 0x0018 PortG Data Set Register when Power Cut Mode BPHDATA 0x001C PortH Data Set Register when Power Cut Mode BPJDATA 0x0024 PortJ Data Set Register when Power Cut Mode BPKDATA 0x0028 PortK Data Set Register when Power Cut Mode BPLDATA 0x002C PortL Data Set Register when Power Cut Mode BPMDATA 0x0030 PortM Data Set Register when Power Cut Mode BPNDATA 0x0034 PortN Data Set Register when Power Cut Mode BPPDATA 0x003C PortP Data Set Register when Power Cut Mode BPRDATA 0x0044 PortR Data Set Register when Power Cut Mode BPTDATA 0x004C PortT Data Set Register when Power Cut Mode - 0x0080 Reserved BPBOE 0x0084 PortB Data Out Enable Control when Power Cut Mode BPCOE 0x0088 PortC Data Out Enable Control when Power Cut Mode BPDOE 0x008C PortD Data Out Enable Control when Power Cut Mode BPEOE 0x0090 PortE Data Out Enable Control when Power Cut Mode BPFOE 0x0094 PortF Data Out Enable Control when Power Cut Mode BPGOE 0x0098 PortG Data Out Enable Control when Power Cut Mode BPHOE 0x009C PortH Data Out Enable Control when Power Cut Mode BPJOE 0x00A4 PortJ Data Out Enable Control when Power Cut Mode BPKOE 0x00A8 PortK Data Out Enable Control when Power Cut Mode BPLOE 0x00AC PortL Data Out Enable Control when Power Cut Mode BPMOE 0x00B0 PortM Data Out Enable Control when Power Cut Mode BPNOE 0x00B4 PortN Data Out Enable Control when Power Cut Mode BPPOE 0x00BC PortP Data Out Enable Control when Power Cut Mode BPROE 0x00C4 PortR Data Out Enable Control when Power Cut Mode BPTOE 0x00CC PortT Data Out Enable Control when Power Cut Mode TMPA910CRA- 847 2010-06-02 TMPA910CRA Base address = 0xF002_0000 Register Address Name (base+) Description BSADATA 0x0100 BSBDATA 0x0104 SA Data Set Register when Power Cut Mode SB Data Set Register when Power Cut Mode BSCDATA 0x0108 SC Data Set Register when Power Cut Mode BSDDATA 0x010C SD Data Set Register when Power Cut Mode BSEDATA 0x0110 SE Data Set Register when Power Cut Mode BSFDATA 0x0114 SF Data Set Register when Power Cut Mode BSGDATA 0x0118 SG Data Set Register when Power Cut Mode BSHDATA 0x011C SH Data Set Register when Power Cut Mode BSJDATA 0x0124 SJ Data Set Register when Power Cut Mode BSKDATA 0x0128 SK Data Set Register when Power Cut Mode BSLDATA 0x012C SL Data Set Register when Power Cut Mode BSMDATA 0x0130 SM Data Set Register when Power Cut Mode - 0x013C Reserved - 0x0144 Reserved BSTDATA 0x014C ST Data Set Register when Power Cut Mode BSUDATA 0x0150 SU Data Set Register when Power Cut Mode BSVDATA 0x0154 SV Data Set Register when Power Cut Mode BSWDATA 0x0158 SW Data Set Register when Power Cut Mode BSAOE 0x0180 SA Data Out Enable Control when Power Cut Mode BSBOE 0x0184 SB Data Out Enable Control when Power Cut Mode BSCOE 0x0188 SC Data Out Enable Control when Power Cut Mode BSDOE 0x018C SD Data Out Enable Control when Power Cut Mode BSEOE 0x0190 SE Data Out Enable Control when Power Cut Mode BSFOE 0x0194 SF Data Out Enable Control when Power Cut Mode BSGOE 0x0198 SG Data Out Enable Control when Power Cut Mode BSHOE 0x019C SH Data Out Enable Control when Power Cut Mode BSJOE 0x01A4 SJ Data Out Enable Control when Power Cut Mode BSKOE 0x01A8 SK Data Out Enable Control when Power Cut Mode BSLOE 0x01AC SL Data Out Enable Control when Power Cut Mode BSMOE 0x01B0 SM Data Out Enable Control when Power Cut Mode - 0x01BC Reserved - 0x01C4 Reserved BSTOE 0x01CC ST Data Out Enable Control when Power Cut Mode BSUOE 0x01D0 SU Data Out Enable Control when Power Cut Mode BSVOE 0x01D4 SV Data Out Enable Control when Power Cut Mode BSWOE 0x01D8 SW Data Out Enable Control when Power Cut Mode TMPA910CRA- 848 2010-06-02 TMPA910CRA Base address = 0xF002_0000 Register Address Name (base+) Description BPARELE 0x0200 PortA Enable Register of Wakeup trigger from Power Cut Mode BPDRELE 0x0204 PortD Enable Register of Wakeup trigger from Power Cut Mode BPPRELE 0x0208 PortP Enable Register of Wakeup trigger from Power Cut Mode - 0x020C Reserved BRTRELE 0x0210 RTC Request Enable Register of Wakeup trigger from Power Cut Mode BPAEDGE 0x0220 PortA Selection of Wakeup trigger Edge from Power Cut Mode BPDEDGE 0x0224 PortD Selection of Wakeup trigger Edge from Power Cut Mode BPPEDGE 0x0228 PortP Selection of Wakeup trigger Edge from Power Cut Mode - 0x022C Reserved BPARINT 0x0240 PortA Wakeup Flag from Power Cut Mode BPDRINT 0x0244 PortD Wakeup Flag from Power Cut Mode BPPRINT 0x0248 PortP Wakeup Flag from Power Cut Mode - 0x024C Reserved BRTRINT 0x0250 RTC Wakeup Flag from Power Cut Mode : : : PMCDRV 0x0260 External Port Driverbility control : : : DMCCKECTL 0x0280 DMCCKE control register PMCCTL 0x0300 Power Management Circuit Control Register - 0x0320 Reserved - 0x0400 Reserved TMPA910CRA- 849 2010-06-02 TMPA910CRA 1. backup register output data register list 1 register correspond register Address to port name 0xF002_0000 PA 0xF002_0004 PB 0xF002_0008 type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit W BPADATA7 BPADATA6 BPADATA5 BPADATA4 BPADATA3 BPADATA2 BPADATA1 BPADATA0 BPBDATA W BPBDATA7 BPBDATA6 BPBDATA5 BPBDATA4 BPBDATA3 BPBDATA2 BPBDATA1 BPBDATA0 PC BPCDATA W BPCDATA7 BPCDATA6 BPCDATA5 BPCDATA4 BPCDATA3 - BPCDATA1 BPCDATA0 0xF002_000C PD BPDDATA W Note2 BPDDATA6 0xF002_0010 - Reserved - 0xF002_0014 PF BPFDATA W BPFDATA7 BPFDATA6 - - BPADATA Note Read undefined. Write as zero. Read undefined. Write as zero. Read undefined. Write as zero. 0xF002_0018 PG BPGDATA W BPGDATA7 BPGDATA6 BPGDATA5 BPGDATA4 BPGDATA3 BPGDATA2 BPGDATA1 BPGDATA0 0xF002_001C PH BPHDATA W BPHDATA7 BPHDATA6 BPHDATA5 BPHDATA4 BPHDATA3 BPHDATA2 BPHDATA1 BPHDATA0 0xF002_0024 PJ BPJDATA W BPJDATA7 BPJDATA6 BPJDATA5 BPJDATA4 BPJDATA3 BPJDATA2 BPJDATA1 BPJDATA0 0xF002_0028 PK BPKDATA W BPKDATA7 BPKDATA6 BPKDATA5 BPKDATA4 BPKDATA3 BPKDATA2 BPKDATA1 BPKDATA0 0xF002_002C PL BPLDATA W - - - BPLDATA4 BPLDATA3 BPLDATA2 BPLDATA1 BPLDATA0 0xF002_0030 PM BPMDATA W - - - - BPMDATA3 BPMDATA2 BPMDATA1 BPMDATA0 0xF002_0034 PN BPNDATA W BPNDATA7 BPNDATA6 BPNDATA5 BPNDATA4 BPNDATA3 BPNDATA2 BPNDATA1 BPNDATA0 0xF002_003C PP BPPDATA W BPPDATA7 BPPDATA6 BPPDATA5 BPPDATA4 BPPDATA3 BPPDATA2 BPPDATA1 BPPDATA0 0xF002_0044 PR BPRDATA W - - - - - BPRDATA2 BPRDATA1 BPRDATA0 0xF002_004C PT BPTDATA W BPTDATA7 BPTDATA6 BPTDATA5 BPTDATA4 BPTDATA3 BPTDATA2 BPTDATA1 BPTDATA0 These registers defined the output data in PCM state. Reset state is 0. After Hot reset, hold the data (setting value of register). Each bit of register = 0: "L" output Each bit of register = 1: "H" output Note1: In PCM state, BPADATA initial value = 0x00, the PULL-UP circuits of PORT A is OFF. If you want to keep the PULL-UP state of PORT A, set 0xFF to BPADATA before switching to PCM state. Note2: Read undefined. Write as zero. TMPA910CRA- 850 2010-06-02 TMPA910CRA 2. backup register output Enable register list 1 register correspond register Address to port name 0xF002_0080 PA Reserved - type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit Read undefined. Write as zero. 0xF002_0084 PB BPBOE W BPBOE7 BPBOE6 BPBOE5 BPBOE4 BPBOE3 BPBOE2 BPBOE1 BPBOE0 0xF002_0088 PC BPCOE W BPCOE7 BPCOE6 BPCOE5 BPCOE4 BPCOE3 BPCOE2 BPCOE1 BPCOE0 0xF002_008C PD W BPDOE7 BPDOE6 BPDOE5 BPDOE4 BPDOE (Note) Read undefined. Write as zero. 0xF002_0090 - Reserved - 0xF002_0094 PF BPFOE W BPFOE7 BPFOE6 - - 0xF002_0098 PG BPGOE W BPGOE7 BPGOE6 BPGOE5 BPGOE4 BPGOE3 BPGOE2 BPGOE1 BPGOE0 0xF002_009C PH BPHOE W BPHOE7 BPHOE6 BPHOE5 BPHOE4 BPHOE3 BPHOE2 BPHOE1 BPHOE0 0xF002_00A4 PJ BPJOE W BPJOE7 BPJOE6 BPJOE5 BPJOE4 BPJOE3 BPJOE2 BPJOE1 BPJOE0 Read undefined. Write as zero. Read undefined. Write as zero. 0xF002_00A8 PK BPKOE W BPKOE7 BPKOE6 BPKOE5 BPKOE4 BPKOE3 BPKOE2 BPKOE1 BPKOE0 0xF002_00AC PL BPLOE W - - - BPLOE4 BPLOE3 BPLOE2 BPLOE1 BPLOE0 0xF002_00B0 PM BPMOE W - - - - BPMOE3 BPMOE2 BPMOE1 BPMOE0 0xF002_00B4 PN BPNOE W BPNOE7 BPNOE6 BPNOE5 BPNOE4 BPNOE3 BPNOE2 BPNOE1 BPNOE0 BPPOE7 BPPOE6 BPPOE5 BPPOE4 BPPOE3 BPPOE2 BPPOE1 BPPOE0 0xF002_00BC PP BPPOE W 0xF002_00C4 PR BPROE W - - - - - BPROE2 BPROE1 BPROE0 0xF002_00CC PT BPTOE W BPTOE7 BPTOE6 BPTOE5 BPTOE4 BPTOE3 BPTOE2 BPTOE1 BPTOE0 These registers set the output enable in PCM state. Reset state is 0. After Hot reset, hold the data (setting value of register). Each bit of register = 0: Output disable. Each bit of register = 1: Output enable. TMPA910CRA- 851 2010-06-02 TMPA910CRA Note: In Power Cut Mode, BPDOE and BPDDATA setting GPIOD GPIOD AVCC3AD AVCC3AD BPDOE<bit6> BPDOE<bit7> PD6 PD7 BPDDATA<bit6> 50k AVSS3AD Input Enable Input Enable GPIOD GPIOD AIN5 PD5 AIN4 PD4 BPDOE<bit5> AVSS3AD BPDOE<bit4> AVSS3AD Input Enable TMPA910CRA- 852 Input Enable 2010-06-02 TMPA910CRA 3. backup register output data register list 2 register correspond register Address to port name 0xF002_0100 SA 0xF002_0104 SB type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit BSADATA W BSADATA7 BSADATA6 BSADATA5 BSADATA4 BSADATA3 BSADATA2 BSADATA1 BSADATA0 BSBDATA W BSBDATA7 BSBDATA6 BSBDATA5 BSBDATA4 BSBDATA3 BSBDATA2 BSBDATA1 BSBDATA0 0xF002_0108 SC BSCDATA W BSCDATA7 BSCDATA6 BSCDATA5 BSCDATA4 BSCDATA3 BSCDATA2 BSCDATA1 BSCDATA0 0xF002_010C SD BSDDATA W BSDDATA7 BSDDATA6 BSDDATA5 BSDDATA4 BSDDATA3 BSDDATA2 BSDDATA1 BSDDATA0 0xF002_0110 SE BSEDATA W BSEDATA7 BSEDATA6 BSEDATA5 BSEDATA4 BSEDATA3 BSEDATA2 BSEDATA1 BSEDATA0 0xF002_0114 SF BSFDATA W BSFDATA7 BSFDATA6 BSFDATA5 BSFDATA4 BSFDATA3 BSFDATA2 BSFDATA1 BSFDATA0 0xF002_0118 SG BSGDATA W BSGDATA7 BSGDATA6 BSGDATA5 BSGDATA4 BSGDATA3 BSGDATA2 BSGDATA1 BSGDATA0 0xF002_011C SH BSHDATA W BSHDATA7 BSHDATA6 BSHDATA5 BSHDATA4 BSHDATA3 BSHDATA2 BSHDATA1 BSHDATA0 0xF002_0124 SJ BSJDATA W BSJDATA7 BSJDATA6 BSJDATA5 BSJDATA4 BSJDATA3 BSJDATA2 BSJDATA1 BSJDATA0 0xF002_0128 SK BSKDATA W BSKDATA7 BSKDATA6 BSKDATA5 BSKDATA4 BSKDATA3 BSKDATA2 BSKDATA1 BSKDATA0 0xF002_012C SL BSLDATA W BSLDATA5 BSLDATA4 BSLDATA3 BSLDATA2 BSLDATA1 BSLDATA0 Note 0xF002_014C ST BSTDATA W BSTDATA7 BSTDATA6 BSTDATA5 BSTDATA4 BSTDATA3 BSTDATA2 BSTDATA1 BSTDATA0 0xF002_0150 SU BSUDATA W BSUDATA7 BSUDATA6 BSUDATA5 BSUDATA4 BSUDATA3 BSUDATA2 BSUDATA1 BSUDATA0 0xF002_0154 SV BSVDATA W BSVDATA7 BSVDATA6 BSVDATA5 BSVDATA4 BSVDATA3 BSVDATA2 BSVDATA1 BSVDATA0 0xF002_0158 SW BSWDATA W - Note BSWDATA5 BSWDATA4 BSWDATA3 BSWDATA2 BSWDATA1 BSWDATA0 These registers defined the output data in PCM state. Reset state is 0. After Hot reset, hold the data (setting value of register). Each bit of register = 0: "L" output Each bit of register = 1: "H" output Note: Read undefined. Write as zero. TMPA910CRA- 853 2010-06-02 TMPA910CRA 4. backup register output Enable register list 2 register correspond register Address to port name 0xF002_0180 SA type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit BSAOE W BSAOE7 BSAOE6 BSAOE5 BSAOE4 BSAOE3 BSAOE2 BSAOE1 BSAOE0 0xF002_0184 SB BSBOE W BSBOE7 BSBOE6 BSBOE5 BSBOE4 BSBOE3 BSBOE2 BSBOE1 BSBOE0 0xF002_0188 SC BSCOE W BSCOE7 BSCOE6 BSCOE5 BSCOE4 BSCOE3 BSCOE2 BSCOE1 BSCOE0 0xF002_018C SD BSDOE W BSDOE7 BSDOE6 BSDOE5 BSDOE4 BSDOE3 BSDOE2 BSDOE1 BSDOE0 0xF002_0190 SE BSEOE W BSEOE7 BSEOE6 BSEOE5 BSEOE4 BSEOE3 BSEOE2 BSEOE1 BSEOE0 0xF002_0194 SF BSFOE W BSFOE7 BSFOE6 BSFOE5 BSFOE4 BSFOE3 BSFOE2 BSFOE1 BSFOE0 0xF002_0198 SG BSGOE W BSGOE7 BSGOE6 BSGOE5 BSGOE4 BSGOE3 BSGOE2 BSGOE1 BSGOE0 0xF002_019C SH BSHOE W BSHOE7 BSHOE6 BSHOE5 BSHOE4 BSHOE3 BSHOE2 BSHOE1 BSHOE0 0xF002_01A4 SJ BSJOE W BSJOE7 BSJOE6 BSJOE5 BSJOE4 BSJOE3 BSJOE2 BSJOE1 BSJOE0 0xF002_01A8 SK BSKOE W BSKOE7 BSKOE6 BSKOE5 BSKOE4 BSKOE3 BSKOE2 BSKOE1 BSKOE0 BSLOE5 BSLOE4 BSLOE3 BSLOE2 BSLOE1 BSLOE0 BSMOE3 Note BSMOE1 Note 0xF002_01AC SL BSLOE W 0xF002_01B0 SM BSMOE W Note Note 0xF002_01CC ST BSTOE W BSTOE7 BSTOE6 BSTOE5 BSTOE4 BSTOE3 BSTOE2 BSTOE1 BSTOE0 0xF002_01D0 SU BSUOE W BSUOE7 BSUOE6 BSUOE5 BSUOE4 BSUOE3 BSUOE2 BSUOE1 BSUOE0 0xF002_01D4 SV BSVOE W BSVOE7 BSVOE6 BSVOE5 BSVOE4 BSVOE3 BSVOE2 BSVOE1 BSVOE0 0xF002_01D8 SW BSWOE W - Note BSWOE5 BSWOE4 BSWOE3 BSWOE2 BSWOE1 BSWOE0 These registers set the output enable in PCM state. Reset state is 0. After Hot reset, hold the data (setting value of register). Each bit of register = 0: Output disable. Each bit of register = 1: Output enable. Note: Read undefined. Write as zero. TMPA910CRA- 854 2010-06-02 TMPA910CRA 5. BPARELE register Address = (0xF002_0000) + (0x0200) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:8] - - Undefined Undefined Read undefined. Write as zero. [7] BPARELE7 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [6] BPARELE6 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [5] BPARELE5 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [4] BPARELE4 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [3] BPARELE3 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [2] BPARELE2 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [1] BPARELE1 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [0] BPARELE0 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [Description] a. <BPARELE[7:0]> Enable PCM release request of key input KI [7:0]. TMPA910CRA- 855 2010-06-02 TMPA910CRA 6. BPDRELE register Address = (0xF002_0000) + (0x0204) Bit Bit Symbol Type Reset Hot Reset Value Value Undefined Undefined Read undefined. Write as zero. Read undefined. Write as zero. [31:8] - - [7] - - Undefined Undefined [6] BPDRELE6 R/W 0y0 hold eve data Description PCM release request Enable 0y0: disable 0y1: enable [5:0] - - Undefined Undefined Read undefined. Write as zero. [Description] a. <BPDRELE6> Enable PCM release request of INTA (TSI). TMPA910CRA- 856 2010-06-02 TMPA910CRA 7. BPPRELE register Address = (0xF002_0000) + (0x0208) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:8] - - Undefined Undefined Read undefined. Write as zero. [7] BPPRELE7 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [6] BPPRELE6 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [5] BPPRELE5 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [4] BPPRELE4 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [3] BPPRELE3 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [2] BPPRELE2 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [1] BPPRELE1 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [0] BPPRELE0 R/W 0y0 hold eve data PCM release request Enable 0y0: disable 0y1: enable [Description] a. <BPPRELE[7:0]> Enable PCM release request of INT7/INT6/INT5/INT4/INT3/INT2/INT1/INT0. TMPA910CRA- 857 2010-06-02 TMPA910CRA 8. BRTRELE register Address = (0xF002_0000) + (0x0210) Bit Bit Symbol Type Reset Hot Reset Value Value [31:1] - - Undefined Undefined [0] BRTRELE0 R/W 0y0 hold eve data Description Read undefined. Write as zero. PCM release request Enable 0y0: disable 0y1: enable [Description] a. <BRTRELE0> Enable PCM release request of RTC. 9. BPAEDGE register Address = (0xF002_0000) + (0x0220) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:8] - - Undefined Undefined Read undefined. Write as zero. [7] BPAEDGE7 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [6] BPAEDGE6 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [5] BPAEDGE5 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [4] BPAEDGE4 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [3] BPAEDGE3 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [2] BPAEDGE2 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [1] BPAEDGE1 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [0] BPAEDGE0 R/W 0y0 hold eve data edge selection of PCM release request 0y0 : rise edge 0y1 : fall edge [Description] a. <BPAEDGE[7:0]> Edge selection of PCM release request of key input KI [7:0]. TMPA910CRA- 858 2010-06-02 TMPA910CRA 10. BPDEDGE register Address = (0xF002_0000) + (0x0224) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:8] - - Undefined Undefined Read undefined. Write as zero. [7] - - Undefined Undefined Read undefined. Write as zero. [6] BPDEDGE6 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [5:0] - - Undefined Undefined Read undefined. Write as zero. [Description] a. <BPDEDGE6> Edge selection of PCM release request of INTA (TSI). TMPA910CRA- 859 2010-06-02 TMPA910CRA 11. BPPEDGE register Address = (0xF002_0000) + (0x0228) Bit Bit Symbol Type Reset Hot Reset Value Value [31:8] - - Undefined Undefined [7] BPPEDGE7 R/W 0y0 hold eve data Description Read undefined. Write as zero. Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [6] BPPEDGE6 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [5] BPPEDGE5 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [4] BPPEDGE4 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [3] BPPEDGE3 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [2] BPPEDGE2 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [1] BPPEDGE1 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [0] BPPEDGE0 R/W 0y0 hold eve data Edge selection of PCM release request 0y0: rise edge 0y1: fall edge [Description] a. <BPPEDGE[7:0]> Edge selection of PCM release request of INT7/INT6/INT5/INT4/INT3/INT2/INT1/INT0. TMPA910CRA- 860 2010-06-02 TMPA910CRA 12. BPARINT register Address = (0xF002_0000) + (0x0240) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:8] - - Undefined Undefined Read undefined. Write as zero. [7] BPARINT7 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [6] BPARINT6 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [5] BPARINT5 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [4] BPARINT4 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [3] BPARINT3 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [2] BPARINT2 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [1] BPARINT1 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [0] BPARINT0 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [Description] a. <BPARINT[7:0]> PCM release interrupt status of key input KI [7:0]. For the factor of PCM release can be confirmed. Please write this register bit as 0 before entering PCM status. TMPA910CRA- 861 2010-06-02 TMPA910CRA 13. BPDRINT register Address = (0xF002_0000) + (0x0244) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:7] - - Undefined Undefined Read undefined. Write as zero. [6] BPDRINT6 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [5:0] - - Undefined Undefined Read undefined. Write as zero. [Description] a. <BPDRINT6> PCM release interrupt status of INTA (TSI). For the factor of PCM release can be confirmed. Please write this register bit as 0 before entering PCM status. TMPA910CRA- 862 2010-06-02 TMPA910CRA 14. BPPRINT register Address = (0xF002_0000) + (0x0248) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:8] - - Undefined Undefined Read undefined. Write as zero. [7] BPPRINT7 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [6] BPPRINT6 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [5] BPPRINT5 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [4] BPPRINT4 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [3] BPPRINT3 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [2] BPPRINT2 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [1] BPPRINT1 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [0] BPPRINT0 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [Description] a. <BPPRINT[7:0]> PCM release interrupt status of INT7/INT6/INT5/INT4/INT3/INT2/INT1/INT0. For the factor of PCM release can be confirmed. Please write this register bit as 0 before entering PCM status. TMPA910CRA- 863 2010-06-02 TMPA910CRA 15. BRTRINT register Address = (0xF002_0000) + (0x0250) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:1] - - Undefined Undefined Read undefined. Write as zero. [0] BRTRINT0 R/W Undefined hold eve data PCM release interrupt status Read: 0y0: no interrupt request 0y1: interrupt request Write: 0y0: Clear 0y1: Inhibit [Description] a. <BRTRINT0> PCM release interrupt status of RTC. For the factor of PCM release can be confirmed. Please write this register bit as 0 before entering PCM status. TMPA910CRA- 864 2010-06-02 TMPA910CRA 16. PMCDRV register Address = (0xF002_0000) + (0x0260) Bit Bit Symbol Type Reset Hot Reset Value Value [31:7] - - Undefined Undefined [6] DRV_SP0 R/W 0y1 hold eve data Description Read undefined. Write as zero. SSP relation port drive power 0y0: 12 mA (1.8 V to 3.0 V) 0y1: 6 mA (3.0 V to 3.6 V) [5] DRV_I2S R/W 0y1 hold eve data I2S relation port drive power 0y0: 12 mA (1.8 V to 3.0 V) 0y1: 6 mA (3.0 V to 3.6 V) [4] DRV_LCD R/W 0y1 hold eve data LCDC relation port drive power 0y0: 12 mA (1.8 V to 3.0 V) 0y1: 6 mA (3.0 V to 3.6 V) [3:2] - - Undefined Undefined Read undefined. Write as zero. [1] DRV_MEM1 R/W 0y0 hold eve data memory relation port drive power [0] DRV_MEM0 R/W 0y1 hold eve data 0y00: Reserved 0y01: 1/2 (3.3 V 0.3 V) 0y10: Reserved 0y11: 1/1 (1.8 V 0.1 V) [Description] a. < DRV_SP0, DRV_I2S, DRV_LCD, DRV_MEM[1:0]> These bits can change the drive power of relation ports with SSP (PT3, PT2, PT1 and PT0), I2S, LCD and memory. Please set this bit according to the range of the voltage used. TMPA910CRA- 865 2010-06-02 TMPA910CRA 17. DMCCKECTL register Address = (0xF002_0000) + (0x0280) Bit Bit Symbol Type Reset Hot Reset Value Value [31:1] - - Undefined Undefined [0] DMCCKEHLD R/W 0y0 hold eve data Description Read undefined. Write as zero. output selection of SJ6 0y0: DMCCKE 0y1: PMC register setting [Description] a. <DMCCKEHLD > The DMCCKE pin is started "H" status always. Therefore, if SDRAM is set to Self-refresh status before status transition to PCM status, Self-refresh state is released if DMCCKE pin is set to "H" state by releasing PCM state. SDRAM Only the DMCCKE pin for SDRAM control can change its status after system resetting and that on release of the PCM status. Set the pin status in the register in the PMC circuit. DMCCKE pin status After system reset "H" status After releasing PCM status If set to "L" status; DMCCKECTL<DMCCKEHLD> = 1 BSJOE<BSJOE6> = 1 BSJDATA<BSJDATA6> = 0 TMPA910CRA- 866 2010-06-02 TMPA910CRA 18. PMCCTL register Address = (0xF002_0000) + (0x0300) Bit Bit Symbol Type Reset Hot Reset Value Value Description [31:8] - - Undefined Undefined Read undefined. Write as zero. [7] PCM_ON R/W 0y0 hold eve data Power Cut Enable Note1 0y0: Disable 0y1: Enable [6] PMCPWE R/W 0y1 hold eve data output selection of PWE 0y0: Port function (PC2) 0y1: PMC register output (PWE) [5:3] - - Undefined Undefined Read undefined. Write as zero. [2] Reserved - Undefined Undefined Read undefined. Write as zero. [1] WUTM1 R/W 0y0 hold eve data Warm-up timing setting [0] WUTM0 R/W 0y0 hold eve data 0y00: 2 (15.625 ms) 10 0y01: 2 (31.25 ms) 11 0y10: 2 (62.5 ms) 12 0y11: 2 (125 ms) [Description] a. <PCM_ON> The status shift to PCM status by writing <PCM_ON> to 1. Note1: Register PMCCTL <PMCPWE>, <WMTM1>, and <WMTM0> those bits can't be changed at the same time of setting PMCCTL<PCM_ON> from 0 to 1 Register PMCCTL <PMCPWE>, <WMTM1>, and <WMTM0> should be changed at <PCM_ON> = 0 status. And when configure <PCM_ON> = 1 , PMCCTL <PMCPWE>, <WMTM1>, and <WMTM0> those bits must be same setting value as the pre-setting value. Note2: After the wakeup interrupt, the status of the external PWE signal changes from 0 to 1 after 2.5 XT1 (77s). Then, the period set by the warm-up timer is counted up, and after another approximately 3XT1 (92s), the internal reset is released. Since power stabilization time depends on the response of the power source to be used and conditions on the set, determine the warm-up time in consideration of the period required until power is stabilized. TMPA910CRA- 867 2010-06-02 TMPA910CRA 3.26.6 Using example About the following program example, program practice in built-in RAM. As transition to PCM status, stop any factors (include pin setting) that can hamper the status change to the PCM before actual status transition occurs. * Stop the watchdog timer. * Stop the AD converter. * Stop DMA operation of the system. * Stop LCDC. * Disable the auto refresh function of SDRAM (transition to self-refresh mode). * Disable DMA transfer. * Fix pin status The pin status at PCM status also sets to fix the pin status at the same time. Edge selection is possible for the external interrupts that permit wakeup. Configure the edge selection. The debounce circuit must be disabled when PD6 is used as the INTA for TSI interrupts. * Disable interrupts. * Stop PLL operation. * Disable the internal cache memory. TMPA910CRA- 868 2010-06-02 TMPA910CRA ; Example of Wakeup by PA port LDR MOV STR r0, = BPADATA r1,#0x000000FF r1,[r0] ; Enable PULL-UP of PA ; ; LDR MOV STR r0,=BPARELE r1,#0x000000FF r1,[r0] ; ; Wakeup by PA : Enable ; LDR MOV STR r0, = BPDRELE r1,#0x00000000 r1,[r0] ; ; ; Wakeup by PD : Disable LDR MOV STR r0, = BPPRELE r1,#0x00000000 r1,[r0] ; ; Wakeup by PP : Disable ; LDR MOV STR r0, = BRTRELE r1,#0x00000000 r1,[r0] ; ; Wakeup by RTC : Disable ; LDR MOV STR r0, = BPAEDGE r1,#0x00000000 r1,[r0] ; ; PA Wakeup edge : rise edge ; LDR MOV STR r0, = BPDEDGE r1,#0x00000000 r1,[r0] ; ; PD Wakeup edge : rise edge ; LDR MOV STR r0, = BPPEDGE r1,#0x00000000 r1,[r0] ; ; PP Wakeup edge : rise edge ; TMPA910CRA- 869 2010-06-02 TMPA910CRA LDR MOV STR r0, = BPARINT r1,#0x00000000 r1,[r0] ; ; clear the status of PA Wakeup request ; LDR MOV STR r0, = BPDRINT r1,#0x00000000 r1,[r0] ; ;clear the status of PD Wakeup request ; LDR MOV STR r0, = BPPRINT r1,#0x00000000 r1,[r0] ; ;clear the status of PP Wakeup request ; LDR MOV STR r0,= PMCCTL r1,#0x43 r1,[r0] ; PCMCTL PCM MODE ; First configure warm-up time as 25ms MOV STR r1,#0xc3 r1,[r0] ; next configure Power Cut Enable NOP NOP LOOP B ; ; LOOP HALT ; ; TMPA910CRA- 870 2010-06-02 TMPA910CRA 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Symbol Parameter Rating Unit DVCC3IO DVCCM DVCC3CMS -0.3 to 3.8 DVCC3LCD DVCC3I2S DVCC1A Power supply voltage V DVCC1B -0.3 to 2.0 DVCC1C AVCC3AD AVDD3T -0.3 to 3.8 AVDD3C -0.3 to DVCC3IO+0.3 (Note 1) -0.3 to DVCCM+0.3 (Note 2) -0.3 to DVCC3CMS+0.3 (Note 3) VIN -0.3 to DVCC3LCD+0.3 (Note 4) Input voltage -0.3 to DVCC3I2S+0.3 (Note 5) V -0.3 to AVCC3AD+0.3 (Note 6) -0.3 to AVDD3T+0.3 (Note 7) -0.3 to AVDD3C+0.3 (Note 8) IOL Output current (per pin) 5 mA IOH Output current (per pin) -5 mA mA IOL Output current (total) 80 IOH Output current (total) -80 mA Power consumption (Ta = 70C) 800 mW PD TSOLDER Soldering temperature (10s) TSTG Storage temperature TOPR Operating temperature 260 C -65 to 150 C 0 to 70 C Note 1: Do not exceed the absolute maximum rating of DVCC3IO (SM2-7, SN0-2, SP0-5, SV0-7, SW0-6, PA0-7, PB0-7, PC0-7, PG0-7, PH0-7, PN0-7, PP0-7, PT0-7) Note 2:Do not exceed the absolute maximum rating of DVCCM (SA0-7, SB0-7, SC0-7, SD0-7, SE0-7, SF0-7, SG0-7, SH0-7, SJ0-7, SK0-7, SL0-7, PR0-2) Note 3: Do not exceed the absolute maximum rating of DVCC3CMS (PE0-7, PF0-7) Note 4: Do not exceed the absolute maximum rating of DVCC3LCD (ST0-7, SU0-7, PJ0-7, PK0-7) Note 5: Do not exceed the absolute maximum rating of DVCC3I2S. Note 6: For PD0-7, VREFHVREFL the absolute maximum rating of AVCC3AD is applied. Note 7: For the USB, D+ and D- pins, the absolute maximum rating of AVCC3T/3C is applied. Note 8: The absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, the device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when desigining products that include this device, ensure that no absolute maximum rating value will ever be exceeded. TMPA910CRA- 871 2010-06-02 TMPA910CRA Solderability Test parameter Solderability Test condition Note Use of Sn-37Pb solder Bath Pass: Solder bath temperature = 230C, Dipping time = 5 seconds solderability rate until forming 95% The number of times = one, Use of R-type flux Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245C, Dipping time = 5 seconds The number of times = one, Use of R-type flux Caution about the Electrostatic Discharge (ESD) Sensitivity of This Product This product is an electrostatic discharge sensitive (ESDS) product that requires extra caution in handling. For ESD test data of this product, please contact your local Toshiba sales representative. Note: We don't take below NC pins as an object of ESD. [Ball A1,A19,W1,W19 and G7] these pins are not connect signals of internal chip. TMPA910CRA- 872 2010-06-02 TMPA910CRA 4.2 DC Electrical Characteristics Operating Voltage Symbol Parameter Min Typ Max 3.0 3.3 3.6 3.6 Unit Condition General I/O DVCC3IO Power Supply Voltage (DVCC3IO) (DVSSCOMx = AVSS = 0V) DVCCM_1 Memory I/O Power 3.0 3.3 DVCCM_2 Memory I/O Power 1.7 1.8 1.9 DVCC3CMS CMOS Sensor I/O Power 1.8 - 3.6 DVCC3LCD LCDD I/O Power 1.8 - 3.6 DVCC3I2S I S I/O Power 1.8 - 3.6 AVCC3AD ADC Power 3.0 3.3 3.6 AVDD3T/3C USB Power 3.15 3.3 3.45 1.4 1.5 1.6 2 DVCC1A Internal Power A DVCC1B Internal Power B DVCC1C High CLK oscillator and PLL X1 = 10 ~ 27MHz V CPU CLK XT1 = 30 ~ 34kHz (~200MHz) Power It is assumed that all power supply pins of the same rail are electrically connected externally and are supplied with the equal voltage. TMPA910CRA- 873 2010-06-02 TMPA910CRA Input Voltage (1) Symbol Parameter Min Typ Max - 0.3 x DVCC3IO - 0.3 x DVCCM Unit Condition Input Low Voltage for VIL0 SM2, SM6-7, SN0-2, SP0-3 SV0-7, SW6, PA0-7, PG0-7 3.0 DVCC3IO 3.6V PH0-7, PT0-7 VIL1 Input Low Voltage for 3.0 DVCCM 3.6V SELDVCCM = 1 SA0-7, SB0-7, SC0-7 VIL2 VIL3 VIL4 VIL5(Note) 1.7 DVCCM 1.9V SD0-7, SL4-7, PR2 - 0.3 x DVCCM Input Low Voltage for - 0.3 x DVCC3CMS - 0.3 x DVCC3I2S - 0.3 x AVCC3AD 3.0 AVCC3AD 3.6V - 0.25xDVCC3IO 3.0 DVCC3IO 3.6V - 0.25xDVCCM PE0-7, PF0-3, PF6-7 Input Low Voltage for -0.3 PL0-4, PM0-3 Input Low Voltage for PD0-7 SELDVCCM = 0 1.8 DVCC3CMS 3.6V V 1.8 DVCC3I2S 3.6V Input Low Voltage for VIL6 SM4, SM5, PC5, PC6, PC7 PN0-7, PP0-7 VIL7 VIL8 Input Low Voltage for PR2 Input Low Voltage for - PR2 3.0 DVCCM 3.6V SELDVCCM = 1 1.7 DVCCM 1.9V 0.25xDVCCM SELDVCCM = 0 Note: When Ports PD0 to PD7 are used as general-purpose inputs. Input Voltage (2) Symbol Parameter Min Typ Max Unit Condition 0.7 x DVCC3IO - DVCC3IO + 0.3 3.0 DVCC3IO 3.6 0.7 x DVCCM - DVCCM + 0.3 3.0 DVCCM 3.6 0.7 x DVCCM - DVCCM + 0.3 1.7 DVCCM 1.9 0.7 x DVCC3CMS - DVCC3CMS+0.3 1.7 DVCC3CMS 3.6 0.7 x DVCC3I2S - DVCC3I2S + 0.3 0.7 x ADCC3AD - AVCC3AD + 0.3 3.0 AVCC3AD 3.6 0.75 x DVCC3IO - DVCC3IO + 0.3 3.0 DVCC3IO 3.6V 0.75 x DVCCM - DVCCM + 0.3 Input High Voltage for VIH0 SM2, SM6-7, SN0-2, SP0-3 SV0-7, SW6, PA0-7, PG0-7, PH0-7, PT0-7 VIH1 VIH2 VIH3 VIH4 VIH5 (Note) Input High Voltage for SA0-7, SB0-7, SC0-7 SD0-7, SL4-7, PR2 Input High Voltage for PE0-7, PF0-3, PF6-7 Input High Voltage for PL0-4, PM0-3 Input High Voltage for PD0-7 V 1.7 DVCC3I2S 3.6 Input High Voltage for VIH6 SM4, SM5, PC5, PC6, PC7 PN0-7, PP0-7 VIH7 VIH8 Input High Voltage for PR2 Input High Voltage for PR2 0.75 x DVCCM - DVCCM + 0.3 3.0 DVCCM 3.6V SELDVCCM = 1 1.7 DVCCM 1.9V SELDVCCM = 0 Note: When Ports PD0 to PD7 are used as general-purpose inputs. TMPA910CRA- 874 2010-06-02 TMPA910CRA Output Voltage (1) Symbol Parameter Min Typ Max Unit Condition Output Low Voltage for VOL0 IOL = 2.0 mA SM3, SP4, SP5, SV0-7, 3.0 DVCC3IO 3.6V SW0-5, PB0-7, PC0-7, PG0-7 PH0-7, PN0-7, PP0-7, PT0-7 VOL1 IOL = 2.0 mA Output Low Voltage for 3.0 DVCCM 3.6V SA0-7, SB0-7, SC0-7 SD0-7, SE0-7, SF0-7, SG0-7 VOL2 - PR0-2 VOL3 VOL4 VOL5 VOL6 IOL = 2.0 mA SH0-7, SJ0-7, SK0-7, SL0-5 - 0.4 V 1.8 DVCCM 1.9V IOL = 3.0 mA Output Low Voltage for 1.8 DVCC3CMS 3.6V PF6-7 IOL = 2.0 mA Output Low Voltage for 1.8 DVCC3I2S 3.6V PL0-4, PM0-3 IOL = 2.0 mA Output Low Voltage for 3.0 AVCC3AD 3.6V PD4-7 IOL = 2.0 mA Output Low Voltage for 1.8 DVCC3LCD 3.6V ST0-7, SU0-7, PJ0-7, PK0-7 Output Voltage (2) Parameter Symbol Min Typ Max Unit Condition Output High Voltage for VOH0 SM3, SP4, SP5, SV0-7, SW0-5, PB0-7, PC0-7, PG0-7 IOH = -1.0 mA DVCC3IO0.4 3.0 DVCC3IO 3.6V PH0-7, PN0-7, PP0-7, PT0-7 VOH1 Output High Voltage for SA0-7, SB0-7, SC0-7 IOH = -1.0 mA DVCCM0.4 3.0 DVCCM 3.6V SD0-7, SE0-7, SF0-7, SG0-7 VOH2 SH0-7, SJ0-7, SK0-7, SL0-5 DVCCM0.4 - PR0-2 VOH3 VOH4 VOH5 Output High Voltage for PL0-4, PM0-3 Output High Voltage for PD4-7 Output High Voltage for ST0-7, SU0-7, PJ0-7, PK0-7 DVCC3I2S0.4 AVCC3AD0.4 DVCC3LCD0.4 TMPA910CRA- 875 - V IOH = -1.0 mA 1.8 DVCCM 1.9V IOH = -1.0 mA 1.8 DVCC3I2S 3.6V IOH = -1.0 mA 3.0 AVCC3AD 3.6V IOH = -1.0 mA 1.8 DVCC3LCD 3.6V 2010-06-02 TMPA910CRA Others Symbol IMon IMon Parameter Internal resistor (ON) MX, MY pins Internal resistor (ON) PX, PY pins Min Typ Max - - 30 Unit VOL = 0.2V - - 30 Condition VOH = 3.0 AVCC3AD 3.6V AVCC3AD - 0.2V ILI Input Leakage Current - 0.02 5 A ILO Output Leakage Current - 0.05 10 A 30 50 70 k - 1.0 - pF fc = 1MHz - 0.6 - V 3.0 DVCC3IO 3.6V PR2 - 0.6 - V 3.0 DVCC3IO 3.6V PR2 - 0.4 - V 1.7 DVCC3IO 1.9V R CIO Pull Up/Down Resistor for RESETn, PA0-7, PD6 Pin Capacitance Schmitt Width for SM4, SM5, PA0-7 PD6, PD7, PC5, PC6, PC7 VTH PF6, PF7, PN0-7, PP0-7 PT4-6 Note 1: Typical values show those with Ta = 25 C and DVCC3IO = DVCC3CMS = DVCC3I2S = DVCC3LCD = 3.3 V, DVCCM = 3.3V or DVCCM = 1.8VDVCC1A,1B,1C = 1.5V unless otherwise noted. Note 2: The above values do not apply when debug mode is used. TMPA910CRA- 876 2010-06-02 TMPA910CRA Symbol Parameter Min Typ Max - 3 4 DVCC3IO = 3.6V DVCC3CMS = 3.6V DVCC3I2S = 3.6V - 10 12 DVCC3LCD = 3.6V - 5 7 - 50 - 28 36 NORMAL (note2) - - ICC - - 13 17 15 19 7 9 181 Unit AVCC3AD = 3.6V PLL_ON fFCLK = mA 200MHz 8 DVCCM = 3.6V Only SDRAM access Only NORF access Only SDRAM access Only NORF access DVCC1A = 1.6V DVCC1B = 1.6V DVCC1C = 1.6V 11 mA 23 AVDD3T = 3.3V AVDD3C = 3.3V DVCCM = 1.9V 246 CPU HALT Condition PLL_OFF fFCLK =25MHz 58 DVCC3IO = 3.6V DVCCM = 3.6V DVCC3CMS = 3.6V DVCC3I2S = 3.6V DVCC3LCD = 3.6V AVCC3AD = 3.6V AVDD3T = 3.6V AVDD3C = 3.6V DVCC1A = 1.6V DVCC1B =1.6V DVCC1C = 1.6V Operationg Conditions: NORMAL CPU: DRYSTONE rev2.1 Instruction Cache : ON, Data Cache: ON Program Execution area : internal RAM, Data area: internal RAM, Stack area: internal RAM USB: Default condition LCDC: HVGA_16bpp A/DC: 5s repeat conversion 2 I S, CMS: Stop SDHC: Stop UART: 480kbps transmission SSP: 100kbps transmission PWM: 100kHz output SDRAM: 100MHz CL=2 BL=8 32bit bus Read/Write (External bus start operation duty is approximately 17%) Or NORF: asynchronous NORF 160ns access 16bit bus continuous read CPU HALT CPU: HALT, Peripheral Circuit: TSB original program USB: Suspend LCDC: TEST mode simplicity operation (VRAM: Internal RAM) 2 A/DC, I S, CMS, SDHC, UART, SSP, PWM: No operarion Note 1: Typical values show those with Ta = 25C, DVCC3IO = DVCC3CMS = DVCC3I2S = DVCC3LCD = 3.3V, DVCCM = 3.3V or DVCCM = 1.8V, DVCC1A,1B,1C = 1.5V unless otherwise noted. Note 2: IC measurement conditions: CL = 25 pF for bus pins, other output pins = open, input pins = level fixed Note 3: The above values do not apply when debug mode is used. TMPA910CRA- 877 2010-06-02 TMPA910CRA Symbol Parameter Min Typ Max Unit Condition Ta 70C 28 7 ICC Power Cut Mode (With PMC function) - 16 A Ta 50C 240 Ta 70C 130 Ta 50C 9 DVCC3IO = 3.6V DVCCM = 3.6V DVCC3CMS = 3.6V DVCC3I2S = 3.6V DVCC3LCD = 3.6V AVCC3AD = 3.6V AVDD3T = 0V AVDD3C = 0V DVCC1A = 0V DVCC1B = 1.6V, DVCC1C = 0V XT = 32kHz X = OFF Note 1: Typical values show those with Ta = 25C, DVCC3IO = DVCC3CMS = DVCC3I2S = DVCC3LCD = 3.3 V, DVCCM = 3.3V or DVCCM = 1.8V,DVCC1A,1B,1C = 1.5V, unless otherwise noted. Note 2: IC measurement conditions: CL = 50 pF for bus pins, other output pins = open, input pins = level fixed Note 3: The above values do not apply when debug mode is used. TMPA910CRA- 878 2010-06-02 TMPA910CRA 4.3 AC Electrical Characteristics All AC specifications shown below are the measurement results under the following conditions unless specified otherwise. AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK) which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCCM, Low = 0.3 x DVCCM * Input level: High = 0.9 x DVCCM, Low = 0.1 x DVCCM Note: The "Equation" column in the table shows the specifications under the conditions DVCCM=1.7 to 1.9 V, DVCCM = 3.0 to 3.6 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. In the case of asynchronous mode, the external wait function from external SMCWAITn pin can't be supported. 4.3.1 Basic Bus Cycles (Asynchronous mode) Read cycle (asynchronous mode) Equation No. Parameter Symbol Min Max 10 800 100 MHz 96 MHz N = 10 N = 10 N=5 M=3 M=3 M=1 K = 10 K = 10 K=5 L=6 L=6 L=3 10.0 10.4 20.8 48 MHz Internal bus period ( = T) tCYC 2 A0-A25 valid to D0-D31 input tAD (N)T - 15.0 85.0 89.2 89.2 3 SMCOEn fall to D0-D31 input tOED (N-M)T - 10.0 60.0 62.9 73.3 4 SMCOEn low level pulse width tOEW (N-M)T - 8.0 62.0 64.9 75.3 5 A0-A25 valid to SMCOEn fall tAOE MT - 5.0 25 26.3 15.8 6 SMCOEn rise to D0-D31 hold tHR 0 0 0 0 7 SMCOEn high level pulse width tOEHW MT - 8.0 22 23.3 12.8 1 Unit ns Write cycle (asynchronous mode) 8 D0-D31 valid to SMCWEn rise tDW (L+1)T - 10.0 60.0 62.9 73.3 9 D0-D31 valid to SMCWEn rise (bls=1) tSDS (L+1)T - 10.0 60.0 62.9 73.3 10 SMCWEn low level width tWW LT - 8.0 52.0 54.5 54.5 11 A0-A25 valid to SMCWEn fall tAW T - 5.0 5.0 5.4 15.8 12 SMCWEn rise to A0-A25 hold tWA (K-L-1)T - 5.0 25.0 26.3 15.8 15.8 13 SMCWEn rise to D0-D31 hold tWD (K-L-1)T - 5.0 25.0 26.3 14 SMCOEn rise to D0-D31 output tOEO 2 2.0 2.0 2.0 15 Data byte control to write complete time tSBW LT - 8.0 52.0 54.5 54.5 * ns The variables used in the equations in the table are defined as follows: N = Number of tRC cycles M = Number of tCEOE cycles K = Number of tWC cycles L = Number of tWP cycles Measuring Condition Connection 1. DVCC3IO x 0.7 SELDVCCM DVCC3IO Register 1. PMCDRV<DRV_MEM1:0> = 0y11 (Full Drive at 1.80.1V) 2. PMCDRV<DRV_MEM1:0> = 0y01 (Half Drive at 3.30.3V) Loaded capacitance CL = 25 pF TMPA910CRA- 879 2010-06-02 TMPA910CRA (1) Asynchronous memory read cycle (tRC = 4, tCEOE = 1) (tRC = 4) tCYC tCH tCL Internal SMCCLK (Not output from external pin) SMCAVDn A0 to A25 tAD SMCCSn tAOE tHR SMCOEn tOEHW tOEW tOED D0 to D31 Data input SMCBEn SMCWEn TMPA910CRA- 880 2010-06-02 TMPA910CRA (2) Asynchronous memory write cycle (tWC = 4, tWP = 2) (tWC = 4) tCYC tCH tCL Internal SMCCLK (Not output from external pin) SMCAVDn A0 to A25 SMCCSn tWA tAW SMCWEn tWW tDW D0 to D31 tWD Data output tOEO SMCOEn tSBW SMCBEn bls = 1 tSDS SMCBEn bls = 0 TMPA910CRA- 881 2010-06-02 TMPA910CRA 4.3.2 Basic Bus Cycles (Synchronous mode) All AC specifications shown below are the measurement results under the following conditions unless specified otherwise. AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCCM, Low = 0.3 x DVCCM * Input level: High = 0.9 x DVCCM, Low = 0.1 x DVCCM Note: The "Equation" column in the table shows the specifications under the conditions DVCCM = 1.7 to 1.9 V or DVCCM = 3.0 to 3.6 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. Read/write cycle (synchronous mode) Equation No. Parameter Symbol Min Max 10 800 100 MHz 96 MHz N = 10 N = 10 N=5 M=3 M=3 M=1 K = 10 K = 10 K=5 L=6 L=6 L=3 10 10.4 20.8 48 MHz Internal bus period ( = T) tCYC 2 CLK rise up time tCR 1.5 1.5 1.5 1.5 3 CLK fall down time tCF 1.5 1.5 1.5 1.5 4 CLK high level width tCH 0.5T - 1.5 3.5 3.7 8.9 5 CLK low level width tCL 0.5T - 1.5 3.5 3.7 8.9 6 SMCCLK rise to D0-D31 input tACC 82.0 85.8 75.3 7 SMCAVDn fall to SMCCLK rise tAVC 0.5T - 3.0 2.0 2.2 7.4 8 SMCCLK rise to SMCAVDn rise tAVH 0.5T - 3.0 2.0 2.2 7.4 9 A0-A25 valid to SMCCLK rise tADC 0.5T - 5.0 0.0 0.2 5.4 SMCCS valid to SMCCLK rise tCES 0.5T - 5.0 0.0 0.2 5.4 T - 3.0 7.0 7.4 17.8 2.0 2.4 12.8 1 10 (N-1.0)T - 8.0 11 SMCAVDn low level width tAVPW 12 SMCCLK rise to D0-D31 input tBACC 13 Data hold time with respect to SMCCLK rise tCDH 0.0 0.0 0.0 0.0 14 WAITn setup time with respect to SMCCLK rise tTK 5.0 5.0 5.0 5.0 15 WAITn hold time with respect to SMCCLK rise tKT 8.0 8.0 8.0 8.0 16 SMCWEn low level width tWW LT - 8.0 52.0 54.5 54.5 17 SMCWEn rise to D0-D31 setup time tSDW LT - 10.0 50.0 52.5 52.5 SMCWEn rise to D0- D31 hold time tHDW (K- L)T - 4.0 36.0 37.7 37.7 18 * T - 8.0 Unit ns The variables used in the equations in the table are defined as follows: N = Number of tRC cycles + required wait states, M = Number of tCEOE cycles K = Number of tWC cycles + required wait states, L = Number of tWP cycles Measuring Condition Connection 1. DVCC3IO x 0.7 SELDVCCM DVCC3IO Register 1. PMCDRV<DRV_MEM1:0> = 0y11 (Full Drive at 1.80.1V) 2. PMCDRV<DRV_MEM1:0> = 0y01 (Half Drive at 3.30.3V) Loaded capacitance CL = 25 pF TMPA910CRA- 882 2010-06-02 TMPA910CRA (1) Synchronous memory read cycle (0 wait states, tRC = 7, tCEOE = 3) (tRC = 7) tCYC tCH Wait Sampling point (tRC-1) tCR SMCCLK tCL tCF tTK tKT SMCWAITn tADC A0 to A25 tCES tACC SMCCSn tAVH tAVC SMCAVDn tAVPW tBACC tBACC tBACC tCDH tCDH tCDH 2'ndData 3'rdData SMCOEn D0 to D31 1'stData tCDH 4thData SMCBEn SMCWEn TMPA910CRA- 883 2010-06-02 TMPA910CRA (2) Synchronous memory read cycle (1 wait state, tRC = 6 ,tCEOE = 3) (tRC = 6) tCYC tCH Wait Sampling point (tRC-1) SMCCLK tCL tT tK tT SMCWAITn 1-wait tADC A0 to A25 tCES tACC SMCCSn tAVH tAVC SMCAVDn tBACC tAVPW tBACC tBACC SMCOEn tCDH D0 to D31 1'stData tCDH tCDH tCDH 2'ndData 3'rdData 4thData SMCBEn SMCWEn TMPA910CRA- 884 2010-06-02 TMPA910CRA (3) Synchronous memory write cycle (0 wait states, tWC = 6, tWP = 3) (tWC = 6) tCYC tCH Wait Sampling point (tWC-1) SMCCLK tCL tT tK SMCWAITn tADC A0 to A25 tCES SMCCSn tAVH tAVC SMCAVDn tAVPW SMCOEn D0 to D31 1'stData tSDW tHDW SMCBEn (tWP = 3) SMCWEn tWW TMPA910CRA- 885 2010-06-02 TMPA910CRA 4.3.3 DDR SDRAM Controller AC Electrical Characteristics AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCCM, Low = 0.3 x DVCCM * Input level: High = 0.9 x DVCCM, Low = 0.1 x DVCCM * Clock output Differential level (VOD): VOD =0.6 x DVCCM * Clock output Differential Crosspoint level (VOX): High = 0.6 x DVCCM, Low = 0.4 x DVCCM Note 1: Only DDR SDRAM devices of LVCMOS type are supported. DDR SDRAM devices of SSTIL (2.5 V) type are not supported. Note 2: The "Equation" column in the table shows the specifications under the conditions DVCCM = 1.7 to 1.9 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. Symbol Parameter Min VIX AC Differential Cross point Voltage 0.4 x DVCCM No. Parameter Symbol Typ. Max Unit 0.6 x DVCCM Equation Min Max Condition 1.7 DVCCM 1.9V 100 96 MHz MHz 10 10.4 tCK T 3 CLK Differential Crosspoint cycle tCH 0.5T - 0.5 4.5 4.7 4 CLK Differential Crosspoint cycle tCL 0.5T - 0.5 4.5 4.7 1 DMCDCLKP/ DMCDCLKN cycle time 2 DMCDCLKP&DMCDCLKN Clock Skew time 5 6 DMCDQSx Access time from CLK(CL* =3) Data Access time from CLK(CL* =3) -0.35 0.35 tAC1 2T-13.5 6.5 7.3 tAC2 2T-13.5 6.5 7.3 0.7 0.7 0.7 tDQSQ 0 8 Address set-up time tAS 0.5T - 3.0 2.0 2.2 9 Address hold time tAH 0.5T - 3.0 2.0 2.2 7 DQS to Data Skew time 10 CKE set-up time tCKS 0.5T - 3.0 2.0 2.2 11 Command set-up time tCMS 0.5T - 3.0 2.0 2.2 12 Command hold time tCMH 0.5T - 3.0 2.0 2.2 13 Data Setup Time tDS 0.25T - 1.5 1.0 1.1 14 Data Hold Time tDH 0.25T - 1.5 1.0 1.1 15 DMCDDM Setup Time tMS 0.25T - 1.5 1.0 1.1 16 DMCDDM Hold Time tMH 0.25T - 1.5 1.0 1.1 tDQSS 0.75T 17 Write command to 1'st DQS Latching Trasistion Unit 1.25T ns 7.50 to 12.5 7.80 to 13.0 *CL = CAS latency In case of DDR_SDRAM, CL number counting method is defferent with SDR_SDRAM. Memory controller CL number = ( DDR_SDRAM's CL Number ) - 1 Measuring Condition Connection 1. DVCC3IO x 0.7 SELDVCCM DVCC3IO 2. DVCC3IO x 0.7 SELMEMC DVCC3IO 3. DMCCLKIN pin connect to DMCDCLKP Register 1. PMCDRV<DRV_MEM1:0> = 0y11 (Full Drive) 2. dmc_user_config5 = 0x0000_0048 Loaded capacitance DMCDCLKP pin and DMCDCLKN pin: CL = 15pF Others: CL = 25 pF TMPA910CRA- 886 2010-06-02 TMPA910CRA (1) DDR SDRAM read timing (2-word read mode, Memory's CAS latency = 3 Memory controller's CAS latency = 2) tCK DMCDCLKP VOD DMCDCLKN tCL VOX tCH CL=1 CL=2 DMCCSx tCMS tCMH DMCRASn tCMS tCMH DMCCASn ACT READ CMD DMCWEn tAS tAH A0 to A15 tAS tAH DMCAP DMCDDMx tAC1 tAC1 Input DMCDDQSx tDQSQ D0 to D15 tAC2 tAC2 Input TMPA910CRA- 887 Input 2010-06-02 TMPA910CRA (2) DDR SDRAM write timing (2-word write mode) tCK DMCDCLKP VOD DMCDCLKN tCL tCH VOX DMCCSn tCMS tCMH DMCRASn tCMS tCMH DMCCASn ACT tCMS tCMH DMCWEn tAS WRITE CMD tAH A0 to A15 tAS tAH DMCAP tMS tMH tMS tMH DMCDDMx Output Output tDQSS DMCDDQSx Output tDS tDH tDS tDH D0 to D15 Output TMPA910CRA- 888 Output 2010-06-02 TMPA910CRA 4.3.4 Mobile SDR SDRAM Controller AC Electrical Characteristics AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCCM, Low = 0.3 x DVCCM * Input level: High = 0.9 x DVCCM, Low = 0.1 x DVCCM Note: The "Equation" column in the table shows the specifications under the conditions DVCCM = 1.7 to 1.9 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. No. Parameter Symbol Equation Min Max 100 MHz 96 MHz Unit 1 CLK cycle time tCK T 10 10.4 2 DMCSCLK high level width tCH 0.5T - 1.5 3.5 3.7 3 DMCSCLK low level width tCL 0.5T - 1.5 3.5 3.7 6.0 6.4 4 Access time from CLK(CL* = 2) T - 4.0 tAC 5 Data hold time from internal read tHR 2.0 2.0 2.0 6 Data setup time tDS 0.5T - 3.0 2.0 2.2 7 Data hold time tDH 0.5T - 4.0 1.0 1.2 8 Address setup time tAS 0.5T - 3.0 2.0 2.2 tAH 0.5T - 4.0 1.0 1.2 tCKS 0.5T - 3.0 2.0 2.2 11 Command setup time tCMS 0.5T - 3.0 2.0 2.2 12 Command hold time tCMH 0.5T - 4.0 1.0 1.2 9 Address hold time 10 CKE setup time ns *CL = CAS latency Measuring Condition Connection 1. DVSSCOMx SELDVCCM DVCC3IO x 0.3 2. DVSSCOMx SELMEMC DVCC3IO x 0.3 3. DMCCLKIN pin connect to DVSSCOMx Register 1. PMCDRV<DRV_MEM1:0> = 0y11 (Full Drive) 2. dmc_user_config3 = 0x0000_0011 (32bit bus width memory) dmc_user_config3 = 0x0000_0010 (16bit bus width memory) Loaded capacitance DMCSCLK pin: CL = 15pF Others: CL = 25 pF TMPA910CRA- 889 2010-06-02 TMPA910CRA 4.3.5 SDR SDRAM Controller Electrical Characteristics AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCCM, Low = 0.3 x DVCCM * Input level: High = 0.9 x DVCCM, Low = 0.1 x DVCCM Note: The "Equation" column in the table shows the specifications under the conditions DVCCM = 3.0 to 3.6 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. No. Parameter Symbol Equation Min Max 100 MHz 96 MHz Unit 1 CLK cycle time tCK T 10 10.4 2 DMCSCLK high level width tCH 0.5T - 1.5 3.5 3.7 3 DMCSCLK low level width tCL 0.5T - 1.5 3.5 3.7 4 Access time from CLK(CL* =2) tAC 6.0 6.4 5 Data hold time from internal read tHR 2.0 2.0 2.0 6 Data set-up time tDS 0.5T - 3.0 2.0 2.2 7 Data hold time tDH 0.5T - 4.0 1.0 1.2 8 Address set-up time tAS 0.5T - 3.0 2.0 2.2 9 Address hold time tAH 0.5T - 4.0 1.0 1.2 T - 4.0 10 CKE set-up time tCKS 0.5T - 3.0 2.0 2.2 11 Command set-up time tCMS 0.5T - 3.0 2.0 2.2 12 Command hold time tCMH 0.5T - 4.0 1.0 1.2 ns *CL = CAS latency Measuring condition Connection 1. DVCC3IO x 0.7 SELDVCCM DVCC3IO 2. DVSSCOMx SELMEMC DVCC3IO x 0.3 3. DMCCLKIN pin connect to DVSSCOMx Register 1. PMCDRV<DRV_MEM1:0> = 0y11 (Full Drive) 2. dmc_user_config3 = 0x0000_0011 (32bit bus width memory) dmc_user_config3 = 0x0000_0010 (16bit bus width memory) Loaded capacitance DMCSCLK pin: CL = 15pF Others: CL = 25 pF TMPA910CRA- 890 2010-06-02 TMPA910CRA (1) SDRAM read timing (CAS latency = 2) tCK DMCSCLK tCH tCL CL = 1 CL = 2 DMCSDQMx tCMS tCMS tCMH DMCSCSn tCMH ACT DMCRASn DMCCASn READ CMD DMCWEn tAS tAH A0 to A15 tAS tAH DMCAP tAC D0 to D31 tHR Data input TMPA910CRA- 891 2010-06-02 TMPA910CRA (2) SDRAM write timing tCK DMCSCLK tCH tCL tCMS DMCSDQMx tCMS DMCSCSn tCMH ACT DMCRASn tCMH WRITE CMD DMCCASn DMCWEn tAS tAH A0 to A15 tAS tAH DMCAP tDS D0 to D31 tDH Data output TMPA910CRA- 892 2010-06-02 TMPA910CRA (3) SDRAM burst read timing (burst cycle start, CAS latency = 2) tCK DMCSCLK tCMS DMCSDQMx DMCSCSn tCMS tCMH DMCRASn tCMS tCMH DMCCASn READ CMD tCMH DMCWEn tAS tAH tAS tAH tAS A0 to A15 DMCAP tAC D0 to D31 tAC Data input tHR TMPA910CRA- 893 tAC Data input Data input tHR 2010-06-02 TMPA910CRA (4) SDRAM burst read timing (burst timing end) tCK DMCSCLK tCMH tCMS DMCSDQMx tCMS tCMH tCMS tCMH tAS tAH DMCSCSn DMCRASn DMCCASn DMCWEn A0 to A15 DMCAP tAC D0 to D31 tAC Data input tHR Data input tHR TMPA910CRA- 894 2010-06-02 TMPA910CRA (5) SDRAM initialization timing tCK DMCSCLK DMCSDQMx tCMS DMCSCSn DMCRASn tCMS tCMH tCMS tCMH tCMS tCMH DMCCASn tCMH DMCWEn A0 to A15 tAS tAH DMCAP TMPA910CRA- 895 2010-06-02 TMPA910CRA (6) SDRAM refresh timing tCK DMCSCLK tRC DMCSDQMx tCMS tCMH DMCSCSn DMCRASn DMCCASn DMCWEn (7) SDRAM self-refresh timing tCK DMCSCLK tCKS tCKS DMCCKE DMCSDQMx tCMS tCMH DMCSCSn DMCRASn DMCCASn DMCWEn TMPA910CRA- 896 2010-06-02 TMPA910CRA 4.3.6 NAND Flash Controller AC Electrical Characteristics AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCC3IO, Low = 0.3 x DVCC3IO * Input level: High = 0.9 x DVCC3IO, Low = 0.1 x DVCC3IO Note 1: The "Equation" column in the table shows the specifications under the conditions DVCC3IO = 3.0 to 3.6 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. Note 2: The letter "n" in the equations represents the value set in NDFMCR2<SPLR[2:0]>, the letter "m" the value set in NDFMCR2<SPHR[2:0]>, the letter "k" the value in NDFMCR2<SPLW[2:0]>, and the letter "l" the value in NDFMCR2<SPHW[2:0]>. Care should be taken not to use values that produce negative results. 100 MHz (n = 3) (m = 3) (k = 3) (l = 3) 96 MHz (n = 3) (m = 3) (k = 3) (l = 3) (n + m) T 60.0 62.5 62.5 Equation No. Symbol Parameter Min Max 1-1 tRC Read access cycle 1-2 tWC Write access cycle (k + l) T 60.0 2 tRP NDREn low level pulse width (n) T -10.0 20.0 21.2 3 tRHP NDREn high level pulse width (m) T -10.0 20.0 21.2 4 tREA NDREn data access time 16.0 17.2 5 tOH Read data hold time 0 0 0 6 tWP NDWEn low level pulse width (k) T -10.0 20.0 21.2 7 tWHP NDWEn high level pulse width (l) T -10.0 20.0 21.2 8 tDS Write data setup time (k) T -10.0 20.0 21.2 9 tDH Write data hold time (l) T -10.0 20.0 21.2 (n) T - 14 Unit ns (Basic clock synchronous to internal fHCLK) SPLR2:0 = "4" SPHR2:0 = "2" tRP NDREn Read cycle tRHP NDWEn tREA tOH ND0 to ND7 Data input SPLW2:0 = "3" SPHW2:0 = "3" NDREn tWP Write cycle NDWEn tWHP tDS ND0 to ND7 AC measurement conditions tDH Data output CL = 40 pF TMPA910CRA- 897 2010-06-02 TMPA910CRA 4.3.7 LCD Controller AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCC3LCD, Low = 0.3 x DVCC3LCD Note: The "Equation" column in the table shows the specifications under the conditions DVCC3LCD = 1.8 to 3.6 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to1.6 V. Parameter Equation Symbol LCLCP clock period (nT) tCW Max 30 96 MHz 48 MHz (n = 3) (n = 3) (n = 2) 30.0 31.25 41.6 5.0 5.4 15.8 15.0 15.8 15.8 Unit When n = even LCLCP high level pulse width (including phase reversal) Min 100 MHz tCWH (nT / 2) - 5.0 When n = odd ((n-1)T / 2) - 5.0 When n = even LCLCP low level pulse width (including phase reversal) tCWL ns When n = even Data valid to LCLCP fall (including phase reversal) (nT / 2) - 5 When n = odd ((n1)T / 2) - 5 tDSU (nT / 2) - 6.0 When n = odd 4.0 4.4 14.8 14.0 14.8 14.8 ((n-1)T / 2) - 6.0 When n = even LCLCP fall to data hold (including phase reversal) tDHD (nT / 2) - 6.0 When n = odd ((n1)T / 2) - 6.0 tCWH tCWL LCDTiming2<IPC> = 1 tCW LCLCP tCWH tCWL LCDTiming2<IPC> = 0 tDSU LD0 to LD23 tDHD LD0 to LD23 out AC measurement conditions * CL = 20 pF Note: The letter "n" in the equations represents the value set in LCDTiming2<PCD_HI><PCD_LO> plus two. The following limitations apply to the "n" value depending on operating frequency. Example 1: When fHCLK = 100 MHz, LCDTiming2<PCD_HI><PCD_LO> 1 (n 3). Example 2: When fHCLK = 48 MHz, LCDTiming2<PCD_HI><PCD_LO> 0 (n 2). TMPA910CRA- 898 2010-06-02 TMPA910CRA 4.3.8 SSP Controller AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fPCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVC3IOM, Low = 0.3 x DVCC3IO * Input level: High = 0.9 x DVCC3IO, Low = 0.1x DVCC3IO Note: The "Equation" column in the table shows the specifications under the conditions DVCC3IO = 3.0 to 3.6 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. Equation Parameter Symbol PCLK PCLK 100M Hz 96 MHz Min Max SPxCLK Period (Master) Tm (m)T However more than 50ns SPxCLK Period (Slave) Ts (n)T SPxCLK rise up time tr 10.0 SPxCLK fall down time tf 10.0 (m = 6 (m = 6 n = 12) n = 12) 60.0 62.5 120.0 125.0 10.0 10.0 10.0 10.0 Master mode: SPxCLK low level pulse width tWLM (m)T / 2 - 7.0 23.0 24.3 Master mode: SPxCLK high level pulse width tWHM (m)T / 2 -7.0 23.0 24.3 Slave mode: SPxCLK low level pulse width tWLS (n)T / 2 - 7.0 53.0 55.5 Slave mode: SPxCLK high level pulse width tWHS (n)T / 2 - 7.0 53.0 55.5 15.0 15.0 20.0 21.3 10.0 11.2 5.0 5.0 (m)T + 10 50 to 70 52.5 to 72.5 (3T) + 25 55.0 56.3 80.0 83.3 80.0 83.8 Master Mode: tODSM SPxCLK rise/fall to output data valid Master Mode: tODHM SPxCLK rise/fall to output data hold Master Mode: Master Mode: SPxCLK rise/fall to input data hold Master Mode: SPxFSS valid to SPxCLK rise/fall Slave mode: SPxCLK rise/fall to output data valid delay time Slave mode: SPxCLK rise/fall to input data valid delay time Slave mode: SPxCLK rise/fall to input data hold Slave mode: SPxFSS valid to SPxCLK rise/fall (m)T /2 - 20 tIDHM 5.0 tOFSM (m)T -10 tODSS tODHS SPxCLK rise/fall to output data hold (m)T/2 -10 tIDSM SPxCLK rise/fall to input data valid delay time Slave mode: 15.0 Note1) (n)T /2 + (2T) (n)T /2 + (3T) tIDSS - 10.0 tIDHS (3T) + 10 40.0 41.3 tOFSS (n)T 120 125 Unit ns Note1: Baud rate Clock is set under below condition Master mode m = (<CPSDVSR> x (1 + <SCR>)) = fPCLK /SPxCLK <CPSDVR> is set only even number and "m" must set during 65204 m 2 Slave Mode n = fPCLK /SPxCLK (65204 n 12 ) AC measurement conditions: Load capacitance CL = 25 pF TMPA910CRA- 899 2010-06-02 TMPA910CRA * SSP SPI mode (Master) * fPCLK 2 x SPxCLK (max) * fPCLK 65204 x SPxCLK (min) (1) Master SSPxCR0<SPH> = 0 (Data is latched on the first edge.) Tm tOFSM SPxCLK output (Master) (SSPxCR0<SPO> = 0) SPxCLK output (Master) (SSPxCR0<SPO> = 1) tWH Internal tf tWL clock state tr Internal clock state tODSM tODSM tODHM SPxDO output tIDHM tIDSM SPxDI input SPxFSS output * SSP SPI mode (Master) (2) Master SSPxCR0<SPH> = 1 (Data ist latched on the second edge.) OFSM Tm SPxCLK output (Master) tWH (SSPxCR0<SPO> = 1) tf tWL tr SPxCLK output (Master) (SSPxCR0<SPO> = 0) tODSM tODHM SPxDO output tIDSM tIDHM SPxDI input SPxFSS output TMPA910CRA- 900 2010-06-02 TMPA910CRA * SSP SPI mode (Slave) 12 x SPxCLK (max) * fPCLK 65204 x SPxCLK (min) * fPCLK (3) Slave SSPxCR0<SPH> = 0 (Data is latched on the first edge.) Ts tOFSS SPxCLK input tWH (SSPxCR0<SPO> = 0) tf tWL SPxCLK input tr (SSPxCR0<SPO> = 1) tIDSS tIDHS SPXDI input tODHS tODSS SPxDO output SPxFSS input * SSP SPI mode (Slave) (4) Slave SSPxCR0<SPH> = 1 (Data is latched on the second edge.) Ts tOFSS SPxCLK input tWH (SSPxCR0<SPO> = 1) tf tWL tr SPxCLK input (SSPxCR0<SPO> = 0) tIDSS tIDHS SPXDI input tODSS tODHS SPxDO output SPxFSS input TMPA910CRA- 901 2010-06-02 TMPA910CRA I2S 4.3.9 AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fPCLK), which is one-half of the CPU clock (fFCLK). fPCLK 16 x I2SxSCLK. * The letter "t" used in the equations in the table represents the period of frequency (fOSCH). * Output level: High = 0.7 x DVCC3I2S, Low = 0.3 x DVCC3I2S * Input level: High = 0.9 x DVCC3I2S, Low = 0.1 x DVCC3I2S Note: The "Equation" column in the table shows the specifications under the conditions DVCC3I2S = 1.8 to 3.6 V and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V. In slave mode, the stabilization time is required after I2SxCLK input. Parameter I2SSCLK Input Symbol Equation Min 100 MHz 96 MHz Unit 24.576 24.576 24.576 Use I2SSCLK fMC fSC /4 fSC /1 6.144 to 24.576 6.144 to 24.576 Use fOSCH fMC t /4 t /1 2.5 to 27 6 to 24 I2SSCLK rise time tr - 5 5 5 I2SSCLK fall time tf - 5 5 5 10 I2SMCLK Out fSC Max I2SxMCLK high level pulse width tWMH 10 - 10 I2SxMCLK low level pulse width tWML 10 - 10 10 I2SxCLK clock output period fSCKM 333 - 333 333 I2SxCLK clock input period fSCKS 160 - 160 160 I2SxCLK high level pulse width tWH 0.45 fSCKM - 149 149 I2SxCLK low level pulse width tWL 0.45 fSCKM - 149 149 tHTRM 0.5 fSCKM + 2T - 186 187 tDTRM - 0.5 fSCKM + 3T + 10 206 207 tSRM 10.0 - 10 10 Master mode: I2S1DATO, I2SxWS hold time Master mode: I2S1DATO, I2SxWS delay time Master mode: I2S0DATI setup time Master mode: I2S0DATI hold time Master mode: I2SSCLK, I2SxMCLK delay time Master mode: I2SxMCLK, I2SxSCLK delay time Slave mode: I2S1DATO, I2SxWS hold time Slave mode: I2S1DATO, I2SxWS delay time Slave mode: I2S0DATI setup time Slave mode I2S0DATI hold time MHz ns tHRM 0.2 fSCKM - 66 66 tDLY0 - 20.0 20 20 tDLY1 - 10.0 10 10 tHTRS 0.5 fSCKS + 2T - 100 100 tDTRS - 0.8 fSCKS + 3T + 20 178 179 tSRS 10.0 - 10 10 tHRS 0.2 fSCKS - 32 32 AC measurement conditions: Load capacitance CL = 25 pF TMPA910CRA- 902 2010-06-02 TMPA910CRA (1) I2S master mode fSC 0.7 VCC I2SSCLK input tf 0.3VCC tr fMC tWML 0.7 VCC tWMH 0.3VCC I2SxMCLK output tDLY0 tWL tWH I2SxSCLK output tSRM tHRM I2S0DATI input tHTRM tDTRM I2S1DATO output I2SxWS output (2) I2S slave mode tWL tWH I2SxSCLK input tSRS I2S0DATI input I2SxWS input tHRS tHTRS tDTRS I2S1DATO output TMPA910CRA- 903 2010-06-02 TMPA910CRA 4.3.10 CMOS Sensor I/F AC measurement conditions * The letter "T" used in the equations in the table represents the period of internal bus frequency (fHCLK), which is one-half of the CPU clock (fFCLK). * Output level: High = 0.7 x DVCC3CMS, Low = 0.3 x DVCC3CMS * Input level: High = 0.9 x DVCC3CMS, Low = 0.1 x DVCC3CMS Note: The "Equation" column in the table shows the specifications under the conditions DVCC3CMS = 1.8 to 3.6 V and DVCC1A = DVCC1B = DVCC1C =1.4 to 1.6 V. Parameter Equation Symbol CMSPCK input frequency * fPCK Min Max 2.0 35.0 tr CMSPCK input rise time 5.0 CMSPCK low level pulse width tCWL 10.0 CMSPCK high level pulse width tCWH 10.0 tDS 5.0 tDH 5.0 tCS 5.0 tCH 0 CMSD[7:0] input data valid to CMSPCK rise MHz 5.0 tf CMSPCK input fall time Unit ns CMSPCK rise to CMSD[7:0] input data hold CMSHBK, CMSVSY input to CMSPCK rise CMSPCK rise to CMSHBK, CMSVSY hold AC measurement conditions: * The CMSPCK input frequency must be one-half or less of the frequency of the internal system clock (fHCLK). tCWL tCWH tr tf CMSPCK tCS tDS tCSD tDSD tDH tDHD tCH tCHD CMSD[7:0] CMSHBK CMSHSY CMSVSY TMPA910CRA- 904 2010-06-02 TMPA910CRA 4.4 AD Conversion Characteristics Note: "Caltulation" of following table is effective in a range of AVCC3AD = 3.0 to 3.6V, DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6V. Parameter Symbol Condition Min Typ Max Analog reference voltage (+) VREFH AVCC3AD AVCC3AD AVCC3AD Analog reference voltage (-) VREFL DVSSCOMn DVSSCOMn DVSSCOMn AD converter power supply voltage AD converter GND Analog input voltage AVCC3AD 3.0 3.3 3.6 AVSS DVSSCOMn DVSSCOMn DVSSCOMn AVIN VREFL Unit V VREFH Analog reference voltage IREFON <VREFON> = 1 2.1 3.5 Power supply current IREFOFF <VREFON> = 0 0.1 10 A mA Full Scale Error EFULL +1 -1 to +4 LSB Offset Error EOFF 3 -4 to +1 LSB Differential Error EDNL -1 to +2 2 LSB Integral Error EINL -2 to +3 3 LSB Note 1: Error = ("conversion result" - "theoretical value") 1 LSB = (VREFH - VREFL)/1024[V] Note 2: The quantization error does not include. Note 3: Minimum operating frequency The minimum operating clock and maximum operating clock (ADCLK) of the AD converter is 3 MHz and 33 MHz, respectively. (3MHz ADCLK 33MHz) Minimum conversion time is 1.39s at 33MHz, and maximum conversion time is 15.3s at 3MHz. TMPA910CRA- 905 2010-06-02 TMPA910CRA 4.5 Recommended Oscillation Circuit The TMPA910CRA is evaluated by using the resonators shown below. Please use this information when selecting the resonator to be used. Note: The total load capacitance of the oscillation pins is the sum of the external (or internal) load capacitances C1and C2 and the stray capacitance on the circuit board. Even if the recommended C1 and C2 constants are used, the total load capacitance may vary with each board. In board design, the patterns around the oscillation circuit must be as short as possible. We also recommend that oscillation evaluations be performed on the actual board to be used. (1) Connection example X1 X2 XT1 XT2 Rf Rf Rd Rd C2 C1 C2 C1 Connection diagram of low-frequency oscillator Connection diagram of high-frequency oscillator (2) Recommended ceramic resonator: Murata Manufacturing Company, Ltd. The table below shows the recommended circuit constants for the high-frequency oscillation circuit. MCU frequency 12.000 16.000 TMPA910CRAXBG 20.000 C1 C2 Rd Rf Power supply Temperature [pF] [pF] [] [] voltage range [V] range [C] 0 Open 1.4 to 1.6 0 to 70 SMD CSTCE10M0G55-R0 (33) (33) LEAD CSTLS10M0G56-B0 (47) (47) SMD CSTCE12M0G55-R0 (33) (33) SMD CSTCE16M0V51-R0 (5) (5) LEAD CSTLS16M0X51-B0 (5) (5) SMD CSTCE20M0V51-R0 (5) (5) CSTCG20M0V51-R0 (5) (5) CSTCG24M0V51-R0 (5) (5) Mini SMD 24.000 conditions Type Recommended resonator [MHZ] 10.000 Recommended operating Recommended constants Oscillation Mini SMD Note 1: Constants C1 and C2 indicates values for the built-in load capacitance type. Note 2: The part numbers and specifications of Murata's products are updated as occasion requires. For details, please check the website of Murata. http://www.murata.com. Note 3: When the ceramic resonator is used for high-frequency oscillator circuit, USB device controller requires using the clock in high precision. In this case, the clock of X1USB pin should be used the clock precision is 24MHz 100ppm. TMPA910CRA- 906 2010-06-02 TMPA910CRA (3) Recommended crystal high-frequency resonator: KYOCERA KINSEKI Corporation The table below shows the recommended circuit constants of the high-frequency oscillation circuit. Oscillation MCU frequency [MHz] TMPA910CRAXBG 24.000 Recommended constants Recommended resonator CX2520SB Recommended operating conditions C1 C2 Rd Rf Power supply Temperature [pF] [pF] [] [] voltage range [V] range [C] 3 3 0 Open 1.4 to 1.6 0 to 70 (4) Recommended crystal low-frequency resonator: KYOCERA KINSEKI Corporation The table below shows the recommended circuit constants of the low-frequency oscillation circuit. Oscillation MCU frequency [kHz] TMPA910CRAXBG 32.768 Recommended constants Recommended resonator ST-4115B Recommended operating conditions C1 C2 Rd Rf Power supply Temperature [pF] [pF] [] [] voltage range [V] range [C] 8 8 470 Open 3.0 to 3.6 0 to 70 Note: The part numbers and specifications of KYOCERA KINSEKI's products are updated as occasion requires. For details, please check the website of KYOCERA KINSEKI. http://www.kinseki.co.jp/. TMPA910CRA- 907 2010-06-02 TMPA910CRA 5. Package Dimensions Package name: P-FBGA361-1616-0.80AZ Unit: mm TMPA910CRA- 908 2010-06-02 TMPA910CRA RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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Product and related software and technology may be controlled under the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. * Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. TMPA910CRA- 909 2010-06-02