February 2000 - Linear Technology

LINEAR TECHNOLOGY

FEBRUARY 2000 VOLUME X NUMBER 1

1- and 2-Channel,

No Latency ∆Σ∆Σ

∆Σ∆Σ

∆Σ, 24-Bit

ADCs Easily Digitize

a Variety of Sensors

by Michael K. Mayes

and Derek Redmayne

Introduction

Since its introduction, the LTC2400’s

performance and ease-of-use have

transformed the method of designing

analog-to-digital converters into a

variety of systems. Some key features

that separate the LTC2400 from con-

ventional high-resolution ADCs and

enable direct digitization of many sen-

sors include:

❏Ultralow offset (1ppm), offset

drift (0.01ppm/°C), full-scale

error (4ppm) and full-scale drift

error (0.02ppm/°C) without user

calibration

❏Absolute accuracy typically less

than 10ppm total (linearity +

offset + full-scale + noise) over

the full operating temperature

range

❏Ease-of-use (eight pins, no

conﬁguration registers, internal

oscillator and latency-free

conversion)

❏Low noise and wide dynamic

range (0.3ppm

RMS

with V

REF

= 5V—21.6 effective bits of

resolution)

This article introduces two new

products based on the technology

used in the LTC2400. Both parts come

in tiny 10-pin MSOP packages. They

include full-scale and zero-scale set

inputs for removing systematic offset/

full-scale error. The LTC2401 is a

single-ended 1-channel device. The

LTC2402 is a 2-channel device with

automatic ping-pong channel

selection.

The absolute accuracy and near

zero drift of these devices enable many

novel applications, of which four are

presented here. The ﬁrst application

uses the full-scale and zero-scale set

inputs of the 1-channel device

(LTC2401) to digitize a half-bridge

sensor. The second is a thermocouple

digitizer with a digital cold-junction

compensation scheme using the

automatic ping-pong channel selec-

tion of the LTC2402 for simpliﬁed

optocoupled isolation. The third com-

bines the LTC2402’s ping-pong

channel selection, absolute accuracy

and excellent rejection into a pseudo-

differential bridge digitizer. The ﬁnal

application uses the LTC2402 to digi-

tize an RTD temperature sensor and

remove voltage drop errors due to

long leads using the second channel

and underrange capabilities.

, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,

FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, Multi-Mode Dimming, No Latency ∆Σ, No R

SENSE

Operational Filter, OPTI-LOOP, Over-The-Top, PolyPhase, PowerSOT, SwitcherCAD and UltraFast are trademarks of

Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the

products.

continued on page 3

IN THIS ISSUE…

COVER ARTICLE

1- and 2-Channel, No Latency

∆Σ

24-Bit ADCs Easily Digitize a

Variety of Sensors .....................1

Michael K. Mayes and Derek Redmayne

Issue Highlights ....................... 2

LTC® in the News… ....................2

DESIGN FEATURES

Tiny SOT-23 Step-Down Regulator

Switches at 1MHz for Space-

Critical Applications .................5

Damon Lee

A Quiescent Current Step-Down

Regulator Extends Standby Time

in Handheld Electronics ............8

Greg Dittmer

Beware: Worst-Case Speciﬁcations

Can Be a Reality ..................... 10

Steve Hobrecht

400MHz Current Feedback Amps

Offer High Slew Rate without the

Gain Bandwidth Product

Limitations of Voltage

Feedback Amps....................... 12

Brian Hamilton

Tiny 12-Bit ADC Delivers 2.2Msps

Through 3-Wire Serial Interface

............................................... 15

Joe Sousa

DESIGN IDEAS

LTC1645/LTC1735 Circuit Solves

PCI Power Problem .................. 20

Ajmal Godil

Active Voltage Positioning Saves

Output Capacitors in Portable

Computer Applications ............23

John Seago and Ajmal Godil

ADSL Line Driver/Receiver

Design Guide, Part 1 ............... 26

Tim Regan

DESIGN INFORMATION ....... 32–35

(complete list on page 32)

New Device Cameos ..................36

Design Tools ............................39

Sales Offices ............................40

Linear Technology Magazine • February 2000

EDITOR’S PAGE

Issue Highlights

Happy Y2K and welcome to the

tenth year of Linear Technology maga-

zine. Did any of your analog circuits

shut down at 12:01 on January first?

Our cover article for this issue

introduces two new No Latency ∆Σ

ADCs, the LTC2401 and the LTC2402,

based on the technology of the

LTC2400 (see Linear Technology

VIII:4, November 1998). Both come

in 10-pin MSOP packages and include

full-scale and zero-scale set inputs for

removing offset/full-scale error. The

LTC2401 is a single-ended 1-channel

device. The LTC2402 is a 2-channel

device with automatic ping-pong

channel selection. Both feature ultra-

low offset, offset drift, full-scale error

and full-scale drift; absolute accuracy

typically less than 10ppm; low noise

and wide dynamic range.

This issue also debuts another new

ADC: the LTC1402 12-bit serial ADC

has a full conversion speed of 2.2Msps

and a very compact 3-wire interface

for connecting to DSPs and micropro-

cessors without glue logic. Its

minuscule 16-pin narrow SSOP pack-

age and compact serial interface ﬁt

close to sensors for optimum analog

signal integrity. The LTC1402 cap-

tures fast steps from an external

analog input multiplexer for high

speed data acquisition and digitizes

high frequency signals very accu-

rately, with a 72dB S/(N+D) at

1.1MHz, for communications or sig-

nal processing systems.

Also revealed in these pages are

three new power devices: the

LTC1701, the LTC1708-PG and the

LTC1771. LTC1701 is a 5-lead SOT-

23, step-down, current mode, DC/

DC converter for low- to medium-

power applications. It operates from a

2.5V to 5.5V input voltage and

switches at 1MHz. The high switching

frequency allows the use of tiny, low

cost capacitors and inductors. Com-

bined with the tiny SOT-23, the area

consumed by the complete DC/DC

converter can be less than 0.3in

The LTC1708-PG is LTC’s newest

PolyPhase™ DC/DC controller. It

includes a dual, synchronous, cur-

rent mode controller, VID voltage

programming and a power-good func-

tion, for a compact CPU power supply

solution. The turn-on timing of the

top MOSFETs is interleaved for the

two controllers, reducing the input

RMS current and hence the input

capacitance requirement. OPTI-

LOOP™ compensation and Burst

Mode™ operation reduce the output

capacitance requirement.

The LTC1771 is a step-down con-

troller that drives an external

P-channel MOSFET for output loads

up to 5A. Its low quiescent current

and ﬂexible operation with a wide

range of output loads allow it to main-

tain high efﬁciency for over four

decades of operating current. Wide

supply range and 100% duty cycle for

low dropout allow maximum energy

to be extracted from the battery, while

current mode operation gives excel-

lent transient response and start-up

behavior. The LTC1771 also features

short-circuit protection, micropower

shutdown to 2µA and a Burst Mode

disable pin for low noise applications.

In the signal condition arena, we

introduce a new family of amplifiers:

the LT1395, LT1396 and LT1397 are

400MHz current feedback ampliﬁers

with a high slew rate and a –3dB

bandwidth that remains relatively

constant over a wide range of open-

loop gains. The current feedback

topology of the these parts can pro-

vide improved performance in many

designs that have historically used

voltage feedback op amps. Because of

their current feedback topology, they

have a slew rate of 800V/µs on a

supply current of only 4.6mA per

ampliﬁer, resulting in a much higher

full-power bandwidth than compa-

rable voltage feedback op amps.

This issue features three design

ideas: a Hot Swap circuit that selects

between 3.3V and 5V inputs and pro-

vides a regulated 3.3V/3A supply; a

discussion of the “active voltage po-

sitioning” technique, which reduces

the need for output capacitors when

used in conjunction with selected LTC

switching controllers; and part one of

a 2-part series on ADSL driver/receiver

design. Our Design Information sec-

tion includes data on three new parts:

the LTC1565-31 7th order, linear

phase lowpass filter, the LTC1546

multiprotocol serial transceiver and

the LTC2050 zero-drift operational

amplifier. The issue concludes with

eight new device cameos.

LTC in the News…

On January 18, Linear Technology

announced its financial results for the

second quarter of fiscal year 2000.

Robert H. Swanson, Chairman and

CEO, stated, “This was a very strong

quarter for us as we achieved record

levels of bookings, sales and profits,

with sales increasing 10% and profits

11% sequentially from the September

quarter. Demand from our customers

escalated throughout the quarter and

increased in all major geographical

areas and all major end markets. Given

this positive business climate, we

expect the upcoming March quarter to

have continuing sequential sales and

profit growth.” The Company reported

sales of $162,294,000 and net income

of $64,951,000 compared with

$45,904,000 a year ago. Net sales

were up 35% over last year.

Also, LTC announced a two-for-one

stock split for shareholders of record

on March 6, 2000. Certificates will be

distributed on March 27, 2000. The

split will increase the number of shares

of common stock outstanding from

approximately 160,000,000 to

320,000,000. According to Robert H.

Swanson, Chairman and CEO, “the

Board of Directors authorized the stock

split with the intention of benefiting

the shareholders by obtaining wider

distribution and improving the mar-

ketability of the common stock.”

The Company was featured by

Investor’s Business Daily in an article

entitled “Linear Carves Out Unique

Niche In Analog Semiconductor Field.”

Reporter Alan Elliott states, “Give some

guys a niche and they’ll take a mile.”

The article points out, “When Linear

Technology took its first steps, analog

was almost a nasty word. Digital chips

were the wave of the future and analog

seemed set to go the way of the buggy

whip.”

Linear Technology Magazine • February 2000

DESIGN FEATURES

Single-Ended Half-Bridge

Digitizer with Reference

and Ground Sensing

Sensors convert real world phenom-

ena (temperature, pressure, gas levels

and others) into voltages. Typically,

the voltage is generated by passing an

excitation current through the sen-

sor. This excitation current also ﬂows

through wiring parasitics R

and R

(see Figure 1). The voltage drop across

these parasitic resistances leads to

systematic offset and full-scale errors.

In order to eliminate the errors

associated with these parasitic resis-

tances, the LTC2401/LTC2402

include a full-scale set input (FS

SET

)

and a zero-scale set input (ZS

SET

). As

shown in Figure 2, the FS

SET

pin acts

as a full-scale sense input. Errors

due to parasitic resistance R

in series

with the half-bridge sensor are

removed by the FS

SET

input to the

ADC. The absolute full-scale output

of the ADC (data out = FFFFFF

HEX

)

will occur at V

= V

= FS

SET

(see

Figure 3). Similarly, the offset errors

due to R

are removed by the ground

sense input, ZS

SET

. The absolute zero

output of the ADC (data out =

000000

HEX

) occurs at V

= V

= ZS

␣ SET

Parasitic resistances R

–R

have

negligible errors due to the 1nA (typ)

leakage current at pins FS

SET,

SET

and V

. The wide dynamic input range

(–300mV to 5.3V) and low noise

(0.6ppm

RMS

) enable the LTC2401 to

directly digitize the output of a bridge

sensor.

Digital Cold-Junction

Compensation

In order to measure absolute tem-

perature with a thermocouple,

cold-junction compensation must be

performed. The LTC2402 enables

simple digital cold-junction compen-

sation. One channel measures the

output of the thermocouple while the

other measures the output of the

cold-junction sensor—diode, ther-

mistor or the like (see Figure 4).

The selection between CH0 (the

thermocouple) and CH1 (the cold junc-

tion) is automatic. The LTC2402

alternates conversions between the

two input channels and outputs a bit

corresponding to the selected channel

in the data output word. This simpli-

ﬁes the user interface by eliminating

a channel-select input pin. As a result,

the LTC2402 is ideal for systems that

perform isolated measurements; it

only requires two optoisolators (one

for serial data out and one for the

serial data output clock).

Alternating conversions between

two input channels is difﬁcult with

conventional ∆Σ ADCs. These devices

require 3–5 conversion cycle settling

every time the input channel is

switched. On the other hand, the

LTC24xx family uses a completely

different architecture than other ∆Σ

converters. This results in latency-

free, single-cycle settling. The

LTC2402 enables continuous con-

version between two alternating

channels without the added complex-

ity associated with conventional ∆Σ

converters.

Pseudodifferential

Applications

Generally, system designers choose

fully differential topologies for several

reasons. First, the interface to a 4- or

6-wire bridge is simple (it has a differ-

ential output). Second, good rejection

of line frequency noise is required.

Third, the output of the sensor is

typically a small differential signal

sitting on a large common mode

voltage; as a result, accurate mea-

surements of the differential signal

independent of the common mode

input voltage is needed. Many

applications currently using fully dif-

ferential analog-to-digital converters

for any of the above reasons can

migrate to a pseudodifferential

conversion using the LTC2402.

SENSOR

FULL-SCALE ERROR

OFFSET ERROR

EXCITATION

–

SENSOR

OUTPUT

–

EXCITATION

SET

GND

LTC2401

SCK

SDO

3-WIRE

SPI

= 0

VIN

ADC DATA OUT

00000H

FFFFFH

ZSSET FSSET

SET

CH1

CH0

SET

GND

LTC2402

SCK

SDO

PROCESSOR

THERMOCOUPLE

COLD JUNCTION

THERMISTOR/DIODE

ISOLATION BARRIER

Figure 1. Errors due to excitation currents

Figure 2. Half-bridge digitizer with zero-scale

and full-scale sense

Figure 3. Transfer curve with zero-scale and

full-scale set

Figure 4. Digital cold-junction compensation

LTC2401/LTC2402, continued from page 1

Linear Technology Magazine • February 2000

DESIGN FEATURES

Direct Connection

to a Full Bridge

The LTC2402 interfaces directly to a

4- or 6-wire bridge (see Figure 5). Like

the LTC2401, the LTC2402 includes

SET

and ZS

SET

pins for sensing the

excitation voltage directly across the

bridge. This eliminates errors due to

excitation currents ﬂowing through

parasitic resistances (R

–R

). The

LTC2402 also includes two single-

ended input channels that can be tied

directly to the differential output of

the bridge. The two conversion results

can be digitally subtracted, yielding

the differential result.

Noise Rejection

The LTC2402’s single-ended rejec-

tion of line frequencies (50Hz/60Hz

±2%) and their harmonics is better

than 110dB. Since the device per-

forms two independent single-ended

conversions, each with >110dB rejec-

tion, the overall common mode and

differential rejection is much better

than the 80dB rejection typically

found in other differential ∆Σ

converters.

In addition to excellent rejection of

line frequency interference, the

LTC2402 also exhibits excellent

single-ended noise rejection of a wide

range of frequencies due to its 4th

order sinc ﬁlter (see Figure 6). Each

single-ended conversion indepen-

dently rejects high frequency noise

(>60Hz). Care must be taken to ensure

that noise at frequencies below 15Hz

and at multiples of the ADC sample

rate (15.6kHz) are not present. For

this application, it is recommended

that the LTC2402 be placed in close

proximity to the bridge sensor in order

to reduce the noise applied to the

ADC input. By performing three suc-

cessive conversions (CH0–CH1–CH0)

the drift and low frequency noise can

be measured and compensated

digitally.

Small Differential

Signals Sitting on Large

Common Mode Voltages

The absolute accuracy (<10ppm total

error) of the LTC2402 enables

extremely accurate measurement of

small signals sitting on large voltages.

Each of the two pseudodifferential

measurements performed by the

LTC2402 is absolutely accurate

independent of the common mode

voltage output from the bridge. The

pseudodifferential result obtained

from digitally subtracting the two

single-ended conversion results is

accurate to within the noise level of

the device times the square root of 2

(3µV

RMS

• √2), independent of the

common mode input voltage.

Typically, bridge sensors output

2mV/V full scale. With a 5V excita-

tion this translates to a full-scale

output of 10mV. Divided by the RMS

noise of the LTC2402, this circuit

yields 2357 counts with no averaging

or ampliﬁcation. If more counts are

required, several conversions may be

averaged. The number of effective

counts is increased by √2 for each

doubling of averages. For example, to

achieve 10,000 counts sixteen read-

ings should be averaged.

In order to achieve more counts, an

LT1126 low noise dual op amp can be

placed in front of the LTC2402, see

Figure 7. The noise performance of

this device is 2.6nV/√Hz. With a gain

of 100, the input-referred noise con-

tribution of the LTC2402 is less than

50nV

RMS

SET

CH1

SET

CH0

GND

LTC2402

SCK

SDO

3-WIRE

SPI

350Ω

×4

EXCITATION

= 0

INPUT FREQUENCY (Hz)

REJECTION (dB)

–20

–40

–60

–80

–100

–120

60 120 180 240 300 420 480 540360

Figure 5. Pseudodifferential strain gauge

application

Figure 6. Single-ended LTC2401/LTC2402

input rejection

SET

CH1

CH0

SET

GND

LTC2402

SCK

SDO

3-WIRE

SPI

350Ω

350Ω350Ω

350Ω

EXCITATION

= 0

–

1/2 LT1126

10k

200Ω

Figure 7. 100,000 count pseudodifferential strain gauge application

continued on page 19

Linear Technology Magazine • February 2000

DESIGN FEATURES

Tiny SOT-23 Step-Down Regulator

Switches at 1MHz for Space-Critical

Applications by Damon Lee

Introduction

As portable devices continue to shrink,

the need for progressively smaller

components increases. To use smaller

capacitors and inductors, switching

regulators need to run at ever higher

frequencies in ever smaller packages.

To help meet this growing demand,

Linear Technology introduces the

LTC1701 5-lead SOT-23, step-down,

current mode, DC/DC converter.

Intended for low- to medium-power

applications, it operates from a 2.5V

to 5.5V input voltage and switches at

1MHz. The high switching frequency

allows the use of tiny, low cost capaci-

tors and inductors, which can be

2mm in height or less. Combined

with the tiny SOT-23, the area con-

sumed by the complete DC/DC

converter can be less than 0.3in

, as

shown in Figure␣ 1.

The output voltage is adjustable

from 1.25V to 5V. The LTC1701 can

also be used as a zeta converter for

battery-powered applications. A built-

in 0.28Ω switch allows up to 500mA

of output current at high efﬁciency.

OPTI-LOOP compensation allows the

transient response to be optimized

over a wide range of loads and output

capacitors.

The LTC1701 incorporates a

current mode, constant-off-time

architecture and includes automatic,

power saving Burst Mode operation

to reduce gate charge losses at low

load currents. With no load, the con-

verter draws only 135µA; in shutdown,

it draws less than 1µA, making it

ideal for battery-powered applications.

In dropout, the internal P-channel

MOSFET switch is turned on con-

tinuously, maximizing the usable

battery life.

High Efﬁciency 2.5V

Step-Down DC/DC Converter

A typical application for the LTC1701

is a 2.5V step-down converter, as

shown in Figure 2. This circuit con-

verts a 2.5V to 5.5V input supply to a

regulated 2.5V output supply at up to

500mA. The efﬁciency peaks at 94%

with a 3.3V input supply, as shown in

Figure 3. The graphs show an

improvement in efﬁciency above

100mA, where Burst Mode operation

is disabled. Burst Mode operation

provides better efﬁciency at lower

currents by producing a single pulse

or a group of pulses that are repeated

2.5V–5.5V

10µF

6.3V

5.1k

121k

L1 4.7µH

47µF

OUT

2.5V/0.5A

/RUN

GND

LTC1701

L1:

C1:

C2:

D1:

SUMIDA CD43-R47 (847) 956-0667

TAIYO YUDEN JMK316BJ106ML (408) 573-4150

SANYO POSCAP 6TPA47M (619) 661-6835

ON MBRM120L (800) 282-9855

330pF

100

1 10 100 1000

LOAD CURRENT (mA)

EFFICIENCY (%)

= 3.3V

= 5.0V

OUT

= 2.5V

Figure 1. LTC1701 evaluation circuit

Figure 2. High efﬁciency 2.5V/500mA step-down regulator

Figure 3. Efﬁciency of Figure 2’s circuit

Linear Technology Magazine • February 2000

DESIGN FEATURES

periodically, as shown in Figure 4. By

switching intermittently, the switch-

ing losses, which are dominated by

the gate-charge losses of the power

MOSFET, are minimized.

Start-up waveforms from a 3.3V

input into a 6Ω load are pictured in

Figure 5. The converter reaches regu-

lation in approximately 200µs,

depending on the load. Soft-start can

be implemented by ramping the volt-

age on the I

/RUN pin, which

requires only an RC delay with a

small Schottky diode, as shown in

Figure 6.

Single-Cell Li-Ion to

3.3V Zeta Converter

Some designs need the ability to main-

tain a regulated output voltage while

the input voltage may be either above

or below the desired output. When

the input is above the output, the

circuit must behave like a buck regu-

lator; when the input is below the

output, it must behave like a boost

regulator. The circuit conﬁguration

OUT

50mV/DIV

200mA/DIV

known as a zeta converter is a very

simple design that can meet this

requirement.

A single lithium-ion battery is a

popular choice for many portable

applications due to its light weight

and high energy density, but it has a

cell voltage that ranges from 4.2V to

2.5V. Thus, a simple buck or boost

topology cannot be used to provide a

3.3V output voltage.

In Figure 7, the LTC1701 is used in

a zeta conﬁguration to supply a con-

stant 3.3V with over 200mA of load

current. The circuit uses a single,

dual-winding inductor (a 1:1 trans-

former) for better performance,

although two separate inductors can

also be used with somewhat lower

efﬁciency. The components shown in

the schematic result in a 3mm high

converter, suitable for portable

applications.

As can be seen in Figure 8, the

overall efﬁciency does not vary much

with supply voltage variations, except

at high currents (over 100mA). This

can be attributed to the dominance of

switching losses across most of the

current range. Since Li-Ion batteries

spend most of their lives with a cell

voltage in the 3.6V–4.0V range, the

typical efﬁciency is about 81%.

2mm High, 1.5V Converter

In many applications, the height con-

straint can be more of a concern than

the area constraint. Small, low proﬁle

inductors and capacitors can be used

with the LTC1701, due to the high

switching frequency of 1MHz. In Fig-

ure 9, a circuit is shown that uses low

proﬁle components to produce a 2mm

VOUT

1V/DIV

ITH/RUN

2V/DIV

IL1

500mA/DIV

RUN C1

ITH/RUN

VIN

2.5V–4.2V

22µF

6.3V

5.1k

20.5k

34k

L1 4.7µH

22µF

6.3V

VOUT

3.3V

VIN

ITH/RUN

VFB

GND

LTC1701

330pF

Li-Ion

1µFL2

4.7µH

C6 4.7µF

C1,C2:

C6:

L1, L2:

D1:

AVX TAJA226M006R (207) 282-5111

TAIYO YUDEN JMK212BJ475MG (408) 573-4150

SUMIDA CLQ72 SERIES (847) 956-0667

ON MBR0520L (800) 282-9855

1 10 100 1000

LOAD CURRENT (mA)

EFFICIENCY (%)

OUT

= 3.3V

= 2.5V

= 3.0V

3.5V

= 4.0V

Figure 4. Example of Burst Mode operation Figure 5. Start-up with 3.3V input into a 6Ω load

Figure 6. Soft-start hookup

Figure 7. Single-cell Li-Ion to 3.3V zeta converter Figure 8. Efﬁciency of Figure 7’s circuit

Linear Technology Magazine • February 2000

DESIGN FEATURES

high (nominal), 1.5V step-down con-

verter that occupies less than 0.3in

The photograph in Figure 1 shows an

example of a layout with these com-

ponents. The efﬁciency, shown in

Figure 10, peaks at 88%. As can be

seen, the overall efﬁciency tends to

degrade with a larger V

-to-V

OUT

ratio,

which is typical for step-down

regulators.

2.5V Converter with

All Ceramic Capacitors

The low cost and low ESR of ceramic

capacitors make them a very attrac-

tive choice for use in switching

regulators. Unfortunately, the ESR is

so low that loop stability problems

may result. Solid tantalum capacitor

ESR generates a loop “zero” at 5kHz

to 50kHz that is instrumental in pro-

viding acceptable loop phase margin.

Ceramic capacitors remain capaci-

2.5V–5.5V

15µF

10V

5.1k

100k

20k

L1 4.7µHV

OUT

1.5V/0.5A

/RUN

GND

LTC1701 C2

22µF

6.3V

4.7µF

330pF

1µF

C1:

C2:

C4:

C5:

L1:

D1:

AVX TAJA156M010R

AVX TAJA226M006R (803) 946-0524

TAIYO YUDEN LMK212BJ105MG (408) 573-4150

TAIYO YUDEN JMK212BJ475MG

MURATA LQH3C4R7M24 (814) 237-1431

ON MBRM120L (800) 282-9855

tive to beyond 300kHz and usually

resonate with their ESL before ESR

damping becomes effective. Also,

ceramic caps are prone to tempera-

ture effects, which require the designer

to check loop stability over the full

operating temperature range.

For these reasons, great care must

be taken when using only ceramic

input and output capacitors. The

OPTI-LOOP compensation compo-

nents can be adjusted when ceramic

capacitors are used. For a detailed

explanation of optimizing the com-

pensation components, refer to LTC

Application Note 76. Figure 11 shows

one example of an all-ceramic-capaci-

tor circuit; its efﬁciency graph is shown

in Figure 12. The efﬁciency in this

case has a very ﬂat peak at 93% due

to the relatively low output capaci-

tance and the low ESR of the ceramic

capacitors.

50 1 10 100 1000

LOAD CURRENT (mA)

EFFICIENCY (%)

VOUT = 1.5V

VIN = 2.5V

VIN = 3.3V

VIN = 5.0V

2.5V–5.5V

10µF

6.3V

5.1k

121k

L1 4.7µHV

OUT

2.5V/0.5A

/RUN

GND

LTC1701 C2

10µF

6.3V

1µF

10V

180pF

1µF

10V C6

33pF

C1, C2:

C4, C5:

L1:

D1:

TAIYO YUDEN JMK316BJ106ML (408) 573-4150

TAIYO YUDEN LMK212BJ105MG

MURATA LQH3C4R7M24 (814) 237-1431

ON MBRM120L (800) 282-9855

100

50 1 10 100 1000

LOAD CURRENT (mA)

EFFICIENCY (%)

VOUT = 2.5V

VIN = 3.0V

VIN = 5.0V

Conclusion

The LTC1701 is a small, monolithic,

step-down regulator that switches at

high frequencies, allowing the use of

tiny, low cost capacitors and induc-

tors for a cost- and space-saving DC/

DC converter. Although the LTC1701

was designed for basic buck applica-

tions, the architecture is versatile

enough to produce an effective zeta

converter, due in part to its power

saving Burst Mode operation and its

optimized OPTI-LOOP compensation.

By combining a high switching fre-

quency and an onboard P-channel

MOSFET in a tiny SOT-23 package,

the LTC1701 is ideal for space-criti-

cal portable applications.

Figure 9. 2mm high 1.5V converter

Figure 10. Efﬁciency of Figure 9’s circuit

Figure 11. All-ceramic-capacitor converter delivers 2.5V at 500mA.

Figure 12. Efﬁciency of Figure 11’s circuit

Linear Technology Magazine • February 2000

DESIGN FEATURES

10µA Quiescent Current Step-Down

Regulator Extends Standby Time

in Handheld Electronics by Greg Dittmer

Introduction

Many handheld products on the mar-

ket today are used only occasionally

but must be kept alive and ready all

the time. When not being used, the

circuitry is powered down to save

battery energy, with a minimum

amount of circuitry remaining on.

Although the supply current is sig-

niﬁcantly reduced in this low power

standby mode, the battery energy will

still be slowly depleted to power the

keep-alive circuitry and the regula-

tor. If the device spends most of its

time in this standby mode, the quies-

cent current of the regulator can have

a signiﬁcant effect on the life of the

battery (see Figure 1). To maximize

the life of the battery in these types of

products, Linear Technology has

extended its family of low quiescent

current step-down converters. The

LTC1474/LTC1475 series broke new

ground a few years ago by providing a

monolithic step-down regulator that

requires only 10µA of supply current

to regulate its output voltage at no

load while maintaining high efﬁciency

at loads up to 300mA. Now, two new

products provide solutions for appli-

cations requiring higher output

currents or constant-frequency

operation at a higher switching fre-

quency while still operating on the

ultralow 10µA no-load supply cur-

rent. The new LTC1771 is a constant

off-time controller for up to 5A of

output current with the addition of an

appropriately sized external P-chan-

nel FET. A second product, soon to be

released, is a monolithic regulator

that provides constant frequency

(550kHz) plus synchronous opera-

tion at up to 500mA of output current.

LTC1771 Controller for

Output Loads to 5A

The LTC1771 is a step-down control-

ler that drives an external P-channel

MOSFET for output loads up to 5A.

Its low quiescent current and ﬂexible

operation with a wide range of output

loads allow the LTC1771 to maintain

high efﬁciency for over four decades

of operating current. Wide supply

range (2.8V–18V) and 100% duty cycle

for low dropout allow maximum en-

ergy to be extracted from the battery,

while current mode operation gives

excellent transient response and start-

up behavior. LTC1771 also features

short-circuit protection (the maximum

current is programmable with an ex-

ternal sense resistor), micropower

shutdown to 2µA and a Burst Mode

disable pin for low noise applications.

The LTC1771 uses a constant off-

time, current mode architecture to

regulate its output voltage. During

normal operation, the P-channel

MOSFET is turned on at the begin-

ning of each cycle, causing current to

ramp up in the inductor and sense

resistor. When the sensed current

reaches the current comparator

threshold, the current comparator

trips and triggers a 1-shot timer that

turns off the MOSFET for 3.5µs. At

the end of this period, the MOSFET is

turned back on and the cycle is

repeated. The peak inductor current

at which the current comparator trips

is controlled by the voltage on pin 2

), the output of the error ampliﬁer.

An external resistor divider allows

the error ampliﬁer to receive an out-

put feedback voltage. When the load

current increases, it causes a slight

decrease in the feedback voltage,

which, in turn, causes the average

inductor current to increase until it

matches the new load current.

LOAD CURRENT (mA)

EFFICIENCY (%)

100

500.1 1 100 1000 10,000

1771 F01b

VIN = 5V

VIN = 10V

VIN = 15V

VOUT = 3.3V

RSENSE = 0.05Ω

400

300

200

100

01 10 100

MINUTES PER WEEK OF USE

BATTERY LIFE (DAYS)

LTC1771

CLOSEST COMPETITION

100

500.1 1.0 10 100 1000

LOAD CURRENT (mA)

EFFICIENCY (%)

VIN = 3.6V

VIN = 10V

VOUT = 2.5V

VIN = 5.0V

VIN = 7.2V

L = 10µH

Figure 1. 9V battery-life comparison for load

requiring 100mA normal and 100

A standby

current at 3.3V

Figure 2. LTC1771 efﬁciency vs load current

for Figure 5’s circuit Figure 3. Efﬁciency vs load current for a new

constant frequency monolithic regulator

Linear Technology Magazine • February 2000

DESIGN FEATURES

Burst Mode for Outstanding

Low Current Efﬁciency

The LTC1771 is able to maintain an

ultralow no-load supply current and

high efﬁciency at extremely light loads

by using Burst Mode operation. Burst

Mode operation commences when the

load, detected by a comparator moni-

toring the I

voltage, falls below about

20%–30% of the maximum load. Dur-

ing Burst Mode operation, short burst

cycles of normal switching to charge

the output capacitor alternate with

longer sleep periods when the switch

is turned off and the load current is

supplied by the output capacitor.

During this sleep period, only the

minimum required circuitry—the

reference voltage and the error ampli-

ﬁer—are left on. Supply current is

further reduced with innovative new

circuitry that allows the error ampli-

ﬁer to run on 10% of its normal

operating current during sleep mode

with no degradation in the transient

response, reducing the total supply

current to less than 10µA. At light

loads, the regulator spends most of

the time in this low quiescent current

sleep mode, minimizing supply cur-

rent and maximizing efﬁciency.

Burst Mode operation can be dis-

abled by pulling the Mode pin to

ground. Disabling Burst Mode opera-

tion allows the loads to decrease

another decade, to about 1%–2% of

maximum load, before the regulator

must skip cycles to maintain regula-

tion. Although less efﬁcient, disabling

Burst Mode operation is useful

because it reduces both audio and RF

interference by reducing voltage and

current ripple and by keeping operat-

ing frequency constant at lower output

currents.

Component Considerations

for Minimizing Supply

Current

No-load supply current for the

LTC1771 consists of the 10µA quies-

cent current of the IC plus a small

additional current to power the low

frequency burst cycles needed to

recharge the output capacitor. Even

at no load, the output capacitor is

slowly discharged due to leakage cur-

rents from the feedback resistors and

the Schottky diode. This leakage cur-

rent, though small, can be signiﬁcant

when the total supply current is only

10µA. The feedback resistor leakage

can be minimized by using resistors

in the megohm range. Care must be

used in selecting the Schottky diode

to minimize no-load supply current

without sacriﬁcing efﬁciency at higher

loads. Low leakage is critical for mini-

mizing no-load supply current;

however, forward voltage drop is criti-

cal for higher current efﬁciency

because loss is proportional to the

forward voltage drop. Unfortunately,

these are conﬂicting parameters (see

Figure 4) and the user will need to

weight the importance of each spec in

choosing the best diode for the appli-

cation.

3.3V/2A

Step-Down Regulator

A typical application circuit using the

LTC1771 is shown in Figure 5, with

the associated efﬁciency curves in

Figure 2. This circuit supplies a 2A

load at 3.3V with an input supply

range of 4.5V to 18V. The 0.05Ω sense

resistor sets the maximum output

current to just above 2A. The 15µH

inductor sets the inductor ripple cur-

rent at about 1A, and with the 0.05Ω

ESR of the output capacitor, results

in 50mV of output voltage ripple. Since

the LTC1771 gate drive pin swings

rail-to-rail, a MOSFET must be cho-

sen that can handle the full supply

voltage. The Si6447 P-Channel MOS-

FET is a good compromise between

low gate charge and R

DS(ON)

. Gate

charge affects efﬁciency at lighter

loads, whereas R

DS(ON)

affects the

efﬁciency at heavier loads. The 4.5V

minimum supply voltage is due to

minimum gate voltage required for

the Si6447. If the input supply is

limited to 12V or less, a 2.5V MOS-

FET, such as the Si3443, could be

used allowing the regulator to oper-

ate to lower supply voltages. The

Microsemi Powermite UPS5817

Schottky diode (617-926-0404) pro-

vides a good compromise between

reverse leakage and forward drop for

the 1A–2A range. The diode leakage

and the feedback resistors increase

the no-load supply current to about

12µA.

Conclusion

With Linear Technology’s growing

family of high performance 10µA

parts, the designers of handheld elec-

tronics now have a myriad of solutions

to optimize their designs without com-

promising the main goals of extending

1000

1000.1 1.0 10 100

LEAKAGE CURRENT (µA)

FORWARD DROP (mV)

MBR0540

MBRS120T3

MBR0520

MBRM120LT3

MBRS320

UPS5817

1A FORWARD CURRENT

3.3V REVERSE VOLTAGE

RUN/SS

4.5V TO 18V

10k

SENSE

0.05Ω

1.64M

Si6447DQ

UPS5817

15µH

22OpF

5pF

10µF

25V

CER

OUT

150µF

6.3V

OUT

3.3V

0.01µF

PGATE

MODE

LTC1771

GND

SENSE

Figure 4. Schottky diode parameter trade-off Figure 5. LTC1771 3.2V/2A regulator

continued on page 14

Linear Technology Magazine • February 2000

DESIGN FEATURES

Beware: Worst-Case Speciﬁcations

Can Be a Reality by Steve Hobrecht

Introduction

The design of portable electronic

devices always involves trade-offs

among cost, weight, size, speed, run-

time, features and reliability. It is

necessary to design the power supply

for worst-case conditions because the

software, which may or may not have

been written yet, may, in some situa-

tions, exercise the hardware to its

fullest potential. If typical operating

conditions are used to deﬁne the power

supply design requirements, hard-

ware reliability may depend upon the

particular software being used, either

in normal operation or when the soft-

ware is “acting up.”

In the case of a typical notebook

computer, the nominal 120mA I/O

current can rise to 2.5A for an inde-

terminate amount of time. The

software being executed is the deter-

mining factor. If a linear regulator is

used that is only capable of a lower

continuous current due to power dis-

sipation or maximum current limit, a

system crash or a hardware failure

may result when higher current is

required. Hidden costs for warranty

repair may result from running seem-

ingly innocuous code, posing a

long-term risk for the manufacturer.

A high efﬁciency, dual, current mode

controller can be substituted for the

single controller plus linear regulator

normally used in this application, to

provide a small, reliable, efﬁcient

solution. This will prevent the inevi-

table thermal problems associated

with the use of a linear regulator.

The application presented here pro-

vides a VID-controlled, 0.9V–2.0V,

15A CPU supply, 1.5V/2.5A I/O sup-

ply and 2.5V ±5%/150mA clock

supply. The power supply compo-

nents chosen meet the maximum

current speciﬁcations over the oper-

ating temperature and input voltage

range.

The LTC1708-PG is the newest

member of Linear Technology’s third

generation of PolyPhase DC/DC con-

trollers. This controller is similar to

the LTC1628 controller (see “A Third

Generation Dual, Opposing-Phase

Switching Regulator Controller,” Lin-

ear Technology IX:2 [June, 1999], pp.

16–20) but with the addition of 5-bit

VID output voltage control and a

power-good indicator.

Application Beneﬁts

The LTC1708-PG includes a dual,

synchronous, current mode control-

ler, VID output voltage programming

and a power-good function in a 28-pin

SSOP package, providing a compact

OUT

SENSE

BYP

GND

SHDN

STBYMD VID V

INTV

TG1

BOOST1

SW1

BG1

VID0–VID4

ATT

SENSE1

–

ATT

OUT

IN1

FCB

TH1

TG2

BOOST2

SW2

BG2

PGND

SENSE2

–

IN2

3.3V

OUT

EXTV

PGOOD

TH2

RUN/SS1 SGND RUN/SS2

0.1µFR

10Ω

510k

4.7µF

0.22µF

L1 1µH

5 VID BITS

1000pF

SENSE1

0.003Ω

CC1

0.1µF

6.3V

OUT1

0.925V–2.00V

100mA–15A

INTV

1000pF

MODE SELECT

VP1

160k

VP2

68k

47pF C

150pF

6.8k

SS1

0.1µF

OUT1

270µF/2V

× 3

7.5V–24V

10µF/35V

CERAMIC

×3

Q3a

Q3b D2

L2 2.2µH

1µF

0.1µF

1000pF

OUT2

1.5V

120mA–2.5A

OUT2

47µF/4V

SENSE2

0.02Ω

R4 17.5k 1%

R3 20k 1%

5V SYSTEM

SUPPLY INPUT

POWER GOOD

100k

220pF

15k

SS2

0.1µF

SYSTEM

SUPPLY

2.5V

ON/OFF

BYP

0.01µF

OUT3

10µF

OUT3

2.5V/150mA

LTC1708-PG

L1:

L2:

Q1:

Q2:

Q3a, Q3b:

D1:

D2:

D3, D4:

VISHAY 5050CE (408) 241-4588

MURATA LQN6C2R2 (814) 237-1431

INTERNATIONAL RECTIFIER IRF7811 (310) 322-3331

INTERNATIONAL RECTIFIER IRF7809

FAIRCHILD FDS8936A (408) 822-2126

MICROSEMI UPS840 (510) 353-0822

ON MBRM140T3 (800) 282-9855

CENTRAL CMDSH-3TR (516) 435-1110

LT1762-2.5

5V/50mA

1µF

Figure 1. LTC1708 microprocessor core, I/O and clock supply: 0.9V–2V/15A, 1.5V/120mA–2.5A and 2.5V/150mA with active voltage positioning

Linear Technology Magazine • February 2000

DESIGN FEATURES

CPU power supply solution. Internal

timing control interleaves the turn-

on timing of the top MOSFETs for the

two controllers, reducing the input

RMS current and hence the input

capacitance requirement. OPTI-LOOP

compensation and low current Burst

Mode operation reduce the output

capacitance requirement.

The 1%, 0.8V reference voltage pro-

vides output voltage accuracy along

with compatibility for future, lower

voltage microprocessor and ASIC

requirements. Load regulation is typi-

cally 0.1% and is compatible with

active voltage positioning techniques

(see “Active Voltage Positioning Saves

Output Capacitors in Portable Com-

puter Applications” on page 23 in this

issue). The device incorporates an

overvoltage “soft-latch” that protects

the load if power supply problems

develop but does not interfere or latch

off when extreme transient condi-

tions end. Internal foldback current

limiting eliminates the need to

overdesign the power components to

protect against short circuits; an over-

current shutdown can be enabled if

desired. These protection features

combine to make a very robust solu-

tion for long term reliability. The

operating modes provide a choice of

Burst Mode operation, constant-fre-

quency operation and PWM modes (in

order of decreasing efﬁciency) to sat-

isfy almost any application. The

constant frequency mode offers a low

noise solution that has high efﬁciency

due to discontinuous operation,

offering a solution for applications

requiring bursts of high current at an

audible rate. This technique reduces

or eliminates the audible noise ema-

nating from the gapped inductor that

is typically used. The fast response

time of the internal controller circuits

allows the controller to maintain its

operating frequency even with very

high input-to-output voltage ratios. A

5V and a 3.3V linear regulator are

provided to power ancillary functions.

2-Phase Operation

The LTC1708 dual, high efﬁciency

DC/DC controller brings the consid-

erable beneﬁts of 2-phase operation

to portable applications. Notebook

computers, PDAs, handheld termi-

nals and automotive electronics will

all beneﬁt from the lower input ﬁltering

requirement, reduced electromagnetic

interference (EMI) and increased efﬁ-

ciency associated with 2-phase

operation.

Application Circuit

Figure 1 shows a VID-controlled 0.9V

to 2.0V, 15A CPU supply, a 1.5V/

2.5A I/O supply and 2.5V ±5%/

150mA clock supply. The controller’s

and EXTV

pins should be con-

nected to a supply of at least 4.5V, as

speciﬁed by the MOSFET manufac-

turer, but the topside switching

MOSFET drains can be connected

independently to a 3.3V, 5V or 10V–

15V battery supply, or even a 24V

wall adapter if desired. The sche-

matic illustrates components selected

for a 7.5V to 24V input.

Transient Performance

The oscilloscope photo (Figure 2)

shows the switching power supply’s

high current output voltage response

to a load current step of 100mA to

15A in the constant frequency mode.

Figure 3 illustrates the overall efﬁ-

ciency for the three different operating

modes: Burst Mode operation, con-

stant-frequency operation and forced

continuous (PWM) mode for 100mA

to 15A.

Conclusion

A practical solution has been

presented that exceeds the mobile

CPU core, I/O and CLK speciﬁcations.

The circuit performs reliably under

the most adverse stimulus. The high

overall efﬁciency minimizes cooling

requirements as well.

The LTC1708 is just one member

of Linear Technology’s third gene-

ration family of constant frequency,

N-channel high efﬁciency controllers.

With PolyPhase timing control, VID

programming, overvoltage and

overcurrent protection features, OPTI-

LOOP compensation and strong

MOSFET drivers, the LTC1708 is a

very safe choice for CPU core and I/O

power applications.

100

00.1 1.0 10 100

IOUT (A)

EFFICIENCY (%)

Burst Mode

OPERATION

PWM MODE

15A

CONSTANT FREQUENCY

OPERATION

VIN = 15V

VOUT1 = 1.6V

OUT1

100mV/DIV

OUT1

5A/DIV

10µs/DIV

Figure 2. Output voltage response to a 100mA–15A load step

Figure 3. Efﬁciency vs output current of

Figure 1’s circuit for three operating modes

Linear Technology Magazine • February 2000

DESIGN FEATURES

400MHz Current Feedback Amps

Offer High Slew Rate without the Gain

Bandwidth Product Limitations of

Voltage Feedback Amps

by Brian Hamilton

Introduction

The LT1395, LT1396 and LT1397 are

400MHz current feedback ampliﬁers

with a high slew rate and a –3dB

bandwidth that remains relatively

constant over a wide range of closed-

loop gains. The current feedback

topology of the LT1395/LT1396/

LT1397 family can provide improved

performance in many new and exist-

ing designs that have historically used

voltage feedback op amps. Because of

its current feedback topology, the

LT1395/LT1396/LT1397 family

boasts a slew rate of 800V/µs on a

supply current of only 4.6mA per

ampliﬁer, resulting in a much higher

full-power bandwidth than compa-

rable voltage feedback op amps. The

current feedback topology of the

LT1395/LT1396/LT1397 also results

in additional design ﬂexibility because

the –3dB bandwidth remains relatively

constant regardless of closed-loop

gain. In contrast, the –3dB band-

width of voltage feedback op amps

decreases in proportion to the closed-

loop gain that has been chosen. For

example, a voltage feedback op amp

with a 400MHz gain bandwidth prod-

uct (GBW) will only have a 100MHz

bandwidth at a closed-loop gain of

four. At the same gain, the LT1395/

LT1396/LT1397 have a gain band-

width of about 240MHz. The parts

have industry-standard single, dual

and quad pinouts, allowing easy

upgrades of existing applications.

The LT1395/LT1396/

LT1397 Family

In addition to a 400MHz –3dB band-

width and an 800V/µs slew rate, the

LT1395/LT1396/LT1397 family has

exceptionally ﬂat frequency response.

Applications that require gain accu-

racy across a broad frequency range

will beneﬁt from the family’s ±0.1dB

bandwidth, which exceeds 100MHz.

For increased design ﬂexibility, the

LT1395/LT1396/LT1397 also boast

a very ﬂexible output stage. They have

over 80mA of output current drive

and, on ±5V supplies, they can swing

up to ±3.6V with a 150Ω load.

The LT1395/LT1396/LT1397

family’s wide supply voltage range

and versatile packaging options also

increase design ﬂexibility. Supplies

can range from a single 4V to ±6V. All

devices and package types are com-

patible with standard op amp pinouts.

In addition to standard SO packages,

the LT1396 and LT1397 are also avail-

able in smaller form factors. The

LT1396 is available in an 8-lead MSOP

package. The LT1397 is available in a

16-lead SSOP package that takes the

same amount of board space as an

SO-8. The LT1395 will be available in

SOT-23 soon.

A simpliﬁed schematic of a single

ampliﬁer from the LT1395/LT1396/

LT1397 family can be seen in Figure

1. Transistors Q1–Q7, J1 and R1

generate the necessary internal bias

currents, with Q6 and Q7 acting as

current sources for the input stage.

Transistors Q8–Q11 form the amp-

liﬁer’s input stage. Currents coming

from Q10 and Q11 are mirrored on

top and bottom by transistors Q12–

Q17. The collectors of transistors Q13

and Q15 drive the high impedance

node of the ampliﬁer. Transistors Q16

and Q17 act as current sources for

the output stage. Transistors Q18–

Q21 and resistors R2 and R3 form the

output stage.

It’s the Input Stage

The advantages of a current feedback

ampliﬁer (CFA) can be better under-

stood by examining the internal circuit

topology in greater detail. The

LT1395/LT1396/LT1397 input stage

reveals that the noninverting input

drives the bases of Q8 and Q9, result-

ing in a high impedance input. On the

other hand, the inverting input drives

the emitters of Q10 and Q11 and

results in a low impedance input; any

differential voltage imposed across

+IN –IN OUT

–

Q3 Q12

Q14Q5

Q10

Q11

Q13 Q16

Q18

HI-Z

Q15

Q19

Q17

Q20

Q21

Figure 1. LT1395/LT1396/LT1397 simpliﬁed schematic (one ampliﬁer)

Linear Technology Magazine • February 2000

DESIGN FEATURES

the inputs creates a current that ﬂows

into or out of the inverting input. This

current modulates the collector cur-

rents of Q10 and Q11, is mirrored on

top and on the bottom, and produces

a voltage swing at the high-imped-

ance node (and output) of the

ampliﬁer. Since the output voltage

swing is based upon the current ﬂow-

ing through the inverting input, the

gain of a current feedback ampliﬁer is

expressed as the ratio of output volt-

age change (dV) divided by inverting

input current change (dI

B–

) and is

referred to as the ampliﬁer’s trans-

impedance (Z

A conventional voltage feedback

input stage (Figure 2) is dramatically

different than the current feedback

input stage described above. The

inverting input of the voltage feed-

back input stage is a high impedance

input; thus, any feedback to this node

is in the form of a voltage. Since the

currents ﬂowing into or out of the

inverting input are small, the

maximum slew current at the high-

impedance node is derived from

internal currents only and has an

upper limit equal to the collector cur-

rent of Q3. In contrast, the slew

current in a CFA is not limited to

internal currents; it is provided

externally via the inverting input and

results in much higher slew rates

than those of conventional voltage

feedback op amps.

A CFA’s constant bandwidth over

closed-loop gain can be easily

explained if we derive equations for

closed-loop gain and closed-loop

bandwidth; we can then compare

them with the equations for a voltage

feedback op amp. Let’s start by com-

paring open-loop transfer functions

and open-loop gain:

A conventional voltage feedback op

amp has an open-loop gain A

that

deﬁnes the transfer function of the

ampliﬁer as follows:

VOUT = AJF • d(VIN) (1)

where d(V

) is the difference voltage

between the noninverting input and

the inverting input. Over frequency,

has a value at DC (A

) and a

dominant pole frequency (f

). The

open-loop response can be expressed

as:

AJF = A0/(1 + j(f/fa)) (2)

A current feedback ampliﬁer has

an open-loop transimpedance Z

that

deﬁnes the transfer function of the

ampliﬁer as follows:

VOUT = ZJF • IB– (3)

where I

B–

is the current ﬂowing out of

the inverting input. Over frequency,

has a value at DC (Z

) and a

dominant pole frequency (f

). The

open-loop response can be expressed

as:

ZJF = Z0 / (1 + j(f/fa)) (4)

If we take an ampliﬁer (either CFA

or voltage feedback) that has been

connected in a noninverting gain

topology (Figure 3), we can now deter-

mine the closed-loop transfer function

as follows:

For a voltage feedback ampliﬁer,

we can see from inspection of Figure

3 that

d(VIN) = VIN – VOUT • (RG/(RF + RG)) (5)

Combining equations 5, 1 and 2

(and assuming (1+ R

)/A

<< 1),

we get the closed-loop transfer

function:

VOUT/VIN = (1 + RF/RG)/(1 + j(f/fA)) (6)

where

fA = (A0 • fa)/(1 + RF/RG) (7)

is the closed-loop bandwidth.

For a current feedback ampliﬁer,

we know that the topology of the

input stage ensures that V

= V

With this in mind, we can see from

inspection of Figure 3 that

IB– = (VIN/RG) + ((VIN – VOUT)/ RF) (8)

Combining equations 8, 3 and 4

(and assuming R

<< 1) we get the

closed-loop transfer function:

VOUT/VIN = (1 + RF/RG)/(1 + j(f/fA)) (9)

where

fA = (Z0 • fa)/RF(10)

is the closed-loop bandwidth.

Looking at equations 6 and 9, we

can see that the closed-loop gain equa-

tions are identical for a voltage

feedback ampliﬁer and a CFA. How-

ever, the closed-loop bandwidths

(equations 7 and 10) are quite differ-

ent. As expected, the voltage feedback

ampliﬁer (equation 7) has a closed-

loop bandwidth that decreases with

increased closed-loop gain such that

their product is a constant.

The CFA has a closed-loop band-

width (equation 10) with some

interesting consequences. To be prop-

erly compensated, the CFA requires a

speciﬁc value of feedback resistor (R

)

between the inverting input and the

output. The value of R

can be

increased to improve stability (or lower

closed-loop bandwidth) in a variety of

applications, such as driving capaci-

tive loads. The requirement of a

resistor in the feedback path can pre-

clude CFAs from being drop-in

replacements for voltage feedback op

amps in some classes of circuits.

Active ﬁlters and integrators are good

examples of this class of circuit; their

implementation usually has capaci-

tors in the feedback network. Circuits

where the value of the feedback resis-

tance may change can also be

problematic for a CFA. There are often

alternative circuit topologies that

allow CFAs to be used in these appli-

cations. Many of these topologies are

+IN –IN

VEE

VBIAS

–

VIN

VOUT

Figure 2. Voltage feedback input stage

Figure 3. Noninverting gain topology

Linear Technology Magazine • February 2000

DESIGN FEATURES

discussed in the applications section

that follows.

The bandwidth (and compensation)

of a CFA is totally independent of R

As seen in equation 9, R

is only used

to set the closed-loop gain.

Application Circuits:

Comparing Voltage Feedback

and Current Feedback

As seen in Figure 4, it is very common

to limit the bandwidth of a conven-

tional voltage feedback ampliﬁer by

putting a small capacitor in parallel

with the feedback resistor, R

. This

technique does not work with current

feedback ampliﬁers because the

capacitor lowers the impedance seen

by the inverting input at high fre-

quencies. This results in reduced

phase margin, which eventually leads

to oscillation. To reduce the band-

width of an application circuit using

one of the LT1395/LT1396/LT1397

CFAs, simply increase the value of

the feedback resistor from the nominal

255Ω; this will lower the bandwidth

and increase stability. If the capacitor

was added to compensate for para-

sitic capacitance at the inverting

input, then increasing the feedback

resistor may not help. In this case, a

lowpass RC ﬁlter can be placed at the

noninverting input.

As seen in Figure 5, an integrator is

one of the easiest application circuits

to make with a conventional op amp.

The LT1395/LT1396/LT1397 CFAs

require a slight change to the conven-

tional topology to make sure that the

inverting input always sees a resis-

tance; simply add a resistor between

the inverting input and the other pas-

sive elements.

The summing ampliﬁer seen in Fig-

ure 6 has almost the same topology

for voltage feedback op amps and for

the LT1395/LT1396/LT1397 CFAs.

The voltage feedback op amp has a

series resistor added to the nonin-

verting input to cancel the effects of

bias current at the inverting and non-

–

VOLTAGE

FEEDBACK

OP AMP

LT1395

CFA

OUT

OP AMP BANDWIDTH LIMITING

CURRENT FEEDBACK AMP BANDWIDTH LIMITING

–

VOLTAGE

FEEDBACK

OP AMP

LT1395

CFA

OUT

OP AMP INTEGRATOR

CURRENT FEEDBACK AMP INTEGRATOR

255Ω

RG1

RG2

VIN1

VIN2 RF

–

VOLTAGE

FEEDBACK

OP AMP

LT1395

CFA

RG1

RG2

VOUT

VOLTAGE FEEDBACK AMPLIFIER SUMMER

CURRENT FEEDBACK AMPLIFIER SUMMER

VIN1

VIN2 RF

inverting inputs. The CFA design

eliminates the resistor at the nonin-

verting input because the inverting

bias current is uncorrelated with the

noninverting bias current. The addi-

tional resistor would not improve DC

accuracy.

Conclusion

With the introduction of the LT1395/

LT1396/LT1397 family of 400MHz

current feedback ampliﬁers, Linear

Technology offers design solutions

that are often superior to those using

conventional voltage feedback op

amps. High slew rate, consistent

closed-loop gain and a ﬂexible output

stage all merge in a family of ampliﬁ-

ers that are useful in a broad range of

applications.

Note:

The actual –3dB bandwidth of a CFA falls off

slightly with increased closed-loop gain. This

bandwidth reduction is caused by the nonzero

input impedance of the inverting input.

Figure 4. Bandwidth limiting Figure 5. Integrators Figure 6. DC-accurate summing

LTC1771, continued from page 9

standby time and maximizing battery

live. With these parts, the designer

has a choice of high or low input

voltage and monolithic or controller

conﬁgurations. The LTC1771 provides

a wide supply range up to 18V and

output currents up to 5A, whereas an

upcoming product gives you constant

frequency operation and loads of up

to 500mA without the need for an

external MOSFET and Schottky diode.

With both available in the MS8 pack-

age and requiring only 10µA of supply

current at no load, these products are

perfect solutions for handheld

electronics.

http://www.linear-tech.com/ezone/zone.html

Articles, Design Ideas, Tips from the Lab…

Linear Technology Magazine • February 2000

DESIGN FEATURES

Tiny 12-Bit ADC Delivers 2.2Msps

Through 3-Wire Serial Interface

by Joe Sousa

Introduction

Serial interfaces occupy little routing

space, but usually limit the speed of

an ADC. The LTC1402 has a full

conversion speed of 2.2Msps and a

very compact 3-wire interface for con-

necting to DSPs and microprocessors

without glue logic. It comes in a 16-pin

narrow SSOP package. This minus-

cule package (200mil × 230mil

footprint) and compact serial inter-

face are easy to ﬁt close to sensors to

best preserve analog signal integrity.

Other serial 12-bit ADCs have

sample rates limited to hundreds of

kilosamples-per-second, which limits

their utility in high speed data acqui-

sition systems. This slow sample rate,

combined with poor distortion char-

acteristics, makes them unsuitable

for tracking high frequency signals.

The LTC1402 will capture, in less

than 60ns, the fast steps from an

external analog input multiplexer for

high speed data acquisition and it will

digitize high frequency signals very

accurately, with a 72dB S/(N+D) (sig-

nal-to-noise plus distortion ratio) at

1.1MHz, for communications or sig-

nal processing systems.

3-Wire Serial Interface

for DSPs, Cables

and Optocouplers

Figure 1a shows an example of

interfacing the LTC1402 to the

TMS320C54x DSP. No glue logic is

needed to interface the LTC1402 to

DSPs. The buffered serial port of the

TMS320C54x talks directly to a dedi-

cated 2kB segment of internal buffer

memory. The ADC’s serial data is

collected in the 2k buffer, in two

alternating 1kB segments, in real

time, at the full 2.2Msps conversion

rate of the LTC1402. Consult the

LTC1402 data sheet for the

TMS320C54x assembly code for this

application.

3-WIRE SERIAL

INTERFACE LINK

CONV

SCK

LTC1402

OUT

OGND

CONV

CLK

TMS320C54X

BFSR

BCLKR

BDR

GND

Figure 1a. DSP serial interface to the TMS320C54X

SIGNAL

CONV

SCK

OUT

OGND

LTC1402

CONV

2.2Msps

CLK

35.2MHz

10µF

PIN 4 = ENA

PIN 12 = ENB

100Ω100Ω

100Ω

100Ω3

TMS320C54X

BFSR

BCLKR

BDR

CATEGORY FIVE

SHIELDED CABLE

UP TO 100 FEET

LTC1688

QUAD DRIVER LTC1520

QUAD RECEIVER

IN+

IN–

GND

Figure 1b. The LTC1402 3-wire serial port sends data over 100 feet of category 5 twisted pair

with the LTC1688/LTC1519 quad driver/receiver pairs

Linear Technology Magazine • February 2000

DESIGN FEATURES

SAMPLE-

AND-HOLD DOUT

BIP/UNI

CONV

SCK

OVDD

DVDD

AVDD

11211

GAIN 7

–5V OR 0V

10µF

VREF

4.096V

10µF64k

OUTPUT

BUFFER

2.048

REFERENCE TIMING

LOGIC

AIN+

LTC1402

OGND962 DGND

AIN–

5V 3V OR 5V

AGND1VSS

14 13AGND2

–

64k

12-BIT ADC

LTC1402

Figure 2. LTC1402 block diagram

The minuscule 16-pin narrow

SSOP package of the LTC1402 saves

space in compact systems or systems

that require a large number of ADCs.

It can be located near the signal con-

ditioning circuitry and send serial

output data over a PC board trace of

up to one foot in length to the DSP, as

shown in Figure 1a.

Figure 1b shows the LTC1688/

LTC1520 quad cable driver/receiver

interfacing the LTC1402 to the DSP

port to send the serial data over longer

distances. The category-5 quad

twisted pair shielded cable can extend

up to 100 feet without data corrup-

tion. Because the SCK, CONV and

OUT

signals originate at the LTC1402,

they arrive at the serial port with

similar delays and remain synchro-

nized. When the data is received at

the serial port of a DSP or other

processor, the port must be program-

med to respond to the appropriate

SCK and CONV edges. It is also nec-

essary to check where the 12-bit

output DATA sits in the 16-bit data

frame. The TMS320C54x serial port

READ instructions can shift the 12-bit

data to the preferred position within

the 16-bit data frame.

The serial interface lends itself to

galvanic isolation with external opto-

couplers. Figure 1c shows how to

isolate the LTC1402 with the HPCL-

2430 dual optocoupler. The 40ns

propagation delays through the dual

optocouplers cancel to maintain a

good timing match between the D

OUT

SCK and CONV signals. The LTC1402,

running at a 2Msps conversion rate,

sends 16-bit data frames through the

HPCL-2430 optocouplers at 32MB/s.

3V or 5V Serial Interface

without Spurious Noise

Figure 2 shows the block diagram of

the LTC1402. The internal architec-

ture has been optimized to send out

data serially during conversion, with-

out degradation of conversion

accuracy due to digital noise. The

35MHz clock input at the SCK pin

(15) and the external 2.2Msps con-

version start input at the CONV pin

(16) do not inject noise into the inter-

nal analog signal path of the ADC. As

a result, the analog accuracy of the

LTC1402 is insensitive to the phase,

duty cycle or amplitude (3V or 5V) of

the external digital inputs. The D

OUT

pin (10) swings from the voltage at the

OGND pin (9) to the voltage at the

pin (11) to allow direct inter-

facing to 5V or 3V DSPs and

microprocessors. The LTC1402 is

ideal in multiple-ground systems,

where the differential input is con-

nected to one ground, the supplies

and grounds of the LTC1402 connect

to a second, local ground and the

output ground connects to a third,

digital ground.

SIGNAL

CONV

SCK

OUT

OGND

LTC1402

CONV

2Msps

CLK

32MHz

10µF

TMS320C54X

BFSR

BCLKR

BDR

1N4148

560Ω

HCPL-2430

GND

IN+

IN–

Figure 1c. The LTC1402 is easily isolated with high speed optocouplers

Linear Technology Magazine • February 2000

DESIGN FEATURES

Very High SFDR in Single 5V

Supply Applications

A proprietary sampling front end cir-

cuit achieves exceptional dynamic

performance at the 1.1MHz Nyquist

frequency: –89dB THD with ±5V sup-

plies and –82dB THD with a single 5V

supply. Figures 3 and 4 show the

spectra from a 1.1MHz Nyquist fre-

quency sine wave with ±5V supplies

and a single 5V supply, respectively.

With this very clean spectrum, the

LTC1402 minimizes crosstalk and

interference in communications

applications where the spectrum is

divided into many frequency slots.

The LTC1402 maintains 72dB

S/(N+D) with a 1.1MHz input sine

wave, with either a single 5V or ±5V

supplies. Positive signals can be

applied with single or dual supplies

and bipolar signals are easily accom-

modated with dual-supply operation.

The full power bandwidth of the

LTC1402 is 80MHz; the full linear

bandwidths (SINAD > 68dB) of 5MHz

with ±5V supplies and 3.5MHz with a

single 5V supply round out the excep-

tional dynamic performance of the

LTC1402. The wideband signal con-

version purity shown in Figures 5a

and 5b makes the LTC1402 well suited

for digitizing sine wave signals well

above the 1.1MHz Nyquist frequency.

Figures 6 and 7 show that transfer

function purity, represented by the

differential and integral linearity plots,

is maintained at the full 2.2Msps

conversion rate.

True Differential Inputs

Cancel Wideband

Common Mode Noise

The front-end sampling circuit

acquires the input signal differen-

tially from the A

IN+

and A

IN–

analog

inputs. Except for the sign inversion,

these two inputs are identical. The

wide common mode rejection band-

width of the LTC1402 (–60dB at

10MHz input) affords excellent ground

noise rejection in complex, noisy sys-

tems. Figure 8a shows the CMRR

performance vs input frequency.

The differential inputs are very easy

to interface to a wide range of signal

sources. Grounding the A

IN–

input

near the signal source reduces com-

mon mode ground noise. Setting the

BIP/UNI pin (8) to a logic high selects

the bipolar ±2.048V range; setting it

to a logic low selects the unipolar 0V

to 4.096V range.

The 0V to 4.096V unipolar range is

ideal for single 5V supply applica-

tions where the A

IN–

input is grounded

and the signal is applied to the A

IN+

input. The ±2.048V bipolar range cen-

tered around midsupply can also be

used in single 5V supply applica-

tions, with the A

IN–

input tied to a

2.5VDC source. Alternately, the full

±2.048V bipolar range can be driven

with a pair of complementary ±1.024V

signals into A

IN+

and A

IN–

. This limits

the swing of external single 5V supply

ampliﬁers to their most linear region,

from 1.5V to 3.5V. Figure 8b shows

half of the LT1813 dual op amp driv-

ing the LTC1402 in this fully

differential conﬁguration with a single

5V supply.

FREQUENCY (MHz)

AMPLITUDE (dB)

–70 2ND

–80

–90

–100

–110

–120

–10

–30

–50

–20

–40

–60

0.55 1.11

4TH

6TH

3RD

5TH

fSAMPLE = 2222222.22Hz

fSINE = 1131727.43Hz

2048 SAMPLES

FREQUENCY (MHz)

AMPLITUDE (dB)

–70 2ND 3RD

4TH

6TH

–80

–90

–100

–110

–120

–10

–30

–50

–20

–40

–60

0.55 1.11

5TH

fSAMPLE = 2222222.22Hz

fSINE = 1131727.43Hz

2048 SAMPLES

Figure 3. Sine wave spectrum plot

(bipolar ±2V) with ±5V supplies

Figure 4. Sine wave spectrum plot

(unipolar 0V–4V) with single 5V supply

INPUT FREQUENCY (Hz)

EFFECTIVE NUMBER OF BITS

SIGNAL-TO-NOISE + DISTORTION (dB)

SAMPLE

= 2.22MHz

Figure 5a. ENOBs and SINAD vs input

frequency (bipolar ±2V) with ±5V supplies

CODE

DNL (LSB)

0.50

4096

–0.50

–1.00 1024 2048 3072

512 1536 2560 3584

1.00

–0.25

0.25

–0.75

0.75

SAMPLE

= 2.2MHz

Figure 6. Differential nonlinearity vs

output code (unipolar 0V–4V)

CODE

INL (LSB)

0.50

4096

–0.50

–1.00 1024 2048 3072

512 1536 2560 3584

1.00

–0.25

0.25

–0.75

0.75

SAMPLE

= 2.2MHz

Figure 7. Integral nonlinearity vs output

code (unipolar 0V–4V)

INPUT FREQUENCY (Hz)

EFFECTIVE NUMBER OF BITS

SIGNAL-TO-NOISE + DISTORTION (dB)

SAMPLE

= 2.22MHz

Figure 5b. ENOBs and SINAD vs input

frequency (unipolar 0V–4V) with single 5V

supply

Linear Technology Magazine • February 2000

DESIGN FEATURES

Internal or

External Reference

The internal 2.048V reference (multi-

plied by 2 at the V

REF

output) sets the

bipolar and unipolar ranges to

±2.048V and 0V to 4.096V, respec-

tively. Tying the Gain pin (7) to the

REF

pin (5) cuts the reference voltage

at the V

REF

pin and analog input

spans in half, to 2.048V. The internal

reference can also be disabled by

tying the Gain pin to V

and tying an

external reference with an output

between 2V and 5V directly to V

REF

The single-ended unipolar input

range of Figure 9a’s circuit depends

on the DAC’s output voltage, which

acts as an inﬁnite sample-and-hold

for signals such as a CCD sensor dark

current or similar applications, as

determined by software procedures.

The LTC1446 12-bit serial DAC

applies a voltage to the GAIN and A

IN–

pins of the ADC, in this case subtract-

ing the A

IN–

voltage from the V

REF

voltage, thus maintaining a positive

full scale of 4.096V while varying zero

scale over the range of 0V to 2V. This

adjustment of the low end of the scale

preserves the full 12-bit dynamic

range of the ADC to digitize the input

video signal between the dark-current

value and 4.096V. The dark-current

value must be a slow-moving DC value

FREQUENCY (MHz)

–40

COMMON MODE REJECTION RATIO (dB)

–30

–20

–10

0.1 10 100 1000

–50

–60

–70 1

–

1/2 LT1813

5V 5V

0.1µF

5pF

= V

±1V

51Ω

68pF

10µF

10µF10µF

11211

IN+

IN–

REF

GAIN

BIP/UNI

AGND2 AGND1

14 62

LTC1402

P-P

2πRC

(MIN)

100

≈

so that the DAC and the reference

buffer ampliﬁer can drive their

respective 10µF capacitors. The

LTC1446 DAC is stable with a 10µF

load; care must be taken when sub-

stituting capacitors.

Figure 9b shows alternative con-

nections to emulate the functional

range of a ﬂash converter in an image

scanner application. The top and bot-

tom of the conversion ranges are set

independently by the LTC1446 DAC,

just like the top and bottom voltages

of the internal resistor ladder in a

ﬂash converter. The bottom of the

–

2.048V

BANDGAP

REFERENCE

LT1813

1/2 LTC1446

64k

10µF

IN+

IN–

REF

AGND2

GAIN

LTC1402

SCANNER

VIDEO

–

2.048V

BANDGAP

REFERENCE

LT1813

1/2 LTC1446

64k

10µF

IN+

IN–

REF

AGND2

GAIN

LTC1402

SCANNER

VIDEO

DISABLED IN

HIGH IMPEDANCE

WITH PIN 7

HIGH

Figure 8a. CMRR vs input frequency

Figure 8b. True differential inputs accept 4V

P-P

bipolar differential signal with 2V

P-P

swings

on each input and an effective gain of 2 from the LT1813 inputs. SINAD = 70.7dB with a

1MHz input.

Figure 9a. The use of a DAC allows software adjustment of the lower

end of the ADC range for applications such as dark-current

cancellation.

Figure 9b. A dual DAC allows software adjustment of both the full-

scale and zero-scale voltages of the ADC, emulating the behavior of

a ﬂash converter.

Linear Technology Magazine • February 2000

DESIGN FEATURES

SAMPLE RATE (MHz)

0.01

0.1

SUPPLY CURRENT (mA)

0.01 0.1 1

0.001

100

CURRENT

DUAL ±5V

CURRENT

DUAL ±5V

CURRENT

SINGLE 5V

CURRENT

SLEEP MODE

(WITH EXTERNAL

REFERENCE)

CURRENT

NAP MODE

CURRENT

SINGLE 5V

conversion range starts at the dark-

current value and the top of the range

is set externally to match the maxi-

mum possible output from the image

scanner. The voltage at AGND (pin 6)

may vary from 0V to 1V; that at VREF

(pin 5) may vary from 2V to 5V. The

LT1813 input buffer ampliﬁers may

not be necessary if the image sensor

has a low input impedance (<100Ω).

Reducing Power

at Low Sample Rates

The LTC1402 consumes 90mW in

normal operation, on either single 5V

or ±5V supplies. NAP and SLEEP

modes cut back power drain to 15mW

and 10mW, respectively. NAP mode

leaves the reference on and takes only

300ns to wake up, making it ideal for

saving power between conversions in

lower-sample-rate applications.

SLEEP mode also shuts down the

reference and takes 10ms to wake up.

The REFREADY bit in the output data

stream indicates when the reference

has settled to full accuracy. NAP and

SLEEP modes are easily set with two

or four pulses at the CONV pin (16)

input, respectively. One or more

pulses at the SCK pin (15) input wakes

up the LTC1402 for conversion.

Figure 10 shows the reduced power

consumption while the sample rate is

reduced and the NAP or SLEEP modes

is used between conversions. For

example, an undersampling appli-

cation with NAP mode between

conversions at a 455ksps sample rate

draws only 40mW.

Conclusion

The LTC1402 has all the speed and

AC and DC performance of fast 12-bit

ADCs with parallel data interfaces,

but it offers a much smaller, glueless

serial interface that saves space in

the 16-pin narrow SSOP package.

The tiny LTC1402 can be placed right

at the sensor for optimum analog

signal capture and the compact 3-

wire serial interface can be routed

through a system board, through a

cable or through an isolation barrier,

to serial ports on DSPs and other

processors.

Figure 10. Current consumption vs sample

rates for various operating modes and supply

conﬁgurations

LTC2402

SCK

SDO

3-WIRE

SPI

SET

CH0

CH1

SET

GND

EXCITATION

= 200µA

EXCITATION

= 200µA

= 0

RTD

–

Figure 8. RTD remote temperature measurement

RTD Temperature Digitizer

RTDs used in remote temperature

measurements often have long leads

between the ADC and RTD sensor.

These long leads result in parasitic

voltage drops due to excitation cur-

rent in the interconnect to the RTD.

This voltage drop can be measured

and digitally removed using the

LTC2402, as illustrated in Figure 8.

The excitation current (typically

200µA) ﬂows from the ADC reference

through a long lead to the remote

temperature sensor (RTD). This cur-

rent is applied to the RTD, whose

resistance changes as a function of

temperature (100Ω–400Ω for 0°C to

800°C). The same excitation current

ﬂows back to the ADC ground and

generates another voltage drop across

the return leads. In order to get an

accurate measurement of the tem-

perature, these voltage drops must

be measured and removed from the

conversion result. Assuming that the

resistance is approximately the same

for the forward and return paths

(R1 = R2), the second channel (CH1)

on the LTC2402 can measure this

drop. These errors are then removed

with simple digital correction.

The result of the ﬁrst conversion

on CH0 corresponds to an input volt-

age of V

RTD

+ R1 • I

EXCITATION

The

result of the second conversion (CH1)

is –R1 • I

EXCITATION

Note that the

LTC2402’s input range is not limited

to the supply rails; it has underrange

as well as overrange capabilities. The

device’s input range is –300mV to

SET

+ 300mV (D

OUT

includes a sign

bit indicating a negative input). Add-

ing the two conversion results, the

voltage drop across the RTD’s leads is

cancelled and the ﬁnal result is V

RTD

Conclusion

Linear Technology has introduced two

new converters to its 24-bit No Latency

∆Σ™ converter family. The family con-

sists of the LTC2400 (1-channel, 8-pin

SO), LTC2408 (8-channel, 24-bit ADC)

and the LTC2401/LTC2402 shown

here. Each device features excellent

absolute accuracy, ease-of-use and

near zero drift. The LTC2401/

LTC2402 also include full-scale set

(FS

SET

) and zero-scale set (ZS

SET

)

inputs for removing errors due to

systematic voltage drops. The perfor-

mance, features and ease-of-use of

these devices warrant that designers

reconsider the accuracy capabilities

of their future system designs.

LTC2401/LTC2402, continued from page 4

Linear Technology Magazine • February 2000

DESIGN IDEAS

LTC1645/LTC1735 Circuit Solves

PCI Power Problem

In some applications, it is neces-

sary to select and hot swap the higher

of two supplies and generate a regu-

lated output voltage from the selected

supply. If only one input supply is

present, the circuit should select it

and generate the same output volt-

age. The term “hot swapping” refers

to plugging a circuit board into or

removing it from a live backplane.

When this is done, the supply bypass

capacitors on the board can draw

huge transient currents from the

backplane power bus as they charge.

The transient currents can cause per-

manent damage to the connector pins

VCC1

SENSE1

VCC2

SENSE2

COMP+

GND

COMPOUT

GATE1

GATE2

FAULT

RESET

TIMER

LTC1645

MBR0520

MBR-

0520

10k

Q3-A

1/2 Si4936 Q3-B

1/2 Si4936

Q1-A

1/2 Si4936 Q1-B

1/2 Si4936

10Ω

10k

2N7002

0.1µF

0.33µF

0.1µF

VIN1

VIN2

3.3V VOUT_HOT_SWAP

VOUT_HOT_SWAP = 5V IF

VIN1 = 5V

AND VIN2 = 3.3V;

VOUT = 3.3V IF VIN1 = FLOAT

AND VIN2 = 3.3V.

COSC

RUN/SS

ITH

SGND

VOSENSE

PGND

FCB

SENSE+

SENSE–

VIN

BOOST

INTVCC

12 +

12V

100µF

R15

100k

R11

1.6M

43pF

0.33µFC8

O.22µF

R13 15k

C9 180pF

C11

100pF

Q5 2N7002

R9 0.01Ω

C16

1000pF

R10 10k

2N7002 Q7

Si4410

L1A

5.7µH

L1B

5.7µH

10µFD3

MBRD835L

R12

31.6k

R14

10k

C11–C12

470µF

12V

×2

C15

10µF

VOUT_SWITCHER

3.3V/3A

C14

4.7µF

C13

1µF

LTC1735

C5, C15: AVX 12062G106 (803) 946-0362

C11, C12: KEMET T510X477(1) 006AS (408) 986-0424

C4: AVX TPS107070R0065

L1A/B: COILTRONICS VP2-0016 (561) 241-7876

Figure 1. LTC1645 3.3V/5V Hot Swap circuit plus LTC1735 SEPIC converter

by Ajmal Godil

and cause glitches on the system

supply, causing other boards in the

system to reset. A circuit based on an

appropriate LTC Hot Swap™ control-

ler can eliminate these problems.

The circuit in Figure 1 selects

between and hot swaps a 3.3V and a

5V input supply and generates a

Linear Technology Magazine • February 2000

DESIGN IDEAS

Figure 2. V

GATE2

and V

OUT_HOT_SWAP

increasing

to 12V and 5V, respectively

Figure 3. V

GATE1

and V

OUT_HOT_SWAP

increasing

to 10V and 3.3V, respectively

Figure 4. LTC1735 SEPIC voltage-rise waveforms;

OUT_HOT_SWAP

and V

OUT_SWITCHER

= 3.3V Figure 5. LTC1735 SEPIC voltage-rise waveforms;

OUT_HOT_SWAP

= 5V and V

OUT_SWITCHER

= 3.3V

GATE1

OUT_HOT_SWAP

GATE2

OUT_HOT_SWAP

OUT_SWITCHER

OUT_HOT_SWAP

= 3.3V

OUT_SWITCHER

OUT_HOT_SWAP

= 5V

constant 3.3V output supply using

the LTC1645 and the LTC1735. The

LTC1645 is a 2-channel Hot Swap

controller and the LTC1735 is a syn-

chronous step-down switching

regulator. The two voltage supplies,

IN1

and V

IN2

, are fed into the LTC1645

Hot Swap circuit, where the higher of

the two supplies is selected

OUT_HOT_SWAP

) and then fed into the

LTC1735 DC/DC converter. The

LTC1735 circuit generates a constant

3.3V output voltage, regardless of

whether its input is 3.3V or 5V. To

simplify the circuit description, the

operation of the LTC1645 and the

LTC1735 will be discussed separately.

LTC1645

Hot Swap Operation

Back-to-back MOSFETs Q1 and Q2

are connected to the V

IN1

(5V) supply

and Q3 and Q4 are connected to the

IN2

(3.3V) supply. The reason for

using back-to-back MOSFETs is to

keep the internal body diodes from

shorting the 5V and 3.3V supplies

together. The LTC1645’s Gate1 pin

controls Q3 and Q4 and its Gate2 pin

controls Q1 and Q2. The ON pin has

a 0.8V turn-on threshold for Gate1

and a 2.0V turn-on threshold for

Gate2. The V

CC1

and V

CC2

pins have

2.3V and 1.2V undervoltage lockout

thresholds, respectively. Since the

circuit in Figure 1 selects between

two supplies, the following two cases

are possible:

Case One:

5V and 3V Supplies Present

When the 5V and 3.3 supplies are

present on V

IN1

and V

IN2

, respectively,

CC1

, V

CC2

, Sense2 and Sense1 are

pulled up to approximately 4.7V by

D1, which clears the undervoltage

lockout thresholds of V

CC1

and V

CC2

The COMP

pin is pulled up to 2.5V by

the voltage divider formed by R2 and

R6. Since the voltage on the COMP

pin (noninverting terminal of the

onboard comparator) is greater than

a 1.24V threshold, the COMPOUT pin

(open drain output of the comparator)

is pulled up to 5V by R7. This turns

on Q5 and pulls the gates of Q3 and

Q4 to ground. The ON pin is pulled up

to approximately 2.74V through R1,

R4 and R8. After one timing cycle (t =

C2 • 1.24V/2µA), an internal 10µA

current source from the charge pump

is connected to the Gate1 and Gate2

pins. The Gate1 pin is pulled to ground

by Q5 and the voltage on the Gate2

pin starts to rise, with a slope given by

dV/dt = 10µA/C1. The internal charge

pump guarantees that the Gate2 volt-

age will rise to approximately 12V. As

Linear Technology Magazine • February 2000

DESIGN IDEAS

OUT_SWITCHER

RIPPLE

100mV/DIV

2µs/DIV

OUT_SWITCHER

100mV/DIV

200µs/DIV

Figure 6. LTC1735 efﬁciency vs load current

OUT_SWITCHER

= 3.3V)

Figure 7. LTC1735 output voltage ripple: output voltage = 3.3V,

load current = 3A Figure 8. LTC1735 transient response: load

step = 0.5A–3.3A

70 0 1000 2000 3000

LOAD

(mA)

EFFICIENCY (%)

OUT_HOT_SWAP

= 3.3V

OUT_HOT_SWAP

= 5V

the Gate2 voltage rises to about 1V,

Q1 and Q2 start conducting and

OUT_HOT_SWAP

starts rising. The out-

put voltage will eventually rise to the

input supply, which is 5V. Figure 2

shows the Gate2 pin and V

OUT_HOT_SWAP

voltages rising to 12V and 5V,

respectively.

Case Two:

Only 3.3V Supply Present

CC1

, V

CC2

, Sense1 and Sense2 are

pulled up to 3.0V by D2, which clears

the undervoltage lockout thresholds

of V

CC1

and V

CC2

. Since the 5V supply

is not present, the ON pin is only

pulled up to 1.65V by R4 and R8.

After one timing cycle, an internal

10µA current source from the charge

pump is connected to the Gate1 pin.

The voltage on the Gate1 pin starts to

rise with a slope given by dV/dt =

10µA/C3. The internal charge pump

guarantees that the Gate1 voltage

will rise to approximately 10V. Since

the ON pin is below 2V (the ON pin

turn-on threshold for Gate2), a 40µA

current source pulls the Gate2 pin

toward ground. As the Gate1 pin volt-

age rises to about 1V, Q3 and Q4 start

conducting and V

OUT_HOT_SWAP

starts

rising. The output voltage will even-

tually rise to the input supply voltage,

which is 3.3V. Figure 3 shows the

Gate1 and V

OUT_HOT_SWAP

voltages ris-

ing to 10V and 3.3V, respectively.

LTC1735 Operation

The LTC1735 is connected in a SEPIC

(single-ended, primary inductance

converter) conﬁguration to produce a

constant 3.3V output at 3A. Since the

minimum input voltage for the

LTC1735 is 3.5V, the V

pin on the

chip is connected to a 12V supply

that can provide a few milliamps. The

main load current is supplied by either

IN1

(5V) or V

IN2

(3.3V). Q5, Q6 and

R11 in Figure 1 allow the LTC1735 to

produce to an output voltage after the

input supply (V

OUT_HOT_SWAP

) has ﬁn-

ished rising. Figures 4 and 5 show the

LTC1735 producing a 3.3V output

from a 3.3V or a 5V V

OUT_HOT_SWAP

supply input. Figure 6 shows the

typical efﬁciency curves for a

OUT_HOT_SWAP

supply of 3.3V or 5V at

an output voltage of 3.3V. Figure 7

shows the output voltage ripple with a

steady-state load of 3A and Figure 8

show the transient response for a

0.5A–3A load step. Note that all the

components used in the circuit of

Figure 1 are surface mountable and

ﬁt in an area of less than 1.5in

For more information on parts featured in this issue, see

http://www.linear-tech.com/go/ltmag

For more information on parts featured in this issue, see

http://www.linear-tech.com/go/ltmag

Linear Technology Magazine • February 2000

DESIGN IDEAS

Active Voltage Positioning Saves

Output Capacitors in Portable

Computer Applications by John Seago

and Ajmal Godil

Introduction

Active voltage positioning is a tech-

nique that can be used to save cost

and space by reducing the number of

output capacitors required to meet a

microprocessor’s power supply

requirements. Total system cost and

required PCB space are important

aspects of today’s portable equipment

designs, so decreasing the number of

large, expensive output capacitors is

worth some effort. Both the LTC1735/

LTC1736 current mode switching

regulator controllers (Linear Technol-

ogy IX:1, February 1999, pp. 1, 3–5,

35) and the LTC1702/LTC1703

voltage mode controllers (Linear Tech-

nology IX:3, September 1999,

pp. 16–20) can take advantage of

active voltage positioning.

Microprocessor Load Steps

Microprocessors frequently change

their load current requirement from

almost no load to maximum load cur-

rent and back again very quickly. The

rising and trailing edges of these load

current steps exceed the bandwidth

of the switching regulator control loop.

Currently, a typical load step is either

0.2A to 12A in 100ns or 12A to 0.2A

in 100ns. The core voltage of the

microprocessor must be held to about

±0.1V of nominal in spite of these load

steps.

Since the switching regulator con-

trol loop cannot respond in 100ns,

the output capacitors must tempo-

rarily supply the load current when

the output current increases rapidly.

Also, the output capacitors must

absorb the energy stored in the

inductor when the output current

decreases rapidly. Capacitor ESR and

ESL primarily determine the amount

of droop and overshoot in the output

voltage caused by a load current step.

Normally, several capacitors in

parallel are required to meet the

microprocessor load transient

requirements.

PGOOD

RUN/SS

OSC

FCB

SGND

SENSE

–

SENSE

VFB

VOSENSE

VID0

VID1

BOOST

INTV

EXTV

VIDV

PGND

VID4

VID3

VID2

LTC1736

VID0 VID1 VID2 VID3 VID4

POWER

GOOD

C2 0.1µF

R5 100k C3 100pF

C4 100pF

C1 39pF

1000pF

330pF

47pF

R3 160k

R2 680k

R1 100k

0.1µFC12–C14

10µF, 35V

Y5V

×3

FDS6680A

0.22µF

MBR0530

MBRS340

L1 1.0µHR6

0.003Ω

Q2–Q3

FDS6680A

×2

C10 1µFC11

4.7µF

10V

OUT

0.9V–2.0V

14A

7.5V–24V

C15–C17

180µF, 4V

×3

C12–C14:

C15–C17:

L1:

TAIYO YUDEN GMK325F106

(408) 573-4150

PANASONIC EEFUE0G181R

(201) 348-7522

PANASONIC ETQP6F1R0SA

Q1–Q3:

R6:

FAIRCHILD FDS6680A

(207) 775-4502

IRC LRF2512-01-R003-J

(512) 992-7900

R4 68k

Figure 1. LTC1736-based core-voltage regulator with active voltage positioning

Linear Technology Magazine • February 2000

DESIGN IDEAS

How Active Voltage

Positioning Works

Active voltage positioning is a form of

deregulation. It sets the output volt-

age high for light loads and low for

heavy loads. In the low-current-to-

high-current transition, the output

voltage starts at a voltage higher than

nominal so the output voltage can sag

more and still meet the minimum

output voltage speciﬁcation. By set-

ting the output voltage lower than

nominal for heavy load conditions,

more output voltage variation is pos-

sible when the load current suddenly

decreases to almost zero. Less output

capacitance is required because more

output voltage variation is allowed on

the output capacitors.

The implementation of active volt-

age positioning depends on the type

of OPTI-LOOP error ampliﬁer used in

the switching regulator. With the

LTC1736, connecting two resistors to

the I

pin adjusts the output voltage

in inverse proportion to the amount

of load current. This technique will

only work with a current mode con-

trol regulator. Different techniques

are available for the LTC1703; these

can also be used on the LTC1736 and

will be discussed later.

LTC1736 Circuit with

Active Voltage Positioning

Reducing output capacitance with

active voltage positioning requires

connecting two resistors to the I

and readjusting the loop compensa-

tion component values. Figure 1

shows a core voltage regulator circuit

designed to operate from a 7.5V to

24V input and provide ±7.5% accu-

racy to VID controlled output voltages

from 0.9V to 2.0V with load current

steps from 0.2A to 12A. Although

7.5% output voltage accuracy does

not sound very impressive, 7.5% of

1.4V is only 105mV, including setpoint

accuracy and load and line regula-

tion, as well as margin for transient

response to the 12A load step.

The circuit in Figure 1 is a current

mode, synchronous buck regulator

with a switching frequency of 300kHz.

The nominal output voltage is selected

by the standard Intel mobile VID code.

The actual output voltage varies as a

function of the load current. The

no-load output voltage from this cir-

cuit is higher than nominal because

the current sourced by R3 creates a

positive offset at the input of the

transconductance error ampliﬁer. The

error ampliﬁer current sourced into

Figure 3. LTC1703-based regulator with active voltage positioning implemented with a sense resistor

Figure 2. Transient response for a 12A load-current step

1.72V

1.60V

1.48V

100µs/DIV

OUT I/O

1.5V/3A

C14

1µF

C10

47µF

R11

9.76k

R13

10.7k

L1 2.2µH

R7 2.7k

Q4-A

Q4-B

C21

62pF

C20

18pF

R16 180k

R10 43k

C16

0.1µF

MBR-

0520L

330µF

22µF

R17 10Ω

C22

10µF

MBR-

0520L

C6 0.1µF

L2 1µH

R9 30k

C23 1200pF

R19 1.8k

R15 330k

C17

43pF

C18

8.2pF

R20

390k

R18

0.0025Ω

C12

1µF

C13

150µF

×4

BOOST1

TG1

SW1

BG1

MAX1

SENS

FB1

COMP1

RUN/SS1

SGND

BOOST2

TG2

SW2

BG2

FB2

MAX2

COMP2

RUN/SS2

FAULT

FCB

PGND

LTC1703

VID0 VID1 VID2 VID3 VID4

OUT CPU

0.9V–2.0V

14A

C19

0.1µF

C1, C2:

C3:

C10:

C13:

L1:

L2:

R18:

TAIYO YUDEN LMK432BJ226MM

(408) 573-4150

AVX TPSV3307010R0060

(207) 282-5111

SANYO POSCAP 6TPA47M

(619) 661-6835

SANYO POSCAP 4TPC150M

COILTRONICS 2P2B-2R2

(561) 241-7876

SUMIDA CEP125

(847) 956-0666

2 × 5mΩ IN PARALLEL

Q1–Q3:

Q4:

IRF7811

(310) 322-3331

SILICONIX Si4966

(800) 544-5665

820

Linear Technology Magazine • February 2000

DESIGN IDEAS

R4 develops a negative input offset

voltage. This negative offset causes

the output voltage to be less than

nominal under full load conditions.

Forced offsets at the input of the

error ampliﬁer should be limited to

±30mV. If a lower output voltage is

required at full load, the voltage drop

across the current sense resistor can

be subtracted from the regulated out-

put voltage by connecting the V

OSENSE

pin to the inductor side of the sense

resistor, as shown in Figure 1. Figure

2 shows a transient waveform of 50mV

and –100mV from a 12V input and

1.6V output of Figure 1’s circuit. The

output voltage tolerance of 7.5%

allows a ±120mV variation.

LTC1703 Circuit with

Active Voltage Positioning

Figures 3 and 4 show two methods of

implementing active voltage position-

ing on an LTC1703 circuit. In Figure

3, the voltage deregulation is set by

adding a 2.5mΩ resistor (R18) in the

power path. At full load, the output

voltage will be less than nominal by

FULL LOAD

• 0.0025. In order to pro-

gram the output voltage higher than

nominal at zero load, a 390k resistor,

R20, is added between the FB1 pin

and ground. The DC value by which

the output voltage increases over

nominal can be calculated by the

following formula:

VHIGHER = (0.8/390k) • 10k ≈ 20mV

In Figure 4, the voltage deregulation

is set by the DC resistance of the

power inductor, which is approxi-

mately 2.5mΩ. The SENSE pin on the

LTC1703 is connected between R20

(150Ω) and C24 (1µF). R20 and C24,

which are connected across the

inductor L2, act as a lowpass ﬁlter

OUT I/O

1.5V/3A

C14

1µF

C10

47µF

R11

9.76k

R13

10.7k

L1 2.2µH

R7 2.7k

Q4-A

Q4-B

C21

62pF

C20

18pF

R16 180k

R10 43k

C16

0.1µF

C7 0.1µF

MBR-

0520L

330µF

22µF

R17 10Ω

C23

10µF

MBR-

0520L

C6 0.1µF

L2 1µH

R9 30k

C23

1200pF

R19 1.8k

R15 330k

C17

43pF

C18

8.2pF

R21

390k

C12

1µF

C13

150µF

×4

BOOST1

TG1

SW1

BG1

MAX1

SENS

FB1

COMP1

RUN/SS1

SGND

BOOST2

TG2

SW2

BG2

FB2

MAX2

COMP2

RUN/SS2

FAULT

FCB

PGND

LTC1703

VID0 VID1 VID2 VID3 VID4

OUT CPU

0.9V–2.0V

14A

C19

0.1µF

C1, C2:

C3:

C10:

C13:

L1:

L2:

TAIYO YUDEN LMK432BJ226MM

(408) 573-4150

AVX TPSV3307010R0060

(207) 282-5111

SANYO POSCAP 6TPA47M

(619) 661-6835

SANYO POSCAP 4TPC150M

COILTRONICS 2P2B-2R2

(561) 241-7876

SUMIDA CEP125

(847) 956-0666

Q1–Q3:

Q4:

IRF7811

(310) 322-3331

SILICONIX Si4966

(800) 544-5665

C22

1µFR20

150Ω

820

1.72V

1.60V

1.48V

50µs/DIV

LOAD STEP = 0A–14A

= 5V

OUT

= 1.6V

OUT

= 4 × 150µF

POSCAPS

HIGHER

with a time constant of 150µs. Like-

wise, a 390k resistor, R21, is added

between the FB1 pin and ground.

Figure 5 shows the transient response

of the LTC1703 circuit in Figures 3

and 4 for a 0A–14A transient load step

with four 150µF Poscap capacitors.

Conclusion

Active voltage positioning allows more

output voltage change during a load

transient so fewer output capacitors

are required. Fewer capacitors result

in a smaller, less expensive

regulator.

Figure 4. LTC1703-based regulator with active voltage positioning implemented using the DC resistance of the inductor

Figure 5. LTC1703 V

OUT

CPU

transient response with active voltage positioning

Linear Technology Magazine • February 2000

DESIGN IDEAS

ADSL Line Driver/Receiver

Design Guide, Part 1 by Tim Regan

Introduction

Consumer desire for faster Internet

access is driving the demand for very

high data rate modems. A digital sub-

scriber line (DSL) implementation

speeds data to and from remote serv-

ers with data rates of 512Kbps to

8Mbps, much faster than current

56Kbps modem alternatives. This

speed of data communication is pro-

viding the Internet with the capability

to transfer information in new for-

mats such as full-motion video, while

greatly improving the timeliness of

conventional information access.

One very important feature of DSL

technology is that the connection is

handled through a normal telephone

line; therefore, no special high speed

cables or ﬁber optic links are required

and every home and ofﬁce is most

likely DSL ready. Another feature is

that the data interface can operate

simultaneously with normal voice

communication over the same tele-

phone line. This allows the modem to

be connected at all times and not

interfere with the use of the same line

for normal incoming and outgoing

phone calls or faxes.

The real “magic” of DSL technology

stems from the application of digital

signal processing (DSP) algorithms

and data coding schemes. The imple-

mentations have built-in intelligence

to accommodate the wide variations

of data transmission signal conditions

–

12.4Ω

–

100Ω

PHONE

LINE

1:2

–

FRX

–

Rx FILTER

5V OR 3.3V

AFE

R 1k

2R 2k

R 1k

2R 2k

Tx FILTER

1/2 LT1795

1/2 LT1361

MIDCOM

50215

15V

–15V

2, 19 10

SHDN

SHDNREF

4–7,

14–17

ADJ

64.9k

15V

–15V

15V

–15V

10µF

0.1µF

POSITIVE SUPPLY

NEGATIVE SUPPLY

6,7

9,10

Figure 1. Central-ofﬁce ADSL transceiver

Linear Technology Magazine • February 2000

DESIGN IDEAS

encountered with each connection

through the telephone switching net-

work. Sophisticated ASICs have been

developed to provide small modems

for PCs and handheld devices and the

ability to compact many DSL lines on

a single PCB card for telephone cen-

tral-ofﬁce deployment.

However, as is the case with almost

any system, DSL still requires funda-

mental operational ampliﬁer functions

to put the signal on to the phone line

and to pick off the small signals

received at the other end. Although

many system designers are compe-

tent and comfortable with DSP and

all things digital, they often ﬁnd their

understanding of analog issues to be

a bit rusty when it comes to imple-

menting the physical connection to

and from the telephone line. This

series of articles will provide an over-

view of the requirements placed on

the ampliﬁers and provide guidelines

to component selection and the impli-

cations on distortion performance and

power consumption and dissipation,

the most important system issues

related to the analog components.

Figure 1 shows a complete central

ofﬁce DSL line driver/receiver. This is

the basic circuit topology that pro-

vides differential transmit signal drive

to the line and detection of the differ-

ential received signal. The full

requirements of DSL are easily met by

using devices from Linear Tech-

nology’s broad line of high speed power

ampliﬁers for the driver and high

speed, low noise dual ampliﬁers for

the receiver. Using either current feed-

back or voltage feedback topologies,

the family of drivers consists of

ampliﬁers with bandwidths from

35MHz to 75MHz, slew rates in excess

of 200V/µs with output current

capability from 125mA to over 1 amp.

The receiver family combines similar

high speed performance with low

noise, less than 10nV/√Hz, and low

quiescent operating current, less than

10mA. The devices shown in Figure 1

are the LT1795 500mA output cur-

rent, 50MHz bandwidth dual op amp

and the LT1361 50MHz dual ampli-

ﬁer with input noise voltage of

9nV/√Hz and total supply current of

only 10mA.

Although there are several varia-

tions of DSL technology (SDSL, HDSL,

HDSL2, VDSL and ADSL, to name a

few) the requirements placed on the

ampliﬁers for these different stan-

dards are very similar. The major

difference between the approaches,

as they affect the line driver, is the

amount of power actually put on to

the phone line by the line-driver

ampliﬁer. For simplicity, these articles

will focus on the most recently

approved standard, ADSL (asymmet-

ric DSL), but the concepts discussed

apply equally to any of the other

standards.

This ﬁrst installment will provide

an overview of the requirements of

ADSL and how it is done, as well as a

discussion of the circuit topology and

the requirements for the components

used for implementation.

The Requirements for ADSL

The full speciﬁcations for ADSL are

contained in two ITU (International

Telecommunications Union) docu-

ments called G.992.1, for systems

often referred to as Full-Rate ADSL or

G.dmt, and G.992.2, a lower data rate

approach often called G.Lite. Both

systems use a technique called

discrete multitone, or DMT, for trans-

mitting data. With DMT, a frequency

band up to 1.2MHz is split up into

256 separate tones (also call sub-

carriers) each spaced 4.3125kHz

apart. With each tone carrying sepa-

rate data, the technique operates as if

256 separate modems were running

in parallel. To further increase the

data transmission rate, each indi-

vidual tone is quadrature amplitude

modulated (QAM). As shown in Fig-

ure 2, the data to be transmitted is

used to create a unique amplitude

and phase-shift characteristic for each

carrier tone, through the combina-

tion of I and Q data, called a symbol.

The symbols represented by each tone

are updated at a 4kHz rate or 4000

symbols per second. Full Rate ADSL

uses up to 15 bits of data to create

AMPLITUDE

CONVERTER

AMPLITUDE

CONVERTER

TONE

(CARRIRER)

INPUT

SYMBOL RATE

(SYMBOLS/s)

SYMBOL RATE

(SYMBOLS/s)

QAM

OUTPUT

SIGNAL

IN-PHASE

DATA

QUADRATURE

(90° PHASE-SHIFTED)

DATA f

INCOMMING

DATA

BIT RATE f

(BITS/s)

BIT-RATE

DIVIDER PHASE

SPLITTER

Q 90°

270°

0°, 360°

180°00 01 10 11

45°

EDOCSLEVEL ROTCEV GAME (°)LGNAIQ )BSM2(I)BSL2(Q

00003–3–2.4522

00103–1–2.3891

00013–12.3261

00113–32.4531

10001–3–2.3252

10101–1–4.1522

10011–14.1531

10111–32.3801

01001 3–2.3882

01101 1–4.1513

01011 1 4.154

01111 3 2.327

11003 3–2.4513

11103 1–2.3243

11013 1 2.381

11113 3 2.454

Figure 2. Quadrature amplitude modulation

Linear Technology Magazine • February 2000

DESIGN IDEAS

each symbol. This results in a theo-

retical maximum of 60Kb/s for each

tone. If all 256 tones are used in

parallel, the total theoretical data rate

can be as fast as 15.36Mb/s. For

G.Lite, only 8 bits are used per sym-

bol with only half of the carrier tones

used for a theoretical maximum data

rate of 4.096Mb/s.

In an actual DSL application, the

tones are allocated for use depending

on the direction of communication,

as shown in Figure 3. Most of the

tones are used for communication

from the central ofﬁce (CO) to an end

user’s PC modem (often referred to as

the CPE or customer premises

equipment). This direction of com-

munication is called “downstream.”

The direction of communication from

a PC modem to the central ofﬁce (and,

ultimately, to an Internet server) is

called “upstream.” The use of more

tones for the downstream direction

makes sense from an Internet-access

point of view, because most users

download more information than they

upload. Most upstream communica-

tion with a server is simply to request

information to be sent quickly down-

stream. This difference in data rates

up- and downstream is the reason

ADSL is called asymmetric DSL.

Also indicated in Figure 3 is the

power spectral density (PSD) of all of

the tones used. This determines the

amount of signal power that needs to

be put on to the phone line. The power

levels are restricted to minimize cross-

talk and interference into other phone

lines contained in wire bundles en

route to and from the central ofﬁce.

The total power required can be

determined from the following

equation:

LINE POWER (dBm) = PSD (dBm/Hz)

+ 10 • Log(FMAX – FMIN)

The downstream power require-

ments are much higher than the

upstream requirements because of

the wider bandwidth used for the

transmission. For this reason, Full

Rate ADSL requires more line power

than G.Lite for downstream trans-

missions. Upstream power is the same

for both Full Rate and G.Lite

retemaraP LSDAetaRlluF maertsnwoD etiL.GLSDA maertsnwoD

LSDAetaRlluF etiL.Gro maertspU

scitsiretcarahC

desUslennahC 652ot13821ot1303ot6

dnaBycneuqerF )zHk( 4011ot7.331255ot7.3314.921ot8.52

)zHk(htdiwdnaB 3.0793.8145.301

lartcepSrewoP DSP,ytisneD )zH/mBd( 04–0–4 73–

rewoPeniL )mBd( 023.6131

lacirtcelE stnemeriuqeR

eniLSMR )Wm(rewoP 0013402

ecnadepmIeniL )Ω(001001001

eniLSMR )V(egatloV 1.324.1

eniLSMR )Am(tnerruC 131251

egarevA-ot-kaeP RAP,oitaR 3.53.53.5

eniLkaeP )V(egatloV 5.61116.7

kaeP-ot-kaeP )V(egatloVeniL 33222.51

eniLkaeP )Am(tnerruC 07101167

eniLkaeP )Wm(rewoP 52725711085

ataDlaciteroehT setaR

lobmyS/stiB518 )lluF(51 )etiL.G(8

lennahC/stiB )s/stiBK( 0623)lluF(06 )etiL.G(23

etaRataDxaM slennahCrof desU s/bM5.31s/bM1.3 )lluF(s/bM4.1 )etiL.G(s/bK867

Table 1. ADSL requirements

POTS UPSTREAM

–37dBm/Hz

–40dBm/Hz

26kHz 130kHz 134kHz 552kHz 1.104MHz

G.LITE

FULL RATE

DOWNSTREAM

BOTH

Figure 3. DMT channel allocation

Linear Technology Magazine • February 2000

DESIGN IDEAS

implementations. As will be seen, the

line power requirement is the most

signiﬁcant factor in designing a line

driver for a particular application.

Table 1 is a summary of the char-

acteristics, electrical requirements

and maximum data rates for ADSL

modems.

The following are important items

to note:

The phone line characteristic

impedance for ADSL is 100Ω. This is

used to determine the voltage and

current required to provide the proper

line-power level.

The term PAR stands for peak-to-

average ratio. This term is similar to

the more common term of crest fac-

tor. This determines the peak value of

the voltage put on the line over time

with respect to the RMS voltage level:

VPEAK = PAR • VRMS

The DMT signal placed on the line

looks basically like white noise,

because many different frequencies

of rapidly changing amplitude and

phase are combined simultaneously.

The changes of each tone are consid-

ered random as they result from an

arbitrary sequence of data bits com-

prising the transmitted information.

Over time, the signals can align and

stack up to create a large peak signal.

If this large peak is not processed

cleanly (for example, if the line-driver

ampliﬁer clips) data errors can occur,

which must be detected and resent.

Transmission errors, particularly over

a noisy environment such as phone

lines, are inevitable. These errors are

identiﬁed by a term called the bit-

error rate (BER); an acceptable level

to maintain fast and accurate data

transmission is one error per every

symbols. The PAR is determined

by the probability of the random line

signal reaching a certain peak voltage

during the time interval required for

symbols. For the DMT signal, this

peak value is 5.3 times the RMS sig-

nal level. This factor is very important

in determining both the minimum

supply voltage required to prevent

clipping of the signal and also the

peak output current capability of the

line driver.

Although the data rates shown in

Table 1 are impressively fast, they

are, indeed, theoretical. In an actual

connection over the phone line, all

manner of interference sources will

alter the frequency response over the

1.2MHz band. These interference

sources can contaminate or attenu-

ate many of the carrier tones to render

them completely unusable, or useful

but with less than the maximum pos-

sible number of data bits encoded.

Additionally, higher frequency tones

are attenuated more than the lower

ones, particularly over longer lengths

of phone line used to make the

connection.

Another issue that can render par-

ticular tones unusable or create

transmission errors is distortion from

the ampliﬁer driving the line. Distor-

tion products, whether harmonic,

intermodulation or from signal clip-

ping, from any of the carrier tones,

create signal energy in the frequency

spaces used by other tones. This

energy also contaminates the data

content of the tones and can result in

fewer tones being used for data trans-

mission. If many tones are unusable

or their data handling capability is

reduced, the actual data rate for any

given connection can be signiﬁcantly

less than the theoretical maximum.

One of the best features of a DSL

modem is the intelligence built in to

obtain the fastest data rate for any set

of line conditions. When a connection

between a modem and the telephone

central ofﬁce is initiated, the ﬁrst

action to occur is called “training-

up.” During this interval, both ends

transmit maximum power in each

channel in an effort to determine

which channels are best suited for

use. The DSP algorithms will auto-

matically pack the most data into the

best transmission channels to maxi-

mize the data rate for a particular

connection. Figure 4 illustrates a typi-

cal line spectrum during a training-up

interval in a G.Lite example, as mea-

sured at the central ofﬁce end.

A Typical ADSL Line Driver/

Receiver Circuit

Referring to Figure 1, the compo-

nents shown will implement a Full

Rate ADSL central ofﬁce (downstream)

port. A discussion of the circuit topol-

ogy and aspects important for

component selection follow.

Transformer Coupling

A transformer is used to connect the

transceiver to the phone line, mainly

to provide isolation from the line. The

turns ratio of the transformer can be

used to provide gain to the transmit-

ted signal. This turns ratio has a

major effect on the power supply volt-

ages for the line-driver ampliﬁers. By

stepping up the signal from the driver

to the line via the transformer, the

amount of voltage swing needed by

the ampliﬁers is reduced. As an ideal

transformer has equal power in the

primary and secondary, while the

voltage is stepped up, the current is

stepped down. The consequences of

using a step-up transformer are ben-

eﬁcial in that lower, more conventional

supply voltages can be used, but the

ampliﬁers must have higher current

driving capability.

The limit on the turns ratio is

primarily a function of the sensitivity

of the receive circuitry. Step-up

transformers will, unfortunately, step-

down the signal received from the

phone line. Further attenuation of

the received signal by the transformer

in addition to the inherent transmis-

sion line attenuation can cause the

receiver to stop functioning. If this

occurs, the modem will disconnect

from the line.

A transformer should be selected

for a ﬂat, distortion-free frequency

response from 20kHz to 2MHz to cover

the full frequency spectrum for an

–20dBm

–120dBm0Hz 560kHz56kHz/DIV

10dBm/DIV

Figure 4. G.Lite training-up spectrum

Linear Technology Magazine • February 2000

DESIGN IDEAS

ADSL transmission. Minimal inser-

tion loss in the transformer over the

same frequency range is also desir-

able. Insertion loss, usually speciﬁed

in dBm, is power lost in the trans-

former. The driver ampliﬁer must

provide this additional power in order

to maintain the required signal power

level on the phone line.

Transformer

Termination Resistors

The two resistors (called back-termi-

nation resistors) shown between the

ampliﬁer outputs and the primary of

the transformer are inserted for two

reasons: to provide a means for

detecting the received signal and to

make the impedance of the modem

match the impedance of the phone

line. The receiver circuit is two differ-

ence ampliﬁers that provide gain to

the small signals that appear across

the termination resistors. The con-

nection and scaling of the input

resistors to the receiver ampliﬁers are

purposely set to provide a ﬁrst-order

cancellation of the simultaneously

occurring transmit signal. This

technique is called “echo cancellation”

and the circuit topology is called a “2-

wire to 4-wire hybrid” (the 2-wire

phone line interfaces with four wires,

the two differential driver lines and

the two receive signal lines). The can-

cellation of the transmitted signal from

the received signal path is not perfect.

Due to signal phase shifts and resis-

tor mismatching, a factor of 6dB to

20dB of attenuation is typical, with

higher frequencies being cancelled

less. The amount of transmitted sig-

nal that remains is cancelled digitally

by DSP echo-canceling algorithms.

The value of the termination resis-

tors is a function of the line impedance

and the transformer turns

ratio. The turns ratio, n, is

deﬁned by the number of

turns of the winding con-

nected to the phone line

(the secondary) divided by

the number of turns of the

driver side winding (the primary). To

make the modem impedance match

the line impedance, the total imped-

ance across the primary winding is

determined by the following

relationship:

PRIMARY

= Z

LINE

To provide balanced drive to the

primary of the transformer, so that

each power ampliﬁer shares the work

load evenly, each termination resis-

tor is set to a value of one-half of

PRIMARY

This value of termination resis-

tance on the primary is also optimal

for receiving maximum power from

the line. The received signal on the

phone line, e

, driving the secondary

through the line impedance, Z

LINE

(nominally 100Ω) will develop signal

power in the primary per the follow-

ing relationship:

RECEIVED PRIMARY POWER =

RX2

LINE2

• R

PRIMARY

+ 2 • Z

LINE

• R

PRIMARY

which is also at a maximum when

PRIMARY

= Z

LINE

While the termination resistors

serve an important purpose, they also

create signiﬁcant signal and power

loss. With the resistors set to their

proper value, one-half of the power

delivered by the ampliﬁers is dissi-

pated in these resistors. To deliver

100mW of signal power to the phone

line, for example, requires the driver

ampliﬁers to output at least 200mW

of power.

Why Differential Drive?

Two ampliﬁers conﬁgured as a differ-

ential gain stage are typically used to

provide signal drive to the primary of

the transformer. There are two rea-

sons for this conﬁguration: it reduces

the supply voltage to the ampliﬁers by

a factor of two and also cancels any

even harmonic distortion nonlinear-

ity contributed by the ampliﬁers.

With single-ended drive of the pri-

mary, the supply voltage for the

ampliﬁer must be large enough to

provide the full peak-to-peak signal

swing of the DMT signal placed on to

the phone line. With differential drive,

each ampliﬁer contributes just one-

half of the peak signal amplitude;

therefore, the total supply voltage is

only one half the peak-to-peak volt-

age level placed on the line. This is

shown conceptually in Figure 5. This

reduction in supply voltage allows

the use of the standard power supply

voltages available in computers for

the high speed DSL modem card.

A differential ampliﬁer will ideally

cancel all even harmonic distortion

products. This is due to the applica-

tion of a signal that is the difference

between two signals, one signal being

–

22V

–22V

+EIN

–EIN

1:1

RBT

44VP-P

22VP-P ZLINE

22VP-P

–

11V

–11V

–

O+

22V

P-P

22V

P-P

–

22V

P-P

LINE

22V

P-P

1:1

O DIFF

11V

P-P

Figure 5a. A single-ended driver requires a high supply voltage to produce

the desired peak-to-peak swing of the DMT signal on the phone line.

Figure 5b. A differential driver achieves the same swing

with half the supply voltage of the single-ended driver.

Linear Technology Magazine • February 2000

DESIGN IDEAS

an inverted version of the other, to the

primary of the transformer. This can

be shown mathematically by repre-

senting the linear output signals of

the ampliﬁers as a power series:

Each output is a linear function of

the input signal:

VO = f(EIN)

which, represented as a power series,

VO = a1EIN + a2EIN2 + a3EIN3 + a4EIN4 +

a5EIN5 …

The inputs to the differential

ampliﬁer are E

IN+

and E

IN–

; therefore:

VO(+) = a1EIN + a2EIN2 + a3EIN3 + a4EIN4

+ a5EIN5 …

and

VO(–) = –a1EIN + a2EIN2 – a3EIN3 +

a4EIN4 – a5EIN5 …

The differential output of the ampli-

ﬁer stage is

VODIFF = VO(+) – VO(–)

therefore:

ODIFF

= 2a

+ 2a

IN3

+ 2a

IN5

+ …

which does not contain any even har-

monic products. The complete

cancellation of even harmonics

depends on the gain and phase-shift

matching of the ampliﬁers and the

signal paths over the frequency range

of concern.

Bandwidth, Slew Rate

and Noise Requirements

of the Ampliﬁers

High speed ampliﬁers with band-

widths much wider than the

transmitted signal bandwidth should

be used to maintain ﬂat gain and

constant phase shift of the DMT sig-

nals. The amount of gain required in

the transmit power ampliﬁers is

dependant on the signal levels pro-

vided by the analog front end (AFE),

which is a circuit block that provides

the interface between the line trans-

ceiver and the DSP processor. The

gain must be sufﬁcient to put the

proper amount of power on the phone

line for the DSL standard being imple-

mented (refer to Table 1). The

maximum frequency to be processed

by the ampliﬁers is also a function of

the standard being applied; this, in

turn, sets the minimum bandwidth

required. As a rule of thumb, the gain

bandwidth product speciﬁcation of

the ampliﬁers used should be at least

ﬁve times the required value to

maintain linear accuracy over the

transmitted signal spectrum. This

speciﬁcation provides an indication

of the distortion-free, high speed sig-

nal processing capability of the

ampliﬁer. For example, a Full Rate

ADSL downstream transmitter with a

gain of four and a maximum frequency

of 1.1MHz requires a gain-bandwidth

of 4.4MHz; therefore, ampliﬁers

should be chosen that have a gain-

bandwidth speciﬁcation of at least

22MHz. Parts with higher bandwidths

are even better for preserving excel-

lent gain and phase shift matching

over the 1.1MHz band of operation.

The slew rate of the ampliﬁers used

is not so critical, because the signal

spectrum is typically band-limited by

ﬁlter networks. The step response of

these ﬁlters slows down the rise and

fall times of the signals presented to

the ampliﬁers. A slew rate of at least

10V/µs is usually adequate. How-

ever, very fast slew rates are essentially

free in wideband ampliﬁer designs.

Internal biasing currents charging

and discharging internal compensa-

tion capacitors and individual node

capacitances of the circuit determine

the slew rate of an ampliﬁer. To pro-

duce a high frequency ampliﬁer,

circuit-biasing currents are increased

to minimize impedances at critical

circuit nodes and small geometry tran-

sistor structures are used to minimize

stray capacitance. This results in very

fast slew rates for the ampliﬁer as an

inherent byproduct of a high gain-

bandwidth product characteristic.

Faster slew rates ensure very fast

dynamic response and reduced sig-

nal distortion.

Low noise characteristics, together

with a wide gain bandwidth capabil-

ity are most important for the

ampliﬁers used in the receive cir-

cuitry. On a typical connection, a

phone line will have a noise ﬂoor

0 200 400 600 800 1000 1200

FREQUENCY (kHz)

POWER SPECTRAL DENSITY (dBm/Hz)

–50

–60

–70

–80

–90

–100

–110

–120

-130

–140

–150

9000'

12,000'

15,000'

21,000'

18,000'

2-BIT THRESHOLD (DMT)

–140dBm/Hz BACKGROUND NOISE

power spectral density of –140dBm/

Hz. This is equivalent to a noise volt-

age of 31nV/√Hz. The receiver

ampliﬁer should have a noise spec-

tral density in the band between

20kHz and 1MHz lower than this level.

Linear Technology provides several

fast ampliﬁers with noise voltage spec-

tra of less than 10nV/√Hz. Lower noise

is required in inverse proportion to

the turns ratio of the transformer

used to address the attendant reduc-

tion in both the noise ﬂoor and the

received signal.

The amount of signal received is a

function of the length of phone line

used to make the connection, as

shown in Figure 6. This is referred to

as the loop length. Very long loop

lengths can severely attenuate the

transmitted signal, particularly at the

higher channel frequencies. The

greater the attenuation of a channel,

the fewer data bits can be transmitted

in that channel, which affects the

overall communication data rate. As

a rule of thumb, a received signal-to-

noise ratio of 18dB allows two data

bits to be used in a channel. With

each 3dB of additional signal above

the noise ﬂoor, an extra bit of data can

be used. With 45dB to 50dB signal-

to-noise ratio, a full 12 bits of data

can be exchanged in one channel

frequency.

The next installment in this series

will provide the design calculations to

determine the minimum requirements

for supply voltage, current drive

capability and resultant power con-

sumption and dissipation. In addition,

heat management issues will be

discussed.

Figure 6. Typical received signal power

spectral density, AWG26 loops

Linear Technology Magazine • February 2000

DESIGN INFORMATION

New Continuous-Time Lowpass Filters

Feature Differential I/O, Linear Phase

and Wide Dynamic Range

by Michael Kultgen and Nello Sevastopoulos

The new LTC1565-XX family of

monolithic, continuous-time lowpass

ﬁlters is tailored for data communica-

tion systems requiring band-limiting

in their differential signal paths.

Because it eliminates the need for

external components, The LTC1565-

XX offers a compact solution to high

frequency, differential ﬁlter require-

ments. Each LTC1565-XX is

optimized for a single cutoff frequency.

The ﬁrst member of the LTC1565-XX

family, the LTC1565-31, is a 7th order,

linear-phase lowpass ﬁlter with a

650kHz cutoff frequency. It is tai-

lored primarily for CDMA cellular base

stations or any other application

requiring linear-phase lowpass ﬁl-

tering with a cutoff frequency in the

vicinity of 650kHz.

Figure 1 shows the extremely

simple hookup of the LTC1565-31.

The ﬁlter is packaged in an SO-8 and

it operates on a single 5V supply.

Aside from power supply and analog

ground bypass capacitors, no other

external components are required.

The device is designed to be driven

differentially, yet, for single-ended

applications, either input can be

shorted to the analog ground (pin 3).

Differential signals with a common

mode range of 1.3V to 2.7V and up to

P-P

amplitude can be DC coupled

into the input pins of the ﬁlter with-

out any signiﬁcant performance

degradation. The maximum dynamic

range (THD plus S/N ratio) is 78dB.

This is obtained with a 2.5V

P-P

differ-

ential signal biased at a 2VDC

common mode voltage.

The ﬁlter output should be taken

differentially, as indicated in Figure

1. The common mode voltage of the

differential output is the voltage of

pin 3, which is one-half of the power

supply of the ﬁlter. Figure 2 shows the

frequency response of the ﬁlter, which

features an almost ﬂat group delay in

the filter’s passband. The amplitude

–

GND

–

OUT

–

SHDN

–

OUT

–

0.01µF0.01µF

0.1µF0.1µF

SHUTDOWN

LTC1565-31

–20

–40

–60

–80

–100

2.0

1.8

1.6

1.4

1.2

1.0

0.8

10k 100k 1M 10M

FREQUENCY (Hz)

ATENUATION (dB)

DELAY (µs)

ATTENUATION

GROUP DELAY

response has a –3dB gain at 650kHz,

–20dB at 1MHz and in excess of

–70dB at 2MHz.

The out-of-band rejection of the

ﬁlter is quite impressive. Depending

on the input signal amplitude, the

stopband attenuation above 3MHz is

between 80dB and 100dB (see Figure

2). The LTC1565-31 achieves these

attenuation levels without preﬁltering.

This is highly desirable in applica-

tions where strong interfering signals

are present at the inputs of the ﬁlter.

Other responses and conﬁgura-

tions will be available in the near

future. Contact LTC marketing for

details regarding other cutoff

frequencies.

Figure 1. The LTC1565-31 is extremely simple to hook up.

Figure 2. LTC1565-31 frequency response

for

the latest information

on LTC products,

visit

www.linear-tech.com

DESIGN INFORMATION

New Continuous-Time Lowpass

Filters Feature Differential I/O,

Linear Phase and Wide Dynamic

Range ..................................... 32

Michael Kultgen and Nello Sevastopoulos

LTC1546 Multiprotocol Chip

Simpliﬁes NET1-, NET2- and TBR2-

Compliant Serial Interfaces

............................................... 33

Dan Eddleman

LTC2050, Zero-Drift Operational

Ampliﬁer in SOT-23 Package

Minimizes Board Area without

Compromising Specs............... 34

David Hutchinson

Linear Technology Magazine • February 2000

DESIGN INFORMATION

LTC1546 Multiprotocol Chip Simpliﬁes

NET1-, NET2- and TBR2-Compliant

Serial Interfaces by Dan Eddleman

The LTC1546 multiprotocol trans-

ceiver simpliﬁes network interface

design and frees up valuable PC board

real estate. Operating from a single

5V supply, the LTC1546 and LTC1544

form a complete, software-selectable

DTE or DCE interface port that sup-

ports the V.28 (RS232), V.35, V.36,

X.21, RS449, EIA530 and EIA530-A

protocols, including all of the neces-

sary cable termination. With these

two chips, the physical layer of a

NET1-, NET2- and TBR2-compliant

LTC1544

LTC1546

DTE_TXD/DCE_RXD

DTE_SCTE/DCE_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_LL/DCE_LL

DCE/DTE

GND

1µF

3.3µF

SCTE B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

LL A

SHIELD

DB-25

CONNECTOR

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

LL A

DCD A

DCD B

DTR A

DTR B

CHARGE

PUMP

INVERT 15

C11

1µF

C10

1µFC9

1µF

DCE/DTE

D1 T

TXD A

TXD B

TXC A

RXC A

RXD A

TXC B

RXC B

RXD B

TXC A

SCTE A

TXD A

TXC B

SCTE B

TXD B

SCTE A

RXC B

RXD A

DTE DCE

RXD B

RXC A

interface can be implemented in less

than 3cm

In a typical application (see Figure

1), the 3-driver/3-receiver LTC1546

multiprotocol serial transceiver/cable

terminator handles the clock and data

signals, and the 4-driver/4-receiver

LTC1544 multiprotocol transceiver

handles the control signals. The mode

pins, M0, M1 and M2, select the active

protocol and termination (see Table

1) and the DCE/DTE pin selects DTE

or DCE mode. PC board layout con-

sists of routing the pins of an LTC1546

and an LTC1544 to the connector and

placing bypass and charge pump ca-

pacitors (see Figure 1). The LTC1546/

LTC1544 chipset is appropriate for

most multiprotocol applications. Sys-

tems that additionally require LL (local

loop-back), RL (remote loop-back), TM

(test mode) or RI (ring indicate) sig-

nals should use the 5-driver/

5-receiver LTC1545 multiprotocol

transceiver in place of the LTC1544.

The LTC1546 is pin compatible

with the popular LTC1543 multi-

protocol transceiver and has the added

feature of on-chip cable termination.

Most previous applications used an

LTC1543 for the clock and data trans-

ceivers and an LTC1344A for the

necessary cable termination. With the

5451CTL/ emaNedoM2M1M0M

desUtoN000

A035-AIE001

035-AIE010

12.X011

53.V100

63.V/944SR101

82.V/232SR110

elbaCoN111

Table 1. Mode-pin functions

LTC1546

Figure 1. LTC1544/LTC1546 software-selectable multiprotocol DCE/DTE port

continued on page 35

Linear Technology Magazine • February 2000

DESIGN INFORMATION

LTC2050, Zero-Drift Operational

Ampliﬁer in SOT-23 Package

Minimizes Board Area without

Compromising Specs by David Hutchinson

Introduction

The LTC2050 is a zero-drift opera-

tional ampliﬁer available in the 5- or

6-lead SOT-23 and SO-8 packages. It

minimizes board area while providing

uncompromising DC performance,

including 3µV (max) DC offset and

30nV/°C (max) DC offset drift. It

operates from a 2.7V supply while

still supporting 5V applications. The

power consumption is 800µA and the

versions in the 6-lead SOT-23 and

SO-8 packages offer power shutdown.

Other key features of this new

device include:

❏Small 5- or 6-lead SOT-23

package

❏2.7V operation

❏3µV maximum offset voltage

❏30nV/°C maximum offset voltage

drift

❏1.5µV

P-P

typical noise (0.1Hz to

10Hz)

❏More than 130dB of DC PSRR,

CMRR and gain (typical)

❏Output swings rail-to-rail with

1kΩ loads

❏Extended common mode input

range

❏Power shutdown below 10µA

(available in 6-lead SOT-23 and

SO-8)

Extended Input Common

Mode Range with

Uncompromising CMRR

At room temperature, with the input

common mode level at mid-supplies,

the LTC2050 typically has 0.5µV of

input-referred offset (input-referred

offset is guaranteed to be less than

±3µV). To ensure this DC accuracy

over the common mode input range,

the LTC2050 has exceptionally high

CMRR over a wide common mode

range from the negative supply typi-

cally to within 0.9V of the positive

rail, as shown in Figure 1. For

example, as the input is varied over

the entire common mode range, the

input referred offset changes typi-

cally by less than 0.4µV at 5V and

less than 0.3µV at 3V. Figure 2 shows

the CMRR over frequency, illustrat-

ing more then 80dB at 1kHz.

Similar levels of PSRR (typically

less then 0.1µV of offset per volt of

supply change) and the near-zero tem-

perature drift ensure that the offset

does not exceed 5µV over the entire

supply and commercial temperature

range.

Rail-to-Rail Output Drive

with a 1k Load

The LTC2050 maintains its DC char-

acteristics while driving resistive loads

requiring source or sink current as

high as 5mA with a 3V or 5V supply.

Figure 3 shows the op amp rail-to-rail

swing versus output resistance load-

ing. With a 1k or 5k load, the output

typically swings to within 100mV or

30mV, respectively, of the rails.

Clock Feedthrough

Virtually Eliminated

The LTC2050 uses autozeroing

circuitry to achieve its zero-drift off-

set and other DC speciﬁcations. In

the LTC2050, the clock used for

autozeroing is typically 7.5kHz. The

term clock feedthrough is used to

indicate visibility of this clock in the

op amp output spectrum. There are

typically two types of clock feed-

through in autozeroed op amps such

as the LTC2050.

140

120

100

012345

COMMON MODE VOLTAGE (V)

CMRR (V)

VS = 3V VS = 5V

140

120

100

1 10 100 1k 10k 100k

FREQUENCY (Hz)

CMRR (V)

= 3V OR 5V

= 0.5V

P-P

00246810

LOAD RESISTANCE (kΩ)

OUTPUT SWING (V)

VS = 3V

VS = 5V

RL TO GND

Figure 1. LTC2050 DC common mode

rejection ratio vs common mode input

voltage

Figure 2. LTC2050 common mode

rejection ratio vs frequency

Figure 3. LTC2050 output voltage swing

vs load resistance

Linear Technology Magazine • February 2000

DESIGN INFORMATION

introduction of the LTC1546, the

LTC1344A is no longer required. In

fact, in most existing designs, the

LTC1543 can be replaced by an

LTC1546, and the LTC1344A can be

removed without any changes to the

PC board. In new designs, the

LTC1546 will simplify PC board lay-

The ﬁrst source is caused by the

settling of the internal sampling

capacitor and is input referred; that

is, it is multiplied by the closed loop

gain of the op amp. This form of clock

feedthrough is independent of input

source resistance or gain setting resis-

tors. Figure 4 shows the spectrum of

the LTC2050 with a closed loop gain

of –100 with R2 = 100k, and R1 = R

= 1k. There is a residue clock

feedthrough of less than 1µV

RMS

(input-referred) at 7.5kHz. This very

low clock feedthough is achieved in

the LTC2050 by internal circuitry that

improves settling of the internal auto-

zero storage capacitors. Also in Figure

4, the clock feedthrough of the

LTC2050 is compared with that of the

very popular LTC1050.

The second form of clock feed-

through appears when the input has

a large source resistance or the gain-

setting resistors are large. In this

case, the charge injection caused by

the internal MOS switches creates

input-referred clock feedthrough cur-

rents that are multiplied by the

impedance seen at the input termi-

nals of the op amp. This form of clock

feedthrough is not signiﬁcant in the

LTC2050 when R

and R1 in Figure 4

are below approximately 10k. Placing

a capacitor across R2 reduces either

form of clock feedthrough by lowering

the bandwidth of the closed-loop

response.

100µV

RMS

/DIV

1mV

RMS

0mV

RMS

100µV

RMS

/DIV

1mV

RMS

0mV

RMS

1kHz/DIV100Hz 10.1kHz

LTC2050

BW = 95Hz

LTC1050

BW = 95Hz

–

Conclusion

The LTC2050 is the latest member of

Linear Technology’s family of zero-

drift operational ampliﬁers. It provides

small packaging while still maintain-

ing precision DC speciﬁcations. In

addition, it operates at supplies as

low as 2.7V and includes a power

shutdown in the 6-lead SOT-23

package.

Figure 4. Output spectrum with a gain of 100; R2 = 100k; R1 = R

= 1k

out and reduce the required footprint

compared to the LTC1543/LTC1544

solution.

The LTC1546/LTC1544 chipset

has been tested by TUV Telecom Ser-

vices, Inc. and has been found to be

compliant with the NET1, NET2 and

TBR2 requirements. Test reports are

available from LTC or TUV upon

request (NET1 and NET2 report

NET2/091301/99; TBR2 report

CTR2/091301/99).

LTC1546/LTC1545, continued from page 33

http://www.linear-tech.com/ezone/zone.html

Articles, Design Ideas, Tips from the Lab…

For more information on parts featured in this issue, see

http://www.linear-tech.com/go/ltmag

For more information on parts featured in this issue, see

http://www.linear-tech.com/go/ltmag

Linear Technology Magazine • February 2000

NEW DEVICE CAMEOS

LTC1706-81 5-Bit Desktop

VID Voltage Controller

Achieves ±0.25% Accuracy

for 1.3V to 3.5V

Microprocessor Supplies

Intel’s Pentium

microprocessors are

breaking through speed barriers,

thanks, in part, to a tightly regulated

power supply that’s capable of pro-

ducing hundreds of amps of current

at various VID levels. The Pentium

processors’ supply voltage require-

ments change with the various clock

speed options. The LTC1706-81, a

5-bit desktop VID voltage program-

mer, meets this need by adjusting the

outputs of a whole family of LTC DC/

DC converters to provide precise sup-

ply voltages to these Pentium

processors. Depending on the state

of the ﬁve VID inputs, a +0.25% accu-

rate output voltage from 1.3V to 2.05V

or from 2.1V to 3.5 V can be pro-

grammed in 50mV or 100mV steps,

respectively. This is fully compliant

with the Intel Pentium Processor

Desktop VID Speciﬁcation (VRM 8.4).

The LTC1706-81 comes in the

small 10-lead MSOP package. It con-

sumes practically zero current (only

device leakage) when all ﬁve inputs

are high; each grounded VID input

adds only 68µA of input current in a

3.3V system. For extremely high cur-

rent applications, such as servers

and supercomputers, just one

LTC1706-81 can program up to six

LTC1629 PolyPhase, high efﬁciency,

step-down DC/DC controllers to com-

plete an extremely compact, powerful,

programmable power supply that uses

only surface mount components.

In addition to the LTC1629, the

LTC1706-81 also works equally well

with the LTC1735, the LTC1702, the

LTC1628 and other LTC DC/DC con-

verters with onboard 0.8V references.

LTC1664: Quad Micropower

10-Bit Voltage Output DAC

Saves Power and Space

The LTC1664 is a quad, micropower,

10-bit, rail-to-rail voltage output DAC

with Sleep mode. Operating on a single

2.7V–5.5V supply rail, the LTC1664

has the lowest power consumption of

any available quad 10-bit voltage

output DAC. Each buffered DAC

draws just 59µA of supply current at

5V (43µA at 3V), yet it is capable of

supplying DC output currents in

excess of 5mA. Sleep mode operation

further reduces total supply-plus-ref-

erence current to just 1µA.

The LTC1664 is available in LTC’s

tiny 16-lead Narrow SSOP package,

delivering outstanding board-space

efﬁciency with four DAC channels in

the space of an SO-8; required board

area is just 0.012in

per DAC. Each of

the four output ampliﬁers is stable

driving capacitive loads up to 1000pF,

so designers need not worry about

the capacitance of long board traces.

The LTC1664 is guaranteed mono-

tonic; differential nonlinearity (DNL)

is typically ±0.2LSB (±0.75LSB

maximum) over the full industrial

temperature range.

The 3-wire serial interface uses a

16-bit input word comprising four

control bits, ten input-code bits and

two don’t-care bits. Asynchronous

CLR, power-on reset and daisy-chain

capability are also provided. It is pos-

sible to keep one or more chips in a

daisy chain in continuous Sleep mode

by giving the Sleep instruction to these

chips each time the active chips in the

chain are updated. The LTC1664 is

also available in a fully software- and

pin-compatible octal version, the

LTC1660.

The LTC1664 has a reference-to-

output gain of one and the Reference

pin can be tied to V

for ratiometric,

0V-to-V

output. Other voltage out-

put DACs either use a gain of two,

thus requiring a separate reference,

or cannot reach the upper rail when

using a gain of one. Moreover, the

Reference input has constant imped-

ance over all codes (70k minimum),

unlike many units that have input

impedance that varies greatly with

code. This constant reference imped-

ance causes the linearity of the

LTC1664 to be insensitive to the

source impedance of the external volt-

age reference, eliminating the need

for low impedance buffer ampliﬁers.

Ultralow supply current, power-

saving Sleep mode and extremely

compact size make the LTC1664 ideal

for battery-powered devices, while its

ease of use, high performance and

wide supply range make it an excel-

lent choice for general-purpose voltage

adjustment and trimmer potentiom-

eter applications.

LTC1657: Micropower,

16-Bit, Parallel, Voltage

Output DAC in 28-Pin SSOP

Package Saves Power

and Board Space

Linear Technology introduces its ﬁrst

buffered 16-bit, parallel, voltage out-

put DAC. The LTC1657 includes a

deglitched rail-to-rail output ampli-

ﬁer, an internal 2.048V reference and

a double-buffered parallel digital

interface for standalone performance.

The LTC1657’s architecture guaran-

tees ±1LSB maximum differential

nonlinearity (DNL) over temperature

to provide true 16-bit performance.

The INL, full-scale and offset are all

laser trimmed to maintain accuracy

over the full operating temperature

range. The device operates on a single

supply of 4.5V to 5.5V and the typical

power supply current is 650µA. The

LTC1657 is similar to Linear

Technology’s LTC1450 12-bit voltage-

output DAC family, allowing an easy

upgrade path.

The LTC1657’s output ampliﬁer

provides a voltage output settling time

of 20µs to within 0.0015% for a full-

scale step. The rail-to-rail voltage

output can sink or source 5mA over

the entire operating temperature

range, to within 500mV of the positive

supply voltage or ground. The output

stage is equipped with a deglitcher

New Device Cameos

Authors can be contacted

at (408) 432-1900

Pentium is a registered trademark of Intel Corp.

Linear Technology Magazine • February

2000

NEW DEVICE CAMEOS

that results in a midscale glitch

impulse of 8nV-s. The full-scale out-

put can be one or two times the

reference voltage, depending on how

the X1/X2 pin is connected. The

LTC1657 is available in 28-pin SSOP

and PDIP packages.

LT1767: Monolithic

1.25MHz, 1.5A Buck

Converter in MS8

Operates Over a 2.7V

to 25V Input Range

The LT1767 is LTC’s latest high speed,

high efﬁciency, monolithic buck con-

verter in a very space efﬁcient MS8

package. The LT1767 adds features

not found on previous-generation

monolithic regulators. Its monolithic

approach results in few external com-

ponents and a straightforward board

layout. The high 1.25MHz switching

frequency reduces the values of in-

put/output ﬁltering components and

allows the use of low value chip in-

ductors, reducing overall system cost.

Using the Sync pin, the operating

frequency can be increased to as high

as 2MHz, further easing system noise

ﬁltering requirements.

Operating from 2.7V to 25V, the

LT1767 can utilize inputs ranging

from 24V wall adapters, to pre-

regulated 12V, 5V or 3.3V supplies, to

batteries. Undervoltage lockout can

be implemented using the accurate

1.3V threshold of the Shutdown pin.

Additionally, an internal 2.6V under-

voltage lockout ensures predictable

operation near minimum input volt-

ages. Both ﬁxed and adjustable output

voltage versions will be available. The

adjustable version has a feedback

reference voltage of 1.2V, simplifying

low output voltage supply design.

High efﬁciency is the result of the

1.5A, 200mΩ internal switch and low

900µA quiescent current. The

LT1767’s efﬁciency permits a rela-

tively high 1.5A switch current to be

used in a small MS8 package. Efﬁ-

ciency is high even at lower output

loading because of the LT1767’s low

quiescent current. With the S/D pin

pulled to ground, supply current falls

to only 6µA.

LTC1694-1 SMBus/I

Accelerator Eliminates

Data Integrity Problems

The LTC1694-1 is an active pull-up

for SMBus and I

systems. It is

designed to eliminate data integrity

problems and enhance transmission

speed under all speciﬁed loading con-

ditions. The LTC1694-1 allows

multiple device connections or a

longer, more capacitive interconnect,

without compromising rise times or

bus performance, by supplying a high

pull-up current of 2.2mA to slew the

SMBus or I

C lines during positive

bus transitions. During negative bus

transitions or steady DC levels, the

LTC1694-1 sources zero current.

External resistors, one on each bus

line, trigger the LTC1694-1 during

positive bus transitions and set the

pull-down current level. These resis-

tors determine the logic low DC level,

set the fall time for negative bus tran-

sitions and permit ﬁne tuning of rise

time vs fall time.

The SMBus and I

C communica-

tion protocols employ open-drain

drives with resistive or current-source

pull-ups. These protocols allow mul-

tiple devices to drive and monitor the

bus without bus contention. The

simplicity of resistive or ﬁxed-cur-

rent-source pull-ups is offset by the

resultant slow rise times if bus

capacitance is high. Rise times are

improved by using lower value pull-

up resistors or higher value current

sources, but the additional current

increases the low state bus voltage,

decreasing noise margins. Slow rise

times seriously affect data reliability,

enforcing a maximum practical bus

speed well below the established maxi-

mum transmission speed of 100kHz.

Faster transition times can be

obtained or higher capacitance driven

by simply paralleling LTC1694-1

devices. Paralleling multiple

LTC1694-1s has no effect on the logic

low DC level or the fall time. The

LTC1694-1 is available in a 5-lead

SOT-23 package, which occupies the

same area as two surface mount

resistors. The LTC1694 is a compan-

ion part to the LTC1694-1 that inte-

grates the DC pull-up current for

simplicity. The LTC1694 and the

LTC1694-1 effectively eliminate

SMBus and I

C data integrity prob-

lems and increase the maximum

system transmission speed.

On-Chip Power-Good

Indicator in LTC1628PG and

LTC1629PG Saves Board

Space and Lowers Total Cost

The power-good indicator in the new

LTC1628PG and LTC1629PG elimi-

nates the necessity of adding

comparators, biasing resistors,

decoupling capacitors and a voltage

reference to circuits using these third

generation DC/DC controllers. These

parts have a PGOOD pin that outputs

a logic low when the output voltage

exceeds ±7.5% of the setpoint. Both

outputs are monitored by the

LTC1628PG, so the PGOOD pin indi-

cates a fault when either output

voltage is outside the ±7.5% window.

The new PG parts are exactly like

the original LTC1628 and LTC1629

except that the PGOOD pin replaces

the FLTCPL pin on the LTC1628 and

the AMPMD pin on the LTC1629. The

FLTCPL function in the LTC1628PG

is programmed so that the FCB pin

controls both outputs and an over-

current fault on either output will

latch-off both outputs. Overcurrent

latch-off can be defeated on the

LTC1628PG in the same manner as

on the LTC1628. The AMPMD func-

tion in the LTC1629PG is programmed

so that the differential ampliﬁer is

conﬁgured as a precision instrumen-

tation ampliﬁer to provide true remote

sensing of the voltage across the load.

Other than preprogramming the

FLTCPL and AMPMD functions, all of

the features of the LTC1628 and

LTC1629 are available in the new PG

parts. The high efﬁciency, PolyPhase

switching of both LTC1628PG and

LTC1629PG reduces the number of

input capacitors and allows the

LTC1629PG to control 30A to 45A

without a heat sink, using smaller

inductors and less output capaci-

tance than competing circuits.

C is a trademark of Philips Electronics N.V.

Linear Technology Magazine • February 2000

NEW DEVICE CAMEOS

LTC1643L-1 Hot Swaps PCI-

Bus without the –12V Supply

The LTC1643 Hot Swap controller

allows a board to be safely inserted

into and removed from a live PCI-Bus

slot containing 5V, 3.3V and ±12V

supplies. A new version, the

LTC1643L-1, loosens the tolerances

on the +12V and –12V supplies. In

systems where the –12V supply has

been eliminated, the –V

input pin

may simply be grounded without

affecting the operation of the Hot Swap

controller.

All other familiar LTC1643 Hot

Swap features are retained, including

the narrow 16-pin SSOP package and

pinout, programmable foldback cur-

rent limit with circuit breaker, fault

and power-good outputs and pro-

grammable supply ramp rates,

allowing insertion into a live back-

plane without disturbing the supply

bus. A new data sheet combining the

speciﬁcations for the LTC1643L,

LTC1643H, and LTC1643L-1 has been

printed and is available for down-

loading from the LTC web site.

LTC1707 Monolithic

Synchronous Stepdown

Regulator Works with

One or Two Li-Ion Batteries

The LTC1707 is a new addition to a

growing family of monolithic step-

down regulators optimized for use

with Li-Ion batteries. New features

include a ±1%, 1.19V reference out-

put, capable of sourcing 100µA, and

selectable low load current operating

modes (Burst Mode operation or pulse

skipping mode). Pulse skipping allows

the LTC1707 to maintain a constant

operating frequency down to low out-

put currents, reducing noise and RF

interference, but without the quies-

cent current penalty of forced

continuous operation.

For further information on any

of the devices mentioned in this

issue of Linear Technology, use

the reader service card or call

the LTC literature service

number:

1-800-4-LINEAR

Ask for the pertinent data sheets

and Application Notes.

For more information on parts featured in this issue, see

http://www.linear-tech.com/go/ltmag

For more information on parts featured in this issue, see

http://www.linear-tech.com/go/ltmag

Authors can be contacted

at (408) 432-1900

http://www.linear-tech.com/ezone/zone.html

Articles, Design Ideas, Tips from the Lab…

The LTC1707, like its predecessor

the LTC1627, is a monolithic, current

mode, synchronous step-down

regulator using a ﬁxed frequency

architecture. The current mode

architecture gives the LTC1707

excellent load and line regulation,

and Burst Mode operation provides

high efﬁciency at low load currents.

100% duty cycle provides low dropout

operation, which extends operating

time in battery-operated systems. The

operating frequency is internally set

at 350kHz and can be externally syn-

chronized at frequencies up to

550kHz. Burst Mode operation is

inhibited during external clock syn-

chronization or when the SYNC/

MODE pin is pulled low. The internal

synchronous switch increases efﬁ-

ciency and eliminates the need for an

external Schottky diode, saving com-

ponents and board space. The

LTC1707 is available in an 8-lead SO

package.

Linear Technology Magazine • February 2000

DESIGN TOOLS

Technical Books

1990 Linear Databook, Vol I —This 1440 page collec-

tion of data sheets covers op amps, voltage regulators,

references, comparators, ﬁlters, PWMs, data conver-

sion and interface products (bipolar and CMOS), in both

commercial and military grades. The catalog features

well over 300 devices. $10.00

1992 Linear Databook, Vol II — This 1248 page supple-

ment to the 1990 Linear Databook is a collection of all

products introduced in 1991 and 1992. The catalog

contains full data sheets for over 140 devices. The 1992

Linear Databook, Vol II is a companion to the 1990

Linear Databook, which should not be discarded.

$10.00

1994 Linear Databook, Vol III —This 1826 page supple-

ment to the 1990 and 1992 Linear Databooks is a

collection of all products introduced since 1992. A total

of 152 product data sheets are included with updated

selection guides. The 1994 Linear Databook Vol III is a

companion to the 1990 and 1992 Linear Databooks,

which should not be discarded. $10.00

1995 Linear Databook, Vol IV —This 1152 page supple-

ment to the 1990, 1992 and 1994 Linear Databooks is a

collection of all products introduced since 1994. A total

of 80 product data sheets are included with updated

selection guides. The 1995 Linear Databook Vol IV is a

companion to the 1990, 1992 and 1994 Linear Databooks,

which should not be discarded. $10.00

1996 Linear Databook, Vol V —This 1152 page supple-

ment to the 1990, 1992, 1994 and 1995 Linear Databooks

is a collection of all products introduced since 1995. A

total of 65 product data sheets are included with updated

selection guides. The 1996 Linear Databook Vol V is a

companion to the 1990, 1992, 1994 and 1995 Linear

Databooks, which should not be discarded. $10.00

1997 Linear Databook, Vol VI —This 1360 page supple-

ment to the 1990, 1992, 1994, 1995 and 1996 Linear

Databooks is a collection of all products introduced

since 1996. A total of 79 product data sheets are

included with updated selection guides. The 1997 Linear

Databook Vol VI is a companion to the 1990, 1992,

1994, 1995 and 1996 Linear Databooks, which should

not be discarded. $10.00

1999 Linear Data Book, Vol VII — This 1968 page

supplement to the 1990, 1992, 1994, 1995, 1996 and

1997 Linear Databooks is a collection of all product data

sheets introduced since 1997. A total of 120 product

data sheets are included, with updated selection guides.

The 1999 Linear Databooks is a companion to the

previous Linear Databooks, which should not be dis-

carded. $10.00

1990 Linear Applications Handbook, Volume I —

928 pages full of application ideas covered in depth by

40 Application Notes and 33 Design Notes. This catalog

covers a broad range of “real world” linear circuitry. In

addition to detailed, systems-oriented circuits, this hand-

book contains broad tutorial content together with liberal

use of schematics and scope photography. A special

feature in this edition includes a 22-page section on

SPICE macromodels. $20.00

1993 Linear Applications Handbook, Volume II —

Continues the stream of “real world” linear circuitry

initiated by the 1990 Handbook. Similar in scope to the

1990 edition, the new book covers Application Notes 40

through 54 and Design Notes 33 through 69. References

and articles from non-LTC publications that we have

found useful are also included. $20.00

1997 Linear Applications Handbook, Volume III —

This 976 page handbook maintains the practical outlook

and tutorial nature of previous efforts, while broadening

topic selection. This new book includes Application

Notes 55 through 69 and Design Notes 70 through 144.

Subjects include switching regulators, measurement

and control circuits, ﬁlters, video designs, interface,

data converters, power products, battery chargers and

CCFL inverters. An extensive subject index references

circuits in LTC data sheets, design notes, application

notes and

Linear Technology

magazines. $20.00

1998 Data Converter Handbook — This impressive 1360

page handbook includes all of the data sheets, applica-

tion notes and design notes for Linear Technology’s

family of high performance data converter products.

Products include A/D converters (ADCs), D/A convert-

ers (DACs) and multiplexers—including the fastest

monolithic 16-bit ADC, the 3Msps, 12-bit ADC with the

best dynamic performance and the ﬁrst dual 12-bit DAC

in an SO-8 package. Also included are selection guides

for references, op amps and ﬁlters and a glossary of data

converter terms. $10.00

Interface Product Handbook — This 424 page hand-

book features LTC’s complete line of line driver and

receiver products for RS232, RS485, RS423, RS422,

V.35 and AppleTalk

applications. Linear’s particular

expertise in this area involves low power consumption,

high numbers of drivers and receivers in one package,

mixed RS232 and RS485 devices, 10kV ESD protection

of RS232 devices and surface mount packages.

Available at no charge

Power Management Solutions Brochure — This 96

page collection of circuits contains real-life solutions for

common power supply design problems. There are over

70 circuits, including descriptions, graphs and perfor-

mance speciﬁcations. Topics covered include battery

chargers, desktop PC power supplies, notebook PC

power supplies, portable electronics power supplies,

distributed power supplies, telecommunications and

isolated power supplies, off-line power supplies and

power management circuits. Selection guides are pro-

vided for each section and a variety of helpful design

tools are also listed for quick reference.

Available at no charge.

Data Conversion Solutions Brochure␣ —␣ This 64 page

collection of data conversion circuits, products and

selection guides serves as excellent reference for the

data acquisition system designer. Over 60 products are

showcased, solving problems in low power, small size

and high performance data conversion applications—

with performance graphs and speciﬁcations. Topics

covered include ADCs, DACs, voltage references and

analog multiplexers. A complete glossary deﬁnes data

conversion speciﬁcations; a list of selected application

and design notes is also included.

Available at no charge

Telecommunications Solutions Brochure

—This 76

page collection of application circuits and selection

guides covers a wide variety of products targeted for

telecommunications. Circuits solve real life problems

for central ofﬁce switching, cellular phones, high speed

modems, base station, plus special sections covering

–48V and Hot Swap

applications. Many applications

highlight new products such as Hot Swap controllers,

power products, high speed ampliﬁers, A/D converters,

interface transceivers and ﬁlters. Includes a telecom-

munications glossary, serial interface standards, protocol

information and a complete list of key application notes

and design notes. Available at no charge.

Applications on Disk

FilterCAD™

2.0 CD-ROM — This CD is a powerful ﬁlter

design tool that supports all of Linear Technology’s high

performance switched capacitor ﬁlters. Included is Fil-

terView™, a document navigator that allows you to

quickly ﬁnd Linear Technology monolithic ﬁlter data

sheets, the FilterCAD manual, application notes, design

notes and

Linear Technology

magazine articles. It

does

not

have to be installed to run FilterCAD. It is not

necessary to use FilterView to view the documents, as

they are standard .PDF ﬁles, readable with any version

of Adobe

Acrobat

. FilterCAD runs on Windows

3.1

or Windows 95. FilterView requires Windows 95. The

FilterCAD program itself is also available on the web and

will be included on the new LinearView™ CD.

Available at no charge.

Noise Disk — This IBM-PC (or compatible) program

allows the user to calculate circuit noise using LTC op

amps, determine the best LTC op amp for a low noise

application, display the noise data for LTC op amps,

calculate resistor noise and calculate noise using specs

for any op amp. Available at no charge

SPICE Macromodel Disk — This IBM-PC (or compat-

ible) high density diskette contains the library of LTC op

amp SPICE macromodels. The models can be used with

any version of SPICE for general analog circuit simula-

tions. The diskette also contains working circuit examples

using the models and a demonstration copy of PSPICE™

by MicroSim. Available at no charge

SwitcherCAD™ — The SwitcherCAD program is a pow-

erful PC software tool that aids in the design and

optimization of switching regulators. The program can

cut days off the design cycle by selecting topologies,

calculating operating points and specifying component

values and manufacturer’s part numbers. 144 page

manual included. $20.00

SwitcherCAD supports the following parts: LT1070 se-

ries: LT1070, LT1071, LT1072, LT1074 and LT1076.

LT1082. LT1170 series: LT1170, LT1171, LT1172 and

LT1176. It also supports: LT1268, LT1269 and LT1507.

LT1270 series: LT1270 and LT1271. LT1371 series:

LT1371, LT1372, LT1373, LT1375, LT1376 and LT1377.

Micropower SwitcherCAD™ — The MicropowerSCAD

program is a powerful tool for designing DC/DC con-

verters based on Linear Technology’s micropower

switching regulator ICs. Given basic design parameters,

MicropowerSCAD selects a circuit topology and offers

you a selection of appropriate Linear Technology switch-

ing regulator ICs. MicropowerSCAD also performs circuit

simulations to select the other components which sur-

round the DC/DC converter. In the case of a battery

supply, MicropowerSCAD can perform a battery life

simulation. 44 page manual included. $20.00

MicropowerSCAD supports the following LTC micro-

power DC/DC converters: LT1073, LT1107, LT1108,

LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174,

LT1300, LT1301 and LT1303.

continued on page 40

DESIGN TOOLS

Linear Technology Magazine • February 2000

LINEAR TECHNOLOGY CORPORATION

1630 McCarthy Boulevard

Milpitas, CA 95035-7417

(408) 432-1900 FAX (408) 434-0507

www.linear-tech.com

For Literature Only: 1-800-4-LINEAR

Adobe and Acrobat are registered trademarks of Adobe

Systems, Inc.; Windows is a registered trademark of

Microsoft Corp.; AppleTalk is a registered trademark of

Apple Computer, Inc. PSPICE is a trademark of MicroSim

Corp.

CD-ROM Catalog

LinearView — LinearView™ CD-ROM version 4.0 is

Linear Technology’s latest interactive CD-ROM. It al-

lows you to instantly access thousands of pages of

product and applications information, covering Linear

Technology’s complete line of high performance analog

products, with easy-to-use search tools.

The LinearView CD-ROM includes the complete product

speciﬁcations from Linear Technology’s Databook library

(Volumes I–VII) and the complete Applications Hand-

book collection (Volumes I–III). Our extensive collection

of Design Notes and the complete collection of

Linear

Technology

magazine are also included.

A powerful search engine built into the LinearView CD-

ROM enables you to select parts by various criteria,

such as device parameters, keywords or part numbers.

All product categories are represented: data conversion,

references, ampliﬁers, power products, ﬁlters and inter-

face circuits. Up-to-date versions of Linear Technology’s

DESIGN TOOLS, continued from page 39

software design tools, SwitcherCAD, Micropower Switch-

erCAD, FilterCAD, Noise Disk and Spice Macromodel

library, are also included. Everything you need to know

about Linear Technology’s products and applications is

readily accessible via LinearView. LinearView runs un-

der Windows 95 or later. Available at no charge.

World Wide Web Site

Linear Technology Corporation’s customers can now

quickly and conveniently ﬁnd and retrieve the latest

technical information covering the Company’s products

on LTC’s Internet web site. Located at www.linear-

tech.com, this site allows anyone with Internet access

and a web browser to search through all of LTC’s

technical publications, including data sheets, applica-

tion notes, design notes,

Linear Technology

magazine

issues and other LTC publications, to ﬁnd information

on LTC parts and applications circuits. Other areas

within the site include help, news and information about

Linear Technology and its sales ofﬁces.

Other web sites usually require the visitor to download

large document ﬁles to see if they contain the desired

information. This is cumbersome and inconvenient. To

save you time and ensure that you receive the correct

information the ﬁrst time, the ﬁrst page of each data

sheet, application note and

Linear Technology

maga-

zine is recreated in a fast, download-friendly format.

This allows you to determine whether the document is

what you need, before downloading the entire ﬁle.

The site is searchable by criteria such as part numbers,

functions, topics and applications. The search is per-

formed on a user-deﬁned combination of data sheets,

application notes, design notes and

Linear Technology

magazine articles. Any data sheet, application note,

design note or magazine article can be downloaded or

faxed back. (Files are downloaded in Adobe Acrobat PDF

format; you will need a copy of Acrobat Reader to view

or print them. The site includes a link from which you

can download this program.)

International

Sales Ofﬁces

FRANCE

Linear Technology S.A.R.L.

Immeuble “Le Quartz”

58 Chemin de la Justice

92290 Chatenay Malabry

France

Phone: 33-1-41079555

FAX: 33-1-46314613

GERMANY

Linear Technology GmbH

Oskar-Messter-Str. 24

D-85737 Ismaning

Germany

Phone: 49-89-962455-0

FAX: 49-89-963147

HONG KONG

Linear Technology Corp. Ltd.

Unit 2109, Metroplaza Tower 2

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Phone: 852-2428-0303

FAX: 852-2348-0885

JAPAN

Linear Technology KK

5F NAO Bldg.

1-14 Shin-Ogawa-cho Shinjuku-ku

Tokyo, 162

Japan

Phone: 81-3-3267-7891

FAX: 81-3-3267-8510

KOREA

Linear Technology Korea Co., Ltd

Yundang Building #1002

Samsung-Dong 144-23

Kangnam-Ku, Seoul 135-090

Korea

Phone: 82-2-792-1617

FAX: 82-2-792-1619

SINGAPORE

Linear Technology Pte. Ltd.

507 Yishun Industrial Park A

Singapore 768734

Phone: 65-753-2692

FAX: 65-752-0108

SWEDEN

Linear Technology AB

Sollentunavägen 63

S-191 40 Sollentuna

Sweden

Phone: 46-8-623-1600

FAX: 46-8-623-1650

TAIWAN

Linear Technology Corporation

Rm. 602, No. 46, Sec. 2

Chung Shan N. Rd.

Taipei, Taiwan, R.O.C.

Phone: 886-2-2521-7575

FAX: 886-2-2562-2285

UNITED KINGDOM

Linear Technology (UK) Ltd.

The Coliseum, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

Phone: 44-1276-677676

FAX: 44-1276-64851

World Headquarters

Linear Technology Corporation

1630 McCarthy Boulevard

Milpitas, CA 95035-7417

Phone: (408) 432-1900

FAX: (408) 434-0507

U.S. Area

Sales Ofﬁces

NORTHEAST REGION

Linear Technology Corporation

3220 Tillman Drive, Suite 120

Bensalem, PA 19020

Phone: (215) 638-9667

FAX: (215) 638-9764

Linear Technology Corporation

15 Research Place

North Chelmsford, MA 01863

Phone: (978) 656-4750

FAX: (978) 656-4760

NORTHWEST REGION

Linear Technology Corporation

720 Sycamore Drive

Milpitas, CA 95035

Phone: (408) 428-2050

FAX: (408) 432-6331

SOUTHEAST REGION

Linear Technology Corporation

17000 Dallas Parkway, Suite 219

Dallas, TX 75248

Phone: (972) 733-3071

FAX: (972) 380-5138

Linear Technology Corporation

9430 Research Blvd.

Echelon IV Suite 400

Austin, TX 78759

Phone: (512) 343-3679

FAX: (512) 343-3680

Linear Technology Corporation

1080 W. Sam Houston Pkwy., Suite 225

Houston, TX 77043

Phone: (713) 463-5001

FAX: (713) 463-5009

Linear Technology Corporation

5510 Six Forks Road, Suite 102

Raleigh, NC 27609

Phone: (919) 870-5106

FAX: (919) 870-8831

CENTRAL REGION

Linear Technology Corporation

2010 E. Algonquin Road, Suite 209

Schaumburg, IL 60173

Phone: (847) 925-0860

FAX: (847) 925-0878

Linear Technology Corporation

Kenosha, WI 53144

Phone: (414) 859-1900

FAX: (414) 859-1974

SOUTHWEST REGION

Linear Technology Corporation

21243 Ventura Blvd., Suite 208

Woodland Hills, CA 91364

Phone: (818) 703-0835

FAX: (818) 703-0517

Linear Technology Corporation

15375 Barranca Parkway, Suite A-213

Irvine, CA 92618

Phone: (949) 453-4650

FAX: (949) 453-4765