Application Information (Continued)
In the circuit of Figure 2, S1 is a P-channel device and S2,
S3, and S4 are N-channel devices. Because the output is
biased below ground, it is important that the p
−
wells of S3
and S4 never become forward biased with respect to either
their sources or drains. A substrate logic circuit guarantees
that these p
−
wells are always held at the proper voltage.
Under all conditions S4 p
−
well must be at the lowest poten-
tial in the circuit. To switch off S4, a level translator generates
V
GS4
= 0V, and this is accomplished by biasing the level
translator from the S4 p
−
well.
An internal RC oscillator and ÷ 2 circuit provide timing sig-
nals to the level translator. The built-in regulator biases the
oscillator and divider to reduce power dissipation on high
supply voltage. The regulator becomes active at about V
+
=
6.5V. Low voltage operation can be improved if the LV pin is
shorted to ground for V
+
≤3.5V. For V
+
≥3.5V, the LV pin
must be left open to prevent damage to the part.
POWER EFFICIENCY AND RIPPLE
It is theoretically possible to approach 100% efficiency if the
following conditions are met:
1. The drive circuitry consumes little power.
2. The power switches are matched and have low R
on
.
3. The impedance of the reservoir and pump capacitors
are negligibly small at the pumping frequency.
The LMC7660 closely approaches 1 and 2 above. By using
a large pump capacitor C
p
, the charge removed while sup-
plying the reservoir capacitor is small compared to C
p
’s total
charge. Small removed charge means small changes in the
pump capacitor voltage, and thus small energy loss and high
efficiency. The energy loss by C
p
is:
By using a large reservoir capacitor, the output ripple can be
reduced to an acceptable level. For example, if the load
current is 5 mA and the accepted ripple is 200 mV, then the
reservoir capacitor can omit approximately be calculated
from:
PRECAUTIONS
1. Do not exceed the maximum supply voltage or junction
temperature.
2. Do not short pin 6 (LV terminal) to ground for supply
voltages greater than 3.5V.
3. Do not short circuit the output to V
+
.
4. External electrolytic capacitors C
r
and C
p
should have
their polarities connected as shown in Figure 1.
REPLACING PREVIOUS 7660 DESIGNS
To prevent destructive latchup, previous 7660 designs re-
quire a diode in series with the output when operated at
elevated temperature or supply voltage. Although this pre-
vented the latchup problem of these designs, it lowered the
available output voltage and increased the output series
resistance.
The National LMC7660 has been designed to solve the
inherent latch problem. The LCM7660 can operate over the
entire supply voltage and temperature range without the
need for an output diode. When replacing existing designs,
the LMC7660 can be operated with diode Dx.
Typical Applications
CHANGING OSCILLATOR FREQUENCY
It is possible to dramatically reduce the quiescent operating
current of the LMC7660 by lowering the oscillator frequency.
The oscillator frequency can be lowered from a nominal 10
kHz to several hundred hertz, by adding a slow-down ca-
pacitor C
osc
(Figure 3). As shown in the Typical Performance
Curves the supply current can be lowered to the 10 µA
range. This low current drain can be extremely useful when
used in µPower and battery back-up equipment. It must be
understood that the lower operating frequency and supply
current cause an increased impedance of C
r
and C
p
. The
increased impedance, due to a lower switching rate, can be
offset by raising C
r
and C
p
until ripple and load current
requirements are met.
SYNCHRONIZING TO AN EXTERNAL CLOCK
Figure 4 shows an LMC7660 synchronized to an external
clock. The CMOS gate overrides the internal oscillator when
it is necessary to switch faster or reduce power supply
00913606
FIGURE 2. Idealized Voltage Converter
LMC7660
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