SEMICMF.019 1
Features
• Single chip mixer/oscillator PLL combination for
multi band tuner for DTT applications
• Each mixer oscillator band optimized for wide
dynamic range
• RF input stages allow for either single-ended or
differential drive
• PLL frequency synthesizer designed for low
phase noise performance
• Broadband output level detect with onset adjust
• PLL frequency synthesizer compatible with
standard digital terrestrial offsets
• Four integrated switching ports
•I
2C fast mode compliant
• ESD protection (Normal ESD handling
procedures should be observed)
Applications
• Terrestrial digital receiver systems
• Terrestrial analogue receiver systems
• Cable receiver systems
• Data communications systems
Figure 1 - Pin Allocation Diagram
LH40
1
PORT P3
VccRF
HI INPUT
PORT P2
PORT P1
MID INPUT
SL2610
LOLOWOP
LOLOWOPB
LOMIDOP
VccLO
LOHIIP
LOHIOP
LOHIOPB
LOHIIPB
VccLO
MID INPUTB
VccRF
LO INPUT
IFOPB
IFOP
AGCBIAS
VCCIF
IFIPB
IFIP
ADD
CONVOP
CONVOPB
VccDIG
LO INPUTB
VccRF
AGCOUT
PORT P0
CHARGE PUMP
XTAL CAP
DRIVE
XTAL
SDA
SCL
LOMIDOPB
HI INPUTB
VEE
(PACKAGE
PADDLE)
Figure 2 - SL2610 Block Diagram
HI
CONVOP
~~
~
BAND
LO
BAND
MID
BAND
CONVOP
B
IFIP
IFIPB
IFOP
IFOPB
AGC BIA
S
AGC OUT
HI
BAND
LO
BAND
MID
BAND
I2C
Interface
Port
Interface
REF
DIVIDER
~
PORT P0
PORT P1
PORT P2
PORT P3
PROG
DIVIDER
CHARGE
PUMP
DRIVE
XTAL
XTALCAP
SDA SCL ADD
IF
SELECT
DS5775 Issue 2.3 July 2002
Ordering Information
SL2610/IG/LH1S (tubes)
SL2610/IG/LH1T (tape & reel)
-40oC to 85oC
SL2610
Wide Dynamic Range Image Reject MOPLL
Data Sheet
SL2610 Data Sheet
2SEMICMF.019
Description
The SL2610 is a mixer oscillator intended primarily for application in all band tuners, where it performs image
reject downconversion of the RF channel to a standard 36MHz or 44MHz IF.
Each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank.
The band outputs share a common low impedance SAWF driver stage.
Frequency selection is controlled by the on-board I2C bus frequency synthesizer. This block also controls four
general purpose switching ports for selecting the prefilter/AGC stages.
The SL2610 has high intermodulation intercept performance so offering high signal to spurious performance in
the presence of higher amplitude interferers or in the presence of a wide bandwidth composite input signal.
An output broadband level detect circuit is included for control of the tuner front end AGC.
Quick Reference Data
Characteristics Units
Frequency range: LOW band 50-500 MHz
MID band 50-500 MHz
HIGH band 200-900 MHz
Conversion gain * 32 ± 2dB
Noise figure 13 dB
Image reject 30 dB
P1dB input referred, Converter section only 106 dBuV
IP3 input referred, Converter section only 14 dBm
IP2 input referred, Converter section only 48 dBm
LO phase noise (free running) @ 10kHz offset -90 dBc/Hz
@ 100kHz offset -110 dBc/Hz
LO phase noise floor -136 dBc/Hz
PLL phase noise -158 dBc/Hz
Maximum composite output amplitude 3 dBm
* Assuming 2 dB shaping filter loss in external IF path.
Data Sheet SL2610
3
SEMICMF.019
Figure 3 - SL2610 Evaluation Board Schematic
PORT P3
1
Vcc RF
2
HIGH IP
3
HIGH IP B
4
PORT P2
5
PORT P1
6
MID INPUT
7
MID IP B
8
Vcc RF
9
LO INPUT
10
LO INPUT B
11
Vcc RF
12
AGC OUT
13
PORT P0
14
DRIVE
15
CHARGE PUMP
16
XTAL CAP
17
XTAL
18
SDA
19
SCL
20
Vcc DIG 21
CONV OP B 22
CONV OP 23
ADD 24
IF INPUT 25
IF INPUT B 26
Vcc IF 27
AGC BIAS 28
IF O/P 29
IF O/P B 30
VccLO 31
LOHII/PB 32
LOHIO/PB 33
LOHIO/P 34
LOHII/P 35
VccLO 36
LOMIDOPB 37
LOMIDOP 38
LOLOWOPB 39
LOLOWOP 40
Vee = PACKAGE PADDLE
IC1
SL2610
C14
2p2
C13
2p2
C12
2p2
C11
2p2
L5 22nH
L6
8.2nH
C16
100pF C15
5pF
R6
4K7
SDA5
3
5V0
4
GND
5
SCL5
6
CN1
HDRIIC5/4W
R11
4K7
R10
4K7
+5V
C17
220nF
C19
39pF
C18
18pF X1
4 MHz
C20
68pF
R7
13K
T1
BCW31 R8 22K
+30V
R9 13K C21
2n2
VT
+5V
+5V
+5V
+5V
+5V
+5V
+5VL4
82nH
D2
BB640 C10
7pF
L3 36nH
L2
1u5H
C2
7pF
L1
120nH
D1
BB640
R2
1K
R4 4K7
VT R5 1K
VT
L7 220nH
L8 220nH
C27 82pF
C26 82pF
+5V
C24 1nF
C25 1nF
VR1 10K
TR1
5:1
SK4
IF OUT
C3
1nF
C4
1nF
C5
1nF
C6
1nF
C7
1nF
C8
1nF
SK1
HI IN
SK2
MID IN
SK3
LOW IN
R3
1K
1
2
3
CN2
Molex3
+30V
GND
+5V
C29
10nF
C30
10nF
C31
10nF
C32
10nF
C33
10nF
C34
10nF
C35
10nF
+
C36
47uF
+30V
C28
100nF
D4
P0 D5
P1 D6
P2 D7
P3
R12
750R R13
750R R14
750R R15
750R
+5V
P0 P1 P2 P3
P0
P1
P2
P3
TP1
AGC OUT
+5V
C22 10nF
C23 10nF
1
2
3
CN3
ADDRESS
C1
100pF
R1
4K7
C9
100pF
VT
TP2
AGC BIAS
R16
20R
R17
10R R18
10R
D3
BB555
R19
10R
SL2610 Data Sheet
4SEMICMF.019
Figure 4 - SL2610 Evaluation Board Layout (Top)
Figure 5 - SL2610 Evaluation Board Layout (Bottom)
Data Sheet SL2610
5
SEMICMF.019
1.0 Functional Description
The SL2610 is a multi band RF mixer oscillator with image reject and on-board frequency synthesizer. It is
intended primarily for application in all band terrestrial tuners and requires a minimum external component
count. It contains all elements required for RF downconversion to a standard IF with the exception of external
VCO tank circuits.
The pin allocation is contained in Figure 1 and the block diagram in Figure 2.
1.1 Mixer/oscillator section
In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner
prefilter and AGC stages. The mixer input is arranged such that the signal can be coupled either differentially or
single-ended, and achieves the specified minimum performance in both configurations. Band input impedances
and NF are contained in Figure 11 and Figure 12 respectively. The converter two tone input spectra are
contained in Figure 13 and Figure 14.
The preamplifier output then feeds the mixer stage where the required channel is image reject downconverted
to the IF frequency. The local oscillator frequency for the downconversion is obtained from the on board local
oscillator, which uses an external varactor tuned tank. Typical VCO applications are contained in Figures 8, 9,
and 10.
The output of the mixer is then fed to the converter output driver which presents a matched 200 Ω differential
load to an external IF shaping filter.
The output of the shaping filter is then coupled into the IFAMP stage, which provides further gain and offers a
50 Ω output impedance to interface direct with the tuner SAW filter.
The SL2610 contains a broadband level detect circuit whose output can be used to control the tuner AGC. The
target level of the AGC detector is controlled by the voltage applied to the AGCBIAS pin. The characteristic of
the target level is given in Figure 18.
1.2 PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter, to control a varicap tuned local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with good phase noise performance. It can also be
operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT)
receivers.
The LO signal is multiplexed from the selected oscillator section to an internal preamplifier which provides gain
and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit
fully programmable divider which is of MN+A architecture, where the dual modulus prescaler is 16/17, the A
counter is 4-bits and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided
down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as
detailed in Table 1.
The output of the phase detector feeds a charge pump and loop amplifier section which when used with an
external loop filter integrates the current pulses into the varactor line voltage.
The programmable divider output Fpd, divided by two and the reference divider output Fcomp, can be switched
to port P0 by programming the device into test mode. The test modes are described in Table 5.
SL2610 Data Sheet
6SEMICMF.019
2.0 Programming
The SL2610 is controlled by an I2C data bus and is compatible with both standard and fast mode formats.
Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesizer
can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the
device into write mode if it is low, and read mode if it is high. Tables 2 and 3 illustrate the format of the data. The
device can be programmed to respond to several addresses, which enables the use of more than one
synthesizer in an I2C bus system (Tables 2 and 3). Table 4 shows how the address is selected by applying a
voltage to the ‘ADD’ input. When the device receives a valid address byte, it pulls the SDA line low during the
acknowledge period and during following acknowledge periods after further data bytes are received. When the
device is programmed into read mode, the controller accepting the data must pull the SDA line low during all
status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low
during this period the device generates an internal STOP condition which inhibits further reading.
2.1 Write mode
With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the
reference divider ratio bits R4-R0 (Table 1), and the charge pump setting bits C1-C0 (Table 6). Byte 5 controls
the IF select (Table 8), the band select function bits BS1-BS0 (Table 7), the switching ports P3-P0 and the test
modes (Table 5).
After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4.
Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5
respectively. Having received two complete data bytes, additional data bytes can be entered, where byte
interpretation follows the same procedure, without re-addressing the device. This procedure continues until a
STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs
during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency
data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the
generation of a STOP condition.
2.2 Read mode
When the device is in read mode, the status byte read from the device takes the form shown Table 3.
Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has
dropped below 3V (at 25oC), e.g. when the device is initially turned ON. The POR is reset to '0' when the read
sequence is terminated by a STOP command. When POR is set high this indicates that the programmed
information may have been corrupted and the device reset to power up condition.
Bit 2 (FL) indicates whether the device is phase locked, a logic '1' is present if the device is locked, and a logic
'0' if the device is unlocked.
Data Sheet SL2610
7
SEMICMF.019
2.3 Programmable features
Synthesiser
programmable divider
Function as described above.
Reference programmable
divider
Function as described above.
Band selection The required mixer oscillator band and RF input is selected by bits BS1-BS0,
within data byte 5, as defined in Table 7.
IF selection The centre of the image reject passband is selected by IF as defined in Table 8.
Charge pump current The charge pump current can be programmed by bits C1-C0 within data byte 4, as
defined in Table 6.
Ports P3-P0 These are configured as NPN open collector buffers and programmed by bits P3-
P0.
Logic ‘1’ = on.
Logic ‘0’ = off (high impedance); default on power up.
In test modes, when TE=1, ports P3-P0 respond according to T2-T0 respectively,
and previously transmitted data is lost.
Test mode The test modes are invoked by setting bits T2–T0 as described in Table 5.
SL2610 Data Sheet
8SEMICMF.019
Table 1 - Reference Division Ratio
R4 R3 R2 R1 R0 Ratio
00000 2
00001 4
00010 8
00011 16
00100 32
00101 64
00110 128
00111 256
01000not allowed
01001 5
01010 10
01011 20
01100 40
01101 80
01110 160
01111 320
10000not allowed
10001 6
10010 12
10011 24
10100 48
10101 96
10110 192
10111 384
11000not allowed
11001 7
11010 14
11011 28
11100 56
11101 112
11110 224
11111 448
Data Sheet SL2610
9
SEMICMF.019
Table 2 - Write Data Format (MSB is transmitted first)
Table 3 - Read Data Format (MSB is transmitted first)
A : Acknowledge bit
MA1,MA0 : Variable address bits (see Table 4)
214-20: Programmable division ratio control bits
R4-R0 : Reference division ratio select (see Table 1)
C1,C0 : Charge pump current select (see Table 6)
BS1-BS0 : Band select bits (see Table 7)
IF : IF passband select (see Table 8)
TE : Test mode enable
T2-T0 : Test mode control bits when TE=1 (see Table 5)
P3-P0 : P3-P0 port output states
POR : Power on reset indicator
FL : Phase lock flag
MSB LSB
Address 11000MA1MA00AByte 1
Programmable
divider
02
14 213 212 211 210 2928AByte 2
Programmable
divider
2726252423222120AByte 3
Control data 1 C1C0R4R3R2R1R0AByte 4
Control data IF BS1 BS0 TE P3/T2 P2/T1 P1/T0 P0 A Byte 5
MSB LSB
Address 11000MA1MA01AByte 1
Status Byte POR FL 0 0 0 0 0 0 A Byte 2
SL2610 Data Sheet
10 SEMICMF.019
# Programmed by connecting a 30 kΩ resistor between pin and Vcc
Table 4 - Address Selection
Table 5 - Test Modes
* crystal and selected local oscillator need signals to enable charge pump test modes and to toggle status
byte bit FL
X -’don’t care’
MA1 MA0 Address Input Voltage Level
0 0 0-0.1Vcc
0 1 Open circuit
1 0 0.4Vvcc – 0.6 Vcc #
1 1 0.9 Vcc - Vcc
TE T2 T1 T0 Test Mode Description
0 X X X Normal operation
1 0 0 0 Normal operation
1 0 0 1 Charge pump sink *
Status byte FL set to logic ‘0’
1 0 1 0 Charge pump source *
Status byte FL set to logic ‘0’
1 0 1 1 Charge pump disabled *
Status byte FL set to logic ‘1’
1 1 0 0 Normal operation and Port P0 = Fpd/2
1 1 0 1 Charge pump sink *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
1 1 1 0 Charge pump source *
Status byte FL set to logic ‘0’
Port P0 = Fcomp
1 1 1 1 Charge pump disabled *
Status byte FL set to logic ‘1’
Port P0 = Fcomp
Data Sheet SL2610
11
SEMICMF.019
Table 6 - Charge pump current
Table 7 - Band select
C1 C0 Current in µA
min typ max
00+85 +130 +175
01+190 +280 +370
10+420 +600 +780
11+930 +1300 +1670
BS1 BS0 Band Selected
00 LO Band
0 1 MID Band
1 0 HI band
1 1 HI band
IF input Centre of Image Reject Passband Passband
Bandwidth
044 MHz 6 MHz
136 MHz 8 MHz
Table 8 - IF SELECT function
SL2610 Data Sheet
12 SEMICMF.019
Figure 6 - Crystal Oscillator Application
Figure 7 - Ifamp Output Load Condition for Test Purposes
Figure 8 - LO Band VCO Application
XTALCAP
XTAL
39 pF
18 pF
SL2610
to 50 Ω load
SL2610
IFOP
IFOPB
5:1
C2 L1
R1
4K7
L2
1u5H 100pF
D1
BB640 VT
R2
1K
7pF
R16
120nH
20R
C1
LOLOWOP LOLOWOPB
Data Sheet SL2610
13
SEMICMF.019
Figure 9 - Mid Band VCO Application
Figure 10 - HI Band VCO Application
R3
1K
L3 36nH
C10
7pF
L4
82nH
R4
4K7
C9
100pF
D2
BB640
LOMIDOP LOMIDOPB
VT
C15
10R
L6 22nH
C16
100pF D3
BB555 5pF R19
L6
C14
C13
C12C11
2p2 2p2 2p2 2p2
R17
10R
R18
10R
4K7
R6
R5 1K
VT
8.2nH
LOHIIP LOHIOP LOHIOPB LOHIIPB
SL2610 Data Sheet
14 SEMICMF.019
Figure 11 - LO, MID and HI Band Input Impedance
Figure 12 - Low, Mid and Hi Band Noise Figure versus Frequency
CH1 S 11 1 U FS
START 50.000 000 MHz STOP 900.000 000 MHz
DEV1 VCC=4.7V
Cor
PRm
12 Mar 2002 15:10:11
1
2
3
4
1_: 152.31 -12.117 145.94 pF
90.000 000 MHz
2_: 150.74
-34.063
220 MHz
3_: 133.48
-62.813
500 MHz
4_: 111.79
-86.926
900 MHz
10.5
11
11.5
12
12.5
13
0 100 200 300 400 500 600 700 800 900 1000
LO Frequency (MHz)
Noise Figure (dB)
Data Sheet SL2610
15
SEMICMF.019
Figure 13 - Converter third order two tone intermodulation test condition spectrum, input
referred, all bands
Figure 14 - Second order two tone intermodulation test condition spectrum, input referred
-14 dBm
-56 dBm
df
(6 MHz)
f1-df f1 f2 f2+df
Incident power from 50Ω source
IIM3; -42dBc
-14 dBm
-54 dBm
df
f2-f1 f1 f2
Incident power from 50Ω source
IIM2; -40dBc
X
SL2610 Data Sheet
16 SEMICMF.019
Figure 15 - Converter Output Impedance (Single Ended)
Figure 16 - IFAMP Input Impedance
CH1 S 11 1 U FS
START 36.000 000 MHz STOP 44.000 000 MHz
DEV1 4.7V
C?
Avg
16
Smo
PRm
27 Mar 2002 07:46:06
1
2
1_: 101.84 -1.9844 2.2279 nF
36.000 000 MHz
2_: 101.25
-3.3398
44 MHz
CH1 S 11 1 U FS
START 30.000 000 MHz STOP 50.000 000 MHz
DEV3 4.7V
C?
Avg
16
Smo
PRm
28 Mar 2002 14:16:05
1
234
1_: 167.25 28.227 140.39 nH
32.000 000 MHz
2_: 168.88
28.781
36 MHz
3_: 171.88
29.594
44 MHz
4_: 173.84
30.125
50 MHz
Data Sheet SL2610
17
SEMICMF.019
Figure 17 - IFAMP Output Impedance (Single Ended)
Figure 18 - AGC Output Level Set versus AGCBIAS Voltage
CH1 S 11 1 U FS
START 30.000 000 MHz STOP 50.000 000 MHz
DEV2 4.7V
C?
Avg
16
Smo
PRm
2 Apr 2002 10:52:12
1
2
3
4
1_: 56.559 4.8379 24.062 nH
32.000 000 MHz
2_: 56.539
5.4844
36 MHz
3_: 56.516
6.7266
44 MHz
4_: 56.477
7.6777
50 MHz
-25
-20
-15
-10
-5
0
5
10
0123456
AGCBIAS Voltage (V)
Output Level (dBm)
SL2610 Data Sheet
18 SEMICMF.019
Electrical Characteristics
Test conditions (unless otherwise stated)
Tamb = -40oC to 85oC, Vee= 0V, Vcc=Vcca=Vccd = 5V +5%
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
Characteristic pin min typ max units conditions
Supply current 163 196 mA All switching ports off.
LO or MID BAND
ENABLED
Input frequency range 50 500 MHz
Input impedance See Figure 11 and refer to Note 8.
Input Noise Figure 13 dB Tamb=27oC, see Figure 12, refer
to Note 2, no correction for external
filtering.
Converter gain 10 14 dB Conversion gain from 50 Ω single
ended source to differential
200 Ω load, refer to Note 3.
Conversion gain to
IFAMP output
28 36 dB Conversion gain from 50 Ω single
ended source to 50 Ω single-ended
load with output transformer as in
Figure 7, see Notes 2 and 3.
Gain variation within
channel
0.4 1 dB Channel bandwidth 8 MHz within
operating frequency range, see
note (2), excluding interstage
shaping filter ripple.
Converter input referred
IP2
26 dBm See Figure 14 and refer to Notes 4
and 6. Assuming ideal power
match.
Converter input referred
IM2
-40 dBc See Figure 14 and refer to Notes 4
and 6.
Converter input referred
IP3
7 dBm See Figure 13 and refer to Notes 4
and 6. Assuming ideal power
match.
Converter input referred
IM3
-42 dBc See Figure 13 and refer to Notes 4
and 6.
Input referred P1dB 101 dBµV
Local oscillator
operation range
50 550 MHz Refer to Note 7.
Local oscillator tuning
range
68
200
225
465
MHz
MHz
With application as in Figure 8.
With application as in Figure 9.
Data Sheet SL2610
19
SEMICMF.019
Characteristic Pin Min Typ Max Units Conditions
LO phase noise, SSB
@ 1 kHz offset
@ 10 kHz offset
@ 100 kHz offset
-55
-86
-109
dBc/Hz
dBc/Hz
dBc/Hz
With application as in Figure 8 and
Figure 9 outside of PLL loop
bandwidth.
LO phase noise floor -136 dBc/Hz With application as in Figure 8 and
Figure 9 at 2 MHz offset
LO temperature stability
80 kHz/oC
Application as in Figure 8 and
Figure 9.
No temperature compensation.
LO turn on drift
100 kHz
Application as in Figure 8 and
Figure 9, frequency drift over 15
minute period from turn on at a
fixed ambient temperature.
No temperature compensation.
LO to RF input leakage 60 dBµV Application as in Figures 8 and 9.
LO Vcc stability 0.5 MHz/V
LO spurs due to RF
pulling
-52 dBc See Note 5.
HI BAND ENABLED
Input frequency range 200 870 MHz
Input impedance See Figure 11 and refer to Note 8.
Input Noise Figure 13 dB Tamb=27oC, see Figure 12, refer
to Note 2, no correction for external
filtering.
Converter gain 10 14 dB Conversion gain from 50 Ω single
ended source to differential
200 Ω load, refer to Note 3.
Conversion gain to
IFAMP output
28 36 dB Conversion gain from 50 Ω single
ended source to 50 Ω single-ended
load with output transformer as in
Figure 7, see Notes 2 and 3.
Gain variation within
channel
0.4 1 dB Channel bandwidth 8 MHz within
operating frequency range, see
Note 3, excluding interstage
shaping filter ripple.
Converter input referred
IP2
26 dBm See Figure 14 and refer to Notes 4
and 6. Assuming ideal power
match.
SL2610 Data Sheet
20 SEMICMF.019
Characteristic Pin Min Typ Max Units Conditions
Converter input referred IM2 -40 dBc See Figure 14 and refer to Notes 4 and
6.
Converter input referred IP3 7 dBm See Figure 13 and refer to Notes 4 and
6. Assuming ideal power match.
Converter input referred IM3 -42 dBc See Figure 13 and refer to Notes 4 and
6.
Input referred P1dB 101 dBµV
Local oscillator operation
range
200 1000 MHz Refer to Note 7.
Local oscillator tuning range 440 950 MHz With application as in
Figure 10.
LO phase noise, SSB
@ 1 kHz offset
@ 10 kHz offset
@ 100 kHz offset
-55
-86
-109
dBc/Hz
dBc/Hz
dBc/Hz
With application as in Figure 10,
outside of PLL loop bandwidth.
LO phase noise floor -136 dBc/Hz With application as in Figure 10, at 2
MHz offset.
LO temperature stability
110 kHz/oC
Application as in Figure 10.
No temperature compensation.
LO turn on drift
100 kHz
Application as in Figure 10, frequency
drift over 15 minute period from turn on
at a fixed ambient temperature.
No temperature compensation.
LO to RF input leakage 60 dBµV Application as in Figure 10.
LO Vcc stability 0.5 MHz/V
LO spurs due to RF pulling -52 dBc See Note 5.
All Bands
Converter output impedance 200 ΩDifferential, see Figure 15.
Image rejection 25
25
dB
dB
At 36 MHz IF frequency IF bit = 1.
At 44 MHz IF frequency IF bit = 0.
See Table 8.
Isolation between band inputs -60 dBc Level of desired signal converted to IF
output through disabled band relative
to signal converted through enabled
band.
Composite output amplitude 3 dBm
Data Sheet SL2610
21
SEMICMF.019
Characteristic Pin Min Typ Max Units Conditions
IFAMP
Input frequency range 32 50 MHz
Input impedance 200 ΩDifferential, see Figure 16.
Gain 20 24 dB Voltage conversion gain from 200 Ω
differential source to differential load as
contained in Figure 7, see Note 3.
Output impedance 100 ΩDifferential, see Figure 17.
Output limiting 3 Vp-p Differential into load as in Figure 7.
IFAMP OPIP3 135 dBµV Two output tones at 2 MHz separation at
104 dBuV into load as in Figure 7, see
Note 2.
IFAMP OPIM3 -62 dBc Two output tones at 2 MHz separation at
104 dBuV into load as in Figure 7, see
Note 2.
AGCBIAS Leakage current 28 -100
-50
100
50
µA
µA
Vee ≤ Vagc1 ≤ Vcc
1.5V ≤ Vagc1 ≤ 3.5V
AGCOUT voltage range 13 0.5 3 V Max load current 20 µA.
AGC output level set See Figure 18.
Supply rejection -52 dBc Spurs introduced on converted output
relative to desired signal by a supply
ripple voltage of 10 mV p-p in the range
1 kHz to 100 kHz (including external
supply decoupling).
Synthesiser
SDA, SCL
Input high voltage
Input low voltage
Input current
Leakage current
Hysterysis
19, 20
19, 20
3
0
-10
0.4
5.5
1.5
10
10
V
V
µA
µA
V
Input voltage =Vee to Vcc
Input voltage = Vee to 5.5V, Vcc=Vee
SDA output voltage 19 0.4
0.6
V
V
Isink = 3 mA
Isink = 6 mA
SCL clock rate 20 400 kHz
SL2610 Data Sheet
22 SEMICMF.019
Notes
1 All power levels are referred to 50 Ω, and 0 dBm = 107 dBµV.
2 Total system with final load as in Figure 7, including an interstage IF shaping filter with IL of 2 dB and
characteristic impedance of 200 Ω differential.
3 The specified gain is determined by the following formula;
Gs = Gm + Vtr where Gs = gain as specified
Gm = gain as measured with specified load conditions
Vtr = voltage transformation ratio of transformer as in Figure 7
4 Two input tones within RF operating range at -14 dBm from 50Ω single ended source with 200 Ω differential output load. DC output
current must be shunted to Vcc through suitable inductor, i.e. 10µH.
5 Modulation spurs introduced on local oscillator through injection locking of the local oscillator by an
undesired RF carrier.
Desired carrier at 80 dBµV, undesired carrier at 90 dBµV at an offset frequency of fd plus 42+fc MHz,
where fd is desired carrier frequency, fc is US chrominance sub carrier and 42 equals 7 channel spacings.
6 All intermodulation specifications are measured with a single-ended input.
7 Operation range is defined as the region over which the oscillator presents a negative impedance.
8 Target to achieve 6 dB minimum S11.
Characteristic Pin Min Typ Max Units Conditions
Charge pump output
current
16 See Table 6.
Vpin16 = 2V
Charge pump output
leakage
16 +3+10 nA Vpin16 = 2V
Charge pump drive output
current
15 0.5 mA Vpin15 = 0.7V
Crystal frequency 17, 18 4 16 MHz Application as in Figure 6.
Recommended crystal
series resonance
10 200 Ω4 MHz parallel resonant crystal.
External reference input
frequency
17, 18 4 20 MHz Sinewave coupled through 10nF
blocking capacitor.
External reference drive
level
18 0.2 0.5 Vpp Sinewave coupled through 10nF
blocking capacitor.
Phase detector
comparison frequency
.03125 0.25 MHz
Equivalent phase noise at
phase detector
-158
With 4 MHz crystal, SSB, within loop
bandwidth.
With Fcomp = 125 kHz
RF division ratio 240 32767
Reference division ratio See Table 1.
Switching ports P0-P3
sink current
leakage current
1, 5, 6,
14 10
10
mA
µA
Vport = 0.7V
Vport = Vcc
Address select
Input high current
Input low current
24
1
-0.5
mA
mA
See Table 4.
Vin=Vcc
Vin=Vee
Data Sheet SL2610
23
SEMICMF.019
Absolute Maximum Ratings
All voltages are referred to Vee at 0V
Characteristic min max units conditions
Supply voltage -0.3 6 V
RF input voltage 117 dBµV Transient condition only.
All I/O port DC offsets -0.3 Vcc+0.3 V
Total port current 20 mA
Storage temperature -55 150 oC
Junction temperature 125 oC Power applied.
Package thermal resistance, chip
to ambient
27 oC/W Package paddle soldered to ground.
Power consumption at 5.25V 1 W
ESD protection 1 kV Mil-std 883B method 3015 cat1
SL2610 Data Sheet
24 SEMICMF.019
Figure 19 - Input and Output Interface Circuits (RF section)
VCC
50Ω29 IFOP
50Ω
30
IFOPB
AGCOUT
VCC
1nF
3, 7, 10
IP
External
to Chip
Typical
133-j62Ω
@ 500MHz
(see Figure 10)
LOW, MID, HI, RF Input
13
20K
AGC Out
CONVOPB
22 CONVOP
100Ω100Ω
VCC
1.38K
95Ω
25
26
IFIP
IFIPB
Converter Output
IF Input
IF Output
LOHIOP
33 LOHIOPB
400
Ω
400
Ω
34
LOHIIP
V
bias
LOHIPB
500
Ω
32
LOHI Input & Output
LOLOWOP
LOMIDOP
Vbias
LOLOW and LOMID Outputs
37
39
LOLOWOPB
LOMIDOPB
2.4V
9K
VCC
28
AGCBIAS
AGCBIAS Input
4, 8, 11
IPB
VCC
38
40
23
35
40K
Data Sheet SL2610
25
SEMICMF.019
Figure 20 - Input and Output Interface Circuits (PLL section)
200µA
13
XTALCAP
18
17
XTAL
Vccd
220
16
15 DRIVE
Vccd
PUMP
24
500K
Vccd
SCL/SDA
ACK
*On SDA only
*
Vccd
120K
40K
ADD
P0, P1, P2, P3
Reference oscillator
SDA/SCL (pins 19 and 20)
Output Ports (pins 1, 5, 6, 14)
ADD input
Loop amplifier
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively
“
Zarlink
”
)
is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or
use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from
such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or
other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use
of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned
by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability,
performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee
that such methods of use will be satisfactory in a specific piece of equipment. It is the user
’
s responsibility to fully determine the performance and suitability of any
equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily
include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to Zarlink
’
s conditions of sale which are available on request.
Purchase of Zarlink s I
2
C components conveys a licence under the Philips I
2
C Patent rights to use these components in and I
2
C System, provided
that the system conforms to the I
2
C Standard Specification as defined by Philips.
Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink products
visit our Web Site at
