© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 8
1Publication Order Number:
MC14512B/D
MC14512B
8-Channel Data Selector
The MC14512B is an 8−channel data selector constructed with
MOS P−channel and N−channel enhancement mode devices in a
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
sequence generation.
Features
•Diode Protection on All Inputs
•Single Supply Operation
•3−State Output (Logic “1”, Logic “0”, High Impedance)
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter Symbol Value Unit
DC Supply Voltage Range VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout −0.5 to VDD
+ 0.5
V
Input or Output Current
(DC or Transient) per Pin
Iin, Iout ±10 mA
Power Dissipation, Per Package (Note 1) PD500 mW
Ambient Temperature Range TA−55 to +125 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (8−Second Soldering) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B 1
16
14512BG
AWLYWW
16
1
MC14512BCP
AWLYYWWG
1
1
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
B
C
Z
DIS
VDD
X7
INH
A
X3
X2
X1
X0
VSS
X6
X5
X4
MC14512B
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2
TRUTH TABLE
C B A Inhibit Disable Z
00000 X0
00100 X1
01000 X2
01100 X3
10000 X4
10100 X5
11000 X6
11100 X7
X X X 1 0 0
X X X X 1 High Impedance
NOTE: X = Don’t Care
ORDERING INFORMATION
Device Package Shipping†
MC14512BCPG PDIP−16
(Pb−Free) 500 Units / Rail
MC14512BDG SOIC−16
(Pb−Free) 48 Units / Rail
MC14512BDR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC14512B
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min
Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
mAd
c
IOL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAd
c
Input Current Iin 15 −± 0.1 −±0.00001 ± 0.1 −± 1.0 mAdc
Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF
Quiescent Current
(Per Package)
IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Note 3) (Note 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (0.8 mA/kHz) f + IDD
IT = (1.6 mA/kHz) f + IDD
IT = (2.4 mA/kHz) f + IDD
mAdc
3−State Leakage Current ITL 15 −± 0.1 −± 0.0001 ± 0.1 −± 3.0 mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C, See Figure 1)
Characteristic Symbol VDD
All Types
Unit
Typ
(Note 6) Max
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time (Figure 2)
Inhibit, Control, or Data to Z
tPLH 5.0
10
15
330
125
85
650
250
170
ns
Propagation Delay Time (Figure 2)
Inhibit, Control, or Data to Z
tPHL 5.0
10
15
330
125
85
650
250
170
ns
3−State Output Delay Times (Figure 3)
“1” or “0” to High Z, and
High Z to “1” or “0”
tPHZ, tPLZ,
tPZH, tPZL
5.0
10
15
60
35
30
150
100
75
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14512B
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4
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
ID
CL
Z
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VSS
PULSE
GENERATOR
50%Vin
50%
DUTY
CYCLE
Parameter Test Conditions
Inhibit to Z A, B, C = VSS, XO = VDD
A, B, C to Z Inh = VSS, XO = VDD
Figure 2. AC Test Circuit and Waveforms
VDD
VSS
VOH
VOL
VDD
VSS
VOH
VOL
VDD
CL
Z
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VSS
PULSE
GENERATOR
20 ns 20 ns
90%
50%
10%
tPLH tPHL
90%
10%
50%
DATA
Z
tTLH tTHL
TEST CONDITIONS:
INHIBIT = VSS
A, B, C = VSS
20 ns 20 ns
tPHL tPLH
50%
90%
10%
tTHL tTLH
Z
INHIBIT,
A, B, OR C 90%
50%
10%
Figure 3. 3−State AC Test Circuit and Waveform
Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open
Switch Positions for 3−State Test
Z
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VSS
PULSE
GENERATOR
VDD
VDD
CL
1k S1
S2
VSS
VDD
S3
S4
VSS
VDD
VOH
VOL
20 ns
90%
50%
10%
tPLZ tPZL
20 ns
DISABLE
INPUT
OUTPUT
OUTPUT
VSS
VOH
VOL
10%
90%
90%
10%
tPHZ tPZH
≈2.5 V @ VDD = 5 V,
10 V, AND 15 V
≈2 V @ VDD = 5 V
≈6 V @ VDD = 10 V
≈10 V @ VDD = 15 V
MC14512B
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5
LOGIC DIAGRAM
13
12
11
1
2
3
4
5
6
7
9
X7
X6
X5
X4
X3
X2
X1
X0
B
C
A
15
10
14
DISABLE
INHIBIT
VDD
Z
VSS
11
IN
OUT
IN
2
OUT
2
TRANSMISSION
GATE
SELECTED
DEVICE
MC14512B
MC14512B
MC14512B
IOD
ITL
ITL
IL
LOAD
DATA
BUS
3−STATE MODE OF OPERATION
Output terminals of several MC14512B 8−Bit Data
Selectors can be connected to a single date bus as shown.
One MC14512B is selected by the 3−state control, and the
remaining devices are disabled into a high−impedance “off”
state. The number of 8−bit data selectors, N, that may be
connected to a bus line is determined from the output drive
current, IOD, 3−state or disable output leakage current, ITL,
and the load current, IL, required to drive the bus line
(including fanout to other device inputs), and can be
calculated by:
ITL
N = + 1
IOD – IL
N must be calculated for both high and low logic state of the
bus line.
MC14512B
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6
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
MC14512B
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7
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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MC14512B/D
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