1061E
- 8/
00
®
Design Tools
System
Ve
rsion
Tools
Cadence
®
4.4.3
2.2.
s8
4.2 - s0
54
2.8.
s00
3.0.
21
Opu
s™ - Sche
mati
c and La
yout
NC
Ver
ilog
™ - Ve
ril
og Si
mulat
or
Pea
rl™
- St
at
ic P
at
h
Ver
ilog-
XL™
- Ver
ilog
Simula
to
r
BuildG
ates™ - Synthesi
s (Ambi
t)
Mentor/
Model
Tech™
5.4b
B2 and Later
Mode
lsim V
erilog
an
d VH
DL
(VITA
L)
Simu
lator
Qui
ckVHDL™
Syno
psy
s™
99.
05, 200
0.05
5.0.2
VSS™ -
VH
DL S
imulat
or
Design Co
mpi
ler™ -
Synth
esis
Te
st C
ompile
r™
- Sca
n In
sert
ion
and
ATPG
Prime
time™
- St
atic
Pat
h
VCS™
- Verilo
g Simulat
or
Exemplar
™
1999
.1j
Leon
ardo Spe
ctru
m™ - Synth
esi
s
Syn
te
st
2.3.0
2.3.0
1.6
TurboCheck
– Gate
TurboS
can
TurboF
aul
t
Suppliers Inquiry
Previous
Next
Link
Name *
Reason for Contact
General Inquiry
Place Order
Report Issue
Target Price (Option)
Email Address *
Message *
BOM / Attach Files (Option)
Maximum allowed file size is 10MB