PIC18F4523-I/PT - Microchip Technology

PIC18F2423/2523/4423/4523

Data Sheet

28/40/44-Pin, Enhanced Flash

Microcontrollers with 12-Bit A/D

and nanoWatt Technology

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Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrit y of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h ac t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

PIC18F2423/2523/4423/4523

Peripheral Highlights:

• 12-bit, up to 13-channel Analog-to-Digital

Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Dual analog comparators with input multiplexing

• High-current sink/source 25 mA/25 mA

• Three programmable external interrupts

• Four input change interrupts

• Up to 2 Capture/Compare/PWM (CCP) modules,

one with Auto-Shutdown (28-pin devices)

• Enhanced Capture/Compare/PWM (ECCP)

module (40/44-pin devices only):

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown an d auto-restart

• Master Synchronous Serial Port (MSSP) module

supporting 3-wire SPI (all 4 modes) and I2C™

Mast er an d Sla ve mod es

• Enhanced USART module:

- Supports RS-485, RS-232 and LIN 1.2

- RS-232 operation us ing internal oscillator

block (no external crystal required)

- Auto-wake-up on Start bit

- Auto-Baud Detect

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 5.8 μA, typical

• Sleep mode current down to 0.1 μA, typical

• Timer1 Oscil lator: 1.8 μA, 32 kHz, 2V

• Watchdog Timer: 2.1 μA

• Two-Speed Oscillator Start-up

Flexible Oscillator S tructure :

• Four Crystal modes, up to 25 MHz

• 4x Phase Lock Loop (available for crystal and

internal oscillators)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 25 MHz

• Internal oscillator block:

- 8 user-selectable f requencies, fr om 31 kHz to 8 MHz

- Provides a complete range of clock speeds

from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Sa fe Clo ck Mon ito r:

- Allows for safe shutdown if external clock stops

Special Microcontroller Features:

• C compiler optimized architecture:

- Optional extended instruction set designed to

optimize re-entrant code

• 100,000 erase/write cycle Enhanced Flash

program memory typical

• 1,000,000 erase/write c ycle Data EEPROM

memory typical

• Flash/Data EEPROM Retention: 100 years typical

• Self-programmable under software control

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single- Su pp ly In-Cir cu it Ser ial

Programming™ (ICSP™) via two pins

• In-Circu it De bu g (IC D ) via tw o pins

• Operating voltage range: 2.0V to 5.5V

• Programmable 16-level High/Low-Voltage

Detection (HLVD) module:

- Su pp o rts interr up t on Hig h/ Low-Voltage Detecti on

• Programmable Brown-out Reset (BOR):

- With software enable option

Device Program Memory Data Memory I/O 12-Bit

A/D (ch)

CCP/

ECCP

(PWM)

MSSP

EUSART

Comp. Timers

8/16-Bit

Flash

(bytes) # Single-Word

Instructions SRAM

(bytes) EEPROM

(bytes) SPI Master

I2C™

PIC18F2423 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3

PIC18F2523 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3

PIC18F4423 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3

PIC18F4523 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3

28/40/44-Pin, Enhanced Flash Microcontrollers with

12-Bit A/D and nanoWatt Technology

PIC18F2423/2523/4423/4523

Pin Diagrams

PIC18F2523

14 15

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

VSS

OSC1/CLKI(3)/RA7

OSC2/CLKO(3)/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(2)

RC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGD

RB6//KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

RB3/AN9/CCP2(2)

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

28-Pin PDIP, SOIC

PIC18F2423

Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.

2: RB3 is the alternate pin for CCP2 multiplexing.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

1011

121314 15

716

232425262728

PIC18F2423

RC0/T1OSO/T13CKI

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4KBI0/AN11

RB3/AN9/CCP2(2)

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

VSS

OSC1/CLKI(3)/RA7

OSC2/CLKO(3)/RA6

RC1/T1OSI/CCP2(2)

RC2/CCP1

RC3/SCK/SCL

PIC18F2523

28-Pin QFN(1)

PIC18F2423/2523/4423/4523

Pin Diagrams (Cont.’d)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

RB3/AN9/CCP2(1)

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

VSS

RD7/PSP7/P1D

RD6/PSP6/P1C

RD5/PSP5/P1B

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

VSS

OSC1/CLKI(2)/RA7

OSC2/CLKO(2)/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(1)

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0

RD1/PSP1

PIC18F4523

40-Pin PDIP

PIC18F4423

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

NC RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2(1)

RC0/T1OSO/T13CKI

OSC2/CLKO(2)/RA6

OSC1/CLKI(2)/RA7

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/SS/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

VSS

VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2(1)

44-Pin TQFP

PIC18F4523

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

PIC18F2423/2523/4423/4523

Pin Diagrams (Cont.’d)

PIC18F4423

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

MCLR/VPP/RE3

RB3/AN9/CCP2(2)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

NC RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1/P1A

RC1/T1OSI/CCP2(2)

RC0/T1OSO/T13CKI

OSC2/CLKO(3)/RA6

OSC1/CLKI(3)/RA7

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/SS/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

RC7/RX/DT

RD4/PSP4

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

VSS

VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

44-Pin QFN(1)

PIC18F4523

Note 1: It is recommended to connect the bottom pad of QFN package parts to VSS.

2: RB3 is the alternate pin for CCP2 multiplexing.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not

being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 5
PIC18F2423/2523/4423/4523
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations............................................................................................................................................................ 23
3.0 Power-Managed Modes........................... .. ....... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. .. .... ....... .. ........................................................ 33
4.0 Reset.......................................................................................................................................................................................... 41
5.0 Memory O rganization................................................................................................................................................................. 53
6.0 Flash Pro g ram Memory........................ .............................. ............................. ........................................................................... 73
7.0 Data EEPR OM Mem o ry...... ............... ............................. .............................. ............................................................................. 83
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89
9.0 Interrupts.................................................................................................................................................................................... 91
10.0 I/O Po rts....... ............... ....................... ....................... ....................... ........................................................................................ 105
11.0 Timer0 Module ......................................................................................................................................................................... 123
12.0 Timer1 Module ......................................................................................................................................................................... 127
13.0 Timer2 Module ......................................................................................................................................................................... 133
14.0 Timer3 Module ......................................................................................................................................................................... 135
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................... .... .......................................... 139
16.0 Enhanced Capture/Compare/PW M (ECCP) Module................................................................................................................ 147
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161
18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 205
19.0 12-Bit Analog-to-Digital Converter (A/D) Module .................................................... ........... .... .... .... .......................................... 227
20.0 Comparator Module................................ .... ....... .... .. .... .. ......... .. .... .. .... .. ......... .. .... .. .... ....... ........................................................ 237
21.0 Comparator Voltage Reference Module..... ......... .. .... .... ......... .. .... .... .... ......... .. .... .... ......... .. .... .... .............................................. 243
22.0 High/Low-Voltage Detect (HLVD).................................... ......... .... .... .... ........... .... .... ......... .... .................................................... 247
23.0 Spe cial Features of the CPU......................... ............................. ................... ................... ........................................................ 253
24.0 Instruction Set Summary.......................................................................................................................................................... 271
25.0 Development Support. .............................................................................................................................................................. 321
26.0 Electrical Characteristics.......................................................................................................................................................... 325
27.0 DC and AC Characteristics Graphs and Tables............................... .... ......... .... .. .... ......... .... .. .... .... .......................................... 363
28.0 Pack a g i n g  In fo rmation.................... ............................. .............................. ............................................................................... 365
Appendix A: Revision History . ............................................................................................................................................................ 373
Appendix B: Device Differences ........................................................................................................................................................ 373
Appendix C: Conversion Considerations ............. ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .... .. .................................................. 374
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 374
Appendix E: Migration from Mid-Range to Enhanced Devices............................... .... .... .... ......... .... .... ........... ................................... 375
Appendix F: Migration from High-End to Enhanced Devices...................................... .... .. ....... .... .... .. .... .. .......................................... 375
Index .................................................................................................................................................................................................  377
The Micro chip Web Site..................................... ....................... ........................ ................................................................................. 387
Customer Change Notification Service............................................................................. ............. .................................................... 387
Customer Support........................................ .... ............. ...... .... ............. ...... ............. ...... .... ................................................................. 387
Reader Response. ............................................................................................................................................................................. 388
PIC18F2423/2523/4423/4523 Product Identification System ............................................................................................................ 389

PIC18F2423/2523/4423/4523

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Customer Noti fic atio n Syst em

PIC18F2423/2523/4423/4523

1.0 DEVICE OVERVIEW

This docu ment contains dev ice -sp ec ifi c info rm ation for

the following devices:

• PIC18F2423

• PIC18F2523

• PIC18F4423

• PIC18F4523

This family offers the advantages of all PIC18

microcontrollers – namely, high computational perfor-

mance at an economical price – with the addition of

high-endurance, Enhanced Flash program memory.

On top of these features, the PIC18LF2423/2523/

4423/4523 family introduces design enhancements

that make these microcontrollers a logical choice for

many high-performance, power sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2423/2523/4423/4523

family incorporate a range of features that can signifi-

cantly reduce power consumption during operation.

Key items include:

•Alternate Run Modes: By clocking the controll er

from the Timer1 source or the internal oscillator

block, power consumption during code execution

can be reduced by as much as 90%.

•Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active . In these st ates, powe r consumptio n can be

reduced even further, to as little as 4% of normal

operation requirements.

•On-the-Fly Mode Switching: The

power-m anage d mod es are invo ked b y use r code

during operation, allowing the user to incorporate

power-saving ideas into their application’s

software design.

•Low Consumption in Key Modules: The

power requirements for both Timer1 and the

Watchdog Timer are minimized. See

Section 26.0 “Electrical Characteristics”

for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the dev ices in the PI C18LF2423/2 523/4423/ 4523

family offer ten different oscillator options, allowing

users a wide range o f choices i n developin g applica tion

hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4

clock output) or one pin (oscillator input, with the

second pin reassigned as general I/O).

• Two External RC Oscillator modes with the same

pin options as the External Clock modes.

• An internal oscillato r block w hich prov ides an

8 MHz clock and an INTRC source (approximately

31 kHz), as well as a range of six user-selectable

clock frequencies, betw een 125 kHz to 4 MHz, for

a total of 8 clock freque ncies. Thi s option frees the

two oscillator pins for use as additional general

purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the High-Speed Crystal and

Internal Oscillator modes, which allows clock

speeds of up to 40 MHz from the HS clock

source. Used with the internal oscillator, the PLL

give s users a com ple te selec tion of cl ock sp eeds,

from 31 kHz to 32 MHz, all without using an

external crystal or clock circuit.

Besides its availability as a clock source, the internal

oscill ato r blo ck pro vid es a s t ab le re ference so urc e th at

gives the family additional features for robust

operation:

•Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a refer-

ence signal pro vi ded by the internal os ci llator . If a

clock failure occurs, the controller is switched to

the intern al oscill ator block , allowing f or continue d

operation or a safe application shutdown.

•Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset , or wake-up from Sleep

mode, until the primary clock source is available.

PIC18F2423/2523/4423/4523

1.2 Oth er Special Features

• 12-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sa mpling p erio d and

thus, reducing code overhead.

•Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are

rated to last for many thousands of erase/write

cycles – up to 100,000 for program memory and

1,000,000 for EEPROM. Data retention without

refresh is conservatively estimated to be greater

than 40 year s.

•Self-Programmability: These devices can write

to their own program memory spaces under inter -

nal software control. By using a bootloader rou-

tine located in the protected Boot Block at the top

of prog ram memory, it becomes possible to cr eate

an application that can update itself in the field.

•Extended Instruction Set: The PIC18LF2423/

2523 /4423/ 4523 family introduces an opt ional

extens ion to the PIC18 instruc tion set, which ad ds

eight n ew instruc tions a nd an In dexed Ad dressing

mode. This extension, enabled as a device con-

figuration option, has been specifically designed

to optimize re-entrant application code originally

developed in high-level languages, such as C.

•Enhanced CCP module: In PWM mode, this

module provides 1, 2 or 4 modulated outputs for

controlling half-bridge and full-bridge drivers.

Other features include auto-shutdown, for dis-

abling PWM outputs on interrupt or other select

conditions and auto-restart, to reactivate outputs

once the condition has cleared.

•Enhanced Addressable USART: This serial

communication module is capable of standard

RS-232 operation an d provides support for th e LIN

bus protocol. Other enhancements include

automatic baud rate detection and a 16-bit Baud

Rate Genera tor for improved res olution. Whe n the

microcontroller is using the inte rnal oscillator

block, the EUSART provides stable operation for

applications that talk to the outside world without

using an external crystal (or its accompanying

power requirement).

•Extended Watchdog Timer (WDT): This

enhanc ed vers ion in corpora tes a 1 6-bit pre scale r,

allow ing an e xtende d tim e-out range that is st able

across operating voltage and temperature. See

Section 26.0 “Electrical Characteristics” for

time-out periods.

1.3 Details on Individual Family

Members

Devices in the PIC18F 2423/2523/44 23/4523 famil y are

available in 28-pin and 40/44-pin packages. Block

diagrams for the two groups are shown in Figure 1-1

and Figure 1-2.

The devices are differentiated from each other in five

ways:

1. Flash program memory (16 Kbytes for

PIC18LF2423/4423 devices and 32 Kbytes for

PIC18LF2523/4523).

2. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports on 28-pin de vices,

5 bidirectional ports on 40/44-pin devices).

4. CCP and Enhanced CCP implementation

(28-pin devices have 2 standard CCP mod-

ules, 40 /44-pin devic es hav e one st and ard CCP

module and one ECCP module).

5. Parallel Slave Port (present only on 40/44-pin

devices).

All other feature s for devi ces in th is family are ide ntical.

These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and

Table 1-3.

Members of the PIC18LF2423/2523/4423/4523 family

are available only as low-voltage devices, designated

by “LF” (such as PIC18LF2423), and function over a

VDD range of 2.0V to 3.6V.

PIC18F2423/2523/4423/4523

TABLE 1-1: DEVICE FEATURES

Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Progra m Me mor y (B yt es) 16384 3276 8 16384 32768

Progra m Me mor y

(Instructions) 8192 16384 8192 16384

Data Memory (Bytes) 768 1536 768 1536

Data EEPROM Me mo ry ( Byte s) 256 256 256 256

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 2 2 1 1

Enhanced

Capture/Compare/PWM Modules 0011

Serial C omm un ica ti ons MSSP,

Enhanced USART MSSP,

Enhanc e d USA R T MSSP,

Enha nced USART MSSP,

Enhanced USART

Parallel Co mmu nicat ion s (P SP) No No Yes Yes

12-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

Resets (and Delays) POR, BOR,

RESET Instruction,

Stack Full, S t ack

Underflow (PWRT, OST),

MCLR (o ptio na l) , WDT

POR, BOR ,

RESET Instruction,

S t ack Full, Stack

Underfl ow (PWR T, OST),

MCLR (optional), WDT

POR, BOR,

RESET Instruction,

Stack Full, S tack

Underflow (PWRT, OST),

MCLR ( opt iona l), WDT

POR, BOR,

RESET Instruction,

Stack Full, S t ack

Underf low (PWRT, OST),

MCLR (optio nal), WDT

Programmable

High/L ow-Volt ag e Det ect Yes Yes Yes Yes

Progra mma bl e B ro wn- ou t Rese t Yes Yes Yes Yes

Instruction Set 75 Instructions;

83 with Ext e nded

Inst ru ctio n S et en ab led

75 Instructions;

83 with Extended

Instruction Set enabled

75 Instructions;

83 with Extended

Instruction Set enabled

75 Instructions;

83 with Ext e nded

Instruction Set enabled

Packages 28-pin PDIP

28-pin SOIC

28-pin QFN

28-pin PDIP

28-pin SOIC

28-pin QF N

40- pi n PD IP

44-pin QFN

44-pin TQF P

40-pin PDIP

44-pin QFN

44-pin TQFP

PIC18F2423/2523/4423/4523

FIGURE 1-1: PIC18L F 242 3/252 3 ( 2 8-PI N) BLO CK D IA GRA M

Instruction

Decode and

Control

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(1)

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10

Data Latch

Dat a Memory

( 3.9 Kbytes )

Address Latch

Data Address<12>

Access

BSR FSR0

FSR1

FSR2

inc/dec

logic

Address

412 4

PCH PCL

PCLATH

31 Level Stack

Progr am Coun ter

PRODLPRODH

8 x 8 Multiply

BITOP 8

ALU<8>

Address Latch

Prog ram Memory

(16/32Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

RB2/INT2/AN8

RB3/AN9/CCP2(1)

PCLATU

PCU

OSC2/CLKO(3)/RA6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only availa ble when MCLR functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

RB4/KBI0/AN11

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

EUSARTComparator MSSP 12-Bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

CCP1

BOR Data

EEPROM

Instruction Bus <16>

STKPTR Bank

State Machine

Control Signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(3)

OSC2(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

VSS

MCLR(2)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSO

OSC1/CLKI(3)/RA7

T1OSI

PORTE

MCLR/VPP/RE3(2)

PIC18F2423/2523/4423/4523

FIGURE 1-2: PIC18LF4423/4523 (40/44-PIN) BLOCK DIAGRAM

Instruction

Decode and

Control

Data Latch

Data Memory

( 3.9Kbyt es )

Address Latch

Data Address<12>

Access

BSR FSR0

FSR1

FSR2

inc/dec

logic

Address

412 4

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP 8

ALU<8>

Address Latch

Prog ram Memory

(16/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PORTD

RD0/PSP0

PCLATU

PCU

PORTE

MCLR/VPP/RE3(2)

RE2/CS/AN7

RE0/RD/AN5

RE1/WR/AN6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to S ec tion 2 .0 “Osc illa to r Configu ra tions ” for additional information.

:RD4/PSP4

EUSARTComparator MSSP 12-Bit

ADC

Timer2Timer1 Timer3Timer0

CCP2

HLVD

ECCP1

BOR Data

EEPROM

Instruction Bus <16>

STKPTR Bank

State Machine

Control Signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(3)

OSC2(3)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

VSS

MCLR(2)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2(1)

RC2/CCP1/P1A

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2(1)

OSC2/CLKO(3)/RA6

RB4/KBI0/AN11

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

OSC1/CLKI(3)/RA7

PIC18F2423/2523/4423/4523

TABLE 1-2: PIC18LF2423/2523 PINOUT I/O DESCRIPTIONS

Pin Name Pin N um b e r Pin

Type Buffer

Type Description

PDIP,

SOIC QFN

MCLR/VPP/RE3

MCLR

VPP

RE3

126I

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the devic e.

Prog ramming voltage input.

Digital input.

OSC1/CLKI/RA7

OSC1

CLKI

RA7

96I

I/O

CMOS

TTL

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode; CMOS otherwise.

External clock source input. Always associated with pin

function OSC1. (See related OSC1/CLKI, OSC2/CLKO

pins.)

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

CLKO

RA6

10 7 O

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which has 1/4 the

frequency of OSC1 and denotes the instruction cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O=Output P =Power

Note 1: Default assignment for C CP2 when Configura tion bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

227

I/O

ITTL

Analog Digital I/O.

Analog input 0.

RA1/AN1

RA1

AN1

328

I/O

ITTL

Analog Digital I/O.

Analog input 1.

RA2/AN2/VREF-/CVREF

RA2

AN2

VREF-

CVREF

I/O

TTL

Analog

Digital I/O.

Analog input 2.

A/D reference voltage (low) input.

Comparator reference voltage output.

RA3/AN3/VREF+

RA3

AN3

VREF+

I/O

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

RA4/T0CKI/C1OUT

RA4

T0CKI

C1OUT

I/O

—

Digital I/O.

Timer0 external clock input.

Comparator 1 output.

RA5/AN4/SS/HLVDIN/

C2OUT

RA5

AN4

HLVDIN

C2OUT

I/O

TTL

Analog

TTL

Analog

—

Digital I/O.

Analog input 4.

SPI slave select input.

High/L ow-Voltage Detec t inpu t.

Comparator 2 output.

RA6 See t he OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-2: PIC18LF2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin N um b e r Pin

Type Buffer

Type Description

PDIP,

SOIC QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O=Output P =Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0/AN12

RB0

INT0

FLT0

AN12

21 18 I/O

TTL

Analog

Digital I/O.

External interrupt 0.

PWM Fault input for CCP1.

Analog input 12.

RB1/INT1/AN10

RB1

INT1

AN10

22 19 I/O

TTL

Analog

Digital I/O.

External interrupt 1.

Analog input 10.

RB2/INT2/AN8

RB2

INT2

AN8

23 20 I/O

TTL

Analog

Digital I/O.

External interrupt 2.

Analog input 8.

RB3/AN9/CCP2

RB3

AN9

CCP2(1)

24 21 I/O

I/O

TTL

Analog

Digital I/O.

Analog input 9.

Capture 2 input/Compare 2 output/PWM 2 output.

RB4/KBI0/AN11

RB4

KBI0

AN11

25 22 I/O

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

Analog input 11.

RB5/KBI1/PGM

RB5

KBI1

PGM

26 23 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGC

RB6

KBI2

PGC

27 24 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

28 25 I/O

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

TABLE 1-2: PIC18LF2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin N um b e r Pin

Type Buffer

Type Description

PDIP,

SOIC QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O=Output P =Power

Note 1: Default assignment for C CP2 when Configura tion bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

11 8 I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2

RC1

T1OSI

CCP2(2)

12 9 I/O

I/O

Analog

Digital I/O.

Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM 2 output.

RC2/CCP1

RC2

CCP1

13 10 I/O

I/O ST

ST Digital I/O.

Capture 1 input/Compare 1 output/PWM 1 output.

RC3/SCK/SCL

RC3

SCK

SCL

14 11 I/O

I/O

Digital I/O.

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C™ mode.

RC4/SDI/SDA

RC4

SDI

SDA

15 12 I/O

I/O

Digital I/O.

SPI data in.

I2C data I/O.

RC5/SDO

RC5

SDO

16 13 I/O

OST

—Digital I/O.

SPI data out.

RC6/TX/CK

RC6

17 14 I/O

I/O

—

Digital I/O.

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

18 15 I/O

I/O

Digital I/O.

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

RE3 — — — — See MCLR/VPP/RE3 pin.

VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

VDD 20 17 P — Positive supply for logic and I/O pins.

TABLE 1-2: PIC18LF2423/2523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin N um b e r Pin

Type Buffer

Type Description

PDIP,

SOIC QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O=Output P =Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

MCLR/VPP/RE3

MCLR

VPP

RE3

11818I

Master Clear (input) or programming voltage (input).

Master Cl ear (Reset) input. This pin is an activ e-low

Reset to the device.

Prog ramming v oltage input.

Digital input.

OSC1/CLKI/RA7

OSC1

CLKI

RA7

13 32 30 I

I/O

CMOS

TTL

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode;

analog otherwise.

External clock source input. Always associated with

pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

CLKO

RA6

14 33 31 O

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which

has 1/4 the frequency of OSC1 and denotes

the instruction cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for C CP2 when Configura tion bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

21919

I/O

ITTL

Analog Digi tal I/O.

Analog input 0.

RA1/AN1

RA1

AN1

32020

I/O

ITTL

Analog Digi tal I/O.

Analog input 1.

RA2/AN2/VREF-/CVREF

RA2

AN2

VREF-

CVREF

42121

I/O

TTL

Analog

Digital I/O .

Analog input 2.

A/D reference voltage (low) input.

Comparator reference voltage output.

RA3/AN3/VREF+

RA3

AN3

VREF+

52222

I/O

TTL

Analog

Digital I/O .

Analog input 3.

A/D reference voltage (high) input.

RA4/T0CKI/C1OUT

RA4

T0CKI

C1OUT

62323

I/O

—

Digital I/O .

Timer0 external clock input.

Comparator 1 output.

RA5/AN4/SS/HLVDIN/

C2OUT

RA5

AN4

HLVDIN

C2OUT

72424

I/O

TTL

Analog

TTL

Analog

—

Digital I/O .

Analog input 4.

SPI slave select inp ut.

High/Low-Voltage Detect input.

Comparator 2 output.

RA6 See the OSC2/CLKO/RA 6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTB is a bidirectional I/O port. PORTB can be

softwar e prog ram me d f or i nte rnal we ak pull-u p s on a ll

inputs.

RB0/INT0/FLT0/AN12

RB0

INT0

FLT0

AN12

33 9 8 I/O

TTL

Analog

Digital I/O .

External int errup t 0.

PWM Fault input for Enhanced CCP1.

Analog input 12.

RB1/INT1/AN10

RB1

INT1

AN10

34 10 9 I/O

TTL

Analog

Digital I/O .

External int errup t 1.

Analog input 10.

RB2/INT2/AN8

RB2

INT2

AN8

35 11 10 I/O

TTL

Analog

Digital I/O .

External int errup t 2.

Analog input 8.

RB3/AN9/CCP2

RB3

AN9

CCP2(1)

36 12 11 I/O

I/O

TTL

Analog

Digital I/O .

Analog input 9.

Capture 2 input/Compare 2 output/PWM 2 output.

RB4/KBI0/AN11

RB4

KBI0

AN11

37 14 14 I/O

TTL

Analog

Digital I/O .

Interrupt-o n-c han ge pin .

Analog input 11.

RB5/KBI1/PGM

RB5

KBI1

PGM

38 15 15 I/O

I/O

TTL

Digital I/O .

Interrupt-o n-c han ge pin .

Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGC

RB6

KBI2

PGC

39 16 16 I/O

I/O

TTL

Digital I/O .

Interrupt-o n-c han ge pin .

In-Circuit Debugger and ICSP programming

clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

40 17 17 I/O

I/O

TTL

Digital I/O .

Interrupt-o n-c han ge pin .

In-Circuit Debugger and ICSP programming

data pin.

TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for C CP2 when Configura tion bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

15 34 32 I/O

—

Digital I/O .

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2

RC1

T1OSI

CCP2(2)

16 35 35 I/O

I/O

CMOS

Digital I/O .

Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM 2 output.

RC2/CCP1/P1A

RC2

CCP1

P1A

17 36 36 I/O

I/O

—

Digital I/O .

Capture 1 input/Compare 1 output/PWM 1 output.

Enhanced CCP1 output.

RC3/SCK/SCL

RC3

SCK

SCL

18 37 37 I/O

I/O

Digital I/O .

Synchronous serial clock input/output for

SPI mode.

Synchronous serial clock input/output for I2C™ mode.

RC4/SDI/SDA

RC4

SDI

SDA

23 42 42 I/O

I/O

Digital I/O .

SPI dat a in.

I2C data I/O.

RC5/SDO

RC5

SDO

24 43 43 I/O

OST

—Digital I/O .

SPI data out.

RC6/TX/CK

RC6

25 44 44 I/O

I/O

—

Digital I/O .

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

26 1 1 I/O

I/O

Digital I/O .

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTD is a bidirectional I/O port or a Parallel Slave

Port (PSP) for interfacing to a microprocessor port.

These pins have TTL input buffers when the PSP

module is enabled.

RD0/PSP0

RD0

PSP0

19 38 38 I/O

I/O ST

TTL Digital I/O .

Parallel Slave Port data.

RD1/PSP1

RD1

PSP1

20 39 39 I/O

I/O ST

TTL Digital I/O .

Parallel Slave Port data.

RD2/PSP2

RD2

PSP2

21 40 40 I/O

I/O ST

TTL Digital I/O .

Parallel Slave Port data.

RD3/PSP3

RD3

PSP3

22 41 41 I/O

I/O ST

TTL Digital I/O .

Parallel Slave Port data.

RD4/PSP4

RD4

PSP4

27 2 2 I/O

I/O ST

TTL Digital I/O .

Parallel Slave Port data.

RD5/PSP5/P1B

RD5

PSP5

P1B

28 3 3 I/O

I/O

TTL

—

Digital I/O .

Parallel Slave Port data.

Enhanced CCP1 output.

RD6/PSP6/P1C

RD6

PSP6

P1C

29 4 4 I/O

I/O

TTL

—

Digital I/O .

Parallel Slave Port data.

Enhanced CCP1 output.

RD7/PSP7/P1D

RD7

PSP7

P1D

30 5 5 I/O

I/O

TTL

—

Digital I/O .

Parallel Slave Port data.

Enhanced CCP1 output.

TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for C CP2 when Configura tion bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

PORTE is a bidirectional I/O port.

RE0/RD/AN5

RE0

AN5

82525

I/O

TTL

Analog

Digital I/O .

Read control f or Parallel Slave P ort

(see also WR and CS pins).

Analog input 5.

RE1/WR/AN6

RE1

AN6

92626

I/O

TTL

Analog

Digital I/O .

Write control for Parallel Slave Port

(see CS and RD pins).

Analog input 6.

RE2/CS/AN7

RE2

AN7

10 27 27 I/O

TTL

Analog

Digital I/O .

Chip Select control for Parallel Slave Port

(see related RD and WR).

Analog input 7.

RE3 — — — — — See MCLR/VPP/RE3 pin.

VSS 12, 31 6, 30,

31 6, 29 P — Ground reference for logic and I/O pins.

VDD 11, 32 7, 8,

28, 29 7, 28 P — Positive supply for logic and I/O pins.

NC — 13 12, 13,

33, 34 — — No connect.

TABLE 1-3: PIC18LF4423/4523 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set.

2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

2.0 OSCILLATOR

CONFIGURATIONS

2.1 Oscillator Types

PIC18LF2423/2523/4423/4523 devices can be oper-

ated in ten different oscillator modes. The user can pro-

gram the Configuration bits, FOSC3:FOSC0, in

Configuration Register 1H to select one of these ten

modes:

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL Enabled

5. RC Exter nal R esistor/Capacitor with

FOSC/4 Output on RA6

6. RCIO External Resist or/Capacitor with I/O

on RA6

7. INTIO1 Internal Oscillator with FOSC/4 Output

on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with FOSC/4 Output

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator /Ceramic

Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or

ceramic resonator is connected to the OSC1 and

OSC2 pins to establish oscillation. Figure 2-1 shows

the pin connections.

The oscillator design requires the use of a parallel cut

crystal.

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION

(XT, LP, HS OR HSPLL

CONFIGURATION)

T ABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s

specifications.

Typical Capacitor Values Used:

Mode Freq. OSC1 OSC2

XT 3.58 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

Dif ferent cap acitor values may be required to prod uce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following Table 2-2 for additional

information.

Note: When using resonators with frequencies

above 3.6 MHz, the use of HS mode,

rather than XT mode, is recommended.

HS mode may be used at any VDD for

which the controller is rated. If HS is

selected, it is possible that the gain of the

oscillator will overdrive the resonator.

Therefore, a series resistor should be

placed between the OSC2 pin and the

resonator. As a good starting point, the

recommended value of RS is 330Ω.

Note 1: See Table 2-1 and T able 2-2 for initial values of

C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

Logic

PIC18FXXXX

RS(2)

Internal

PIC18F2423/2523/4423/4523

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

An external clock source may also be connected to the

OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC.

CONFIGURATION)

2.3 External Clock Input

The EC and ECIO Oscilla tor modes require an externa l

clock source to be conn ected to the OSC1 pi n. There is

no oscillator start-up time required after a Power-on

Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be us ed f or t e st pu r pos es or t o sy nc hr o n iz e ot he r

logic. Figure 2-3 shows the pin connections for the EC

Oscillator mode.

FIGURE 2-3: EXTERNAL CLOCK

INPUT OPERATION

(EC CONFIGURATION)

The ECIO O sc il lato r mo de func tio ns lik e t he EC mode,

except that the OSC2 pin becomes an additional gen-

eral purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-4 shows the pin connections

for the ECIO Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

INPUT OPERATION

(ECIO CONFIGURATION)

Osc.

Type Crystal

Freq.

Typical Capa citor V alues

Tested:

C1 C2

LP 32 kHz 18 pF 18 pF

XT 1 MHz

4 MHz 15 pF

15 pF 15 pF

15 pF

HS 4 MHz

10 MHz

20 MHz

25 MHz

15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed

below fo r ba si c start-up and operation. These values

are not optimized.

Dif ferent capa citor values may be require d to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following this table for additional

information. Cryst a ls Us ed:

32 kHz 4 MHz

25 MHz 10 MHz

1 MHz 20 MHz

Note 1: When operating below 3V VDD, or when

using ce ram ic res on ators abov e 3.6 MHz

at any voltage, it may be necessary to use

the HS mode or switch to a crystal

oscillator.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

3: RS may be required to avoid overdriving

tuning fork crystals, such as those com-

monly used in LP mode or with the T imer1

oscillator . RS may also be used to reduce

crystal drive in other modes where

waveform distortion could be an issue.

See AN949, “Making Your Oscillator

Work”.

4: Always veri fy os ci lla tor pe rform an ce ov er

the VDD and temperature range that is

expect ed for the applica tion. See AN949,

“Making Your Oscillator Work” for testing

methods.

OSC1

OSC2

Open

Clock from

Ext. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKO

FOSC/4

Clock from

Ext. System PIC18FXXXX

OSC1/CLKI

I/O (OSC2)

RA6

Clock from

Ext. System PIC18FXXXX

PIC18F2423/2523/4423/4523

2.4 RC Oscillator

For timing insensitive applications, the “RC” and

“RCIO” device options offer additional cost savings.

The actual oscillator frequency is a function of several

factors:

• supply voltage

• values of the external resistor (REXT) and

capacitor (CEXT)

• operating temperature

Given the same device, operating voltag e and tempera-

ture and component values, there will also be unit-to-unit

frequency variations. Thes e are due to factors such as:

• normal manufacturing variation

• difference in lead frame capacitance between

package types (especially for low CEXT values)

• variations within the tolerance of limits of REXT

and CEXT

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be u s ed f or t e st pu r pos es or t o sy nc hr o n iz e ot he r

logic. Figure 2-5 shows how the R/C combination is

connected.

FIGURE 2-5: RC OSCILLATOR MODE

The RCIO Oscillator mode (Figure 2-6) functions like

the RC mode, except that the OSC2 pin becomes an

additional general purpose I/O pin. The I/O pin

becomes bit 6 of PORTA (RA6).

FIGURE 2-6: RCIO OSCILLATOR MODE

2.5 PLL Frequency Multi plier

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower frequency

oscillator circuit, or to clock the device up to its highest

rated frequency from a crystal oscillator. This may be

useful for customers who are concerned with EMI due

to high-fre que nc y c rys tals, or us ers w ho re qui re h igh er

clock speeds from an internal oscillator.

2.5.1 HSPLL OSCILLATOR MODE

The HSPL L mode make s use of the HS mode oscil lator

for freque ncies u p to 10 MH z. A PLL t hen multipl ies the

oscillator output frequency by 4 to produce an internal

clock frequency up to 40 MHz. The PLLEN bit is not

available in this oscillator mode.

The PLL is only available to the crystal oscillator when

the FOSC3 :FOSC0 Config uration bit s are prog rammed

for HSPLL mode (= 0110).

FIGURE 2-7: PLL BLOCK DIAGRAM

(HS MODE)

2.5.2 PLL AND INTOSC

The PLL i s als o ava ilabl e to th e inte rnal os cill ator bl ock

when the INTOSC is configured as the primary clock

source. In thi s configura tion, the PLL i s enabled in so ft-

ware and generates a clock output of up to 32 MHz.

The operation of INTOSC with the PLL is described in

Section 2.6.4 “PLL in INTOSC Modes”.

OSC2/CLKO

CEXT

REXT

PIC18FXXXX

OSC1

FOSC/4

Internal

Clock

VDD

VSS

Recommended values: 5K ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

CEXT

REXT

PIC18FXXXX

OSC1 Internal

Clock

VDD

VSS

Recommended values: 5K ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

I/O (OSC2)

RA6

MUX

VCO

Loop

Filter

Crystal

Osc

OSC2

OSC1

PLL Enable

FIN

FOUT

SYSCLK

Phase

Comparator

HS Oscillator Enable

÷4

(from Configuration Register 1H)

HS Mode

PIC18F2423/2523/4423/4523
DS39755B-page 26 Preliminary © 2007 Microchip Technology Inc.
2.6 Internal Oscillator Block
The PIC1 8LF2423/2 523/4423/4 523 devic es inclu de an
internal oscillator block which generates two different
clock signals; either can be used as the micro-
controller’s clock source. This may eliminate the need
for external oscillator circuits on the OSC1 and/or
OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled whe n a clock frequ ency from 125 kHz
to 8 MHz is selected, and can provide 31 kHz if
required.
The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
sour ce; it is also ena bled automatic ally when an y of the
following are enabled: 
• Power -up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 30).
Addit ionally, the 31 kHz clock can be pro vided by either
the INTOSC, or INTRC clock sources, depending on
the INTSRC bit (OSCTUNE<7>).
2.6.1 INTIO MODES
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4, 
while  OSC1 fu nc tio ns  as RA 7 fo r dig it a l in put and 
output.
• In INTIO2 mode, OSC1 functions as RA7 and 
OSC2 functions as RA6, both for digital input and 
output.
2.6.2 INTOSC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz. 
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.
2.6.3 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica-
tion . Thi s is do ne by  writi ng to  the  OSCTUN E regi ster
(Register 2-1).
When the O SC TUN E reg is ter is  mo di fied , the  IN T O SC
frequency will begin shifting to the new frequency. The
INTOSC clock will stabilize within 1 ms. Code execu-
tion continues during this shift. There is no indication
that the shift has occurred.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”. 
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in Internal Oscillator modes.
2.6.4 PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the inter-
nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation. 
The PLL is available for use with the INTOSC when:
1. The primary clock is the INTOSC clock source
(selected in CONFIG1H<3:0>), and
2. The 4 or 8 MHz INTOSC output is selected.
Wr ite s to  the PLL EN bit w il l be ig nor ed un til  both  thes e
conditions are met.
2.6.5 INTOSC FREQUENCY DRIFT
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compens ation tec hniques  are di scus sed
in  Section 2.6.5.1 “Compensating with the
EUSART”, Section 2.6.5.2 “Compensating with the
Timers” and Sec tion 2.6.5.3 “C om pe nsa tin g w it h th e
CCP Module in Capture Mode”, but other techniques
may b e  us ed .

PIC18F2423/2523/4423/4523

2.6.5.1 Compensating with the EUSART

An adjustment may be required when the EUSART

begins to genera te framing e rrors or rec eive s data w ith

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high; to

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low; to

compensate, increment OSCTUNE to increase the

clock frequency.

2.6.5.2 Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is greater than expected, then the internal oscillator

bloc k is r unni ng too fast. To ad just for th is, d ecrem ent

the OSCTUNE register.

2.6.5.3 Compensating with the CCP Module

in Capture Mode

A CCP module can use free-running Timer1 (or

Timer3), clocked by the internal oscil lator block and an

external event with a known period (i.e., AC power

frequenc y). The ti me of the first ev ent is c aptured in the

CCPRxH:CCPRxL registers and is recorded for use

later. When the second event causes a capture, the

time of the firs t eve nt is su btra cte d fro m the tim e of th e

second event. Since the period of the external event is

known, the time difference between events can be

calculated.

If the measured time is much greater than the calcu-

lated time, the internal oscillator block is running too

fast; to compensate, decrement the OSCTUNE register .

If the measured time is much less than the calculated

time, the int er nal osci llator block is runn ing t oo slow ; to

compensate, increment the OSCTUNE register .

R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)

0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)

1 = PLL enabled for INTO SC (4 MHz and 8 MHz only)

0 = PLL disabled

bit 5 Unimplemented: Read as ‘0’

bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximu m frequency

• •

00001

00000 = Center frequency. Oscillator module is running at the calibrated frequency.

11111

• •

10000 = Minimum frequency

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See

Section 2.6.4 “PLL in INTOSC Modes” for detail s.

PIC18F2423/2523/4423/4523

2.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the PIC18LF2423/2523/

4423/4523 family includes a feature that allows the

device clock source to be switched from the main

oscillator to an alternate low-frequency clock source.

PIC18LF2423/2523/4423/4523 devices offer two alter-

nate clock sources. When an alternate clock source is

enabled, the various power-managed operating modes

are available.

Essentially, there are three clock sources for these

devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the External Crystal

and Resonator modes, the External RC modes, the

External Clock modes and the internal oscillator block.

The particular mode is defined by the FOSC3:FOSC0

Configuration bits. The details of these modes are

covered earlier in this chapter.

The secondary oscillators are those external sources

not connected to the OSC1 or OSC2 pins. These

sources may continue to operate even after the

controller is placed in a power-managed mode.

PIC18LF2423/2523/4423/4523 devices offer the

T imer1 osc illator as a second ary oscillat or . This oscill a-

tor , in all powe r-managed modes, is often the time base

for func tions such as a Real- Time Clock.

Most often, a 32.768 kHz watch crystal is connected

between the RC0/T1OSO/T13CKI and RC1/T1OSI

pins. Like the LP mode oscillator circuit, loading

capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in

Section 12.3 “Timer1 Oscillator”.

In additio n to being a primary clock source, the internal

oscillator block is available as a power-managed

mode cl oc k s ourc e. The INTRC s our ce i s al so us ed as

the clock source for several special features, such as

the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18LF2423/2523/4423/

4523 devices are shown in Figure 2-8. See

Section 23.0 “Special Features of the CPU” for

Configuration register details.

FIGURE 2-8: PI C18LF 24 23/2 523 /442 3/4 523 CLOC K DIAGRAM

PIC18F2423/2523/4423/4523

4 x PLL

FOSC3:FOSC0

Secondary Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for oth er Mod ules

OSC1

OSC2

Sleep HSPLL, INTOS C/P LL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

Postscaler

MUX

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON<6:4>

111

110

101

100

011

010

001

000

31 kHz

INTRC

Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON<6:4>

Clock

Control

OSCCON<1:0>

Source

8 MHz

31 kHz (INTRC)

OSCTUNE<6>

OSCTUNE<7>

and Two-Spee d Start-up

Primar y Osc illa to r

PIC18F2423/2523/4423/4523

2.7.1 OSCILLA TOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several

aspects of the device clock’s operation, both in full

power ope ratio n and in pow e r-ma nag ed mo des .

The System Clock Select bits, SCS1:SCS0, select the

clock source. The available clock sources are the

primary clock (defined by the FOSC3:FOSC0 Configu-

ration bits), the secondary clock (Timer1 oscillator) and

the internal oscillator block. The clock source changes

immediately after one or more of the bits is written to,

following a brief clock transition interval. The SCS bits

are cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits

(IRCF2:IRCF0) select the frequency output of the

internal oscillator block to drive the device clock. The

choices are the INTRC source, the INTOSC source

(8 MHz) or one of the frequencies derived from the

INTOSC postscaler (31.25 kHz to 4 MHz). If the

internal oscillator block is supplying the device clock,

changing the states of these bits will have an immedi-

ate change on the internal oscillator’s output. On

device Resets, the default output frequency of the

internal oscillator block is set at 1 MHz.

When a nominal ou tput frequenc y of 31 kHz is selecte d

(IRCF2:IRCF0 = 000), users may choose which inter-

nal oscillator acts as the source. This is done with the

INTSRC bit in the OSCTUNE register (OSCTUNE<7>).

Setting this bit selects INTOSC as a 31.25 kHz clock

source by enabling the divide-by-256 output of the

INTOSC postscaler. Clearing INTSRC selects INTRC

(nominally 31 kHz) as the clock source, and disables

the INTOSC clock source.

This option allows users to select the tunable and more

precise INTOSC as a clock source, while maintaining

power sa vings with a very lo w clock speed. R egardless

of the setting of INTSRC, INTRC always remains the

clock source for features such as the Watchdog Timer

and the Fail-Safe Clock Monitor.

The OSTS, IO FS an d T1 R UN bits ind ic ate whic h cl oc k

source is currently providing the device clock. The

OSTS bit indicates that the Oscillator Start-up Timer

has timed out and the primary clock is providing the

device clock in Primary Clock modes. The IOFS bit

indicates when the internal oscillator block has stabi-

lized and is providing the device clock in RC Clock

modes. The T1RUN bit (T1CON<6>) indicates when

the Timer1 oscillator is providing the device clock in

Secondary Clock modes. In power-managed modes,

only one of these three bits will be set at any time. If

none of these bits are set, the INTRC is providing the

clock or INTOSC has just started and is not yet stable.

The IDL EN bi t dete rmines i f th e device goes into Sleep

mode or one of the Idle modes when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power-M ana ged Modes”.

2.7.2 OSCILLATOR TRANSITIONS

PIC18LF2423/2523/4423/4523 devices contain

circuitry to prevent clock “glitches” when switching

between clock sources. A short pause in the device

clock occurs during the clock switch. The length of this

pause is the sum of two cycles of the old clock source

and three to four cycles of the new clock source. This

formula assumes that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

T imer 1 oscillat or is enable d by setting th e

T1OSCEN bit in the T ime r1 Control re gis-

ter (T1CON<3>). If the Timer1 oscillator

is not en abl ed, then any attempt to se lec t

a secon dary c loc k sour ce will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before

selecting the secondary clock source or a

very long delay may occur while the

Timer1 oscillator starts.

PIC18F2423/2523/4423/4523

R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Dev ice enters Idle mode on SLEEP instruction

0 = Device e nters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (INTOSC drives clock directly)

110 = 4 MHz

101 = 2 MHz

100 = 1 MHz(3)

011 = 500 kHz

010 = 250 kHz

001 = 125 kHz

000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running

0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable

0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Cloc k Select bits

1x = Internal oscillator block

01 = Secondary (Timer1) oscillator

00 = Primary oscillator

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.

3: Default output frequency of INTOSC on Reset.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 31
PIC18F2423/2523/4423/4523
2.8 Effects of Power-Managed Modes 
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2  pin, if us ed by th e oscillat or) will  stop oscil lating. 
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In Internal Oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source.  The  31 kHz INTRC ou tput ca n be us ed direc tly
to provide the clock and may be enabled to support
various special features regardless of the power-
managed mode (see Section 23.2 “Watchdog Timer
(WDT)”,  Section 23.3 “Two-Speed Start-up” and
Section 23.4 “Fail-Safe Clock Monitor” for more
informa tion  on WDT,  Fai l-Saf e Clo ck  M oni tor a nd Two-
Speed Start-up ). The IN TOSC  output  at 8 MHz may  be
used directly to clock the device or may be divided
down by the post scaler . The INT OSC output is disabled
if the clock is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep w ill increase th e current cons umed during S leep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock. Other features may be operating that do
not require a device clock source (i.e., MSSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 26.2 “DC Characteristics: Power-Down and
Supply Current”.
2.9 Power-up Delays
Power-up delays are controlled by two timers, so that
no exte rna l Reset c irc ui try  is  re qui red  fo r m os t a ppl ic a-
tions. The delays ensure that the device is kept in
Reset  until the  device powe r supply i s stable  under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 26-10). It is enabled by clearing (= 0) the
PWRTEN Configuration bit. 
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device  is k ept in  Res et for  an add itiona l 2 ms, follow ing
the HS mode OST delay, so the PLL can lock to the
inco mi ng cl ock  frequ enc y.
There is a delay of interval TCSD (parameter 38,
Table 26-10), following POR, while the controller
become s ready to ex ecute instruc tions. This del ay runs
concurrently with any other delays. This may be the
only de lay that occu rs when any of the E C, RC or  INTIO
modes are used as the primary clock source.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE  
Oscillator Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO Floating, external resistor should pull high Configured as PORTA, bit 6
INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent 
volt a ge lev el Feedback inverter disabled at quiescent 
voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

3.0 POWER-MANAGED MODES

PIC18LF2423/2523/4423/4523 devices offer a total of

seven operating modes for more efficient power man-

agemen t. These m odes prov ide a variety of options for

selective power conservation in applications where

resources may be limited (i.e., battery-powered

devices).

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

These categories define which portions of the device

are clo cked and some times , what sp eed. The Ru n and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

bloc k). The Sleep mode does not use a clock source.

The power-managed modes include several power-

saving features of fered on p reviou s PIC® devic es. On e

is the clock switching feature, offered in other PIC18

devices, allowing the controller to use the Timer1 oscil-

lator in plac e of the primary oscillator. Also included is

the Sleep mode, offered by all PIC devices, where all

device clocks are stopped.

3.1 Selecti ng Powe r-Managed Modes

Selecting a power-managed mode requires two

decisions: if the CPU is to be clocked or not and the

selection of a clock source. The IDLEN bit

(OSCCON<7>) controls CPU clocking, while the

SCS1:SCS0 bits (OSCCON<1:0>) select the clock

source. The individual modes, bit settings, clock sources

and af fected mod ules are sum mariz ed in Table 3-1.

3.1.1 CLOCK SOURCES

The SCS1: SCS0 bits allow the sele ction of one o f three

clock sources for power-managed modes. They are:

• the primary clock, as defined by the

FOSC3:FOSC0 Configuration bits

• the secondary clock (the Timer1 oscillator)

• the internal oscillator block (for RC modes)

3.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS1:SCS0 bits select the clock source to be used.

Changing these bits causes an immediate switch to the

new clock source, assuming that it is running. The switch

may also be subjec t to clock transition delays. These are

discussed in Section 3.1.3 “Clock Transitions and

Status Indicators” and subsequent s ections .

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator select

bits, or changing the IDL EN bit, prior to issuing a SLEEP

instruction. If the IDLEN bit is already configured

correctly, it may only be necessary to perform a SLEEP

instruction to switch to the de sired mod e.

TABLE 3-1: POWER-MANAGED MODES

Mode OSCCON Bits Module Clocking Available Clock and Oscillator Source

IDLEN<7>(1) SCS1:SCS0<1:0> CPU Peripherals

Sleep 0N/A Off Off None – All clocks are disabled

PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and

Internal Oscillator Block(2).

This is the normal full power execution mode.

SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator

RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)

PRI_IDLE 100Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC

SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator

RC_IDLE 11xOff Clocked Inter nal Oscil lator Bloc k (2)

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

PIC18F2423/2523/4423/4523

3.1.3 CLOCK TRANSITIONS AND S TATUS

INDICATORS

The length of the transition between clock sources is

the sum of two cyc les of the o ld clo ck so urce and thre e

to four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Three bits indicate the current clock source and its

status. They are:

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a

given power-managed mode. When the OSTS bit is

set, the primary clock is providing the device clock.

When the IOFS bit is set, the INTOSC output is

providing a stable 8 MHz clock source to a divider that

actually drives the de vice clock. When the T1RUN bit is

set, the Timer1 oscillator is providing the clock. If none

of these bits are set, then either the INTRC clock

source is clocking t he dev ic e, o r th e INTOSC source i s

not yet stable.

If the internal oscillator block is configured as the

primary clock source b y the FOSC3:FOSC0 Configura-

tion bit s, then both the OSTS and IOFS bit s may be set

when in PRI_RUN or PRI_IDLE modes. This indicates

that the pri ma ry c loc k (IN TOSC output) is genera t in g a

stable 8 MHz output. Entering another power-managed

RC mod e at the s ame frequenc y would c lear the O STS

bit.

3.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the

SLEEP instruction is determined by the setting of the

IDLEN bit at the time the instruction is executed. If

another SLEEP instruction is executed, the device will

enter the power-manag ed mode spe ci fie d by ID L EN at

that time. If IDLEN has changed, the device will enter

the new power-managed mode specified by the new

setting. Entry to, and exit from Idle mode, does not

affect the state of the IDLEN bit.

3.2 Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock sou rce.

3.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution

mode of the microcontroller. This is also the default

mode upon a device Reset, unless T wo-Speed S tart-up

is enabled (see Section 23.3 “Two-Speed Start-up”

for det ails). In thi s mode, the O STS bit is se t. The IOFS

bit may be set if the internal oscillator block is the

primary clock source (see Section 2.7.1 “Oscillator

Control Register”).

3.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clock ed from the T ime r1 oscill ator . This gives us ers the

option of lower power consumption while still using a

high accuracy clock source.

SEC_RUN mode is en tered by setting the SC S1:SCS0

bits to ‘01’. The device clock source is switched to the

Timer1 oscillator (see Figure 3-1), the primary oscilla-

tor is shut down, the T1RUN bit (T1CON<6>) is set and

the OSTS bit is cleared.

On transitions from SEC_RUN to PRI_RUN mode, the

peripherals and CPU continue to be clocked from the

Timer1 oscillator while the primary clock is started.

When t he prima ry clo ck becom es r eady, a clock sw itch

back to the primary clock occurs (see Figure 3-2).

When the clock switch is complete, the T1RUN bit is

cleared, the OSTS bit is set and the primary clock is

providing the clock. The IDLEN and SCS bits are not

affected by the wake-up; the Timer1 oscillator

continues to run.

Note 1: Caution should be used when modifying a

single IR CF bit. I f VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated

(see Figure 26-1 and Figure 26-2).

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either the Sleep mode or

one of the Idle modes, depending on the

setting of the IDLEN bit.

Note: The Timer1 oscillator should already be

running pri or to entering SEC_RUN mod e.

If the T1OSCEN bit is not set when the

SCS1:SCS0 bits are set to ‘01’, entry to

SEC_RUN mode will not occur. If the

Timer1 oscillator is enabled, but not yet

running, dev ice cloc ks wi ll be delayed until

the oscillator has started. In such situa-

tions, initial oscillator operation is far from

stable and unpredictable operation may

result.

PIC18F2423/2523/4423/4523

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

3.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer. In this mode, the primary clock is

shut down. When using the INTRC source, this mode

provides the best power conservation of all the Run

modes, while still executing code. It works well for user

applic atio ns wh ich are not hi ghly timin g sen si tiv e or do

not requ ire high-speed clocks at all times.

If the primary clock source is the internal oscillator

block (either INTRC or INTOSC), there are no distin-

guishable differences between PRI_RUN and

RC_RUN modes during execution. However, a clock

switch delay will occur during entry to and exit from

RC_RUN mode. Therefore, if the primary cloc k source

is the internal oscillator block, the use of RC_RUN

mode is not recommended.

This mode is entered by setting the SCS1 bit to ‘1’.

Although it is ignored, it is recommen ded that the SCS0

bit also be c leared; this is t o ma int ain softwa re comp at-

ibility with future devices. When the clock source is

switched to the INTOSC multiplexer (see Figure 3-3),

the primary oscillator is shut down and the OSTS bit is

cleared. The IRCF bits may be modified at any time to

immediately change the clock speed.

Q4Q3Q2

OSC1

Peripheral

Program

T1OSI

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition(1)

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q1 Q3 Q4

OSC1

Peripheral

Program PC

T1OSI

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

SCS1:SC S0 bi ts Changed

TPLL(1)

12 n-1n

Clock

OSTS bit Set

Transition(2)

TOST(1)

Note: Cau tio n s hou ld be u se d w he n m odi fy ing a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated

(see Figure 26-1 and Figure 26-2).

PIC18F2423/2523/4423/4523

If the IRCF bits and the INTSRC bit are all clear, the

INTOSC output is not enabled and the IOFS bit will

remain clear; there will be no indication of the current

clock source. The INTRC source is providing the

device clocks.

If the IRCF bits are changed from all clear (thus,

enabling the INTOSC output) or if INTSRC is set, the

IOFS bit becomes set after the INTOSC output

becomes stable. Clocks to the device continue while

the INTOSC source stabilizes after an interval of

TIOBST.

If the IR CF b its were previous ly at a no n-z ero val ue, or

if INTSRC was set before setting SCS1 and the

INTOSC source was already stable, the IOFS bit will

remain set.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multipl exer whil e the primary clo ck is st arted . When th e

prim ary cl oc k b ec ome s ready, a cloc k s w itc h t o the pri-

mary clock occurs (see Figure 3-4). When the clock

switch is complete, the IOFS bit is cleared, the OSTS

bit is set and the primary clock is providing the device

clock. T he IDLEN an d SC S bit s are not af fe cte d by the

switch. The INTRC source will continue to run if either

the WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q4Q3Q2

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition(1)

Q4Q3Q2 Q1 Q3Q2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

Q1 Q3 Q4

OSC1

Peripheral

Program PC

INTOSC

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock trans iti on typica ll y occurs wi thin 2-4 TOSC.

SCS1:SCS0 bits Changed

TPLL(1)

12 n-1 n

Clock

OSTS bit Set

Transition(2)

Multiplexer

TOST(1)

PIC18F2423/2523/4423/4523

3.3 Sleep Mode

The powe r-managed Sleep mo de in the PIC18LF2423/

2523/4423/4523 devices is identical to the legacy

Sleep mode offered in all other PIC devices. It is

entered by clearing the IDLEN bit (the default state on

device Reset) and executing the SLEEP instruction.

This shuts down the selected oscillator (Figure 3-5). All

clock source status bits are cleared.

Entering t he Sleep mode from any other mode does n ot

require a clock switch. This is because no clocks are

needed once the controller has entered Sleep. If the

WDT is selected, the INTRC source will continue to

operate. If the Timer1 oscillator is enabled, it will also

continue to run.

When a wake even t occurs i n Sleep mo de (by int errupt,

Reset or WDT time-o ut), the devi ce wil l not be clocke d

until the clock source selected by the SCS1:SCS0 bits

becomes ready (see Figure 3-6), or it will be clocked

from the internal oscillator block if either the Two-

Speed Start-up or the Fail-Safe Clock Monitor are

enabled (see Section 23.0 “Special Features of the

CPU”). In either case, the OSTS bit is set when the

primary clock is providing the device clocks. The

IDLEN and SCS bits are not affected by the wake-up.

3.4 Idle Modes

The Idle modes allow the controller’s CPU to be shut

down while the peripherals continue to operate.

Selecting a particular Idle mode allows users to further

manage power consumption.

If the IDLEN bit i s set to a ‘1’ when a SLEEP in struction is

exec uted, the periph erals will be cl ocked fr om the cl ock

source selected using the SCS1 :SCS0 bits; however, the

CPU will not be clocked. The clock source status bits are

not affected. Setting IDLEN and executing a SLEEP

instr uction pro vides a qu ick method of switchi ng fr om a

given R u n m o de to its corresp onding Id le mod e.

If the WDT is selected, the INTRC source will continue

to operate . If the T imer1 oscillato r is enabled, it will also

continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

tim e-out or a Reset. When a wa ke even t occur s, CPU

execution is delayed by an interval of TCSD

(parameter 38, Table 26-10) while it becomes ready to

execute code. When the CPU begins executing code,

it resumes with the same clock source for the current

Idle mode. For example, when waking from RC_IDLE

mode, the internal oscillator block will clock the CPU

and peripherals (in other words, RC_ RUN mo de). The

IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS1:SCS0 bits.

FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q4Q3Q2

OSC1

Peripheral

Sleep

Program

Q1Q1

Counter

Clock

CPU

Clock

PC + 2PC

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program PC

PLL Clock

Q3 Q4

Output

CPU Clock

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter PC + 6

PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST(1) TPLL(1)

OSTS bit Set

PC + 2

PIC18F2423/2523/4423/4523

3.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the faste st resump tion of device op eration with its more

accur ate prima ry clock source , since the clock sou rce

does not have to “warm-up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the C PU is disab led, th e periphe rals c ontinu e

to be clocked from the primary clock source specified

by the FOSC3:FOSC0 Configuration bits. The OSTS

bit remains set (see Figure 3-7).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become read y to execute in structions. Aft er the wake-

up, the OSTS bit remains set. The IDLEN and SCS bits

are not affected by the wake-up (see Figure 3-8).

3.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator . This mode is entered from SEC_RUN by set-

ting the IDLEN bit and exec uting a SLEEP instruction. If

the device is in another Run mode, set the IDLEN bit

first, then set the SCS1:SCS0 bits to ‘01’ and exec ute

SLEEP. When the clock source is switched to the

Timer1 oscillator, the primary oscillator is shut down,

the OSTS bit is cleared and the T1RUN bit is set.

When a w ake event o ccurs, the pe ripherals contin ue to

be clocked from the Timer1 oscillator. After an interval

of TCSD fol lowing t he wa ke eve nt, the C PU b egins exe-

cuting c ode being c locked by the Timer1 osc illator. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 3-8).

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when the

SLEEP instruction is executed, the SLEEP

instruction will be ignored and entry to

SEC_IDLE mode will not occur. If the

Timer1 oscillator is enabled but not yet

running, peripheral clocks will be delayed

until the oscillator has started. In such sit-

uations, initial oscillator operation is far

from stable and unpredictable operation

may re sult.

Peripheral

Program PC PC + 2

OSC1

Q3 Q4 Q1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Wake Event

TCSD

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 39
PIC18F2423/2523/4423/4523
3.4.3 RC_IDLE MODE
In RC_I DL E m od e, t he  C PU  is  d is abl ed  but  th e p erip h-
erals  co nti nue  to b e c loc ke d fro m the internal oscillator
block using the INTOSC multiplexer. This mode allows
for cont rollable  power c onservation  during  Idle periods .
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device  is in a nother Run m ode, first set  IDLEN, th en set
the SCS1 bit and execute SLEEP. Although its value is
ignored,  it is re comm ended  that SC S0 also  be cle ared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select  a higher clock frequency by modifying the IRCF
bits be for e ex ecut in g the SLEEP instruction. When the
clock source is swi tched to the INT OSC multiplexer , the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 26-10). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruct ion was exe-
cuted and the INTOSC source was already stable, the
IOFS bit will remain set. If the IRCF bits and INTSRC
are all clear , the INTOSC output  will not be enabled, the
IOFS bit  will remain c lear and there  will be no ind ication
of the current clock source.
When a w ake event o ccurs, the pe ripherals  continue  to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wa ke  event,  the CP U begins  exe-
cuting code being clocked by the INTOSC multiplexer.
The ID LEN a nd  SC S b it s  a re  not  affected by the wake-
up. The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sle ep Mode” and Section 3.4 “Idle Modes”). 
3.5. 1 EXIT BY  INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source m us t  be en ab led  by s etti ng i t s enable bi t in on e
of the INTCON or PIE registers. The exit sequence is
initiate d when the c orresponding  interrupt flag  bit is set.
On all ex its from Idl e or Sleep mod es by interrupt,  code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code execu-
tion continues or resumes without branching (see
Section 9.0 “Interrupts”).
A fixed  delay of interval TCSD fol lo w i ng  the w ak e ev en t
is required when leaving Sleep and Idle modes. This
del ay is required for the CPU t o prepare  for execut ion.
Instruction execution resumes on the first clock cycle
following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If th e dev ice is  not ex ecut ing  code ( all  Idle mo des a nd
Sleep mod e), th e time-o ut w ill res ul t in a n ex it fro m the
power-managed mode (see Section 3.2 “Run
Modes” a nd Section 3.3 “Sleep Mode”).  If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 23.2 “Watchdog
Timer (WDT)”). 
The WDT timer and postscaler are cleared by
executi ng  a  SLEEP or CLRWDT instru ction,  the lo ss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.
3.5. 3 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins e xe cu ting code . If the intern al o sc il lat or block i s
the new clock source, the IOFS bit is set instead. 
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 23.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 23.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the  Re set  sourc e ha s cle ared. Execut ion  is
clock ed by  the  INTOSC mu lti plexer driv en b y th e inter-
nal osc illator bl ock. Exec ution is  clocked by  the interna l
oscillator block until either the primary clock becomes
ready or a  power-ma naged  mode i s ente red befo re the
primary  clock be comes re ady; the pri mary clo ck is the n
shut down.

PIC18F2423/2523/4423/4523

3.5.4 EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source

is not stopped and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these instances, the primary clock source is either

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (RC, EC and INTIO

Oscillator modes). However, a fixed delay of interval

TCSD following the wake event is still required when

leaving Sleep and Idle modes to allow the CPU to

prepare for execution. Instruction execution resumes

on the first clock cycle following this delay.

TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up Clock Source

after Wake-up Exit Delay Clock Ready Status

Bit (OSCCON)

Primary Device Clock

(PRI_IDLE mode)

LP, XT, HS

TCSD(1) OSTS

HSPLL

EC, RC

INTOSC(2) IOFS

T1OSC or INTRC(1)

LP, XT, HS TOST(3)

OSTSHSPLL TOST + trc(3)

EC, RC TCSD(1)

INTOSC(1) TIOBST(4) IOFS

INTOSC(2)

LP, XT, HS TOST(4)

OSTSHSPLL TOST + trc(3)

EC, RC TCSD(1)

INTOSC(1) None IOFS

None

(Sleep mode)

LP, XT, HS TOST(3)

OSTSHSPLL TOST + trc(3)

EC, RC TCSD(1)

INTOSC(1) TIOBST(4) IOFS

Note 1: TCSD (par ame ter 38 ) is a requir ed del ay w hen wa king from Sl eep an d all Idle modes and runs conc urrentl y

with any other required delays (see Sec tion 3.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz.

2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.

3: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is

also designated as TPLL.

4: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 41
PIC18F2423/2523/4423/4523
4.0 RESET
The PIC 18LF 2423/ 2523 /4423 /452 3 dev ices  dif fere ntiat e
between various kinds of Reset: 
a) Power-on Reset (POR) 
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes 
d) Watchdog Timer (WDT) Reset (during 
execution)
e) Programmable Brown-out Reset (BOR) 
f) RESET Inst ruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BO R and  cov ers the  ope rati on of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Re se ts ar e co v ere d i n Section 23.2 “Watchdog
Timer (WDT)”.
A simp lified  block di agram o f the on -chip R eset cir cuit
is sh own i n Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indic ate that a spec ific Reset  event has oc curred. In
most ca ses, these b its can o nly be clear ed by the e vent
and mus t be s et by the  app lic at ion  afte r the event. Th e
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT        
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC
(1)
 
POR Pulse
OST
10-Bit Ripple Counter
PWRT
11-Bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is the INTRC source  from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Brown-out
Reset BOREN
RESET
Instruction
Stack
Pointer Stack Full/Underflow Reset
Sleep
( )_I D LE
1024 Cycles
65.5 ms
32 μs
MCLRE
S
RQChip_Reset

PIC18F2423/2523/4423/4523

R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0

IPEN SBOREN —RITO PD POR BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit(1)

If BOREN1:BOREN0 = 01:

1 = BOR is enabled

0 = BOR is disabled

If BOREN1:BOREN0 = 00, 10 or 11:

Bit is disabled and read as ‘0’.

bit 5 Unimplemented: Read as ‘0’

bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)

0 = The RESET instruction was executed causing a device Reset (must be set in software after a

Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD: Power-Down Detection Flag bit

1 = Set by power-up or by the CLRWDT instru ction

0 = Set by ex ecution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit(2)

1 = A Power-on Reset has not occurred (set by firmware only)

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Re set Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this

Note 1: It is recommende d tha t the POR bi t be s et a fter a Po wer-on R ese t ha s be en d etec ted so that sub seq ue nt

Power-on Resets m ay be detected .

2: Brown-out Re se t is sa id to h ave occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to

‘1’ by software immediately after POR).

PIC18F2423/2523/4423/4523

4.2 Master Clear (MCLR)

The MCLR pin provides a method for triggering an

external Reset of the device. A Reset is generated by

hold ing the pin low . T hese devi ces have a noise fi lter in

the MCLR Reset path which detects and ignores small

pulses.

The MCLR pin i s not dri ven l ow b y any i nter nal Res ets ,

including the WDT.

In PIC18LF2423/2523/4423/4523 devices, the MCLR

input can be disabled with the MCLRE Configuration

bit. When MC LR is disabled, the pin becomes a digital

input. See Section 10.5 “PORTE, TRISE and LATE

Registers” for more information.

4.3 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR

pin th rou gh a res is tor ( 1 kΩ to 10 kΩ) to VDD. Thi s will

eliminate external RC components usually needed to

create a Power-on Re set delay. A minimum rise rate for

VDD is specified (parameter D004). For a slow rise

time, see Figure 4-2.

When the devic e s t a rts normal ope rati on (i.e., exits the

Reset condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

POR events are captured by the POR bit (RCON<1>).

The state of the bit is set to ‘0’ whenev er a POR occ urs;

it does not change for any other Reset event. POR is

not reset to ‘1’ by any hardware event. To capture

multiple events, the user manually resets the bit to ‘1’

in software following any POR.

FIGURE 4-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR from external capacitor C, i n the event

of MCLR/VPP pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overs tress (EOS).

VDD

MCLR

PIC18FXXXX

VDD

PIC18F2423/2523/4423/4523

4.4 Brown-out Reset (BOR)

PIC18LF2423/2523/4423/4523 devices implement a

BOR circuit that provides the user with a number of

configuration and power-saving options. The BOR is

controlled by the BORV1:BORV0 and

BOREN1:BOREN0 Configuration bits. There are a total

of four BOR configurations which are summarized in

Table 4-1.

The BOR t hreshold is set b y the BOR V1:BOR V0 bi ts. If

BOR is enabled, any drop of VDD below VBOR (param-

eter D005) for greater than TBOR (parameter 35) will

reset the device. A Reset may or may not occur if VDD

falls below VBOR for less than TBOR. The chip will

remain in Brown-out Reset until VDD rises above VBOR.

If the Po wer-up T imer is enabled, i t will be inv oked after

VDD rises above VBOR; it then will keep the chip in

Reset for an additional time delay, TPWRT

(parameter 33). If VDD drops below VBOR while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be

initialized. Once VDD rises above VBOR, the Power-up

Timer will execute the additional time delay.

BOR and the Power-on Timer (PWRT) are

independently configured. Enabling BOR Reset does

not automatically enable t he PW RT.

4.4.1 SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be

enabled or disabled by the user in software. This is

done with the control bit, SBOREN (RCON<6>).

Setting SBOREN enables the BOR to function as

previously described. Clearing SBOREN disables the

BOR entirely. The SBOREN bit operates only in this

mode; oth erwise it is re ad as ‘0’.

Placing the BOR under software control gives the user

the additional flexibility of tailoring the application to its

environ me nt w it hou t ha vi ng to reprog ram the devi ce to

change BOR configuration. It also allows the user to

tailor device power consumption in software by elimi-

nating the incremental current that the BOR consumes.

While the BOR current is typically very small, it may

have some impact in low-power applications.

4.4.2 DETECTING BOR

When BO R is enab led, the BO R bit always resets to ‘0’

on any BOR or POR event. This makes it difficult to

determin e if a BOR eve nt ha s occ urre d jus t by reading

the state of BOR alone. A more reliable method is to

simultaneously check the state of both POR and BOR.

This as sumes that t he POR bit is re set to ‘1’ in softwa re

immediately after any POR event. If BOR is ‘0’ while

POR is ‘1’, it can be reli ably assumed th at a BOR event

has occurred.

4.4.3 DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains

under hardware control and operates as previously

described. Whenever the device enters Sleep mode,

howev er, the BOR is au tom ati ca lly dis abl ed . When the

device returns to any other operating mode, BOR is

automatically re-enabled.

This mode allows for applications to recover from

brown-out situations, while actively executing code,

when the device requires BOR protection the most. At

the same time, it save s additional po wer in Sleep mode

by eliminating the small incremental BOR current.

TABLE 4-1: BOR CONFIGURATIONS

Note: Even when BOR is under softwa re control,

the BOR Reset voltage level is still set by

the BORV1:BORV0 Configuration bits. It

cannot be changed in software.

BOR Configuration Status of

SBOREN

(RCON<6>) BOR Operation

BOREN1 BOREN0

00Ignored BOR disabled; must be enabled by reprogramming the Configuration bits.

01Available BOR enabled in software; operation controlled by SBOREN.

10Ignored BOR enabled in hardware in Run and Idle modes, disabled during

Sleep mode.

11Ignored BOR enabled in hardware.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 45
PIC18F2423/2523/4423/4523
4.5 Device Reset Timers
PIC18LF2423/2523/4423/4523 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time -out
4.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18LF2423/2523/
4423/4523 devices is an 11-bit counter which uses
the INTRC sour ce as the clock input. This yields an
approximate time interval of 2048 x 32 μs=65.6ms.
While the PWRT is counting, the device is held in
Reset.
The powe r-up tim e de lay  depe nd s on the  INTRC  cl oc k
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit. 
4.5.2 OSCIL LATOR START-UP TIMER 
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT del ay  is  ov er  (par a me t er 3 3 ). T h is  en su re s t ha t
the crystal or resonator oscillator has started and is
stab le enou gh to  to clock the  controll er. More tim e may
be required for the oscillator to meet its frequency
tolerance specification.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most pow er-ma nag ed mod es .
4.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to  p rov ide  a fixe d  tim e-o ut  that is  su f f i cient for th e
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. The PO R pulse clears. 
2. PWRT time-out is invoked (if enabled).
3. The OST time-out is invoked. The oscillator
starts at the beginning of this period.
4. PLL lock time-out (if using HSPLL mode).
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT  disabled, on
the other hand, there will be no time-out at all.
Since the  time-outs  occur from the PO R pulse, if MCLR
is kept  low  long e nough,  all ti me-outs will exp ire. Brin g-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS  
Oscillator
Configuration
Power-up(2) and Brown-out Exit from 
Power-Managed Mode
PWRTEN = 0PWRTEN = 1
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024  TOSC 1024 TOSC
EC, ECIO 66 ms(1) ——
RC, RCIO 66 ms(1) ——
INTIO1, INTIO2 66 ms(1) ——
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.

PIC18F2423/2523/4423/4523

FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

FIGURE 4-4: TIME-O UT SEQUENCE ON POWER-UP (MCL R RISES BEFORE T OST COMPLETES)

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR RISES AFTER T OST COMPLETES)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

OSC1

TPWRT

TOST

VDD

MCLR

INTER N AL PO R

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

OSC1

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

OSC1

PIC18F2423/2523/4423/4523

FIGURE 4-6: SL OW VDD RISE TIME (MCLR TIED TO VDD, VDD RIS E > TPWRT)

FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

0V 3V

TPWRT

TOST

OSC1

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 OSC1 cycles. TPLL ≈ 2 ms max.

OSC1

PIC18F2423/2523/4423/4523

4.6 Reset State of Registers

Most registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. The other registers are forced to a “Reset

state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BO R, are set or cle ared dif ferently i n dif ferent

Reset situations, as indicated in Table 4-3. These bits

are used in software to determine the nature of the

Reset.

Table 4-4 describes the Reset states for all of the

Special Function Registers. These are categorized by

Power-on and Brown-out Resets, Master Clear and

WDT Resets and WDT wake-ups.

TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

Condition Program

Counter

RCON Register STKPTR Register

RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 11100 0 0

RESET Instruction 0000h 0uuuu u u

Brown-out Reset 0000h 111u0 u u

MCLR during Power-Managed

Run Modes 0000h u1uuu u u

MCLR during Power-Managed Idle

Modes and Sle ep Mo de 0000h u10uu u u

WDT Time-out du ring Fu ll Pow e r o r

Power-Managed Run Mode 0000h u0uuu u u

MCLR during Full Power Execution 0 000h uuuuu u u

Stack Full Reset (STVREN = 1) 0000h uuuuu 1 u

Stack Und erflow Reset

(STVREN = 1)0000h uuuuu u 1

Stack Underflow Error (not an

actual Reset, STVREN = 0)0000h uuuuu u 1

WDT Time-out during

Power-Managed Idle or Sleep

Modes

PC + 2 u00uu u u

Interrupt Exit from

Power-Managed Modes PC + 2(1) uu0uu u u

Legend: u = unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

inter rupt ve cto r (008h or 0018 h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

PIC18F2423/2523/4423/4523

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

TOSU 2423 2523 4423 4523 ---0 0000 ---0 0000 ---0 uuuu(3)

TOSH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu(3)

TOSL 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu(3)

STKPTR 2423 2523 4423 4523 00-0 0000 uu-0 0000 uu-u uuuu(3)

PCLATU 2423 2523 4423 4523 ---0 0000 ---0 0000 ---u uuuu

PCLATH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

PCL 2423 2523 4423 4523 0000 0000 0000 0000 PC + 2(2)

TBLPTRU 2423 2523 4423 4523 --00 0000 --00 0000 --uu uuuu

TBLPTRH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TBLPTRL 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TABLAT 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

PRODH 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON 2423 2523 4423 4523 0000 000x 0000 000u uuuu uuuu(1)

INTCON2 2423 2523 4423 4523 1111 -1-1 1111 -1-1 uuuu -u-u(1)

INTCON3 2423 2523 4423 4523 11-0 0-00 11-0 0-00 uu-u u-uu(1)

INDF0 2423 2523 4423 4523 N/A N/A N/A

POSTINC0 2423 2523 4423 4523 N/A N/A N/A

POSTDEC0 2423 2523 4423 4523 N/A N/A N/A

PREINC0 2423 2523 4423 4523 N/A N/A N/A

PLUSW0 2423 2523 4423 4523 N/A N/A N/A

FSR0H 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

FSR0L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

WREG 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 2423 2523 4423 4523 N/A N/A N/A

POSTINC1 2423 2523 4423 4523 N/A N/A N/A

POSTDEC1 2423 2523 4423 4523 N/A N/A N/A

PREINC1 2423 2523 4423 4523 N/A N/A N/A

PLUSW1 2423 2523 4423 4523 N/A N/A N/A

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

PIC18F2423/2523/4423/4523

FSR1H 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

FSR1L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

BSR 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

INDF2 2423 2523 4423 4523 N/A N/A N/A

POSTINC2 2423 2523 4423 4523 N/A N/A N/A

POSTDEC2 2423 2523 4423 4523 N/A N/A N/A

PREINC2 2423 2523 4423 4523 N/A N/A N/A

PLUSW2 2423 2523 4423 4523 N/A N/A N/A

FSR2H 2423 2523 4423 4523 ---- 0000 ---- 0000 ---- uuuu

FSR2L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS 2423 2523 4423 4523 ---x xxxx ---u uuuu ---u uuuu

TMR0H 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TMR0L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

OSCCON 2423 2523 4423 4523 0100 q000 0100 q000 uuuu uuqu

HLVDCON 2423 2523 4423 4523 0-00 0101 0-00 0101 u-uu uuuu

WDTCON 2423 2523 4423 4523 ---- ---0 ---- ---0 ---- ---u

RCON(4) 2423 2523 4423 4523 0q-1 11q0 0q-q qquu uq-u qquu

TMR1H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 2423 2523 4423 4523 0000 0000 u0uu uuuu uuuu uuuu

TMR2 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

PR2 2423 2523 4423 4523 1111 1111 1111 1111 1111 1111

T2CON 2423 2523 4423 4523 -000 0000 -000 0000 -uuu uuuu

SSPBUF 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SSPCON1 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SSPCON2 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

PIC18F2423/2523/4423/4523

ADRESH 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 2423 2523 4423 4523 --00 0000 --00 0000 --uu uuuu

ADCON1 2423 2523 4423 4523 --00 0qqq --00 0qqq --uu uuuu

ADCON2 2423 2523 4423 4523 0-00 0000 0-00 0000 u-uu uuuu

CCPR1H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

2423 2523 4423 4523 --00 0000 --00 0000 --uu uuuu

CCPR2H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON 2423 2523 4423 4523 --00 0000 --00 0000 --uu uuuu

BAUDCON 2423 2523 4423 4523 01-0 0-00 01-0 0-00 --uu uuuu

ECCP1DEL 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

ECCP1AS 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

2423 2523 4423 4523 0000 00-- 0000 00-- uuuu uu--

CVRCON 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

CMCON 2423 2523 4423 4523 0000 0111 0000 0111 uuuu uuuu

TMR3H 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

T3CON 2423 2523 4423 4523 0000 0000 uuuu uuuu uuuu uuuu

SPBRGH 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

SPBRG 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

RCREG 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TXREG 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

TXSTA 2423 2523 4423 4523 0000 0010 0000 0010 uuuu uuuu

RCSTA 2423 2523 4423 4523 0000 000x 0000 000x uuuu uuuu

EEADR 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

EEDATA 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

EECON2 2423 2523 4423 4523 0000 0000 0000 0000 0000 0000

EECON1 2423 2523 4423 4523 xx-0 x000 uu-0 u000 uu-0 u000

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

PIC18F2423/2523/4423/4523

IPR2 2423 2523 4423 4523 11-1 1111 11-1 1111 uu-u uuuu

PIR2 2423 2523 4423 4523 00-0 0000 00-0 0000 uu-u uuuu(1)

PIE2 2423 2523 4423 4523 00-0 0000 00-0 0000 uu-u uuuu

IPR1 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

2423 2523 4423 4523 -111 1111 -111 1111 -uuu uuuu

PIR1 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu(1)

2423 2523 4423 4523 -000 0000 -000 0000 -uuu uuuu(1)

PIE1 2423 2523 4423 4523 0000 0000 0000 0000 uuuu uuuu

2423 2523 4423 4523 -000 0000 -000 0000 -uuu uuuu

OSCTUNE 2423 2523 4423 4523 0q-0 0000 00-0 0000 uu-u uuuu

TRISE 2423 2523 4423 4523 0000 -111 0000 -111 uuuu -uuu

TRISD 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

TRISC 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

TRISB 2423 2523 4423 4523 1111 1111 1111 1111 uuuu uuuu

TRISA(5) 2423 2523 4423 4523 1111 1111(5) 1111 1111(5) uuuu uuuu(5)

LATE 2423 2523 4423 4523 ---- -xxx ---- -uuu ---- -uuu

LATD 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

LATC 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

LATB 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

LATA(5) 2423 2523 4423 4523 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)

PORTE 2423 2523 4423 4523 ---- xxxx ---- uuuu ---- uuuu

PORTD 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PORTB 2423 2523 4423 4523 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA(5) 2423 2523 4423 4523 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5)

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector

(0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with

the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled

as PORTA pins, they are disabled and read ‘0’.

PIC18F2423/2523/4423/4523

5.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 Enhanced

microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard arc hitecture devices, the da ta and progra m

memories use separate busses; this allows for concur-

rent access of the two memory spaces. The data

EEPROM, for practical purposes, can be regarded as

a peripheral device, since it is ad dressed and accessed

through a set of control registers.

Additional detailed information on the operation of the

Flash program memory is provided in Section 6.0

“Flash Program Memory”. Data EEPROM is

discussed separately in Section 7.0 “Data EEPROM

Memory”.

5.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program

counter, which is capable of addressing a 2-Mbyte

progra m memory sp ace. Acces sing a lo cation b etween

the upper boundary of the physically implemented

memory and the 2-Mbyte address will return all ‘0’s ( a

NOP instr ucti on).

The PIC18F2423 and PIC18F4423 each have

16 Kbytes of Flash memory and can store up to 8,192

single-word instructions. The PIC18F2523 and

PIC18F4523 each have 32 Kbytes of Flash memory

and can store up to 16,384 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset

vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

The program memory map for PIC18LF2423/2523/

4423/4523 devices is show n in Figure 5-1.

FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR

PIC18LF24 23/2 523 /4423/4523 DEV ICE S

PC<20:0>

Stack Level 1

•

S tack Level 31

Reset Vector

Low Priority Interrupt Vect or

•

CALL,RCALL,RETURN

RETFIE,RETLW

0000h

0018h

On-Chip

Program Memory

High Priority Interrupt Vector 0008h

User Memory Space

1FFFFFh

4000h

3FFFh

Read ‘0’

200000h

PIC18FX423

PIC18FX523

8000h

7FFFh

On-Chip

Program Memory

Read ‘0’

PIC18F2423/2523/4423/4523

5.1.1 PROGRAM COUNTER

The Progra m Counter (PC) s pecifies the address of the

instruction to fetch for execution. The PC is 21 bits wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and wr itable. Th e high byt e, or PCH regi ster, contains

the PC<1 5:8> bits; it is not directly re adable or writ able.

Update s to the PCH register are performe d through the

PCLATH register. The upper byte is called PCU. This

directly readable or writable. Updates to the PCU

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are tran sferred to PCL ATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 5.1.4.1 “Computed

GOTO”).

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit of PCL is fixed to

a value of ‘0’. The PC increments by 2 to address

sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

5.1.2 RETURN ADDRESS STACK

The Return Address Stack allows any combination of

up to 31 program calls and interrupts to occur. The PC

is pushed onto the stack when a CALL or RCALL

instruction is executed or an interrupt is Acknowle dged.

The PC value is pulled off the stack on a RETURN,

RETLW or a RETFIE instruction. PCLATU and PCLATH

are not affected by any of the RETURN or CALL

instructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data sp ace. The Stac k Pointer

is readable and writable and the address on the top of

the stack is readable and writable through the Top-of-

Stack Special Function Registers. Data can also be

pushed to, or popped from the stack, using these

registers.

A CALL type inst ruct ion cause s a pus h onto t he stac k.

The Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

following the CALL). A RETURN type ins truc ti on c au se s

a pop from the stack. The contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; thi s

is only a Res et v alu e. Status bit s in dic ate if th e s t ac k i s

full or has overflowed or has underflowed.

5.1.2.1 Top-of-Stack Access

Only the top of the Return Address Stack (TOS) is

readable and writable. A set of three registers,

TOSU:T OSH:T OSL, hold the content s of the st ack loca-

tion pointed to by the STKP TR register (Figure 5-2). This

allows users to implement a s oftware stack if nec essary.

After a CALL, RCALL or interrupt, the software can read

the pushed value by reading the TOSU:TOSH:TOSL

registers. These values can be placed on a use r defined

software stack. At return time, the software can return

these values to T OSU:T O SH:T O SL and do a return.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

00011

001A34h

11111

11110

11101

00010

00001

00000

00010

Return Address Stack<20:0>

Top-of-Stack 000D58h

TOSLTOSHTOSU 34h1Ah00h STKPTR<4:0>

Top-of-St a ck Regis t ers S tack Pointer

PIC18F2423/2523/4423/4523

5.1.2.2 Return Stack Point er (STKPTR)

The STKP TR register (Regis ter 5-1) conta ins the S tack

Pointer value, the STKFUL (Stack Full) status bit and

the STKUNF (Stack Underflow) status bits. The value

of the Stack Pointer can be 0 through 31. The Stack

Pointer increments before values are pushed onto the

stack and decrements after values are popped off the

stack. On Reset, the Stack Pointer value will be zero.

The user may read and write the Stack Pointer value.

This feature can be used by a Real-Time Operating

System (RTOS) for return stack maintenance.

After t he PC is pus hed o nto the stac k 31 times (witho ut

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) Configuration bit. (Refer to

Section 23.1 “Configuration Bit s” for a descrip tion of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is clea red, the STKFUL bi t will be se t on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

When the stack has been popped enough times to

unload th e stack, the ne xt pop will return a value of zero

to the PC and sets the STKUNF bit, while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

5.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the

ability to pus h values on to the stack an d pul l values off

the stack without disturbing normal program execution

is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

T OSU, T OSH and T OS L can be m odifie d to plac e dat a

or a return address on the stack.

The PUSH instruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

The POP instruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not the same as a Reset, as the contents

of the SFRs are not affected.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Unde rflo w Fla g bit(1)

1 = Stack underflow occurred

0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

PIC18F2423/2523/4423/4523

5.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow

conditions are enabled by setting the STVREN bit in

Config ura tion Regi ster 4L. Whe n STVR EN i s s et, a ful l

or underflow will set the appropriate STKFUL or

STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow co ndition will set

the appropriate STKFUL or STKUNF bit but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by the user software or a Power-on Reset.

5.1.3 FAST REGISTER STACK

A fast register stack is provided for the STATUS,

WREG and BSR registers, to provide a “fast return”

option for i nterr upts. The st a ck for each register is onl y

one leve l deep and is neith er readable nor wri table. It is

loaded with the current value of the corresponding

inte rrupt source s will pu sh val ues i nto th e stack regis-

ters. The values in the registers are then loaded back

into their associated registers if the RETFIE, FAST

instruction is used to return from the interrupt.

If both low and high priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low priority interrupts. If a high priority interrupt occurs

while servicing a low priority interrupt, the stack register

values stored by the low priority interrupt will be

overwritten. In these cases, users must save the key

registers in software during a low priority interrupt.

If interrupt pri ority is not used, all interrupts may use the

fast register stack for returns from interrupt. If no inter-

rupts are used, the fast register stack can be used to

restore the STATUS, WREG and BSR registers at the

end of a subroutine call. To use the fast register stack

for a subroutine call, a CALL label,FAST instructi on

must be executed to save the STATUS, WREG and

BSR registers to the fast register stack. A

RETURN,FAST instruction is then executed to restore

these registers from the fast register stack.

Example 5-1 shows a source code example that uses

the fast register stack during a subroutine call and

return.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

5.1.4 LOOK-UP TABLES IN PROGRAM

MEMORY

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be implemented in two ways:

• Computed GOTO

• Table Reads

5.1.4.1 Computed GOTO

A comput ed GOTO i s a cc om pli sh ed b y a ddi ng a n offset

to the program counter. An example is shown in

Example 5-2.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nn instructions. The

W register is loa ded with an offset into the ta ble befo re

executi ng a c al l to tha t t a ble . Th e fi rst ins tru cti on o f th e

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW nn

instructions that returns the value ‘nn’ to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be mu ltiples of 2 (LSb = 0).

In this method, only one data byte may be stored in

each instruction location and room on the Return

Address Stack is required.

EXAMPLE 5-2: COMPUTED GOTO USING

AN OFFSET VALUE

5.1.4.2 Table Reads and Table Writes

A better method of storing data in program memory

allow s two bytes of dat a to be stored in each instruc tion

location.

Look-up table data may be stored two bytes per pro-

gram word by using table reads and writes. The Table

Pointer (TBLPTR) register specifies the byte address

and the Table Latch (TABLAT) register contains the

data that is read from or written to program memory.

Data is transferred to or from program memory one

byte at a time.

Table read and table write operations are discussed

further in Section 6.1 “Table Reads and Table

Writes”.

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

•

SUB1 •

•

RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE

ORG nn00h

TABLE ADDWF PCL

RETLW nnh

PIC18F2423/2523/4423/4523

5.2 PIC18 Instruction Cycle

5.2.1 CLOCKING SCHEME

The m icroc on t rol l er c l oc k i n pu t, w het h er fro m an i n te r-

nal or external source, is internally divided by four to

generate four non-overlapping quadrature clocks (Q1,

Q2, Q3 and Q4). Internally, the program counter is

incremented on every Q1; the instruction is fetched

from the program memory and latched into the instruc-

tion regis ter during Q4. The instructio n is decoded and

executed during the following Q1 through Q4. The

clocks and instruction execution flow are shown in

Figure 5-3.

5.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1

through Q4. The instruction fetch and execute are

pipelined in such a manner that a fetch takes one

instruction cycle, while the decode and execute take

another instruction cycle. However, due to the pipe-

lining, each instruction effectively executes in one

cycle. If an i nstruction causes the program c ounter to

change (e.g., GOTO), then two cycles are required to

complete the instruction (Example 5-3 ).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then de coded and executed during the Q2,

Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destin ation write).

FIGURE 5-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKO

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

All instruc tions are single cycle, exc ept for any program branche s. These tak e two cycles since the fetch in struction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

PIC18F2423/2523/4423/4523
DS39755B-page 58 Preliminary © 2007 Microchip Technology Inc.
5.2.3 INSTRUCTIONS IN PROGRAM 
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even add ress (LSb = 0). To maintain alignment
with i nstruction bo undaries , the PC i ncrement s in s teps
of 2 a nd the LSb wi ll always read  ‘0’ (see Section 5.1.1
“Program Counter”).
Figure 5-4 shows an exam ple  of h ow instruction word s
are stored in the program memory.
The CALL and GOTO instructions have the absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner . The
of fset value stored in a  branch instruction represent s the
number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details  of the instruction s et.
FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY
5.2.4 TWO -WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions:  CALL,  MOVFF,  GOTO and LSFR. In all
cases,  the se cond wor d of th e inst ruct ions al ways  has
‘1111’ as  its  four M ost Si gnifican t bit s; the  ot her 12  bit s
are literal data, usually a data memory address. 
The use o f ‘1111’ in the 4 MSbs of an instruction spec-
ifies a special form of NOP. If the instruc tion is  exec uted
in proper s eq uen ce – imme dia tel y after the first word –
the da ta in the s econd wor d is acce ssed and  used by
the instru ction sequence. If th e fi rst word is skipped for
some reason and the seco nd word is execute d by itself,
a NOP is executed instead. This is necessary for cases
when the two-word instruction is preceded by a condi-
tional instruction that changes the PC. Example 5-4
shows how this works.
EXAMPLE 5-4: TWO-WO RD INSTRUCTIONS
Word Address
LSB = 1LSB = 0↓
Program Memory
Byte Locations  →        000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See  Section 5.6 “PIC18 Instruction
Execution and the Extended Instruc-
tion Set” for information on two-word
instructions in  the extended  instruction  set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F2423/2523/4423/4523

5.3 Data Memory Organization

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4096 bytes of data

memory. The memory spac e is divided i nto as many a s

16 banks that contain 256 bytes each; PIC18LF2423/

2523/4423/4523 devices implement all 16 banks.

Figure 5-5 shows th e data me mory or ganizatio n for the

PIC18LF2423/2523/4423/4523 devices.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and per ipheral functio ns, while GP Rs are used for dat a

storage and scratchpad operations in the user’s

applic ation. Any read of an unim plemente d locat ion will

read as ‘0’s.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

subsection.

To ensure that commonly used registers (SFRs and

select GP Rs) c an b e ac cess ed i n a singl e c ycle, PIC1 8

devices im pl em ent an Ac cess Ba nk . Th is i s a 256-by te

memor y space that provid es fa st acc ess to SFRs and

the lower portion of GPR Bank 0 without using the

BSR. Section 5.3.2 “Access Bank” provides a

detailed description of the Access RAM.

5.3.1 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address doe s no t ne ed to be pr ovi ded for e ach read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit

low-order address and a 4-bit Bank Pointer.

Most in struct ions in th e PIC18 instruct ion se t make us e

of the Ban k Pointer , known as the Ba nk Select Reg ister

(BSR). This SFR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the

8 Least Significant bits. Only the four lower bits of the

BSR are implemented (BSR3:BSR0). The upper four

bit s are unused; the y will always read ‘0’ an d cannot be

written to. T he BSR can be load ed directly by using the

MOVLB instruction.

The value of the BSR indicates the bank in data

memory; the 8 bits in the instruction show the location

in the b an k a nd can be t hought of as an offset from th e

bank’s lower boundary. The relationship between the

BSR’s value and the bank division in data memory is

shown in Figure 5-7.

Since up to 16 regis ters may share the s ame low -order

address, the user must always be careful to ensure th at

the proper bank is selected before performing a data

read or write. For example, writing what should be

progra m data to an 8 - bi t ad dres s of F9h while the BSR

is 0Fh will end up resetting the program counter.

While any bank can be s elected, only th os e ba nk s that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory map in

Figure 5-5 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source a nd target reg isters. This i nstruction ig nores the

BSR comple tely when it ex ecutes. All othe r instruction s

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their targ et regis te rs.

Note: The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 5.5 “Data Memory and the

Extended Instruction Set” for more

information.

PIC18F2423/2523/4423/4523

FIGURE 5-5: DATA MEMORY MAP FOR PIC18LF2423/4423 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

080h

07Fh

F80h

FFFh

00h

7Fh

80h

FFh

Access B ank

When ‘a’ = 0:

The BSR is ignored and the

Access Bank is used.

The first 128 bytes are

general purpose RAM

(from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

When ‘a’ = 1:

The BSR spec ifies t he Ban k

used by the instruction.

F7Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unused

Read 00h

Unused

PIC18F2423/2523/4423/4523

FIGURE 5-6: DATA MEMORY MAP FOR PIC18LF2523/4523 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

080h

07Fh

F80h

FFFh

00h

7Fh

80h

FFh

Access B ank

When ‘a’ = 0:

The BSR is ignored and the

Access Bank is used.

The first 128 bytes are

general purpose RAM

(from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

When ‘a’ = 1:

The BSR spec ifies t he Ban k

used by the instruction.

F7Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unused

Read 00h

Unused

GPR

PIC18F2423/2523/4423/4523

FIGURE 5-7: USE OF THE BANK SELECT REGISTER

(DIRECT ADDRESSING POINTS TO 0x02FF)

5.3.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit

address allows users to address the entire range of

data mem ory, it al so mean s th at the user must a lways

ensure that the correct bank is selected. Otherwise,

data may be read from or written to the wrong location.

This can be disastrous if a GPR is the intended target

of an operation, but an SFR is written to instead.

Verifying and/or changing the BSR for each read or

write to data memory can become very inefficient.

To stream line access for the most comm only used dat a

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Access Bank consists of the first 128 bytes of

memory (00h-7Fh) in Bank 0 and the last 128 bytes of

memory (80 h-FFh) in Block 15 . The lower half is known

as the “Access RAM” and is composed of GPRs. This

upper half is also where the device’s SFRs are

mapped. These two areas are mapped contiguously in

the Access Bank and can be addressed in a linear

fashion by an 8-bit address (Figure 5-5).

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, the inst r uct i on

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored enti r el y.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle, without

updating the BSR first. For 8-bit addresses of 80h and

above, t his mean s that use rs can evaluate and opera te

on SFRs more efficiently. The Access RAM below 80h

is a goo d place for da ta values th at the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). This is di scus sed in mo re d etail

in Section 5.5.3 “Mapping the Access Bank in

Indexed Literal Offset Mode”.

5.3. 3 GENERAL PURPOSE REGISTER

FILE

PIC18 devices may have banked memory in the GPR

area. This is data RAM which is available for use by all

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow downwards towards the bot-

tom of the SFR area. GPRs are not initialized by a

Power-on Reset and are unchanged on all o ther Resets.

Note 1: The Access RAM bit of the instruction can be used t o f orce an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data Memory

Bank Select(2)

From Opcode(2)

0000

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

Bank 3

through

Bank 13

0010 11111 111

BSR(1)

PIC18F2423/2523/4423/4523

5.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of

data mem ory (F FFh) an d exte nd down ward to oc cupy

the top half of Bank 15 (F80h to FFFh). A list of these

registers is given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets: those asso-

ciated w ith t he “core ” devi ce fun ctiona lity (A LU, R eset s

and inter rupts) a nd those related to the peripheral func-

tions. The Reset and Interrupt registers are described

in their respective chapters, while the ALU’s STATUS

related to the operation of a peripheral feature are

describ ed in the ch apte r for that perip hera l.

The SFRs are typically distributed among the

periphera ls w ho se fun cti ons th ey c ontr ol. U nus ed SFR

locations are unimplemented and read as ‘0’s.

TABLE 5-1: SPECI AL FUNC TION REGISTER MAP FOR PIC1 8LF242 3/252 3/4 423 /4523 D EVICES

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1

FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1

FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1

FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2)

FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2)

FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2)

FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2)

FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL(3) F97h —(2)

FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3)

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3)

FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB

FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2)

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2)

FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2)

FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2)

FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3)

FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3)

FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA

FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2)

FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2)

FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2)

FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2)

FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE(3)

FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3)

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

3: This register is not available on 28-pin devices.

PIC18F2423/2523/4423/4523
DS39755B-page 64 Preliminary © 2007 Microchip Technology Inc.
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR Details 
on page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 54
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 49, 54
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 49, 54
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 49, 55
PCLATU — — — Hol d ing R egist er for  PC<20:16> ---0 0000 49, 54
PCLATH Holding Regist er for  PC<15:8> 0000 0000 49, 54
PCL PC Low Byte (PC<7:0>) 0000 0000 49, 54
TBLPTRU —— bit 21 Progr am Memory Table  Pointer Upper B yte (TBLPTR<20: 16>) --00 0000 49, 76
TBLPTRH Program Memory Table Pointer Hig h Byte (TB LPTR<15:8>) 0000 0000 49, 76
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 49, 76
TABLAT Program Memory Table Latch 0000 0000 49, 76
PRODH Product Register High Byte xxxx xxxx 49, 89
PRODL Product Register Low Byte xxxx xxxx 49, 89
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 93
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 49, 94
INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 49 , 95
INDF0 Uses contents of FSR0 to a ddress data memory  – value of FSR0 not chang ed (not a physical r egister) N/A 49, 69
POSTINC0 Uses contents of FSR0  to addres s data memory – val ue of FSR0 post-incremented (no t a physical register) N/A 49, 69
POSTDEC0 Uses co ntents of FSR0 to address data memory – val ue of FSR0 post-decreme nted (not a physical re gister) N/A 49, 69
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 69
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – 
value of FSR0 offset by W N/A 49, 69
FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 49, 69
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49, 69
WREG Work ing Regi st er xxxx xxxx 49
INDF1 Uses contents of FSR1 to a ddress data memory  – value of FSR1 not chang ed (not a physical r egister) N/A 49, 69
POSTINC1 Uses contents of FSR1  to addres s data memory – val ue of FSR1 post-incremented (no t a physical register) N/A 49, 69
POSTDEC1 Uses co ntents of FSR1 to address data memory – val ue of FSR1 post-decreme nted (not a physical re gister) N/A 49, 69
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 69
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – 
value of FSR1 offset by W N/A 49, 69
FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 50, 69
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 50, 69
BSR — — — — Bank Select Register ---- 0000 50, 59
INDF2 Uses contents of FSR2 to a ddress data memory  – value of FSR2 not chang ed (not a physical r egister) N/A 50, 69
POSTINC2 Uses contents of FSR2  to addres s data memory – val ue of FSR2 post-incremented (no t a physical register) N/A 50, 69
POSTDEC2 Uses co ntents of FSR2 to address data memory – val ue of FSR2 post-decreme nted (not a physical re gister) N/A 50, 69
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 69
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – 
value of FSR2 offset by W N/A 50, 69
FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 50, 69
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50, 69
STATUS — — —NOVZDCC---x xxxx 50, 67
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See 
Section 4.4 “Brown-out Reset (BOR)”.
2: These regi sters a nd/or bits are not implemented on 28-pin de vices and are read as ‘0’. Reset values are shown for 40/44-pin devices; 
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in 
INTOSC Modes”.
4: The RE3 bit is only available wh en Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is 
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. 
When disabled, these bits read as ‘0’.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 65
PIC18F2423/2523/4423/4523
TMR0H Timer0 Register High Byte 0000 0000 50, 125
TMR0L Timer0 Register Low Byte xxxx xxxx 50, 125
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 123
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 30, 50
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 245
WDTCON — — — — — — —SWDTEN--- ---0 50, 263
RCON IPEN SBOREN(1) —RITO PD POR BOR 0q-1 11q0 42, 48, 
102
TMR1H Timer1 Register High Byte xxxx xxxx 50, 131
TMR1L Timer1 Register Low Bytes xxxx xxxx 50, 131
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 127
TMR2 Timer2 Register 0000 0000 50, 134
PR2 Timer2 Period Register 1111 1111 50, 134
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 133
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 50, 169, 
170
SSPADD MSSP Address Register in I2C™ Slave Mode. MSSP Baud Rate Reload Regist er in I2C  Master Mode. 0000 0000 50, 170
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 50, 162, 
171
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 163, 
172
SSPCON2 GCEN ACKSTAT ACKDT/
ADMSK5 ACKEN/
ADMSK4 RCEN/
ADMSK3 PEN/
ADMSK2 RSEN/
ADMSK1 SEN 0000 0000 50, 173
ADRESH A/D Result Register High Byte xxxx xxxx 51, 236
ADRESL A/D Result Register Low Byte xxxx xxxx 51, 236
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 51, 227
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 51, 228
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 229
CCPR1 H Cap tur e/C o mpar e/P WM R egis t er 1 High Byte xxxx xxxx 51, 140
CCPR1 L Captur e/C o mpar e/P WM R egis t er 1 Low Byte xxxx xxxx 51, 140
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 51, 139, 
147
CCPR2 H Cap tur e/C o mpar e/P WM R egis t er 2 High Byte xxxx xxxx 51, 140
CCPR2 L Captur e/C o mpar e/P WM R egis t er 2 Low Byte xxxx xxxx 51, 140
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 51, 139
BAUDCON ABDOVF RCIDL —SCKPBRG16— WUE ABDEN 01-0 0-00 51, 208
ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 51, 157
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 51, 157
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51, 243
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 51, 237
TMR3H Timer3 Register High Byte xxxx xxxx 51, 137
TMR3L Timer3 Register Low Byte xxxx xxxx 51, 137
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51, 135
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR Details 
on page:
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See 
Section 4.4 “Brown-out Reset (BOR)”.
2: These regi sters a nd/or bits are not implemented on 28-pin de vices and are read as ‘0’. Reset values are shown for 40/44-pin devices; 
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in 
INTOSC Modes”.
4: The RE3 bit is only available wh en Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is 
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. 
When disabled, these bits read as ‘0’.

PIC18F2423/2523/4423/4523
DS39755B-page 66 Preliminary © 2007 Microchip Technology Inc.
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 51, 210
SPBRG EUSART Baud Rate  Generator Register Low Byte 0000 0000 51, 210
RCREG EUSART Receive Register 0000 0000 51, 217
TXREG EUSART Transmit Register 0000 0000 51, 215
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 206
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 207
EEADR EEPROM Address Register 0000 0000 51, 74, 83
EEDATA EEPROM Data Register 0000 0000 51, 74, 83
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 51, 74, 83
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 51, 75, 84
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 11-1 1111 52, 101
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 00-0 0000 52, 97
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 00-0 0000 52, 99
IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 100
PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 96
PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 98
OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 27, 52
TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 52, 118
TRISD(2) PORTD Data Direction Control Register 1111 1111 52, 114
TRISC PORTC Data Direction Control Register 1111 1111 52, 111
TRISB PORTB Data Direction Control Register 1111 1111 52, 108
TRISA TRISA7(5) TRISA6(5) PORTA Data Direction Control Register 1111 1111 52, 105
LATE(2) — — — — — PORTE Data Latch Register 
(Read and Write to Data Latch) ---- -xxx 52, 117
LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 114
LATC PORT C Data Latc h Regi ster (Read and Write to Data Latch) xxxx xxxx 52, 111
LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 108
LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 105
PORTE — — — —RE3
(4) RE2(2) RE1(2) RE0(2) ---- xxxx 52, 117
PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52, 114
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52, 111
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 108
PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 52, 105
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2423/2523/4423/4523) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR Details 
on page:
Legend: x = unknown , u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See 
Section 4.4 “Brown-out Reset (BOR)”.
2: These regi sters a nd/or bits are not implemented on 28-pin de vices and are read as ‘0’. Reset values are shown for 40/44-pin devices; 
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in 
INTOSC Modes”.
4: The RE3 bit is only available wh en Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is 
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. 
When disabled, these bits read as ‘0’.

PIC18F2423/2523/4423/4523

5.3.5 STATUS REGIST ER

The STATUS register, shown in Register 5-2, contains

the arithmetic status of the ALU. As with any other SFR,

it can be the operand for any instruction.

If the STATUS register is the des ti nati on for an instru c-

tion that affects the Z, DC, C, OV or N bits, the results

of the instruction are not written; instead, the STATUS

performed. Therefore, the result of an instruction with

the STATUS registe r as it s des tinati on may be d if fere nt

than intended. As an example, CLRF STATUS will set

the Z bit and leave the remaining Status bits

unchanged (‘000u u1uu’).

It is recommended that only BCF, BSF, SWAPF, MOVFF

and MOVWF instructions are used to alter the STATUS

C, DC, OV or N bits in the STATUS register.

For other i ns truc tio ns that do n ot affect Status bi t s , se e

the instruction set summaries in Table 24-2 and

Table 24-3.

Note: The C and DC bits operate as the borrow

and digit borrow bits, respectively, in

subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDC

(1) C(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1 = Result was neg ative

0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit

magnitude which causes the sign bit (bit 7 of the result) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/borrow bit(1)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/borrow bit(2)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow, the polarity is revers ed. A subtractio n is execute d by adding the 2’s c omplement of th e second

operand. For ro tate (RRF, RLF) instructio ns , thi s bi t is loaded w ith eit her b it 4 o r bit 3 of the sourc e re gis ter.

2: For borrow, the polarity is revers ed. A subtrac tion is exec uted by adding the 2’s c ompleme nt of the secon d

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the

source register.

PIC18F2423/2523/4423/4523
DS39755B-page 68 Preliminary © 2007 Microchip Technology Inc.
5.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the da ta m emory  sp ace can  be addr essed  in  several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
dependi ng on whic h operands are us ed and whe ther or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
•Direct
•Indirect
An additi onal addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.5.1 “Indexed
Addressing with Literal Offset”. 
5.4.1 INHEREN T AND LITERAL 
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that glo-
bally a ffects t he devi ce or  they  oper ate i mplic itly  on o ne
register. This addressing mode is known as Inherent
Addr es si ng . E xa m ple s  in c lu de  SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include  CALL and GOTO, which include a 20-bit
program memory address.
5.4.2 DIRECT ADDRESSING
Direct Addressing mode specifies all or part of the
source and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
In the co re PIC1 8 inst ruction  se t, bit-or iented  and by te-
oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register add ress in
one of  the banks of d ata RAM ( Section 5.3.3  “General
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction. 
The Acc es s RAM  b it  ‘a’  de term in es  ho w  the  a ddre ss i s
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with  the addres s to determ ine the com plete 12-b it
addr ess of t he regis ter.  When ‘a’  is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destin ation of the ope ration’ s result s is determine d
by the destination bit ‘d’. Wh en ‘d’ is ‘1’, the results are
stor ed  ba ck  in  t he s o ur c e re g is ter, over wr iti n g i ts or i gi -
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a  dest ination  that is  implicit  in the  inst ruction;  their
destination is either the ta rget register being operated
on or the W register.
5.4.3 INDIRECT ADDRESSING
Indirect  Addressing mode allows the user to access a
loc ation in data memory without giving a f ixed address
in the instruction. This is done by using File Select
Registers  (FSRs) as pointers t o the locations  to be read
or written  to. Since the FSR s are themsel ves loca ted in
RAM as Special Function Registers, they can also be
directly manipulated under program control. This
makes FSRs very useful in implementing data
structures, such as tables and arrays in data memory. 
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit au tomati c mani pulati on of the poi nter val ue wi th
auto-incrementing, auto-decrementing or offsetting
with a not her value .  Th is  al lo ws for efficient code, using
loops, such as the ex ample of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5: HOW TO CLEAR RAM 
(BANK 1) USING 
INDIRECT ADDRESSING   
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 ex tended  instruction set is
enabled. See Section 5.5 “Data Memory
and the Extended Instruction Set” for
more information.
LFSR FSR0, 100h ;   
NEXT  CLRF POSTINC0 ; Clear INDF 
; register then 
; inc pointer 
BTFSS FSR0H, 1 ; All done with
; Bank1? 
BRA NEXT ; NO, clear next 
CONTINUE ; YES, continue 

PIC18F2423/2523/4423/4523

5.4.3.1 FSR Regist er s and the INDF

Operand

At the core of Indirect Addressing are three sets of

registers: FSR0, FSR1 and FSR2. Each represents a

pair of 8-bit registers, FSRnH and FSRnL. The four

upper bits of the FSRnH register are not used so each

FSR pair hol ds a 12 -bit valu e. Thi s re prese nts a va lue

that can address the entire range of the data memory

in a linear fashion. The FSR register pairs, then, serve

as pointers to data memory locations.

Indirect Addressing is accomplished with a set of

Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers: they are

mapped in the SFR space but are not physically imple-

mented. Reading or writing to a part icular INDF register

actually accesses its corresponding FSR register pair.

A read from INDF1, for example, reads the data at the

address indicated by FSR1H :FSR1L. Instructions that

use the INDF registers as operands actually use the

contents of their co rrespon ding FS R as a poin ter to th e

instruction’s target. The INDF operand is just a

convenient way of using the pointer.

Because Indirect Addre ssing uses a fu ll 12-bit addr ess,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

5.4.3.2 FSR Regis ters and PO S TINC,

POSTDEC, PREINC and PLUSW

In additi on to the INDF o perand, each F SR register p air

also has four additional indirect operands. Like INDF,

these are “virtual” registers that cannot be indirectly

read or written to. Accessing these registers actually

accesses the associated FSR register pair, but also

performs a specific action on it stored value. They are:

• POSTDEC: accesses the FSR value, then

automatically decrements it by 1 afterwards

• POSTINC: accesse s the FSR valu e, then

automatically increments it by 1 afterwards

• PREINC: increments the FSR value by 1, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range o f -127 to 128) t o that of th e FSR and uses

the new value in the operation.

In this context, accessing an INDF register uses the

value in th e FSR registers with out changing them. Sim -

ilarly, accessing a PLUSW reg ister gives the FSR valu e

of fset by that in the W registe r; neither v alue is ac tuall y

changed in the operation. Accessing the other virtual

registers changes the value of the FSR registers.

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pair; that is, roll-

overs o f the FSRnL re giste r from FFh to 00h carry over

to the FSRnH register. On the other hand, results of

these operations do not change the value of any flags

in the STATUS register (e.g., Z, N, OV, etc.).

FIGURE 5-8: INDIRECT ADDRESSING

FSR1H:FSR1L

Data Memory

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

Bank 3

through

Bank 13

ADDWF, INDF1, 1

Using an instruction with one of the

indirect addressing register s as the

operand....

...uses the 12-bit address stored in

the FSR pair associated with that

...to determine the data memory

location to be used in that operation.

In this case, the FSR1 pair contains

ECCh. This means the contents of

location ECCh will be added to that

of the W register and stored back in

ECCh.

xxxx1110 11001100

PIC18F2423/2523/4423/4523

The PLUSW register can be used to implement a form

of Indexed Addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

5.4.3.3 Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs

or virtual registers represent special cases. For exam-

ple, usin g an FSR to point to on e of the virtual registers

will not result in successful operations. As a specific

case, assume that FSR0H:FSR0L contains FE7h, the

address of INDF1. Attempts to read the value of the

INDF1 using INDF0 as an operand will return 00h.

Attempt s to write to INDF1 using IN DF0 as th e operand

will result in a NOP.

On the other hand, u sing the virtu al reg isters to wr ite to

an F SR p air may n ot oc cur as plan ned. I n thes e ca ses,

the val ue will be w ritten to the FSR p ai r bu t withou t any

incrementing or decrementing. Thus, writing to INDF2

or POSTDEC2 will write the same value to the

FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses Indirect Addressing.

Similarly, operations by Indirect Addressing are gener-

ally pe rmitted on all other SFRs . Users sh ould exerc ise

the appropriate caution that they do not inadvertently

change settings that might affect the operation of the

device.

5.5 Data Memory and the Extended

Instructi on Set

Enabling the PIC18 extended instruction set (XINST

Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifi-

cally, the use of the Access Bank for many of the core

PIC18 instructions is different; this is due to the

introduction of a new addressing mode for the data

memor y space.

What doe s not chan ge is ju st as im po rtant. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect Addressing

with FSR0 and FSR1 also remain unchanged.

5.5.1 INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of Indirect Addressing using the FSR2

conditi ons, instruct ions that use th e Access Ban k – that

is, most bit-oriented and byte-oriented instructions –

can invoke a form of Indexed Addressing using an

of fset spe cified in the instru ction. Thi s speci al addr ess-

ing mode is known as Indexed Addressing with Literal

Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0) and

• The file ad dres s argument is le ss th an or equal to

5Fh.

Under these conditions, the file address of the instruc-

tion is not interpreted as the lower byte of an address

(used with th e BSR in Direct Addres sing), or as an 8-bit

address in the Access Bank. Instead, the value is

interpreted as an offset value to an Address Pointer,

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

5.5.2 INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use Direct

Addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set.

Instruct ions that only use Inherent or Literal Addressing

modes are una ffected.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they do not use the Access Bank

(Access RAM bit is ‘1’), or inc lud e a fi le ad dres s of 60h

or above. Instructions meeting these criteria will

continu e to exec ute as before . A comp aris on of the di f-

ferent possible addressing modes when the extended

instruction set is enabled in shown in Figure 5-9.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 24.2.1

“Extended Instruction Syntax”.

PIC18F2423/2523/4423/4523

FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When ‘a’ = 0 and f ≥ 60h:

The instruction executes in

Direct Forced mode. ‘f’ is inter-

preted as a location in the

Access RAM between 060h

and 0FFh. Th is is th e sam e as

locations 060h to 07Fh

(Bank 0) and F80h to FFFh

(Bank 15) of data memory.

Locations below 60h are not

available in this addressing

mode.

When ‘a’ = 0 and f ≤ 5Fh:

The instruction executes in

Indexed Literal Offset mode. ‘f’

is interpre ted as an offset to the

address value in FSR2. The

two are added together to

obtain the address of the target

address can be anywhere in

the data memory space.

Note that in this mode, the

correct syn tax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

When ‘a’ = 1 (all values of f):

The instruction executes in

Direct mode (also known as

Direct Long mode). ‘f’ is inter-

preted as a location in one of

the 16 banks of the data

memory space. The bank is

design ated by the Bank Sel ect

can be in any implemented

bank in the data memory

space.

000h

060h

100h

F00h

F80h

FFFh

Valid range

00h

60h

80h

FFh

Data Memory

Access RAM

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

000h

080h

100h

F00h

F80h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

FSR2H FSR2L

ffffffff001001da

000h

080h

100h

F00h

F80h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

for ‘f’

BSR

00000000

080h

PIC18F2423/2523/4423/4523

5.5.3 MAP PING THE ACCESS BANK IN

INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode

ef fectively chan ges how the first 96 locat ions of Access

RAM (0 0h to 5Fh ) are m ap ped . R at her tha n c on t ai nin g

just the content s of the bottom ha lf of Bank 0, this mode

maps the contents from Bank 0 and a user-defined

“window” that can be located anywhere in the data

memory space. The value of FSR2 establishes the

lower boundary of the addresses mapped into the

window, while the upper boundary is defined by FSR2

plus 95 (5Fh). Addresses in the Access RAM above

5Fh are mapped as previously described (see

Section 5.3.2 “Access Bank”). An example of Access

Bank remapping in this addressing mode is shown in

Figure 5-10.

Remapping of the Access Bank applies only to opera-

tions u sing the I ndexed Lite ral Offs et mode. Ope rations

that use the BSR (Access RAM bit is ‘1’) will continue

to use Direct Addressing as before.

5.6 PIC18 Instruction Execution and

the Extended Instruction Set

Enabling the extended instruction set adds eight

additional commands to the existing PIC18 instruction

set. These instructions are executed as described in

Section 24.2 “Extended Instruction Set”.

FIGURE 5-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET

ADDRESSING

Data Memory

000h

100h

200h

F80h

F00h

FFFh

Bank 1

Bank 15

Bank 2

through

Bank 14

SFRs

05Fh

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region

from the FSR2 Pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

Locations in Bank 0 from

060h to 07Fh are mapped,

as usual, to the middle hal f

of the Access Bank.

Special Function Regis-

ters at F80h through FFFh

are mapped to 80h

through FFh, as usual.

Bank 0 addresses below

5Fh can still be addressed

by using the BSR.

Access Bank

00h

80h

FFh

7Fh

Bank 0

SFRs

Bank 1 “Window”

Bank 0

Window

Example Situation:

07Fh

120h

17Fh

5Fh

Bank 1

PIC18F2423/2523/4423/4523

6.0 FLASH PR OGRAM MEMORY

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 32 bytes at a time. Program memory is

erased in blocks of 64 bytes at a time. A bulk erase

operation may not be issued from user code.

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value wri tten to program memory does not n eed to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

6.1 Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table read operations retrieve data from program

memory and places it into the data RAM space.

Figure 6-1 shows the operation of a table read with

program memory and data RAM.

Table w ri te oper at ions s tore d ata fr om the data me mor y

space into holding registers in program memory. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 6.5 “W riting

to Flash Program Memory”. Figure 6-2 shows the

operation of a table write with program memory and data

RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block can

start and end at any byte address. If a ta ble write is being

used to write executable code into program memory,

program instructions will need to be word aligned.

FIGURE 6-1: TABLE READ OPER ATION

Table Pointer(1) Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer register points to a byte in program memory .

Program Memory

(TBLPTR)

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FIGURE 6-2: TABLE WRITE OPERATION

6.2 Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

6.2.1 EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 6-1) is the control

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

The EEPGD control bit determi nes if th e access will be

a program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

The CFGS control bit determines if the access will be

to the Co nfigur ation/Ca librati on regis ters or to pro gram

memory/data EEPROM memory. When set,

subsequent operations will operate on Configuration

registers regardless of EEPGD (see Section 23.0

“Special Features of th e CPU”). When clear , memory

selection access is determined by EEPGD.

The FREE bit, when set, will allow a program memory

erase operation. When FREE is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only wr ite s are enab led .

The WREN bit, when set, will allow setting the WR bit

and beginning a write operation. On power-up, the

WREN bit is clear. WREN must be set by code before

WR can be set. WREN remains set until cleared by

code.

The WRERR bit is set in hardware when the WR bit is

set, and cl eared when the int ernal pro gramming timer

expires an d the w rite op era t ion i s compl ete. If the w ri te

is interrupted for any reason, the WRERR bit remains

set.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

Table Pointer(1) Table Latch (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory

(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by

TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in

Section 6.5 “W r iting to Fla sh Program Mem or y ”.

Holding Registers

Program Memory

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset, or a write operation was

attempted improperly.

Note: The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be

cleared in software.

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R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR(1) WREN WR RD

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(clear ed by completion of erase oper ation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Cont rol bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

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6.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR sp ace. The Table Latch registe r is used to

hold 8-bit data during data transfers between program

memory and data RAM.

6.2.3 TBLPTR – TABLE POINTER

The Table Pointer (TBLPTR) register address es a by te

within the program memory . The TBLPTR is comprised

of three SFR regis ters: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

progra m memory sp ace. Th e 22nd b it allows acce ss to

the device ID, the user ID and the Configuration bits.

The Table Pointer register, TBLPTR, is used by the

TBLRD and TBLWT instru cti ons . These i ns truc tio ns ca n

update the TBLPTR in one of four ways based on the

table operation. These operations are shown in

Table 6-1. These ope rations on the TBLP TR only af fect

the low-orde r 21 bi ts.

6.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

into TABLAT.

When a TBLWT is executed, the five LSbs of the Table

Pointer register (TBLP TR<4:0>) determine which o f the

32 program memory holding registers is written to.

When the timed write to program memory begins (via

the WR bit), the 17 MSbs of the TBLPTR

(TBLPTR<21:5>) determine which program memory

block of 32 bytes is written to. For more detail, see

Section 6.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the

16 MSbs of the T able Pointer register (TBLPTR<21:6>)

point to the 64-byte block that wi ll be erased. The Leas t

Significant bits (TBLPTR<5:0>) are ignored.

Figure 6-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

Example Operation on Table Pointer

TBLRD*

TBLWT* TBLPTR is not modifi ed

TBLRD*+

TBLWT*+ TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*- TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+* TBLPTR is incremented before the read/write

21 16 15 87 0

TABLE ERASE – TBLPTR<21:6>

TABLE READ – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

TABLE WRITE – TBLPTR<21: 5>

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6.3 Reading the Flash Program

Memory

The TBLRD instruction is used to retrieve data from

program memory and places it into data RAM. Table

reads fro m program memory are pe rformed one byte at

a time.

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

The interna l program memory is typically org anized by

words. The Least Significan t bit of th e address selects

between the high and low bytes of the word. Figure 6-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY

EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD

(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD TABLAT

TBLPTR = xxxxx1

FETCH

Instruction Register

(IR) Read Register

TBLPTR = xxxxx0

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWF WORD_EVEN

TBLRD*+ ; read into TABLAT and increment

MOVFW TABLAT, W ; get data

MOVF WORD_ODD

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6.4 Erasing Flash Program Memory

The mi nimum eras e block is 32 words or 64 byte s. Only

through the use of an external programmer, or through

ICSP™ control, can larger blocks of program memory

be bulk erased. Word erase in the Flash array is not

supported.

When initiating an erase sequence from the micro-

controll er itsel f, a block of 64 by tes of program me mory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

The EECON1 regis te r com ma nds the era se operation.

The EEPGD bit must be set to point to the Flash pro-

gram memory. The WREN bit must be set to enable

write op erations. The FREE bit i s set to selec t an erase

operation.

For protec tio n, t he w ri te i ni tiat e s equ enc e f or EEC ON 2

must be used.

A long w rite i s nec essary for erasing th e inte rnal Fl ash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

program ming timer.

6.4.1 FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

1. Load Table Pointer register with address of row

being erased.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable int errup ts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

8. Re-enable interrupts.

EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE_ROW

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Row Erase operation

BCF INTCON, GIE ; disable interrupts

Required MOVLW 55h

Sequence MOVWF EECON2 ; write 55h

MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

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6.5 Writing to Flash Program Memory

The minimum programming block is 16 words or

32 bytes. Word or byte programming is not supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are 32 holding registers used by the table writes for

programming.

Since the Table Latch (TABLAT) is only a single byte, the

TBLWT instruction may ne ed to be ex ecuted 32 times for

each programming operation. All of the table write

operations will essentially be short writes because only

the holding registers are written. At the end of updating

the 32 holding registers, the EECON1 register must be

written to in order to start the programming operation

with a long write.

The long write is necessary for programming the inter-

nal F lash. Inst ruction e xecutio n is halt ed while in a lon g

write cycle. The long write will be terminated by the

internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY

6.5.1 FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

1. Read 64 bytes int o RAM .

2. Update data values in RAM as necessary.

3. Load Table Pointer register with address being

erased.

4. Execute the row erase procedure.

5. Load Table Pointer register with address of first

byte being written.

6. Decrement Table Pointer.

7. Write the 32 by tes in to the hold ing reg isters with

pre-increment.

8. Set the EECON 1 register for the wri te operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

9. Disable int errup ts.

10. Write 55h to EECON2.

11. Write 0AAh to EECON2.

12. Set the WR bit. This will begin the w rite cy cl e.

13. The CPU will st all fo r duration of the write (a bout

2 ms using internal timer).

14. Re-enable interrupts.

15. Repeat from step 6 for the remaining 32 bytes.

16. Verify the memory (table read).

This procedure will require about 6 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 6-3.

Note: The default value of the holding registers on

device Resets and after write operations is

FFh. A write of FFh to a holding register

does not modi fy th at byt e. T his mea ns th at

individual bytes of program memory may be

modified, provided that the change does not

attemp t to cha nge an y bit f rom a ‘0’ to a ‘1’.

When modifying individual bytes, it is not

necessary to load all 32 holding registers

before ex ec u t in g a writ e o pe rat ion.

TABLAT

TBLPTR = xxxx1FTBLPTR = xxxxx1TBLPTR = xxxxx0

Write Register

TBLP TR = xxxxx2

Program Memory

Holding Register H olding Register Holding Register Holding Register

88 8 8

Note: Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the 32 bytes in

the holding regist er.

PIC18F2423/2523/4423/4523

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW D’64’ ; number of bytes in erase block

MOVWF COUNTER

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW ; 6 LSB = '0'

MOVWF TBLPTRL

READ_BLOCK

TBLRD*+ ; read into TABLAT, and inc

MOVF TABLAT, W ; get data

MOVWF POSTINC0 ; store data

DECFSZ COUNTER, F ; done?

BRA READ_BLOCK ; repeat

MODIFY_WORD

MOVLW DATA_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW DATA_ADDR_LOW

MOVWF FSR0L

MOVLW NEW_DATA_LOW ; update buffer word

MOVWF POSTINC0

MOVLW NEW_DATA_HIGH

MOVWF INDF0

ERASE_BLOCK

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Row Erase operation

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Req MOVWF EECON2 ; write 55h

Seq MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

TBLRD*- ; dummy read - decrement pointer

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

WRITE_BUFFER_BACK1 ; write first 32 bytes to Flash

MOVLW D’32’ ; number of bytes in holding register

MOVWF COUNTER

WRITE_BYTE_TO_HREGS1

MOVFF POSTINC0,WREG ; get low byte of buffer data

MOVWF TABLAT ; present data to table latch

TBLWT+* ; short write to holding

; register using pre-increment

DECFSZ COUNTER ; loop until buffers are full

BRA WRITE_BYTE_TO_HREGS1

PIC18F2423/2523/4423/4523

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

6.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

6.5.3 UNEXPECTED TERMINATION OF

WRITE OP ERATION

If a wri te is term in ate d by an u npl an ned ev en t, s uc h a s

loss of power or an unexpected Reset, the memory

locatio n jus t progra mmed shou ld be verifi ed and repr o-

gramme d if needed. If t he write operatio n is interrupte d

by a MCLR Reset or a WDT Time-out Reset during

normal operation, the user can check the WRERR bit

and rewrite the location(s) as needed.

6.5.4 PROTECTION AGAINST

SPURIOUS WRITES

To protect against unintended and spurious writes to

Flash program memory, the write initiate sequence

must be followed. In Example 6-3, the “Required

Sequence” acts to protect memory from unintended

writes by requiring this very specific sequence of five

instructions. This sequence must be executed exactly

as shown or the write will not occur.

6.6 Flash Program Operation During

Code Protection

Additional protection may be implemented using the

code protection features described in Section 23.5

“Program Verification and Code Protection”.

PROGRAM_MEMORY1

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Req MOVWF EECON2 ; write 55h

Seq MOVLW 0Aah

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start program (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

BCF EECON1, WREN ; disable write to memory

WRITE_BUFFER_BACK2 ; write remaining 32 bytes to Flash

MOVLW D’32’ ; number of bytes in holding register

MOVWF COUNTER

WRITE_BYTE_TO_HREGS2

MOVFF POSTINC0, WREG ; get low byte of buffer data

MOVWF TABLAT ; present data to table latch

TBLWT+* ; short write to holding

; register using pre-increment

DECFSZ COUNTER, F ; loop until buffers are full

BRA WRITE_BYTE_TO_HREGS2

PROGRAM_MEMORY2

BSF EECON1, EEPGD ; point to Flash program memory

BCF EECON1, CFGS ; access Flash program memory

BSF EECON1, WREN ; enable write to memory

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Req MOVWF EECON2 ; write 55h

Seq MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start program (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

BCF EECON1, WREN ; disable write to memory

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DS39755B-page 82 Preliminary © 2007 Microchip Technology Inc.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY 
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values on 
page
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 49
TABLAT Program Memory Table Latch 49
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
EECON2 EEPROM Control Register 2 (not a physical register) 51
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 51
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

PIC18F2423/2523/4423/4523

7.0 DATA EEPROM MEMORY

The data EEPROM i s a nonvolatil e memory array, sep-

arate from the data RAM and program memory, that is

used for long-term storage of program data. It is not

directly mapped in either the register file or program

memory space but is indirectly addressed through the

Special Function Registers (SFRs). The EEPROM is

readable and writ able durin g normal ope ration over the

entire VDD range.

Five SFRs are used to read and write to the data

EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR

The data EEPROM allows byte read and write. When

interfacing to the data memory block, EEDATA holds

the 8-bit data for read/write and the EEADR register

holds the address of the EEPROM location being

accessed.

The EEPROM data memory is rated for high erase/write

cycle endurance. A byte write automatically erases the

location and writes the new data (erase-before-write).

The write time is controlled by an on-chip timer; it will

vary with voltage and temperature as well as from chip

to chip. Please refer to parameter D122 (Table 26-1 in

Section 26.0 “Electrical Characteristics”) for exact

limits.

7.1 EEADR Register

The EEADR register is used to address the data

EEPROM for read and write operations. The 8-bit

range of the register can address a memory range of

256 bytes (00h to FFh).

7.2 EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two

registers which control access to the program memory

and are used in a similar manner for the data

EEPROM.

The EECON1 register (Register 7-1) is the control

bit EEPGD det erm ine s if the acce ss wi ll be to program

Flash or data EEPROM memory. When clear, opera-

tions will access the data EEPROM memory. When set,

program Flash memory is accessed.

Control bit, CFGS, determines if the access will be to

the Configuration registers or to program Flash

memory/data EEPROM memory. When set, sub-

sequent operations access Configuration registers.

When CFGS is clear, the EEPGD bit selects either

program Flash or data EEPROM memory.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. The WRERR bit i s

set in hardware when the WR bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

can be set but not cleared in software. It is only cleare d

in hardware at the completion of the write operation.

Control bits, RD and WR, start read and erase/write

operat ions, respec tively . These bi ts are set by fi rmware

and cleared by hardware at the completion of the

operation.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 6.1 “Table Reads

and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is

used exclusively in the memory write and erase

sequences. Reading EECON2 will read all ‘0’s.

Note: During normal operation, the WRERR

may read as ‘1’. This can indicate that a

write operation was prematurely termi-

nated by a Reset, or a write operation was

attempted improperly.

Note: The EEIF interrupt flag bit (PIR2<4 >) is set

when the write is complete. It must be

cleared in software.

PIC18F2423/2523/4423/4523

R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD CFGS — FREE WRERR(1) WREN WR RD

bit 7 bit 0

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access Flash program memory

0 = Access data EEPROM memory

bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit

1 = Access Configuration registers

0 = Access Flash program or data EEPROM memory

bit 5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(clear ed by completion of erase oper ation)

0 = Perform write only

bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program/Data EEPROM Write Enable bit

1 = Allows write cycles to Flash program/data EEPROM

0 = Inhibits write cycles to Flash program/data EEPROM

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Cont rol bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)

0 = Does not initiate an EEPROM read

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

PIC18F2423/2523/4423/4523

7.3 Reading the Data EEPROM

Memory

To read a d ata memory location, the user must write the

address to the EEADR register, clear the EEPGD

control bit (EECON1<7>) and then set control bit, RD

(EECON1<0>). The data is available on the very next

instruction cycle; therefore, the EEDATA register can

be read by the next instruction. EEDATA will hold this

value u ntil another re ad operation, or until it is w ritten to

by the user (during a write operation).

The basic process is shown in Example 7-1.

7.4 Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be writ ten to the EEAD R r egiste r and the da ta writ-

ten to the EEDATA register. The sequence in

Example 7-2 must be followed to initiate the write cycle.

The write will not begin if this sequence is not exactly

followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code exe-

cution (i.e., runaway programs). The WREN bit should

be kept clear at all times, except when updating the

EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, EECON1,

EEADR and EEDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. Both WR and WREN cannot be set with the same

instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Interrupt Flag

bit, EEIF, is set. The user may either enable this

interrupt or poll this bit. EEIF must be cleared by

software.

7.5 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

EXAMPLE 7-1: DATA EEPROM READ

EXAMPLE 7-2: DATA EEPROM WRITE

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ; Data Memory Address to read

BCF EECON1, EEPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, RD ; EEPROM Read

MOVF EEDATA, W ; W = EEDATA

MOVLW DATA_EE_ADDR ;

MOVWF EEADR ; Data Memory Address to write

MOVLW DATA_EE_DATA ;

MOVWF EEDATA ; Data Memory Value to write

BCF EECON1, EEPGD ; Point to DATA memory

BCF EECON1, CFGS ; Access EEPROM

BSF EECON1, WREN ; Enable writes

BCF INTCON, GIE ; Disable Interrupts

MOVLW 55h ;

Required MOVWF EECON2 ; Write 55h

Sequence MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BSF INTCON, GIE ; Enable Interrupts

; User code execution

BCF EECON1, WREN ; Disable writes on write complete (EEIF set)

PIC18F2423/2523/4423/4523

7.6 Operation During Code-Protect

Data EEPROM memory has its own code-protect bit s in

Configuration Words. External read and write

operations are disabled if code protection is enabled.

The mic rocontroll er its elf can bo th read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 23.0

“Special Features of the CPU” for additional

information.

7.7 Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPR OM memory. To protect against

spurious EEPROM writes, various mechanisms have

been implemented. On power-up, the WREN bit is

cleared. In addition, writes to the EEPROM are bloc ked

during the Power-up Timer period (TPWRT,

parameter 33).

The wri te in iti ate sequenc e an d the WR EN bi t tog eth er

help prevent an accidental write during brown-out,

power glitch or software malfunction.

7.8 Using the Data EEPROM

The data EEPROM is a high endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). Frequently changing values will typically be

updated more often than specification D124. If this is

not t he ca se, an arra y re fres h mus t be perf orm ed. For

this reason, variabl es that change infrequently (su ch as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE

Note: If data EEPROM is only used to store

const a nts and/or data that changes rarely,

an array refresh is likely not required. See

specification D124.

CLRF EEADR ; Start at address 0

BCF EECON1, CFGS ; Set for memory

BCF EECON1, EEPGD ; Set for Data EEPROM

BCF INTCON, GIE ; Disable interrupts

BSF EECON1, WREN ; Enable writes

Loop ; Loop to refresh array

BSF EECON1, RD ; Read current address

MOVLW 55h ;

MOVWF EECON2 ; Write 55h

MOVLW 0AAh ;

MOVWF EECON2 ; Write 0AAh

BSF EECON1, WR ; Set WR bit to begin write

BTFSC EECON1, WR ; Wait for write to complete

BRA $-2

INCFSZ EEADR, F ; Increment address

BRA LOOP ; Not zero, do it again

BCF EECON1, WREN ; Disable writes

BSF INTCON, GIE ; Enable interrupts

PIC18F2423/2523/4423/4523

TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

EEADR EEPROM Address Register 51

EEDATA EEPROM Data Register 51

EECON2 EEPROM Control Register 2 (not a physical register) 51

EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 51

IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52

PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52

PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

8.0 8 x 8 HARD WARE MULTIPLIER

8.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier

as part of the ALU. The multiplier performs an unsigned

operation and yields a 16-bit result that is stored in the

product register pair, PRODH:PRODL. The multiplier ’s

operation does not affect any flags in the STATUS

Making multiplication a hardware operation allows it to

be com pl eted i n a sing le ins truction cy cl e. This has th e

advantages of higher computational throughput and

reduced code size for multiplication algorithms and

allows the PIC18 devices to be used in many applica-

tions previously reserved for digital signal processors.

A comparison of various hardware and software

multiply operations, along with the savings in memory

and execution time, is shown in Table 8-1.

8.2 Operation

Example 8-1 shows the instruction s equence for an 8 x 8

unsigned multiplication. Only one instruction is required

when one of the arguments is already loaded in the

WREG regis ter.

Exampl e 8-2 shows the sequence t o do an 8 x 8 signed

multiplication. To account for the sign bits of the

argumen ts, e ach argu ment’ s Most Si gnificant bit (MSb)

is tested and the appropriate subtractions are done.

EXAMPLE 8- 1: 8 x 8 UNSIGNED

MULTIP L Y ROU TI NE

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVF ARG2, W

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

Routine Multiply Method Program

Memory

(Words)

Cycles

(Max)

Time

@ 32 MHz @ 10 MHz @ 4 MHz

8 x 8 unsigned Without hardware multiply 13 69 8.63 μs27.6 μs69 μs

Hardware multiply 1 1 125 ns 400 ns 1 μs

8 x 8 signed Without hardware multiply 33 91 11.4 μs36.4 μs91 μs

Hardware multiply 6 6 750 ns 2.4 μs6 μs

16 x 16 unsigned Without hardware multiply 21 242 30.3 μs96.8 μs 242 μs

Hardware multiply 28 28 3.5 μs 11.2 μs28 μs

16 x 16 signed Without hardware multiply 52 254 31.8 μs 102.6 μs 254 μs

Hardware multiply 35 40 5.0 μs16.0 μs40 μs

PIC18F2423/2523/4423/4523

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiplication. Equation 8-1 shows the

algorith m that is us ed. The 32-b it result is st ored in fo ur

registers (RES3:RES0).

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8- 3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers

(RES3:RES0). To account for the sign bits of the

arguments, the MSb for each argument pair is tested

and the appropriate subtractions are done.

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-4: 16 x 16 SIGNED

MU LTIPLY ROUTINE

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L) +

(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +

(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?

BRA SIGN_ARG1 ; no, check ARG1

MOVF ARG1L, W ;

SUBWF RES2 ;

MOVF ARG1H, W ;

SUBWFB RES3

;

SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3

;

CONT_CODE

PIC18F2423/2523/4423/4523

9.0 INTERRUPTS

The PIC18LF2423/2523/4423/4523 devices have mul-

tiple interrupt sources and an interrupt priority feature

that allows most interrupt sources to be assigned a

high priori ty level or a low priority level. The high priority

interr upt vector is at 0008h and the low priority interrupt

vector is at 0018h. High priority interrupt events will

interrupt any low priority interrupts that may be in

progress.

There are ten registers which are used to control

interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

It is recommended that the Microchip header files sup-

plied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compil er to automa tical ly ta ke care of the pla ceme nt of

these bits within the specified register.

In ge nera l, in terru pt so urces have three bits to cont rol

their operation. They are:

•Flag bit to indicate that an interrupt event

occurred

•Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

•Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globall y. Setting the G IEH bit (INTCON<7 >) enables all

interrupts that have the priority bit set (high priority).

Setting the GIEL bit (INTCON<6>) enables all inter-

rupts that have the priority bit cleared (low priority).

When the interrupt flag, enable bit and appropriate

global int errupt enab le bit are set, the interrup t will vec-

tor imm ediate ly to address 000 8h or 0018h, depen ding

on the priority bit setting. Individual interrupts can be

disabled through their corresponding enable bits.

When the IPEN bit is cleared (default state), the

interrupt priority feature is disabled and interrupts are

compatible with PIC® mid-range devices. In Compati-

bility mode, the interrupt priority bits for each source

have no effect. INTCON<6> is the PEIE bit, which

enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit, which enables/disables all

interrupt sources. All interrupts branch to address

0008h in Compatibility mode.

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. If the

IPEN bit is clear ed, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt. Low priority interrupts are not

processed while high priority interrupts are in progress.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address (0008h

or 0018h). Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bits must be

cleared in software before re-enabling interrupts to

avoid recursive inte rrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrup t routine and set s the GIE bit (GIEH or GI EL

if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or

the POR TB input chang e interrupt, the i nterrupt latenc y

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

PIC18F2423/2523/4423/4523

FIGURE 9-1: PIC18 INTERRUPT LOGIC

TMR0IE

GIE/GIEH

PEIE/GIEL

Wake-up if in

Interrupt to CPU

Vector to Location

0008h

INT2IF

INT2IE

INT2IP

INT1IF

INT1IE

INT1IP

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

IPEN

TMR0IF

TMR0IP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

PEIE/GIEL

Interrupt to CPU

Vector to Location

IPEN

0018h

SSPIF

SSPIE

SSPIP

SSPIF

SSPIE

SSPIP

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

Additional Peripheral Interrupts

ADIF

ADIE

ADIP

High Priority Interrupt Generation

Low Priority Interrupt Generation

RCIF

RCIE

RCIP

Additional Peripheral Interrupts

Idle or Sleep modes

GIE/GIEH

PIC18F2423/2523/4423/4523

9.1 INTCON Registers

The INTCON registers are readable and writable

registers, which contain various enable, priority and

flag bits.

Note: Interru pt flag bit s ar e set when an inter rupt

conditi on occurs , regardless of the sta te of

its corresponding enable bit or the global

enable b it. Thi s feat ure all ows for sof tware

polling.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt, otherwise, an interrupt

will occu r as soon as interrupt s are enab led.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts

When IPEN = 1:

1 = Enables all high priority interrupts

0 = Disables all interrupts

bit 6 PEIE/GIEL: Perip hera l Interru pt Enab le bit

When IPEN = 0:

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

When IPEN = 1:

1 = Enables all low priority peripheral interrupts

0 = Disables all low priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change inte rrup t

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 re gister has overflowe d (must be cleare d in software)

0 = TMR0 re gister did no t overfl ow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)

0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit(1)

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and

allow the bit to be cleared.

PIC18F2423/2523/4423/4523

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1

RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3 Unimplemented: Read as ‘0’

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

1 = High priority

0 = Low prior ity

bit 1 Unimplemented: Read as ‘0’

bit 0 RBIP: RB Port Change Interrupt Priority bit

1 = High priority

0 = Low prior ity

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global enable bit. This feature allows for software polling.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt,

otherwise, an interrupt will occur as soon as interrupts are enabled.

PIC18F2423/2523/4423/4523

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt

0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt

0 = Disables the INT1 external interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)

0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)

0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the global enable bit. This feature allows for software polling.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt,

otherwise, an interrupt will occur as soon as interrupts are enabled.

PIC18F2423/2523/4423/4523

9.2 PIR Registers

The PIR regi sters c onta in the ind ividual fl ag bit s for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Request Flag registers (PIR1 and PIR2).

Note 1: Interrupt flag bit s are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt and after servicing

that interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit 5 RCIF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)

0 = The EUSART receive buffer is empty

bit 4 TXIF: EUSART Transmit Inte rrupt Flag bit

1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0 = The EUSART transmit buffer is full

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode .

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register over flowed (must be cl eared in s oftware)

0 = TMR1 register did not overflow

Note 1: This bit is unimplemented on 28 -pin devices and will read as ‘0’.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = Device clock operating

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comp ara tor inpu t has not ch ang ed

bit 5 Unimplemented: Read as ‘0’

bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1 = The write operation is complete (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision occurred (must be cleared in software)

0 = No bus collision occurred

bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit

1 = A high/low-voltage condition occurred (direction determined by VDIRMAG bit, HLVDCON<7>)

0 = A high/low-voltage condition has not occurred

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register over flowed (must be cl eared in s oftware)

0 = TMR3 register did not overflow

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register captur e occurred (must be clea red in software)

0 = No TMR1 regist er capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

PIC18F2423/2523/4423/4523

9.3 PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Interrupt

Enable registers (PIE1 and PIE2). When IPEN = 0, the

PEIE bit must be set to enable any of these peripheral

interrupts.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write inte rrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disable s the A/D interru pt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt

0 = Disable s the EUSART receive interr upt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt

0 = Disable s the EUSART transmi t inter rupt

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrup t

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disable s the CCP 1 interru pt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: This bit is unimplemented on 28 -pin devices and will read as ‘0’.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enabled

0 = Dis abled

bit 5 Unimplemented: Read as ‘0’

bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit

1 = Enabled

0 =Disabled

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enabled

0 =Disabled

PIC18F2423/2523/4423/4523

9.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Interrupt

Priority registers (IPR1 and IPR2). Using the priority bits

requires that the Interrupt Priority Enable (IPEN) bit be

set.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)

1 = High priority

0 = Low priority

bit 6 ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 RCIP: EUSART Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 TXIP: EUSART Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2 CCP1IP: CCP1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

Note 1: This bit is unimplemented on 28 -pin devices and will read as ‘0’.

PIC18F2423/2523/4423/4523

R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 = High priority

0 = Low priority

bit 6 CMIP: Comparator Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 BCLIP: Bus Collision Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0 CCP2IP: CCP2 Interrupt Priority bit

1 = High priority

0 = Low priority

PIC18F2423/2523/4423/4523
DS39755B-page 102 Preliminary © 2007 Microchip Technology Inc.
9.5 RCON Register
The RCO N regist er conta ins flag b its whic h are used  to
deter mine the  caus e of the  last R eset or wa ke -up  from
Idle or  Slee p mo des . R CO N als o co ntains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
Register”.
              
REGISTER 9-10: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0
IPEN SBOREN —RITO PD POR BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit 
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1) 
For details of bit operation, see Register 4-1.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3 TO: Watchdog Time-out Flag bit 
For details of bit operation, see Register 4-1.
bit 2 PD: Power-Down Detection Flag bit 
For details of bit operation, see Register 4-1.
bit 1 POR: Power-on Reset Status bit(2) 
For details of bit operation, see Register 4-1.
bit 0 BOR: Brown-out Re set Status bit
For details of bit operation, see Register 4-1.
Note 1: If SBOREN  is  ena bl ed,  it s  Res et s t a te i s ‘ 1’;  oth erw is e, i t i s ‘0’. See Re gist e r 4-1 for additio na l in form at ion.
2: The actual Reset value of POR is determined by th e typ e of de vi ce R eset. See Registe r 4-1 for additiona l 
information.

PIC18F2423/2523/4423/4523

9.6 INTn Pin Interrupts

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 p ins are edge-triggered. If the corresponding

INTEDGx bit in the INTCON2 register is set (= 1), the

interrupt is triggered by a rising edge; if the bit is clear,

the trigger is on the falling edge. When a valid edge

appears on the RBx/INTx pin, the corresponding flag

bit, INTxIF, is set. This interrupt can be disabled by

clearin g th e c orre spo nd ing ena bl e bi t, INT xIE. Fla g bi t,

INTxIF, must be cleared in software in the Interrupt

Service Routine before re-enabling the interrupt.

All extern al interrupt s (INT0, INT1 an d INT2) can wake-

up the proces sor from Idle or Sleep mo des if bit INTx IE

was set prior to going into those modes. If the Global

Interrupt Enable bit, GIE, is set, the processor will

branch to the interrupt vector following wake-up.

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0. It is always a high

priority interrupt source.

9.7 TMR0 Interrupt

In 8-b it mod e (whic h is the de faul t), a n overfl ow in t he

TMR0 register (FFh →00h) will se t flag bit, TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt

can be enabled/disabled by setting/clearing enable bit,

TMR0IE (INTCON<5>). Interrupt priority for Timer0 is

determined by the value contained in the interrupt

priority bit, TMR0IP (INTCON2<2>). See Section 11.0

“Timer0 Module” for further details on the Timer0

module.

9.8 PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

9.9 Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 5.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 9-1 saves and restores the WREG,

STATUS and BSR re giste rs duri ng an Interru pt Servic e

Routine.

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank

MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere

MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF BSR_TEMP, BSR ; Restore BSR

MOVF W_TEMP, W ; Restore WREG

MOVFF STATUS_TEMP, STATUS ; Restore STATUS

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

10.0 I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. Some pins

of the I/O ports are multiplexed with an alternate

function from the peripheral features on the device. In

general, when a perip heral is ena bled, that pi n may not

be used as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (rea ds the level s on the pin s of the

device)

• LAT register (output latch)

The Dat a Latch (LAT register) is us eful for read-mo dify-

write operations on the value that the I/O pins are

driving.

A simplified model of a generic I/O port, without the

interf aces to other peripherals, is sho wn in Figure 10-1.

FIGURE 10-1: GENERIC I/O PORT

OPERATION

10.1 PORTA, TRISA and LATA Registers

PORTA is a 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding POR T A pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISA bit (= 0) will

make the correspon ding POR TA pin an out put (i.e., put

the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it, will write to the port latch.

The Data La tch (LA TA) register is also me mory mapped.

Read-modify-write operations on the LAT A register read

and write the latched output valu e for PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input and one of the comparator outputs to

become the RA4/T0CKI/C1OUT pin. Pins RA6 and

RA7 are multiplexed with the main oscillator pins; they

are enabled as oscillator or I/O pins by the selection of

the main oscillator in the Configuration register (see

Section 23.1 “Configuration Bits” for details). When

they are not used as port pins, RA6 and RA7 and their

associated TRIS and LAT bits are read as ‘0’.

The RA5/AN4/SS/HLVDIN/C2OUT pin is also used by

the MSSP module as a digital input. For this purpose,

the pin must be configured as digital in ADCON1, and

TRISA<5> must be set.

The other PORTA pins are multiplexed with analog

input s, the analog VREF+ and VREF- inputs, the compar-

ator voltage reference output and the HLVD analog

input. The operation of pins RA3:RA0 and RA5 as

analog inputs is selected by clearing or setting the

control bits in the ADCON1 register (A/D Control

Pins RA0 through RA5 may also be used as comparator

inputs or outputs by setting the appropriate bits in the

CMC ON re gist er. To use RA3:R A0 as di gital inputs , it is

also necessary to turn off the comparators.

The R A4 / T0 CK I /C 1O U T pi n is a S c hm it t Trigg e r inp ut .

All other PORTA pins have TTL input levels and full

CMOS out put driv ers .

The TR ISA register contro ls the direc tion of the PO RT A

pins, ev en w he n th ey a re being used as analog inp uts.

The user mu st ensure the bit s in the TRISA registe r are

maintained set when using them as analog inputs.

EXAMPLE 10-1: INITIALIZING PORTA

Data

Bus

WR LAT

WR TRIS

RD PORT

Data Latch

TRIS Latc h

RD TRIS

Input

Buffer

I/O pin(1)

RD LAT

or PORT

Note 1: I/O pins have diode protection to VDD and VSS.

Note: On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA4 is configured as a digital input.

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

CLRF LATA ; Alternate method

; to clear output

; data latches

MOVLW 07h ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVWF 07h ; Configure comparators

MOVWF CMCON ; for digital input

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

PIC18F2423/2523/4423/4523

TABLE 10-1: PORTA I/O SUMMARY

Pin Function TRIS

Setting I/O I/O

Type Description

RA0/AN0 RA0 0O DIG LATA <0> data output; not affected by analog input.

1I TTL PORTA<0> data input; disabled when analog input enabled.

AN0 1I ANA A/D input channel 0 and Comparator C1- input. Default input

configuration on POR; does not affect digital output.

RA1/AN1 RA1 0O DIG LATA <1> data output; not affected by analog input.

1I TTL PORTA<1> data input; disabled when analog input enabled.

AN1 1I ANA A/D input channel 1 and Comparator C2- input. Default input

configuration on POR; does not affect digital output.

RA2/AN2/

VREF-/CVREF RA2 0O DIG LATA<2> data output; not affected by analog input. Disabled when

CVREF output enabled.

1I TTL PORTA<2> data input. Disabled when analog functions enabled;

disabled when CVREF output enabled.

AN2 1I ANA A/D input channel 2 and Comparator C2+ input. Default input

configuration on POR; not affected by analog output.

VREF-1I ANA A/D and comparator voltage reference low input.

CVREF xO ANA Comparator voltage reference output. Enabling this feature disables

digital I/O.

RA3/AN3/VREF+RA30O DIG LATA <3> data output; not aff ected by analog input.

1I TTL PORTA<3> data input; disabled when analog input enabled.

AN3 1I ANA A/D input channel 3 and Comparator C1+ input. Default input

configuration on POR.

VREF+1I ANA A/D and comparator voltage reference high input.

RA4/T0CKI/C1OUT RA4 0O DIG LATA<4> data output.

1I ST PORTA<4> data input; default configuration on POR.

T0CKI 1I ST Timer0 clock input.

C1OUT 0O DIG Comparator 1 output; takes priority over port data.

RA5/AN4/SS/

HLVDIN/C2OUT RA5 0O DIG LATA <5> data output; not aff ected by analog input.

1I TTL PORTA<5> data input; disabled when analog input enabled.

AN4 1I ANA A/D input channel 4. Default configuration on POR.

SS 1I TTL Slave select input for MSSP (MSSP module).

HLVDIN 1I ANA High/Low-Voltage Detect external trip point input.

C2OUT 0O DIG Comparator 2 output; takes priority over port data.

OSC2/CLKO/RA6 OSC2 xO ANA Main oscillator feedback output conn ection (XT, HS and LP modes).

CLKO xO DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator

modes.

RA6 0O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.

1I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes

only.

OSC1/CLKI/RA7 OSC1 xI ANA Main oscillator input connection.

CLKI xI ANA Main clock input connection.

RA7 0O DIG LATA<7> data output. Disabled in external oscillator modes.

1I TTL PORTA<7> data input. Disabled in external oscillator modes.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt T rigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

PIC18F2423/2523/4423/4523

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52

LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 52

TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

Note 1: RA7:RA6 and their associated latch an d data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

PIC18F2423/2523/4423/4523

10.2 PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make th e corresp onding POR TB pi n an out put (i.e .,

put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

EXAMPLE 10-2: INITIALIZI NG PORTB

Each of th e POR TB pins has a we ak inte rnal pul l-up. A

single control bit can turn on pull-ups for all digital input

pins. This is performed by clearing bit, RBPU

(INTCON2<7>). The weak pull-up is automatically

turned off when the port pin is configured as a digital

output or an anal og inpu t. The pul l-up s are dis abled on

a Power-on Reset.

Four of the PORTB pins (RB7:RB4) have an interrupt-

on-chan ge feature, also known as a Ke yboard Interru pt

(KBI3:KBI0). Only pins conf igured as inputs can cause

this int errupt to occu r (i.e., any RB 7:RB4 pin co nfigured

as an output is excluded from the interrupt-on-change

comparison). The input pins (of RB7:RB4) are

comp ared with the old val ue latch ed on the la st read of

PORTB. The “mismatch” outputs of RB7:RB4 are

ORed together to generate the RB Port Change

Interrupt with Flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from the Sleep

mode, or any of the Idle modes. The user, in the

Interrupt Service Routine, can clear the interrupt in the

following manner:

a) Any read or write of PORTB (except with the

MOVFF (ANY), PORTB instruction).

b) Clear flag bit, RBIF.

A mismatc h condit ion wil l contin ue to set flag bit , RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

RB3 can be configured by the Configuration bit,

CCP2MX, as the alternate peripheral pin for the CCP2

module (CCP2MX = 0).

RB7:RB5 are used during device programming as

PGD:PGC:PGM pins, respectively. See Section 23.7

“In-Circuit Serial Programming”, Section 23.8 “In-

Circuit Debugger” and Section 23.9 “Single-Supp ly

ICSP Programming” for details.

RB2:RB0 offer external interrupt inputs (INT2:INT0,

respectively). See Section 9.6 “INTn Pin Interrupts”

for details.

RB0 offers an input (FL T0) for use when ECCP1 is using

an external Fault input to disable ECCP1 Faults. See

Section 16.4.7 “Enhanced PWM Auto-Shutdown” for

details.

Note: On a Power-on Reset, RB4:RB0 are

configu red as analog inp uts by defau lt and

read as ‘0’; RB7:RB5 are configured as

digital inputs.

By programming the Configuration bit,

PBADEN, RB4:RB0 will alternatively be

configured as digital inputs on POR.

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

CLRF LATB ; Alternate method

; to clear output

; data latches

MOVLW 0Fh ; Set RB<4:0> as

MOVWF ADCON1 ; digital I/O pins

; (required if config bit

; PBADEN is set)

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

PIC18F2423/2523/4423/4523

TABLE 10-3: PORTB I/O SUMMARY

Pin Function TRIS

Setting I/O I/O

Type Description

RB0/INT0/FLT0/

AN12 RB0 0O DIG LATB<0> data output; not affected by analog input.

1I TTL P ORTB<0> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

INT0 1I ST External interrupt 0 input.

FLT0 1I ST Enhanced PWM Fault input (ECCP1 module); enabled in software.

AN12 1I ANA A/D input channel 12.(1)

RB1/INT1/AN10 RB1 0O DIG LATB<1> data output; not affected by analog input.

1I TTL P ORTB<1> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

INT1 1I ST External Interrupt 1 input.

AN10 1I ANA A/D input channel 10.(1)

RB2/INT2/AN8 RB2 0O DIG LATB<2> data output; not affected by analog input.

1I TTL P ORTB<2> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

INT2 1I ST External interrupt 2 input.

AN8 1I ANA A/D input channel 8.(1)

RB3/AN9/CCP2 RB3 0O DIG LATB<3> data output; not affected by analog input.

1I TTL P ORTB<3> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

AN9 1I ANA A/D input channel 9.(1)

CCP2(2) 0O DIG CCP2 compare and PWM output.

1I ST CCP2 capture input

RB4/KBI0/AN11 RB4 0O DIG LATB<4> data output; not affected by analog input.

1I TTL P ORTB<4> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

KBI0 1I TTL Interrupt-on-pin change.

AN11 1I ANA A/D input channel 11.(1)

RB5/KBI1/PGM RB5 0O DIG LATB<5> data output.

1I TTL P ORTB<5> data input; weak pull-up when RBPU bit is cleared.

KBI1 1I TTL Interrupt-on-pin change.

PGM xI ST S ingle-Supply Programming mode entry (ICSP™ ). Enabled by LVP

Configuration bit; all other pin functions disabled.

RB6/KBI2/PGC RB6 0O DIG LATB<6> data output.

1I TTL P ORTB<6> data input; weak pull-up when RBPU bit is cleared.

KBI2 1I TTL Interrupt-on-pin change.

PGC xI ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3)

RB7/KBI3/PGD RB7 0O DIG LATB<7> data output.

1I TTL P ORTB<7> data input; weak pull-up when RBPU bit is cleared.

KBI3 1I TTL Interrupt-on-pin change.

PGD xO DIG Serial execution data output for ICSP and ICD operation.(3)

xI ST Serial execution data input for ICSP and ICD operation.(3)

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default

when PBADEN is set and digital inputs when PBADEN is cleared.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.

3: All other pin functions are disabled when ICSP or ICD are enabled.

PIC18F2423/2523/4423/4523

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52

LATB PORTB Data Latch Register (Read and Write to Data Latch) 52

TRISB PORTB Data Direction Control Register 52

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP49

INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 49

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 111
PIC18F2423/2523/4423/4523
10.3 PORTC, TRISC and LATC 
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will mak e the correspo nding PORT C pin an ou tput (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC. 
PORT C is multip lexed with s everal periphe ral function s
(Table 10-5). The pins have Schmitt Trigger input buff-
ers. RC1 is normally configured by Configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
RC7 and RC6 are used by the EUSART (Section 18.0
“Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)”). RC5, RC4 and
RC3 are used by the MSSP (Section 17.0 “Master
Synchronous Serial Port (MSSP) Module”). RC2 is
used by ECCP1 (Section 16.0 “Enhanced Capture/
Compare/PWM (ECCP) Module”). RC1 and RC0 are
used by the Timer1 oscillator (Section 12.3 “Timer1
Oscillator”). RC0 may also function as a clock input for
Timer1 and Timer3 (Section 12.0 “Timer1 Module”
and Section 14.0 “Timer3 Module”, respectively). RC1
may also be used by CCP2 (Section 15.0 “Capture/
Compare/PWM (CCP) Modules”) depending on the
Configuration bit, CCP2MX (Register 23-4,
CONFIG3H).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an i np ut . The  us er  sh ou ld re fe r to  th e co rre sp on di ng
periph eral se ctio n for addi tion al info rmati on.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current  contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3: INITIALIZING PORTC      
Note: On a Power-on Reset, these pins are
configured as digital inputs.
CLRF PORTC ;  Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ;  Value used to 
; initialize data                    
; direction
MOVWF TRISC ;  Set RC<3:0> as inputs
; RC<5:4> as outputs
;  RC<7:6> as inputs

PIC18F2423/2523/4423/4523

TABLE 10-5: PORTC I/O SUMMARY

Pin Function TRIS

Setting I/O I/O

Type Description

RC0/T1OSO/

T13CKI RC0 0O DIG LATC<0> data output.

1I ST PORTC<0> data input.

T1OSO xO ANA Ti mer1 oscillator output; enabled when Timer1 oscillator enabled.

Disables digital I/O.

T13CKI 1I ST Timer1/Timer3 counter input.

RC1/T1OSI/CCP2 RC1 0O DIG LATC<1> data output.

1I ST PORTC<1> data input.

T1OSI xI ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.

Disables digital I/O.

CCP2(1) 0O DIG CCP2 compare and PWM output; takes priority over port data.

1I ST CCP2 capt ure input.

RC2/CCP1/P1A RC2 0O DIG LATC<2> data output.

1I ST PORTC<2> data input.

CCP1 0O DIG ECCP1 compare or PWM output; takes priority over port data.

1I ST ECCP1 capture input.

P1A(2) 0O DIG ECCP1 Enhanced PWM output, channel A. May be configured for

tri-state during Enhanced PWM shutdown events. Takes priority over

port data.

RC3/SCK/SCL RC3 0O DIG LATC<3> data output.

1I ST PORTC<3> data input.

SCK 0O DIG SPI clock output (MSSP module); takes priority over port data.

1I ST SPI clock input (MSSP module).

SCL 0ODIGI

2C™ clock output (MSSP module); takes priority over port data.

1II

2C/SMB I2C clock input (MSSP module); input type depends on module setting.

RC4/SDI/SDA RC4 0O DIG LATC<4> data output.

1I ST PORTC<4> data input.

SDI 1I ST SPI data input (MSSP module).

SDA 1ODIGI

2C data output (MSSP module); takes priority over port data.

1II

2C/SMB I2C data input (MSSP module); input type depends on module setting.

RC5/SDO RC5 0O DIG LATC<5> data output.

1I ST PORTC<5> data input.

SDO 0O DIG S PI data output (MSSP module); takes priority over port data.

RC6/TX/CK RC6 0O DIG LATC<6> data output.

1I ST PORTC<6> data input.

TX 1O DIG Asynchronous serial transmit data output (EUSART module);

takes priority over port data. User must configure as output.

CK 1O DIG Synchronous serial clock outp ut (EUSART module); takes priority

over port data.

1I ST Sync hronous serial clock input (EU SART module).

RC7/RX/DT RC7 0O DIG LATC<7> data output.

1I ST PORTC<7> data input.

RX 1I ST Asynchronous serial receive data input (EUSART module).

DT 1O DIG Synchronous serial data output (EUSART module); takes priority over

port data.

1I ST Sync hronous serial data input (EUSART module). User must

configure as an input.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt T rigger input buffer; ANA = Analog level input/output;

I2C/SMB = I2C/S M Bus in put b uffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Default assignment for CCP2 when the CCP2MX Configurat ion bit is set. Alternate assignment is RB3.

2: Enhanced PWM output is available only on PIC18F4523 devices.

PIC18F2423/2523/4423/4523

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 52

LATC PORTC Data Latch Register (Read and Write to Data Latch) 52

TRISC PORTC Data Direction Control Register 52

PIC18F2423/2523/4423/4523

10.4 PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will mak e the correspo nding PORT D pin an ou tput (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

All pins on PORTD are implemented with Schmitt Trig-

ger input buffers. Each pin is individually configurable

as an input or output.

Three of the PORTD pins are multiplexed with outputs

P1B, P1C and P1D of the Enhanc ed CCP modu le. The

operation of these additional PWM output pins is

covered in greater detail in Section 16.0 “Enhanced

Capture/Compare/PWM (ECCP) Module”.

POR TD can also be confi gure d as an 8- bit w id e m ic ro-

processor port (Parallel Slave Port) by setting control

bit, PSPMODE (TRISE<4>). In this mode, the input

buffers are TTL. See Section 10.6 “Parallel Slave

Port” for additional information on the Parallel Slave

Port (PSP).

EXAMPLE 10-4: INITIALIZING PORTD

Note: PORTD is only available on 40/44-pin

devices.

Note: On a Power-on Reset, these pins are

configured as digital inputs.

Note: When the Enhanced PWM mode is used

with either dual or quad outputs, the PSP

functions of PORTD are automatically

disabled.

CLRF PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF LATD ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISD ; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

PIC18F2423/2523/4423/4523

TABLE 10-7: PORTD I/O SUMMARY(1)

Pin Function TRIS

Setting I/O I/O

Type Description

RD0/PSP0 RD0 0O DIG LATD<0> data output.

1I ST PORTD<0> data input.

PSP0 xO DIG PSP read data output (LATD<0>); takes priority over port data.

xI TTL PSP write data input.

RD1/PSP1 RD1 0O DIG LATD<1> data output.

1I ST PORTD<1> data input.

PSP1 xO DIG PSP read data output (LATD<1>); takes priority over port data.

xI TTL PSP write data input.

RD2/PSP2 RD2 0O DIG LATD<2> data output.

1I ST PORTD<2> data input.

PSP2 xO DIG PSP read data output (LATD<2>); takes priority over port data.

xI TTL PSP write data input.

RD3/PSP3 RD3 0O DIG LATD<3> data output.

1I ST PORTD<3> data input.

PSP3 xO DIG PSP read data output (LATD<3>); takes priority over port data.

xI TTL PSP write data input.

RD4/PSP4 RD4 0O DIG LATD<4> data output.

1I ST PORTD<4> data input.

PSP4 xO DIG PSP read data output (LATD<4>); takes priority over port data.

xI TTL PSP write data input.

RD5/PSP5/P1B RD5 0O DIG LATD<5> data output.

1I ST PORTD<5> data input.

PSP5 xO DIG PSP read data output (LATD<5>); takes priority over port data.

xI TTL PSP write data input.

P1B 0O DIG ECCP1 Enhanced PWM output, channel B; t akes priority over port and

PSP data. May be configured for tri-state during Enhanced PWM

shutdown events.

RD6/PSP6/P1C RD6 0O DIG LATD<6> data output.

1I ST PORTD<6> data input.

PSP6 xO DIG PSP read data output (LATD<6>); takes priority over port data.

xI TTL PSP write data input.

P1C 0O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and

PSP data. May be configured for tri-state during Enhanced PWM

shutdown events.

RD7/PSP7/P1D RD7 0O DIG LATD<7> data output.

1I ST PORTD<7> data input.

PSP7 xO DIG PSP read data output (LATD<7>); takes priority over port data.

xI TTL PSP write data input.

P1D 0O DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and

PSP data. May be configured for tri-state during Enhanced PWM

shutdown events.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care

(TRIS bit does not affect port direction or is overridden for this option).

Note 1: These registers and/or bits are not implemented on 28-pin devices.

PIC18F2423/2523/4423/4523

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52

LATD PORTD Data Latch Register (Read and Write to Data Latch) 52

TRISD PORTD Data Direction Control Register 52

TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52

CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.

Note 1: These registers and/or bits are not implemented on 28-pin devices.

PIC18F2423/2523/4423/4523

10.5 PORTE, TRISE and LATE

Registers

Depending on the particular PIC18LF2423/2523/4423/

4523 device selected, PORTE is implemented in two

different ways.

For 40/44-pin devices, PORTE is a 4-bit wide port.

Thre e pi n s (RE 0 /R D/AN5, RE1/WR/AN6 and RE2/CS/

AN7) are i ndi vi dually c on fig urab le as i npu t s or output s .

These pins have Schmitt Trigger input buffers. When

select ed as an analog input, these pins will read as ‘0’s.

The corresponding data direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an in put (i.e. , put th e c orres po ndi ng outp ut

driver in a high-impedance mode). Clearing a TRISE bit

(= 0) will m ake the corre sponding P ORTE pin an output

(i.e., pu t the co ntents o f the output latch on the selecte d

pin).

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

The upper four bits of the TRISE register also control

the operati on of the Parallel Slav e Port. Their operatio n

is explained in Register 10-1.

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

The fourth pin of PORTE (MCLR/VPP/RE3) is an input

only pin. Its operation is controlled by the MCLRE Con-

figuration bit. When selected as a port pin (MC LRE = 0),

it functions as a dig ital input only pin ; as such, it doe s not

have TRIS or LAT bits associated with its operation.

Otherwise, it functions as the device’s Master Clear

input. In either configuration, RE3 also functions as the

programming volt age input during programming.

EXAMPLE 10-5: INITIALIZING PORTE

10.5.1 PORTE IN 28-PIN DEVICES

For 28-pin devices, PORTE is only available when

Master Clear functionality is disabled (MCLRE = 0). In

these cases, PORTE is a single bit, input only port com-

prised of RE3 only. The pin operates as previously

described.

Note: On a Power-on Reset, RE2:RE0 are

configured as analog inputs.

Note: On a Pow er- on Re set, RE3 i s enab led as

a digital input only if Master Clear

functionality is disabled.

CLRF PORTE ; Initialize PORTE by

; clearing output

; data latches

CLRF LATE ; Alternate method

; to clear output

; data latches

MOVLW 0Ah ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 03h ; Value used to

; initialize data

; direction

MOVWF TRISE ; Set RE<0> as inputs

; RE<1> as outputs

; RE<2> as inputs

PIC18F2423/2523/4423/4523

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IBF: Input Buffer Full Status bit

1 = A word has been received and waiting to be read by the CPU

0 = No word has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software)

0 = No overflow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel Slave Port mode

0 = General purpose I/O mode

bit 3 Unimplemented: Read as ‘0’

bit 2 TRISE2: RE2 Direction Control bit

1 = Input

0 = Output

bit 1 TRISE1: RE1 Direction Control bit

1 = Input

0 = Output

bit 0 TRISE0: RE0 Direction Control bit

1 = Input

0 = Output

PIC18F2423/2523/4423/4523

TABLE 10-9: PORTE I/O SUMMARY

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Pin Function TRIS

Setting I/O I/O

Type Description

RE0/RD/AN5 RE0 0O DIG LATE<0> data output; not affected by analog input.

1I ST PORTE<0> data input; disabled when analog input enabled.

RD 1I TTL PSP read enable input (PSP enabled).

AN5 1I ANA A/D input channel 5; default input configuration on POR.

RE1/WR/AN6 RE1 0O DIG LATE<1> data output; not affected by analog input.

1I ST PORTE<1> data input; disabled when analog input enabled.

WR 1I TTL PSP write enable input (PSP enabled).

AN6 1I ANA A/D input channel 6; default input configuration on POR.

RE2/CS/AN7 RE2 0O DIG LATE<2> data output; not affected by analog input.

1I ST PORTE<2> data input; disabled when analog input enabled.

CS 1I TTL PSP write enable input (PSP enabled).

AN7 1I ANA A/D input channel 7; default input configuration on POR.

MCLR/VPP/RE3(1) MCLR — I ST External Master Clear input; enabled when MCLRE Configuration bit is

set.

VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always

available, regardless of pin mode.

RE3 —(2) I ST PORTE<3> data input; enabled when MCLRE Configuration bit is

clear.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin

devices.

2: RE3 does not have a corresponding TRIS bit to control data direction.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTE — — — —RE3

(1,2) RE2 RE1 RE0 52

LATE(2) — — — — — POR TE D at a Lat ch R egi ste r

(Read and Write to Data Latch) 52

TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52

ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are

implemented only when PORTE is implemented (i.e ., 40/44-pin devices).

PIC18F2423/2523/4423/4523

10.6 Parallel Slave Port

In addition to its function as a general I/O port, PORTD

can also operate as an 8-bit wide Parallel Slave Port

(PSP) or microprocessor port. PSP operation is con-

trolled by the 4 upper bits of the TRISE register

(Register 10-1). Setting control bit, PSPMODE

(TRISE<4>), enables PSP operation as long as the

Enhance d CCP module i s not o peratin g in D ual Outp ut

or Qu ad Ou tput PWM mode . In Slav e mod e, the p ort is

asynchronously readable and writable by the external

world.

The PSP can directly interface to an 8-bit micro-

processor data bus. The external microprocessor can

read or write the POR TD latch a s an 8-bit latc h. Setting

the control bit, PSPMODE, enables the PORTE I/O

pins to become control inputs for the microprocessor

port. When set, port p in RE0 is the RD inp ut, RE1 is the

WR input and RE2 is the CS (Chip Select) input. For

this functionality, the corresponding data direction bits

of the TRISE register (TRISE<2:0>) must be config-

ured as inputs (set). The A/D port Configuration bits,

PFCG3:PFCG0 (ADCON1<3:0>), must also be set to a

value in the range of ‘1010’ through ‘1111’.

A write to the PSP occurs when both the CS and WR

lines are first detected low and ends when either are

detecte d high. The PSPIF and IBF fla g bits are both set

when the write ends.

A read from t he PSP occurs when both the CS and R D

lines are first detected low. The data in PORTD is read

out and the O BF bit is c lear. If the user writes new da t a

to POR TD to set OBF, the data is im mediately rea d out;

however, the OBF bit is not set.

When either the CS or RD lines are detected high, the

PORT D pins return to the inpu t sta te and th e PSPIF bit

is set. Use r applications sho uld wait for PSPIF to b e set

before servicing the PSP; when this happens, the IBF

and OBF bits can be polled and the appropriate action

taken.

The timing for the control signals in Write and Read

modes is shown in Figure 10-3 and Figure 10-4,

respectively.

FIGURE 10-2: PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

Note: The Parallel Slave Port is only available on

40/44-pin devices.

Data Bus

WR LATD RDx pin

RD PORTD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1< 7>)

Read

Chip Select

Write

TTL

WR PORTD

RD LATD

Data Latch

Note: I/O pins have diode protection to VDD and VSS.

PORTE Pins

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 121
PIC18F2423/2523/4423/4523
FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS         
FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS         
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT     
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52
LATD PORTD Data Latch Register (Read and Write to Data Latch) 52
TRISD PORTD Data Direction Control Register 52
PORTE — — — — RE3 RE2 RE1 RE0 52
LATE — — — — — PORTE Data Latch Register
(Read and Write to Data Latch) 52
TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52
INTCON GIE/GIEH PEIE/GIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

11.0 T IMER0 MODULE

The T imer0 module incorporate s the follo wing features:

• Software selectable operation as a timer or

counter in both 8-bit or 16-bit modes

• Readable and writable registers

• Dedicated 8-bit, software programmable

prescaler

• Selectable clo ck so urce (internal or external)

• Edge select for external clock

• Interrupt-on-overflow

The T0CON register (Register 11-1) controls all

aspects of the module’s operation, including the

prescale selection. It is both readable and writable.

A simplified block diagram of the Timer0 module in 8-bit

mode is shown in Figure 11-1. Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0

0 = Stops Timer0

bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit

1 = Timer0 is configured as an 8-bit timer/counter

0 = Timer0 is configured as a 16-bit timer/counter

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transit ion on T0CKI pin

0 = Internal instr uction cycle clock (CLKO)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Timer0 Prescaler Assignment bit

1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0 = Timer0 prescaler is assigned. Timer0 clock in put comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits

111 = 1:256 Prescale value

110 = 1:128 Prescale value

101 = 1:64 Prescale value

100 = 1:32 Prescale value

011 = 1:16 Prescale value

010 = 1:8 Prescale value

001 = 1:4 Prescale value

000 = 1:2 Prescale value

PIC18F2423/2523/4423/4523

11.1 Timer0 Operation

Timer0 can operate as either a timer or a counter; the

mode is selected with the T0CS bit (T0CON<5>). In

Timer mode (T0CS = 0), the module increments on

every clock by default unless a dif ferent prescaler valu e

is selected (see Section 11.3 “Prescaler”). If the

TMR0 register is written to, the increment is inhibited

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 registe r.

The Counter mode is selected by setting the T0CS bit

(= 1). In this mode, Timer0 increments either on every

rising or fal ling edge of pi n RA4/T0CKI . The increme nt-

ing edge is determined by the Timer0 Source Edge

Select bit, T0SE (T0CON<4>); clearing this bit selects

the risi ng edge . Res trictio ns on the ext ernal c lock inp ut

are discussed below.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements to ensure

that the external clock can be synchronized with the

internal phase clock (TOSC). There is a delay between

synchronization and the onset of incrementing the

timer/counter.

11.2 Timer0 Reads and Writes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode; it is actually a buffered version of the real high

byte of Timer0 which is not directly readable nor writ-

able (refer to Figure 11-2). TMR0H is updated with the

contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

T imer 0 without havi ng to verify tha t the read of the hig h

and low byte were valid, due to a rollover between

successive reads of the high an d low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buf fer register . The high

byte is updated with the contents of TMR0H when a

write o ccurs to TMR0L. Th is allows all 16 bits o f T imer0

to be updated at once.

FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS2:T0PS0

Set

TMR0IF

on Overflow

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS2:T0PS0

Set

TMR0IF

on Overflow

TMR0

TMR0H

High Byte

Read TMR0L

Write TMR0L

PIC18F2423/2523/4423/4523

11.3 Prescaler

An 8-bi t counter i s availabl e as a presc aler for the T imer0

module. The prescaler is not directly readable or writable;

its value is set by the PSA and T0PS2:T0PS0 bits

(T0CON<3:0>) which determine the prescaler

assi gn ment and pre s ca le ra tio .

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When it is assigned, prescale values

from 1:2 through 1:256 in power-of-2 increments are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, etc.) clear the prescaler count.

11.3 .1 SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

11.4 Timer0 Inte rr u p t

The TMR0 interrupt is generated when the TMR0

from FFFFh to 0000h in 16-bit mode. This overflow sets

the TMR0IF flag bit. The interrupt can be masked by

clearing the TMR0IE bit (INTCON<5>). Before re-

enabling the interrupt, the TMR0IF bit must be cleared

in software by the Interrupt Service Routine.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Writing to TMR0 when the prescaler is

assign ed to Timer0 will clear th e pr escal er

count but will not change the prescaler

assignment.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

TMR0L Timer0 Register Low Byte 50

TMR0H Timer0 Register High Byte 50

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 50

TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52

Legend: Shaded cells are not used by Ti mer0.

Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

12.0 TIMER1 MODULE

The Timer1 timer/counter module incorporates these

features:

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR1H

and TMR1L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Reset on CCP Special Event Trigger

• Device clock status flag (T1RUN)

A simplified block diagram of the Timer1 module is

shown in Fi gure 12-1. A bloc k di agr am of the mod ule ’s

operatio n in Read /Wr ite mode is show n in Figure 12-2.

The module incorporates its own low-power oscillator

to provide an additional clocking option. The Timer1

oscillator ca n also be used a s a low-power clock source

for the microcontroller in power-managed operation.

Timer1 can also be used to provide Real-Time Clock

(RTC) functionality to applications with only a minimal

addition of external components and code overhead.

Timer1 is controlled through the T1CON Control

Oscillator Enable bit (T1OSCEN). Timer1 can be

enabled or disabled by setting or clearing control bit,

TMR1ON (T1CON<0>).

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer1 in one 16-bit operation

0 = Enables register read/write of Timer1 in two 8-bit operations

bit 6 T1RUN: Timer1 System Clock Status bit

1 = Dev ice clock is derived from Timer1 oscill ator

0 = Dev ice cl ock is derived from anothe r source

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Cloc k Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscill ator Enable bit

1 = Timer1 oscillator is enabled

0 = Timer1 oscillator is shut off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer 1

PIC18F2423/2523/4423/4523

12.1 Timer1 Operation

Timer1 can operate in one of these modes:

•Timer

• Synchrono us Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). When TMR1CS is cleared

(= 0), Timer1 increments on every internal instruction

cycle (Fosc/4). When the bit is set, Timer1 increments

on every rising edge of the Timer1 external clock input

(T13CKI) or the Timer1 oscillator, if enabled.

When Timer1 is enabled, the RC1/T1OSI and RC0/

T1OSO/T13CKI pins become inputs. This means the

values of TRISC<1:0> are ignored and the pins are

read as ‘0’.

FIGURE 12-1: TIMER1 BLOCK DIAGRAM

FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

Peripheral Cloc k

T1OSCEN(1)

FOSC/4

Internal

Clock

On/Off

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

TMR1ON

TMR1L Set

TMR1IF

on Overflow

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer1

Timer3 Clock Input and

SEC_mode System Clock

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

Peripheral Clock

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR1L

Internal Data Bus

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

Read TMR1L

Write TMR1L

TMR1ON

Clear TMR1

(CCP Special Event Trigger)

Time r1 Oscill ator

On/Off

Timer1

Timer3 Clock Input and

SEC_mo de System Cloc k

PIC18F2423/2523/4423/4523

12.2 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON< 7>) is set, the add ress fo r TMR1H is mappe d

to a buffer r egist er fo r the high b yte o f Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16 bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte, has

become invalid due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. The Timer1 high

byte is updated with the contents of TMR1H when a

write occurs to TMR1L. This allows a user to write all

16 bit s to both the high a nd low bytes of T imer1 at once.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

12.3 Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated

between pins T1OSI (input) and T1OSO (amplifier

output). It is enabled by setting the Timer1 Oscillator

Enable bit, T1OSCEN (T1CON<3>). The oscillator is a

low-power circuit rated for 32 kHz tuning fork style crys-

tals. It will continue to run during all power-managed

modes. The circuit for a typical LP oscillator is shown in

Figure 12-3. Table 12-1 shows the capacitor selection

for the Timer1 oscillator.

The user m us t pro vi de a sof tware time del ay to en su re

proper start-up of the Timer1 oscillator.

FIGURE 12-3: EXTERNAL

COMPONENTS FOR THE

TI MER1 LP OSCILLATOR

T ABLE 12-1: CAPACITOR SELECTION FOR

THE TIMER OSCILLATOR

12.3.1 USING TIMER1 AS A

CLOCK SOURCE

The T imer1 oscillato r is also avai lable as a clo ck source

in po wer-man aged mode s. By s etting t he cloc k select

bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device

switches to SEC_RUN mode; both the CPU and

periphera ls are clocked from the T imer1 oscillator . If the

IDLEN bit (OSCCON<7>) is cleared and a SLEEP

instruction is executed, the device enters SEC_IDLE

mode. Additional details are available in Section 3.0

“Power-M ana ged Modes”.

Whenever the Timer1 oscillator is providing the clock

source, the Timer1 system clock status flag, T1RUN

(T1CON< 6>), is set. Th is can be us ed to determine th e

controller’s current clocking mode. It can also indicate

the clock source being currently used by the Fail-Safe

Clock Monitor. If the Clock Monitor is enabled and the

Timer1 oscillator fails while providing the clock, polling

the T1RUN bit will indicate wheth er the clock is bei ng

provided by the Timer1 oscillator or another source.

12.3.2 LOW-POWER TIMER1 OPTION

The Timer1 oscillator can operate at two distinct levels

of power consumption based on device configuration.

When the LPT1OSC Configuration bit is se t, the Timer1

oscillator operates in a low-power mode. When

LPT1OSC is not set, T imer1 operates at a higher power

level. Po we r co ns um ptio n fo r a p art ic ula r mo de is rel a-

tively constant, regardless of the device’s operating

mode. The default Timer1 configuration is the higher

power mode.

As the low-power Timer1 mode tends to be more sen-

sitive to interference, high noise environments may

cause some oscillator instability. The low-power option

is, therefore, best suited for low noise applications

where power conservation is an important design

consideration.

Note: See the Notes with Table 12-1 for additiona

information about capacitor selection.

XTAL

PIC18FXXXX

T1OSI

T1OSO

32.768 kHz

Osc Type Freq C1 C2

LP (CL = 12.6 pF) 32 kHz 18 pF(1) 18 pF(1)

LP (CL = 6.0 pF) 32 kHz 6 pF(1) 6pF

(1)

Note 1: Microchip suggests these values as a

starting point in validating the oscillator

circuit.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

3: Capacitor values are for design guidance

only.

PIC18F2423/2523/4423/4523

12.3.3 TIMER1 OSCILLATOR LAYOUT

CONSIDERATIONS

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

The oscillator circuit, shown in Figure 12-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a hig h-s pee d cir cui t m us t b e loc ate d near the osc ill a-

tor (such as the CCP1 pin in Output Compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 12-4, may be helpful when used on a

single-sided PCB or in addition to a ground plane.

FIGURE 12-4: OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

12.4 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit, TMR1IF

(PIR1<0>). This interrupt can be enabled or disabled

by setting or clearing the Timer1 Interrupt Enable bit,

TMR1IE (PIE1<0>).

12.5 Resetting Time r1 Us ing the CCP

Special Event Trigger

If either of the CCP modules is configured to use Timer1

and generate a Special Event T rigger in Comp are mode

(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this

signal will reset Timer1. The trigger from CCP2 will also

start an A/D conversion if the A/D module is enabled

(see Secti on 15.3.4 “Special Event Tr igger” for more

information).

The module must be configured as either a timer or a

synch rono us cou nte r to t ak e a dva nt age of thi s fe ature.

When used this way, the CCPRH:CCPRL register pair

ef fe cti vely bec om es a period regi ste r for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

12.6 Using Timer 1 as a Real-Time Clock

Adding an extern al LP os cilla tor to Timer1 (such a s the

one described in Section 12.3 “Timer1 Oscillator”

above) gives users the option to include RTC function-

ality to their applications. This is accomplished with an

inexpensive watch crystal to provide an accurate time

base and several lines of application code to calculate

the time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

The application code routine, RTCisr, shown in

Example 12-1, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. I ncrementing the TM R1 re g-

ister pair to overflow triggers the interrupt and calls the

routine, w hich in creme nts the seco nds cou nter by on e;

additional counters for minutes and hours are

inc remented as t he previous count er overfl ow.

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to pre-

load it; the simple st method is to set the MSb of TMR1H

with a BSF instruction. Note that the TMR1L register is

never preloaded or altered; doing so may introduce

cumulative error over many cycles.

For this m ethod to be a ccurate, T imer 1 must oper ate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1), as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

VDD

OSC1

VSS

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

Note: The Special Event Triggers from the CCP

modules will not set the TMR1IF interrupt

flag bit (PIR1<0>).

PIC18F2423/2523/4423/4523

EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

RTCinit

MOVLW 80h ; Preload TMR1 register pair

MOVWF TMR1H ; for 1 second overflow

CLRF TMR1L

MOVLW b’00001111’ ; Configure for external clock,

MOVWF T1CON ; Asynchronous operation, external oscillator

CLRF secs ; Initialize timekeeping registers

CLRF mins ;

MOVLW .12

MOVWF hours

BSF PIE1, TMR1IE ; Enable Timer1 interrupt

RETURN

RTCisr

BSF TMR1H, 7 ; Preload for 1 sec overflow

BCF PIR1, TMR1IF ; Clear interrupt flag

INCF secs, F ; Increment seconds

MOVLW .59 ; 60 seconds elapsed?

CPFSGT secs

RETURN ; No, done

CLRF secs ; Clear seconds

INCF mins, F ; Increment minutes

MOVLW .59 ; 60 minutes elapsed?

CPFSGT mins

RETURN ; No, done

CLRF mins ; clear minutes

INCF hours, F ; Increment hours

MOVLW .23 ; 24 hours elapsed?

CPFSGT hours

RETURN ; No, done

CLRF hours ; Reset hours

RETURN ; Done

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52

PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52

IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52

TMR1L Timer1 Register Low Byte 50

TMR1H Timer1 Register High Byte 50

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50

Legend: Shaded cells are not used by the Timer1 module.

Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

13.0 TIMER2 MODULE

The Timer2 module timer incorporates the following

features:

• 8-bit timer and period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4 and

1:16)

• Software programmable postscaler (1:1 through

1:16)

• Interrupt on TMR2-to-PR2 match

• Optional use as the shift clock for the MSSP

module

The module is controlled through the T2CON register

(Register 13-1), which enables or disables the timer

and configures the prescaler and postscaler. Timer2

can be shut off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumpt ion.

A simplified block diagram of the module is shown in

Figure 13-1.

13.1 Timer2 Operation

In normal operation, TMR2 is incremented from 00h on

each clock (FOSC/4). A 4-bit counter/prescaler on the

clock input gives direct input, divide-by-4 and divide-by-

16 prescale options; these are selected by the prescaler

control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The

value of TMR 2 is comp ared to that of the period register ,

PR2, on each clock cycle. When the two values match,

the comparator generates a match signal as the timer

output. This signal also reset s the value of TMR2 to 00h

on the next cycle and drives the output counter/

postscaler (see Section 13.2 “T imer 2 Interrupt”).

The TMR2 and PR2 register s are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, while the PR2 register initializes at FFh.

Both the p rescaler and post scale r counters ar e cleare d

on the following events:

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

PIC18F2423/2523/4423/4523
DS39755B-page 134 Preliminary © 2007 Microchip Technology Inc.
13.2 Timer2 Interrupt
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This  coun ter gen erat es th e TMR2 m atc h inter rupt  flag
which  is latched in TM R2IF (PIR1<1>). The interrupt i s
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range o f  16  po stscale optio ns  (fro m 1 :1  thro ugh  1:1 6
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
13.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operat io ns in PWM mo de.  
T i mer2 ca n be op tion ally u sed as  the sh ift clo ck so urce
for the MSSP module operating in SPI mode. Addi-
tional information is provided in Section 17.0 “Master
Synchronous Serial Port (MSSP) Module”.
FIGURE 13-1: TIMER2 BLOCK DIAGRAM       
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER      
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
TMR2 Timer2 Register 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
PR2 Timer2 Period Register 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
Comparator
TMR2  Outpu t
TMR2
Postscaler
Prescaler PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS3:T2OUTPS0
T2CKPS1:T2CKPS0
Set TMR2IF
Inte rn a l  Data B u s 8
Reset TMR2/PR2
8
8
(to PWM or MSSP) 
Match

PIC18F2423/2523/4423/4523

14.0 TIMER3 MODULE

The Timer3 module timer/counter incorporates these

features:

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR3H

and TMR3L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Module Reset on CCP Speci al Event Trigger

A simplified block diagram of the Timer3 module is

shown in Fi gure 14-1. A bloc k di agr am of the mod ule ’s

operatio n in Read /Wr ite mode is show n in Figure 14-2.

The Timer3 module is controlled through the T3CON

options for the CCP modules (see Section 15.1.1

“CCP Modules and Timer Resources” for more

information).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer3 in one 16-bit operation

0 = Enables register read/write of Timer3 in two 8-bit operations

bit 6,3 T3CCP2:T3CCP1: Timer3 an d Timer1 to CCPx Enable bits

1x = Timer3 is the capture/compare clock source for the CCP modules

01 = Timer3 is the capture/compare clock source for CCP2;

Ti mer1 is the capture/compare clock source for CCP1

00 = Timer1 is the capture/compare clock source for the CCP modules

bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Pr escale Select b its

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the device clock comes from Timer1/Timer3.)

When TMR3CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1 TMR3CS: Timer3 Clock Source Select bit

1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first

falling edge)

0 = Internal clock (FOSC/4)

bit 0 TMR3ON: Timer3 On bit

1 = Enables Timer3

0 = Stops Timer3

PIC18F2423/2523/4423/4523

14.1 Timer3 Operation

Timer3 can operate in one of three modes:

•Timer

• Synchrono us Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>). When TMR3CS is cleared

(= 0), Timer3 increments on every internal instruction

cycle ( F OSC/4). When the bit is set, Timer3 increments

on every rising edge of the T13CKI clock input pin or

the Timer1 oscillator, if enabled.

As with Timer1, the RC1/T1OSI and RC0/T1OSO/

T13CKI pi ns becom e input s when the Timer1 oscil lator

is enabled. This means the values of TRISC<1:0> are

ignored and the pins are read as ‘0’.

FIGURE 14-1: TIMER3 BLOCK DIAGRAM

FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Peripheral Clock

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

TMR3ON

TMR3L Set

TMR3IF

on Overflow

TMR3

High Byte

Timer1 Oscillato r

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer3

CCP1/CCP2 Special Event Trigger

CCP1/CCP2 Select from T3CON<6,3> Clear TMR3

Timer1 Clock Input and

SEC_mode System Clock

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

Peripheral Clock

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8 Synchronize

Detect

T1OSO/T13CKI

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR3L

Internal Data Bus

Set

TMR3IF

on Overflow

TMR3

TMR3H

High Byte

Read TMR3L

Write TMR3L

TMR3ON

CCP1/CCP2 Special Event Tr igge r

Timer1 Oscillato r

On/Off

Timer3

CCP1/CCP2 Select from T3CON<6,3> Clear TMR3

Timer1 Clock Input and

SEC_mode System Clock

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 137
PIC18F2423/2523/4423/4523
14.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON< 7>) is set,  the add ress fo r TMR3H is  mappe d
to a  buffer r egist er fo r the  high b yte o f Timer3.  A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provi des  th e us er  with  the  abil it y to  acc urat ely  rea d all
16 bits of  Timer 3 withou t havi ng to det ermi ne whet her
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bit s to both the high a nd low bytes of T imer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register. 
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3 Using the Timer1 Oscillator as the 
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting  the T1 OSCEN  (T1CON <3>) bi t. To use it as th e
T imer3 clock  source, the  TMR3CS bit mu st also be set.
As previously noted, this also configures Timer3 to
increm ent on e very ri sin g edge  of the o scillato r so urce.
The Timer1 oscillator is described in Section 12.3
“Timer1 Oscillator”.
14.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3  Using the CCP 
Special Event Trigge r
If either of the CCP modules is configured to use
Timer3 and to generate a Special Event Trigger
in Compare mode (CCP1M3:CCP1M0 or
CCP2M3:CCP2M0 = 1011), the Special Event Trigger
will reset Timer3. The CCP2 Special Event Trigger will
also start an A/D conversion if the A/D module is
enabled  (see  Section 15.3.4 “Spe cial Eve nt Trigger”
for more information). 
The module must be configured as either a timer or
synch rono us  cou nte r to t ak e a dva nt age of thi s fe ature.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work. 
In the event that a write to Timer3 coincides with a
Special Event T rigger from a CCP modul e, the write will
take precedence. 
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER        
Note: The Special Event Triggers from the CCP
modules will not set the TMR3IF interrupt
flag bit (PIR2<1>). 
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR2 OSCFIF CMIF —EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE —EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP —EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
TMR3L Timer3 Register Low Byte 51
TMR3H Timer3 Register High Byte 51
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

15.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18LF2423/2523/4423/4523 devices all have two

CCP (Capt ure/Comp are/PWM) modules. Each mo dule

cont ains a 16-bi t regis ter wh ich can operate as a 1 6-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle regist er.

In 28-pin dev ices, the two st andard CCP modules (CC P1

and CCP2) operate as described in this chapter. In 40/

44-pin devices, CCP1 is im plemented as an Enhanced

CCP module with standard Capture and Compare

modes and Enhanced PWM modes. The ECCP imple-

mentation is discussed in Section 16.0 “Enhanced

Capture/Compare/PWM (ECCP) Module”.

The Ca pture and Comp are opera tions de scribed in this

chapter apply to all standard and Enhanced CCP

modules.

Note: Throughout this section and Section 16.0

“Enhanced Capture/Comp are/PWM (ECCP)

Module”, references to the register and bit

names for CCP module s are referred to gener-

ically by the use of ‘x’ or ‘y’ in place of the

specific module number. Thus, “CCPxCON”

might refer to the control register for CCP1,

CCP2 or ECCP1. “CCPxCON” is used

throughout these sections to refer to the mod-

ule control register, regardless of whether the

CCP module is a standard or Enhanced

implementation.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCPx Module

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs

(DCx9:DCx2) of the duty cycle are found in CCPRxL.

bit 3-0 CCPxM3:CCPxM0: CCPx Module Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0001 = Reserved

0010 = Compare mode: toggle output on match (CCPxIF bit is set)

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high

(CCPIF bit is set)

1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low

(CCPIF bit is set)

1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,

CCPx pin reflects I/O state)

1011 = Compare mode: trigger special event, reset tim er, start A/D conversion on

CCP2 match (CCPxIF bit is set)

11xx =PWM mode

PIC18F2423/2523/4423/4523

15.1 CCP Module Configuration

Each Capture/Compare/PWM module is associated

with a control register (generically, CCPxCON) and a

data register (CCPRx). The data register, in turn, is

comprised of two 8-bit registers: CCPRxL (low byte)

and CCPRxH (high byte). All registers are both

readable and wri tab le in Captu re and Co mpare modes.

CCPR1H is read-only in PWM mode.

15.1.1 CCP MODULES AND TIMER

RESOURCES

The CCPx modules utilize Timers 1, 2 or 3, depending

on the mo de selected. T imer1 and T imer3 are available

to modules in Capture or Compare modes, while

Timer2 is available for modules in PWM mode.

TABLE 15-1: CCP MODE – TIMER

RESOURCE

The assignment of a particular timer to a module is

determined by the Timer to CCP enable bits in the

T3CON register (Register 14-1). Both modules may be

acti ve at any given t ime an d may shar e the s ame tim er

resource if they are configured to operate in the same

mode (Capture/Compare or PWM) at the same time. The

interactions between the two modules are summarized in

Figure 15-1 and Figure 15-2. If the selected timer is in

Asynchronous Counter mode, the capture operation will

not work.

15.1.2 CCP2 PIN ASSIGNMENT

The pin as signment fo r CCP2 (Capture inpu t, Compare

and PW M output) c an chang e, based o n device config-

uration. The CCP2MX Configuration bit determines

which pin CCP2 is multiplexed to. By default, it is

assign ed to RC1 (CC P2MX = 1). If the Configuration bit

is cleared, CCP2 is multiplexed with RB3.

Changing the pin assignment of CCP2 does not auto-

matically change any requirements for configuring the

port pin. Users must always verify that the appropriate

TRIS register is configured correctly for CCP2

operation, regardless of where it is located.

TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES

CCP/ECCP Mode Timer Resource

Capture

Compare

PWM

Ti mer1 or Timer3

Timer2

CCP1 Mode CCP2 Mode Interaction

Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different

for each CCP.

Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3

(depending upon which time base is used). CCP2 Special Event Triggers will also start

A/D conversions. Operation of CCP1 could be affected if it is using the same timer as a

time base.

Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3

(depending upon which time base is used). Operation of CCP2 could be affected if it is

using the same timer as a time base.

Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.

CCP2 Special Event Triggers will also start A/D conversions. Conflicts may occur if both

modules are using the same time base.

Capture PWM(1) None

Compare PWM(1) None

PWM(1) Capture None

PWM(1) Compare None

PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).

Note 1: Includes standard and Enhanced PWM operation.

PIC18F2423/2523/4423/4523

15.2 Capture Mode

In Capture mode, the CCPRxH:CCPRxL register pair

captures the 16-bit value of the TMR1 or TMR3

registers when an event occurs on the corresponding

CCPx pin. An event is defined as one of the following:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

The event is selected by the mode select bits,

CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture

is made, the interrupt request flag bit, CCPxIF, is set; it

must be cleared in software. If another capture occurs

before the value in register CCPRx is read, the old

captured value is overwritten by the new captured value.

15.2.1 CCP PIN CONFIGURATION

In Capture mode, the appropriate CCPx pin should be

configured as an input by setting the corresponding

TRIS direction bit.

15.2.2 TIMER1/TIMER3 MODE SELECTION

The tim ers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchr oni zed Count er mode . I n As ynchr ono us Co unt er

mode, the capture operation will not work. The timer to be

used wit h each C CPx mo du le is selec t ed in th e T3C ON

Resources”).

15.2.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit clear while changing the

CCP mode to avoid false interrupts. The interrupt flag

bit, CCPxIF, should also be cleared following any such

change in ope rati ng mod e.

15.2.4 CCP PRESCALER

There are four prescaler settings in Capture mode; they

are specifie d as p art of the operati ng mode sel ected by

the mode select bits (CCPxM3:CCPxM0). Whenever

the CCPx module is turned off or Capture mode is

disabled, the prescaler counter is cleared. This means

that any Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleare d; therefore , the first cap ture may be from

a non-zero prescaler. Example 15-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 15-1: CHANGIN G BETWEEN

CAPTURE PRESCALERS

(CCP2 SHOWN)

FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

Note: If a CCP pin is configured as an output

while the CCP is in Captur e mode, a write

to that pi n can cause a CCP capture.

CLRF CCP2CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP2CON ; Load CCP2CON with

; this value

CCPR1H CCPR1L

TMR1H TMR1L

Set CCP1IF TMR3

Enable

Q1:Q4

CCP1CON<3:0>

CCP1 pin Prescaler

÷ 1, 4, 16 and

Edge Detect TMR1

Enable

CCPR2H CCPR2L

TMR1H TMR1L

Set CCP2IF

TMR3

Enable

CCP2CON<3:0>

CCP2 pin Prescaler

÷ 1, 4, 16

TMR3H TMR3L

TMR1

Enable

T3CCP2

T3CCP1

T3CCP2

T3CCP1

TMR3H TMR3L

and

Edge Detect

PIC18F2423/2523/4423/4523

15.3 Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against either the TMR1 or TMR3

can be:

• drive n high

• driven low

• toggled (high-to-low or low-to-high)

• remain unchan ged (that is, reflec ts the st ate of the

I/O latch)

The acti on on the pin is b ased on the val ue of the mode

select bits (CCPxM3:CCPxM0). At the same time, the

interrupt flag bit, CCPxIF, is set.

15.3.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

15.3.2 TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode

or Sy nchroni zed C ounter mode if th e CCP x modul e is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

15.3.3 SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCPxM3:CCPxM0 = 1010), t h e c o r res po nd i ng C C Px

pin is not affected. Only a CCP interrupt is generated,

if enabled and the CCPxIE bit is set.

15.3.4 SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Co mpare mo de to trig ger act ions by oth er mo dule s.

The Special Event Trigger is enabled by selecting

the Compare Special Event Trigger mode

(CCPxM3:CCPxM0 = 1011).

For either CCP module , the Special Event Tr igger resets

the timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a programm able

period register for either timer.

The S pecial Event Trigge r for C CP2 can a lso start an

A/D conversion. In order to do this, the A/D converter

must already be enabled.

FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM

Note: Clearing the CCPxCON register will force

the corresponding CCP pin output

comp are latch t o the defa ult low leve l. This

is not the pin output data latch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator Q

Output

Logic

Special Event Trigge r

Set CCP1IF

CCP1 pin

TRIS

CCP1CON<3:0>

Output Enable

TMR3H TMR3L

CCPR2H CCPR2L

Comparator

T3CCP2

T3CCP1

Set CCP2IF

Compare

(Timer1/Timer3 Reset)

Output

Logic

Special Event Trigger

CCP2 pin

TRIS

CCP2CON<3:0>

Output Enable

(Timer1/Timer3 Reset, A/D Trigger)

Match

Compare

Match

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 143
PIC18F2423/2523/4423/4523
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3    
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN SBOREN(2) —RI TO PD POR BOR 48
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
TRISB PORTB Data Di rection Control Regis ter 52
TRISC PORTC Data Direction Control Register 52
TMR1L Time r1 Register Low Byte 50
TMR1H Timer1 Register High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
TMR3H Timer3 Register High Byte 51
TMR3L Time r3 Register Low Byte 51
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
CCPR1L Ca ptur e/Compare/ PWM Register 1 Low Byte 51
CCPR1H Capture/Compare/PWM Register  1 High  Byte 51
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
CCPR2L Ca ptur e/Compare/ PWM Register 2 Low Byte 51
CCPR2H Capture/Compare/PWM Register  2 High  Byte 51
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51
Legend: — = unimplemented, read as ‘0’. Shaded cell s are not use d by Capture/Co mpare, Tim er1 or Timer3.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is 
disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.

PIC18F2423/2523/4423/4523

15.4 PWM Mode

In Pulse-W idth Modulati on (PWM) mode, the CCPx pin

produces up to a 10-bit resolution PWM output. Since

the CCP2 pin is multiplexed with a PORTB or PORTC

data latch, the appropriate TRIS bit must be cleared to

make the CCP2 pin an output.

Figure 15-3 shows a simplified block diagram of the

CCPx module in PWM mode.

For a step-by-step procedure on how to set up the

CCPx module for PWM operation, see Section 15.4.4

“Setup for PWM Operation”.

FIGURE 15-3: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 15-4) has a time base (period)

and a time that the output stays high (duty cycle).

The frequency of the PWM is the inverse of the

period (1/per iod) .

FIGURE 15-4: PWM OUTPUT

15.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

EQUATION 15-1:

PWM frequency is defined as 1/[PWM period].

When TM R2 is equal to PR2, t he following three event s

occur on the next increment cycle:

•TMR2 is cleared

• The CCPx pin is set (exception: if PWM duty

cycle = 0%, the CCPx pin will not be set)

• The PWM dut y cycle is l atched fro m CCPRx L into

CCPRxH

15.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPRxL register and to the CCPxCON<5:4> bits. Up

to 10-bit resolution is available. The CCPRxL contains

the eight MSbs and the CCPxCON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPRxL:CCPxCON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

EQUATION 15-2:

CCPRx L an d CC PxC O N<5 :4> c an be w ri tten to a t an y

time, but the duty cycle value is not latched into

CCPRxH until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPRxH is a read-only register.

Note: Clearing the CCPxCON register will force

the corresponding CCP pin output

comp are latch t o the defa ult low leve l. This

is not the pin output data latch.

CCPRxL

CCPRxH (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Regist ers CCPxCON<5:4>

Clear Timer,

CCP1 pin a nd

latch D.C.

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit

internal Q clock, or 2 bits of the prescaler, to create the

10-bit time base.

CCPx Output

Corresponding

TRIS bit

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note: The T imer2 post scalers (see Section 13.3

“Timer2 Output”) are not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •

TOSC • (TMR2 Prescale Value)

PIC18F2423/2523/4423/4523

The CCPRxH register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPRxH and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCPx pin is cleared.

The ma ximum P WM res olut ion (b its) fo r a giv en PWM

frequency is given by the equation:

EQUATION 15-3:

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

15.4.3 PWM AUTO-SHUTDOWN

(CCP1 ONLY)

The PWM auto-shutdown features of the Enhanced CCP

module are also available to CCP1 in 28-pin devices. The

operation of this feature is discussed in detail in

Section 16.4.7 “Enha nced PWM Auto-Shutdown”.

Auto-shutdown features are not available for CCP2.

15.4.4 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCPx module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPR xL register and CCPxCON<5:4 > bits.

3. Make the CCPx pin an output by clearing the

appropriate TRIS bit.

4. Set the TMR2 prescale value, then enable

Timer2 by writing to T2CON.

5. Configure the CCPx module f or PWM operatio n.

Note: If the PWM d uty c ycle v alu e i s lon ger tha n

the PWM period, the CCP2 pin will not be

cleared.

PWM Resolution (max) =

FOSC

FPWM * TMR 2 Pre s cale Value

log

bit

log(2)

⎛

⎜

⎝

⎛

⎜

⎝

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 1 0 8 7 6.5 8

PIC18F2423/2523/4423/4523
DS39755B-page 146 Preliminary © 2007 Microchip Technology Inc.
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2     
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit  2 Bit 1 Bit 0 Rese t 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN SBOREN(2) —RI TO PD POR BOR 48
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
TRISB PORTB Data  Directi on Contro l Registe r 52
TRISC PORT C Data Direction Control Register 52
TMR2 T imer2 Register 50
PR2 Time r2 Perio d Regis ter 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
CCPR1L Capture/C omp are /PWM Reg iste r 1 Low Byte 51
CCPR1H Capture/Compare/PWM Register 1 High Byte 51
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
CCPR2L Capture/C omp are /PWM Reg iste r 2 Low Byte 51
CCPR2H Capture/Compare/PWM Register 2 High Byte 51
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 51
ECCP1DEL PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 51
Legend: — = unimplem e nte d,  re ad  as  ‘0’. Shaded cel ls are not use d  by  PW M  or  Timer2.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear .
2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is 
disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.

PIC18F2423/2523/4423/4523

16.0 ENHANCED CAPTURE/

COMPARE/PWM (ECCP)

MODULE

In PIC18LF4423/4523 devices, CCP1 is implemented

as a standard CCP module with Enhanced PWM

capabilities. These include the provision for 2 or 4

output channels, user-selectable polarity, dead-band

control and automatic shutdown and restart. The

enhanced features are discussed in detail in

Section 16.4 “Enhanced PWM Mode”. Capture,

Compare and single-output PWM functions of the

ECCP module are the same as described for the

standard CCP module.

The control register for the Enhanced CCP module is

shown in Register 16-1. It differs from the CCPxCON

registers in PIC18LF2423/2523 devices in that the two

Most Significant bits are implemented to control PWM

functionality.

Note: The ECCP mo dule is impl eme nte d onl y in

40/44-pin devices.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits

If CCP1M3:CCP1M2 = 00, 01, 10:

xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins

If CCP1M3:CCP1M2 = 11:

00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pi ns

01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive

10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as

port pins

11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive

bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bit s are the tw o LSbs of the 1 0-bit PW M duty cycl e. The e ight M Sbs of t he duty cycle a re fo und

in CCPR1L.

bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits

0000 = Capture/Compare/PWM off (resets ECCP module)

0001 = Reserved

0010 = Compare mode, toggle output on match

0011 = Capture mode

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)

1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)

1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state

1011 = Compare mode, Special Event Trigger (ECCP resets TMR1 or TMR3, sets CC1IF bit)

1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low

PIC18F2423/2523/4423/4523
DS39755B-page 148 Preliminary © 2007 Microchip Technology Inc.
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has an additional register
associated with Enhanced PWM operation and
auto-shutdo wn fe atures. It is:
• ECCP1DEL (Dead-Band Delay) 
16.1 ECCP Outputs and Configuration 
The E nhance d CCP  modul e may h ave up  to  four PW M
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD. The
outputs that are active depend on the CCP operating
mode selected. The pin assignments are summarized
in Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the
P1M1:P1M0 and CCP1M3:CCP1M0 bits. The
appropriate TRISC and  TRISD direction bit s for the port
pins must also be set as outputs.
16.1.1 ECCP MODULES AND TIMER 
RESOURCES
Like the  standard CCP modules, the ECCP m odule can
utilize Timers 1, 2 or 3, depending on the mode
select ed. Timer1 an d Timer3 are a va ila ble  for m od ule s
in Capture or Compare modes, while Timer2 is avail-
able for modules in PWM mode. Interactions between
the st andard and  Enhanced CCP mod ules are id entical
to those described for standard CCP modules.
Additional details on timer resources are provided in
Section 15.1.1 “CCP Modules and Timer
Resources”.
16.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP2. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “Compare
Mode”. No changes are required when moving
between 28-pin and 40/44-pin devices.
16.2.1 SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP1 resets the
TMR1 o r TMR3 registe r pa ir , depe nding on w hich timer
resource is currently selected. This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1 or Timer3.    
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode, as in Table 16-1.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES  
Note: When se tti ng up si ngl e output PWM oper-
ations, users are free to use either of the
processes described in Section 15.4.4
“Setup for PWM Operation” or
Section 16.4.9 “Setup for PWM Opera-
tion”. The latter is more generic and will
work for ei ther single or multi-output PWM.
ECCP Mode CCP1CON
Configuration RC2 RD5 RD6 RD7
All 40/44-pin devices:
Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7
Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7
Quad PWM x1xx 11xx P1A P1B P1C P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.

PIC18F2423/2523/4423/4523

16.4 Enhanced PWM Mode

The Enhanced PWM mode provides additional PWM

output options for a broader range of control applica-

tions. The module is a backward comp a t ib le ve rsi on of

the st andard CCP m odule and o ffers up to four output s,

designated P1A through P1D. Users are also able to

select the polarity of the signal (either active-high or

active -low). The module’ s outpu t mode an d polarit y are

configured by setting the P1M1:P1M0 and

CCP1M3:CCP1M0 bits of the CCP1CON register.

Figure 16-1 shows a simplified block diagram of PWM

operatio n. All con trol regi sters are double -buf fe red and

are loaded at the beginning of a new PWM cycle (the

period boundary when Timer2 resets) in order to pre-

vent gli tches on any of the outputs. The exception is the

PWM Delay register, ECCP1DEL, which is loaded at

either the duty cycle boundary or the period boundary

(whichever comes first). Because of the buffering, the

module waits unt il the assigne d timer reset s, inste ad of

starting immediately. This means that Enhanced PWM

waveforms do not exactly match the standard PWM

wavef orms, but are ins tead of fset by one ful l instruc tion

cycle (4 TOSC).

As before, the user must manually configure the

appropriate TRIS bits for output.

16.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following equation.

EQUATION 16-1:

PWM frequency is defined as 1/[PWM period]. When

TMR2 is e qual to PR 2, the foll owing three event s occur

on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (if PW M duty cycle = 0%, the

CCP1 pin will not be set)

• The PWM duty cycle is copi ed from CCPR 1 L into

CCPR1H

FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE

Note: The Timer2 postscaler (see Section 13.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Timer,

set CCP1 pin and

latch D.C.

Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.

TRISx<x>

CCP1/P1A

TRISx<x>

P1B

TRISx<x>

P1D

Output

Controller

P1M1<1:0> 2CCP1M<3:0>

ECCP1DEL

CCP1/P1A

P1B

P1C

P1D

P1C

PIC18F2423/2523/4423/4523

16.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The PWM duty cycle is

calculated by the following equation.

EQUATION 16-2:

CCPR1L and CC P1CON <5:4> c an be wr itten to at an y

time, but the duty cycle value is not copied into

CCPR1H until a m atch between PR2 and TM R2 occurs

(i.e., the period is complete ). In PWM mode, CCPR1H

is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-b uf feri ng is esse ntial for g litchl ess PWM ope ra-

tion. When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or two bits

of the TMR2 prescaler, the CCP1 pin is cleared. The

maximum PWM resolution (bits) for a given PWM

frequency is given by the following equation.

EQUATION 16-3:

16.4.3 PWM OUTPUT CONFIGURATIONS

The P1M1:P1M0 bits in the CCP1CON register allow

one of four configurations:

• Single Output

• Half-Bridge Output

• Full-Bridge Output, Forwar d mode

• Full-Bridge Output, Reverse mode

The Single Output mode is the standard PWM mode

discussed in Section 16.4 “Enhanced PWM Mode”.

The Half-Bridge and Full-Bridge Output modes are

covered in detail in the sections that follow.

TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

Note: If the PWM d uty c ycle v alu e i s lon ger tha n

the PWM period, the CCP1 pin will not be

cleared.

PWM Resolution (max) =

FOSC

FPWM * TMR 2 Pre s cale Value

log

bit

log(2)

⎛

⎜

⎝

⎛

⎜

⎝

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 1 0 8 7 6.5 8

PIC18F2423/2523/4423/4523

FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

Period

SIGNAL PR2 + 1

CCP1CON

<7:6>

P1A Modulated

P1B Modulated

P1A Ac ti ve

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

Duty

Cycle

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Period

SIGNAL PR2 + 1

CCP1CON

<7:6>

P1A Modulated

P1B Modulated

P1A Ac ti ve

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

Duty

Cycle

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Relationships:

• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

• D uty C ycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

• Delay = 4 * TOSC * (E CCP1DEL<6:0>)

Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 16.4.6 “Programmable

Dead-Band Delay”).

PIC18F2423/2523/4423/4523

16.4.4 HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used as

output s to drive p ush-pull load s. The PWM output s ignal

is output on the P1A pin, whi le the complementary PWM

output signal is output on the P1B pin (Figure 16-4). This

mode can be used for half-bridge applications, as shown

in Figure 16-5, or for full-bridge applications where four

power switches are being modulated with two PWM

signals.

In Half-Bridge Output mode, the programmable dead-

band delay can be used to prevent shoot-through

current in half-bridge power devices. The value of bits,

PDC6:PDC0, sets the number of instruction cycles

befor e the output is driven acti ve. If the v alue is g reater

than the duty cycle, the corresponding output remains

inactive during the entire cycle. See Section 16.4.6

“Programmable Dead-Band Delay” for more details

of the dead-band delay operations.

Since the P1A and P1B outputs are multiplexed with

the PORTC<2> and PORTD<5> data latches, the

TRISC<2> and TRISD<5> bits must be cleared to

configure P1A and P1B as outputs.

FIGURE 16-4: HALF-BRIDGE PWM

OUTPUT

FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

Period

Duty Cycle

(1)

P1A(2)

P1B(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

PIC18F4X23

P1A

P1B

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

PIC18F4X23

P1A

P1B

Standard Half-Bridge Circuit (“Push-Pull”)

Half-Bridge Output Driving a Full-Bridge Circuit

PIC18F2423/2523/4423/4523

16.4.5 FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as

outputs; however , only two outputs are active at a time.

In the Forward mode, pin P1A is continuously active

and pin P1D is modulated. In the Reverse mode, pin

P1C is continuously active and pin P1B is modulated.

These are illustrated in Figure 16-6.

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORTC<2> and PORTD<7:5> data latches. The

TRISC<2> and TRISD<7:5> bits must be cleared to

make the P1A, P1B, P1C and P1D pins outputs.

FIGURE 16-6: FULL-BRIDGE PWM OUTPUT

Period

Duty Cycle

P1A(2)

P1B(2)

P1C(2)

P1D(2)

Forwar d Mo de

(1)

Period

Duty Cycle

P1A(2)

P1C(2)

P1D(2)

P1B(2)

Reverse Mode

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

Note 2: Output signal is shown as active-high.

PIC18F2423/2523/4423/4523

FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION

16.4.5.1 Directio n Change in Full-Br idge M ode

In the Full-Bridge Output mode, the P1M1 bit in the

CCP1CON register allows the user to control the

forward/reverse direction. When the application firm-

ware changes this direction control bit, the module will

assume the new direction on the next PWM cycle.

Just before the end of the current PWM period, the

modulated outputs (P1B and P1D) are placed in their

inactiv e state, whil e the unmodula ted outputs (P1A and

P1C) are switched to drive in the opposite direction.

This occurs in a time interval of 4 TOSC * (Timer2

Prescale Value) before the next PWM period begins.

The Timer2 prescaler will be either 1, 4 or 16, depend-

ing on the value of the T2CKPS1:T2CKPS0 bits

(T2CON<1:0>). During the interval from the switch of

the unmodulated outputs to the beginning of the next

period, the modulated outputs (P1B and P1D) remain

inactive. This relationship is shown in Figure 16-8.

Note that in the Full-Bridge Output mode, the CCP1

module do es not prov ide any dead-band de lay. In ge n-

eral, since only one output is modulated at all times,

dead-band delay is not required. However, there is a

situation where a dead-band delay might be required.

This situation occurs when both of the following

conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn-off ti me of the power swi tch, in cluding

the power device and driver circuit, is greater

than the turn-on tim e.

Figure 16-9 shows an example where the PWM

direction changes from forward to reverse at a near

100% duty cycle. At time t1, the outputs P1A and P1D

become inactive, while output P1C becomes active. In

this example, since the turn-off time of the power

device s is longer th an the turn-on time, a shoot-through

current may flow through power devices, QC and QD

(see Figure 16-7), for the duration of ‘t’. The same

phenomenon will occur to power devices, QA and QB,

for PWM direction change from reverse to forward.

If changing PWM direction at high duty cycle is required

for an application, one of the following requirements

must b e met:

1. Reduce PWM for a PWM period before

changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

P1A

P1C

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

P1B

P1D

QB QD

PIC18F4X23

PIC18F2423/2523/4423/4523

FIGURE 16-8: PWM DIRECTION CHANGE

FIGURE 16-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Period(1)

SIGNAL

Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals

of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals

are inactive at this time.

Period

(Note 2)

P1A (Active-High)

P1B (Active-High)

P1C (Active-High)

P1D (Active-High)

Forward Period Reverse Period

P1A(1)

tON(2)

tOFF(3)

t = tOFF – tON(2,3)

P1B(1)

P1C(1)

P1D(1)

External Sw itch D(1)

Potential

Shoot-Through

Current(1)

Note 1: All signals are shown as active-high.

2: tON is the turn-on delay of power switch QC and its driver.

3: tOFF is the turn-off delay of power switch QD and its driver.

External Sw itch C(1)

PIC18F2423/2523/4423/4523

16.4.6 PROGRAMMABLE DEAD-BAND

DELAY

In half-b ridge applications where all po wer switches are

modulated at the PWM frequency at all times, the

power switches normally require more time to turn off

than to turn on. If both the upper and lower power

switc he s a re sw it ched at the same time (one turne d o n

and the other turned off), both switches may be on for

a short period of time until one switch completely turns

off. During this brief interv al, a very hig h current (shoot-

through current) may flow through both power

switches, shorting the bridge supply. To avoid this

potentia lly des tructiv e shoot -through current from flow-

ing during switching, turning on either of the power

switches is normally delayed to allow the other switch

to completely turn off.

In the Half-Bridge Output mode, a digitally programmable

dead-b and de lay i s avai labl e to avo id sh oot-th roug h cur-

rent from destroying the bridge power switches. The

delay occurs at the signal transition from the nonactive

state to the act ive state . See F igure 16-4 for illu strat ion.

Bits PDC6:PDC0 of the ECCP1DEL register

(Register 16-2) set the delay period in terms of micro-

controller instruction cycles (TCY or 4 TOSC). These bits

are no t availabl e on 28-p in devices as the st andard CC P

modul e do es n ot su pport h al f -b rid ge op er ation.

16.4.7 ENHANCED PWM AUTO-SHUTDOWN

When the CCP1 is programmed for any of the Enhanced

PWM modes, the active output pins may be configured

for auto-shutdown. Auto-shutdown immediately places

the Enhanced PWM output pins into a defined shutdown

state when a shut dow n even t occurs.

A shutdown event can be caused by either of the

comparator modules, a low level on the Fault input pin

(FLT0) or any combination of these three sources. The

comparators may be used to monitor a voltage input

proportional to a current being monitored in the bridge

circuit. If the voltage exceeds a threshold, the

comparator switches state and triggers a shutdown.

Alternatively , a low digital signal on FL T0 can also trigger

a shut down. The auto-shutdown fea ture can be disabled

by not selecting any auto-shutdown sources. The auto-

shutdown sources to be used are selected using the

ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS

When a shutdown occurs, the output pins are asyn-

chronously placed in their shutdown states, specified

by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits

(ECCP1AS3:ECCP1AS0). Each pin pair (P1A/P1C

and P1B/P1D) may be set to drive high, drive low or be

tri-stated (not driving). The ECCPASE bit

(ECCP1A S<7>) is also s et to ho ld the En hance d PWM

outputs in their shutdown states.

The ECCPASE bit is set by har dware when a shu tdown

event o cc urs. If autom ati c re starts are no t e nab led , th e

ECCPASE bit is cleared by firmware when the cause of

the shutdown clears. If automatic restarts are enabled,

the ECCPASE bit is automatically cleared when the

cause of the auto-shutdown has cleared.

If the ECCPASE bit is set when a PWM period begins,

the PWM o utputs remain in their shutdown state for that

entire PW M peri od. Wh en the ECCPASE bit is c leared,

the PWM outputs will return to normal operation at the

beginning of the next PWM period.

Note: Programmable dead-band delay is not

implemented in 28-pin devices with

standard CCP modules.

Note: Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PRSEN: PWM Restart Enable bit

1 = Upon auto-shut down, the ECCP ASE bit clears automatically on ce the shutdown event goes away;

the PWM restarts automatically

0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0 PDC6:PDC0: PWM Delay Count bits(1)

Delay ti me, i n numb er o f FOSC/4 (4 * TOSC) cycles, b etwee n the s chedule d and a ctual time for a PWM

signal to transition to active.

Note 1: Reserved on 28-pin devices; maintain these bits clear.

CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit

1 = A shutdown event has occurred; ECCP outputs are in shutdown state

0 = ECCP outputs are operating

bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-S hutdown Source Select bit s

111 = FLT0 or Comparator 1 or Comparator 2

110 = FLT0 or Comparator 2

101 = FLT0 or Comparator 1

100 =FLT0

011 = Either Comparator 1 or 2

010 = Comparator 2 output

001 = Comparator 1 output

000 = Auto-shutdown is disabled

bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits

1x = Pins A and C are tri-state (40/44-pin devices); PWM output is tri-state (28-pin devices)

01 = Drive Pins A and C to ‘1’

00 = Drive Pins A and C to ‘0’

bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1)

1x = Pins B and D tri-state

01 = Drive Pins B and D to ‘1’

00 = Drive Pins B and D to ‘0’

Note 1: Reserved on 28-pin devices; maintain these bits clear.

PIC18F2423/2523/4423/4523

16.4.7.1 Auto-Shutdown and Automatic

Restart

The auto-shutdown feature can be configured to allow

automatic restarts of the module following a shutdown

event. This is enabled by setting the PRSEN bit of the

ECCP1DEL register (ECCP1DEL<7>).

In Shut down mode with PRSEN = 1 (Figure 16-10), the

ECCPASE bit will remain set for as long as the cause

of the shutdown continues. When the shutdown condi-

tion clears, the ECCPASE bit is cleared. If PRSEN = 0

(Fig ure 16 -11 ), o nce a s hutdow n c ond itio n oc cur s, the

ECCPASE bit will remain set until it is cleared by firm-

ware. Onc e ECCPASE is cleared, the Enha nc ed PW M

will resume at the beginning of the next PWM period.

Independent of the PRSEN bit setting, if the auto-

shutdown source is one of the comparators, the

shutdown condition is a level. The ECCPASE bit

cannot be cleared as long as the cause of the shutdown

persists.

The Auto-Shu tdown mode can be force d by writing a ‘1’

to the ECCPASE bit.

16.4.8 START-UP CONSIDERATIONS

When the EC CP module is use d in the PWM mode, th e

applic ation hardware m ust use the p roper external pull-

up and/or pull-down resistors on the PWM output pins.

When the microcontroller is released from Reset, all of

the I/O p ins are in the h igh-impedan ce state. The exter-

nal circuits must keep the power switch devices in the

OFF state until the microcontroller drives the I/O pins

with the proper signal levels, or activates the PWM

output(s).

The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow

the user to choose whether the PW M output signals are

active-high or active-low for each pair of PWM output

pins (P1A/P1C and P1B/P1D). The PWM output

polarities must be selected before the PWM pins are

configu red as output s. Changin g the p olarity conf igura-

tion while the PWM pins are configured as outputs is

not recom mended, sinc e it may result i n damage to th e

application circuits.

The P1A, P1B, P1C and P1D output latches may not be

in the proper states when the PWM module is initialized.

Enabling the P WM pins for outp ut at the sa me time as

the ECCP module may cause damage to the applica-

tion circuit . The ECCP module must be enabl ed in the

proper output mode and complete a full PWM cycle

before configuring the PWM pins as o utputs. The com-

pletion o f a f ull PWM c ycle is indicate d by the TMR2I F

bit being set as the second PWM period begins.

FIGURE 16-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)

FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)

Note: Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

Shutdown

PWM

ECCPAS E bit

Activity

Event

Shutdown

Event Occurs Shutdown

Event Clears PWM

Resumes

Normal PWM

Start of

PWM Period

Shutdown

PWM

ECCPA SE bi t

Activity

Event

Shutdown

Event Occurs Shutdown

Event Clears PWM

Resumes

Normal PWM

Start of

PWM Period

ECCPASE

Cleared by

Firmware

PWM Period

PIC18F2423/2523/4423/4523

16.4.9 SETUP FOR PWM OPERA TIO N

The following steps should be taken when configuring

the ECCP module for PWM operation:

1. Configure the PWM pins, P1A and P1B (and

P1C and P1D, if used), as inputs by setting the

corresponding TRIS bits.

2. Set the PWM period by loading th e PR2 register .

3. If auto-shutdown is required:

• Disable auto-shutdown (ECCPASE = 0)

• Configure source (FLT0, Comparator 1 or

Comparator 2)

• Wait fo r non-shutdown condition

4. Configure the ECCP module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

• Select on e of the avail able output

configurations and direction with the

P1M1:P1M0 bits.

• Select the polarities of the PWM output

signals with the CCP1M3:CCP1M0 bits.

5. Set the PWM du ty cycle by loading the CCPR1L

6. For Half-Bridge Output mode, set the dead-

band delay by loading ECCP1DEL<6:0> with

the appropriate value.

7. If auto-shutdown operation is required, load the

ECCP1AS register:

• Select the auto-s hutdown sources using the

ECCPAS2:ECCPAS0 bits.

• Select the shutdown states of the PWM

output pins using the PSSAC1:PSSAC0 and

PSSBD1:PSSBD0 bits.

• Set the ECCPASE bit (ECCP1AS<7>).

• Configure th e compa rators using the CMCON

• Configure the comparator inputs as analog

inputs.

8. If auto-restart operation is required, set the

PRSEN bit (ECCP1DEL<7>).

9. Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

• Set the TMR2 prescale value by loading the

T2CKPS<1:0> bits (T2CON<1:0>).

• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

10. Enable PWM outputs after a new PWM cycle

has started:

• Wait unt il TMR n overflo ws (TMR nIF bit is set).

• En able the CCP1/P1A, P1B, P1C and/o r P1D

pin outputs by clearing the respective TRIS

bits.

• Clear the ECCPASE bit (ECCP1AS<7>).

16.4.10 OPERATION IN POWER- M ANAG ED

MODES

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the ECCP pin is driving a value, it will con-

tinue to drive that value. When the device wakes up, it

will conti nue from this st ate. If T wo-Spee d St art-ups a re

enabled, the initial start-up frequency from INTOSC

and the postscaler may not be stable immediately.

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change. In all other

power-managed modes, the selected power-managed

mode clock will clock Timer2. Other power-managed

mode clocks will most likely be different than the

primary clock frequency.

16.4.10.1 Operation with Fail-Safe

Clock Monitor

If the Fai l-Safe Cl ock Monito r is enabl ed, a clock failure

will forc e the d evice i nto the power-m anaged RC_RUN

mode and the OSCFIF bit (PIR2<7>) will be set. The

ECCP will then be clocked from the internal oscillator

clock source, which may have a different clock

frequency than the primary clock.

See the previous section for additional details.

16.4.11 EFFECTS OF A RESET

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the CCP registers to their

Reset states.

This forces the Enhanced CCP module to reset to a

state compatible with the standard CCP module.

PIC18F2423/2523/4423/4523
DS39755B-page 160 Preliminary © 2007 Microchip Technology Inc.
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3     
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN SBOREN(1) —RI TO PD POR BOR 48
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
PIR2 OSCFIF CMIF —EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE —EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP —EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
TRISB PORTB Data Direction Control Register 52
TRISC PORTC Data Direction Control Register 52
TRISD PORTD Data Direction Control Register 52
TMR 1L Ti m er 1 Register  Low Byte 50
TMR 1H Timer1 Re gist er  H ig h Byt e 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
TMR2 Timer2 Register 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
PR2 Timer2 Period  Regi s te r 50
TMR 3L Ti m er 3 Register  Low Byte 51
TMR 3H Timer3 Re gist er  H ig h Byt e 51
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
CCPR1L Capture/Compare/PWM Register 1 Low Byte 51
CCPR1H Capture/Compare/PWM Register 1 High Byte 51
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 51
ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 51
Legend: —  = unimpl em ented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: T he SBOREN bit  is  only av ai l able w hen the BO RE N1: BO REN0 Co nf ig ur at ion bi ts = 01; o therwise, it is di sabled 
and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
2: Thes e bits are unimpl em ented on 28-pin devi ces; always  maintain thes e bits clear.

PIC18F2423/2523/4423/4523

17.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

17.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface, useful for communicating with other

periphera l or m icroc ontroll er devic es. Th ese p eriphera l

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C)

- Full Master mode

- Slave mode (with general address call)

The I2C interface supports the following modes in

hardware:

•Master mode

• Multi-Master mode

• Slave mode (with addres s masking f or both 1 0-bit

and 7-bit addressing)

17.2 Control Registers

The MSSP module has three associated registers.

These include a status register (SSPSTAT) and two

control registers (SSPCON1 and SSPCON2). The use

of thes e register s and their ind ividual C onfigurati on bit s

differ significantly depending on whether the MSSP

module is operated in SPI or I2C mode.

Additional details are provided under the individual

sections.

17.3 SPI Mode

The S PI mode allo ws 8 bits of dat a to be sy nchronousl y

transmitted and received simultaneously. All four

modes of SPI are supported. To accomplish

communication, typically three pins are used:

• Serial Data Out (SDO) – RC5/SDO

• Serial Data In (SDI) – RC4/SDI/SDA

• Serial Clock (SCK) – RC3/SCK/SCL

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slav e Select (SS ) – RA5/AN4/SS/HLVDIN/

C2OUT

Figure 17-1 shows the block diagram of the MSSP

module when operating in SPI mode.

FIGURE 17-1: MSSP BLOCK DIAGRAM

(SPI MODE)

( )

Read Write

Internal

Data Bus

SSPSR reg

SSPM3:SSPM0

bit 0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

TRIS bit

SMP:CKE

SDO

SSPBUF reg

SDI

SCK

Note: Only port I /O names are us ed in this diagram f or

the sake of brevity. Refer to the text for a full list of

multiplexed functions.

PIC18F2423/2523/4423/4523

17.3.1 REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

SSPCON1 and SSPSTAT are the control and status

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buff ered. A write to SSPBUF will write to bo th SSPBUF

and SSPSR.

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE(1) D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6 CKE: SPI Clock Select bit(1)

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

bit 5 D/A: Data/Addre ss bit

Used in I2C mode only.

bit 4 P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3 S: Start bit

Used in I2C mode only.

bit 2 R/W: Read/Write Inform ation bit

Used in I2C mode only.

bit 1 UA: Update Address bit

Used in I2C mode only.

bit 0 BF: Buffer Full Status bit (Receive mode only)

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>).

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV(1) SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit (Transmit mode onl y )

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit(1)

SPI Slave mode:

1 = A new byte is received while the SSPBUF register is still hol ding the previous da ta. In case of over-

flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the

SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in so ftware).

0 = No overflow

bit 5 SSPEN: Master Synchronous Serial Port Enable bit

1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2)

0 = Disables serial port and configures these pins as I/O port pins(2)

bit 4 CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits

0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin(3)

0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled(3)

0011 = SPI Master mode, clock = TMR2 output/2(3)

0010 = SPI Master mode, clock = FOSC/64(3)

0001 = SPI Master mode, clock = FOSC/16(3)

0000 = SPI Master mode, clock = FOSC/4(3)

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPBUF register.

2: When enabled, these pins must be properly configured as input or output.

3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

PIC18F2423/2523/4423/4523

17.3.2 OPERATION

When initializing the SPI, several options need to be

specif ied. This is done by progra mming the ap propriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buf fer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received da ta is ready. Once the 8 bit s of data

have bee n received, that byte is moved to the SSPBUF

(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading t he data that was just re ceived. Any write to the

SSPBUF register during transmission /reception of dat a

will be ign ore d an d the wr ite c ol lis io n de tec t bi t, WCO L

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determin ed if the foll ow-

ing write(s) to the SSPBUF register completed

successfully.

When the application software is expecting to receive

valid da ta, the SSPBUF shoul d be read before th e next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF (SSPSTAT<0>), indicates when

SSPBUF has been loaded with the received data

(transmiss ion is complete ). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmit ter . Generall y, the MSSP interru pt

is used to determine when the transmission/reception

has completed. The SSPBUF must be read and/or

written. If the interrupt method is not going to be used,

then sof tware polli ng can be do ne to ensure t hat a write

collision does not occur. Example 17-1 shows the

loading of the SSPBUF (SSPSR) for data transmission.

The SSPSR is n ot directly reada ble or writ able and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP Status register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 17-1: LOADING THE SSP BUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?

BRA LOOP ;No

MOVF SSPBUF, W ;WREG reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

PIC18F2423/2523/4423/4523

17.3.3 ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, reinitialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pin s. For the pins t o behave as the serial p ort fun c-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

• SDI is automa tic all y c on trol led by the SP I module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• SCK (Slave mode) must have TRISC<3> bit set

•SS

must have TRISA<5> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

17.3.4 TYPICAL CO NNEC TION

Figure 17-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock e dge and l atched on the oppos ite edge

of the cloc k. Both processors should be programmed to

the same Clock Polarity (CKP), then both controllers

would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends data – Slave sends dummy data

• Master sends data – Slave sends data

• Master sends dummy data – Slave sends data

FIGURE 17-2: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb LSb

SDO

SDI

PROC ESSOR 1

SCK

SPI Master (SSPM 3:SSP M0 = 00xxb)

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSbMSb

SDI

SDO

PROC ESSOR 2

SCK

SPI Slave (SSPM3:SSPM0 = 010xb)

Serial Clock

PIC18F2423/2523/4423/4523

17.3.5 MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 17-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF registe r is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal p resent on the S DI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately

programming the CKP bit (SSPCON1<4>). This then,

would give waveforms for SPI communication, as

shown in Figure 17-3, Figure 17-5 and Figure 17-6,

where t he MSB is tran smitted fi rst. In Ma ster mode , the

SPI clock rat e (bit rate) is user-prog rammable to be one

of the fo llowing:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2

Figure 17-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

dat a is shown.

FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycl e

after Q2↓

bit 0

PIC18F2423/2523/4423/4523

17.3.6 SLAVE MODE

In Slave m ode , the dat a is trans mi tted and rece iv ed a s

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the

clock line must match the proper Idle state. The clock

line can be observed by reading the SCK pin. The Idle

state is determined by the CKP bit (SSPCON1<4>).

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

17.3.7 SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode wit h SS pin control ena bled

(SSPCON1<3:0> = 04h). The pin must not be driven

low for the SS pin to function as an in put. The data latch

must be high. When the SS pin is low , transmission and

receptio n are enab led and the SDO pin is driv en. When

the SS pin goes hi gh , th e SD O pin is no lo n ge r dr iv en ,

even if in the middle of a tran smitted byte an d becomes

a floating output. External pull-up/pull-down resistors

may be desirable depending on the application.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an in put. This d isables transmissi ons from th e SDO.

The SDI can always be left as an input (SDI function)

since it cann ot cre ate a bus con flict.

FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM

Note 1: When the SP I is in Sl ave mode with SS pin

contro l enabled (SSP CON1<3:0> = 0100),

the SP I module will res et if the SS pi n is set

to VDD.

2: If the SPI is us ed in Slave mo de with CK E

set, then the SS pin control must be

enabled.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit 7

SDO bit 7 bit 6 bit 7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Wr i te to

SSPBUF

SSPSR to

SSPBUF

Flag

bit 0

bit 7 bit 0

Next Q4 Cycle

after Q2↓

PIC18F2423/2523/4423/4523

FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit 7

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

Optional

Next Q4 Cycle

after Q2↓

bit 0

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

Interrupt

(SMP = 0)

CKE = 1)

(SMP = 0)

Write to

SSPBUF

SSPS R to

SSPBUF

Flag

Not Optional

Next Q4 Cycle

after Q2↓

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 169
PIC18F2423/2523/4423/4523
17.3.8 OPERATION IN POWER-MANAGED 
MODES
In SPI  Master mo de, modu le clo cks may be op erati ng
at a different speed than when in full power mode. In
the case of Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock will be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INT OSC source. See Section 2.7 “Clock Source s
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP inte rrupts are en abled, they can  wake the con-
troller from Sleep mode, or on e of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will freeze until
the device wakes. After the device returns to Run
mode, the module will resume transmitting and
receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
17.3.9 EFFECTS OF A RESET
A Reset disables  the MSSP module and terminat es the
current transfer.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits. 
TABLE 17-1: SPI BUS MODES          
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION       
Standard SPI Mode 
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 52
TRISC PORTC Data Direction Control Register 52
SSPBUF MSSP Receive Buffer/Transmit Register 50
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50
SSPSTAT SMP CKE D/A P S R/W UA BF 50
Legend: Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary 
oscillator modes. When disabled, these bits read as ‘0’.

PIC18F2423/2523/4423/4523

17.4 I2C Mode

The MSSP module in I2C mode fully implements all

master and slave functions (including general call

support) and provides interrupts on Start and Stop bits

in hardware to determine a free bus (multi-master

function). The MSSP module implements the standard

mode specifications as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer:

• Serial clock (SCL) – RC3/SCK/SCL

• Serial data (SDA) – RC4/SDI/SDA

The user must configure these pins as inputs or outputs

through the TRISC<4:3> bits.

FIGURE 17-7: MSSP BLOCK DIAGRAM

(I2C™ MODE)

17.4.1 REGISTERS

The MSSP module has six registers for I2C operation.

These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

• MSSP Address Register (SSPADD)

SSPCON1, SSPCON2 and SSPSTAT are the control

and status registers in I2C mode operation. The

SSPCON1 and SSPCON2 registers are readable and

writa bl e. Th e l ower 6 b it s o f t he SSPS TAT are re ad -o nl y.

The up per tw o b its of th e SSPSTAT are rea d/ writ e.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

SSPADD re gister holds the slave device address when

the MSSP is configured in I2C Slave mode. When the

MSSP is configured in Master mode, the lower seven

bits of SSPADD act as the Baud Rate Generator reload

value.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buff ered. A write to SSPBUF will write to bo th SSPBUF

and SSPSR.

Read Write

SSPSR reg

Match Detect

SSPADD reg

SSPBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

Shift

Clock

MSb LSb

Note: Only port I/O names are used in this diagram fo r

the sake of brevity. Refer to the text for a full list

of multiplexed functions.

SCL

SDA

Start and

Stop bit Detect

Address Mask

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A P(1) S(1) R/W(2,3) UA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6 CKE: SMBus Select bit

In Master or Slave mode:

1 = Enable SMBus specific inputs

0 = Disable SMBus specific inputs

bit 5 D/A: Data/Addre ss bit

In Master mode:

Reserved.

In Slave mode:

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit(1)

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

bit 3 S: Start bit(1)

1 = Indicates that a Start bit has been detected last

0 = Start bit was not detected last

bit 2 R/W: Read/Write Inform ation bit(2,3)

In Slave mode:

1 = Read

0 = Write

In Master mode:

1 = Transmit is in progress

0 = Transmit is not in progress

bit 1 UA: Update Address bit (10-Bit Slave mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

In Transmit mode:

1 = SSPBUF is full

0 = SSPBUF is empty

In Receive mode:

1 = SSPBUF is full (does not include the ACK and Stop bits)

0 = SSPBUF is empty (does not include the ACK and Stop bits)

Note 1: This bit is cleared on Reset and when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

In Master Transmit mode:

1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a

transmission to be started (must be cleared in software)

0 = No collision

In Slave Transmit mode:

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0 = No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6 SSPOV: Receive Overflow Indicator bit

In Receive mode:

1 = A byte is rec eived while t he SSPBUF re gister is still holdi ng the previo us by te (must be cle ared i n

software)

0 = No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mo de.

bit 5 SSPEN: Master Synchronous Serial Port Enable bit

1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins(1)

0 = Disables serial port and configures these pins as I/O port pins(1)

bit 4 CKP: SCK Release Control bit

In Slave mode:

1 = Release clock

0 = Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode .

bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1011 = I2C Firmware Controlled Master mode (slave Idle)

1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))

0111 = I2C Slave mode, 10-bit address

0110 = I2C Slave mode, 7-bit address

Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ACKDT/

ADMSK5 ACKEN(1)/

ADMSK4 RCEN(1)/

ADMSK3 PEN(1)/

ADMSK2 RSEN(1)/

ADMSK1 SEN(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General C all Enable bit (Slave mo de only)

1 = Enable interrupt when a general call address (0000h) is received in the SSPSR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1 = Acknowledge was not received from slave

0 = Acknowledg e was received from slave

bit 5 ACKDT/ADMSK5: Acknowle dge Data bi t

In Master Receive mode:(2)

1 = Not Acknowledge

0 = Acknowledge

In Slave mode:

1 = Address masking of ADD5 enabled

0 = Address masking of ADD5 disabled

bit 4 ACKEN/ADMSK4: Acknowledge Sequence Enable bit

In Master Receive mode:(1)

1 = Initiate Acknowledge sequence on SDA and SCL pins and transm it ACKDT data bi t. Automatically

cleared by hardware.

0 = Acknowledge sequence Idle

In Slave mode:

1 = Address masking of ADD4 enabled

0 = Address masking of ADD4 disabled

bit 3 RCEN/ADMSK3: Receive Enable bit

In Master Receive mode:(1)

1 = Enables Receive mode for I2C

0 = Receive Idle

In Slave mode:

1 = Address masking of ADD3 enabled

0 = Address masking of ADD3 disabled

bit 2 PEN/ADMSK2: Stop Condition Enable bit

In Master mode:(1)

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition Idle

In Slave mode:

1 = Address masking of ADD2 enabled

0 = Address masking of ADD2 disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is active, these bits may not be set (no

spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

PIC18F2423/2523/4423/4523

bit 1 RSEN/ADMSK1: Repeate d Start Conditi on Enab le bit

In Master mode:(1)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repeated Start c ondition Idle

In Slave mode (7-Bit Address mode):

1 = Address masking of ADD1 enabled

0 = Address masking of ADD1 disabled

In Slave mode (10-Bit Address mode):

1 = Address masking of ADD1 and ADD0 enabled

0 = Address masking of ADD1 and ADD0 disabled

bit 0 SEN: Start Condition Enable/Stretch Enable bit(1)

In Master mode:

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition Idle

In Slave mode:

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADD<7:0>: MSSP Address bits

Note 1: MSSP Address register in I2C™ Slave mode. MSSP Baud Rate register in I2C Master mode.

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is active, these bits may not be set (no

spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

PIC18F2423/2523/4423/4523

17.4.2 OPERATION

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON<5>).

The SSPCON1 register allows control of the I2C

operation. Four mode selection bits (SSPCON<3:0>)

allow one of the following I2C modes to be selected:

•I

2C Master m ode, clock = (FOSC/4) x (SSP ADD + 1)

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

•I

2C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

•I

2C Firmware Controlled Master mode, slave is

Idle

Selection of any I2C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain,

provided these pins are programmed to inputs by

setting the appropriate TRISC bits. To ensure proper

operation of the module, pull-up resistors must be

provided externally to the SCL and SDA pins.

17.4.3 SLAVE MODE

In Slave mod e, the SCL and SDA pins mu st be co nfi g-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (sl ave-tra nsmit ter).

The I2C Sl av e mod e hardwa re wi ll alw a ys ge nera te a n

interrupt on an address match. Address masking will

allow the hardware to generate an interrupt for more

than one address (up to 31 in 7-bit addressing and up

to 63 in 10-bit addressing). Through the mode select

bits, the user can also choose to interrupt on Start and

Stop bits.

When an add ress is match ed, or the d at a trans fer after

an add res s mat ch i s rece ived , th e ha rdw are au tom ati -

cally will generate the Acknowledge (ACK) pulse and

load the SSPBUF register with the received value

currently in the SSPSR register.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

• The Buffer Full bit, BF (SSPSTAT<0>), was set

before the transfer was received.

• The overflow bit, SSPOV (SSPCON1<6>), was

set before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The

BF bit is cleared by reading the SSPBUF register , while

bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and

low fo r pro per op erati on. The h igh an d low times of the

I2C specification, as well as the requirement of the

MSSP module, are sh own in timing para meter 100 and

parameter 101.

17.4.3.1 Addressing

Once the MSSP module has been enabled, it waits for

a S t art conditio n to occur. Follow ing the S t art condi tion,

the 8 bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1 > is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

1. The SSPSR register value is loaded into the

SSPBUF register.

2. The Buffer Full bit, BF, is set.

3. An ACK pulse is generated.

4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is

set (interrupt is generated, if enabled) on the

falling edge of the ninth SCL pulse.

In 10-Bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPST A T<2>) must specify a write so

the slave device will receive the second address byte.

For a 10-bit address, the first byte would equal ‘11110

A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the

address. The sequence of events for 10-bit address is as

follows, with step s 7 through 9 for the slav e-transmitter:

1. Receive first (high) byte of address (bits SSPIF,

BF and UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

5. Update t he SSPADD registe r with the first (high)

byte of a ddre ss . If m at ch rel ea ses SCL lin e, thi s

will clea r bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

7. Receive Repeated Start condition.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

PIC18F2423/2523/4423/4523

17.4.3.2 Address Masking

Masking an address bit causes that bit to become a

“don’t care”. When one address bit is masked, two

addresses will be Acknowledged and cause an

interrupt. It is possible to mask more than one address

bit at a time, wh ich mak es it pos sible to Ac knowled ge

up to 31 addresses in 7-bit mode and up to

63 addresses in 10-bit mode (see Example 17-2).

The I2C s lave b ehave s the s ame w ay whe ther address

masking is used or not. However, when address

masking is used, the I2C slave can Acknowledge

multiple addresses and cause interrupts. When this

occurs, it is necessary to determine which address

caused the interrupt by checking SSPBUF.

• 7-Bit Address mode

Address mask bits, ADMSK<5:1>, mask the

corresponding address bits in the SSPADD

(ADMSK<n> = 1), the corresponding address bit

is ig nore d (AD D<n > = x). For the module to issue

an address Acknowledge, it is sufficient to match

only on addresses that do not have an active

address mask.

• 1 0-Bit Address mode

Address mask bits, ADMSK<5:2>, mask the

corresponding address bits in the SSP ADD register .

In addition, ADMSK<1> simultaneously masks the

two LSBs of the address, ADD<1:0>. For any

ADMSK bits that are active (ADMSK<n> = 1), the

corresponding address bit is ignored (ADD<n> = x).

Also note that although in 10-Bit Addressing mode

the upper address bits reuse part of the SSPADD

with those bits. They only affect the lower address

bits.

EXAMPLE 17-2: ADDRE SS MASKI NG

Note 1: ADMSK<1> masks the two Least

Significant bits of the address.

2: The two Most Significant bits of the

address are not affected by address

masking.

7-bit addressing:

SSPxADD<7:1> = 1010 0000

ADMSK<5:1> = 00 111

Addresses Acknowledged = 0xA0, 0xA2, 0xA4, 0xA6

0xA8, 0xAA, 0xAC, 0xAE

10-bit addressing:

SSPxADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not af fected.)

ADMSK<5:1> = 00 111

Addresses Acknowledged = 0xA0, 0xA1, 0xA2, 0xA3

0xA4, 0xA5, 0xA6, 0xA7

0xA8, 0xA9, 0xAA 0xAB

0xAC, 0xAD, 0xAE, 0xAF

The upper two bits are not affected by the address masking.

PIC18F2423/2523/4423/4523

17.4.3.3 Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register and the SDA line is held low

(ACK).

When the address byte overflow condition exists, then

the no Ack no w led ge (ACK ) pul se is g iv en. An ov erfl ow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF (PIR1<3>), must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL

will be held low (clock stretch) following each data

transfer. The clock must be released by setting bit,

CKP (SSPCON1<4>). See Section 17.4.4 “Clock

Stretching” for more detail.

17.4.3.4 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low regardless of SEN (see Section 17.4.4 “Clock

Stretching” for more detail). By stretching the clock,

the master will be unable to assert another clock pulse

until the s lav e is don e preparing the transm it da t a. Th e

transmit data mus t be loaded i nto the SSPBUF reg ister

which also loads the SSPSR register. Then pin RC3/

SCK/SCL should be enabled by setting bit, CKP

(SSPCON1<4>). The eight data bits are shifted out on

the falli ng ed ge of the SC L inp ut. This en sure s th at the

SDA signal is valid during the SCL high time

(Figure 17-10).

The ACK pulse from the master-receiver is latched on

the rising edge of the nin th SCL input pu lse. If the SDA

line is high (not ACK), then the data transfer is com-

plete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT regis-

ter) and the slave monitors for another occurrence of

the Start bit. If the SDA line was low (ACK), the next

transmit data must be loa ded into the SSPBUF regi ster .

Again, pin RC3/SCK/SCL must be enabled by setting

bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

PIC18F2423/2523/4423/4523

FIGURE 17-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S12345678912345678912345 789 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP (CKP does not reset to ‘0’ when SE N = 0)

PIC18F2423/2523/4423/4523

FIGURE 17-9: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011

(RECEPTION, 7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S12345678912345678912345 789 P

A7 A6 A5 X A3 X X D7D6D5D4D3D2D1D0 D7D6D5D4D3 D1D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP (CKP does not reset to ‘0’ when SEN = 0)

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.

PIC18F2423/2523/4423/4523

FIGURE 17-10 : I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9

SSPBUF is w ritten in software

Cleared in software From SSPIF ISR

Data in

sampled

ACK

Transmitting Data

R/W = 0

ACK

Receiving Address

A7 D7

D6 D5 D4 D3 D2 D1 D0

2 3 4 5 6 7 8 9

SSP BUF is writte n in s o ft w a r e

Cleared in software From SSPIF ISR

Transmitting Data

CKP

ACK

CK P is s e t in so f tw a re CKP is s e t in so f tw a r e

SCL held low

while CPU

responds to SSPIF

PIC18F2423/2523/4423/4523

FIGURE 17-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001

(RECEPTION, 10-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9 A8 A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware

when SSPADD is updated

with low byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(CKP does not reset to ‘0’ when SEN = 0)

Clock is held low until

update of SSPADD has

taken place

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be acknowledged and cause an interrupt.

3: Note that the Most Significant bits of the address are note affected by the bit masking.

PIC18F2423/2523/4423/4523

FIGURE 17-12 : I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware

when SSPADD is updated

with low byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(CKP does not reset to ‘0’ when SEN = 0)

Clock is held low until

update of SSPADD has

taken place

PIC18F2423/2523/4423/4523

FIGURE 17-13 : I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8

R/W=1

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Bus master

terminates

transfer

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated with low

byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address.

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

Receive First Byte of Address

12345 789

D7 D6 D5 D4 D3 D1

ACK

Tran smitting Data Byte

Dummy read of SSPBUF

to clear BF flag

Cleared in software

Write of SSPBUF

initiates transmit

Cleared in software

Completion of

clears BF flag

CKP (SSPCON1<4>)

CKP is set in software

CKP is automatically cleared in hardware, holding SCL low

Clock is held low until

update of SSPADD has

taken place

data transmission

Clock is held low until

CKP is set to ‘1’

third address sequence

BF flag is clear

at the end of the

PIC18F2423/2523/4423/4523

17.4.4 CLOCK STRETCHING

Both 7-Bit and 10-Bit Slave modes implement

automatic cl oc k s tre tch ing during a transm it sequence.

The SEN bit (SSPCON2<0>) al lows clock stretch ing to

be enabled during receives. Setting SEN will cause

the SCL pin to be held low at the end of each data

receive sequence.

17.4.4.1 Clock Stretching for 7-Bit Slave

Receive Mode (SEN = 1)

In 7-Bit Slave R ecei ve m od e, on the fall ing edg e of the

ninth clock at the end of the ACK sequence if the BF

bit is set, the CKP bit in the SSPCON1 register is

automatically cleared, forcing the SCL output to be

held low. The CKP being cleared to ‘0’ will assert the

SCL line low. The CKP bit must be set in the user’s

ISR befo re recep tion i s allo wed to co ntinue . By hol ding

the SCL line low, the user has time to service the ISR

and read the contents of the SSPBUF before the

master device can initiate another receive sequence.

This will prevent buffer overruns from occurring (see

Figure 17-15).

17.4.4.2 Clock Stretching for 10-Bit Slave

Receive Mode (SEN = 1)

In 10-Bit Slave Receive mode during the address

sequence, clock stretching automatically takes place

but CKP is not c lea red . Duri ng t his time, if th e UA b it i s

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

17.4.4.3 Clock Stretching for 7-Bit Slave

Transmit Mode

7-Bit Slave Transmit mode implements clock stretch-

ing by clearing the CKP bit after the falling edge of the

ninth clock if the BF bit is clear. This occurs regardless

of the state of the SEN bit.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line

low, the user has time to service the ISR and load the

contents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 17-10).

17.4.4.4 Clock Stretching for 10-Bit Slave

Transmit Mode

In 10-Bit Slave Transmit mode, clock stretching is con-

trolled during the first two address sequences by the

state of the UA bit, just as it is in 10-Bit Slave Receive

mode. The first two addresses are followed by a third

address sequence which contains the high-order bits

of the 10-bit address and the R/W bit set to ‘1’. After

the third address sequence is performed, the UA bit is

not set, the module is now configured in Transmit

mode and clock stretching is controlled by the BF flag

as in 7-Bit Slave Transmit mode (see Figure 17-13).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

Note: If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ni nth c lock oc curs and i f

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a

data sequence, not an address sequence.

Note 1: If the user lo ads t he co nten t s of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit.

PIC18F2423/2523/4423/4523

17.4.4.5 Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCL output low until the SCL output is already sam-

pled low. Therefore, the CKP bit will not assert the

SCL line until an external I2C master device has

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I2C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 17-14).

FIGURE 17-14: CLOCK SYNCHRONIZATION TIMING

SDA

SCL

DX – 1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCONx

CKP

Master device

deasserts clock

Master device

asserts clock

PIC18F2423/2523/4423/4523

FIGURE 17-15 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S123456789 1 234567 89 12345 789 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP

written

to ‘1’ in

If BF is cleared

prior to the falling

edge of the 9th clock,

CKP will not be reset

to ‘0’ and no clock

stretching will occur

software

Clock is held low until

CKP is set to ‘1’

Clock is not held low

because buffer full bit is

clear prior to falling edge

of 9th clock Clock is not held low

because ACK =

BF is set after falling

edge of the 9th clock,

CKP is reset to ‘0’ and

clock stretching occurs

PIC18F2423/2523/4423/4523

FIGURE 17-16 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated with low

byte of address after falling edge

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address after falling edge

SSPBUF is writ ten with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

CKP written to

‘

’

Note: An update of th e SS PADD registe r b efore

the falling edge of the ninth clock will have

no effect on UA and UA will remain set.

Note: An update of the SSPADD

edge of the ninth clock will

have no effect on UA and

UA will remain set. in software

Clock is held low until

update of SSPADD has

taken place

of ninth clock

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

Dummy read of SSPBUF

to clear BF flag

Clock is held low until

CKP is set to

‘

’

Clock is not held low

because ACK =

PIC18F2423/2523/4423/4523

17.4.5 GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master. The exception is the general call address

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the Gen-

eral Call Enable bit, GCEN, is enabled (SSPCON2<7>

is set). Following a S tart bit detect, 8 bits are sh ifted into

the SSPSR and the address is compared against the

SSPADD. It is also compared to the general call

address and fixed in hardware.

If the general call address matches, the SSPSR is

transferre d to the S SPBUF, the BF f lag bit is set (eighth

bit) and on the falling edg e of the ninth bit (ACK b it), the

SSPIF interrupt flag bit is set.

When the interrupt is serviced, the source for the

interr upt can be checke d by reading t he cont ents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the seco nd half of the address to match an d the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-Bit Address mode, then the second

half of the address is not necessary, the UA bit will not

be set and the slave will begin receiving data after the

Acknowledge (Figure 17-17).

FIGURE 17-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

SDA

SCL S

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

Cleared in software

SSPBUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

GCEN (SSPCON2<7>)

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set inter rupt

‘0’

‘1’

PIC18F2423/2523/4423/4523

17.4.6 MASTER MODE

Master mode is enabled by setting and clearing the

appropria te SSPM bit s in SSPCON1 and by set ting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions . The S t op (P) a nd St art (S) bi ts are clea red fro m

a Reset o r when the MSSP m odule is di sabled. Co ntrol

of the I2C bus ma y be tak en when the P bit is set, or the

bus is Idle, with both the S and P bits clear.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit conditions.

Once Master mode is enabled, the user has six

options.

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configure the I2C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDA and SCL.

The following events will cause the MSSP Interrupt

Flag bit, SSPIF, to be set (MSSP interrupt, if enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

FIGURE 17-18: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)

Note: The MSSP module, when configured in

I2C Mast er mode, does n ot allow que ueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission befo re the S tart condi-

tion is complet e. In th is case , the SSPBUF

will not be w ri tten to an d the WCOL bi t wi ll

be set, indicating that a write to the

SSPBUF did not occur.

Read Write

SSPSR

Start bit, Stop bit,

SSPBUF

Internal

Data Bus

Set/ Re set S, P, WCO L (SSPSTAT, SSPC O N 1)

Shift

Clock

MSb LSb

SDA

Acknowledge

Generate

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL

SCL In

Bus Collision

SDA In

Receive Enable

Clock Cntl

Clock Arbitrate/WCOL Detect

(hold off clock source)

SSPADD<6:0>

Baud

Set SS PIF, BC LIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM3:SSPM0

Start bit Detect

PIC18F2423/2523/4423/4523

17.4.6.1 I2C Master Mode Operation

The master device generates all of the serial clock

pulses and the S t a rt and Stop con dition s. A transfer i s

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer , the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/W) bit.

In this case, the R/W bit w ill be logic ‘ 0’. Ser ial d ata is

transmi tted 8 b it s at a ti me . Afte r each by te i s t rans m it-

ted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Rec eive mode, t he first byte transm itted con-

tains the slave address of the transmitting device

(7 bits) and th e R/W bit. In this case, the R/W bit w ill b e

logic ‘ 1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Ser ial dat a is received 8 bits at a time. After

each byte is received, an Acknowledge bit is transmit-

ted. Start and Stop conditions indicate the beginning

and end of transmission.

The Baud Rate Generator used for the SPI mode

operation is used to set the SCL clock frequency for

either 100 kHz, 400 kHz or 1 MHz I2C operation. See

Section 17.4.7 “Baud Rate” for more detail.

A typical transmit sequence would go as follows:

1. The user generates a Start condition by setting

the Start Enable bit, SEN (SSPCON2<0>).

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

4. Address is shi fted out the SDA pin unt il all 8 bit s

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

6. The MSSP mo dule g enerate s an interrup t at th e

end of th e ninth c lock cyc le by settin g the SSPIF

bit.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is sh ifted ou t the SDA pin until all 8 bit s are

transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP mo dule gene rates an int errupt a t the

end of th e ninth c lock cyc le by settin g the SSPIF

bit.

11. The user generates a Stop condition by setting

the Stop Enable bit, PEN (SSPCON2<2>).

12. Interrupt is ge nerat ed once the Stop conditi on is

complete.

PIC18F2423/2523/4423/4523

17.4.7 BAUD RATE

In I2C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 17-19). When a write occurs

to SSPBUF, the Baud Rate Generator will automaticall y

begin counting. The BRG counts down to 0 and stops

until an other re load h as t aken pl ace. Th e BRG c ount i s

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I2C Master mode, the BRG is

reloaded automatically.

Once the given operation is complete (i.e., transmis-

sion of th e last dat a bit is followed by ACK), the int ernal

clock will automatically stop counting and the SCL pin

will rema in in it s last state.

Table 17-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 17-19: BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 17-3: I2C™ CLOCK RATE W/BRG

SSPM3:SSPM0

BRG Down Counter

CLKO FOSC/4

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control Reload

FCY FCY * 2 BRG Value FSCL

(2 Rollovers of BRG)

10 MHz 20 MHz 18h 400 kHz(1)

10 MHz 20 MHz 1Fh 312.5 kHz

10 MHz 20 MHz 63h 100 kHz

4 MHz 8 MHz 09h 400 kHz(1)

4 MHz 8 MHz 0Ch 308 kHz

4 MHz 8 MHz 27h 100 kHz

1 MHz 2 MHz 02h 333 kHz(1)

1 MHz 2 MHz 09h 100 kHz

1 MHz 2 MHz 00h 1 MHz(1)

Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

PIC18F2423/2523/4423/4523

17.4.7.1 Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 17-20).

FIGURE 17-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

SCL

SCL deasserted but slave holds

DX – 1DX

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCL low (clock arbitration) SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

PIC18F2423/2523/4423/4523

17.4.8 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN (SSPCON2<0>). If the SDA and SCL

pins are sampled high, the Baud Rate Generator is

reloaded with the cont ent s of SSPADD<6 :0> and st arts

its count. If SC L and SDA are both sampled hig h whe n

the Baud Rate Generator times out (TBRG), the SDA

pin is driven low. The action of the SDA being driven

low whil e SC L is hig h is the Sta rt condition and cause s

the S bit (SSPSTAT<3>) to be set. Following this, the

Baud Rate Generator is reloaded with the contents of

SSPADD<6:0> and resumes it s cou nt. When the Baud

Rate Generator times out (TBRG), the SEN bit

(SSPCON2<0>) will be automatically cleared by

hardware; the Baud Rate Generator is suspended,

leavin g th e SD A l in e h eld lo w and th e Start conditio n i s

complete.

17.4.8.1 WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL is s et an d the co ntents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 17-21: FIRST START BIT TIMING

Note: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low , or if during the S tart condition, the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs,

the Bus Collision Interrupt Flag, BCLIF, is

set, the Start condition is aborted and the

I2C module is reset into its Idle state.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the Start

conditi on is complete.

SDA

SCL

TBRG

1st bit 2nd bit

TBRG

SDA = 1, At completion of Start bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSPSTAT<3>)

and sets SSPIF bit

PIC18F2423/2523/4423/4523

17.4.9 I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

(SSPCON2<1>) is programmed high and the I2C logic

module is in the Idle state. When the RSEN bit is set,

the SCL pin is asserted lo w. When the SCL pin is sam-

pled low, the Baud Rate Generator is loaded with the

contents of SSPADD<5:0> and begins counting. The

SDA pin is released (brought high) for one Baud Rate

Generator coun t (TBRG). When th e Baud Rate Gene ra-

tor times out, if SDA is sampled high, the SCL pin will

be deasserted (brought high). When SCL is sampled

high, the Baud Rate Generator is reloaded with the

contents of SSPADD<6:0> and begins counting. SDA

and SCL must be sampled high for one TBRG. This

action is then followed by assertion of the SDA pin

(SDA = 0) for one TBRG while SCL is high. Following

this, the RSEN bit (SSPCON2<1>) will be automatically

cleared and the Baud Rate Generator will not be

reloaded, leaving the SDA pin held low. As soon as a

Start condition is detected on the SDA and SCL pins,

the S bit (SSPSTAT<3>) will be set. The SSPIF bit will

not be set until the Baud Rate Gene rator has timed out.

Immediately following the SSPIF bit getting set, the user

may write the SSPBUF with the 7-bit address in 7-bit

mode or the default first address in 10-bit mode. After the

first eight bits are transmitted and an ACK is received,

the user may then transmit an additional eight bits of

address (10-bit mode) or eight bit s of dat a (7-bit mode).

17.4.9.1 WCOL Status Flag

If the user writes the SSPBUF when a Repeated Start

sequence is in progress, the WCOL is set and the

contents of the buf fer are un ch anged (th e write doesn ’t

occur).

FIGURE 17-22: REPEAT START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

conditi on occ urs if:

• SDA is samp led low whe n SCL goes

from low-to-hi gh.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

Start condition is complete.

SDA

SCL

Sr = Repeated Start

Write to SSPCON2

Writ e to SSPBUF occurs here

on falling edge of ninth c lock,

end of Xmit

At completion of Start bit,

hardw are clea rs R SEN bi t

1st bit

S bit set by hardware

TBRG

SDA = 1,

SCL (no change). SCL = 1

occurs here.

TBRG TBRG TBRG

and sets SSPIF

RSEN bit set by hardware

PIC18F2423/2523/4423/4523

17.4.10 I2C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address, is accomplished by sim-

ply writing a value to the SSPBUF register. This action

will set the Buffer Full flag bit, BF and allow the Baud

Rate Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification

parameter 106). SCL is held low for one Baud Rate

Generator rollover count (TBRG). Data should be valid

befor e SCL is rele ased high (see data setup time spec-

ificati on par ameter 107). When the SCL pin is release d

high, it is held that way for TBRG. The data on the SDA

pin must rem ain st able f or that duratio n and some hol d

time after the next falli ng ed ge of SCL. After the eigh th

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit d uring the nin th bi t time if an

addr es s m at c h oc cur r ed, o r if d a ta wa s rec ei v ed p r op-

erly . The status of ACK is written i nto th e ACKDT bit on

the falli ng edge of the ninth clock. If the master receive s

an Acknowledge, the Acknowledge Status bit,

ACKSTA T, is cl eared. If not, the bit is set. After the ninth

clock, the SSPIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 17-23).

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

deassert the SDA pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

cloc k, the mast er wil l sam ple the SDA pin to see if t he

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT status bit

(SSPCON2<6>). Followi ng the falling edg e of the ninth

clock transmission of the address, the SSPIF is set, the

BF flag is cleared and the Baud Rate Generator is

turned off until another write to the SSPBUF takes

place, holding SCL low and allowing SDA to float.

17.4.10.1 BF S tatus Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all 8 bits are shifted out.

17.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

17.4.10.3 ACKSTAT Status Flag

In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK =0) and is set when the slav e does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data .

17.4.11 I2C MASTER MODE RECEPTION

Master mode recepti on is enabl ed by progra mmin g the

Receive Enable bit, RCEN (SSPCON2<3>).

The Baud Rate Generator begins counting and on each

rollove r, the sta te of the SC L pin ch ang es (high -to-l ow /

low-to-high) and data is shifted into the SSPSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag bit is

set, the SSPIF flag bi t is set and the Baud Ra te Gener-

ator is s uspen ded from countin g, hold ing SC L low. The

MSSP is now in Idle state awaiting the next command.

When the buffer is read by the CPU, the BF flag bit is

automatically cleared. The user can then send an

Acknowledge bit at the end of reception by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>).

17.4.11.1 BF Status Flag

In receiv e op eration, the BF bit is set w he n an add res s

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

17.4.11.2 SSPOV S tatus Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a p revious reception.

17.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e ., SSPSR is still shifting in a data

byte), th e WCOL bi t is set an d the conte nts of th e buffer

are unchanged (the write doesn’t occur).

Note: The MSSP module must be in an Idle state

before the RCEN bit is set or the RCEN bit

will be disregarded.

PIC18F2423/2523/4423/4523

FIGURE 17-23 : I2C™ MASTER MODE W AVEFORM (T RANSMISSION, 7 OR 10-BIT ADDRESS)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared in software service routine

SSPBUF is written in software

from MSSP interrupt

After Start condition, SEN cleared by hardware

SSPBUF written with 7-bit address and R/W

start transmit

SCL held low

while CPU

responds to SSPIF

SEN = 0

of 10-bit Address

Write SEN (SSPCON2<0>) = 1

Start condition begins From slave, clear ACKSTAT bit (SSPCON2<6>)

ACKSTAT in

SSPCON2 = 1

Cleared in softwar e

SSPBUF written

PEN

R/W

Cleared in software

PIC18F2423/2523/4423/4523

FIGURE 17-24 : I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 12345678912345678 9 1234

Bus master

terminates

transfer

ACK Receiving Data from Slave

Receiving Data from Slave D0

D3D4

D6D7

ACK

R/W = 0

Transmit Address to Slave

SSPIF

ACK is not sent

Write to SEN (SSPCON2<0>) = 1,

Write to SSPBUF occurs here, ACK from Sla ve

Master configured as a receiver

by programming SSPCON2<3> (RCEN = 1)PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared in software

start XMIT

SEN = 0

SSPOV

SDA = 0, SCL = 1

while CPU

(SSPSTAT<0>)

ACK

Cleared in software

Set SSPIF interrupt

at end of receive

Set P bit

(SSPSTAT<4>)

and SSPIF

Cleared in

software

ACK from Master

Set SS PIF at end

Set SSPIF interrupt

at end of Acknowledge

sequence

Set SSPIF interrupt

at end of Acknow-

ledge sequence

of receive

Set ACKEN, start Acknowledge sequence

SDA = ACK DT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSPCON2<4>

to start Acknowledge sequence

SDA = ACKDT (SSPCON2<5>) = 0

RCEN cleared

automatically

responds to SSPIF

ACKEN

begin Start condition

Cleared in software

SDA = ACKDT = 0

Last bit is shifted into SSPSR and

contents are unloaded into SSPBUF

SSPOV is set because

SSPBUF is still full

PIC18F2423/2523/4423/4523

17.4.12 ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the use r wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low . Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into Idle mode (Figure 17-25).

17.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buf fer are un chang ed (the w rite doe sn’t

occur).

17.4.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN (SSPCON2<2>). At the end of a receive/

transmit, the SCL line is held low after the falling edge

of the ninth clock. When the PEN bit is set, the master

will assert th e SDA line low. When the SDA line is s am-

pled low, the Baud Rate Generator is reloaded and

counts down to ‘0’. When the Baud Rate Generator

times out, the SCL pin will be brought high and one

TBRG (Baud Rate Generator rollover count) later, the

SDA pin will be deass erted. Wh en the SDA pin is sam-

pled hi gh whil e SCL is high, the P bit (SSPSTAT<4>) is

set. A TBRG later, the PEN bit is cleared and the SSPIF

bit is set (Figure 17-26).

17.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 17-25: ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 17-26: STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

SSPI F set at

Acknowledge sequence starts here,

write to SSPCON2 ACKEN automatically cleared

Cleared in

TBRG TBRG

the end of receive

ACKEN = 1, ACKDT = 0

SSPIF

software SSPIF set at the end

of Acknowledge sequence

Cleared in

software

ACK

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2,

set PEN

Falling edg e of

SCL = 1 for TBRG, followed by SDA = 1 fo r TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

TBRG

to setup Stop condition

ACK

TBRG

PEN bit (SSPCON2<2>) is clea red by

hardw ar e and the SSPIF bit is set

PIC18F2423/2523/4423/4523

17.4.14 SLEEP OPERATION

While in Sleep mode, the I2C module can receive

address es or data and when an a ddress match or com-

plete byte transfer occurs, wake the processor from

Sleep (if the MSSP interrupt is enabled).

17.4.15 EFFECTS OF A RESET

A Reset disable s the MSSP module and terminates the

current transfer.

17.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

deter mination of when the bus i s free. The S top (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I2C bus may

be taken when the P bit (SSPSTAT<4>) is set, or the

bus is Idle, with both the S and P bits clear. When the

bus is busy, enabling the MSSP interrupt will generate

the interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed in

hardware with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address T rans fe r

• Data Transfer

• A Start Co ndition

• A Repeated Start Condition

• An Acknowledge Condition

17.4.17 MULTI -MASTER COMMUNIC A T ION,

BUS COLLI SION AND BU S

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ an d the da t a s am ple d on th e SDA pin = 0,

then a bus collision has taken place. Th e master will set

the Bus Collision Interrupt Flag, BCLIF and reset the

I2C port to its Idle state (Figure 17-27).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are dea sserted and the

SSPBUF can b e written to . When the us er servic es th e

bus collision Interrupt Service Routine and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condi-

tion was in progress when the bus collision occurred, the

condition is aborted, the SDA and SCL lines are deas-

serted and the respective control bits in the SSPCON2

lision Interrupt Service Routine and if the I2C bus is free,

the user can res ume communication by asserting a S tart

condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detectio n of Start a nd Stop c ond iti ons al low s the deter-

minatio n of when t he b us is free. C ontro l of the I2C bus

can be taken when the P bit is set in the SSPSTAT

cleared.

FIGURE 17-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data doesn’t match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCLIF)

by the master.

by master

Data changes

while SCL = 0

PIC18F2423/2523/4423/4523

17.4.17.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the begi nning of

the Start condition (Figure 17-28).

b) SCL is sam pl ed l ow before SD A is as se rted low

(Figure 17-29).

During a Start condition, both the SDA and the SCL

pins are monitored.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted ,

• the BCLIF flag is set and

• the MSSP module is reset to its Idle state

(Figure 17-28).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded from SSPADD<6:0>

and counts down to 0. If the SCL pin is sampled low

while SDA is high, a bus collision occurs because it is

assumed that another master is attempting to drive a

data ‘1’ during the Start condition.

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 17-30). If, however , a ‘1’ is sampled on the SDA

pin, the S DA pin is asserted low at th e end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to 0; if the SCL pin is sampled as ‘0’

duri ng this time , a bus colli sion does not oc cur. At the

end of t he BRG co unt , the SCL pin is a sserted low.

FIGURE 17-28: BUS COLLISION DURING START CONDITION (SDA ONLY)

Note: The reason that bus collisio n is not a factor

duri ng a Start cond itio n is t hat no t wo bus

masters can assert a St art condition at the

exact same time. Therefore, one master

will always assert SDA before the other.

This condition does not cause a bus colli-

sion because the two masters must be

allowed to arbitrate the first address fol-

lowin g the S t art conditi on. If the addres s is

the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

SDA

SCL

SEN SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSPIF set because

MSSP module reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSPIF set because

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCLIF

SSPIF

SDA = 0, SCL = 1.

SSPIF and BCLIF are

cleared in software

SSPIF and BCLIF are

cleared in software

Set BCLIF,

S tart condition. Set BCLIF.

PIC18F2423/2523/4423/4523

FIGURE 17-29: BUS COLLISION DURING START CONDITION (SCL = 0)

FIGURE 17-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SCL

SEN bus collision occurs. Set BCLIF.

SCL = 0 before SDA = 0,

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupt cleared

in software

bus collision occurs. Set BCLIF.

SCL = 0 before BRG time-out,

‘0’‘0’

SDA

SCL

SEN

Set S

Less th an TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupts cleared

in software

set SS PIF

SDA = 0, SCL = 1,

SCL pulled low after BRG

time-out

Set SS PIF

‘0’

SDA pulled low by other master .

Reset BRG and assert SDA.

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

PIC18F2423/2523/4423/4523

17.4.17.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occu rs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user dea sserts SDA and the pin is a llowed to

float high, the BRG is loaded with SSPADD<6:0> and

counts down to 0. The SCL pin is then deasserted and

when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 17-31).

If SDA is sampled high, the BRG is relo aded and begins

counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exac tly the sam e time.

If SCL goes from high-to-low before the BRG times out

and SDA has not al ready been asserted, a bus collision

occurs. In this case, another master is attempting to

transmi t a data ‘1’ during the R e pea ted Start condition,

see Figure 17-32.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 17-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 17-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCLIF

SSPIF

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

Cleared in software

‘0’

SDA

SCL

BCLIF

RSEN

SSPIF

Interrupt cleared

in software

SCL goes low before SDA,

set BCLIF. Release SDA and SCL.

TBRG TBRG

‘0’

PIC18F2423/2523/4423/4523

17.4.17.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),

the Baud R ate Generator is loaded w ith SSP AD D<6:0>

and count s dow n to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 17-33). If the SCL pin is

sample d lo w befo re SD A is allowed to flo at hi gh, a bus

collis ion occ urs. This is anoth er case of anot her m aster

attempting to drive a data ‘0’ (Figure 17-34).

FIGURE 17-33: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 17-34: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

SDA asserted low

SDA sampled

low after TBRG,

set BCLIF

‘0’

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

Assert SDA SCL goes low before SDA goes high,

set BCLIF

‘0’

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

18.0 ENHANCED UNIVE RSA L

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is one of the

two serial I/ O modules. (G enerically, the USART is also

known as a Serial Communications Interface or SCI.)

The EUSART can be configured as a full-duplex

asynchronous system that can communicate with

peripheral devices, such as CRT terminals and

personal compute rs. It can also b e configured as a half-

duplex synchronous system that can communicate

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs, etc.

The Enhanced USART module implements additional

features, including automatic baud rate detection and

calibration, automatic wake-up on Sync Break recep-

tion and 12-bit B reak chara cter transmit. These ma ke it

ideally suited for us e in Local I nterconnect Ne twork bus

(LIN bus) systems.

The EUSART can be configured in the following

modes:

• Asynchronous (full duplex) with:

- Auto-wake-up on character reception

- Auto-baud calibration

- 12-bit Break ch arac ter tran sm is si on

• Synchronous – Master (half duplex) with

selectable clock polarity

• Synchronous – Slave (half duple x) with se lecta ble

clock polarity

The pins of the Enhanced USART are multiplexed

with PORTC. In order to configure RC6/TX/CK and

RC7/RX/DT as an EUSART:

• bit SPEN (RCSTA<7>) must be set (= 1)

• b it TRISC<7> must be set (= 1)

• bit TRISC<6> must be set (= 1)

The operation of the Enhanced USART module is

controlled through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These are detailed on the following pages in

respectively.

Note: The EUSART control will automatically

reconfigure the pin from input to output as

needed.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-Bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: EUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = Send Sync Break on next transmission (cleared by hardware upon completion)

0 = Sync Break transmission completed

Synchronous mode:

Don’t care.

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode .

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC18F2423/2523/4423/4523

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-Bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care.

Synchronous mode – Master:

1 = E nabl es single re ceive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care.

bit 4 CREN: Continuo us Receiv e Enab le bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enab le bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):

Don’t care.

bit 2 FERR: Framing Error bit

1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC18F2423/2523/4423/4523

R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit

1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)

0 = No BRG rollover has occurred

bit 6 RCIDL: Receive Operation Idle Status bit

1 = Receive operation is Idle

0 = Receive operation is active

bit 5 Unimplemented: Read as ‘0’

bit 4 SCKP: Synchronou s Clock Polarity Select bit

Asynchronous mode:

Unused in this mode .

Synchronous mode:

1 = Idle state for clock (CK) is a high le vel

0 = Idle state for clock (CK) is a low level

bit 3 BRG16: 16-Bit Baud Rate Register Enable bit

1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG

0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored

bit 2 Unimplemented: Read as ‘0’

bit 1 WUE: Wake-up Enable bit

Asynchronous mode:

1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in

hardware on following rising edge

0 = RX pin not monitored or rising edge detected

Synchronous mode:

Unused in this mode .

bit 0 ABDEN: Auto-Baud Dete ct Enab le bit

Asynchronous mode:

1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);

cleared in hardware upon completion.

0 = Baud rate measurement disabled or completed

Synchronous mode:

Unused in this mode .

PIC18F2423/2523/4423/4523

18.1 Baud Rate Generator (BRG)

The BRG is a dedicated 8-bit or 16-bit generator that

supports both the Asynchronous and Synchronous

modes of the EUSART. By default, the BRG operates

in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)

selects 16-bit mode.

The SPBRGH:SPBRG regi ste r p air co ntro ls the perio d

of a free-running timer. In Asynchronous mode, bits

BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also

control the baud rate. In Synchronous mode, BRGH is

ignored. Table 18-1 shows th e formula f or c om putation

of the baud rate for different EUSART modes which

only a pply i n Mas te r mode (int ernall y gen erated clock ).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH:SPBRG registers can be

calculated using the formulas in Table 18-1. From this,

the error in baud rate can be determined. An example

calculation is shown in Example 18-1. Typical baud

rates and error values for the various Asynchronous

modes are shown in Table 18-2. It may be advan-

tageous to use the high baud rate (BRGH = 1) or the

16-bit BRG to reduce the baud rate error, or achieve a

slow baud rate for a fast oscillator frequency.

Writing a new value to the SPBRGH:SPBRG registers

causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

18.1.1 OPERATI ON IN POWER-M AN AGED

MODES

The device clock is used to generate the desired baud

rate. When one of the power-managed modes is

entered, the new clock source may be operating at a

diffe rent frequency. This may require an adjustment to

the value in the SPBRG register pair.

18.1.2 SAMPLING

The data on the RX pin is sampled three times by a

majority detect circuit to determine if a high or a low

level is present at the RX pin.

TABLE 18-1: BAUD RATE FORMULAS

Configuration Bits BRG/EUSART Mode Baud Rate Formula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/[64 (n + 1)]

001 8-bit/Asynchronous FOSC/[16 (n + 1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous FOSC/[4 (n + 1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair

PIC18F2423/2523/4423/4523

EXAMPLE 18-1: CALCULATING BAUD RATE ERROR

TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

For a device wit h F OSC of 16 MHz, desire d baud rat e of 960 0, Asynchronous mode, 8-b it BRG:

Desired B aud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))

Solving for SPBRGH:SPBRG:

X=((FOSC/Desired Baud Rate)/64) – 1

= ((160 00000/9600 )/64) – 1

= [25.0 42] = 25

Calcu lated Baud Rate = 16000 000/(64 (25 + 1))

= 9615

Error = (Calculated Baud Rate – Desired Baud Rate )/ De sired Baud Rate

= (9615 – 9600) /9600 = 0.16%

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset V alues

on page

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 51

SPBRGH EUSART Baud Rate Generator Register High Byte 51

SPBRG EUSART Baud Rate Generator Register Low Byte 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

PIC18F2423/2523/4423/4523

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103

2.4 2.404 0.16 207 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51

9.6 9.615 0.16 51 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12

19.2 19.231 0.16 25 19.531 1.73 15 19.531 1.73 7 — — —

57.6 55.555 -3.55 8 62.500 8.51 4 52.083 -9.58 2 — — —

115.2 125.000 8.51 3 104.167 -9.58 2 78.125 -32.18 1 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51

1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12

2.4 2.404 0.16 25 2.403 -0.16 12 — — —

9.6 8.929 -6.99 6 — — — — — —

19.2 20.833 8.51 2 — — — — — —

57.6 62.500 8.51 0 — — — — — —

115.2 62.500 -45.75 0 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2————————————

2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207

9.6 9.615 0.16 207 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51

19.2 19.231 0.16 103 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25

57.6 57.143 -0.79 34 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8

115.2 117.647 2.12 16 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 — — — — — — 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51

2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25

9.6 9.615 0.16 25 9.615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

PIC18F2423/2523/4423/4523

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.01 6666 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665

1.2 1.200 -0.02 1666 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415

2.4 2.401 0.04 832 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207

9.6 9.615 0.16 207 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51

19.2 19.231 0.16 103 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25

57.6 57.142 -0.79 34 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8

115.2 117.647 2.12 16 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51

2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25

9.6 9.615 0.16 25 9.615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.00 26666 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665

1.2 1.200 0.00 6666 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665

2.4 2.400 0.01 3332 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832

9.6 9.603 0.04 832 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207

19.2 19.185 -0.07 416 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103

57.6 57.553 -0.07 138 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34

115.2 115.942 0.64 68 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832

1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207

2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103

9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25

19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12

57.6 58.824 2.12 16 55.555 3.55 8 — — —

115.2 111.111 -3.55 8 — — — — — —

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC18F2423/2523/4423/4523

18.1.3 AUTO-BAUD RATE DETECT

The Enhan ced USART module supports the automatic

detection and calibration of baud rate. This feature is

active only in Asynchronous mode and while the WUE

bit is clear.

The automatic baud rate measurement sequence

(Figure 18-1) begins whenever a Start bit is received

and the ABDEN bit is set. The calculation is

self-averaging.

In the Auto-Bau d Rate Detect (ABD) mode, the clock to

the BRG i s reversed. Rather than the BRG c locking the

incomi ng RX signal, the RX signal is tim ing the BRG. In

ABD mode, the internal Baud Rate Generator is used

as a coun ter to time the bit p eriod of the inco ming serial

byte stream.

Once the ABDEN bit is set, the state machine will clear

the BRG and look for a Start bit. The Auto-Baud Rate

Detect must receive a byte with the value 55h (ASCII

“U”, which is also the LIN bus Sync character) in order to

calculate the proper bit rate. The measurement is taken

over both a low and a high bit time in order to minimize

any effec ts caused by asymmetry o f the incoming signal.

After a Start bit, the SPB RG begins counting up, using

the preselected clock source on the first rising edge of

RX. After eight bit s on the RX pin or the fifth rising edge,

an accumulated value tot alling the proper BRG period is

left in the SPBRGH:SPBRG register pair. Once the 5th

edge is seen (thi s should correspond to the S top bit), the

ABDEN bit is automatically clea red.

If a rollover of the BRG occurs (an overflow from FFFFh

to 0000h), the event is trapped by the ABDOVF status

bit (BAUDCON<7>). It is set in hardware by BRG roll-

over s and can be se t or cleared b y the user in softwar e.

ABD mode rem ains a ctive after roll over even t s and the

ABDEN bit remains set (Figure 18-2).

While calibrating the baud rate period, the BRG regis-

ters are clocked at 1/8th the preconfigured clock rate.

Note that the BRG clock will be configured by the

BRG16 and BRGH bits. Independent of the BRG16 bit

setting, bo th the SPBRG a nd SPBRGH will b e u sed a s

a 16-bit counter. This allows the user to verify that no

carry occurred for 8-bit modes by checking for 00h in

the SPBRGH register. Refer to Table 18-4 for counter

clock rates to the BRG.

While the ABD sequence takes place, the EUSART

state machine is held in Idle. The RCIF interrupt is set

once the fifth rising edge on RX is detected. The value

in the RCREG needs to be read to clear the RCIF

interrupt. The contents of RCREG should be discarded.

TABLE 18-4: BRG COUNTER

CLOCK RATES

18.1.3.1 ABD and EUSART Transmission

Since the BRG clock is reversed during ABD acquisi-

tion, the EUSART transmitter cannot be used during

ABD. This means that whenever the ABDEN bit is set,

TXREG ca nnot be writte n to. Users shou ld also ensu re

that ABDEN does not become set during a transmit

sequenc e. Faili ng to do this m ay resul t in unp redict able

EUSART operation.

Note 1: If the WUE bit is set with the ABDEN bit,

Auto-Baud Rate Detection will occur on

the byte following th e Bre ak character.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible

due to bit error rates. Overall system tim-

ing and communication baud rates must

be taken into consideration when using the

Auto-Baud Rate Detection feature.

BRG16 BRGH BRG Counter Clock

00 FOSC/512

01 FOSC/128

10 FOSC/128

11 FOSC/32

Note: During the ABD sequence, SPBRG and

SPBRGH are both used as a 16-bit counter,

independent of BRG16 setting.

PIC18F2423/2523/4423/4523

FIGURE 18-1: AUTOMATIC BAUD RATE CALCULATION

FIGURE 18-2: BRG OVERFLOW SEQUENCE

BRG Value

RX pin

ABDEN bit

RCIF bit

bit 0 bit 1

(Interrupt)

Read

RCREG

BRG Clock

Start

Auto-Cleared

Set by User

XXXXh 0000h

Edge #1 bit 2 bit 3

Edge #2 bit 4 bit 5

Edge #3 bit 6 bit 7

Edge #4 Edge #5

001Ch

Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

SPBRG XXXXh 1Ch

SPBRGH XXXXh 00h

Stop bi t

Start bit 0

XXXXh 0000h 0000h

FFFFh

BRG Clock

ABDEN bit

RX pin

ABDOVF bit

BRG Value

PIC18F2423/2523/4423/4523

18.2 EUSART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA<4>). In this mode, the

EUSART uses standard Non-Return-to-Zero (NRZ) for-

mat (one Start bit, eight or nine data bits and one Stop

bit). The most common data format is 8 bits. An on-chip

dedic at ed 8-bit/16-bit Ba ud R at e Ge nerator can be u se d

to derive standard baud rate frequencies from the

oscillator.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent but use the same data format and baud

rate. The Baud Rate Generator produces a clock, either

x16 or x64 of the bit shift rate depending on the BRGH

and BRG16 bits (TXST A<2> and BAUDCON<3>). Parity

is not supported by the hardware but can be

implemented in softw are and stored as the 9 th data bit.

When operating in Asynchronous mode, the EUSART

module consists of the following important elements:

• Baud Rate Generat or

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

• Auto-Wake-up on Sync Break Character

• 12-Bit Break Character Transmit

• Auto-Baud Rate Detectio n

18.2.1 EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 18-3. The heart of the transmitter is the T ransmit

(Serial) Shi ft R eg ist er (TSR). T he Sh ift re gis te r obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the Stop

bit has been transmitted from the previous load. As

soon as the Stop bit is transmitted, the TSR is loaded

with new data from the TXREG register (if available).

Once the TXREG register transfers the data to the TSR

and the TXIF flag bit (PIR1<4>) is set. This interrupt can

be enab led or di sabled by s etting o r clearing the in terrupt

enable bit, TXIE (PIE1<4>). TXIF wi ll be set regardless of

the state of TXIE; it cannot be cleared in software. TXIF

is also not cleared immediately up on loading TXREG, but

becomes valid in the second instruction cycle following

the lo ad i nstru ct ion. Poll ing T XIF imme diate ly f ollo win g a

load o f TXREG wi ll re turn in va lid res ul t s .

While TXIF indi cates the sta tus of th e TXREG regi ste r ;

another bit, TRMT (TXSTA<1>), shows the status of

the TSR register. TRMT is a read-only bit which is set

when the TSR register is empty. No interrupt logic is

tied to this bit so the user has to poll this bit in order to

determine if the TSR register is empty.

To set up an Asynchronous Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asy nch ron ous seri al port by clearin g

bit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

5. Enable the transmission by setting bit TXEN

which will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts

transmission).

8. If using interrup ts, ensu re that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 18-3: EUSART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit T XIF is set when en able bit TXEN

is set.

TXIF

TXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate Generator TX9D

MSb LSb

Data Bus

TXREG Register

TSR Register

(8) 0

TX9

TRMT SPEN

TX pin

Pin Buffer

and Control

• • •

SPBRGH

BRG16

PIC18F2423/2523/4423/4523
DS39755B-page 216 Preliminary © 2007 Microchip Technology Inc.
FIGURE 18-4: ASYNCHRONOUS TRANSMISSION       
FIGURE 18-5: ASYNCHRONOUS TRANSMIS SION (BACK-TO-BACK)        
TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION       
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Trans mit Sh ift
Reg. Empty Flag)
1 TCY
Stop bit
Word 1
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Stop bit Start bit
Transmit Shift Reg.
Word  1 Word  2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive trans m issions.
1 TCY
1 TCY
Start bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
TXREG EUSART Transmit Register 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 51
SPBRG EUSART Baud Rate Generator Register Low Byte 51
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

PIC18F2423/2523/4423/4523

18.2.2 EUSART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 18-6.

The data is received on the R X pin an d driv es the da t a

recovery block. The data recovery block is actually a

high-sp eed shifter operating at x16 times the baud rat e,

whereas the main receive serial shifter operates at the

bit rate or at FOSC. This mode would typically be used

in RS-232 systems.

To set up an Asynchronous R eception:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, set enable bit RCIE.

4. If 9-bit reception is desired, set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit, RCIF, will be set when reception is

complete and an interrupt will be generated if

enable bit, RCIE, was set.

7. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during r eception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit C RE N.

10. If using interrup ts, e nsure tha t the G IE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

18.2.3 SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asy nch ron ous seri al port by clearin g

the SYNC bit and setting the SPEN bit.

3. If i nterru pts are requ ired, set the RCE N bit and

select the desired priori ty level with the RCIP bit.

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

7. The RCIF bit will be set when reception is

complete. The interrupt will be Acknowledged if

the RCIE and GIE bits are set.

8. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if app lic able).

9. Read RCREG to determine if the device is being

addressed.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

FIGURE 18-6: EUSART RECEIVE BLOCK DIAGRAM

x64 B aud Rate C LK

Baud Rate Generator

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR Register

MSb LSb

RX9D RCREG Register FIFO

Interrupt RCIF

RCIE Data Bus

÷ 64

÷ 16

or Stop Start

(8) 7 1 0

RX9

• • •

SPBRGSPBRGH

BRG16

÷ 4

PIC18F2423/2523/4423/4523
DS39755B-page 218 Preliminary © 2007 Microchip Technology Inc.
FIGURE 18-7: ASYNCHRONOUS RECEPTION          
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
18.2.4 AUTO-WAKE-UP ON SYNC BREAK 
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. Th e auto-wak e-up feature al lows the cont roller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, mon itoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sist s of a hig h-to-low t ransition  on the RX/ DT line.  (This
coinc ides wi th the star t of a Syn c Break or  a Wake-up
Signal character for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 18-8) and asynchronously, if the device is in
Sleep mode (Figure 18-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up e ve nt.  At th is  poi nt,  the  EU SAR T module is in
Idle mode and retur ns to normal operation. This signals
to the user that the Sync Break event is over.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
RCREG EUSART Receive Register 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL —SCKP BRG16 — WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 51
SPBRG EUSART Baud Rate Generator Register Low Byte 51
Legend: — = unimplemented locations read as  ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Rese rved in 28-pi n devi ces; al ways maintain these b its clear.
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0
Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Inte rru pt Flag )
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.

PIC18F2423/2523/4423/4523

18.2.4.1 Special Considerations Using

Auto-Wake-up

Since auto-wake-up functions by sensing rising edge

transitions on RX/DT, information with any state

changes before the Stop bit may signal a false end-of-

character and cause data or framing errors. To work

properly , therefore, the initial character in the transmis-

sion must be all ‘0’s. This can be 00h (8 bytes) for

stan dard RS-2 32 devi ces or 00 0h (12 bit s) for LIN bus .

Oscillator start-up time must also be considered,

especially in applications using oscillators with longer

start-up intervals (i.e., XT or HS mode). The Sync

Break (or Wake-up Signal) character must be of

suf f ic ien t len gth and be followed by a sufficient interval

to allow enough time for the selected oscillator to start

and provide proper initialization of the EUSART.

18.2.4.2 Special Considerations Using

the WUE Bit

The timi ng of WUE and R CIF events ma y cause so me

confusion when it comes to determining the validity of

rece iv ed da t a. As not ed, set tin g the WUE b it pl ac es t he

EUSART in an Idle mode. The wake-up event causes a

receive interrupt by setting the RCIF bit. The WUE bit is

cleared after this when a rising edge is seen on RX/DT.

The interrupt condition is then cleared by reading the

RCREG register. Ordinarily, the data in RCREG will be

dummy data and should be disca rded.

The fact that the WUE bit has been cleared (or is still

set) and the RCIF flag is set should not be used as an

indicator of the integrity of the data in RCREG. Users

should consider implementing a parallel method in

firmware to verify received data integrity.

To assu re t hat n o act ual data i s los t, che ck the RCI DL

bit to ve rify th at a recei ve ope rati on is not in process. If

a receive operation is not occurring, the WUE bit may

then be set just prior to entering the Sleep mode.

FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TI MINGS DURING NORMAL OPERATION

FIGURE 18-9: AUTO-WAKE-UP BIT (WUE) TI MINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(1)

RX/DT Line

RCIF

Note 1: The EUSART remains in Idle while the WUE bit is set.

Bit set by user

Cleared due to user read of RCREG

Auto-Cleared

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(2)

RX/DT Line

RCIF

Bit set by user

Cleared due to user read of RCREG

Sleep Command Executed

Note 1: If the wake -up event requires long oscillator warm-up tim e, the auto-clear o f the WUE bit can occu r before the oscillato r is read y. This

sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

Note 1

Auto-Cleared

PIC18F2423/2523/4423/4523

18.2.5 BREAK CHARACTER SEQUENCE

The EUSART module has the capabili ty of s en din g th e

special Break character sequen ces that are required by

the LIN bus standard. The Break character transmit

cons ists of a Start bit, foll owed by tw elve ‘ 0’ bits and a

Stop bit. The Frame Break character is sent whenever

the SENDB and TXEN bits (TXSTA<3> and

TXSTA<5>) are set while the Transmit Shift Regi ster is

loaded with data. Note that the value of data written to

TXREG will be ignored and all ‘0’s will be transmitted.

The SENDB bit i s automaticall y reset by ha rdware after

the corresponding Stop b it is s ent . This al lo w s the us er

to preloa d the trans mit FIFO with the n ext transm it byte

following the Break character (typically, the Sync

character in the LIN specification).

Note that the data value written to the TXREG for the

Break ch aracter is ignored. Th e write si mply se rves the

purpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 18-10 for the timing of the Break

character sequence.

18.2.5.1 Br ea k and Sync Transmi t Seque nc e

The following sequence will send a message frame

header ma de up of a Break, followe d by an Auto-Bau d

Sync byte. This sequence is typical of a LIN bus

master.

1. Configu re th e EUSA RT for the desired mode.

2. Set the TXEN and SENDB bits to set up the

Break character.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transm it FIFO buf fe r.

5. After the Break ha s been s ent, the SENDB bit i s

reset by hardware. The Sync character now

transmi t s in the prec onfigured mode.

When the TXR EG b ec om es em pty, as indi ca ted by th e

TXIF, the next data byte can be written to TXREG.

18.2.6 RECEIVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

The first method forces configuration of the baud rate

at a freq uency of 9/ 13 the typi cal spee d. This allow s for

the S top bit transition to be at the correct sampling loca-

tion (13 bi ts for Break v ersus S tart bi t and 8 data bi ts for

typical data).

The second method uses the auto-wake-up feature

describ ed in Section 18.2.4 “Auto-Wake-up on Sync

Break Character”. By enabling this feature, the

EUSART will sample the next two tra nsitions on RX/DT,

cause an RCIF interru pt and receiv e the n ext da ta byte

followed by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. Fo r both methods, th e user can set the ABD bit

once the TXIF interrupt is observed.

FIGURE 18-10: SEND BREAK CHARACTER SEQUENCE

Write to TXREG

BRG Output

(Shift Clock)

Start bit bit 0 bit 1 bit 11 Stop bit

Break

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TX (pin)

TRMT bit

(Transmi t Sh ift

Reg. Empty Flag)

SENDB

(Transmi t Sh ift

Reg. Empty Flag)

SENDB Sampled Here Auto-Cleared

Dummy Write

PIC18F2423/2523/4423/4523

18.3 EUSART Synchronous

Master Mode

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit

SYNC (TXSTA<4>). In addition, enable bit SPEN

(RCSTA<7>) is set in order to con figure the TX and R X

pins to CK (clock) and DT (data) lines, respectively.

The Master mode indicates that the processor trans-

mits the master clock on the CK line. Clock polarity is

selected with the SCKP bit (BAUDCON<4>); setting

SCKP sets the Idle state on CK as high, while clearing

the bit se ts the Id le stat e as low. This option is provided

to support Microwire devices with this module.

18.3.1 EUSART SYNCHRONOUS MASTER

TRANSMISSION

The EUSART transmitter block diagram is shown in

Figure 18-3. The heart of the transmitter is the T ransmit

(Serial) Shi ft R eg ist er (TSR). T he Sh ift re gis te r obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available).

Once the TXR EG register tr ansfers the dat a to the TSR

the TXIF flag bit (PIR1<4>) is se t. The interrupt ca n be

enabled or disabled by setting or clearing the interrupt

enable bit, TXIE (PIE1<4>). TXIF is set regardless of

the state of enable bit TXIE; it cannot be cleared in

softwa re. It wi ll res et onl y w hen n ew dat a is load ed in to

the TXREG register.

While flag bit TXIF indicates the status of the TXREG

status of the TSR register . TRMT is a read-only b it which

is set when the TSR is empty. No interrupt logic is tied to

this bit so the user has to poll this bit in order to deter-

mine if the TSR register is empty. The TSR is not

mapped in dat a memory so it is not available to the user .

To set up a Synchronous Master Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. S tart transmission by loa ding data to the TXREG

8. If using interrup ts, ensu re that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 18-11: SYNCHRONOUS TRANSMISSION

bit 0 bit 1 bit 7

Word 1

Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1Q2 Q3Q4 Q1Q2 Q3Q4Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4

bit 2 bit 0 bit 1 bit 7

RC7/RX/DT

RC6/TX/CK pi n

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bi t ‘1’ ‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

RC6/TX/CK pi n

(SCKP = 0)

(SCKP = 1)

PIC18F2423/2523/4423/4523
DS39755B-page 222 Preliminary © 2007 Microchip Technology Inc.
FIGURE 18-12: SYNCHRONOUS  TRANSMISSION (THROUGH TXEN)       
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION       
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXRE G  r e g
TXIF  b i t
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
TXREG EUSART T rans m it Regis ter 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL —SCKPBRG16—WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 51
SPBRG EUSART Baud Rate Generator Register Low Byte 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 223
PIC18F2423/2523/4423/4523
18.3.2 EUSART SYNCHRONOUS 
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled  by setting either the Sin gle Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable  bit SREN is set, only a single word i s received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits  are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
1 1. If using interrupts, ensure that the GIE and PEIE bits
in the INT CON re gister ( INTCON< 7:6>) are  set.
FIGURE 18-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)       
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION       
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
RCREG E USART Receive Register 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 51
SPBRG EUSART Baud Rate Generator Register Low Byte 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
CREN bit
RC7/RX/DT
RC6/TX/CK pin
Write  t o
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4
‘
0
’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0
’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RC6/TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)

PIC18F2423/2523/4423/4523
DS39755B-page 224 Preliminary © 2007 Microchip Technology Inc.
18.4 EUSART Synchronous 
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchro nous Master  mode in that t he shift clock  is sup-
plied e xternally  at the C K pin (ins tead of be ing supp lied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode. 
18.4.1 EUSART SYNCHRONOUS 
SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit. 
b) The second word will remain in the TXREG
register. 
c) Flag bit, TXIF, will not be set. 
d) When the first word has be en shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit, TXIF, will now be
set. 
e) If enable bit TXIE is set, the interrupt will wake the
chip from Sleep . If the g lobal interrupt i s enabled,
the program will branch to the interrupt vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION       
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on pag e
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
TXREG EUSART Transmit Register 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register High Byte 51
SPBRG EUSART Baud Rate Generator Register Low Byte 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 225
PIC18F2423/2523/4423/4523
18.4.2 EUSART SYNCHRONOUS SLAVE 
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR registe r will transfer the  data to the
RCREG register; if the  RCIE enable bit i s set, t he inter-
rupt generated will wake the chip from the low-power
mode. If the global interru pt is enabled, the program will
branch to the interrupt vector.
To set up a Sy nchrono us Slave Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
6. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrup ts, ensu re that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION      
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
RCREG EUSART Receive Register 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL —SCKPBRG16—WUE ABDEN 51
SPBRGH EUSART Ba ud Rate Genera tor Regi ster High Byte 51
SPBRG EUSART Baud Rate Generator Regi ster Low Byte 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

19.0 12-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has

10 inputs for the 28-pin devi ces and 13 for the 40/44-pin

devices. This module allows conversion of an analog

input signal to a corresponding 12-b it digit al num ber.

The module has five registers:

• A/D Result High Registe r (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Re gister 0 (ADCO N0)

• A/D Control Re gister 1 (ADCO N1)

• A/D Control Re gister 2 (ADCO N2)

The ADCON0 register, shown in Register 19-1,

controls the operation of the A/D module. The

ADCON1 register, shown in Register 19-2, c onfigures

the functions of the port pins. The ADCON2 register,

shown in Register 19-3, configures the A/D clock

source, p rogrammed acquisi tion time and justification.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHS3:CHS0: Analog Channel Select bits

0000 = Channel 0 (AN0)

0001 = Channel 1 (AN1)

0010 = Channel 2 (AN2)

0011 = Channel 3 (AN3)

0100 = Channel 4 (AN4)

0101 = Channel 5 (AN5)(1,2)

0110 = Channel 6 (AN6)(1,2)

0111 = Channel 7 (AN7)(1,2)

1000 = Channel 8 (AN8)

1001 = Channel 9 (AN9)

1010 = Channel 10 (AN10)

1011 = Channel 11 (AN11)

1100 = Channel 12 (AN12

1101 = Unimplemented(2)

1110 = Unimplemented(2)

1111 = Unimplemented(2)

bit 1 GO/DONE: A/D Conversion Status bit

When ADON = 1:

1 = A/D conversion in progress

0 = A/D Idle

bit 0 ADON: A/D On bit

1 = A/D converter module is enabled

0 = A/D converter module is disabled

Note 1: These channels are not implemented on 28-pin devices.

2: Performing a conversion on unimplemented channels will return a floating input measurement.

PIC18F2423/2523/4423/4523

U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1)

—— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)

1 = VREF- (AN2)

0 = VSS

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)

1 = VREF+ (AN3)

0 = VDD

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:

Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When

PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.

2: AN5 through AN7 are available only on 40/44-pin devices.

A = Analog input D = Digital I/

PCFG3:

PCFG0

AN12

AN11

AN10

AN9

AN8

AN7(2

)

AN6(2

)

AN5(2

)

AN4

AN3

AN2

AN1

AN0

0000(1) AAAAAAAAAAAAA

0001 AAAAAAAAAAAAA

0010 AAAAAAAAAAAAA

0011 DAAAAAAAAAAAA

0100 DDAAAAAAAAAAA

0101 DDDAAAAAAAAAA

0110 DDDDAAAAAAAAA

0111(1) DDDDDAAAAAAAA

1000 DDDDDDAAAAAAA

1001 DDDDDDDAAAAAA

1010 DDDDDDDDAAAAA

1011 DDDDDDDDDAAAA

1100 DDDDDDDDDDAAA

1101 DDDDDDDDDDDAA

1110 DDDDDDDDDDDDA

1111 DDDDDDDDDDDDD

PIC18F2423/2523/4423/4523

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified

0 = Left justified

bit 6 Unimplemented: Read as ‘0’

bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits

111 = 20 TAD

110 = 16 TAD

101 = 12 TAD

100 = 8 TAD

011 = 6 TAD

010 = 4 TAD

001 = 2 TAD

000 = 0 TAD(1)

bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits

111 = FRC (clock derived from A/D RC oscillator)(1)

110 = FOSC/64

101 = FOSC/16

100 = FOSC/4

011 = FRC (clock derived from A/D RC oscillator)(1)

010 = FOSC/32

001 = FOSC/8

000 = FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D

clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

PIC18F2423/2523/4423/4523

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(VDD and VSS), or the voltage level on the RA3/AN3/

VREF+ and RA2/AN2/VREF-/CVREF pins.

The A/D converter has a unique feature of being able

to operate while the device is in Sleep mode. To oper-

ate in Sleep, th e A/D conv ersion clock must b e derive d

from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted.

Each port pin associated with the A/D converter can be

configured as an analog input, or as a digital I/O. The

ADRESH and ADRESL registers contain the result of

the A/D conversion. When the A/D conversion is com-

plete, the result is loaded into the ADRESH:ADRESL

cleared and A/D Interrupt Flag bit, ADIF, is set. The block

diagram of the A/D module is s hown in Figure 19-1.

FIGURE 19-1: A/D BLOCK DIAGRAM

(Input Voltage)

VAIN

VREF+

Reference

Voltage

VDD(2)

VCFG1:VCFG0

CHS3:CHS0

AN7(1)

AN6(1)

AN5(1)

AN4

AN3

AN2

AN1

AN0

0111

0110

0101

0100

0011

0010

0001

0000

12-Bit

Converter

VREF-

VSS(2)

A/D

AN12

AN11

AN10

AN9

AN8

1100

1011

1010

1001

1000

Note 1: Channels AN5 through AN7 are not available on 28-pin devices.

2: I/O pins have diode protection to VDD and VSS.

PIC18F2423/2523/4423/4523

The value in the ADRESH:ADRESL registers is

unknown following POR and BOR Resets, and is not

af fected by an y other Reset.

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 19.1

“A/D Acquisition Requirements”. After this acquisi-

tion time has elapsed, the A/D conversion can be

started. An acquisition time can be programmed to

occur bet ween setting th e GO/DONE bit an d the actual

start of the conversion.

The following steps should be followed to perform an A/D

conversion:

1. Configure the A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversi on cl ock (ADCO N2)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desi red):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion:

• Set GO/DONE bit (ADCON0 register)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH:ADRESL);

clear bit ADIF, if required.

7. For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

FIGURE 19-2: A/D TRANSFER FUNCTION

FIGURE 19-3: ANALOG INPUT MODEL

Digital Code Output

FFEh

003h

002h

001h

000h

0.5 LSB

1 LSB

1.5 LSB

2 LSB

2.5 LSB

4094 LSB

4094.5 LS B

3 LSB

Analog Input Voltage

FFFh

4095 LSB

4095.5 LS B

VAIN CPIN

Rs ANx

5 pF

VT = 0.6V

VT = 0.6V ILEAKAGE

RIC ≤ 1k

Sampling

Switch

SS RSS

CHOLD = 25 pF

VSS

VDD

±100 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

various junctions

= Sampling Switch Re sistanceRSS

VDD

Sampling Switch

1234

(kΩ)

PIC18F2423/2523/4423/4523

19.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 19-3. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance va ries ov er the dev ice vol tag e

(VDD). The sour ce impedanc e af fects th e offse t voltag e

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), the channel must be sampled for

at least the minimum acquisition time before starting a

conversion.

To calculate the minimum acquisition time,

Equation 19-1 may be used. This equation assumes

that 1/2 LSb error is used (4096 st eps for the A/D). The

1/2 LSb er ror is the ma ximu m error allow ed for the A/D

to meet its specified resolution.

Example 19-3 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following application system

assumptions:

CHOLD = 25 pF

Rs = 2.5 kΩ

Conversion Error ≤1/2 LSb

VDD =3V → Rss = 4 kΩ

Temperature = 85°C (system max.)

EQUATION 19-1: ACQUISITION TIME

EQUATION 19-2: A/D MINIMUM CHARGING TIME

EQUATION 19-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note: When the conversion is started, the

holding cap ac itor i s di scon nected from the

input pin.

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

AMP + TC + TCOFF

VHOLD = (VREF – (VREF/409 6)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))

TC = -(CHOLD)(RIC + RSS + RS) ln(1/4096)

TACQ =TAMP + TC + TCOFF

TAMP =0.2 μs

TCOFF = (Temp – 25°C)(0.02 μs/°C)

(85°C – 25°C)(0.02 μs/°C)

1.2 μs

Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.

TC = -(CHOLD)(RIC + RSS + RS) ln(1/4095) μs

-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0004883) μs

1.56 μs

TACQ =0.2 μs + 1.56 μs + 1.2 μs

2.96 μs

PIC18F2423/2523/4423/4523

19.2 Selecting and Configuring

Acquisition Time

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set. It also gives users the option to use an

automatically determined acquisition time.

Acquisition time may be set with the ACQT2:ACQT0

bits (ADCON2<5:3>), which provides a range of 2 to

20 TAD. When the GO/DONE bit is set, th e A/D modul e

continues to sample the input for the selected acquisi-

tion time, then automatically begins a conversion.

Since the acquisition time is programmed, there may

be no need to wait for an acquisition time between

selecting a channel and setting the GO/DONE bit.

Manual acquisition is selected when

ACQT2:ACQT0 = 000. When the GO/DONE bit is set,

sampli ng is stopp ed and a conv ersion begi ns. The user

is responsible for en suring the required acquisition time

has passed between selecting the desired input

channel and setting the GO/DONE bit. This option is

also the default Reset state of the ACQT2:ACQT0 bits

and is compatible with devices that do not offer

progra mmab le ac qui sition times .

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. If an acquisition time is programmed, there is

nothing to indicate if the acquisition time has ended or

if the conversion has begun.

19.3 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 13 TAD per 12-bit conversion.

The source of the A/D conversion clock is software

selectable. There are seven possible options for TAD:

•2 T

OSC

•4 TOSC

•8 TOSC

•16 TOSC

•32 TOSC

•64 TOSC

• Internal RC Osci ll ator

For correct A/D conversions, the A/D conversion clock

(TAD) must be as short a s possible, bu t greater than the

minimum TAD (see parameter 130 for more

information).

Table 19-1 shows the resultant TAD times de ri ve d fr o m

the device operating frequencies and the A/D clock

source selected.

TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES

A/D Clock Source (TAD)Assumes TAD Min. = 0.8 μs

Operation ADCS2:ADCS0 Maximum FOSC

2 TOSC 000 2. 50 MH z

4 TOSC 100 5. 00 MH z

8 TOSC 001 10.00 MHz

16 TOSC 101 20.00 MHz

32 TOSC 010 40.00 MHz

64 TOSC 110 40.00 MHz

RC(2) x11 1.00 MHz (1)

Note 1: The RC sour ce has a typical TAD time of 2.5 μs.

2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC

divider should be used instead. Otherwise, the A/D accuracy specification may not be met.

PIC18F2423/2523/4423/4523

19.4 Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ADCS2:ADCS0 bits in

ADCON2 should be updated in accordance with the

clock source to be used. The ACQT2:ACQT0 bits do

not need to be adjusted as the ADCS2:ADCS0 bits

adjust the TAD time for the new clock speed. After

entering the mode, an A/D acquisition or conversion

may be started. Once started, the device should

conti nue t o be clo cked by the same clock s ource u ntil

the conversion has been completed.

If desired, the device may be placed into the

corr espondi ng Idle m ode dur ing th e conve rsion . If t he

device c loc k freq ue ncy is les s tha n 1 MHz, the A/D RC

clock source should be selected.

Operation in the Sleep mode requires the A/D FRC

clock to be selected. If bits ACQT2:ACQT0 are set to

‘000’ and a con version is started, the conversion will be

delay ed on e ins tr uctio n cycl e to allo w exec uti on of the

SLEEP instruc tion and e ntry to Slee p mode. The IDLEN

bit (OSCCON<7>) must have already been cleared

prior to starting the conversion.

19.5 Configuring Analog Port Pins

The ADCON1, TRISA, TRISB and TRISE registers all

configure the A/D port pins. The port pins needed as

analog inputs must have their corresponding TRIS bits

set (input) . If the TRIS bit is cleare d (output), the digit al

output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS3:CHS0 bits and the TRIS bits.

Note 1: When reading the PORT register, all pins

configured as analog input channels will

read as cl eared (a low lev el). Analog co n-

version on pins configured as digital pins

can be perform ed. The vol tag e on the pin

will be accurately converted.

2: Analog l evels o n any p in defin ed as a dig-

ital input may cause the digital input buffer

to consume current out of the device’s

specification limits.

3: The PBADEN bit in Configuration

reset as analog or digital pins by control-

ling how the PCFG3:PCFG0 bits in

ADCON1 are reset.

PIC18F2423/2523/4423/4523

19.6 A/D Conversions

Figure 19-4 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are cleared. A conversion is

started after the following instruction to allow entry into

Sleep mode before the conversion begins.

Figure 19-5 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are set to ‘010’ and selecting a

4TAD acquisition time before the conversion starts.

Clearing the GO/DONE bit during a conversion will abort

the current conversion. The A/D Result register pair will

NOT be updated with the partially completed A/D

conversion sample. This means the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

CY wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

19.7 Discharge

The discharge phase is used to initialize the value of

the holding capacitor. The array is discharged before

every sample. This feature helps to optimize the unity-

gain am plifier , a s the circuit al ways needs to charge the

capacitor array , rather than charge/discharge based on

previous measure values.

FIGURE 19-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 19-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note: The GO/DONE bit should NOT be set in

the sam e inst ructio n that tu rns on the A/D.

Code should wait at least 3 TAD after

enabling the A/D before beginning an

acquisition and conversion cycle.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10TCY – TAD

ADRESH:ADRESL are loaded, GO/DONE bit is cl eared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

b11 b8 b7 b6 b5 b4 b3

b10 b9

On the following cycle:

Discharge

TAD13TAD12 b0b1 TAD1

(typically 200 ns)

123456 7 813

Set GO/DONE bit

(Holding capacitor is disconnected)

912

Conversion starts

1234

(Holding ca pacito r continu es

acquiring input)

TACQT Cycles TAD Cycles

Automatic

Acquisition

Time

b0b11 b8 b7 b6 b5 b4 b1

b10 b9

ADRESH:ADRESL are loaded, GO/DONE bit is c leared,

ADIF bit is set, holding capacitor is connected to analog input.

On t he following cycle:

TAD1

Discharge

10 11

b3 b2

(typically

200 ns)

Points to end of TACQT period (current black arrow)

PIC18F2423/2523/4423/4523
DS39755B-page 236 Preliminary © 2007 Microchip Technology Inc.
19.8 Use of the CCP2 Trigger
An A/D conv ersio n can  be st arted  by th e Speci al Eve nt
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ an d that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automati-
cally repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input
channel  must b e selecte d and the mi nimum ac quisitio n
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D  module is not  enabled (A DON is c leared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
 
TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION     
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on pag e
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
PIR2 OSCFIF CMIF —EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE —EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP —EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
ADRESH  A/D Result Register High Byte 51
ADRESL  A/D Result Register Low Byte 51
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 51
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 51
PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 52
TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 52
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52
TRISB PORTB Data Direction Control Register 52
LATB PORTB Data Latch Register (Read and Write to Data Latch) 52
PORTE(1) — — — —RE3
(3) RE2 RE1 RE0 52
TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52
LATE(1) — — — — — PORTE Dat a Latch Register 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary 
oscillator modes. When disabled, these bits read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.

PIC18F2423/2523/4423/4523

20.0 COMPARATOR MODULE

The analog comparator module contains two

comparators that can be configured in a variety of

ways. The inputs can be selected from the analog

inputs multiplexed with pins RA0 through RA5, as well

as the on-chip voltage reference (see Section 21.0

“Comparator Voltage Reference Module” ). The digi-

tal outputs (normal or inverted) are available at the pin

level a nd c an a ls o be read thro ugh the c on trol regi ster .

The CMCON register (Register 20-1) selects the

comparator input and output configuration. Block

diagrams of the various comparator configurations are

shown in Figure 20-1.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:

1 = C2 VIN+ > C2 VIN-

0 = C2 VIN+ < C2 VIN-

When C2INV = 1:

1 = C2 VIN+ < C2 VIN-

0 = C2 VIN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 = C1 VIN+ > C1 VIN-

0 = C1 VIN+ < C1 VIN-

When C1INV = 1:

1 = C1 VIN+ < C1 VIN-

0 = C1 VIN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output inverted

0 = C2 output not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 output inverted

0 = C1 output not inverted

bit 3 CIS: Comparator Input Switch bit

When CM2:CM0 = 110:

1 =C1 VIN- connects to RA3/AN3/VREF+

C2 VIN- connects to RA2/AN2/VREF-/CVREF

0 =C1 VIN- connects to RA0/AN0

C2 VIN- connects to RA1/AN1

bit 2-0 CM2:CM0: Comparator Mode bits

Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings.

PIC18F2423/2523/4423/4523

20.1 Comparator Configuration

There are eight modes of operation for the compara-

tors, shown in Figure 20-1. Bits CM2:CM0 of the

CMCON register are used to select these modes. The

TRISA register controls the data direction of the com-

parator pins for each mode. If the Comparator mode is

changed, the comparator output level may not be valid

for the specified mode change delay shown in

Section 2 6.0 “Electrical Characteristics”.

FIGURE 20-1: COMPARATOR I/O OPERATING MODES

Note: Compara tor in terr upts sh ould be dis abled

during a Comparator mode change;

otherwi se , a false inte rrup t may oc cur.

RA0/AN0 VIN-

VIN+

RA3/AN3/ Off (Read as ‘0’)

Comparators Reset

CM2:CM0 = 000

RA1/AN1 VIN-

VIN+

RA2/AN2/ Off (Read as ‘0’)

VIN-

VIN+C1OUT

Two Independent Comparators

CM2:CM0 = 010

VIN-

VIN+C2OUT

VIN-

VIN+C1OUT

Two Common Reference Compa rators

CM2:CM0 = 100

VIN-

VIN+C2OUT

VIN-

VIN+Off (Read as ‘0’)

One Independent Comparator with Output

CM2:CM0 = 001

VIN-

VIN+C1OUT

VIN-

VIN+Of f (Read as ‘0’)

Comparators Off (POR Default Value)

CM2:CM0 = 111

VIN-

VIN+Of f (Read as ‘0’)

VIN-

VIN+C1OUT

Four Inputs Multiplexed to Two Comparators

CM2:CM0 = 110

VIN-

VIN+C2OUT

From VREF Module

CIS = 0

CIS = 1

CIS = 0

CIS = 1

VIN-

VIN+C1OUT

Two Common Reference Comparators with Outputs

CM2:CM0 = 101

VIN-

VIN+C2OUT

A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch

CVREF

VIN-

VIN+C1OUT

Two Independent Comparators with Outputs

CM2:CM0 = 011

VIN-

VIN+C2OUT

RA5/AN4/SS/HLVDIN/C2OUT*

RA4/T0CKI/C1OUT*

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

VREF+

RA1/AN1

RA2/AN2/

VREF-/CVREF

RA4/T0CKI/C1OUT*

RA5/AN4/SS/HLVDIN/C2OUT*

RA0/AN0

RA3/AN3/

VREF+

RA1/AN1

RA2/AN2/

VREF-/CVREF

RA4/T0CKI/C1OUT*

* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.

PIC18F2423/2523/4423/4523

20.2 Comparator Operation

A single comp arator is shown in Figure 20-2, along with

the relationship between the analog input levels and

the digit al ou tput. When the an alog input a t VIN+ is less

than the analog input VIN-, the o utput of the co mparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 20-2 represent

the unce rt ainty, due to in put of fse ts a nd resp on se tim e.

20.3 Comparator Reference

Depending on the comparator operating mode, either

an external or internal voltage reference may be used.

The analog signal present at VIN- is compared to the

signal at VIN+ and the di gital output of the comparator

is adjusted accordingly (Figure 20-2).

FIGURE 20-2: SINGLE COMPARATOR

20.3.1 EXTERNAL REF E REN CE SIG NA L

When external voltage references are used, the

comparator module can be configured to have the com-

parators operate from the same or different reference

sour ces. How ever , th resho ld detecto r applica tions ma y

require the same reference. The reference signal can

be applied to either pin of the comparator(s) (see

Table 26-2).

20.3.2 INTERNAL REFERENCE SIGNAL

The com p a r ato r m odu le also allows th e sel ec tio n of an

internally generated voltage reference from the

comparator voltage reference module. This module is

describ ed in m ore de tai l in Section 21.0 “Comparator

Voltage Reference Module”.

The internal reference is only available in the mode

where four inputs are multiplexed to two comparators

(CM2:CM0 = 110). In this mode, the internal voltage

reference is applied to the VIN+ pin of both

comparators.

20.4 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal ref-

erence is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs. Otherwise, the maximum delay of

the comparators should be used (see Table 26-2).

20.5 Comparator Outputs

The comparator outputs are read through the CMCON

output s may al so be dire ctly output to the RA4 a nd RA5

I/O pins . When enab led, multipl exors in th e output p ath

of the RA4 and RA5 pins will switch and the output of

each pin will be the unsynchronized output of the

comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the specifications.

Figure 20-3 shows the comparator output block

diagram.

The TRISA bits will still function as an output enable/

disable for the RA4 and RA5 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C2INV and C1INV bits (CMCON<5:4 >).

–

VIN+

VIN-Output

Output

VIN-

VIN+

Note 1: When reading the PORT register, all pins

configu red a s anal og inp uts will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

2: Analog levels on any pin defined as a

digital inpu t may cau se the in put bu ffer to

consume more current than is specified.

PIC18F2423/2523/4423/4523

FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM

20.6 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

stat us of the out put bits, as rea d from CMCON<7:6> , to

determine the actual change that occurred. The CMIF

bit (PIR2<6>) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing it. Since it is also

possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

Both the CMIE bit (PIE2<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit (INTCON<7>) must also be set. If

any of these bits are clear, the interrupt is not enabled,

though the CMIF bit will still be set if an interrupt

conditi on oc curs.

The use r , in the Interru pt Service Rout ine, can clear th e

inter rupt in the following manne r:

a) Any read or write of CMCON will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit, CMIF, to be cleared.

20.7 Comparator Operation

During Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode, when enabled.

Each operational comparator will consume additional

current, as shown in the comparator specifications. To

minimi ze power co nsumption wh ile in Sleep mod e, turn

off the comparators (CM2:CM0 = 111) before entering

Sleep. If the dev ice w ak es up fro m Sle ep, the c ontent s

of the CMCON register are not affected.

20.8 Effects of a Reset

A device Reset forces the CMCON register to its Reset

state , ca using the comp arat or modul es to be turn ed of f

(CM2:CM0 = 111). However, the input pins (RA0

through RA3) are configured as analog inputs by

default on device Rese t. The I/O configuration for these

pins is determined b y the sett ing of the PCF G3:PCFG0

bits (ADCON1<3:0>). Therefore, device current is

minimized when analog inputs are present at Reset

time.

To RA4 or

RA5 pin

Bus

Data

Set

MULTIPLEX

CMIF

bit

PORT pins

Read CMCON

Reset From

other

Comparator

CxINV

EN CL

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR2<6>)

interrupt flag may not get set.

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 241
PIC18F2423/2523/4423/4523
20.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betwee n
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 20-4: COMPARATOR ANALOG INPUT MODEL        
TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE  
VA
RS < 10k
AIN CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Ca pacita nce
VT= Threshold Voltage
ILEAKAGE =  Leakage Current at the pin due to various junctions
RIC = Inte rconn ect Resistan ce
RS= Source Impedance
VA = Analog Voltage
Comparator
Input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 
Values 
on page
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 52
PIR2 OSCFIF CMIF —EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE —EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP —EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52
LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 52
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various 
primary oscillator modes. When disabled, these bits read as ‘0’.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

21.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The comparator voltage reference is a 16-tap resistor

ladder network that provides a selectable reference

voltage. Although its primary purpose is to provide a

reference for the analog comparators, it may also be

used independently of them.

A block diagram of t he module is shown in Figure 21-1.

The resis tor ladder is segment ed to provide two range s

of CVREF values and has a power-down function to

conserve power when the reference is not being used.

The module’s supply reference can be provided from

either device VDD/VSS or an external voltage reference.

21.1 Configuring the Comparator

Voltage Reference

The vol tag e referen ce m odule i s control led th rough th e

CVRCON register (Register 21-1). The comparator

voltage reference provides two ranges of output

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary diffe rence between the rang es is the si ze of th e

steps selected by the CVREF Selection bits

(CVR3:C VR0), w it h on e ra nge offering finer resolu tio n.

The equations used to calculate the output of the

comparator voltage reference are as follows:

If CVRR = 1:

CVREF = ((CVR3:CVR0)/24) x CV RSRC

If CVRR = 0:

CVREF = (CVRSRC x 1/4) + (( (CVR3:CVR0)/32) x

CVRSRC)

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF- that are multiplexed with RA2 and RA3. The

voltage source is selected by the CVRSS bit

(CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF out-

put (see Table 26-3 in Section 26.0 “Electrical

Characteristics”).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CVREN: Comp ara tor Voltage Referen ce Enable bit

1 =CV

REF circuit powered on

0 =CV

REF circuit powered down

bit 6 CVROE: Comparator VREF Outp ut Enabl e bit(1)

1 =CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin

0 =CV

REF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin

bit 5 CVRR: Comparator VREF Range Selection bit

1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size (low range)

0 = 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size (hig h range)

bit 4 CVRSS: Compa r ator VREF Source Selection bit

1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)

0 = Comparator reference source, CVRSRC = VDD – VSS

bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bit s (0 ≤ (CVR3:CVR0) ≤ 15)

When CVRR = 1 (low range):

CVREF = ((CVR3:CVR0)/24) • (CVRSRC)

When CVRR = 0 (high range):

CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)

Note 1: CVROE overrides the TRISA<2> bit setting.

PIC18F2423/2523/4423/4523

FIGURE 21-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

21.2 Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 21-1) keep CVREF from approaching the refer-

ence source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 26.0 “Electrical Characteristics”.

21.3 Operation During Sleep

When the device wakes up from Sleep through an

interr upt o r a Watchdog Timer time-out, the c onte nt s of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

21.4 Effects of a Reset

A device Reset disables the voltage reference by

clearing bit, CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit, CVROE (CVRCON<6>) and selects the high-voltage

range by clearing bit, CVRR (CVRCON<5>). The CVR

value select bits are also cleared.

21.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

CVROE bit is set. Enabling the voltage reference out-

put ont o RA2 when it is con figured as a di gital in put will

increase current consumption. Connecting RA2 as a

digital output with CVROE enabled will also increase

current consumption.

The RA2 pin can be used as a simple D/A output with

lim ite d dr i ve c apa bi lit y. D u e t o t he li m ite d c ur re nt dri v e

capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 21-2 shows an example buffering technique.

16-to-1 MUX

CVR3:CVR0

CVREN

CVRSS = 0

VDD

VREF+CVRSS = 1

CVRSS = 0

VREF-CVRSS = 1

16 St eps

CVRR

CVREF

PIC18F2423/2523/4423/4523

FIGURE 21-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

CVREF Output

CVREF

Module Voltage

Reference

Output

Impedance

R(1)

RA2

Note 1: R is dependent upon the Comparator V REF Selection bits, CVRCON<3:0> and CVRCON<5>.

PIC18FXXXX

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51

TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52

Legend: Shaded cells are not used with the comparator voltage reference.

Note 1: PORTA pins are enabled based on oscillator configuration.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

22.0 HIGH/LOW-VOLTAGE DETECT

(HLVD)

PIC18LF2423/2523/4423/4523 devices have a

High/Low-Voltage Detect module (HLVD). This is a pro-

grammable circuit that allows the user to specify both a

device voltage trip point and the direction of change from

that point. If the device experiences an excursion past

the trip point in that direction, an interrupt flag is set. If the

interrupt is enabled, the program execution will branch to

the interrupt vector address and the software can then

respond to the interrupt.

The High/Low-Voltage Detect Control register

(Register 22-1) completely controls the operation of the

HLVD module. This allows the circuitry to be “turned

off” by the user under software control, which

minimizes the current consumption for the device.

The block diagram for the HLVD module is shown in

Figure 22-1.

R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1

VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 VDIRMAG: Voltage Direction Magnitude Select bit

1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)

0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)

bit 6 Unimplemented: Read as ‘0’

bit 5 IRVST: Internal R eference Voltage Stable F lag bit

1 = Indicates that the volt age detect logi c will generat e the interrupt fla g at the specifi ed voltage range

0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage

range and the HLVD interrupt should not be enabled

bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit

1 = HLVD enabled

0 = HLVD disabled

bit 3-0 HLVDL3:HLVDL0: Voltage Dete cti on Lim it bits(1)

1111 = External analog input is used (input comes from the HLVDIN pin)

1110 = Maximu m setting

0000 = Minimum setting

Note 1: See Table 26-4 for specifications.

PIC18F2423/2523/4423/4523

The module is enabled by setting the HLVDEN bit.

Each time that the HLVD module is enabled, the cir-

cuitry requires some time to stabilize. The IRVST bit is

a read-only bit and is used to indicate when the circuit

is stable. The module can only generate an interrupt

after the circuit is stable and IRVST is set.

The VDIRMAG bit determines the overall operation of

the module. When VDIRMAG is cleared, the module

monitors for drops in VDD below a predetermined set

point. Wh en the bit is set, the mo dule moni tors for rises

in VDD above the set point.

22.1 Operation

When the HLVD module is enabled , a comp arat or uses

an internally generated reference voltage as the set

point. The set point is compared with the trip point,

where each node in the resistor divider represents a

trip point voltage. The “trip point” voltage is the voltage

level at which the device detects a high or low-voltage

event, depending on the configuration of the module.

When the supply voltage is equal to the trip point, the

voltage tapped off of the resistor array is equal to the

internal reference voltage generated by the voltage

reference module (approximately 1.25V). The compar-

ator then generates an interrupt signal by setting the

HLVDIF bit.

The trip point voltage is software programmable to any one

of 15 trip poin t values, or an external vo ltage input. The trip

point is selected by programming the HLVDL3:HLVDL0

bits ( H LVDCON<3:0>).

The HLVD modul e has a n additio nal featu re that allows

the user to supply the trip volt age to the module from an

external source. This mode is enabled when bits

HLVDL3:HLVDL0 are set to ‘1111’. In this state, the

comparator input is multiplexed from the external input

pin, HLVDIN. This gives users flexibility because it

allows them to configure the High/Low-Voltage Detect

interrupt to occur at any voltage in the valid operating

range.

FIGURE 22-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)

Set

VDD

16-to-1 MUX

HLVDEN

HLVDCON

HLVDIN

HLVDL3:HLVDL0 Register

HLVDIN

VDD

Externally Gene rated

Trip Point

HLVDIF

HLVDEN

BOREN Internal Volt age

Reference

VDIRMAG

Approximately 1.25V

PIC18F2423/2523/4423/4523

22.2 HLVD Setup

The following steps are needed to set up the HLVD

module:

1. Write the valu e to the HLVDL3:HLVDL0 bits th at

selects the desired HLVD trip point.

2. Set the VDIRMAG bit to detect high voltage

(VDIRMAG = 1) or low voltage (VDIRMAG = 0).

3. Enable the HLVD module by setting the

HLVDEN bit.

4. Cle ar the HLVD i nte rrupt flag (PIR 2<2> ), whi ch

may have been set from a previous interrupt.

5. Enable the HLVD interrupt, if interrupts are

desired, by setting the HLVDIE and GIE bits

(PIE2<2 > and INTCON <7>). An i nterrupt will not

be generated until the IRVST bit is set.

22.3 Current Consumption

When the module is enabled, the HLVD comparator

and volt age divider are enabled and will consume stati c

current. The total current consumption, when enabled,

is specified in electrical specification parameter D022B.

Depending on the application, the HLVD module does

not need to be operating constantly. To decrease the

current requirements, the HLVD circuitry may only

need to be en abled for short pe riods w here the volt age

is checked. After doing the check, the HLVD module

may be disabled.

22.4 HLVD Start-up Time

The internal reference voltage of the HLVD module,

specified in electrical specification parameter D420,

may be used by other internal circuitry, such as the

Programmable Brown-out Reset. If the HLVD or other

circuits using the voltage reference are disabled to

lower the device’s current consumption, the reference

volt age circui t will requ ire time to be come st able befo re

a low or high-voltage condition can be reliably

detected. This start-up time, TIRVST, is an interval that

is independent of device clock speed. It is specified in

electrical specification parameter 36.

The HLVD interrupt f lag is no t en abl ed u nti l TIRVST has

expired and a stable reference voltage is reached. For

this reason, brief excursions beyond the set point may

not be detected during this interval. Refer to

Figure 22-2 or Figure 22-3.

FIGURE 22-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)

VLVD

VDD

HLVDIF

VLVD

VDD

Enable HLVD

TIRVST

HLVDIF ma y not be set

Enable HLVD

HLVDIF

HLVDIF cleared in software

HLVDIF cleared in software,

CASE 1:

CASE 2:

HLVDIF remains set since HLVD condition still exists

TIRVST

Internal Reference is stable

IRVST

PIC18F2423/2523/4423/4523

FIGURE 22-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)

22.5 Applications

In many applications, the ability to detect a drop below

or rise above a particular threshold is desirable. For

general batter y applic ations, Figure 22- 4 sho ws a pos-

sible voltage curve. Over time, the device voltage

decreases. When the device voltage reaches voltage

VA, the HLVD logic generates an interrupt at time TA.

The interrupt could cause the execution of an ISR,

which would allow the application to perform “house-

keeping tasks” and perform a controlled shutdown

before the device voltage exits the valid operating

range at TB. The HLVD, thus, would give the applica-

tion a time window, represented by the difference

between TA and TB, to safely exit.

FIGURE 22-4: TYPICAL LOW-VOLTAGE

DETECT APPLICATION

VLVD

VDD

HLVDIF

VLVD

VDD

Enable HLVD

TIRVST

HLVDIF may not be set

Enable HLVD

HLVDIF

HLVDIF cleared in software

HLVDIF cleared in software,

CASE 1:

CASE 2:

HLVDIF remains set since HLVD condition still exists

TIRVST

IRVST

Internal Reference is stable

IRVST

Time

Voltage

TATB

VA = HLVD trip point

VB = Minimum valid device

operating voltage

Legend:

PIC18F2423/2523/4423/4523

22.6 Operation During Sleep

When en abled, the HLVD circuitry continues to opera te

during Sleep. If the device voltage crosses the trip

point, the HLVDIF bit will be set and the device will

wake-up from Sleep. Device execution will continue

from the interrupt vector address if interrupts have

been globally enabled.

22.7 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the HLVD module to be turned off.

TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on Page

HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 50

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52

PIE2 OCSFIE CMIE —EEIE BCLIE HLVDIE TMR3IE CCP2IE 52

IPR2 OSCFIP CMIP —EEIP BCLIP HLVDIP TMR3IP CCP2IP 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

23.0 SPECIAL FEATURES OF THE

CPU

PIC18LF2423/2523/4423/4523 devices include several

features intended to maximize reliability and minimize

cost through elimination of external components. These

are:

• Oscillator Selection

• Resets:

- Pow er-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor

• Two-Speed Sta rt-up

• Code Protection

• ID Locations

• In-Circuit Serial Programming

The oscillator can be configured for the application

dependi ng on frequ ency, power, accuracy and cost . All

of the options are discussed in detail in Section 2.0

“Oscillator Configurations”.

A complete discussion of device Resets and interrupts

is avail able in previous sections of this data sheet.

In addition to their Power-up and Oscillator Start-up

Timers provided for Resets, PIC18LF2423/2523/4423/

4523 devices have a Watchdog Timer, which is either

permanently enabled via the Configuration bits or

software controlled (if co nfigured as dis abled).

The inclu sio n of an in ternal RC osci ll ator also provi de s

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure. Two-

Speed Start-up enables code to be executed almost

immedi ately on s tart-up, while th e primary clock so urce

completes its start-up delays.

All of these features are enabled and configured by

setting the appropriate Configuration register bits.

23.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’) or left unprogram med (read as ‘1’) to select various

device configurations. These bits are mapped starting

at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h-3FFFFFh), which

can only be accessed using table reads and table writes.

Programming the Configuration registers is done in a

manner s imilar to p rogrammin g the Flas h memo ry. The

WR bit in the EECON1 register starts a self-timed write

to the Configuration register . In normal opera tion mode,

a TBLWT instruction with the TBLPTR pointing to the

Config uration reg ister se ts up the addre ss and the dat a

for the Configuration register write. Setting the WR bit

starts a long write to the Configuration register. The

Conf igu rati on regi ster s a re writ ten a by te a t a ti me. To

write or erase a configuration cell, a TBLWT instruct i on

can writ e a ‘1’ or a ‘0’ into the cell. For addi tional d etail s

on Flash programming, refer to Section 6.5 “Writing

to Flash Program Memory”.

TABLE 23-1: CONFIGURATION BIT S AND DEVICE IDs

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogrammed

Value

300001h CONFIG1H IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111

300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111

300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111

300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011

300006h CONFIG4L DEBUG XINST — — —LVP—STVREN10-- -1-1

300008h CONFIG5L — — — —CP3

(1) CP2(1) CP1 CP0 ---- 1111

300009h CONFIG5H CPD CPB — — — — — — 11-- ----

30000Ah CONFIG6L — — — —WRT3

(1) WRT2(1) WRT1 WRT0 ---- 1111

30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----

30000Ch CONFIG7L — — — —EBTR3

(1) EBTR2(1) EBTR1 EBTR0 ---- 1111

30000Dh CONFIG7H —EBTRB— — — — — — -1-- ----

3FFFFEh DEVID1(2) DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0 xxxx xxxx(2)

3FFFFFh DEVID2(2) DEV11 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 xxxx xxxx(2)

Legend: x = unknown, u = unchanged, — = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: U nimplement ed in PIC18LF2423/4423 devices; maintain this bit set.

2: See Register 23-12 and Register 23-13 for DEVID1 and DEVID2 values. DEVID registers are read-only and cannot be

programmed by the user.

PIC18F2423/2523/4423/4523

R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1

IESO FCMEN —— FOSC3 FOSC2 FOSC1 FOSC0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 IESO: Internal/External Oscillator Switchover bit

1 = Oscillator Switchover mode enabled

0 = Oscillator Switchover mode disabled

bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 FOSC3:FOSC0: Oscillator Selection bits

11xx = External RC oscillator, CLKO function on RA6

101x = External RC oscillator, CLKO function on RA6

1001 = Internal oscillator block, CLKO function on RA6, port function on RA7

1000 = Internal oscillator block, port function on RA6 and RA7

0111 = External RC oscillator, port function on RA6

0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)

0101 = EC oscillator, port function on RA6

0100 = EC oscillator, CLKO function on RA6

0011 = External RC oscillator, CLKO function on RA6

0010 = HS oscillator

0001 = XT os cillator

0000 = LP oscillator

PIC18F2423/2523/4423/4523

U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— — —BORV1

(1) BORV0(1) BOREN1(2) BOREN0(2) PWRTEN(2)

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-5 Unimplemented: Read as ‘0’

bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1)

11 = Minimum setting

00 = Maximum setting

bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(2)

11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)

10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)

01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)

00 = Brown-out Reset disabled in hardware and software

bit 0 PWRTEN: Power-up Timer Enable bit(2)

1 = PWRT disabled

0 = PWRT enabled

Note 1: See Section 26.1 “DC Characteristics: Supply Voltage” for specifications.

2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently

controlled.

PIC18F2423/2523/4423/4523

U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-5 Unimplemented: Read as ‘0’

bit 4-1 WDTPS3:WDTPS0: Watchdog T i me r Post s ca le Sele ct bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

bit 0 WDTEN: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on the SWDTEN bit)

PIC18F2423/2523/4423/4523

R/P-1 U-0 U-0 U-0 U-0 R/P-0 R/P-1 R/P-1

MCLRE — — — — LPT1OSC PBADEN CCP2MX

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 MCLRE: MCLR Pin Enable bit

1 = MCLR pin enabled; RE3 input pin disabled

0 = RE3 input pin enabled; MCLR disab led

bit 6-3 Unimplemented: Read as ‘0’

bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit

1 = Timer1 configured for low-power operation

0 = Timer1 configured for higher power operation

bit 1 PBADEN: PORTB A/D Enable bit

(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)

1 = PORTB<4:0> pins are configured as analog input channels on Reset

0 = PORTB<4 :0> pins are configured as digital I/O on Rese t

bit 0 CCP2MX: CCP2 MUX bit

1 = CCP2 input/output is multiplexed with RC1

0 = CCP2 input/output is multiplexed with RB3

R/P-1 R/P-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1

DEBUG XINST — — —LVP—STVREN

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 DEBUG: Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug

bit 6 XINST: Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5-3 Unimplemented: Read as ‘0’

bit 2 LVP: Single-Supply ICSP™ Enable bit

1 = Single-Supply ICSP enabled

0 = Single-Supply ICSP disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 STVREN: Stack Full/Underflow Reset Enable bit

1 = Stack full/underflow will cause Reset

0 = Stack full/underflow will not cause Reset

PIC18F2423/2523/4423/4523

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — —CP3

(1) CP2(1) CP1 CP0

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 Unimplemented: Read as ‘0’

bit 3 CP3: Code Prote c tion bit(1)

1 = Block 3 (006000-007FFFh) not code-protected

0 = Block 3 (006000-007FFFh) code-protected

bit 2 CP2: Code Prote c tion bit(1)

1 = Block 2 (004000-005FFFh) not code-protected

0 = Block 2 (004000-005FFFh) code-protected

bit 1 CP1: Code Prote c tion bit

1 = Block 1 (002000-003FFFh) not code-protected

0 = Block 1 (002000-003FFFh) code-protected

bit 0 CP0: Code Prote c tion bit

1 = Block 0 (000800-001FFFh) not code-protected

0 = Block 0 (000800-001FFFh) code-protected

Note 1: Unimplemented in PIC18LF2423/4423 devices; maintain this bit set.

R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

CPD CPB — — — — — —

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 CPD: Data EEPROM Code Protection bit

1 = Data EEPROM not code-protected

0 = Data EEPROM code-protected

bit 6 CPB: Boot Block Code Protection bit

1 = Boot Block (000000-0007FFh) not code-protected

0 = Boot Block (000000-0007FFh) code-protected

bit 5-0 Unimplemented: Read as ‘0’

PIC18F2423/2523/4423/4523

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — —WRT3

(1) WRT2(1) WRT1 WRT0

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRT3: Write Pr otection bit (1)

1 = Block 3 (006000-007FFFh) not write-protected

0 = Block 3 (006000-007FFFh) write-protected

bit 2 WRT2: Write Pr otection bit(1)

1 = Block 2 (004000-005FFFh) not write-protected

0 = Block 2 (004000-005FFFh) write-protected

bit 1 WRT1: Write Pr otection bit

1 = Block 1 (002000-003FFFh) not write-protected

0 = Block 1 (002000-003FFFh) write-protected

bit 0 WRT0: Write Pr otection bit

1 = Block 0 (000800-001FFFh) not write-protected

0 = Block 0 (000800-001FFFh) write-protected

Note 1: Unimplemented in PIC18LF2423/4423 devices; maintain this bit set.

R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0

WRTD WRTB WRTC(1) — — — — —

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 WRTD: Data EEPROM Write Protection bit

1 = Data EEPROM not write-protected

0 = Data EEPROM write-protected

bit 6 WRTB: Boot Block Write Protection bit

1 = Boot Block (000000-0007FFh) not write-protected

0 = Boot Block (000000-0007FFh) write-protected

bit 5 WRTC: Configuration Register Write Protection bit(1)

1 = Configuration registers (300000-3000FFh) not write-protected

0 = Configuration registers (300000-3000FFh) write-protected

bit 4-0 Unimplemented: Read as ‘0’

Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.

PIC18F2423/2523/4423/4523

U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1

— — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 Unimplemented: Read as ‘0’

bit 3 EBTR3: Table Read Protection bit(1)

1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks

0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks

bit 2 EBTR2: Table Read Protection bit(1)

1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks

0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks

bit 1 EBTR1: Table Read Protection bit

1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks

0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks

bit 0 EBTR0: Table Read Protection bit

1 = Block 0 (000800-001FFFh) not protected from table reads executed in other blocks

0 = Block 0 (000800-001FFFh) protected from table reads executed in other blocks

Note 1: Unimplemented in PIC18LF2423/4423 devices; maintain this bit set.

U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0

— EBTRB — — — — — —

bit 7 bit 0

Legend:

R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7 Unimplemented: Read as ‘0’

bit 6 EBTRB: Boot Block Table Read Protection bit

1 = Boot Block (000000-0007FFh) not protected from table reads executed in other blocks

0 = Boot Block (000000-0007FFh) protected from table reads executed in other blocks

bit 5-0 Unimplemented: Read as ‘0’

PIC18F2423/2523/4423/4523

RRRRRRRR

DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0

bit 7 bit 0

Legend:

R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 DEV3:DEV0: Device ID bits

1101 = PIC18F4423

1001 = PIC18F4523

0101 = PIC18F2423

0001 = PIC18F2523

bit 3-0 REV3:REV0: Revi si on ID bit s

These bits are used to indicate the device revision.

RRRRRRRR

DEV11(1) DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1)

bit 7 bit 0

Legend:

R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-0 DEV11:DEV4: Device ID bits(1)

These bits are used with the DEV3:DEV0 bits in the Device ID Register 1 to identify the

part number.

0001 0001 = PIC18LF2423/2523 devices

0001 0000 = PIC18LF4423/4523 devices

Note 1: These va lu es f or D EV11:DEV4 may be sha red wi th o ther d ev ic es. The s pe ci fic dev ic e is alwa ys ide nti fied

by using the entire DEV11:DEV0 bit sequence.

PIC18F2423/2523/4423/4523

23.2 Watchdog Timer (WDT)

For PIC18LF2423/2523/4423/4523 devices, the WDT

is driven by the INTRC source. When the WDT is

enabled , the c lock sour ce is al so enable d. The nom inal

WDT period is 4 ms and has the same stability as the

INTRC os cil la tor.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by bits in Configu-

ration Register 2H. Av ailable periods range from 4 ms

to 131.072 seconds (2.18 minutes). The WDT and

post scaler are cleare d when any of the following event s

occur: a SLEEP or CLRWDT instruction is executed, the

IRCF bits (OSCCON<6:4>) are changed or a clock

failure has occurred.

23.2.1 CONTROL REGISTER

Regi ste r 23-14 sh ow s t he WDT CON re gi s ter. This is a

readable and writab le register which co nt a ins a co ntro l

bit that allows software to override the WDT enable

Configuration bit, but only if the Configuration bit has

disabled the WDT.

FIGURE 23-1: WDT BLOCK DIAGRAM

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: Changing the setting of the IRCF bits

(OSCCON<6:4>) clears the WDT and

postscaler counts.

3: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

4: When the FSCM detects a clock failure

and switches clock sources, the WDT and

postscaler count s are cle are d.

INTRC Source

WDT

Wake-up from

Reset

WDT Counter

Program ma ble Pos tsca ler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

Power-Managed

Reset

All Device Resets

Sleep

÷128

Change on IRCF bits Modes

4 ms

PIC18F2423/2523/4423/4523

TABLE 23-2: SUMMARY OF WA TCHDOG TIMER REGISTERS

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —SWDTEN

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1)

1 = Watchdog Timer is on

0 = Watchdog Timer is off

Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

RCON IPEN SBOREN(1) —RI TO PD POR BOR 48

WDTCON — — — — — — —SWDTEN50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is

disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.

PIC18F2423/2523/4423/4523

23.3 Two-Speed Start-up

The Two-Speed Start-up feature helps to minimize the

latency period from oscillator st art-up to code execution

by allowing the microcontroller to use the INTOSC

oscillator as a clock source until the primary clock

source is available. It is enabled by setting the IESO

Configuration bit.

Two-Speed Start-up should be enabled only if the

primary oscillator mode is LP, XT, HS or HSPLL

(crystal-based modes). Other sources do not require

an OST start-up delay; for these, Two-Speed Start-up

should be disabled.

When ena bled, Resets and wake-ups from Sleep mode

cause the device to configure itself to run from the

internal oscillator block as the clock source, following

the time-out of the Power-up Timer after a Power-on

Reset. This allows almost immediate code execution

while the primary oscillator starts and the OST is run-

ning. On ce the OST times ou t, the device autom atically

switches to PRI_RUN mode.

To use a clock speed other than 1 MHz on wake from

Sleep mode, or when a FSCM event occurs, the

INTOSC clock source can be preset to provide that

speed by mo difying the IRCF 2 :IRC F0 bi ts imme dia tel y

after Rese t.

In all other power-managed modes, Two-Speed Start-

up is not used. The device will be clocked by the

currently selected clock source until the primary clock

source becomes available. The setting of the IESO bit

is ignored.

23.3.1 SPECIAL CONSIDERATIONS FOR

USING TWO-SPEED START-UP

While using the INTOSC oscillator in Two-Speed Start-

up, the device still obeys the normal command

sequences for entering power-managed modes,

including multiple SLEEP instructions (refer to

Section 3.1.4 “Multiple Sleep Commands”). In

practice, this means that user code can change the

SCS1:SCS0 bit settings or issue SLEEP instructions

before the OST times out. This would allow an

application to briefly wake-up, perform routine

“housekeeping” tasks and return to Sleep before the

device starts to operate from the primary oscillator.

User code can a lso c heck if t he primar y clo ck s our ce i s

currently providing the dev ic e c loc ki ng by ch eck ing the

status of the OSTS bit (OSCCON<3>). If the bit is set,

the pr im ary osc il lat or i s p rovi di ng the clock. Othe rwis e,

the internal oscillator block is providing the clock during

wake-up from Reset or Sleep mode.

FIGURE 23-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)

Q1 Q3 Q4

OSC1

Peripheral

Program PC PC + 2

INTOSC

PLL Clock

PC + 6

Output

Q3 Q4 Q1

CPU Clock

PC + 4

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

Wake from Interrupt Event

TPLL(1)

12 n-1n

Clock

OSTS bit Set

Transition(2)

Multiplexer

TOST(1)

PIC18F2423/2523/4423/4523

23.4 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the

microcontroller to continue operation in the event of an

external oscillator failure by automatically switching the

device clock to the internal oscillator block. The FSCM

function is ena bled b y s etting the FCMEN Configuration

bit.

When FSCM is enabled, the INTRC oscillator runs at

all times to mo nitor cloc ks to pe rip herals and pr ov id e a

backup clock in the event of a clock failure. Clock

monitoring (shown in Figure 23-3) is accomplished by

crea ting a s ample clock signal, which i s the I NTRC o ut-

put divided by 64. This allows ample time between

FSCM sample clocks for a peripheral clock edge to

occur. The peripheral device clock and the sample

clock are present ed as inpu ts to the Clock Monitor latch

(CM). The CM is set on the falling edge of the device

clock source, but cleared on the rising edge of the

sample clock.

FIGURE 23-3: FSCM BLOCK DIAGRAM

Clock failure is tested for on the falli ng edge of the sam-

ple clock. If a sample clock falling edge occurs while

CM is still set, a clock failure has been detected

(Figure 23-4). This causes the following:

• the FS CM generates an oscillat or fail interr upt by

setting bit, OSCFIF (PIR2<7>);

• the device clock source is switched to the internal

oscill ato r blo ck (O SCC ON i s not up dated to s how

the current clock source – this is the fail-safe

condition) and

•the WDT is reset.

The frequenc y from the internal oscillator block may not

be suf ficiently stable for timi ng sensitive applications. In

these c ases, it ma y be desirab le to sele ct another cl ock

configuration and enter an alternate power-managed

mode. Th is can be don e to attempt a p artial recov ery or

execute a controlled shutdown. See Section 3.1.4

“Multiple Sleep Commands” and Section 23.3.1

“Special Considerations for Using Two-Speed

Start-up” for more details.

To use a clock speed other than 1 MHz on wake from

Sleep mode, or when a FSCM event occurs, the

INTOSC clock source can be preset to provide that

speed by mo difying the IRCF 2 :IRC F0 bits immediatel y

after Reset.

The FS CM will dete ct failure s of the p rimary or sec ond-

ary clock sources only. If the internal oscillator block

fails, no failure woul d be detected, nor would any action

be possible.

23.4.1 FSCM AND THE WATCHDOG T IMER

Both the FSCM and the WDT are clocked by the

INTRC oscillator. Since the WDT operates with a

separate divider and counter, disabling the WDT has

no ef fect on the op eration of the IN TRC oscill ator when

the FSCM is enabled.

As already noted, the clock source is switched to the

INTOSC clock when a clock failure is detected.

Depending on the frequency selected by the

IRCF2:IRCF0 bits, this may mean a substantial change

in the speed of code execution. If the WDT is enabled

with a small prescale value, a decrease in clock speed

allows a WDT time-out to occur and a subsequent

device Reset. For this reason, Fail-Safe Clock Monitor

event s also res et the WDT and post scaler , all owing it to

start timing from when execution speed was changed

and dec reasing the li kelihoo d of an erroneou s time-out.

23.4.2 EXITING FAIL-SAFE OPER ATION

The fail-safe condition is terminated by either a device

Reset or by entering a power-managed mode. On

Reset, the controller starts the primary clock source

specified in Configuration Register 1H (with any

required start-up delays that are required for the oscil-

lator mode, such as OST or PLL timer). The INTOSC

multiplexer provides the device clock until the primary

clock source becomes ready (similar to a Two-Speed

Start-up). The clock source is then switched to the pri-

mary cl ock (in dic ate d by the OST S bit in th e O SCCO N

then resumes monitoring the pe ripheral clock.

The primary clock source may never become ready

durin g start-up . In thi s case, op eration is clocked by the

INTOSC mu ltiplexer. The OS CCON regist er will rema in

in its Reset state until a power-managed mode is

entered.

Peripheral

INTRC ÷ 64

(32 μs)

Clock Monitor

Latch (CM)

(edge-triggered)

Clock

Failure

Detected

Source

Clock

488 Hz

(2.048 ms)

PIC18F2423/2523/4423/4523

FIGURE 23-4: FSCM TIMING DIAGRAM

23.4.3 FSCM INTERRUPTS IN

POWER-MANAGED MODES

By entering a power-managed mode, the clock

multiplexer selects the clock source selected by the

OSCCON register. Fail-Safe Monitoring of the power-

manage d clock sou rce resumes in t he power-man aged

mode.

If an oscillator failure occurs during power-managed

operation, the subsequent events depend on whether

or not the oscillator failure interrupt is enabled. If

enabled (OSCFIF = 1), code execution will be clocked

by the INTOSC multiplexer. An automatic transition

back to the failed clock source will not occur.

If the interrupt is disabled, subsequent interrupts while

in Idle mode will cause the CPU to begin executing

instructions while being clocked by the INTOSC

source.

23.4.4 POR OR WAKE FROM SLEEP

The FS CM is designed to detect osc illator failu re at any

point after the primary clock has started. When the

primary device clock is in EC or RC mode, monitoring

can begin immediately following these events.

For oscillator modes involving a crystal or resonator

(HS, HSPLL, LP or XT), the situation is somewhat

different. Since the oscillator may require a start-up

time considerably longer than the FCSM sample clock

time, a false clock failure may be detected. To prevent

this, the internal os cillator bl ock is au tomatically config-

ured as the device cl ock and fun ctions unt il the primar y

clock is stable (the OST and PLL timers have timed

out). This is identical to Two-Speed Start-up mode.

Once the primary clock is stable, the INTRC returns to

its role as the FSCM source.

As noted in Section 23.3.1 “Special Considerations

for Using Two-Speed Start-up”, it is also possible to

select another clock c onfiguration and enter an alternate

power-managed mode while waiting for the primary

clock to become st able. When the new power-managed

mode is selected, the prima ry clock is disab led.

OSCFIF

CM Output

Device

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this

example have been chosen for clarity.

(Q)

CM Test CM Test CM Test

Note: The sa me logi c tha t prevents false oscill a-

tor failu re interrupt s on POR , or wake from

Sleep, will also prevent the detection of

the oscillator ’s failure to start at all follow-

ing these events. This can be avoided by

monitoring the OSTS bit and using a

timing routine to determine if the oscillator

is taking too long to start. Even so, no

oscillator failure interrupt will be flagged.

PIC18F2423/2523/4423/4523

23.5 Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PIC® MCU devices.

The user program memory is divided into five blocks.

One of these is a bo ot block of 2 Kbytes. The remainder

of the memory is divided into four blocks on binary

boundaries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 23-5 shows the program memory organization

for 16 a nd 32-Kbyte devic es an d th e specific code p ro-

tection bit associated with each block. The actual

locations of the bits are summarized in Table 23-3.

FIGURE 23-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18LF2423/2523/4423/4523

TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

300008h CONFIG5L — — — —CP3

(1) CP2(1) CP1 CP0

300009h CONFIG5H CPD CPB — — — — — —

30000Ah CONFIG6L — — — —WRT3

(1) WRT2(1) WRT1 WRT0

30000Bh CONFIG6H WRTD WRTB WRTC — — — — —

30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0

30000Dh CONFIG7H — EBTRB — — — — — —

Legend: Shaded cell s are uni mp lem ented.

Note 1: Unimplemented in PIC18LF2423/4423 devices; maintain this bit set.

MEMORY SIZE/DEVICE Block Code Protection

Controlled By:

16 Kbytes

(PIC18LF2423/4423) 32 Kbytes

(PIC18LF2523/4523) Address

Range

Boot Block Boot Block 000000h

0007FFh CPB, WRTB, EBTRB

Block 0 Block 0 000800h

001FFFh CP0, WRT0, EBTR0

Block 1 Block 1 002000h

003FFFh CP1, WRT1, EBTR1

Unimplemented

Read ‘0’s

Block 2 004000h

005FFFh CP2, WRT2, EBTR2

Block 3 006000h

007FFFh CP3, WRT3, EBTR3

Unimplemented

Read ‘0’s

1FFFFFh

(Unimplemented Memory Space)

PIC18F2423/2523/4423/4523

23.5.1 PROGRAM MEMORY

CODE PROTECTION

Any location in program memory may be read from, or

written to, using the table read and table write instruc-

tions. The device I D m ay b e r ead w it h table reads. The

Configuration registers may be read and written with

the table read and table write instructions.

In normal execution mode, the CPn bits have no direct

ef fect. CPn bits inhi bit external reads and writes. A block

of user memory may be protected fro m table writes if the

WRTn Configuration bit is ‘0’. The EBTRn bits control

table reads. For a block of u ser memory with the EBTRn

bit set to ‘0’, a table read instruction that executes from

within that block is allow ed to read . A table read instruc-

tion that executes from a l ocation out sid e of that blo ck is

not allowed to read and will result in reading ‘0’s.

Figures 23-6 through 23-8 illu strate t able write and t able

read protection.

FIGURE 23-6: TABLE WRITE (WRTn) DISALLOWED

Note: Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ st ate. Code p ro-

tection bits are only set to ‘1’ by a full chip

erase or block erase f unction. The full c hip

erase and block erase functions can only

be initiated via ICSP or an external

programmer.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

WRTB, EBTRB = 11

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLWT*

TBLP TR = 0008F Fh

PC = 001FFEh

TBLWT*

PC = 005FFEh

Results: All table writes disabled to Blockn whenever WRTn = 0.

PIC18F2423/2523/4423/4523

FIGURE 23-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

FIGURE 23-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD*

TBLP TR = 0008F Fh

PC = 003FFEh

Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

WR TB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD*

TBLPTR = 0008FFh

PC = 001FFEh

Results: Table reads permitted within Blockn, even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

PIC18F2423/2523/4423/4523

23.5.2 DATA EEPROM

CODE PROTECTION

The entire data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of data EEPROM.

WRTD inhibits internal and external writes to data

EEPROM. The CPU can always read data EEPROM

under n ormal op eration, re gardless o f the prot ection b it

settings.

23.5.3 CONFIGURATION REGISTER

PROTECTION

The Configuration registers can be write-protected.

The WRTC bit controls protection of the Configuration

registers. In normal execution mode, the WRTC bit is

readable only. WRTC can only be written via ICSP or

an external programmer.

23.6 ID Locations

Eight memory locations (200000h-200007h) are

designated as ID locations, where the user can store

checksum or other code identification numbers. These

locatio ns are b oth read abl e a nd w ri table during norma l

execution through the TBLRD and TBLWT instructions

or du r ing p r ogr am / ve rif y. T he I D lo ca t io ns c an b e r ead

when the de vice is code-protected.

23.7 In-Circuit Serial Programming

PIC18LF2423/2523/4423/4523 devices can be serially

progra mmed w hile in t he en d app licati on c ircuit. This i s

simply done with tw o lines for cl ock and data and thre e

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed. Block or bulk operations

are enabled for VDD of 3.0V to 5.5V

23.8 In-Circuit Debugger

When the DEBUG Configuration bit is programmed to

a ‘0’, the In-Circuit Debugger functionality is enabled.

This funct ion al lows s imple debug ging f unctio ns wh en

use d wi t h M PLA B® ID E. W h en the mi c ro c on tr ol le r h as

this featu r e ena ble d, so me reso urc es are not av ail abl e

for gene ral us e. Table 23-4 s hows whi ch res ource s ar e

required by the background debugger.

TABLE 23-4: DEBUGGER RESOURCES

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP/RE3, VDD,

VSS, RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip or one of

the third party develop m ent tool companies.

23.9 Single-Supply ICSP Programming

The LVP Configuration bit enables Single-Supply ICSP

Programming (formerly known as Low-Voltage ICSP

Programming or LVP). When Single-Supply Program-

ming is enabled, the microco ntroller can be programm ed

without requiring high voltage being applied to the

MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then

dedicated to controlling Program mode entry and is not

available as a general purpos e I/O pin.

While programming, using Single-Supply Programming

mode, VDD is applied to the MCLR/VPP/RE3 pin as in

normal execution mode. To enter Programming mode,

VDD is applied to the PGM pin.

If Single-Supply ICSP Programming mode will not be

used, the LVP bit can be cl eared. RB5/KBI1/PGM the n

become s a vaila ble as the dig ita l I/O p in, RB 5. The LVP

bit may be set or cleared only when using standard

high-voltage programming (VIHH applied to the MCLR/

VPP/RE3 pin). Once LVP has been disabled, only the

standard high-voltage programming is available and

must be used to program the device.

Memory that is not code -protected ca n be erased usin g

either a b lock erase, or erased ro w by row, then written

at any s pecified VDD. If co de-protected m emory is to be

erased, a block erase is required. If a block erase is to

be performed when using Low-Voltage Programming,

the device must be supplied with VDD of 3.0V to 5.5V.

I/O pins: RB6 , RB7

Sta ck: 2 levels

Program Memory: 512 bytes

Data Memory: 10 bytes

Note 1: High-voltage programming is always

available, regardless of the state of the

LVP bit or the PGM pin, by applying VIHH

to the MCLR pin.

2: By default, Single-Supply ICSP is

enabled in unprogrammed devices (as

supplied from Microchip) and erased

devices.

3: When Single-Supply Programming is

enabled, the RB5 pin can no longer be

used as a general purpose I/O pin.

4: When LVP is enabled, externally pull the

PGM pin to VSS to allow normal program

execution.

PIC18F2423/2523/4423/4523

24.0 INSTRUCTION SET SUMMARY

PIC18LF2423/2523/4423/4523 devices incorporate the

standard s et of 75 PIC18 core ins tructions, as well as an

extended set of 8 new instructions, for the optimization

of code that is recursive or that utili zes a software st ack.

The extended set is disc ussed later in this section.

24.1 Standard Instruction Set

The standard PIC18 instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration from these

PIC instru ction se ts. Most inst ruction s are a singl e pro-

gram me mory w ord (1 6 bit s), bu t there are four i nstru c-

tions that require two program memory locations.

Each single-word instruction is a 16-bit word divided

into an o pcode, whi ch specifies the instructi on type and

one or more operands, which further specify the

operation of the instruction.

The instruction set is highly orthog onal and is grouped

into four basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal operati ons

•Control operations

The PIC18 instruction set summary in Table 24-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 24-1 shows the opcode field

descriptions.

Most byte-oriented in str uct ions hav e t hree operands :

1. The file register (specified by ‘f’)

2. The destination of the result (specified by ‘d’)

3. The accessed me mory (specified by ‘a’)

The file register designator ‘f’ specifies which file

designator ‘d’ specifies where the result of the opera-

tion is to be placed. If ‘d’ is zero, the result is placed in

the WREG register. If ‘d’ is one, the result is placed in

the file register specified in the instruction.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed me mory (specified by ‘a’)

The bit field design ator ‘b’ sele cts the numb er of the bit

affected by the operation, while the file register

design ator ‘f’ represent s the numbe r of the fil e in w hich

the bit is located.

The literal ins truc tions may use so me of t he follo wing

operands:

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

The control ins tructions ma y use so me of the foll owing

operands:

• A program memory address (specified by ‘n’)

• The mode of the CALL or RETURN instructions

(specified by ‘s’)

• The mode of the table read and table write

ins tructions (specif ied by ‘m’)

• No operand required

(specified by ‘—’)

All instructions are a single word, except for four

double-word instructions. These instructions were

made double-word to contain the required information

in 32 bits. In the second word, the 4 MSbs are ‘1’s. If

this second word is executed as an instruction (by

it se lf), it will exe cu te as a NOP.

All single-word instructions are executed in a single

inst ruc tion c yc le , un le ss a conditio nal test is true or th e

program counter is changed as a result of the instruc-

tion. In th ese cases, the execution takes two i nstruction

cycle s, with the addit ional instru ction cyc le(s) exec uted

as a NOP.

The doub le-word inst ructions exe cute in two ins truction

cycles.

One in struction cycle consist s of f our oscil lator peri ods.

Thus, for an oscillator frequency of 4 MHz, the normal

inst ruction ex ecution ti me is 1 μs. If a conditi onal test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 μs.

Two-word branch instructions (if true) would take 3 μs.

Figur e 24-1 show s the gener al format s that the ins truc-

tions can have. All examples use the convention ‘nnh’

to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 24-2,

lists the standard instructions recognized by the

Microchip MPASMTM Assembler.

Section 24.1.1 “Standard Instruction Set” provides

a description of each instruction.

PIC18F2423/2523/4423/4523

TABLE 24-1: OPCODE FIELD DESCRIPTIONS

Field Description

aRAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb Bit address within an 8-bit file register (0 to 7).

BSR Bank Select Register. Used to select the current RAM bank.

C, DC, Z, OV, N ALU St atus bits: Carry, Digit Carry, Zero, Overflow, Negative.

dDestination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest Destination: either the WREG register or the specified register file location.

f8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

fs12-bit Register file address (000h to FFFh). This is the source address.

fd12-bit Register file address (000h to FFFh). This is the destination address.

GIE Global Interrupt Enable bit.

kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

label Label name.

mm The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*No change to register (such as TBLPTR with table reads and writes)

*+ Post-Increment register (suc h as TBLPTR with table reads and writes)

*- Post-Decrement register (such as TBLPTR with table reads and writes)

+* Pre-Increment register (such as TBLPTR with table reads and writes)

nThe relative address (2’s complement number) for relative branch instructions or the direct address for

Call/Branch and Return instructions.

PC Program Counter.

PCL Program Counter Low Byte.

PCH Program Counter High Byte.

PCLATH Program Counter High Byte Latch.

PCLATU Program Counter Upper Byte Latch.

PD Power-Down bit.

PRODH Product of Multiply High Byte.

PRODL Product of Multiply Low Byte.

sFast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR 21-bit Table Pointer (points to a program memory location).

TABLAT 8-bit Table Latch.

TO Time-out bit.

TOS Top-of-Stack.

uUnused or unchanged.

WDT Watchdog Ti m er.

WREG Working register (accumulator).

xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for

compatibility with all Microchip software tools.

zs7-bit offset value for indirect addressing of register files (source).

zd7-bit offset value for indirect addressing of register files (destination).

{ } Optional argument.

[text] Indicates an indexed address.

(text) The contents of text.

[expr]<n> Specifies bit n of the register indicated by the pointer expr.

→Assigned to.

< > Register bit field.

∈In the set of.

italics User-defined term (font is Courier New).

PIC18F2423/2523/4423/4523

FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10 9 8 7 0

d = 0 for result destination to be WREG register

OPCODE d a f (FILE #)

d = 1 for result destination to be file register (f)

a = 0 to force Access Bank

Bit-oriented file register operations

15 12 11 9 8 7 0

OPCODE b (BIT #) a f (FILE #)

b = 3-bit position of bit in file register (f)

Literal operations

15 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Byte to Byte move operations (2-word)

15 12 11 0

OPCODE f (Source FILE #)

CALL, GOTO and Branch operations

15 8 7 0

OPCODE n<7:0> (literal)

n = 20-bit immediate value

a = 1 for BSR to select bank

f = 8-bit file register address

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

15 12 11 0

1111 n<19:8> (literal)

15 12 11 0

1111 f (Destination FILE #)

f = 12-bit file register address

Control operations

Example Instruction

ADDWF MYREG, W, B

MOVFF MYREG1, MYREG2

BSF MYREG, bit, B

MOVLW 7Fh

GOTO Label

15 8 7 0

OPCODE n<7:0> (literal)

15 12 11 0

1111 n<19:8> (literal)

CALL MYFUNC

15 11 10 0

OPCODE n<10:0> (literal)

S = Fast bit

BRA MYFUNC

15 8 7 0

OPCODE n<7:0> (liter a l ) BC MYFUNC

PIC18F2423/2523/4423/4523

TABLE 24-2: PIC18FXXXX INSTRUCTION SET

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected Notes

MSb LSb

BYTE-ORIENTED OPERATIONS

ADDWF

ADDWFC

ANDWF

CLRF

COMF

CPFSEQ

CPFSGT

CPFSLT

DECF

DECFSZ

DCFSNZ

INCF

INCFSZ

INFSNZ

IORWF

MOVF

MOVFF

MOVWF

MULWF

NEGF

RLCF

RLNCF

RRCF

RRNCF

SETF

SUBFWB

SUBWF

SUBWFB

SWAPF

TSTFSZ

XORWF

f, d, a

f, a

f, d, a

f, a

f, d, a

fs, fd

f, a

f, d, a

f, a

f, d, a

f, a

f, d, a

Add WREG and f

Add WREG and Carry bit to f

AND WREG with f

Clear f

Complement f

Compare f with WREG, skip =

Compare f with WREG, skip >

Compare f with WREG, skip <

Decrement f

Decrement f, Skip if 0

Decrement f, Skip if Not 0

Increment f

Increment f, Skip if 0

Increment f, Skip if Not 0

Inclusive OR WREG with f

Move f

Move fs (sour ce) to 1st word

fd (destination) 2nd word

Move WREG to f

Multiply WREG with f

Negate f

Rotate Left f through Carry

Rotate Lef t f ( N o C a r ry)

Rotate Right f through Carry

Rotate Right f (No Carry)

Set f

Subtract f from WREG with

borrow

Subtract WREG fro m f

Subtract WREG from f with

borrow

Swap nibbles in f

Test f, skip if 0

Exclusive OR WREG with f

1 (2 or 3)

0010

0001

0110

0001

0110

0000

0010

0100

0010

0011

0100

0001

0101

1100

1111

0110

0000

0110

0011

0100

0011

0100

0110

0101

0011

0110

0001

01da0

0da

01da

101a

11da

001a

010a

000a

01da

11da

10da

11da

10da

00da

ffff

111a

001a

110a

01da

00da

100a

01da

11da

10da

011a

10da

ffff

C, D C , Z, OV, N

Z, N

None

C, D C , Z, OV, N

None

C, D C , Z, OV, N

None

Z, N

None

C, D C , Z, OV, N

C, Z, N

Z, N

C, Z, N

Z, N

None

C, D C , Z, OV, N

None

Z, N

1, 2

1,2

1, 2

1, 2, 3, 4

1, 2

1, 2, 3, 4

1, 2

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘ 1’ f or a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the i nstruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

PIC18F2423/2523/4423/4523

BIT-ORIENTED OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a

f, d, a

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

Bit Toggle f

1 (2 or 3)

1001

1000

1011

1010

0111

bbba

ffff

None

1, 2

3, 4

1, 2

CONTROL OPERATIONS

BNC

BNN

BNOV

BNZ

BOV

BRA

CALL

CLRWDT

DAW

GOTO

NOP

POP

PUSH

RCALL

RESET

RETFIE

RETLW

RETURN

SLEEP

n, s

—

Branch if Carry

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call subroutine 1st word

2nd word

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1st word

2nd word

No Operation

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

Software device Reset

Return from interrupt enable

Return with literal in WREG

Return from Subroutine

Go into Standby mode

1 (2)

1110

1101

1110

1111

0000

1110

1111

0000

1111

0000

1101

0000

0010

0110

0011

0111

0101

0001

0100

0nnn

0000

110s

kkkk

0000

1111

kkkk

0000

xxxx

0000

1nnn

0000

1100

0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

kkkk

0001

0000

nnnn

kkkk

0100

0111

kkkk

0000

xxxx

0110

0101

nnnn

1111

000s

kkkk

001s

0011

None

TO, PD

None

All

GIE/GIEH,

PEIE/GIEL

None

TO, PD

TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘ 1’ f or a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the i nstruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

PIC18F2423/2523/4423/4523

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

f, k

Add literal and WREG

AND literal with WREG

Inclusive OR literal with WREG

Move literal (12-bit) 2nd word

to FSR(f) 1st word

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

Exclusive OR literal with WREG

0000

1110

1111

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

00ff

kkkk

0000

kkkk

C, D C , Z, OV, N

Z, N

None

C, D C , Z, OV, N

Z, N

DATA MEMORY ↔ PROGRAM MEMOR Y OPE R ATIONS

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

0000

1000

1001

1010

1011

1100

1101

1110

1111

None

TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘ 1’ f or a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the i nstruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

PIC18F2423/2523/4423/4523

24.1.1 STANDARD INSTRUCTION SET

ADDLW ADD Literal to W

Syntax: ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1111 kkkk kkkk

Description: The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Wri te to W

Example: ADDLW 15h

Before Instruction

W = 10h

After Instruction

W = 25h

ADDWF ADD W to f

Syntax: ADDWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) + (f) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01da ffff ffff

Description: Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: ADDWF REG, 0, 0

Before Instruction

W = 17h

REG = 0C2h

After Instruction

W = 0D9h

REG = 0C2h

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then be comes: {label} inst ruction argument(s).

PIC18F2423/2523/4423/4523

ADDWFC ADD W and Carry bit to f

Syntax: ADDWFC f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) + (f) + (C) → dest

Status Affected: N,OV, C, DC, Z

Encoding: 0010 00da ffff ffff

Description: Add W, the Carry flag and data memory

location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: ADDWFC REG, 0, 1

Before Instruction

Carry bit = 1

REG = 02h

W=4Dh

After Instruction

Carry bit = 0

REG = 02h

W = 50h

ANDLW AND Literal with W

Syntax: ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. k → W

Status Affected: N, Z

Encoding: 0000 1011 kkkk kkkk

Description: The contents of W are ANDed with the

8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ Proces s

Data Write to W

Example: ANDLW 05Fh

Before Instruction

W=A3h

After Instruction

W = 03h

PIC18F2423/2523/4423/4523

ANDWF AND W with f

Syntax: ANDWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .AND. (f) → dest

Status Affected: N, Z

Encoding: 0001 01da ffff ffff

Description: The contents of W are ANDed with

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: ANDWF REG, 0, 0

Before Instruction

W = 17h

REG = C2h

After Instruction

W = 02h

REG = C2h

BC Branch if Carry

Syntax: BC n

Operands: -128 ≤ n ≤ 127

Operation: if Carry bit is ‘1’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0010 nnnn nnnn

Description: If the Carry bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BC 5

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 1;

PC = address (HERE + 12)

If Carry = 0;

PC = address (HERE + 2)

PIC18F2423/2523/4423/4523

BCF Bit Clear f

Syntax: BCF f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: 0 → f

Status Affected: None

Encoding: 1001 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: BCF FLAG_REG, 7, 0

Before Instruction

FLAG_R EG = C7 h

After Instruction

FLAG_REG = 47h

BN Branch if Negative

Syntax: BN n

Operands: -128 ≤ n ≤ 127

Operation: if Negative bit is ‘1’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0110 nnnn nnnn

Description: If the Negative bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 1;

PC = address (Jump)

If Negative = 0;

PC = address (HERE + 2)

PIC18F2423/2523/4423/4523

BNC Branch if Not Carry

Syntax: BNC n

Operands: -128 ≤ n ≤ 127

Operation: if Carry bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0011 nnnn nnnn

Description: If the Carry bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. S ince the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNC Jump

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 0;

PC = address (Jump)

If Carry = 1;

PC = address (HERE + 2)

BNN Branch if Not Negative

Syntax: BNN n

Operands: -128 ≤ n ≤ 127

Operation: if Negative bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0111 nnnn nnnn

Description: If the Negative bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 0;

PC = address (Jump)

If Negative = 1;

PC = address (HERE + 2)

PIC18F2423/2523/4423/4523

BNOV Branch if Not Overflow

Syntax: BNOV n

Operands: -128 ≤ n ≤ 127

Operation: if Overflow bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0101 nnnn nnnn

Description: If the Overflow bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. S ince the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 0;

PC = address (Jump)

If Overflow = 1;

PC = address (HERE + 2)

BNZ Branch if Not Zero

Syntax: BNZ n

Operands: -128 ≤ n ≤ 127

Operation: if Zero bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0001 nnnn nnnn

Description: If the Zero bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BNZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 0;

PC = address (Jump)

If Zero = 1;

PC = address (HERE + 2)

PIC18F2423/2523/4423/4523

BRA Unconditional Branch

Syntax: B RA n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1101 0nnn nnnn nnnn

Description: Add the 2’s complement number ‘2n’ to

the PC. Since the PC will have

incremented to fetch the next instruction,

the new address will be PC + 2 + 2n. This

instruction is a two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

Example: HERE BRA Jump

Before Instruction

PC = address (HERE)

After Instruction

PC = address (Jump)

BSF Bit Set f

Syntax: BSF f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: 1 → f

Status Affected: None

Encoding: 1000 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: BSF FLAG_REG, 7, 1

Before Instruction

FLAG_REG = 0Ah

After Instruction

FLAG_REG = 8Ah

PIC18F2423/2523/4423/4523

BTFSC Bit Test File, Skip if Clear

Syntax: BTFSC f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: skip if (f) = 0

Status Affected: None

Encoding: 1011 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 24.2 .3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE

FALSE

TRUE

BTFSC

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (TRUE)

If FLAG<1> = 1;

PC = address (FALSE)

BTFSS Bit Test File, Skip if Set

Syntax: BTFSS f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation: skip if (f) = 1

Status Affected: None

Encoding: 1010 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructi ons in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE

FALSE

TRUE

BTFSS

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (FALSE)

If FLAG<1> = 1;

PC = address (TRUE)

PIC18F2423/2523/4423/4523

BTG Bit Toggle f

Syntax: BTG f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation: (f) → f

Status Affected: None

Encoding: 0111 bbba ffff ffff

Description: Bit ‘b’ in data memory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details .

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: BTG PORTC, 4, 0

Before Instruction:

PORTC = 0111 0101 [75h]

After Instruc t ion:

PORTC = 0110 0101 [65h]

BOV Branch if Ov erflow

Syntax: BOV n

Operands: -128 ≤ n ≤ 127

Operation: if Overflow bit is ‘1’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0100 nnnn nnnn

Description: If the Overflow bit is ‘1’, then th e

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 1;

PC = address (Jump)

If Overflow = 0;

PC = address (HERE + 2)

PIC18F2423/2523/4423/4523

BZ Branch if Zero

Syntax: BZ n

Operands: -128 ≤ n ≤ 127

Operation: if Zero bit is ‘1’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0000 nnnn nnnn

Description: If the Zero bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruct ion.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump: Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data Write to PC

operation No

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’ Process

Data No

operation

Example: HERE BZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 1;

PC = address (Jump)

If Zero = 0;

PC = address (HERE + 2)

CALL Subroutine Call

Syntax: CALL k {,s}

Operands: 0 ≤ k ≤ 1048575

s ∈ [0,1]

Operation: (PC) + 4 → TOS,

k → PC<20:1>

if s = 1

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>) 1110

1111

110s

k19kkk

k7kkk

kkkk

kkkk0

kkkk8

Description: Subroutine call of entire 2-Mbyte

memory range. First, return address

(PC + 4) is pushed onto the return

stack. If ‘s’ = 1, the W, STAT US and

BSR registers are also pushed into their

respective shadow registers, WS,

STATUSS and BSRS. If ‘s’ = 0, no

update occurs (default). Then, the

20-bit value ‘k’ is loaded into PC<20:1>.

CALL is a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>, PUSH PC to

stack Read literal

‘k’<19:8>,

Write to PC

operation No

operation

Example: HERE CALL THERE, 1

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS = address (HERE + 4)

WS = W

BSRS = BSR

STATUSS= STATUS

PIC18F2423/2523/4423/4523

CLRF Clear f

Syntax: CLRF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: 000h → f

1 → Z

Status Affected: Z

Encoding: 0110 101a ffff ffff

Description: Clears the contents of the specified

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: CLRF FLAG_REG, 1

Before Instruction

FLAG_REG = 5Ah

After Instruction

FLAG_REG = 00h

CLRWDT Clear Watchdog Timer

Syntax: CLRWDT

Operands: None

Operation: 000h → WDT,

000h → WDT postscaler,

1 → TO,

1 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits, TO

and PD, are set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data No

operation

Example: CLRWDT

Before Instruction

WDT Counter = ?

After Instruction

WDT Counter = 00h

WDT Postscaler = 0

TO =1

PD =1

PIC18F2423/2523/4423/4523

COMF Complement f

Syntax: COMF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) → dest

Status Affected: N, Z

Encoding: 0001 11da ffff ffff

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: COMF REG, 0, 0

Before Instruction

REG = 13h

After Instruction

REG = 13h

W=ECh

CPFSEQ Compare f with W, Skip if f = W

Syntax: CPFSEQ f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) = (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 001a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE CPFSEQ REG, 0

NEQUAL :

EQUAL :

Before Instruction

PC Address = HERE

W=?

REG = ?

After Instruction

If REG = W;

PC = Address (EQUAL)

If REG ≠ W;

PC = Address (NEQUAL)

PIC18F2423/2523/4423/4523

CPFSGT Compare f with W, Skip if f > W

Syntax: CPFSGT f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) > (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 010a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of the W by

performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

contents of WREG, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruct ion.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG > W;

PC = Address (GREATER)

If REG ≤ W;

PC = Address (NGREATER)

CPFSLT Compare f with W, Skip if f < W

Syntax: CPFSLT f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) < (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 000a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruct ion.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE CPFSLT REG, 1

NLESS :

LESS :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG < W;

PC = Address (LESS)

If REG ≥ W;

PC = Address (NLESS)

PIC18F2423/2523/4423/4523

DAW Decimal Adjust W Register

Syntax: DAW

Operands: None

Operation: If [W<3:0> > 9] or [DC = 1] then

(W<3:0>) + 6 → W<3:0>;

else

(W<3:0>) → W<3:0>;

If [W <7:4> + DC > 9] or [C = 1] the n

(W<7:4>) + 6 + DC → W<7:4> ;

else

(W<7:4>) + DC → W<7:4>

Status Affected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example 1:

DAW

Before Instruction

W=A5h

C=0

DC = 0

After Instruction

W = 05h

C=1

DC = 0

Example 2:

Before Instruction

W=CEh

C=0

DC = 0

After Instruction

W = 34h

C=1

DC = 0

DECF Decremen t f

Syntax: DECF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest

Status Affected: C, DC, N, OV, Z

Encoding: 0000 01da ffff ffff

Description: Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: DECF CNT, 1, 0

Before Instruction

CNT = 01h

Z=0

After Instruction

CNT = 00h

Z=1

PIC18F2423/2523/4423/4523

DECFSZ Decrement f, Skip if 0

Syntax: DECFSZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest,

skip if result = 0

Status Affected: None

Encoding: 0010 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE DECFSZ CNT, 1, 1

GOTO LOOP

CONTINUE

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT – 1

If CNT = 0;

PC = Address (CONTINUE)

If CNT ≠0;

PC = Address (HERE + 2)

DCFSNZ Decrement f, Skip if Not 0

Syntax: DCFSNZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest,

skip if result ≠ 0

Status Affected: None

Encoding: 0100 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE DCFSNZ TEMP, 1, 0

ZERO :

NZERO :

Before Instruction

TEMP = ?

After Instruction

TEMP = TEMP – 1,

If TEMP = 0;

PC = Address (ZERO)

If TEMP ≠0;

PC = Address (NZERO)

PIC18F2423/2523/4423/4523

GOTO Unconditional Branch

Syntax: GOTO k

Operands: 0 ≤ k ≤ 1048575

Operation: k → PC<20:1>

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>) 1110

1111

k19kkk

k7kkk

kkkk

kkkk0

kkkk8

Description: GOTO allows an unconditional branch

anywhere within entire 2-Mbyte memory

range. The 20-bit value ‘k’ is loaded into

PC<20:1>. GOTO is always a two-cycle

instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>, No

operation Read literal

‘k’<19:8>,

Write to PC

operation No

operation

Example: GOTO THERE

After Instruction

PC = Address (THERE)

INCF Increment f

Syntax: INCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest

Status Affected: C, DC, N, OV, Z

Encoding: 0010 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: INCF CNT, 1, 0

Before Instruction

CNT = FFh

Z=0

C=?

DC = ?

After Instruction

CNT = 00h

Z=1

C=1

DC = 1

PIC18F2423/2523/4423/4523

INCFSZ Increment f, Skip if 0

Syntax: INCFSZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest,

skip if result = 0

Status Affected: None

Encoding: 0011 11da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE INCFSZ CNT, 1, 0

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT + 1

If CNT = 0;

PC = Address (ZERO)

If CNT ≠0;

PC = Address (NZERO)

INFSNZ Increment f, Skip if Not 0

Syntax: INFSNZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest,

skip if result ≠ 0

Status Affected: None

Encoding: 0100 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE INFSNZ REG, 1, 0

ZERO

NZERO

Before Instruction

PC = Address (HERE)

After Instruction

REG = REG + 1

If REG ≠0;

PC = Address (NZERO)

If REG = 0;

PC = Address (ZERO)

PIC18F2423/2523/4423/4523

IORLW Inclusive OR Literal with W

Syntax: IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → W

Status Affected: N, Z

Encoding: 0000 1001 kkkk kkkk

Description: The contents of W are ORed with the

eight-bit literal ‘k’. The result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to W

Example: IORLW 35h

Before Instruction

W=9Ah

After Instruction

W=BFh

IORWF Inclusive OR W with f

Syntax: IORWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .OR. (f) → dest

Status Affected: N, Z

Encoding: 0001 00da ffff ffff

Description: Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: IORWF RESULT, 0, 1

Before Instruction

RESULT = 13h

W = 91h

After Instruction

RESULT = 13h

W = 93h

PIC18F2423/2523/4423/4523

LFSR Load FSR

Syntax: LF SR f, k

Operands: 0 ≤ f ≤ 2

0 ≤ k ≤ 4095

Operation: k → FSRf

Status Affected: None

Encoding: 1110

1111

1110

0000

00ff

k7kkk

k11kkk

kkkk

Description: The 12-bit literal ‘k’ is loaded into the

File Select Register pointed to by ‘f’.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ MSB Process

Data Write

literal ‘k’

MSB to

FSRfH

Decode Read literal

‘k’ L S B Process

Data Write literal

‘k’ to FSRfL

Example: LFSR 2, 3ABh

After Instruction

FSR2H = 03h

FSR2L = ABh

MOVF Move f

Syntax: MOVF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: f → dest

Status Affected: N, Z

Encoding: 0101 00da ffff ffff

Description: The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write W

Example: MOVF REG, 0, 0

Before Instruction

REG = 22h

W=FFh

After Instruction

REG = 22h

W = 22h

PIC18F2423/2523/4423/4523

MOVFF Move f to f

Syntax: MOVFF fs,fd

Operands: 0 ≤ fs ≤ 4095

0 ≤ fd ≤ 4095

Operation: (fs) → fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.) 1100

1111

ffff

ffffs

ffffd

Description: The contents of source register ‘fs’ are

moved to destination register ‘fd’.

Location of source ‘f s’ can be anywhere

in the 4096-byte data space (000h to

FFFh) and location of destination ‘fd’

can also be anywhere from 000h to

FFFh.

Either source or destination can be W

(a useful special situation).

MOVFF is particularly useful for

transferring a dat a memory location to a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Words: 2

Cycles: 2 (3)

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

(src)

Process

Data No

operation

Decode No

operation

No dummy

read

operation Write

(dest)

Example: MOVFF REG1, REG2

Before Instruction

REG1 = 33h

REG2 = 11h

After Instruction

REG1 = 33h

REG2 = 33h

MOVLB Move L iteral to Low Nibble in BSR

Syntax: MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → BSR

Status Affected: None

Encoding: 0000 0001 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into the

Bank Select Register (BSR). The value

of BSR<7:4> always remains ‘0’,

regardless of the value of k7:k4.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data W rite literal

‘k’ to BSR

Example: MOVLB 5

Before Instruction

BSR Register = 02h

After Instruction

BSR Register = 05h

PIC18F2423/2523/4423/4523

MOVLW Move Literal to W

Syntax: MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → W

Status Affected: None

Encoding: 0000 1110 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to W

Example: MOVLW 5Ah

After Instruction

W=5Ah

MOVWF Move W to f

Syntax: MOVWF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1 ]

Operation: ( W) → f

Status Affected: None

Encoding: 0110 111a ffff ffff

Description: Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, t he BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index ed

Literal Offset Mode ” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: MOVWF REG, 0

Before Instruction

W=4Fh

REG = FFh

After Instruction

W=4Fh

REG = 4Fh

PIC18F2423/2523/4423/4523

MULLW Multiply Literal with W

Syntax: MULLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) x k → PRO DH : PRO D L

Status Affected: None

Encoding: 0000 1101 kkkk kkkk

Description: An unsigned mu ltiplication is carried

out between the contents of W and the

8-bit literal ‘k’. The 16-bit result is

placed in the PRODH:PRODL register

pair. PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither Overflow nor Carry is

possible in this operation. A Zero result

is possible but not detected.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ P rocess

Data Write

registers

PRODH:

PRODL

Example: MULLW 0C4h

Before Instruction

W=E2h

PRODH = ?

PRODL = ?

After Instruction

W=E2h

PRODH = ADh

PRODL = 08h

MULWF Multiply W with f

Syntax: MULW F f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (W) x (f) → PRODH:PRODL

Status Affected: None

Encoding: 0000 001a ffff ffff

Description: An unsigned multiplication is carried

out between the contents of W and the

result is stored in the PRODH:PRODL

high byte. Both W and ‘f’ are

unchanged.

None of the Status flags are affected.

Note that neither Overflow nor Carry is

possible in this operation. A Zero

result is possible but not detected.

If ‘a’ is ‘0’, the Access Ban k is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

registers

PRODH:

PRODL

Example: MULWF REG, 1

Before Instruction

W=C4h

REG = B5h

PRODH = ?

PRODL = ?

After Instruction

W=C4h

REG = B5h

PRODH = 8Ah

PRODL = 94h

PIC18F2423/2523/4423/4523

NEGF Negate f

Syntax: NEGF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: ( f ) + 1 → f

Status Affected: N, OV, C, DC, Z

Encoding: 0110 110a ffff ffff

Description: Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: NEGF REG, 1

Before Instruction

REG = 0011 1010 [3Ah]

After Instruction

REG = 1100 0110 [C6h]

NOP No Operation

Syntax: NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

Description: No operation.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation

Example:

None.

PIC18F2423/2523/4423/4523

POP Pop Top of Return Stack

Syntax: POP

Operands: None

Operation: (TOS) → bit bucket

Status Affected: None

Encoding: 0000 0000 0000 0110

Description: The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the return

stack to incorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation POP TOS

value No

operation

Example: POP

GOTO NEW

Before Instruction

TOS = 0031A2h

Stack (1 level down) = 014332h

After Instruction

TOS = 014332h

PC = NEW

PUSH Push Top of Return Stack

Syntax: PUSH

Operands: None

Operation: (PC + 2) → TOS

Status Affected: None

Encoding: 0000 0000 0000 0101

Description: The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode PUSH

PC + 2 onto

return stack

operation No

operation

Example: PUSH

Before Instruction

TOS = 345Ah

PC = 0124h

After Instruction

PC = 0126h

TOS = 0126h

Stack (1 level down) = 345Ah

PIC18F2423/2523/4423/4523

RCALL Relative Call

Syntax: RCALL n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 → TOS,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1101 1nnn nnnn nnnn

Description: Subroutine call with a jump up to 1K

from the current location. First, return

address (PC + 2) is pushed onto the

stack. Then, add the 2’s complement

number ‘2n’ to the PC. S ince the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruct ion.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

PUSH PC to

stack

Process

Data Write to PC

operation No

operation

Example: HERE RCALL Jump

Before Instruction

PC = Address (HERE)

After Instruction

PC = Address (Jump)

TOS = Address (HERE + 2)

RESET Reset

Syntax: RESET

Operands: None

Operation: Reset all registers and flags that are

affected by a MCLR Reset.

Status Affected: All

Encoding: 0000 0000 1111 1111

Description: This instruction provides a way to

execute a MCLR Reset in software.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Start

Reset No

operation No

operation

Example: RESET

After Instruction

Registers = Reset V alue

Flags* = Reset Value

PIC18F2423/2523/4423/4523

RETFIE Return from Interrupt

Syntax: RETFIE {s}

Operands: s ∈ [0,1]

Operation: (TOS) → PC,

1 → GIE/GI EH o r PEIE/GIE L

if s = 1

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

Status Affected: GIE/GIEH, PEIE/GIEL.

Encoding: 0000 0000 0001 000s

Description: Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers, WS,

STATUSS and BSRS, are loaded into

their corresponding registers, W,

STATUS and BSR. If ‘s’ = 0, no update

of these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation POP PC

from stack

Set GIEH or

GIEL

operation No

operation

Example: RETFIE 1

After Interrupt

PC = TOS

W=WS

BSR = BSRS

STATUS = STATUSS

GIE/ GIEH, PEIE/GIEL = 1

RETLW Return Literal to W

Syntax: RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → W,

(TOS) → PC,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 1100 kkkk kkkk

Description: W is loaded with the eight-bit literal ‘k’.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data POP PC

from stack,

Write to W

operation No

operation

Example:

CALL TABLE ; W contains table

; offset value

; W now has

; table value

TABLE

ADDWF PCL ; W = offset

RETLW k0 ; Begin table

RETLW k1 ;

RETLW kn ; End of table

Before Instruction

W = 07h

After Instruction

W = value of kn

PIC18F2423/2523/4423/4523

RETURN Return from Subroutine

Syntax: RETURN {s}

Operands: s ∈ [0,1]

Operation: (TOS) → PC

if s = 1

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR ,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers, WS, STATUSS and BSRS,

are loaded into their corresponding

registers, W, STATUS and BSR. If

‘s’ = 0, no update of these registers

occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data POP PC

from stack

operation No

operation

Example: RETURN

After Instruc t ion:

PC = TOS

RLCF Rotate Left f through Carry

Syntax: RLCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n + 1>,

(f<7>) → C,

Status Affected: C, N, Z

Encoding: 0011 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used to

select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5F h). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: RLCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=1100 1100

C=1

Cregister f

PIC18F2423/2523/4423/4523

RLNCF Rotate Left f (No Carry)

Syntax: RLNCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n + 1>,

(f<7>) → dest<0>

Status Affected: N, Z

Encoding: 0100 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the res ult is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh ). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructi ons in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: RLNCF REG, 1, 0

Before Instruction

REG = 1010 1011

After Instruction

REG = 0101 0111

RRCF Rot ate Right f through Carry

Syntax: RRCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n – 1>,

(f<0>) → C,

Status Affected: C, N, Z

Encoding: 0011 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: RRCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=0111 0011

C=0

Cregister f

PIC18F2423/2523/4423/4523

RRNCF Rotate Right f (No Carry)

Syntax: RRNCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n – 1>,

(f<0>) → dest<7>

Status Affected: N, Z

Encoding: 0100 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If ‘a’

is ‘1’, then the bank will be selected as

per the BSR value (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: RRNCF REG, 1, 0

Before Instruction

REG = 1101 0111

After Instruction

REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before Instruction

W=?

REG = 1101 0111

After Instruction

W=1110 1011

REG = 1101 0111

SETF Set f

Syntax: SETF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: FFh → f

Status Affected: None

Encoding: 0110 100a ffff ffff

Description: The contents of the specified register

are set to FFh.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write

Example: SETF REG, 1

Before Instruction

REG = 5Ah

After Instruction

REG = FFh

PIC18F2423/2523/4423/4523

SLEEP Enter Sleep Mode

Syntax: SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT postscaler,

1 → TO ,

0 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0011

Description: The Power-Down status bit (PD) is

cleared. The Time-out status bit (TO)

is set. Watchdog T imer and its

postscaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation Process

Data Go to

Sleep

Example: SLEEP

Before Instruction

TO =?

PD =?

After Instruction

TO =1 †

PD =0

† If WDT causes wake-up, this bit is cleared.

SUBFWB Subtract f from W with Borrow

Syntax: SUBFWB f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W ) – (f) – (C) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 01da ffff ffff

Description: Subtract register ‘f’ and Carry flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored in

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and t he extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instruct ions in In dexed Literal O ffset

Mode” f or details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: SUBFWB REG, 1, 0

Before Instruction

REG = 3

W=2

C=1

After Instruction

REG = FF

W=2

C=0

Z=0

N = 1 ; result is negative

Example 2: SUBFWB REG, 0, 0

Before Instruction

REG = 2

W=5

C=1

After Instruction

REG = 2

W=3

C=1

Z=0

N = 0 ; result is positive

Example 3: SUBFWB REG, 1, 0

Before Instruction

REG = 1

W=2

C=0

After Instruction

REG = 0

W=2

C=1

Z = 1 ; result is zero

N=0

PIC18F2423/2523/4423/4523

SUBLW Subtract W from Literal

Syntax: SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k – (W) → W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1000 kkkk kkkk

Description W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to W

Example 1: SUBLW 02h

Before Instruction

W = 01h

C=?

After Instruction

W = 01h

C = 1 ; result is positive

Z=0

N=0

Example 2: SUBLW 02h

Before Instruction

W = 02h

C=?

After Instruction

W = 00h

C = 1 ; result is zero

Z=1

N=0

Example 3: SUBLW 02h

Before Instruction

W = 03h

C=?

After Instruction

W = FFh ; (2’s complemen t )

C = 0 ; result is negative

Z=0

N=1

SUBWF Subtract W from f

Syntax: SUBWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – (W) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 11da ffff ffff

Description: Subtrac t W from regist er ‘f ’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and t he extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” f or details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: SUBWF REG, 1, 0

Before Instruction

REG = 3

W=2

C=?

After Instruction

REG = 1

W=2

C = 1 ; result is positive

Z=0

N=0

Example 2: SUBWF REG, 0, 0

Before Instruction

REG = 2

W=2

C=?

After Instruction

REG = 2

W=0

C = 1 ; result is zero

Z=1

N=0

Example 3: SUBWF REG, 1, 0

Before Instruction

REG = 1

W=2

C=?

After Instruction

REG = FFh ;(2’s complement)

W=2

C = 0 ; result is negative

Z=0

N=1

PIC18F2423/2523/4423/4523

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – (W) – (C) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 10da ffff ffff

Description: Subtract W and the Carry flag (borrow)

from register ‘f’ (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example 1: SUBWFB REG, 1, 0

Before Instruction

REG = 19h (0001 1001)

W=0Dh (0000 1101)

C=1

After Instruction

REG = 0Ch (0000 1011)

W=0Dh (0000 1101)

C=1

Z=0

N = 0 ; result is positive

Example 2: SUBWFB REG, 0, 0

Before Instruction

REG = 1Bh (0001 1011)

W=1Ah (0001 1010)

C=0

After Instruction

REG = 1Bh (0001 1011)

W = 00h

C=1

Z = 1 ; res u l t is ze r o

N=0

Example 3: SUBWFB REG, 1, 0

Before Instruction

REG = 03h (0000 0011)

W=0Eh (0000 1101)

C=1

After Instruction

REG = F5h (1111 0100)

; [2’s co mp]

W=0Eh (0000 1101)

C=0

Z=0

N = 1 ; result is negative

SWAPF Swap f

Syntax: SWAPF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

Status Affected: None

Encoding: 0011 10da ffff ffff

Description: The upper and lower nibbles of register

‘f’ are exchanged. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: SWAPF REG, 1, 0

Before Instruction

REG = 53h

After Instruction

REG = 35h

PIC18F2423/2523/4423/4523

TBLRD Table Read

Syntax: TBLRD ( *; *+; *-; +*)

Operands: None

Operation: if TBLRD *,

(Prog Mem (TBLPTR)) → TABLAT;

TBLPTR – No Change;

if TBLRD *+,

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) + 1 → TB L PT R ;

if TBLRD *-,

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) – 1 → TBL PT R ;

if TBLRD +*,

(TBLPTR) + 1 → TB L PT R ;

(Prog Mem (TBLPTR)) → TABLAT

S t at us Af fect ed: None

Encoding: 0000 0000 0000 10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLP TR <0> = 0: Least Significant Byte

of Program Memor y

Word

TBLP TR <0> = 1: Most Significant Byte

of Program Memor y

Word

The TBLRD instruction can modify the value

of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation No

operation

operation No operatio n

(Read Program

Memory)

operation No operation

(Write TABLA T)

TBLRD Table Read (Continued)

Example 1: TBLRD *+ ;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

MEMORY (00A356h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 00A357h

Example 2: TBLRD +* ;

Before Instruction

TABLAT = AAh

TBLPTR = 01A357h

MEMORY (01A357h) = 12h

MEMORY (01A358h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 01A358h

PIC18F2423/2523/4423/4523

TBLWT Table Write

Syntax: TBLWT ( *; *+; *-; +*)

Operands: None

Operation: if TBLWT*,

(TABLAT) → Holding Register;

TBLPTR – No Change;

if TBLWT*+,

(TABLAT) → Holding Register;

(TBLPTR) + 1 → TBL PT R ;

if TBLWT*-,

(TABLAT) → Holding Register;

(TBLPTR) – 1 → TBLPTR;

if TBLWT+*,

(TBLPTR) + 1 → TBL PT R ;

(TABLAT) → Holding Register

Status Affected: None

Encoding: 0000 0000 0000 11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction uses the 5 LSBs of

TBLPTR to determine which of the

32 holding registers the T ABLAT is written

to. The holding registers are used to

program the contents of Program

Memory (P.M.). (Refer to Section 6.0

“Flash Program Memory” for additional

details on programming Flash memory.)

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory.

TBLPTR has a 2-Mbyte address range.

The LSb of the TBLPTR selects which

byte of the program memory location to

access.

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity: Q1 Q2 Q3 Q4

Decode No

operation No

operation

operation No

operation

(Read

TABLAT)

operation No

operation

(Write to

Holding

TBLWT Table Write (Continued)

Example 1: TBLWT *+;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

HOLD ING REGIST ER

(00A356h) = FFh

After Instructions (table write completion)

TABLAT = 55h

TBLPTR = 00A357h

HOLD ING REGIST ER

(00A356h) = 55h

Example 2: TBLWT +*;

Before Instruction

TABLAT = 34h

TBLPTR = 01389Ah

HOLD ING REGIST ER

(01389Ah) = FFh

HOLD ING REGIST ER

(01389Bh) = FFh

After Instruction (table write completion)

TABLAT = 34h

TBLPTR = 01389Bh

HOLD ING REGIST ER

(01389Ah) = FFh

HOLD ING REGIST ER

(01389Bh) = 34h

PIC18F2423/2523/4423/4523

TSTFSZ Test f, Skip if 0

Syntax: TSTFSZ f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: skip if f = 0

Status Affected: None

Encoding: 0110 011a ffff ffff

Description: If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOP is executed,

making this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data No

operation

If skip: Q1 Q2 Q3 Q4

operation No

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation No

operation

operation No

operation

Example: HERE TSTFSZ CNT, 1

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

If CNT = 00h,

PC = Address (ZERO)

If CNT ≠00h,

PC = Address (NZERO)

XORLW Exclusive OR Literal with W

Syntax: XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W ) .XO R . k → W

Status Affected: N, Z

Encoding: 0000 1010 kkkk kkkk

Description: The contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to W

Example: XORLW 0AFh

Before Instruction

W=B5h

After Instruction

W=1Ah

PIC18F2423/2523/4423/4523

XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .XOR. (f) → dest

Status Affected: N, Z

Encoding: 0001 10da ffff ffff

Description: Exclusive OR the contents of W with

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select t he

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in In d e x e d L it e r a l Offset Ad d re ssi n g

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Orient ed and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: XORWF REG, 1, 0

Before Instruction

REG = AFh

W=B5h

After Instruction

REG = 1Ah

W=B5h

PIC18F2423/2523/4423/4523

24.2 Extended Instruction Set

In additi on to t he s t an dard 75 i nst ruc tions of the PI C1 8

instruc tio n s et, PIC18LF242 3/2 523 /4423/452 3 device s

also provide an optional extension to the core CPU

functionality. The added features include eight addi-

tional instructions that augment Indirect and Indexed

Addressing operations and the implementation of

Indexed Literal Of fset Addressin g mode for many of the

standard PIC18 instructions.

The additional features of the extended instruction set

are d isabled by defa ult. To enabl e them, users m ust set

the XINST Configuration bit.

The instructions in the extended set can all be

class ified as literal operation s, which eith er manip ulate

the File Select Registers, or use them for Indexed

Addressing. Two of the instructions, ADDFSR and

SUBFSR, each have an additional special instantiation

for using FSR2. These versions (ADDULNK and

SUBULNK) allow for automatic return after execution.

The exte nded instr uctions are s pecifically im plemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

• Dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• Function Pointer invocation

• Software Stack Pointer manipulation

• Manipulation of variables located in a software

stack

A summary of the instructions in the extended instruc-

tion set is provide d in Table 24-3. Det aile d descr ipti ons

are pro vided in Section 24.2.2 “Extended Instruction

Set”. The opcode field descriptions in Table 24-1

(page 272) apply to both the standard and extended

PIC18 instruction sets.

24.2.1 EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed argu-

ment s, using one of the File Sele ct Register s and some

of fset to spe ci fy a sou rce or destinati on reg ist er. When

an argument for an instruction serves as part of

Indexed Addressing, it is enclosed in square brackets

(“[ ]”). This is done to in dicate that the argument is used

as an index or of f set . MPASM™ Assembl er wil l flag an

error if it de termines that an inde x or offset value is not

bracketed.

When the ex tended ins truction s et is enabled, bra cket s

are also used to indicate index arguments in byte-

oriented and bit-oriented in structions. This is in addition

to other changes in their syntax. For more details, see

Section 24.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”.

TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Note: The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in assembler.

The syntax for these commands is pro-

vided as a reference for u sers who may b e

reviewing code that has been generated

by a compiler.

Note: In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text and going forward, optional

arguments are denoted by braces (“{ }”).

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected

MSb LSb

ADDFSR

ADDULNK

CALLW

MOVSF

MOVSS

PUSHL

SUBFSR

SUBULNK

f, k

zs, fd

zs, zd

f, k

Add literal to FSR

Add literal to FSR2 and return

Call subroutine using WREG

Move zs (source) to 1st word

fd (destination) 2nd word

Move zs (source) to 1st word

zd (destination) 2nd word

Store literal at FSR2,

decrement FSR2

Subtract literal from FSR

Subtract literal from FSR2 and

return

1110

0000

1110

1111

1110

1111

1110

1000

0000

1011

ffff

1011

xxxx

1010

1001

ffkk

11kk

0001

0zzz

ffff

1zzz

xzzz

kkkk

ffkk

11kk

kkkk

0100

zzzz

ffff

zzzz

kkkk

None

PIC18F2423/2523/4423/4523

24.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR

Syntax: ADDFSR f, k

Operands: 0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

Operation: FSR(f) + k → FSR(f)

Status Affected: None

Encoding: 1110 1000 ffkk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of the FSR specified by ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to

FSR

Example: ADDFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 0422h

ADDULNK Add Li t era l to FS R 2 and R e turn

Syntax: ADDULNK k

Operands: 0 ≤ k ≤ 63

Operation: FSR2 + k → FSR2,

(TOS) → PC

Status Affected: None

Encoding: 1110 1000 11kk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of FSR2. A RETURN is then

executed by loading the PC with the

TOS.

The instruction takes two cycles to

execute; a NOP is performed during

the second cycle.

This may be thought of as a special

case of the ADDFSR instruction,

where f = 3 (binary ‘11’); it operates

only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’ Process

Data Write to

FSR

Operation No

Operation

Example: ADDULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 0422h

PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

PIC18F2423/2523/4423/4523

CALLW Subroutine Call Using WREG

Syntax: CALLW

Operands: None

Operation: (PC + 2) → TOS,

(W) → PCL,

(PCLATH) → PCH,

(PCLATU) → PCU

Status Affected: None

Encoding: 0000 0000 0001 0100

Description First, the return address (PC + 2) is

pushed onto the return stack. Next, the

contents of W are written to PCL; the

existing value is discarded. Then, the

contents of PCLATH and PCLATU are

latched into PCH and PCU,

respectively. The second cycle is

executed as a NOP instruction while the

new next instruction is fetched.

Unlike CALL, there is no option to

update W, STATUS or BSR.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

WREG PUSH PC to

stack No

operation

operation No

operation

Example: HERE CALLW

Before Instruction

PC = address (HERE)

PCLATH = 10h

PCLATU = 00h

W = 06h

After Instruction

PC = 001006h

TOS = address (HERE + 2)

PCLATH = 10h

PCLATU = 00h

W = 06h

MOVSF Move Indexed to f

Syntax: MOVSF [zs], fd

Operands: 0 ≤ zs ≤ 127

0 ≤ fd ≤ 4095

Operation: ((FSR2) + zs) → fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.) 1110

1111

1011

ffff

0zzz

ffff

zzzzs

ffffd

Description: The contents of the source register are

moved to destination register ‘fd’. The

actual address of the source register is

determined by adding the 7-bit literal

offset ‘zs’ in the first word to the value of

FSR2. The address of the destination

‘fd’ in the second word. Both addresses

can be anywhere in the 4096-byte data

space (000h to FFFh).

The MOVSF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr Determine

source addr Read

source reg

Decode No

operation

No dummy

read

operation Write

(dest)

Example: MOVSF [05h], REG2

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 33h

PIC18F2423/2523/4423/4523

MOVSS Move Indexed to Indexed

Syntax: MOVSS [zs], [zd]

Operands: 0 ≤ zs ≤ 127

0 ≤ zd ≤ 127

Operation: ((F SR2) + zs) → ((FSR2) + zd)

Status Affected: None

Encoding:

1st word (source)

2nd word (dest.) 1110

1111

1011

xxxx

1zzz

xzzz

zzzzs

zzzzd

Description The contents of the source register are

moved to the destination register . The

addresses of the source and destination

registers are determined by adding the

7-bit literal offset s ‘zs’ or ‘zd’,

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

The MOVSS instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h. If the

resultant destination address points to

an indirect addressing register, the

instruction will execute as a NOP.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr Determine

source addr Read

source reg

Decode Determine

dest addr Determine

dest addr Write

to dest reg

Example: MOVSS [05h], [06h]

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 33h

PUSHL

Store Literal at FSR2, Decrement FSR2

Syntax: PUSHL k

Operands: 0 ≤ k ≤ 255

Operation: k → (FSR2),

FSR2 – 1 → FSR2

S t at us Af fect ed: None

Encoding: 1111 1010 kkkk kkkk

Description: The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2. FSR2

is decremented by 1 after the operation.

This instruction allows users to push values

onto a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

data Write to

destination

Example: PUSHL 08h

Before Instruction

FSR2H:FSR2L = 01ECh

Memory (01ECh) = 00h

After Instruction

FSR2H:FSR2L = 01EBh

Memory (01ECh) = 08h

PIC18F2423/2523/4423/4523

SUBFSR Subtract Literal from FSR

Syntax: SUBFSR f, k

Operands: 0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

Operation: FSR( f) – k → FSRf

Status Affected: None

Encoding: 1110 1001 ffkk kkkk

Description: The 6-bit literal ‘k’ is subtracted from

the contents of the FSR specified by

‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: SUBFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 03DCh

SUBULNK

Subtract Literal from FSR2 and Return

Syntax: SUBULNK k

Operands: 0 ≤ k ≤ 63

Operation: FSR2 – k → FSR2

(TOS) → PC

S t at us Af fect ed: None

Encoding: 1110 1001 11kk kkkk

Description: The 6-bit literal ‘k’ is subtracted from the

contents of the FSR2. A RETURN is then

executed by loading the PC with the TOS.

The instruction takes two cycles to

execute; a NOP is performed during the

second cycle.

This may be thought of as a special case of

the SUBFSR instruction, where f = 3 (binary

‘11’); it operates only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Operation No

Operation

Example: SUBULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 03DCh

PC = (TOS)

PIC18F2423/2523/4423/4523

24.2.3 BYTE-ORIE NTED AND

BIT-ORIENTED INSTRUCTIONS IN

INDEXED LITERAL OFFSET MODE

In additio n to eight new comm ands in the extende d set,

enabling the extended instruction set also enables

Indexed Literal Offset Addre ssing mode (Section 5.5.1

“Indexed Addressing with Literal Offset”). This has

a sign ificant im pact on the way t hat many com mands of

the standard PIC18 instruction set are interpreted.

When the ex ten ded se t is di sabled, a ddresses em be d-

ded in opco des are treated as literal memory locations:

either as a l oc ati on i n th e Ac ce ss Ban k (‘ a’ = 0), or in a

GPR bank designated by the BSR (‘a’ = 1). When the

extended instruction set is enabled and ‘a’ = 0, how-

ever, a file register argument of 5Fh or less is

interpreted as an offset from the point er val ue in FSR2

and not as a literal address. For practical purposes, this

means that all i nstructio ns that us e the Acc ess RAM b it

as an argument – that is, all byte-oriented and bit-

oriented instructions, or almost half of the core PIC18

instructions – may behave differently when the

extended instruction set is enabled.

When the content of FSR2 is 00h, the boundaries of the

Access RAM are essentially remapped to their original

values. This may be useful in creating backward

compatible code. If this technique is used, it may be

necessary to save the value of FSR2 and restore it

when moving back and forth between C and assembly

routines in order to preserve the Stack Pointer. Users

must also keep in mind the syntax requirements of the

extended instruction set (see Section 24.2.3.1

“Extended Instruction Syntax with Standard PIC18

Commands”).

Although the Indexed Literal Offset Addressing mode

can be very useful for dynamic stack and pointer

manipulation, it can also be very annoying if a simple

arithmetic operation is carried out on the wrong

gramming must keep in mind that, when the extended

instruction set is enabled, register addresses of 5Fh or

less are used for Indexed Literal Offset Addressing.

Representative examples of typical byte-oriented and

bit-oriented instructions in the Indexed Literal Offset

Address ing mode are pro vided on the f ollowing p age to

show how execution is affected. The operand condi-

tions shown in the examples are applicable to all

instructions of these types.

24.2.3.1 Extended Instruction Syntax with

Standard PIC18 Commands

When the extended instruction set is enabled, the file

bit-or iented command s is replaced with the li teral offs et

value, ‘k ’. As al rea dy no ted , this occ urs only when ‘f’ is

less t han or eq ual to 5Fh. When an of fset val ue is use d,

it must be indicated by square brackets (“[ ]”). As with

the exte nded ins tructions , the us e of brac kets indicate s

to the com pil er th at the val ue is to be in terp rete d as an

index or an offset. Omitting the brackets, or using a

value greater than 5Fh within brackets, will generate an

error in the MPASM Assembler.

If the ind ex argume nt is pr operly brackete d for Indexe d

Literal O ffset Addre ssing, the Acces s RAM argument i s

never specified; it will automatically be assumed to be

‘0’. This is in contrast to standard operation (extended

instruction set disabled) when ‘a’ is set on the basis of

the target address. Declaring the Access RAM bit in

this mode will also generate an error in the MPASM

Assembler.

The destination argument, ‘d’, functions as before.

In the latest versions of the MPASM Assembler,

languag e s upp ort for the exte nde d i ns truc tio n s et m us t

be explicitly invoked. This is done with either the

command line option, /y, or the PE directive in the

source lis tin g.

24.2. 4 CONSIDERATIONS WHEN

ENABLING THE EXTENDED

INSTRUCTION SET

It is i mport ant to note that the exten sions to th e ins truc-

tion set may not be beneficial to all users. In particular,

users who are not writing code that uses a software

stack may not benefit from using the extensions to the

instruction se t.

Additionally, the Indexed Literal Offset Addressing

mode may create issues with legacy applications

written to the PIC18 assembler. This is because

instruc t ion s i n th e le gac y cod e m ay atte mp t to a dd r es s

registers in the Access Bank below 5Fh. Since these

addresses are interpreted as literal offsets to FSR2

when the instruction set extension is enabled, the

application may read or write to the wrong data

addresses.

When porting an application to the PIC18LF2423/2523/

4423/4523, it is very important to consider the type of

code. A l arge, re-entrant application that is written in ‘C’

and wou ld bene fit from effi cient compi lation will do well

when using the instruction set extensions. Legacy

applic ations tha t heavily use the Ac cess Ban k will most

likely not benefit from using the extended instruction

set.

Note: Enabling the PIC18 instruction set

extension may cause legacy applications

to behave erratically or fail entirely.

PIC18F2423/2523/4423/4523

ADDWF ADD W to Indexed

(Indexed Literal Offset mode)

Syntax: ADDWF [k] {,d}

Operands: 0 ≤ k ≤ 95

d ∈ [0,1]

Operation: (W) + ((FSR2) + k) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01d0 kkkk kkkk

Description: T he contents of W are added to the

contents of the register indicated by

FSR2, offset by the value ‘k’.

If ‘d’ is ‘0’, the result is stored in W. If ‘d’

is ‘1’, the result is stored back in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data Write to

destination

Example: ADDWF [OFST] , 0

Before Instruction

W = 17h

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 20h

After Instruction

W = 37h

Contents

of 0A2Ch = 20h

BSF Bit Set Indexed

(Indexed Literal Offset mode)

Syntax : BSF [k ], b

Operands: 0 ≤ f ≤ 95

0 ≤ b ≤ 7

Operation: 1 → ((FSR2) + k)

Status Affected: None

Encoding: 1000 bbb0 kkkk kkkk

Description: Bit ‘b’ of t he register indicated by FSR2,

offset by the value ‘k’, is set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Data Write to

destination

Example: BSF [FLAG_OFST], 7

Before Instruction

FLAG_OFST = 0Ah

FSR2 = 0A00h

Contents

of 0A0Ah = 55h

After Instruction

Contents

of 0A0Ah = D5h

SETF Set Indexed

(Indexed Literal Offset Mode)

Syntax: SETF [k]

Operands: 0 ≤ k ≤ 95

Operation: FFh → ((F SR2) + k)

Status Affected: None

Encoding: 0110 1000 kkkk kkkk

Description: The contents of the register indicated by

FSR2, offset by ‘k’, are set to FFh.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data Write

Example: SETF [OFST]

Before Instruction

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 00h

After Instruction

Contents

of 0A2Ch = FFh

PIC18F2423/2523/4423/4523

24.2.5 SPECIAL CONSIDERATIONS WITH

MICROCHIP MPLAB ® IDE TOOLS

The latest versions of Microchip’s software tools have

been de signe d t o full y sup port th e exte nded i nstruc tion

set of the PIC18LF2423/2523/4423/4523 family of

devices. This includes the MPLAB C18 C compiler,

MPASM assembly language and MPLAB Integrated

Development Environment (IDE).

When selecting a target device for software

development, MPLAB IDE will automatically set default

Configuration bits f or that devi ce. The default setting for

the XINST Configuration bit is ‘0’, disabling the

extended instruction set and Indexed Literal Offset

Address ing mod e. For pr oper e xecution of app licat ions

developed to take advantage of the extended

instruction set, XINST must be set during

programming.

To develop software for the extended instruction set,

the user must enable support for the instructions and

the Index ed Addressing mode in the ir languag e tool(s).

Depending on the environment being used, this may be

done in several ways:

• A menu option, or dialog box wi thin the

environ me nt, th at allow s t he u se r to c onf igu r e th e

language tool and its settings for the project

• A comm and line op tion

• A directive in the source code

These options vary between different compilers,

assemblers and development environments. Users are

encouraged to review the documentation accompany-

ing their development systems for the appropriate

information.

PIC18F2423/2523/4423/4523

25.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Programmers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

25.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold sep ara tel y)

- In-Circuit Debugger (sol d separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-l in e help

• Integration of select third part y tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (eit her a ssembly or C )

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC18F2423/2523/4423/4523

25.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

25.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

25.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, de letion and extraction

25.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or lin ked with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

25.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and inte rnal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

PIC18F2423/2523/4423/4523

25.7 MPLAB ICE 2000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC micro-

controllers. Software control of the MPLAB ICE 2000

In-Circuit Emulator is advanced by the MPLAB Inte-

grated Development Environment, which allows edit-

ing, building, downloading and source debugging from

a sin gle environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

25.8 MPLAB ICE 4000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 4000 In-Circuit Emu lator is intende d to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PIC MCUs and dsPIC DSCs. Software control of the

MPLAB ICE 4000 In-Circuit Emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environm ent.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

25.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

25.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is in cluded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions and

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

PIC18F2423/2523/4423/4523

25.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

25.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer with an easy-to-use interface for pro-

gramming many of Microchip’s baseline, mid-range

and PIC1 8F families of Fl ash memory mic rocontrollers.

The PICkit 2 S tar ter Kit includes a pr ototypin g develop-

ment board, twelve sequential lessons, software and

HI-TECH’s PICC Lite C compiler, and is designed to

help get up to speed quickly using PIC® micro-

controllers. The kit provides everything needed to

program, evaluate and develop applications using

Microchip’s powerful, mid-range Flash memory family

of microcontroll ers.

25.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards incl ude prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart® battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

PIC18F2423/2523/4423/4523

26.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ..........................................-0.3V to (VDD + 0.3V)

Volta ge on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Volta ge on MCLR with respect to VSS (Note 2)......................................................................................... 0V to +13.25V

Total powe r dissipati on (Note 1) ...............................................................................................................................1.0W

Maximum curr ent o ut of VSS pin ...........................................................................................................................300 mA

Maximum curr ent i nto VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. ±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum curr ent su nk by all ports .......................................................................................................................200mA

Maximum current sourced by all ports..................................................................................................................200 mA

Note 1: Power dissip ati on is calcula ted as follow s :

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause

latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/

RE3 pin, rather than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC18F2423/2523/4423/4523

FIGURE 26-1: PIC18F2423/2523/4423/4523 VOLT AGE-FREQUENCY GRAPH (INDUSTRIAL)

FIGURE 26-2: PIC18LF2423/2523/4423/4523 VOLT AGE-FREQUENCY GRAPH (INDUSTRIAL)

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

40 MHz

5.0V

3.5V

3.0V

2.5V

PIC18FX423/X523

4.2V

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

40 MHz

5.0V

3.5V

3.0V

2.5V

PIC18LFX423/X523

FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz

Note: VDDAPPMIN is the minimum voltage of the PIC® device in th e application.

4 MHz

4.2V

PIC18F2423/2523/4423/4523

26.1 DC Characteristics:Supply Voltage

PIC18F2423/2523 /4423/4523 (Industrial)

PIC18LF2423/2523 /4423/4523 (Indust rial)

PIC18LFX423/X523

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Symbol Characteristic Min Typ Max Units Conditions

VDD Supply Voltage

D001 PIC18LFX423/X523 2.0 — 5.5 V

D001A PIC18FX423/X523 4.2 —5.5 v

D002 VDR RAM Data Retention

Voltage(1) 1.5 — — V

D003 VPOR VDD Start Voltage

to ensure Inte rnal

Power-o n Reset Signal

——0.7V

See section on Power-on Reset for details

D004 SVDD VDD Rise Rate

to ensure Inte rnal

Power-o n Reset Signal

0.05 — — V/ms See section on Power-on Reset for details

VBOR Brown-out Reset Voltage

D005 PIC18LFX423/X523 Indust r ia l Low Voltage

BORV1:BORV0 = 11 N/A — N/A V Reserved

BORV1:BORV0 = 10 2.65 2.79 2.93 V

BORV1:BORV0 = 01 4.11 4.33 4.55 V

BORV1:BORV0 = 00 4.36 4.59 4.82 V

PIC18FX423/ X523 Indust rial

BORV1:BORV0 = 11 N/A —N/A VReserved

BORV1:BORV0 = 10 N/A —N/A V

BORV1:BORV0 = 01 4.11 4.33 4.55 V

BORV1:BORV0 = 00 4.36 4.59 4.82 V

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limi t to w hic h VDD can be low e red in Sleep mode, or durin g a de vi ce Res et, without losing R AM

data.

PIC18F2423/2523/4423/4523

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial)

PIC18LFX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Power-Down Current (IPD)(1)

PIC18LFX4 23/ X523 20 950 nA - 40°C VDD = 2.0V

(Sleep mode)

0.02 1.0 μA +25°C

0.6 1.1 μA +85°C

PIC18LFX423/X523 0.03 1.4 μA-40°C VDD = 3.0V

(Sleep mode)

0.03 1.5 μA +25°C

0.8 1.6 μA +85°C

All devi ces 0.04 1.9 μA-40°C VDD = 5.0V

(Sleep mode)

0.04 2.0 μA +25°C

1.7 2.1 μA +85°C

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estim at ed by the formu l a Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w ill be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Supply Current (IDD)(2,3)

PIC18LFX423/X523 15 31.5 μA-40°C

FOSC = 31 kHz

(RC_RUN mode,

INTRC sour ce)

15 30 μA +25°C VDD = 2. 0V

15 28.5 μA+85°C

PIC18LFX423/X523 40 63 μA-40°C

35 60 μA +25°C VDD = 3. 0V

30 57 μA+85°C

All devi ces 105 168 μA-40°C

90 160 μA +25°C VDD = 5.0V

80 152 μA+85°C

PIC18LFX423/X523 320 630 μA-40°C

FOSC = 1 M Hz

(RC_RUN mode,

INTOSC source)

330 600 μA +25°C VDD = 2.0V

330 570 μA+85°C

PIC18LFX423/X523 0.6 1.3 mA -40°C

0.55 1.2 mA +25°C VDD = 3.0V

0.6 1.1 mA +85°C

All devi ces 1.1 2.3 mA -40°C

1.1 2.2 mA +25°C VDD = 5.0V

1.0 2.1 mA +85°C

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w i ll be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Supply Current (IDD)(2,3)

PIC18LFX423/X523 0.8 2.1 mA -40°C

FOSC = 4 MHz

(RC_RUN mode,

INTRC sour ce)

0.8 2.0 mA +25°C VDD = 2. 0V

0.8 1.9 mA +85°C

PIC18LFX423/X523 1.3 2.7 mA -40°C

1.3 2.6 mA +25°C VDD = 3. 0V

1.3 2.5 mA +85°C

All devi ces 2.5 5.3 mA -40°C

2.5 5.0 mA +25°C VDD = 5. 0V

2.5 4.8 mA +85°C

PIC18LFX423/X523 2.9 6.5 μA-40°C

FOSC = 31 kHz

(RC_IDLE mode,

INTRC sour ce)

3.1 6.2 μA +25°C VDD = 2.0V

3.6 5.9 μA+85°C

PIC18LFX423/X523 4.5 10.1 μA-40°C

4.8 9.6 μA +25°C VDD = 3.0V

5.8 9.1 μA+85°C

All devi ces 9.2 15.8 μA-40°C

9.8 15.0 μA +25°C VDD = 5. 0V

11.4 14.3 μA+85°C

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estim at ed by the formu l a Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w ill be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Supply Current (IDD)(2,3)

PIC18LFX423/X523 165 315 μA-40°C

FOSC = 1 M Hz

(RC_IDLE mode,

INTOSC source)

175 300 μA +25°C VDD = 2.0V

190 285 μA+85°C

PIC18LFX423/X523 250 470 μA-40°C

270 450 μA +25°C VDD = 3.0V

290 430 μA+85°C

All devi ces 500 840 μA-40°C

520 800 μA +25°C VDD = 5.0V

550 760 μA+85°C

PIC18LFX423/X523 340 525 μA-40°C

FOSC = 4 M Hz

(RC_IDLE mode,

INTOSC source)

350 500 μA+25°C VDD = 2.0V

360 475 μA+85°C

PIC18LFX423/X523 520 735 μA-40°C

540 700 μA+25°C VDD = 3.0V

580 665 μA+85°C

All devi ces 1.0 1.6 mA -40°C

1.1 1.5 mA +25°C VDD = 5. 0V

1.1 1.4 mA +85°C

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w i ll be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Supply Current (IDD)(2,3)

PIC18LFX423/X523 250 420 μA-40°C

FOSC = 1 MHz

(PRI_RUN,

EC oscillator)

260 400 μA +25°C VDD = 2.0V

250 380 μA+85°C

PIC18LFX423/X523 550 740 μA-40°C

480 700 μA +25°C VDD = 3.0V

460 670 μA+85°C

All devi ces 1.2 1.6 mA -40°C

1.1 1.5 mA +25°C VDD = 5.0V

1.0 1.4 mA +85°C

PIC18LFX423/X523 0.72 1.6 mA -40°C

FOSC = 4 MHz

(PRI_RUN,

EC oscillator)

0.74 1.5 mA +25°C VDD = 2.0V

0.74 1.4 mA +85°C

PIC18LFX423/X523 1.3 2.6 mA -40°C

1.3 2.5 mA +25°C VDD = 3.0V

1.3 2.4 mA +85°C

All devi ces 2.7 4.7 mA -40°C

2.6 4.5 mA +25°C VDD = 5.0V

2.5 4.3 mA +85°C

All devi ces 15 26 mA -40°C

FOSC = 40 MH z

(PRI_RUN,

EC oscillator)

16 25 mA +25°C VDD = 4.2V

16 24 mA +85°C

All devi ces 21 32 mA -40°C

21 30 mA +25°C VDD = 5.0V

21 28 mA +85°C

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estim at ed by the formu l a Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w ill be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Supply Current (IDD)(2,3)

All de vices 7.5 16 mA -40°C VDD = 4. 2V FOSC = 4 MHz

(PRI_RUN HS+PLL)

7.4 15 mA +25°C

7.3 14 mA +85°C

All devi ces 10 21 mA -40°C VDD = 5.0V FOSC = 4 M Hz

(PRI_RUN HS+PLL)

10 20 mA +25°C

9.7 19 mA +85°C

All devi ces 17 35 mA -40°C VDD = 4.2V FOSC = 10 M H z

(PRI_RUN HS+PLL)

17 34 mA +25°C

17 33 mA +85°C

All devi ces 23 46 mA -40°C VDD = 5.0V FOSC = 10 M H z

(PRI_RUN HS+PLL)

23 45 mA +25°C

23 43 mA +85°C

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w i ll be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Supply Current (IDD)(2,3)

PIC18LFX423/X523 65 130 μA-40°C

FOSC = 1 MHz

(PRI_IDLE mode,

EC oscillator)

65 120 μA +25°C VDD = 2.0V

70 115 μA+85°C

PIC18LFX423/X523 120 270 μA-40°C

120 250 μA +25°C VDD = 3.0V

130 240 μA+85°C

All devi ces 300 480 μA-40°C

240 450 μA +25°C VDD = 5.0V

300 430 μA+85°C

PIC18LFX423/X523 260 475 μA-40°C

FOSC = 4 MHz

(PRI_IDLE mode,

EC oscillator)

255 450 μA +25°C VDD = 2.0V

270 430 μA+85°C

PIC18LFX423/X523 420 900 μA-40°C

430 850 μA +25°C VDD = 3.0V

450 810 μA+85°C

All devi ces 0.9 1.5 mA -40°C

0.9 1.4 mA +25°C VDD = 5.0V

0.9 1.3 mA +85°C

All devi ces 6.0 9.5 mA -40°C

FOSC = 40 MH z

(PRI_IDLE mode,

EC oscillator)

6.2 9.0 mA +25°C VDD = 4.2 V

6.6 8.6 mA +85°C

All devices 8.1 12.6 mA - 40 °C

9.1 12.0 mA +25°C VDD = 5. 0V

8.3 11.4 mA +85°C

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estim at ed by the formu l a Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w ill be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Supply Current (IDD)(2,3)

PIC18LFX423/X523 14 31.5 μA-10°C

FOSC = 32 kH z(4)

(SEC_RUN mode,

Ti mer1 as clock)

15 30 μA +25°C VDD = 2.0V

16 29 μA+70°C

PIC18LFX423/X523 40 74 μA-10°C

35 70 μA +25°C VDD = 3.0V

31 67 μA+70°C

All devi ces 99 126 μA-10°C

81 120 μA +25°C VDD = 5.0V

75 114 μA+70°C

PIC18LFX423/X523 2.5 7.4 μA-10°C

FOSC = 32 kH z(4)

(SEC_IDLE mode,

Ti mer1 as clock)

3.7 7.0 μA +25°C VDD = 2.0V

4.5 6.7 μA+70°C

PIC18LFX423/X523 5.0 10.5 μA-10°C

5.4 10 μA +25°C VDD = 3.0V

6.3 9.5 μA+70°C

All devi ces 8.5 17 μA-10°C

9.0 16 μA +25°C VDD = 5.0V

10.5 15 μA+70°C

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operating Cond itions (unless otherwise stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w i ll be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)

D022

(ΔIWDT)Watchd og Timer 1.3 7.6 μA-40°C VDD = 2.0V1.4 8.0 μA+25°C

2.0 8.4 μA+85°C

1.9 11.4 μA-40°C VDD = 3.0V2.0 12.0 μA+25°C

2.8 12.6 μA+85°C

4.0 14.3 μA-40°C VDD = 5.0V5.5 15.0 μA+25°C

5.6 15.8 μA+85°C

D022A

(ΔIBOR)Brown-out Reset(5) 35 52 μA-40°C to +85°CVDD = 3.0V

40 63 μA-40°C to +85°CV

DD = 5.0V

D022B

(ΔILVD)High/Low-Voltage

Detect(5) 22 47 μA-40°C to +85°CVDD = 2.0V

25 58 μA-40°C to +85°CV

DD = 3.0V

29 69 μA-40°C to +85°CV

DD = 5.0V

D025

(ΔIOSCB)Timer1 Oscillator 2.1 4.5 μA-40°CVDD = 2.0V 32 kHz on Timer1(4)

1.8 4.5 μA+25°C

2.1 4.5 μA+85°C

2.2 6.0 μA-40°CVDD = 3.0V 32 kHz on Timer1(4)

2.6 6.0 μA+25°C

2.9 6.0 μA+85°C

3.0 8.0 μA-40°CVDD = 5.0V 32 kHz on Timer1(4)

3.2 8.0 μA+25°C

3.4 8.0 μA+85°C

D026

(ΔIAD)A/D Converter 1.0 2.0 μA-40°C to +85°CV

DD = 2.0V A/D on , no t converting1.0 2.0 μA-40°C to +85°CV

DD = 3.0V

1.0 2.0 μA-40°C to +85°CV

DD = 5.0V

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2423/2523/4423/4523 (Industri al)

PIC18LF2423/2523/4423/4523 (Industrial) (Conti nued)

PIC18LFX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operat in g C onditions (unless otherw i se stated)

Opera tin g te m perature - 40 °C ≤ TA ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Legend: Shading of rows is to ass i st in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all feat ures that

add del ta current disa bl ed ( suc h as WDT, Ti m er 1 O scillator, BOR, e tc.) .

2: The s upp ly cur r ent is m ai nl y a function of op e rating voltage , fre quency an d m ode. Othe r fact ors, such as I/O pi n

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an im pact o n th e cu rr ent consu m pt ion.

The test conditi ons for all IDD measurements in active operati on mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-sta ted, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through REXT is not included. The curr ent th ro ugh the resist or can be

estim at ed by the formu l a Ir = VDD/2REXT (mA) with REXT in kΩ.

4: St andard lo w-cost 32 kH z cr yst al s have an operating tem perature range of -10°C to +70°C. Extended temperature

crystal s ar e avai l abl e at a much higher cost.

5: BOR and HLVD enable inter na l ba nd gap refer ence. With bo th m odules enabl ed, curre nt consump tio n w ill be

less than the su m of bo th specificat io ns.

PIC18F2423/2523/4423/4523

26.3 DC Characteristics: PIC18F2423/2523/4423/4523 (Industrial)

PIC18LF2423/2523/4423/4523 (Industri al)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Symbol Characteristic Min Max Units Conditions

VIL Input Low Voltage

I/O Ports:

D030 with TTL buffer V SS 0 .15 VDD VVDD < 4.5V

D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger buffer

RC3 and RC4 VSS

VSS 0.2 VDD

0.3 VDD V

D032 MCLR VSS 0.2 VDD V

D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes

D033A

D033B

D034

OSC1

T13CKI

VSS

0.2 VDD

0.3

RC, EC modes(1)

XT, LP modes

VIH Input High Voltage

I/O Ports:

D040 with TTL buffer 0.25 VDD + 0.8V VDD VVDD < 4.5V

D040A 2.0 VDD V4.5V ≤ VDD ≤ 5.5V

D041 with Schmitt Trigger buffer

RC3 and RC4 0.8 VDD

0.7 VDD VDD

VDD V

D042 MCLR 0.8 VDD VDD V

D043 OSC 1 0.7 V DD VDD V HS, HSPLL modes

D043A

D043B

D043C

D044

OSC1

T13CKI

0.8 VDD

0.9 VDD

1.6

VDD

EC mode

RC mode(1)

XT, LP modes

IIL Input Leakage Current (2,3)

D060 I/O Ports — ±1μAV

SS ≤ VPIN ≤ VDD,

Pin at high-impedance

D061 MCLR —±5μAVss ≤ VPIN ≤ VDD

D063 OSC1 — ±5μAVss ≤ VPIN ≤ VDD

IPU Weak Pull-up Current

D070 IPURB PORTB Weak Pull-up Current 50 400 μAVDD = 5V, VPIN = VSS

Note 1: In RC oscillator co nfiguratio n, the OSC1/CLKI pin is a Schmitt T rigger inp ut. It is not recommen ded that the

PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Parameter is characte rized but not tested.

PIC18F2423/2523/4423/4523

VOL Output Low Voltage

D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

D083 OSC2/CLKO

(RC, RCIO, EC, ECIO modes) —0.6VI

OL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

VOH Output High Voltage(3)

D090 I/O Ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

D092 OSC2/CLKO

(RC, RCIO, EC, ECIO modes) VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

Capacitive Loading Specs

on Output Pins

D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes

when external clock is

used to drive OSC1

D101 CIO All I/O pins and OSC2

(in RC mode) — 50 pF To meet the AC Timing

Specifications

D102 CBSCL, SDA — 400 pF I2C™ Specification

26.3 DC Characteristics: PIC18F2423/2523/4423/4523 (Industrial)

PIC18LF2423/2523/4423/4523 (Industri al) (Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temp erature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Symbol Characteristic Min Max Units Conditions

Note 1: In RC oscillator co nfiguratio n, the OSC1/CLKI pin is a Schmitt T rigger inp ut. It is not recommen ded that the

PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Parameter is characterized but not tested.

PIC18F2423/2523/4423/4523

TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Internal Program Memory

Programming Specifications(1)

D110 VPP Voltage on MCLR/VPP/RE3 pin VDD + 4.0V — 12.5 V (Note 3)

D113 IDDP Supply Current during

Programming ——10mA

Data EEPROM Memory

D120 EDByte Endurance 100K 1M — E/W -40°C to +85°C

D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write Cycle Time — 4 — ms

D123 TRETD Characteristic Retention 40 — — Year Provided no other

specifications are violated

D124 TREF Number of Total Erase/Writ e

Cycles before Re fresh(2) 1M 10M — E/W -40°C to +85°C

Program Flash Memory

D130 EPCell Endu rance 10K 100K —E/W -40°C to +85°C

D131 VPR VDD for Rea d VMIN —5.5 V VMIN = Minimum operating

voltage

D132 VIE VDD for Block Erase 3.0 —5.5 V Using ICSP™ port

D132A VIW VDD for Externally Timed Erase

or Write 2.0 —5.5 V Using ICSP port

D132B VPEW VDD for Self-Timed Write VMIN —5.5 V VMIN = Minimum operating

voltage

D133 TIE ICSP Block Erase Cycle Time — 4 — ms VDD > 4.5V

D133A TIW ICSP Erase or Write Cycle Time

(externall y tim ed) 1——msVDD > 4.5V

D133A TIW Self-Timed Write Cycle Time — 2 — ms

D134 TRETD Characteristic Retention 40 100 — Year Provided no other

specifications are violated

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: These specifications are for programming the on-chip program memory through the use of table write

instructions.

2: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM

endurance.

3: Required only if Si ng le-Su ppl y Progra mm in g is disabl ed.

PIC18F2423/2523/4423/4523

TABLE 26-2: COMPARATOR SPECIFICATIONS

TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).

Param

No. Sym Characteristics Min Typ Max Units Comments

D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV

D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V

D302 CMRR Comm on Mo de Re je cti on Ra tio * 55 — — dB

300 TRESP Response Time(1)* — 150 400 ns PIC18FXXXX

300A — 150 600 ns PIC18LFXXXX,

VDD = 2.0V

301 TMC2OV Comparator Mode Change to

Output Valid* ——10μs

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions

from VSS to VDD.

Operating Condit ions : 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).

Param

No. Sym Characteristics Min Typ Max Units Comments

D310 VRES Resolution VDD/24 — VDD/32 LSb

D311 VRAA Absolute Accuracy — — 1/2 LSb Low Range (C VRR = 1)

D312 VRUR Unit Resistor Value (R)* — 2k — Ω

310 TSET Settling Time(1)*— — 10 μs

* These parameters are characterized but not tested.

Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.

PIC18F2423/2523/4423/4523

FIGURE 26-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

TABLE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

VLVD

HLVDIF

VDD

(HLVDIF set by hardware)

(HLVDIF can be

cleared in software)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D420 HLVD Voltage on VDD

Transition High-to-Low HLVDL<3:0> = 0000 2.12 2.17 2.22 V

HLVDL<3:0> = 0001 2.18 2.23 2.28 V

HLVDL<3:0> = 0010 2.31 2.36 2.42 V

HLVDL<3:0> = 0011 2.38 2.44 2.49 V

HLVDL<3:0> = 0100 2.54 2.60 2.66 V

HLVDL<3:0> = 0101 2.72 2.79 2.85 V

HLVDL<3:0> = 0110 2.82 2.89 2.95 V

HLVDL<3:0> = 0111 3.05 3.12 3.19 V

HLVDL<3:0> = 1000 3.31 3.39 3.47 V

HLVDL<3:0> = 1001 3.46 3.55 3.63 V

HLVDL<3:0> = 1010 3.63 3.71 3.80 V

HLVDL<3:0> = 1011 3.81 3.90 3.99 V

HLVDL<3:0> = 1100 4.01 4.11 4.20 V

HLVDL<3:0> = 1101 4.23 4.33 4.43 V

HLVDL<3:0> = 1110 4.48 4.59 4.69 V

† Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterizati on.

PIC18F2423/2523/4423/4523

26.4 AC (Timing) Characteristics

26.4.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

using one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

TF Frequency T Time

Lowercase letters (pp) and their meanings:

pp cc CCP1 osc OSC1

ck CLKO rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T13CKI

mc MCLR wr WR

Uppercase letters and their meanings:

SF Fall P Period

HHigh RRise

I Invalid (High-Impedance) V Valid

L Low Z High-Impedance

I2C only

AA ou tput access H igh High

BUF Bus fr ee Low Low

TCC:ST (I2C specifications only)

CC HD Hold SU Setup

ST DAT DATA input hold STO Stop condition

STA Start condition

PIC18F2423/2523/4423/4523

26.4.2 TIMING CONDITIONS

The temperature and voltages specified in Table 26-5

apply to all timing specifications unless otherwise

noted. Figure 26-4 specifies the load conditions for the

timing specifications.

TABLE 26-5: TEMPERATURE AND VOLT AGE SPECIFICATIONS – AC

FIGURE 26-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Note: Because of space limitations, the generic

terms “PIC18FXXXX” and “PIC18LFXXXX”

are used throughout this section to refer to

the PIC18F2423/2523/4423/4523 and

PIC18LF2423/2523/4423/4523 families of

devices specifically and only those devices.

AC CHARACTERISTICS

Standard Operating Conditions (unle ss otherw is e stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Operating voltage VDD range as described in DC spec Section 26.1 and

Section 26.3.

LF parts operate for industrial temperatures only.

VDD/2

VSS

RL=464Ω

CL= 50 pF fo r all pins except OSC2/CLKO

and including D and E outputs as ports

Load Condition 1 Load Condition 2

PIC18F2423/2523/4423/4523

26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

23344

Param.

No. Symbol Characteristic Min Max Units Conditions

1A FCLKI Frequency CLKI External

Clock DC 40 MHz EC, ECIO Oscillator mode

DC 1 MHz XT Oscillator mode

DC 25 MHz HS Oscillator mode

4 10 MHz HS + PLL Oscillator mo de

DC 33 kHz LP Oscillator mo de

1B FOSC Oscillator DC 4 MHz RC Oscillator mode

4 10 MHz HS + PLL Oscillator mo de

5 33 kHz LP Oscill ator mode

1C TCLKI Period CLKI External

Clock 25 — ns EC, ECIO Oscillator mode

1000 — ns XT Oscillator mode

40 — ns HS Oscillator mode

100 250 ns HS + PLL Oscillator mo de

30 — μs LP Oscillator mode

1D Tosc Oscillator 250 — ns RC Oscillator mode

100 250 ns HS + PLL Oscillator mo de

30 — μs LP Os ci ll ator mo de

CY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC

3TOSL,

TOSHExternal Clock in (OSC1)

High or Low Time 30 — ns XT Oscillator mode

2.5 — μs LP Oscillator mo de

10 — ns HS Oscillator mode

OSR,

TOSFExtern al Clock in (OSC1) Rise or Fal l T ime — 20 ns XT Oscilla tor mode

— 50 ns LP Oscillator mode

— 7.5 ns HS Oscillator mode

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations

except PL L . All s pec ifi ed v alu es are b as ed on ch ara cte riz ation dat a for that parti cular os cilla tor type und er

sta nda rd o pera tin g c ond itions with the dev ic e e xe cu ting co de. Excee din g th es e s pec ifi ed l im its m ay res ult

in an unst abl e oscillator operati on and/or hi gher than e xpected c urrent con sumption. All devices are tested

to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock

input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

PIC18F2423/2523/4423/4523

TABLE 26-7: PLL CLOCK TI MING SPECIFICATIONS (VDD = 4.2V TO 5.5V)

TABLE 26-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY

PIC18F2423/2523/4423/4523 (INDUSTRIAL)

PIC18LF2423/2523/4423/4523 (INDUSTRIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only

F11 FSYS On-Chip VCO Syst em Fr equency 16 — 40 MH z HS mode only

F12 trc PLL Start-up Time (Lock Time) — — 2 ms

F13 ΔCLK CLKO Stability (Jitter) -2 — +2 %

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

PIC18LFX423/X523

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C for industrial

PIC18FX423/X523

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operati ng tem per ature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Device Min Typ Max Units Conditions

INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)

PIC18LFX423/X523 -2 +/-1 2 % +25°C VDD = 2.7-3.3V

-5 — 5 % -10°C to +85°C VDD = 2.7-3.3V

-10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V

PIC18FX423/X523 -2 +/-1 2 % +25°C VDD = 4.5-5.5V

-5 — 5 % -10°C to +85°C VDD = 4.5-5.5V

-10 +/-1 10 %-40°C to +85°C VDD = 4.5-5.5V

INTRC Accuracy @ Fre q = 31 kHz(2)

PIC18LFX423/X523 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V

PIC18FX423/X523 26.562 —35.938 kHz -40°C to +85°C VDD = 4.5-5.5V

Legend: Shading of rows is to assist in readability of the table.

Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.

2: INTRC frequency after calibration.

3: Change of INTRC frequency as VDD changes.

PIC18F2423/2523/4423/4523

FIGURE 26-6: CLKO AND I/O TIMING

TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS

Note: Refer to Figure 26-4 for load conditions.

OSC1

CLKO

I/O pin

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

Old Value New Value

Param

No. Symbol Characteristic Min Typ Max Units Conditions

10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1)

11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1)

12 TckR CLKO Rise Time — 35 100 ns (Note 1)

13 TckF CLKO Fall Time — 35 100 ns (Note 1)

14 TckL2ioV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)

15 TioV2ckH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1)

16 TckH2ioI Port In Hold after CLKO ↑ 0——ns(Note 1)

17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns

18 TosH2ioI OSC1 ↑ (Q2 cycle) to

Port Input Invalid

(I/O in hold time)

PIC18FXXXX 100 — — ns

18A PIC18LFXXXX 200 — — ns VDD = 2.0V

19 TioV2osH Port Input V alid to OSC1 ↑ (I/O in setup time) 0 — — ns

20 TioR Port Output Rise Time PIC18FXXXX — 10 25 ns

20A PIC18LFXXXX — — 60 ns VDD = 2.0V

21 TioF Port Output Fall Time PIC18FXXXX — 10 25 ns

21A PIC18LFXXXX — — 60 ns VDD = 2.0V

22† TINP I NT Pin High or Low Time TCY ——ns

23† TRBP RB7:RB4 Change INT High or Low Time TCY ——ns

24† TRCP RC7:RC4 Change INT High or Low Time 20 — — ns

† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

PIC18F2423/2523/4423/4523

FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 26-8: BROWN-OUT RESET TIMING

TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

30 TmcL MCLR Pulse Width (l ow) 2 — — μs

31 TWDT Watchdog Timer Time -out Perio d

(no postscaler) 3.47 4.00 4.82 ms 128 INTRC periods

32 TOST Oscillati on Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period

33 TPWRT Power-up Timer Period 55.4 65.5 77.1 ms 2048 INTRC periods

34 TIOZ I/O High-Impedance from MCLR

Low or Watchdog Ti mer Reset —2—μs

35 TBOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see D005)

36 TIVRST Time for Internal Reference

Voltage to become Stable —2050 μs

37 TLVD High/Low-Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD

38 TCSD CPU Start-up Time 5 — 10 μs

39 TIOBST Time for INTOSC to Stabilize 55.6 64.0 75.3 μs

VDD

MCLR

Internal

POR

PWRT

Time-out

Oscillator

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O pins

Note: Refer to Figure 26-4 for load conditions.

VDD BVDD

35 VBGAP = 1.2V

VIRVST

Enable Internal

Internal Reference 36

Reference V olt age

Voltage Stable

PIC18F2423/2523/4423/4523

FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

40 Tt0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

41 Tt0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

42 Tt0P T0CKI Period No prescaler TCY + 10 — ns

With prescaler Greater of:

20 ns or

(TCY + 40)/N

— ns N = prescale

value

(1, 2, 4,..., 256)

45 Tt1H T13CKI

Clock High

Time

Synchro nou s, no pres ca le r 0.5 TCY + 20 — ns

Synchronous,

with prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 25 — ns VDD = 2.0V

Asynchronous PIC18FXXXX 30 — ns

PIC18LFXXXX 50 — ns VDD = 2.0V

46 Tt1L T13CKI

Clock Low

Time

Synchro nou s, no pres ca le r 0.5 TCY + 5 — ns

Synchronous,

with prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 25 — ns VDD = 2.0V

Asynchronous PIC18FXXXX 30 — ns

PIC18LFXXXX 50 — ns VDD = 2.0V

47 Tt1P T13CKI

Clock Input

Period

Synchronous Greater of:

20 ns or

(TCY + 40)/N

— ns N = prescale

value (1, 2, 4, 8)

Asynchronous PIC18FXXXX 60 — ns

PIC18LFXXXX 100 — ns VDD = 2.0V

48 Tcke2tm rI Delay from External T13CKI Clock Edge to

Timer Increment 2 TOSC 7 TOSC —

49 Ft1 T13CKI Oscillator Input Frequency Range DC 50 kHz

Note: Refer to Figure 26-4 for load conditions.

T0CKI

T1OSO/T13CKI

TMR0 or

TMR1

PIC18F2423/2523/4423/4523

FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)

TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)

Note: Refer to Figure 26-4 for load conditions.

CCPx

(Capture Mode)

50 51

CCPx

53 54

(Compare or PWM Mode)

Param

No. Symbol Characteristic Min Max Units Conditions

50 T ccL CCPx Input Low

Time No prescaler 0.5 TCY + 20 — n s

With

prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 20 — ns VDD = 2.0V

51 TccH CCPx Input

High Time No prescaler 0.5 TCY + 20 — ns

With

prescaler PIC18FXXXX 10 — ns

PIC18LFXXXX 20 — ns VDD = 2.0V

52 TccP CCP x Input Pe riod 3 TCY + 40

N—nsN = prescale

value (1, 4 or 16)

53 TccR CCPx Output Fall Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

54 TccF CCPx Output Fall Time PIC1 8FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

PIC18F2423/2523/4423/4523

FIGURE 26-11: PARALLEL SLAVE PORT TIMING (PIC18F4423/4523)

TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4423/4523)

Note: Refer to Figure 26-4 for load conditions.

RE2/CS

RE0/RD

RE1/WR

RD7:RD0

Param.

No. Symbol Characteristic Min Max Units Conditions

62 TdtV2wrH Data In Valid before WR ↑ or CS ↑

(setup time) 20 — ns

63 TwrH2dtI WR ↑ or CS ↑ to Data– In

Invalid (hold time) PIC18FXXXX 20 — ns

PIC18LFXXXX 35 — ns VDD = 2.0V

64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns

65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns

66 TibfINH Inhibit of the IBF Flag bit being Cleared from

WR ↑ or CS ↑—3 T

PIC18F2423/2523/4423/4523

FIGURE 26-12 : EXAMPL E SPI MA STER MODE TIMING (CKE = 0)

TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76

MSb LSb

bit 6 - - - - - -1

MSb In LSb In

bit 6 - - - -1

Note: Refer to Figure 26-4 for load conditions.

Param

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS ↓ to SCK ↓ or SCK ↑ Inpu t TCY —ns

71 TscH SCK Input High Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

71A Sing le Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

72A Sing le Byte 40 — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns

73A Tb2b Last Clock Edge of Byte 1 t o the 1s t Clock Edge

of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SDO Data Output Fall Time — 25 ns

78 TscR SCK Output Rise Time

(Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Time (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after

SCK Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

PIC18F2423/2523/4423/4523

FIGURE 26-13 : EXAMPL E SPI MA STER MODE TIMING (CKE = 1)

TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

MSb In

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

LSb

Note: Refer to Figure 26-4 for load conditions.

Param.

No. Symbol Characteristic Min Max Units Conditions

71 TscH SCK Input High Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns

73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SD O Data Output Fall Time — 25 ns

78 TscR SCK Output Rise Time

(Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Time (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after

SCK Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

81 TdoV2scH,

TdoV2scL SDO Data Output Setup to SCK Edge TCY —ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

PIC18F2423/2523/4423/4523

FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY —ns

71 TscH SCK Input High Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73 TdiV2scH,

TdiV2scL Setup Time of SDI Data Input to SCK Edge 100 — ns

73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TdoR SDO Data Output Rise Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SDO Data Output Fall Time — 25 ns

77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns

78 TscR SCK Output Rise Ti me (Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Time (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

83 TscH2ssH,

TscL2ssH SS ↑ after SCK edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76 77

SDI

MSb LSb

bit 6 - - - - - -1

bit 6 - - - -1 LSb In

Note: Refer to Figure 26-4 for load conditions.

MSb In

PIC18F2423/2523/4423/4523

FIGURE 26-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param

No. Symbol Characteristic Min Max Units Conditions

70 TssL2scH,

TssL2scL SS ↓ to SCK ↓ or SCK ↑ Input TCY —ns

71 TscH SCK Input High Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TscL SCK Input Low Time

(Slave mode) Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TscH2diL,

TscL2diL Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TdoR SDO Da t a Ou t put Rise Time PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

76 TdoF SDO Da t a Ou t pu t Fall Time — 25 ns

77 TssH2doZ SS↑ to SDO Output High-Impedance 10 50 ns

78 TscR SCK Output Rise Time

(Master mode) PIC18FXXXX — 25 ns

PIC18LFXXXX — 45 ns VDD = 2.0V

79 TscF SCK Output Fall Time (Master mode) — 25 ns

80 TscH2doV,

TscL2doV SDO Data Output Valid after SCK

Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

82 TssL2doV SDO Data Output Valid after SS ↓

Edge PIC18FXXXX — 50 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

83 TscH2ssH,

TscL2ssH SS ↑ after SCK Edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

SDI

75, 76

MSb bit 6 - - - - - -1 LS b

MSb In bit 6 - - - -1 LSb In

Note: Refer to Figure 26-4 for load conditions.

PIC18F2423/2523/4423/4523

FIGURE 26-16 : I2C™ BUS START/STOP BITS TIMING

TABLE 26-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

FIGURE 26-17 : I2C™ BUS DATA TIMING

Note: Refer to Figure 26-4 for load conditions.

SCL

SDA

Start

Condition Stop

Condition

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated

Start condition

Setup Time 400 kHz mode 600 —

91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

Hold Time 400 kHz mode 600 —

92 TSU:STO Stop Condition 100 kHz mode 4700 — ns

Setup Time 400 kHz mode 600 —

93 THD:STO Stop C ondition 100 kHz mode 4000 — ns

Hold Time 400 kHz mode 600 —

Note: Refer to Figure 26-4 for load conditions.

91 92

100

101

103

106 107

109 109 110

102

SCL

SDA

Out

PIC18F2423/2523/4423/4523

TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 4.0 — μs

400 kHz mode 0.6 — μs

MSSP Module 1.5 TCY —

101 TLOW Clock Low Time 100 kHz mode 4.7 — μs

400 kHz mode 1.3 — μs

MSSP Module 1.5 TCY —

102 TRSDA and SCL Rise

Time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

103 TFSDA and SCL Fall

Time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

90 TSU:STA Start Condition

Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated

Start condition

400 kHz mode 0.6 — μs

91 THD:STA Start Cond iti on

Hold Time 100 kHz mode 4.0 — μs After this period, the first

clock pulse is generated

400 kHz mode 0.6 — μs

106 THD:DAT Data Input Hold

Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 μs

107 TSU:DAT Data Input Setup

Time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 1 00 — ns

92 TSU:STO Stop Condition

Setup Time 100 kHz mode 4.7 — μs

400 kHz mode 0.6 — μs

109 TAA Output Valid from

Clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be fr ee

before a new transmission

can start

400 kHz mode 1.3 — μs

D102 CBBus Capacitive Loading — 400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement,

TSU:DAT ≥250 ns, must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next dat a bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

standard mode I2C bus specification), before the SCL line is released.

PIC18F2423/2523/4423/4523

FIGURE 26-18: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS

TABLE 26-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS

FIGURE 26-19: MASTER SSP I2C™ BUS DATA TIMING

Note: Refer to Figure 26-4 for load conditions.

91 93

SCL

SDA

Start

Condition Stop

Condition

90 92

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Cond ition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for

Repeated Start

condition

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the

first clock pulse is

generated

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

Note 1: Maximum pin capacitance = 10 pF for all I2C pins.

Note: Refer to Figure 26-4 for load conditions.

90 91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

PIC18F2423/2523/4423/4523

TABLE 26-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Cloc k High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

102 TRSDA and SCL

Rise Time 100 kHz mode — 100 0 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

103 TFSDA and SCL

Fall Time 100 kHz mode — 300 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1) — 100 ns

90 TSU:STA Start Condition

Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for

Repeated Start

condition

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

91 THD:STA Start Condition

Hold Time 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first

clock pulse is generated

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

106 THD:DAT Data Input

Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 ms

107 TSU:DAT Data Input

Setup Time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

92 TSU:STO Stop Condition

Setup Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

109 TAA Output Valid

from Clock 100 kHz mode — 350 0 ns

400 kHz mode — 100 0 ns

1 MHz mode(1) ——ns

110 TBUF Bus Free T im e 100 kHz mode 4.7 — ms T im e the bu s must be free

before a new transmission

can st a rt

400 kHz mode 1.3 — ms

D102 CBBus Capacitive Loading — 400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C pins.

2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107 ≥250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the

SCL line is released.

PIC18F2423/2523/4423/4523

FIGURE 26-20: EUSART SYNCHRONOUS TRANSMIS S ION (MASTER/SLAVE) TIMING

TABLE 26-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 26-21: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 26-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

121 121

120 122

RC6/TX/CK

RC7/RX/DT

Note: Refer to Figure 26-4 for load conditions.

Param

No. Symbol Characteristic Min Max Units Conditions

120 TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock High to Data Out Valid PIC18FXXXX — 40 ns

PIC18LFXXXX — 100 ns VDD = 2.0V

121 Tckrf Clock Out Rise Time and Fall Time

(Master mode) PIC18FXXXX — 20 ns

PIC18LFXXXX — 50 ns VDD = 2.0V

122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns

PIC18LFXXXX — 50 ns VDD = 2.0V

125

126

RC6/TX/CK

RC7/RX/DT

Note: Refer to Figure 26-4 for load conditions.

Param.

No. Symbol Characteristic Min Max Units Conditions

125 TdtV2ckl SYNC RCV (MASTER & SLAVE)

Data Hold before CK ↓ (DT hold time) 10 — ns

126 TckL2dtl Data Hold after CK ↓ (DT hold time) 15 — ns

PIC18F2423/2523/4423/4523

TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18LF2423/2523/4423/4523 (INDUSTRIAL)

PIC18LF2423/2523/4423/4523 (INDUSTRIAL)

Param

No. Sym Characteristic Min Typ Max Units Conditions

A01 NRResolution — — 12 bit ΔVREF ≥ 3.0V

A03 EIL I ntegral Linearity Error — ±1 ± 1.5 LSb VDD = 3.0V ΔVREF ≥ 3.0V

——±2.0LSbV

DD = 5.0V

A04 EDL Differential Linearity Error — ±1 +1.5/-1.0 LSb VDD = 3.0V ΔVREF ≥ 3.0V

——TBDLSbV

DD = 5.0V

A06 EOFF Offset Error — ±1 ±5 LSb VDD = 3.0V ΔVREF ≥ 3.0V

——±3LSbV

DD = 5.0V

A07 EGN Gain Error — ±1 ±1.25 LSb VDD = 3.0V ΔVREF ≥ 3.0V

——±2.00LSbV

DD = 5.0V

A10 — Monotonicity Guaranteed(1) —VSS ≤ VAIN ≤ VREF

A20 ΔVREF Reference Voltage Range

(VREFH – VREFL)3—AV

DD – AVSS V For 12-bit resolution

A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V For 12-bit resolution

A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V For 12-bit resolution

A25 VAIN Analog Input Voltage VREFL —VREFH V

A30 ZAIN Recommended Imped-

ance of Analog Voltage

Source

——2.5kΩ

A50 IREF VREF Input Current(2) —

——

—5

150 μA

μADuring VAIN acquisitio n.

During A/D conve rsion

cycle.

Legend: TBD = To Be Determined

Note 1: The A/ D convers ion result never decreases with an increase in the input voltage and has no missing codes.

2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.

VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.

PIC18F2423/2523/4423/4523

FIGURE 26-22 : A/D CONVE RSION TIMING

TABLE 26-25: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

11 10 9 2 1 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . . . . .

TCY

Param

No. Symbol Characteristic Min Max Units Conditions

130 TAD A/D Clock Period PIC18FXXXX 0.8 12.5(1) μsTOSC based, VREF ≥ 3.0V

PIC18LFXXXX 1.4 25.0(1) μsVDD = 3.0V;

TOSC based, VREF full range

PIC18FXXXX TBD 1 μs A/D RC mode

PIC18LFXXXX TBD 3 μsV

DD = 3.0V; A/D RC mode

131 TCNV Conversion Time

(not including acquisition time)(2) 13 14 TAD

132 TACQ Acquisition Time(3) 1.4 — μs

135 TSWC Switching Time from Convert → Sample — (Note 4)

TBD TDIS Discharge Time 0.2 — μs

Legend: TBD = To Be Determined

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES registers may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage c hanges full sc ale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

27.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

Graphs and tables are not available at this time.

PIC18F2423/2523/4423/4523

NOTES:

PIC18F2423/2523/4423/4523

28.0 PACKAGING INFORMATION

28.1 Package Marking Information

28-Lead PDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F2523-I/SO

0710017

40-Lead PDIP

XXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F4423-I/P

0710017

Example

/SP

PIC18F2523-I

0710017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week c ode (wee k of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microc hip p art num ber cannot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

28-Lead QFN

XXXXXXXX

YYWWNNN

Example

18F2423

-I/ML

0710017

PIC18F2423/2523/4423/4523

Package Marking Information (Continue d)

44-Lead TQFP

XXXXXXXXXX

YYWWNNN

Example

PIC18F4423

-I/PT

0710017

XXXXXXXXXX

44-Lead QFN

XXXXXXXXXX

YYWWNNN

PIC18F4523

Example

-I/ML

0710017

PIC18F2423/2523/4423/4523

28.2 Package Details

The following sections give the technical details of the packages.

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e .100 BSC

Top to Seating Plane A – – .200

Molded Package Thickness A2 .120 .135 .150

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .335

Molded Package Width E1 .240 .285 .295

Overall Length D 1.345 1.365 1.400

Tip to Seating Plane L .110 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .040 .050 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-070

PIC18F2423/2523/4423/4523

28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 1.27 BSC

Overall Height A – – 2. 65

Molded Package Thickness A2 2.05 – –

Standoff § A1 0.10 – 0.30

Overall Width E 10.30 BSC

Molded Package Width E 1 7.50 BSC

Overall Length D 17.90 BSC

Chamfer (optional) h 0.25 – 0.75

Foot Length L 0.40 – 1.27

Footprint L1 1.40 REF

Foot Angle Top φ0° – 8°

Lead Thickness c 0.18 – 0. 33

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

Microchip Technology Drawing C04-052

PIC18F2423/2523/4423/4523

28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]

ith 0.55 mm Contact Length

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Package is saw singulated.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 28

Pitch e 0.65 BSC

Overall Height A 0.80 0 .90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Width E 6.00 BSC

Exposed Pad Width E2 3.65 3.70 4.20

Overall Length D 6.00 BSC

Exposed Pad Length D2 3.65 3 .70 4.20

Contact Width b 0.23 0.30 0.35

Contact Length L 0.50 0.55 0.70

Contact-to-Exposed Pad K 0.20 – –

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

Microchip Technology Drawing C04-105

PIC18F2423/2523/4423/4523

40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 40

Pitch e .100 BSC

Top to Seating Plane A – – .250

Molded Package Thickness A2 .125 – .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .590 – .625

Molded Package Width E1 .485 – .580

Overall Length D 1.980 – 2.095

Tip to Seating Plane L . 115 – .200

Lead Thickness c .008 – . 015

Upper Lead Width b1 .030 – .070

Lower Lead Width b .014 – .023

Overall Row Spacing § eB – – . 700

NOTE 1

123

A1 b1

Microchip Technology Drawing C04-016

PIC18F2423/2523/4423/4523

44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Chamf ers at corners are optional; size may vary.

. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Leads N 44

Lead Pitch e 0.80 BSC

Overall Height A – – 1. 20

Molded Package Thickness A2 0.95 1.00 1.05

Standoff A1 0.05 – 0.15

Foot Length L 0.45 0.60 0. 75

Footprint L1 1.00 REF

Foot Angle φ0° 3.5° 7°

Overall Width E 12.00 BSC

Overall Length D 12.00 BSC

Molded Package Width E1 10.00 BSC

Molded Package Length D1 10.00 BSC

Lead Thickness c 0.09 – 0. 20

Lead Width b 0.30 0.37 0.45

Mold Draft Angle Top α11° 12° 13°

Mold Draft Angle Bottom β11° 12° 13°

NOTE 1 NOTE 2

123

Microchip Technology Drawing C04-076

PIC18F2423/2523/4423/4523

44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Package is saw singulated.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 44

Pitch e 0.65 BSC

Overall Height A 0.80 0 .90 1.00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Width E 8.00 BSC

Exposed Pad Width E2 6.30 6.45 6.80

Overall Length D 8.00 BSC

Exposed Pad Length D2 6.30 6 .45 6.80

Contact Width b 0.25 0.30 0.38

Contact Length L 0.30 0.40 0.50

Contact-to-Exposed Pad K 0.20 – –

DEXPOSED

PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

A3A1

Microchip Technology Drawing C04-103

PIC18F2423/2523/4423/4523

APPENDIX A: REVISION HISTORY

Revision A (June 2006)

Original data sheet for PIC18F2423/2523/4423/4523

devices.

Revision B (January 2007)

This revision includes updates to the packaging

diagrams.

APPENDIX B: DEVICE

DIFFERENCES

The differences between the devices listed in this data

sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Features PIC18F2423 PIC18F2523 PIC18F4423 PIC18F4523

Progr am Memory ( Byt es) 16384 32768 16384 32768

Progr am M emory (Inst ru ct i ons ) 8192 1 6384 8192 16384

In terr u pt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Captur e/ Compare/PW M M od ul es 2 2 1 1

Enhanced

Captur e/ Compare/PW M M od ul es 00 1 1

Para llel Communi cations (P SP) No No Yes Yes

12-Bit An al og-to-Digi tal Modul e 10 in put channels 10 input ch annels 13 i npu t channels 13 input c han nel s

Packages 28-pin PDIP

28-pin SOIC

28-pin QF N

28-pin PDIP

28-pin SOIC

28-pin QF N

40-pin PDIP

44-pin TQFP

44-pin QFN

40-pin PDIP

44-pin TQFP

44-pin QFN

PIC18F2423/2523/4423/4523

APPENDIX C: CONVERSION

CONSIDERATIONS

This appendix discusses the considerations for

converting from previous versions of a device to the

ones listed in this data sheet. Typically, these changes

are due to the differences in the process technology

used. An example of this type of conversion is from a

PIC16C74A to a PIC16C74B.

Not Applicable

APPENDIX D: MIGRATION FROM

BASELINE TO

ENHANCED DEVICES

This section disc usses how to migrate fr om a Baseline

device (i.e., PIC16C5X) to an Enhanced MCU device

(i.e., PIC18FXXX).

The following are the list of modifications over the

PIC16C5X mic roc on trol ler fam il y:

Not Currently Av ail able

PIC18F2423/2523/4423/4523

APPENDIX E: MIGRATION FROM

MID-RANGE TO

ENHANCED DEVICES

A detailed discussion of the differences between the

mid-range MCU devices (i.e., PIC16CXXX) and the

enhanced devices (i.e., PIC18FXXX) is provided in

AN716, “Migrating Designs from PIC16C74A/74B to

PIC18C442”. The changes discussed, while device

specific, are generally applicable to all mid-range to

enhanced device migrations.

This Ap plicatio n Note is availab le as L iterature Nu mber

DS00716.

APPENDIX F: MIGRATION FROM

HIGH-END TO

ENHANCED DEVICES

A detailed d is cu ss ion of the m igra tio n pathway and di f-

ferences between the high-end MCU devices (i.e.,

PIC17CXXX) and the enhanced devices (i.e.,

PIC18FXXX) is provided in AN726, “PIC17CXXX to

PIC18CXXX Migration”. This Application Note is

available as Literature Number DS00726.

PIC18F2423/2523/4423/4523

NOTES:

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 377
PIC18F2423/2523/4423/4523
INDEX
A
A/D ................................................................................... 227
A/D Converter Interru p t, Configur in g   ........ ........... ....231
Acquisition Requirements  ......................... ........... ....232
ADCON0 Register ....................................................227
ADCON1 Register ....................................................227
ADCON2 Register ....................................................227
ADRESH Register  ............................................227, 230
ADRESL Register ....................................................227
Analog  Port Pins, Config u ring ... .................. .............234
Associ a te d  Re g i st e rs ..... ............... ................... ........236
Calculating the Minimum Required 
Acqui sition Tim e  ...... ............... ................... ......232
Configuring the Module ............................................231
Conversion Clock (TAD) ...........................................233
Conversion Status (GO/DONE Bit) ... .......................230
Conversions ............................................................. 235
Converter Characteristics ........................................360
Discharge .................................................................235
Operation in Power-Managed Modes ......................234
Selecting and Configuring 
Acqui sition Tim e  ...... ............... ................... ......233
Special Event Trigger (CCP) ....................................236
Use of the CCP2 Trigger ..........................................236
Absolute Maximum Ratings .............................................325
AC (Timing) Characteristics .............................................342
Load Conditions for Device 
Timing Sp e c ificatio ns ................ ............... ........343
Parame te r  Symbology  .............. ........................... ....342
Temperature and Voltage Specifications ................. 343
Timing Conditions ............................... .. .. .... ..... .... .. ..343
AC Characteristics
Internal RC Accuracy ...............................................345
Access Bank
Mapping with Indexed Literal 
Offset Mode  ........... .. .... .. ..... .. .. .. .... .. .. .. ..... .. .... .. ..72
ACKSTAT ........................................................................195
ACKSTAT Status Flag .....................................................195
ADCON0 Register ............................................................227
GO/DONE Bit  ...........................................................230
ADCON1 Register ............................................................227
ADCON2 Register ............................................................227
ADDFSR ..........................................................................314
ADDLW ............................................................................277
ADDULNK ........................................................................ 314
ADDWF ............................................................................ 277
ADDWFC .........................................................................278
ADRESH Register ............................................................227
ADRESL Register  ....................................................227, 230
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................278
ANDWF ............................................................................ 279
Assembler
MPASM Assembler ..................................................322
B
Bank Select Regis te r (BSR) .................. ....................... ......59
Baud Rate Generator .......................................................191
BC .................................................................................... 279
BCF ..................................................................................280
BF ....................................................................................195
BF Statu s Flag ..................... ....................... .....................195
Block Diagrams
A/D ........................................................................... 230
Analog Input Model .................................................. 231
Baud Rate Generator  .............................................. 191
Capture Mode Operation .................. .. ..... .. .... .. .. .. .. .. 141
Comparator Analog Input Model ........................ .. .. .. 241
Comparator I/O Operating Modes ........................... 238
Comparator Output  ........ ............... ......................... .. 240
Comparator Voltage Reference ................. .. .... .. .. .... 244
Comparator Voltage Reference 
Outpu t Bu ffer Ex amp l e  ............... ..................... 245
Compare Mode Operation ....................... .. .. .... .. .. .. .. 142
Device Clock .............................................................. 28
Enhanced PWM ..................................................... .. 149
EUSART Receive .................................................... 217
EUSART Transmit ................................................... 215
External Power-on Reset Circuit 
(Slow VDD Power-up) ........................................ 43
Fail-Safe Clock Monitor (FSCM) .............................. 265
Generic I/O Port  ....................................................... 105
High/Low-Voltage Detect with External Input  ...... .... 248
Interrupt Logic ............................................................ 92
MSSP (I2C Master Mode) ........................................ 189
MSSP (I2C Mode) ........................... .. .. ....... .. .... .. .. .... 170
MSSP (SPI Mode)  ................................................... 161
On-Chip  Rese t Circuit ......... ......................... .............. 41
PIC18F2423/2523 ..................................................... 10
PIC18F4423/4523 ..................................................... 11
PLL (HS Mode) .......................................................... 25
PORTD and PORTE (Parallel Slave Port) ............... 120
PWM Operation (Simplified ) ... ...... ...... ........... .......... 144
Reads from Flash Program Memory  ......................... 77
Single Comparator ................................................... 239
Table Read Operation ...................... .. ....... .. .. .... .. .. .... 73
Table Write Operation   ................ ................... ............ 74
Table Writes to Flash  Progr a m Memory ................ .... 79
Timer0 in 16-Bit Mode ............................................. 124
Timer0 in 8-Bit Mode ............................................... 124
Timer1 ..................................................................... 128
Timer1 (16-Bit Read/Write Mode) ............................ 128
Timer1 LP Oscillator ................................................ 129
Timer2 ..................................................................... 134
Timer3 ..................................................................... 136
Timer3 (16-Bit Read/Write Mode) ............................ 136
Watchdog Timer  .......... .. ....... .. .... .. .. .... ....... .. .... .. .. .... 262
BN .................................................................................... 280
BNC ................................................................................. 281
BNN ................................................................................. 281
BNOV .............................................................................. 282
BNZ ................................................................................. 282
BOR. See Brown-out Reset.
BOV ................................................................................. 285
BRA ................................................................................. 283
BRG. See Baud Rate Generator.
Brown-o u t Re set (BOR) ............ .................. ............... ........ 44
Detecting ................................................................... 44
Disabling in Sleep Mode ............................................ 44
Software Enabled  .......... ....... .... .... .. .... ......... .. .... .. .... .. 44
BSF .................................................................................. 283
BTFSC ............................................................................. 284
BTFSS ............................................................................. 284
BTG ................................................................................. 285
BZ .................................................................................... 286

PIC18F2423/2523/4423/4523
DS39755B-page 378 Preliminary © 2007 Microchip Technology Inc.
C
C Compilers
MPLAB C18 ...... ................... ....................... .............322
MPLAB C30 ...... ................... ....................... .............322
CALL ................................................................................286
CALLW ............................................................................. 315
Capture (CCP Module) .................................... .... .... .... .....141
Associ a te d  Re g i sters  ............................ ...................143
CCP Pin Configuration .............................................141
CCPRxH:CCPRxL Reg i s te rs  ....... ....... .............. .......141
Prescaler .................................................................. 141
Softwa re In terrupt  .................. ............... ...................141
Timer1/Timer3 Mode Selection ................................141
Capture (ECCP Module) ............................... .. .... .. .... .. .....148
Capture/Compare /PWM (CCP) .......... ................... ...........139
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................140
CCP2 Pin Assignment  .............................................140
CCPRxH Regist e r .......... .............. ............... .............140
CCPRxL Regi ster ........... ................... .............. .........140
Compare Mode. See Compare.
Interaction of CCP1 and CCP2 for 
Timer Resources ..............................................140
Module Configuration ...............................................140
Clock Sources ....................................................................28
Selectin g  th e  31 k Hz So u r ce ............................... .......29
Selection  Using OSCCON Register  .............. .............29
CLRF ................................................................................287
CLRWDT ..........................................................................287
Code Examples
16 x 16 Signed Multiply Routine  ................. .... .. .. .......90
16 x 16 Unsigned Multiply Routine  ................. .... ..... ..90
8 x 8 Signed Multiply Routine  ........................... .. .......89
8 x 8 Unsigned Multiply Routine  ................. .. .. .. .. .......89
Changing Between Capture Prescalers ...................141
Computed  GOTO Usin g  a n  Offset Val ue ...................56
Data EEPROM Read ............. ............... .....................85
Data EEPROM Refr e sh Rou tin e  ................... .............86
Data EEPROM Wr ite   ............. ......................... ...........85
Erasing a  Fl a sh Pr o g ram Memory Row ...... ...............78
Fast Register Stack ....................................................56
How to Clear RAM (Bank 1) Using 
Indirect Addressing ............................................68
Implementing a Real-Time Clock Using 
a Timer1 Interrupt Service  ... ............... .............131
Initializing PORTA ....................................................105
Initializing PORTB ....................................................108
Initializing PORTC ....................................................111
Initializing PORTD ....................................................114
Initializing PORTE ....................................................117
Loading the SSPBUF (SSPSR) R egister .................164
Reading a Flash Program Memory Word  ......... .........77
Saving STATUS, WREG and 
BSR Register s in RAM ...................... .......... .....103
Writing to Flash Program Memory  .......................80–81
Code Protection  ...............................................................253
COMF ...............................................................................288
Comparator ......................................................................237
Analog Input Connection Considerations  .................241
Associ a te d  Re g i sters  ............................ ...................241
Configuration ............................................................238
Effects of a Reset .....................................................240
Interrupts .................................................................. 240
Operation .................................................................239
Operation During Sleep  ...........................................240
Outputs .................................................................... 239
Reference ................................................................ 239
External Signal  ................................................ 239
Internal Signal .................................................. 239
Response Time .................... .. ....... .... .. .... .... ....... .. .... 239
Comparat o r Spe cifica tio n s  ................ .......... ............... ...... 34 0
Comparator Voltage Reference ........................ .. ....... .. .. .. 243
Accura cy  a n d Err o r ................ .............................. .... 244
Associ a te d  Re g i sters ..... ............... ................... ........ 245
Configuring .............................................................. 243
Connection Considerations .............................. .... .. .. 244
Effects of a Reset ........ .......... .......................... ........ 244
Operation During Sleep ........................................... 244
Compare (CCP Module)  ...... .... .. .... ......... .. .... .. .... ......... .. .. 142
Associ a te d  Re g i sters ..... ............... ................... ........ 143
CCP Pin Configuration ............................................. 142
CCPRx Register  .. .......... ......................... ................. 14 2
Softwar e  In terrup t Mode ........ ................... ............... 142
Special Event Trigger  .............................. 137, 142, 236
Timer1/Timer3 Mode Selection ................................ 142
Compare (ECCP Module) ..................... .. .. .... .. .. ....... .... .. .. 148
Computed GOTO ............................................................... 56
Configuration Bits  ............................................................ 253
Configuration Register Protection .................................... 270
Context Saving During Interrupts ..................................... 103
Conversi on  Co nsid e ratio n s .......... ............... ............... ...... 37 4
CPFSEQ .......................................................................... 288
CPFSGT .......................................................................... 289
CPFSLT ........................................................................... 289
Crystal Oscillator/Ceramic Resonator ....... ........ ....... .......... 23
Customer Change Notification Service ............................ 387
Customer Support .......................... ........... .... .... ........... .... 387
D
Data Addre ssing  Modes  ................ .............................. ...... 68
Comparing Addressing Modes with the 
Extended Instruction Set Enabled ..................... 71
Direct ......................................................................... 68
Indexed  Literal Offset  ........ ................... ............... ...... 70
Instruction s Affected ...................................... .... 70
Indirect ....................................................................... 68
Inherent and Literal  .................................................... 68
Data EEPROM
Code Protection .. ..................................................... 270
Data EEPRO M Mem ory ......... ................... ................... ...... 83
Associ a te d  Re g i sters ..... ............... ................... .......... 87
EEADR Register ........................................................ 83
EECON1 and EECON2 Regist e rs  ................... .......... 83
Operation During Code-Protect . ................................ 86
Protection Agai n st Spuriou s Write .... ............... .......... 86
Reading ..................................................................... 85
Using ......................................................................... 86
Write Verify ................................................................ 85
Writing ....................................................................... 85
Data Memor y ............ ................... ................... ................... 59
Access Ban k ........................ .................................. .... 62
and the Extended Instruction Set  .............................. 70
Bank Select Register (BSR)  ...................................... 59
General Purpose Registers  ....................................... 62
Map for PIC18F2423/4423  ........................................ 60
Map for PIC18F2523/4523  ........................................ 61
Special Function Registers ........................................ 63
DAW ................................................................................ 290
DC and AC Characteristics
Graphs and Tables .................................................. 363

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 379
PIC18F2423/2523/4423/4523
DC Characteristic s ...........................................................337
Power-Down and Supply Current  ............................328
Supply Voltage .........................................................327
DCFSNZ ..........................................................................291
DECF ...............................................................................290
DECFSZ ...........................................................................291
Development Support  ......................................................321
Device Differences ...........................................................373
Device Overview ..................................................................7
Details on Individual Family Members .........................8
Features (tabl e )  .... .............. ................... .......................9
New Core Features ......................................................7
Other Special Features ................................................8
Device Reset Timers ..........................................................45
Oscillator Start-up Timer (OST) .................................45
PLL Lock Time-out .....................................................45
Power-up  Tim e r ( PWRT)   ....... ............... ............... ......45
Time-out Sequence ................................... .. ....... .... ....45
Direct Add ressi ng ................. ................... ...........................69
E
Effect on Standard PIC MCU Instructions ..... .... ............. ..318
Effects of Power-Managed Modes on 
Vario u s Clock Source s ......... ............... .......................31
Electrical Characteristics  ..................................................325
Enhanced Capture/Compare/PWM (ECCP) ....................147
Associ a te d  Re g i sters ...................... ................... ......160
Capture and Compare Modes  .. ................................148
Capture Mode. See Capture (ECCP Module).
Enhanced PWM Mode .............................................149
Outputs and Configuration .......................................148
Pin Configurations for ECCP1  .................................148
PWM Mode. See PWM (ECCP Module).
Special Event Trigger ...............................................148
Standard PWM Mode  ...............................................148
Timer Resources ......................................................148
Enhanced Universal Synchronous As ynchr onous 
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acqui sition Tim e  ....................... ................... ......232
A/D Minimu m Charging Time ........ .............. .............232
Errata ...................................................................................6
EUSART
Asynchronous Mode ................................................215
Associated Registers, Receive ........................218
Associ a te d  Re g isters,  Transmit ...... .................216
Auto-Wake-up on Sync 
Break Chara cter ..... ............... ...................218
Break Character Sequence  .............................220
Receiver ...........................................................217
Receiving a Break Character ...........................220
Setting Up 9-Bit Mode with 
Address Detect ........................................217
Transmitter .......................................................215
Baud Rate Generator
Operation in Power-Managed Mode ................209
Baud Rate Generator (BRG) ....................................209
Associ a te d  Re g i sters .................... ...................210
Auto-Baud Rate Dete c t ..... .................. .............213
Baud Rate Error, Calculating ................... .... ....210
Baud Rates, Asynchronous Modes   . ................211
High Baud Rate Select (BRGH Bit)  .................209
Sampling ..........................................................209
Synchronous Master Mode . .. ...... ........ ............... ...... 221
Associa ted  Re gi sters, Receive .............. .......... 223
Associ a te d  Register s,  Tran smit ............. .......... 222
Reception ........................................................ 223
Transmission ................................................... 221
Synchronous Slave Mode ...................................... .. 224
Associa ted  Re gi sters, Receive .............. .......... 225
Associ a te d  Register s,  Tran smit ............. .......... 224
Reception ........................................................ 225
Transmission ................................................... 224
Extended Instruction Set
ADDFSR .................................................................. 314
ADDULNK ............................................................... 314
CALLW .................................................................... 315
Considerations for Use ............................................ 318
MOVSF .................................................................... 315
MOVSS .................................................................... 316
PUSHL ..................................................................... 316
SUBFSR .................................................................. 317
SUBULNK ................................................................ 317
Syntax ...................................................................... 313
Using MPLAB IDE Tools  ......................................... 320
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor  ........................................... 253, 265
Exiting  Op e ration ... ............... ......................... .......... 265
Interrupts in Power-Managed Modes  ... ................... 266
POR or Wake from Sleep ........................................ 266
WDT During Oscillator Failure ...... ...... ..................... 265
Fast Register Stack  ........................................................... 56
Flash Pr o g ram Memory ............................ ......................... 73
Associ a te d  Re g i sters . ............... ............................. .... 82
Control Reg i s te rs ... ............... .............. ............... ........ 74
EECON1 and EECON2 .............. ..................... .. 74
TABLAT (Ta b l e  Lat ch) Regist e r  ........ .......... ...... 76
TBLPTR (Tab l e  Po in ter) Regi ster .... .................. 76
Erase Sequence ............................. .... ............. .... ...... 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Boundaries Based on Operation  ....................... 76
Table Pointer Boundaries ............. ................. ...... ...... 76
Table Reads and Table Writes ...................... .. .... .. .. .. 73
Write Sequence ......................................................... 79
Writing To .................................................................. 79
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 292
H
Hardware Mult ip lier ........ ........... .............. ........... .............. .. 89
Introduction ................................................................ 89
Operation ................................................................... 89
Performance Comparison .......................................... 89

PIC18F2423/2523/4423/4523
DS39755B-page 380 Preliminary © 2007 Microchip Technology Inc.
High/Lo w -V o ltage Detect  ..... .............. ............... ...............247
Applications ..............................................................250
Associ a te d  Re g i sters  ............................ ...................251
Characteristics .........................................................341
Curren t Cons u mption ............... ......................... .......249
Effects of a Reset .....................................................251
Operation .................................................................248
During Sleep ....................................................251
Setup ........................................................................249
Start- u p  Time  ...... .............................. .................. .....249
Typical Low-Voltage Application ............. .. .... .. .. .......250
HLVD. See High/Low-Voltage Detect. 
I
I/O Ports ....... ............................................. .......................105
I2C Mode (MSSP)
Acknowledge Sequence Timing ...............................198
Baud Rate Generator ...............................................191
Bus Collision
During a Repeated Start Condition ..................202
During a Stop Condition ...................................203
Clock Arbitration .......................................................192
Clock Stretching .......................................................184
10-Bit Slave Receive Mode (SEN = 1) .............184
10-Bit Slave Transmit Mode .............................184
7-Bit Slave Receive Mode (SEN = 1) ...............184
7-Bit Slave Transmit Mode ...............................184
Clock Synchroniza tio n a nd the  CKP bit  ...................185
Effects of a Reset .....................................................199
General Call Address Support  .................................188
I2C Clock Rate w/BRG .............................................191
Master Mode ............................................................189
Operation .........................................................190
Reception .........................................................195
Repeated Start Condition Timing .....................194
Start Condition Timing  .............................. .......193
Transmission ....................................................195
Multi-Master Communication, Bus Collision 
and Arbitration ............................. .. .. .. .. .. .. .. .......199
Multi-Master Mode  ...................................................199
Operation .................................................................175
Read/Write Bit Information (R/W Bit) ...............175, 177
Registers .................................................................. 170
Serial Clock (RC3/SCK/SCL) ...................................177
Slave Mode ..............................................................175
Addressing ....................................................... 175
Reception .........................................................177
Transmission ....................................................177
Sleep Operation .......................................................199
Stop Condition Timin g  ....................... .............. .........198
ID Locations .............................................................253, 270
INCF .................................................................................292
INCFSZ ............................................................................293
In-Circuit Debugger ..........................................................270
In-Circuit Serial Programming (ICSP)  ......................253, 270
Indexed Literal Offset Addressing
and Standard PIC18 Instructions .............................318
Indexed Literal Offset Mode ......... .... .. .. ....... .. .... .. .. .... .. .....318
Indirect Addressing  ............................................................69
INFSNZ ............................................................................293
Initialization Conditions for all Registers  ......................49–52
Instruction Cycle .................................................................57
Clocking Scheme .......................................................57
Instruction Flow/Pipelining  .................................................57
Instruction Set
ADDLW .................................................................... 277
ADDWF .................................................................... 277
ADDWF (Indexed Literal Offset Mode) .................... 319
ADDWFC ................................................................. 278
ANDLW .................................................................... 278
ANDWF .................................................................... 279
BC ............................................................................279
BCF ......................................................................... 280
BN ............................................................................280
BNC ......................................................................... 281
BNN ......................................................................... 281
BNOV ...................................................................... 282
BNZ ......................................................................... 282
BOV ......................................................................... 285
BRA ......................................................................... 283
BSF .......................................................................... 283
BSF (Indexed Literal Offset Mode) .......................... 319
BTFSC ..................................................................... 284
BTFSS ..................................................................... 284
BTG ......................................................................... 285
BZ ............................................................................ 286
CALL ........................................................................ 286
CLRF ....................................................................... 287
CLRWDT ................................................................. 287
COMF ...................................................................... 288
CPFSEQ .................................................................. 288
CPFSGT .................................................................. 289
CPFSLT ................................................................... 289
DAW ........................................................................ 290
DCFSNZ .................................................................. 291
DECF ....................................................................... 290
DECFSZ .................................................................. 291
Extended Instruction Set  ......................................... 313
General Format ...................... ......... .... .... .... ......... .... 273
GOTO ...................................................................... 292
INCF ........................................................................ 292
INCFSZ .................................................................... 293
INFSNZ .................................................................... 293
IORLW ..................................................................... 294
IORWF ..................................................................... 294
LFSR ....................................................................... 295
MOVF ...................................................................... 295
MOVFF .................................................................... 296
MOVLB ....................................................................296
MOVLW ................................................................... 297
MOVWF ................................................................... 297
MULLW .................................................................... 298
MULWF .................................................................... 298
NEGF ....................................................................... 299
NOP ......................................................................... 299
Opcode Field Descriptions ....................................... 272
POP ......................................................................... 300
PUSH ....................................................................... 300
RCALL ..................................................................... 301
RESET ..................................................................... 301
RETFIE .................................................................... 302
RETLW .................................................................... 302
RETURN .................................................................. 303
RLCF ....................................................................... 303
RLNCF ..................................................................... 304
RRCF ....................................................................... 304
RRNCF .................................................................... 305
SETF ....................................................................... 305

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 381
PIC18F2423/2523/4423/4523
SETF (Indexed Literal Offset Mode) ........................319
SLEEP .....................................................................306
Standard Instructions ...............................................271
SUBFWB ..................................................................306
SUBLW .................................................................... 307
SUBWF .................................................................... 307
SUBWFB ..................................................................308
Summary ..................................................................271
SWAPF .................................................................... 308
TBLRD .....................................................................309
TBLWT .....................................................................310
TSTFSZ ...................................................................311
XORLW ....................................................................311
XORWF ....................................................................312
INTCON Registers .......................................................93–95
Inter-Integrated Circuit. See I2C.
Internal Oscillator Block  .....................................................26
Adjustment .................................................................26
INTIO Modes ..............................................................26
INTOSC Frequency Drift ............................................26
INTOSC Output Frequency .... ..................... ...............26
OSCTUNE Regis te r ..... .......... ................... ............... ..26
PLL in INTOSC Modes  ..................... .... .. .... ....... .... ....26
Internal RC Oscillator
Use with WDT ..........................................................262
Inter n e t Ad d ress ........ ................... .................................. ..387
Inter rupt Sources  ......................... ....................................253
A/D Convers i o n  Compl e te   ........ .......... ............... ......231
Interrupt-on-Change (RB7:RB4)  ..............................108
INTn Pin ...................................................................103
PORTB, Interrupt-on-Change  ................................ ..103
TMR0 .......................................................................103
TMR1 Overflow ........................................................127
TMR2 to PR2 Match (PWM)  ............................144, 149
TMR3 Overflow ........................................................135
Interrupts ............................................................................91
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag 
(RBIF Bit) ................. ....................... .................108
INTO SC, INTRC.  See Internal Oscillator Block.
IORLW .............................................................................294
IORWF ............................................................................. 294
IPR Regist e rs ...... ............... ............... .................. .............100
L
LFSR ................................................................................ 295
Low-Voltage ICSP Programmin g. See Single-Su pply 
ICSP Programm ing.
M
Master Clear (MCLR) ......................................................... 43
Master Synchronous Serial Port (MSSP). See MSSP .
Memory Organization .........................................................53
Data Memor y  .... ................... ................... ...................59
Program Memory .......................................................53
Mem o r y Prog ra m min g  Requireme n ts .......... ......... ...... .....3 3 9
Microc h i p  In ternet  Web Site ..... ................... ................... ..387
Migration from Baseline to 
Enhanced Devices ................. ........... .... ...... ......... ....374
Migration from High-End to 
Enhanced Devices ................. ........... .... ...... ......... ....375
Migration from Mid-Range to 
Enhanced Devices ................. ........... .... ...... ......... ....375
MOVF ...............................................................................295
MOVFF ............................................................................296
MOVLB ............................................................................ 296
MOVLW ........................................................................... 297
MOVSF ............................................................................ 315
MOVSS ............................................................................ 316
MOVWF ........................................................................... 297
MPLAB ASM30 Assembler, Linker, Librarian .................. 322
MPLAB ICD 2 In-Circuit Debugger .......................... .... .. .. 323
MPLAB ICE 2000 High-Perf orm ance Univers a l 
In-Circuit Emulator ................................................... 323
MPLAB ICE 4000 High-Perf orm ance Univers a l 
In-Circuit Emulator ................................................... 323
MPLAB Integrated Development 
Environ ment Software .................. ........................... 321
MPLAB PM3 Device Programmer ................................... 323
MPLINK Object Linker/MPLIB Object Librarian ............... 322
MSSP
ACK Pulse ................. .. ....... .... .. .... .. .. ....... .... .. .. 175, 177
Control Registers (general)  ................................... .. 161
I2C Mode. See I2C Mode.
Module Overview ..................................................... 161
SPI Master/Slave Connection  .................................. 165
SPI Mode. See SPI Mode.
SSPBUF Register .................................................... 166
SSPSR Regist e r ...... ................... ............... .............. 166
MULLW ............................................................................ 298
MULWF ............................................................................ 298
N
NEGF ............................................................................... 299
NOP ................................................................................. 299
O
Oscillator Configuration  ..................................................... 23
EC .............................................................................. 23
ECIO .......................................................................... 23
HS .............................................................................. 23
HSPLL ....................................................................... 23
Internal Oscillator Block ............................................. 26
INTIO1 ....................................................................... 23
INTIO2 ....................................................................... 23
LP .............................................................................. 23
RC ............................................................................. 23
RCIO .......................................................................... 23
XT .............................................................................. 23
Oscillat o r Selection ...... ............... .......... ........... ................ 253
Oscillator S tart-up Timer (OST) ............ ...... ................. 31, 45
Oscillat or S wi tching  ... .......... ....... .............. ........... .......... .... 28
Oscillato r Trans itions ....... ...... ....... .......... ........... .......... ...... 29
Oscillator, Timer1 ..................................................... 127, 137
Oscillator, Timer3 ............................................................. 135
P
Packagi n g  In fo rmation ... ................... ................... ............ 365
Details (Diagrams) ................................................... 367
Marking .................................................................... 365
Parallel Slave Port (PSP) ......................................... 114, 120
Associ a te d  Re g i sters . ............... ............................. .. 121
CS (Chip Select)  ...................................................... 120
PORTD .................................................................... 120
RD (Read Input)  ...................................................... 120
Select (PSPMODE Bit) . ... ................................ 114, 120
WR (Write Input) .............................................. .... .... 120
PICSTART Plus Development Programmer .................... 324
PIE Registers ..................................................................... 98

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Pin Functions
MCLR/VPP/RE3 ....................................................12, 16
OSC1/CLKI/RA7 ..................................................12, 16
OSC2/CLKO/RA6 ................................................12, 16
RA0/AN0 .............................................................. 13, 17
RA1/AN1 .............................................................. 13, 17
RA2/AN2/VREF-/CVREF ........................................ 13, 17
RA3/AN3/VREF+ ...................................................13, 17
RA4/T0CKI/C1OUT ..............................................13, 17
RA5/AN4/SS/HLVDIN/C2OUT .............................13, 17
RB0/INT0/FLT0/AN12 ..........................................14, 18
RB1/INT1/AN10 ...................................................14, 18
RB2/INT2/AN8 .....................................................14, 18
RB3/AN9/CCP2 ...................................................14, 18
RB4/KBI0/AN11 ...................................................14, 18
RB5/KBI1/PGM ....................................................14, 18
RB6/KBI2/PGC ....................................................14, 18
RB7/KBI3/PGD ....................................................14, 18
RC0/T1OSO/T13CKI ...........................................15, 19
RC1/T1OSI/CCP2 ................................................ 15, 19
RC2/CCP1 .................................................................15
RC2/CCP1/P1A .........................................................19
RC3/SCK/SCL .....................................................15, 19
RC4/SDI/SDA ......................................................15, 19
RC5/SDO .............................................................15, 19
RC6/TX/CK ..........................................................15, 19
RC7/RX/DT ..........................................................15, 19
RD0/PSP0 ..................................................................20
RD1/PSP1 ..................................................................20
RD2/PSP2 ..................................................................20
RD3/PSP3 ..................................................................20
RD4/PSP4 ..................................................................20
RD5/PSP5/P1B .......................................................... 20
RD6/PSP6/P1C ..........................................................20
RD7/PSP7/P1D ..........................................................20
RE0/RD/AN5 .............................................................. 21
RE1/WR/AN6 ............................................................. 21
RE2/CS/AN7 .............................................................. 21
VDD .......................................................................15, 21
VSS .......................................................................15, 21
Pinout I/O Descriptions
PIC18F2423/2523 ...................................................... 12
PIC18F4423/4523 ...................................................... 16
PIR Regist e rs .................. ............... ......................... ...........96
PLL Frequency Multiplier  ...................................................25
HSPLL Oscillator Mode ......................... .... .... .... .........25
Use with INTOSC .......................................................25
POP ..................................................................................300
POR. See Power-on Reset.
PORTA
Associ a te d  Re g i sters  ............................ ...................107
LATA Register ..........................................................105
PORTA Register ......................................................105
TRISA Register ........................................................105
PORTB
Associ a te d  Re g i sters  ............................ ...................110
LATB Register ..........................................................108
PORTB Register ......................................................108
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit)  ..........108
TRISB Register ........................................................108
PORTC
Associ a te d  Re g i sters  ............................ ...................113
LATC Register  .........................................................111
PORTC Register ......................................................111
RC3/SCK/SCL Pin  ......... .............. .......................... ..177
TRISC Register ......... ............... ............... .................111
PORTD
Associ a te d  Re g i sters ..... ............... ................... ........ 116
LATD Register ......................................................... 114
Para ll e l  Sl a ve  Po r t  ( PSP) Fun ctio n  ............ ..... ...... .. . 114
PORTD Register ...................................................... 114
TRISD Regist e r ...... .............. ............... ..................... 114
PORTE
Associ a te d  Re g i sters ..... ............... ................... ........ 119
LATE Register  .. ................... .............................. ...... 117
PORTE Register ...................................................... 117
PSP Mode Select (PSPM OD E Bit) .......................... 114
TRISE Register ........................................................ 117
Power-Managed Modes ............................................... .... .. 33
and A/D Operation ................................................... 234
and Multiple Sleep Commands .................................. 34
and PWM Operation ................................................ 159
and SPI Operation ................................................... 169
Clock Transitions and Status Indicators  .................... 34
Effects on Clock Sources ........................................... 31
Entering ..................................................................... 33
Exiting Idle and Sleep Modes ..................... ........... ....39
by Interrupt  ........................................................ 39
by Reset  ............................................................ 39
by WDT Time-out .............................................. 39
Without a Start-up Delay  ................ .. ......... .... .. .. 40
Idle Modes ................................................................. 37
PRI_IDLE ........................................................... 38
RC_IDLE ...........................................................39
SEC_IDLE ......................................................... 38
Run Modes  ................................................................ 34
PRI_RUN ...........................................................34
RC_RUN ............................................................ 35
SEC_RUN .........................................................34
Selecting .................................................................... 33
Sleep Mode  ............................................................... 37
Summary (table)  ................................... ..................... 33
Power-on Reset (POR) ...................................................... 43
Time-out Sequence  .................................. .. ......... .. .... 45
Power-up Delays  ............................................................... 31
Power-up Timer (PWRT) ................................................... 31
Prescaler
Timer2 ..................................................................... 150
Presca le r, Timer0  ...................... ................... ............... .... 125
Presca le r, Timer2  ...................... ................... ............... .... 145
PRI_IDLE Mode ................................................................. 38
PRI_RUN Mode ................................................................. 34
Program Counter ........ ....................................................... 54
PCL, PCH and PCU Registers  .................................. 54
PCLATH and PCLATU Registers ............... ....... .... .... 54
Program Mem ory
and Extended Instruction Set  .................................... 72
Code Protection .. ..................................................... 268
Instructions ................................................................ 58
Two-Word .......................................................... 58
Interrupt Vector .......................................................... 53
Look-up Tables ...................... ....... .. .... .. .... ....... .... .. .... 56
Map and Stack (diagram)  .......................................... 53
Reset Vec to r .................... .............................. ............ 53
Program Verification and Code Protection  ...................... 267
Associ a te d  Re g i sters ..... ............... ................... ........ 267
PSP. See Parallel Slave Port.
Pulse-Width Modulation. See PWM (CCP Module) 
and PWM (ECCP Module).
PUSH ............................................................................... 300
PUSH and PO P In structions ............... ............................... 55
PUSHL ............................................................................. 316

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 383
PIC18F2423/2523/4423/4523
PWM (CCP Module)
Associ a te d  Re g i sters ...................... ................... ......146
Auto-Shutdown (CCP1 Only) ...................................145
Duty Cycle .............. .............. .......................... ..........144
Example Frequencies/Resolutions  ..........................145
Period .......................................................................144
Setup for PWM Operation  ......................... ...............145
TMR2 to PR2 Match  ................................................144
PWM (ECCP Modul e) .............. ................... ............... ......149
CCPR1H:CCPR1L Registers ...................................149
Direction Change in Full-Bridge 
Output Mode ............ .. .... ..... .. .. .. .. .... .. .. ..... .. .... ..154
Duty Cycle .............. .............. .......................... ..........150
Effects of a Reset .....................................................159
Enhanced PWM Auto-Shutdown  .............................156
Example Frequencies/Resolutions  ..........................150
Full-Bridge Application Example ..............................154
Full-Bridge Mode ..................................... .. ......... .... ..153
Half-Bridge Mode .....................................................152
Half-Bridge Output Mode 
Applications Example  ......................................152
Operation in Power-Managed Modes ......................159
Operation with Fail-Safe Clock Monitor  ...................159
Output Co nf ig u r a tio n s .... ............... ..................... ......150
Output Relatio n s h i ps (Active-High)  ......... ....... ...... ....151
Output Re latio n ships (Active-Low)  .............. ........... ..151
Period .......................................................................149
Programmable Dead-Band Delay ........... .... ......... ....156
Setup for PWM Operation  ......................... ...............159
Start- u p Co nsid e ration s ....... ............... ........... ..........158
TMR2 to PR2 Match  ................................................149
Q
Q Clock  ................................ .. .... .. ......... .. .... .. .... .. .....145, 150
R
RAM. See Data Memory .
RBIF Bit ............................ ............................. ...................108
RC Oscillator ......................................................................25
RCIO Oscillator Mode ................................................25
RC_IDLE Mode ..................................................................39
RC_RUN Mode ..................................................................35
RCALL .............................................................................301
RCON Register
Bit Sta tu s  Dur i n g  Initialization ................. ............... ....48
Reader Response ............................................................388
Register File ....................... ................... ................... ..........62
Register File Summary  ................................................64–66
Registers
ADCON0 (A/D Control 0) .........................................227
ADCON1 (A/D Control 1) .........................................228
ADCON2 (A/D Control 2) .........................................229
BAUDCON (Baud Rate Control) ..............................208
CCP1CON (Enhanced Capture/Compare/PWM 
Control 1) ......... ................... ................... ..........147
CCPxCON (Standard Capture/Compare/PWM 
Control) ............................................................ 139
CMCON (C o mpar a tor C o n tro l )   .... ...... .......... ..... ...... . 2 3 7
CONFIG1H (Configuration 1 High) ..........................254
CONFIG2H (Configuration 2 High) ..........................256
CONFIG2L (Configuration 2 Low) ............................255
CONFIG3H (Configuration 3 High) ..........................257
CONFIG4L (Configuration 4 Low) ............................257
CONFIG5H (Configuration 5 High) ..........................258
CONFIG5L (Configuration 5 Low) ............................258
CONFIG6H (Configuration 6 High) ..........................259
CONFIG6L (Configuration 6 Low) ........................... 259
CONFIG7H (Configuration 7 High) .......................... 260
CONFIG7L (Configuration 7 Low) ........................... 260
CVRCON (Comparator Voltage 
Reference Control) .......................................... 243
DEVID1 (De vice  ID 1) ..................... ............... .......... 261
DEVID2 (De vice  ID 2) ..................... ............... .......... 261
ECCP1AS (ECCP Auto-Shutdown Control) ............ 157
ECCP1DEL (Dead-Band Delay) .................. ...... .... .. 157
EECON1 (EEPROM Control 1 )  ................... ........ 75, 84
HLVDCON (High/Low-Voltage 
Detect Control) ................................................ 247
INTCON (Interrupt Contr ol)  ....................................... 93
INTCON2 (Interrupt Control 2)  .................................. 94
INTCON3 (Interrupt Control 3)  .................................. 95
IPR1 (Peripheral Interrupt Priority 1) ....................... 100
IPR2 (Peripheral Interrupt Priority 2) ....................... 101
OSCCON (Oscillator Control) .................................... 30
OSCTUNE (Oscillator Tun i n g )  ..................... .......... .... 27
PIE1 (Peripheral Interrupt Enable 1)  .... ..................... 98
PIE2 (Peripheral Interrupt Enable 2)  .... ..................... 99
PIR1 (Peripheral Interrupt Request 
(Flag) 1 ) ................. ................... ................... ...... 96
PIR2 (Peripheral Interrupt Request 
(Flag) 2 ) ................. ................... ................... ...... 97
RCON (Reset Control) ....................................... 42, 102
RCSTA (Receive Status and Control)  ..................... 207
SSPADD (MSSP  Address) ......... ............... .............. 174
SSPCON 1 (M SSP Control 1, I2C Mode) ................. 172
SSPCON1 (M SSP  Control 1, SPI Mode)  . ............... 163
SSPCON 2 (M SSP Control 2, I2C Mode) ................. 173
SSPSTAT (MSS P St atus,  I2C Mode)  . ....... .. .... .. .. .... 171
SSPSTA T  (MSS P St atus, SPI  Mode) ......... ............ . 162
STATUS .................................................................... 67
STKPTR (St a ck Poin ter) ......... ................... .............. .. 55
T0CON (Timer0 Con tr o l) ........ ............... .......... ........ 123
T1CON (Timer1 Con tr o l) ........ ............... .......... ........ 127
T2CON (Timer2 Con tr o l) ........ ............... .......... ........ 133
T3CON (Timer3 Con tr o l) ........ ............... .......... ........ 135
TRISE (PORTE/PSP Control)  ................................. 118
TXSTA (Transmit Status and Con trol) ......... ............ 206
WDTCON (Watchdog Timer Contr ol) ...................... 263
RESET ............................................................................. 301
Reset State of Registers .................................................... 48
Resets ....................................................................... 41, 253
Brown-o u t Re set (BOR) ........ .............. ..................... 253
Oscillator Start-up Timer (OST) .. ................. ............ 253
Power-on Reset (POR) ............................................ 253
Power-up Timer (PWRT) ......................................... 253
RETFIE ............................................................................ 302
RETLW ............................................................................ 302
RETURN .......................................................................... 303
Return Add ress St a ck  .... ................... ....................... .......... 54
Return Stack Point e r (STKPTR) ....... .......... ............... ........ 55
Revision History ............................................................... 373
RLCF ............................................................................... 303
RLNCF ............................................................................. 304
RRCF ............................................................................... 304
RRNCF ............................................................................ 305
S
SCK ................................................................................. 161
SDI ................................................................................... 161
SDO ................................................................................. 161
SEC_IDLE Mode  ............................................................... 38
SEC_RUN Mode ................................................................ 34

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Serial Clock, SCK .............................................................161
Serial Data In (SDI) .......... ................................................161
Serial Data Out (SDO)  .....................................................161
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 305
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 161
SLEEP ..............................................................................306
Sleep
OSC1 and OSC2 Pin States ................... .. .. .... .. .. .......31
Softwa re Simulato r (MP L AB SIM) ............... .....................322
Special Event Trigger. See Compare (ECCP Mode).
Speci a l Feat u res of the CPU ...... ............... .............. .........253
Special Function Registers  ................................................63
Map ............................................................................63
SPI Mode (MSSP )
Associ a te d  Re g i sters  ............................ ...................169
Bus Mode Compatibility ......... ............. .......... ...... .....169
Effects of a Reset .....................................................169
Enabling SPI I/O  ......................................................165
Master Mode ............................................................166
Master/Slave Connection ............... ....... .. .. .... .. .... .....165
Operation .................................................................164
Operation in Power-Managed Modes  ......................169
Serial Clock ..............................................................161
Serial Data In ...........................................................161
Serial Data Out  ........................................................161
Slave Mode ..............................................................167
Slave Select .............................................................161
Slave Select Synchronization  ..................................167
SPI Clock .................................................................166
Typica l Co nnec tion  ............ ............... .............. .........165
SS ....................................................................................161
SSPOV .............................................................................195
SSPOV Status Flag ..........................................................195
SSPSTAT Register
R/W Bit .............................................................175, 177
Stack Full/Underflow Resets ..............................................56
SUBFSR ...........................................................................317
SUBFWB ..........................................................................306
SUBLW ............................................................................307
SUBULNK ........................................................................317
SUBWF ............................................................................307
SUBWFB ..........................................................................308
SWAPF ............................................................................308
T
Table Pointer Operations (table) ........................................76
Table Reads/Table Writes ..................................................56
TBLRD .............................................................................309
TBLWT ............................................................................. 310
Time-out in Various Situations (table) ................................45
Timer0 .............................................................................. 123
Associ a te d  Re g i sters  ...................................... .........125
Interrupt ....................................................................125
Operation .................................................................124
Prescaler .................................................................. 125
Presca le r Assignme n t ( PS A Bit)  ................. .............125
Prescaler Select (T0PS2:T0PS0 Bits)  .....................125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode . ...........................124
Source Edge Select (T0SE Bit) ................................124
Source  Se le ct (T0CS Bit) ............. ........... .................124
Switching  Prescaler  Assignmen t ......... .......... ...........125
Timer1 ..............................................................................127
16-Bit Read/Write Mode  ........................... .. ....... .. .. .. 129
Associ a te d  Re g i sters ..... ............... ................... ........ 131
Interrupt ................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Layout Considera tions ................ ................... .. 130
Overflow  In terrupt ..................... .................. ............. 127
Resetting, Using the CCP 
Special Event Trigger ......................................130
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Rea l-Time Clock ....................................... 130
Timer2 ..............................................................................133
Associ a te d  Re g i sters ..... ............... ........................... 134
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register  ................................................... 144, 149
TMR2 to PR2 Match Interrupt .......................... 144, 149
Timer3 ..............................................................................135
16-Bit Read/Write Mode  ........................... .. ....... .. .. .. 137
Associ a te d  Re g i sters ..... ............... ................... ........ 137
Interrupt ................................................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow  In terrupt ..................... .................. ............. 135
Special Event Trigger (CCP) ................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
Timing Diagrams
A/D Conver sion .... .............. ......................... ............. 361
Acknowledge Sequence .......................................... 198
Asynchronous Receptio n ......................................... 218
Asynchronous Tran smiss ion . ................................... 216
Asynchronous Tra nsmiss ion 
(Back-to-Back) ................................................. 216
Automatic Baud Rate Calculation ............................ 214
Auto-Wake-up Bit (WUE) During 
Normal Operation .... ............... ......................... 219
Auto-Wake-up Bit (WUE) During Sleep ................... 219
Baud Rate Generator with Clock Arbitration ............ 192
BRG Overflow Sequence ......................................... 214
BRG Reset Due to SDA Arbitration During 
Start Condition ................................................. 201
Brown-o ut Re set (BOR) ................ .............. ............. 347
Bus Collision During a Repeated Start 
Condition (Case 1) ........................................... 202
Bus Collision During a Repeated Start 
Condition (Case 2) ........................................... 202
Bus Collision During a Start 
Condition (SCL = 0) ......................................... 201
Bus Collision During a Stop 
Condition (Case 1) ........................................... 203
Bus Collision During a Stop 
Condition (Case 2) ........................................... 203
Bus Collision During Start 
Condition (SDA Only) ...................................... 200
Bus Collision for Transmit and Acknowledge  .......... 199
Capture/Compare/PWM (All CCP Modules) ............ 349
CLKO and I/O .......................................................... 346
Clock Synchronization ............................................. 185
Clock/Instruction Cycle .............................................. 57

© 2007 Microchip Technology Inc. Preliminary DS39755B-page 385
PIC18F2423/2523/4423/4523
EUSART Synchronous Receiv e 
(Master/Slave) .................................................359
EUSART Synchronous T ransm ission 
(Master/Slave) .................................................359
Example SPI Master Mode (CK E = 0)  .....................351
Example SPI Master Mode (CK E = 1)  .....................352
Example SPI Slave Mode (CKE = 0)  .......................353
Example SPI Slave Mode (CKE = 1)  .......................354
External Clock (All Modes Except PLL) ...................344
Fail -Safe  C l o c k Mon it o r ( F SC M) .. ...... ...... ..... .......... .2 6 6
First Start Bit Timing  ................. ...............................193
Full-Bridge PWM Output ..........................................153
Half-Bridge PWM Output  .........................................152
High/Low-Voltage Detect Characteristics  ................341
High-Voltage Detect Operation 
(VDIRMAG = 1) .............. ............... ...................250
I2C Bus Data ............................................................355
I2C Bus Start/Stop Bits .............................................355
I2C Master Mode (7 or 10-Bit Transmission)  ...........196
I2C Master Mode (7-Bit Reception) ..........................197
I2C Slave Mode (10-Bit Reception, SEN = 0) ..........182
I2C Slave Mode (10-Bit Reception, SEN = 0, 
ADMSK = 01001) ......... ....... .. .... .. .. .... .. ....... .. .. ..181
I2C Slave Mode (10-Bit Reception, SEN = 1) ..........187
I2C Slave Mode (10-Bit Transmission) . ....................183
I2C Slave Mode (7-bit Reception, SEN = 0) . ............178
I2C Slave Mode (7-bit Reception, SEN = 0, 
ADMSK = 01011) ......... ....... .. .... .. .. .... .. ....... .. .. ..179
I2C Slave Mode (7-Bit Reception, SEN = 1) ............186
I2C Slave Mode (7-Bit Transmission) .......................180
I2C Slave Mode General Call Address 
Sequence (7 or 10-Bit Address Mode)  ............188
I2C Stop Condition Receive or Transmit Mode ........198
Low-Voltage Detect Operation 
(VDIRMAG = 0) .............. ............... ...................249
Master SSP I2C Bus Data ........................................357
Master SSP I2C Bus Start/Stop Bits  ........................357
Parallel Slave Port (PIC18F4423/4523) ...................350
Parallel Slave Port (PSP) Read  ...............................121
Paral l e l  Sla ve Port (PS P)  Write  ....................... ........121
PWM Auto-Shutdown (PRSEN = 0, 
Auto-R e start Disabled)  ................... .................158
PWM Auto-Shutdown (PRSEN = 1, 
Auto-Restart Enabled)  .....................................158
PWM Direction Change  ................................... .... ....155
PWM Direction Change at Near 
100% Duty Cycle .............................................155
PWM Output   ................ ....................... ................... ..144
Repeat Start Condition ...................... .. .. .... .. ..... .. .... ..194
Reset, Watchdog Timer (WDT), Oscillator 
Start-up Timer (OST), Power-up 
Timer (PWRT) ..................................................347
Send Break Character Sequenc e ............................220
Slave Synchronization  .............................................167
Slow VDD Rise Time (MCLR Tied to VDD, 
VDD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) .........................................166
SPI Mode (Slave Mode, CKE = 0)  . ..........................168
SPI Mode (Slave Mode, CKE = 1)  . ..........................168
Synchronous Reception 
(Master Mode, SREN)  .....................................223
Synchronous Transmission ......................................221
Synchronous Transmission 
(Through TXEN)  ..............................................222
Time-out Sequence on POR w/PLL Enabled 
(MCLR Tied to VDD) .......................................... 47
Time-out Sequence on Power-up 
(MCLR Rises After TOST Completes) ................ 46
Time-out Sequence on Power-up 
(MCLR Rises Before TOST Completes) ............. 46
Time-out Sequence on Power-up 
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 46
Timer0 and Timer1 External Clock .......................... 348
Transition for Entry to Idle Mode  ............................. .. 38
Transition for Entry to SEC_RUN Mode ........ .. .. .. .... .. 35
Transition for Entry to Sleep Mode .......................... .. 37
Transition for Two-Speed Start-up 
(INTOSC to HSP L L) ........... ............... .............. 264
Transition for Wake from Idle to 
Run Mode .......................................................... 38
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to 
PRI_RUN Mode ................................................. 36
Transition from SEC_RUN Mode to 
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
Timing Diagrams and Specifications  ............................... 344
A/D Conversion Requirements ................................ 361
Capture/Compare/PWM Requirements ................... 349
CLKO and I/O Requirements ................................... 346
EUSART Synchronous  Receive 
Requirements .................................................. 359
EUSART Synchronous  Transmission 
Requirements .................................................. 359
Example SPI Mode Requireme nts 
(Master Mode, CKE = 0) .................................. 351
Example SPI Mode Requireme nts 
(Master Mode, CKE = 1) .................................. 352
Example SPI Mode Requireme nts 
(Slave Mode, CKE = 0) .................................... 353
Example SPI Mode Requireme nts 
(Slave Mode, CKE = 1) .................................... 354
External Clock Requirements .................................. 344
I2C Bus Data Requirements 
(Slave Mode) ................................................... 356
I2C Bus Start/Stop Bits Requirements 
(Slave Mode) ................................................... 355
Master SSP I 2C Bus Data 
Requirements .................................................. 358
Master SSP I 2C Bus Start /S top Bits 
Requirements .................................................. 357
Parallel Slave Port Requirements 
(PIC18F4423/4523) ......................................... 350
PLL Clock ................................................................ 345
Reset, Watchdog Timer, Oscillator Start-up 
Timer, Power-up Timer and Brown-out 
Reset Requirements ................................ .... .... 347
Timer0 and Timer1 External 
Clock Requirements ........................................ 348
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit  ......................................................... 114
TSTFSZ ........................................................................... 311
Two-Speed Start-up ................................................. 253, 264
Two-Word Instructions
Example Cases  ......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 209

PIC18F2423/2523/4423/4523
DS39755B-page 386 Preliminary © 2007 Microchip Technology Inc.
V
Voltage Reference Specifications ............................. .......340
W
Watchdog Timer (WDT)  ................. .... .... ........... .... ...253, 262
Associ a te d  Re g i sters  ............................ ...................263
Control Reg i ster ...... ............... ............... ...................262
During Oscillator Failure  ..........................................265
Programming Consi dera tions  ................. ............... ..262
WCOL  ......................................................193, 194, 195, 198
WCOL Status Flag ...................................193, 194, 195, 198
WWW Address .................................................................387
WWW, On-Line Support  . ......................................................6
X
XORLW ............................................................................ 311
XORWF ........................................................................... 312

PIC18F2423/2523/4423/4523

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PIC18F2423/2523/4423/4523

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DS39755BPIC18LF2423/2523/4423/4523

1. What are the best features of this docume nt?

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PIC18F2423/2523/4423/4523

PIC18F2423/2523/4423/4523 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device PIC18F2423/2523(1), PIC18F4423/4523(1),

PIC18F2423/2523T(2), PIC 1 8F 44 23 /45 2 3T(2);

VDD range 4.2V to 5.5V

PIC18LF2423/2523(1), PIC18LF4423/4523(1),

PIC18LF2423/2523T(2), PIC18LF4423/4523T(2);

VDD range 2.0V to 5.5V

Temperatu re R ang e I = -40°C to +85°C (Industrial)

Package PT = TQFP (Thin Quad Flatpack)

SO = SOIC

SP = Skinny Plastic DIP

P=PDIP

ML = QFN

Pattern QTP, SQTP, Code or Special Requirements

(blank oth erwi se )

Examples:

a) PIC18F4 523 -I/ P 301 = Industria l temp., PD IP

package, Normal VDD limi ts , QTP p att ern #3 01.

b) PIC18F2423-I/SO = Industrial temp., SOIC

package, Normal VDD limits.

c) PIC18F4423-I/P = Industrial temp., PDIP

package, Normal VDD limits.

Note 1: LF = Low-Voltage Range

2: T = In tape and reel

(TQFP packages only)

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12/08/06