LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 2.9 nV/sqrt(Hz) Low Noise, RRIO Amplifier Check for Samples: LMP7732 FEATURES DESCRIPTION * * The LMP7732 is a dual low noise, rail-to-rail input and output, low voltage amplifier. The LMP7732 is part of the LMPTM amplifier family and is ideal for precision and low noise applications with low voltage requirements. 1 23 * * * * * * * * * * (Typical Values, TA = 25C, VS = 5V) Input Voltage Noise - f = 3 Hz 3.3 nV/Hz - f = 1 kHz 2.9 nV/Hz CMRR 130 dB Open Loop Gain 130 dB GBW 22 MHz Slew Rate 2.4 V/s THD 0.001% @ f = 10 kHz, AV = 1, RL = 2 k Supply Current 4.4 mA Supply Voltage Range 1.8V to 5.5V Operating Temperature Range -40C to 125C Input Bias Current 1.5 nA RRIO The LMP7732 provides a wide GBW of 22 MHz while consuming only 4 mA of current. This high gain bandwidth along with the high open loop gain of 130 dB enables accurate signal conditioning in applications with high closed loop gain requirements. The LMP7732 has a supply voltage range of 1.8V to 5.5V, making it an ideal choice for battery operated portable applications. APPLICATIONS * * * This operational amplifier offers low voltage noise of 2.9 nV/Hz with a 1/f corner of only 3 Hz. The LMP7732 has bipolar junction input stages with a bias current of only 1.5 nA. This low input bias current, complemented by the very low level of voltage noise, makes the LMP7732 an excellent choice for photometry applications. Gas Analysis Instruments Photometric Instrumentation Medical Instrumentation The LMP7732 is offered in the 8-Pin SOIC and VSSOP packages. The LMP7731 is the single version of this product and is offered in the 5-Pin SOT-23 and 8-Pin SOIC packages. Typical Performance Characteristics Input Voltage Noise vs. Frequency Input Current Noise vs. Frequency 100 100 10 VS = 2.5V, 3.3V, 5V CURRENT NOISE (pA/ Hz) VOLTAGE NOISE (nV/ Hz) VS = 2.5V, 3.3V, 5V VCM = 0.5V VCM = 2.5V VCM = 0.5V 10 VCM = 2.5V 1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 1 0.1 1 10 100 1k 10k FREQUENCY (Hz) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LMP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2013, Texas Instruments Incorporated LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Human Body Model ESD Tolerance (3) For inputs pins only 2000V For all other pins 2000V Machine Model 200V Charge Device Model 1000V VIN Differential 2V Supply Voltage (VS = V+ - V-) 6.0V -65C to 150C Storage Temperature Range Junction Temperature (4) +150C max Soldering Information (1) (2) (3) (4) Infrared or Convection (20 sec) 235C Wave Soldering Lead Temp. (10 sec) 260C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC board. Operating Ratings (1) -40C to 125C Temperature Range Supply Voltage (VS = V+ - V-) Package Thermal Resistance (JA) (1) 2 1.8V to 5.5V 8-Pin SOIC 190 C/W 8-Pin VSSOP 235C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 2.5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 2.5V, V- = 0V, VCM = V+/2, RL >10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Typ (3) Max (2) VCM = 2.0V 9 500 600 VCM = 0.5V 9 500 600 VCM = 2.0V 0.5 5.5 VCM = 0.5V 0.2 5.5 VCM = 2.0V 1 30 45 VCM = 0.5V 12 50 75 VCM = 2.0V 1 50 75 VCM = 0.5V 11 60 80 Parameter Conditions Min (2) Input Offset Voltage (4) VOS TCVOS IB Input Offset Voltage Temperature Drift Input Bias Current IOS Input Offset Current TCIOS Input Offset Current Drift CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio VCM = 0.5V and VCM = 2.0V 0.0474 0.15V VCM 0.7V 0.23V VCM 0.7V 101 89 120 1.5V VCM 2.35V 1.5V VCM 2.27V 105 99 129 2.5V V+ 5V 105 101 113 1.8V V+ 5.5V CMVR Common Mode Voltage Range Large Signal CMRR 80 dB + AVOL Open Loop Voltage Gain 0 112 104 130 RL = 2 k to V+/2 VOUT = 0.5V to 2.0V 109 90 119 (1) (2) (3) (4) dB 50 75 RL = 2 k to V+/2 13 50 75 RL = 10 k to V /2 6 50 75 RL = 2 k to V+/2 9 50 75 Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 22 12 31 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 15 10 44 V dB 4 mV from either rail mA VCM = 2.0V 4.0 5.4 6.8 VCM = 0.5V 4.6 6.2 7.8 AV = +1, CL = 10 pF, RL = 10 k to V+/2 VOUT = 2 VPP 2.4 Supply Current Slew Rate nA nA/C RL = 10 k to V+/2 Output Voltage Swing Low SR nA 2.5 RL = 10 k to V /2 VOUT = 0.5V to 2.0V + IS V/C dB VOUT Output Current V 111 Output Voltage Swing High IOUT Units mA V/s Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum Ratings indicate junction temperature limits beyond which the device maybe permanently degraded, either mechanically or electrically. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Ambient production test is performed at 25C with a variance of 3C. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 3 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com 2.5V Electrical Characteristics(1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 2.5V, V- = 0V, VCM = V+/2, RL >10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol GBW Parameter Gain Bandwidth Min (2) Conditions Typ (3) + 21 + CL = 20 pF, RL = 10 k to V /2 Max (2) Units MHz GM Gain Margin CL = 20 pF, RL = 10 k to V /2 14 dB M Phase Margin CL = 20 pF, RL = 10 k to V+/2 60 deg RIN Input Resistance THD+N Total Harmonic Distortion + Noise en Input Referred Voltage Noise Density Input Voltage Noise in 4 Input Referred Current Noise Density Differential Mode 38 k Common Mode 151 M 0.002 % AV = 1, fO = 1 kHz, Amplitude = 1V f = 1 kHz, VCM = 2.0V 3.0 f = 1 kHz, VCM = 0.5V 3.0 0.1 Hz to 10 Hz 75 f = 1 kHz, VCM = 2.0V 1.1 f = 1 kHz, VCM = 0.5V 2.3 Submit Documentation Feedback nV/Hz nVPP pA/Hz Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 3.3V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Typ (3) Max (2) VCM = 2.5V 6 500 600 VCM = 0.5V 6 500 600 VCM = 2.5V 0.5 5.5 VCM = 0.5V 0.2 5.5 VCM = 2.5V 1.5 30 45 VCM = 0.5V 13 50 77 VCM = 2.5V 1 50 70 VCM = 0.5V 11 60 80 Parameter Conditions Min (2) Input Offset Voltage (4) VOS TCVOS IB Input Offset Voltage Temperature Drift Input Bias Current IOS Input Offset Current TCIOS CMRR PSRR Input Offset Current Drift Common Mode Rejection Ratio VCM = 0.5V and VCM = 2.5V 0.048 0.15V VCM 0.7V 0.23V VCM 0.7V 101 89 120 1.5V VCM 3.15V 1.5V VCM 3.07V 105 99 130 2.5V V+ 5.0V 105 101 Power Supply Rejection Ratio 1.8V V+ 5.5V CMVR Common Mode Voltage Range Large Signal CMRR 80 dB + AVOL Open Loop Voltage Gain RL = 10 k to V /2 VOUT = 0.5V to 2.8V + RL = 2 k to V /2 VOUT = 0.5V to 2.8V 0 (1) (2) (3) (4) nA/C 3.3 112 104 130 110 92 119 V dB RL = 10 k to V+/2 5 50 75 RL = 2 k to V+/2 14 50 75 RL = 10 k to V /2 9 50 75 RL = 2 k to V+/2 13 50 75 Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 28 22 45 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 25 20 48 mV from either rail mA VCM = 2.5V 4.2 5.6 7.0 VCM = 0.5V 4.8 6.4 8.0 AV = +1, CL = 10 pF, RL = 10 k to V+/2 VOUT = 2 VPP 2.4 Supply Current Slew Rate nA dB Output Voltage Swing Low SR nA 111 + IS V/C 113 VOUT Output Current V dB Output Voltage Swing High IOUT Units mA V/s Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum Ratings indicate junction temperature limits beyond which the device maybe permanently degraded, either mechanically or electrically. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Ambient production test is performed at 25C with a variance of 3C. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 5 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com 3.3V Electrical Characteristics(1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol GBW Parameter Gain Bandwidth Min (2) Conditions Typ (3) + 22 + CL = 20 pF, RL = 10 k to V /2 Max (2) Units MHz GM Gain Margin CL = 20 pF, RL = 10 k to V /2 14 dB M Phase Margin CL = 20 pF, RL = 10 k to V+/2 62 deg THD+N Total Harmonic Distortion + Noise AV = 1, fO = 1 kHz, Amplitude = 1V RIN 0.002 % Differential Mode 38 k Common Mode 151 M Input Referred Voltage Noise Density f = 1 kHz, VCM = 2.5V 2.9 nV/Hz f = 1 kHz, VCM = 0.5V 2.9 Input Voltage Noise 0.1 Hz to 10 Hz 75 nVPP Input Referred Current Noise Density f = 1 kHz, VCM = 2.5V 1.1 pA/Hz f = 1 kHz, VCM = 0.5V 2.1 Input Resistance en in 5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Typ (3) Max (2) VCM = 4.5V 6 500 600 VCM = 0.5V 6 500 600 VCM = 4.5V 0.5 5.5 VCM = 0.5V 0.2 5.5 VCM = 4.5V 1.5 30 50 VCM = 0.5V 14 50 85 VCM = 4.5V 1 50 70 VCM = 0.5V 11 65 80 Parameter Conditions Min (2) Input Offset Voltage (4) VOS TCVOS IB Input Offset Voltage Temperature Drift Input Bias Current IOS Input Offset Current TCIOS CMRR PSRR Input Offset Current Drift Common Mode Rejection Ratio VCM = 0.5V and VCM = 4.5V 0.0482 0.15V VCM 0.7V 0.23V VCM 0.7V 101 89 120 1.5V VCM 4.85V 1.5V VCM 4.77V 105 99 130 2.5V V+ 5V 105 101 113 Power Supply Rejection Ratio 1.8V V+ 5.5V CMVR AVOL (1) (2) (3) (4) 6 Common Mode Voltage Range Open Loop Voltage Gain Large Signal CMRR 80 dB Units V V/C nA nA nA/C dB dB 111 0 5 RL = 10 k to V+/2 VOUT = 0.5V to 4.5V 112 104 130 RL = 2 k to V+/2 VOUT = 0.5V to 4.5V 110 94 119 V dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum Ratings indicate junction temperature limits beyond which the device maybe permanently degraded, either mechanically or electrically. All limits are specified by testing, statistical analysis or design. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Ambient production test is performed at 25C with a variance of 3C. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 5V Electrical Characteristics(1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5V, V- = 0V, VCM = V+/2, RL > 10 k to V+/2. Boldface limits apply at the temperature extremes. Symbol Typ (3) Max (2) RL = 10 k to V+/2 8 50 75 RL = 2 k to V+/2 24 50 75 RL = 10 k to V+/2 9 50 75 RL = 2 k to V+/2 23 50 75 Parameter Min (2) Conditions Output Voltage Swing High VOUT Output Voltage Swing Low IOUT Output Current IS Supply Current SR GBW Slew Rate Gain Bandwidth Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 33 27 47 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 30 25 49 mV from either rail mA VCM = 4.5V 4.4 6.0 7.4 VCM = 0.5V 5.0 6.8 8.4 AV = +1, CL = 10 pF, RL = 10 k to V+/2 VOUT = 2 VPP Units mA 2.4 V/s + 22 MHz + CL = 20 pF, RL = 10 k to V /2 GM Gain Margin CL = 20 pF, RL = 10 k to V /2 12 dB M Phase Margin CL = 20 pF, RL = 10 k to V+/2 65 deg RIN Input Resistance THD+ N Total Harmonic Distortion + Noise en Input Referred Voltage Noise Density Input Voltage Noise in Input Referred Current Noise Density Differential Mode 38 k Common Mode 151 M 0.001 % AV = 1, fO = 1 kHz, Amplitude = 1V f = 1 kHz, VCM = 4.5V 2.9 f = 1 kHz, VCM = 0.5V 2.9 0.1 Hz to 10 Hz 75 f = 1 kHz, VCM = 4.5V 1.1 f = 1 kHz, VCM = 0.5V 2.2 nV/Hz nVPP pA/Hz Connection Diagram 8-Pin SOIC/VSSOP 1 A 3 B + +IN A 7 + 2 -IN A V 8 - 4 6 - OUT A 5 + V OUT B -IN B +IN B Figure 1. Top View Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 7 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Offset Voltage Distribution 10 9 TCVOS Distribution 25 VS = 2.5V VS = 2.5V, 3.3V VCM = 0.5V VCM = 0.5V 20 PERCENTAGE (%) PERCENTAGE (%) 8 7 6 5 4 3 15 10 5 2 1 0 -40 -30 -20 -10 0 10 20 30 0 -0.5 40 0 VOS (PV) Figure 2. Offset Voltage Distribution 1.5 TCVOS Distribution 25 VS = 3.3V, 5V VS = 5V VCM = 0.5V VCM = 0.5V 20 PERCENTAGE (%) PERCENTAGE (%) 8 1 Figure 3. 10 9 0.5 TCVOS (PV/C) 7 6 5 4 3 15 10 5 2 1 0 -40 -30 -20 -10 0 10 20 30 0 -0.5 40 0 VOS (PV) Figure 4. 1 1.5 Figure 5. Offset Voltage Distribution TCVOS Distribution 14 9 VS = 2.5V VS = 2.5V, 5V 8 12 VCM = 2V VCM = VS - 0.5V PERCENTAGE (%) 7 PERCENTAGE (%) 0.5 TCVOS (PV/C) 6 5 4 3 10 8 6 4 2 2 1 0 -40 -30 -20 8 -10 0 10 20 30 40 0 -0.5 0 0.5 VOS (PV) TCVOS (PV/C) Figure 6. Figure 7. Submit Documentation Feedback 1 1.5 Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Offset Voltage Distribution TCVOS Distribution 14 8 VS = 3.3V, 5V VS = 3.3V 7 12 VCM = 2.5V, 4.5V VCM = 2.5V 10 PERCENTAGE (%) PERCENTAGE (%) 6 5 4 3 8 6 4 2 2 1 0 -40 -30 -20 -10 0 10 20 30 0 -0.5 40 0 Figure 8. Figure 9. Offset Voltage vs. Temperature 1.5 Offset Voltage vs. Temperature 100 VS = 2.5V, 3.3V, 5V 75 VCM = 0.5V 5 TYPICAL PARTS 50 20 10 0 VS = 2.5V, 3.3V, 5V VCM = 2V, 2.5V, 4.5V 5 TYPICAL PARTS 25 VOS (PV) VOS (PV) 1 TCVOS (PV/C) 40 30 0.5 VOS (PV) 0 -25 -10 -50 -20 -75 -30 -40 -20 0 20 40 -100 -40 -20 80 100 120 60 0 TEMPERATURE (C) 20 40 60 80 100 120 TEMPERATURE (C) Figure 10. Figure 11. PSRR vs. Frequency CMRR vs. Frequency 160 0 VS = 2.5V, 3.3V, 5V 140 -20 -PSRR 120 CMRR (dB) PSRR (dB) -40 -60 VS = 2.5V -80 +PSRR 100 -100 60 40 -120 20 VS = 3.3V -140 10 80 100 VS = 5V & 3.3V 1k 10k 100k 1M 10M 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 9 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Offset Voltage vs. Supply Voltage Offset Voltage vs. VCM 5 100 VS = 2.5V 50 -5 VOS (PV) OFFSET VOLTAGE (PV) 75 25C 0 -40C -10 125C 25 85C 25C 0 -15 -40C -25 85C -20 -50 -25 1.5 125C 2 2.5 3 3.5 4 4.5 5 -75 5.5 0 0.5 1 SUPPLY VOLTAGE (V) Figure 14. Offset Voltage vs. VCM Offset Voltage vs. VCM VS = 5V VS = 3.3V 75 50 50 VOS (PV) 125C VOS (PV) 2.5 100 75 85C 25 25C 0 -40C -25 125C 25 85C 25C 0 -40C -25 -50 -50 -75 -75 0 0.5 1 1.5 2 2.5 3 3.3 0 1 2 3 4 5 VCM (V) VCM (V) Figure 16. Figure 17. Input Offset Voltage Time Drift Slew Rate vs. Supply Voltage 3.4 5.0 RISING EDGE 3.2 4.0 SLEW RATE (V/Ps) OFFSET VOLTAGE DRIFT (PV) 2 Figure 15. 100 3.0 2.0 3 2.8 FALLING EDGE 2.6 AV = +1 2.4 VIN = 1 VPP VS = 5V 1.0 RL = 2 k: 5 TYPICAL UNITS 2.2 0.0 0 50 100 150 200 250 300 TIME (s) 2 1.5 RL = 10 k: CL = 10 pF 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 18. 10 1.5 VCM (V) Figure 19. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Time Domain Voltage Noise Time Domain Voltage Noise Figure 20. Figure 21. Time Domain Voltage Noise Output Voltage vs. Output Current 1000 VS = 2.5V, 3.3V, 5V VOUT FROM RAIL (mV) 800 VS = 2.5V 600 400 SINK 200 0 -200 -400 SOURCE -600 -800 0 5 10 15 20 25 30 OUTPUT CURRENT (mA) Figure 22. Figure 23. Input Bias Current vs. VCM Input Bias Current vs. VCM 100 100 VS = 2.5V 125C 60 85C 40 25C 20 0 -20 -40 -40C -60 60 85C 40 25C 20 0 -20 -40C -40 -60 -80 -80 -100 VS = 3.3V 125C 80 INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (nA) 80 -100 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 VCM (V) VCM (V) Figure 24. Figure 25. 2.5 3 3.5 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 11 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Input Bias Current vs. VCM Open Loop Frequency Response Over Temperature 100 100 INPUT BIAS CURRENT (nA) 225 VS = 5V 125C 80 GAIN 80 180 60 60 20 GAIN (dB) 25C 0 -20 -40 PHASE 20 45 VS = 2.5V, TA = 25C -40C 0 0 VS = 2.5V, 3.3V, 5V -20 RL = 10 k: TA = -40C, 25C, 85C, 125C -40 1M 10M 100k 1k 10k -80 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VCM (V) FREQUENCY (Hz) Figure 26. Figure 27. Open Loop Frequency Response Open Loop Frequency Response 225 VS = 5V GAIN GAIN 180 80 135 60 RL = 10 k: 180 CL = 20 pF 135 -40C 90 25C 90 40 PHASE 20 V = 2.5V, C = 100 pF, S L 45 RL = 10 k: GAIN (dB) GAIN (dB) RL = 2 k: PHASE () VS = 5V, CL = 20 pF, 60 40 PHASE 20 45 85C 0 0 VS = 2.5V, 3.3V, 5V -20 -40 RL = 2 k:, 10 k: 1k 10k 100k 1M 10M -90 100M -40 1k 10k 100k Figure 28. THD+N vs. Frequency -90 100M THD+N vs. Output Voltage 1 RL = 100 k: RL = 100 k: CL = 10 pF CL = 10 pF f = 1 kHz VO = VS -1V 0.1 VS = 2.5V THD+N (%) THD+N (%) 10M Figure 29. 1 0.01 1M -45 FREQUENCY (Hz) FREQUENCY (Hz) 0.1 0 125C -20 -45 CL = 20 pF, 50 pF, 100 pF -90 100M 100 225 80 -45 PHASE () 100 0 135 90 40 -60 -100 VS = 5V, TA = -40C PHASE () 85C 40 VS = 3.3V 0.001 0.01 VS = 2.5V 0.001 VS = 3.3V VS = 5V VS = 5V 0.0001 10 100 1k 10k 100k 0.0001 FREQUENCY (Hz) 1 10 VOUT (VPP) Figure 30. 12 0.1 Figure 31. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Small Signal Step Response 20 mV/DIV 500 mV/DIV Large Signal Step Response VS = 5V VIN = 2 VPP f = 10 kHz VS = 5V VIN = 100 mVPP f = 10 kHz AV = +1 AV = +1 RL = 10 k: RL = 10 k: CL = 10 pF CL = 10 pF Figure 32. Figure 33. Large Signal Step Response Small Signal Step Response 200 mV/DIV 10 Ps/DIV 1 V/DIV 10 Ps/DIV VS = 5V VIN = 400 mVPP f = 10 kHz VS = 5V VIN = 100 mVPP f = 10 kHz AV = +10 AV = +10 RL = 10 k: RL = 10 k: CL = 10 pF CL = 10 pF 10 Ps/DIV 10 Ps/DIV Figure 34. Figure 35. Supply Current vs. Supply Voltage Output Swing High vs. Supply Voltage 7 40 6 35 125C VOUT FROM RAIL (mV) SUPPLY CURRENT (mA) RL = 2 k: 5 25C 4 -40C 3 2 30 85C 20 -40C 15 25C 10 1 0 1.5 125C 25 5 2 2.5 3 3.5 4 4.5 5 5.5 0 1.5 2 2.5 3 3.5 4 4.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 36. Figure 37. 5 5.5 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 13 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise noted: TA = 25C, RL > 10 k, VCM = VS/2. Output Swing Low vs. Supply Voltage Sinking Current vs, Supply Voltage 60 40 -40C RL = 2 k: 25C 50 125C 30 25 ISINK (mA) VOUT FROM RAIL (mV) 35 85C 20 15 85C 40 125C 30 -40C 25C 10 20 5 0 1.5 2 2.5 3 3.5 4 4.5 5 10 1.5 5.5 2 2.5 3 3.5 4 4.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 38. Figure 39. 5 5.5 Sourcing Current vs. Supply Voltage 60 -40C ISOURCE (mA) 50 25C 40 125C 30 85C 20 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 40. 14 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 APPLICATION NOTES LMP7732 The LMP7732 is a dual low noise, rail-to-rail input and output, low voltage amplifier. The low input voltage noise of only 2.9 nV/Hz with a 1/f corner at 3 Hz makes the LMP7732 ideal for sensor applications where DC accuracy is of importance. The LMP7732 has high gain bandwidth of 22 MHz. This wide bandwidth enables the use of the amplifier at higher gain settings while retaining ample usable bandwidth for the application. This is particularly beneficial when system designers need to use sensors with very limited output voltage range as it allows larger gains in one stage which in turn increases signal to noise ratio. The LMP7732 has a proprietary input bias cancellation circuitry on the input stages. This allows the LMP7732 to have only about 1.5 nA bias current with a bipolar input stage. This low input bias current, paired with the inherent lower input voltage noise of bipolar input stages makes the LMP7732 an excellent choice for precision applications. The combination of low input bias current, low input offset voltage, and low input voltage noise enables the user to achieve unprecedented accuracy and higher signal integrity. Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical support and extensive characterization data is available for sensitive applications or applications with a constrained error budget. The LMP7732 comes in the 8-Pin SOIC and VSSOP packages. These small packages are ideal solutions for area constrained PC boards and portable electronics. INPUT BIAS CURRENT CANCELLATION The LMP7732 has proprietary input bias current cancellation circuitry on its input stage. The LMP7732 has rail-to-rail input. This is achieved by having a p-input and n-input stage in parallel. Figure 41 only shows one of the input stages as the circuitry is symmetrical for both stages. Figure 41 shows that as the common mode voltage gets closer to one of the extreme ends, current I1 significantly increases. This increased current shows as an increase in voltage drop across resistor R1 equal to I1*R1 on IN+ of the amplifier. This voltage contributes to the offset voltage of the amplifier. When common mode voltage is in the mid-range, the transistors are operating in the linear region and I1 is significantly small. The voltage drop due to I1 across R1 can be ignored as it is orders of magnitude smaller than the amplifier's input offset voltage. As the common mode voltage gets closer to one of the rails, the offset voltage generated due to I1 increases and becomes comparable to the amplifiers offset voltage. IBIAS CANCELLATION CIRCUIT V + INPUT STAGE + V R R C1 C2 R1 IN + I1 Q1 Q2 R2 IN - Figure 41. Input Bias Current Cancellation Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 15 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com INPUT VOLTAGE NOISE MEASUREMENT The LMP7732 has very low input voltage noise. The peak-to-peak input voltage noise of the LMP7732 can be measured using the test circuit shown in Figure 42. 0.1 PF 100 k: - 1/2 LMP7732 10: + VOLTAGE GAIN = 50,000 2 k: 4.7 PF + 1/2 LMP7732 - 100 k: 4.3 k: 22 PF 2.2 PF 110 k: SCOPE x1 RIN = 1M 24.3 k: 0.1 PF Figure 42. 0.1 Hz to 10 Hz Noise Test Circuit The frequency response of this noise test circuit at the 0.1 Hz corner is defined by only one zero. The test time for the 0.1 Hz to 10 Hz noise measurement using this configuration should not exceed 10 seconds, as this time limit acts as an additional zero to reduce or eliminate the contributions of noise from frequencies below 0.1 Hz. Figure 43 shows typical peak-to-peak noise for the LMP7732 measured with the circuit in Figure 42. Figure 43. 0.1 Hz to 10 Hz Input Voltage Noise Measuring the very low peak-to-peak noise performance of the LMP7732, requires special testing attention. In order to achieve accurate results, the device should be warmed up for at least five minutes. This is so that the input offset voltage of the op amp settles to a value. During this warm up period, the offset can typically change by a few V because the chip temperature increases by about 30C. If the 10 seconds of the measurement is selected to include this warm up time, some of this temperature change might show up as the measured noise. Figure 44 shows the start-up drift of five typical LMP7732 units. 16 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 OFFSET VOLTAGE DRIFT (PV) 5.0 4.0 3.0 2.0 VS = 5V 1.0 RL = 2 k: 5 TYPICAL UNITS 0.0 0 50 100 150 200 250 300 TIME (s) Figure 44. Start-Up Input Offset Voltage Drift During the peak-to-peak noise measurement, the LMP7732 must be shielded. This prevents offset variations due to airflow. Offset can vary by a few nV due to this airflow and that can invalidate measurements of input voltage noise with a magnitude which is in the same range. For similar reasons, sudden motions must also be restricted in the vicinity of the test area. The feed-through which results from this motion could increase the observed noise value which in turn would invalidate the measurement. DIODES BETWEEN THE INPUTS The LMP7732 has a set of anti-parallel diodes between their input pins, as shown in Figure 45. These diodes are present to protect the input stage of the amplifiers. At the same time, they limit the amount of differential input voltage that is allowed on the input pins. A differential signal larger than the voltage needed to turn on the diodes might cause damage to the diodes. The differential voltage between the input pins should be limited to 3 diode drops or the input current needs to be limited to 20 mA. V ESD IN + + V R1 ESD R2 + IN - ESD ESD - - V V Figure 45. Anti-Parallel Diodes between Inputs DRIVING AN ADC Analog to Digital Converters, ADCs, usually have a sampling capacitor on their input. When the ADC's input is directly connected to the output of the amplifier a charging current flows from the amplifier to the ADC. This charging current causes a momentary glitch that can take some time to settle. There are different ways to minimize this effect. One way is to slow down the sampling rate. This method gives the amplifier sufficient time to stabilize its output. Another way to minimize the glitch, caused by the switch capacitor, is to have an external capacitor connected to the input of the ADC. This capacitor is chosen so that its value is much larger than the internal switching capacitor and it will hence provide the charge needed to quickly and smoothly charge the ADC's sampling capacitor. Since this large capacitor will be loading the output of the amplifier as well, an isolation resistor is needed between the output of the amplifier and this capacitor. The isolation resistor, RISO, separates the additional load capacitance from the output of the amplifier and will also form a low-pass filter and can be designed to provide noise reduction as well as anti-aliasing. The draw back of having RISO is that it reduces signal swing since there is some voltage drop across it. Figure 46 (a) shows the ADC directly connected to the amplifier. To minimize the glitch in this setting, a slower sample rate needs to be used. Figure 46 (b) shows RISO and an external capacitor used to minimize the glitch. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 17 LMP7732 SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 www.ti.com FEEDBACK NETWORK (a) ADC V+ SENSOR INPUT NETWORK V- (b) FEEDBACK NETWORK V+ ADC RISO SENSOR INPUT NETWORK V- C Figure 46. Driving An ADC 18 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 LMP7732 www.ti.com SNOSAZ0E - AUGUST 2007 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMP7732 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMP7732MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP77 32MA LMP7732MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP77 32MA LMP7732MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM AZ3A LMP7732MME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM AZ3A LMP7732MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM AZ3A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMP7732MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMP7732MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP7732MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMP7732MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP7732MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMP7732MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMP7732MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMP7732MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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