0.1 1 10 1k 10k
FREQUENCY (Hz)
1
10
100
100
VOLTAGE NOISE (nV/
Hz)
VS = 2.5V, 3.3V, 5V
VCM = 0.5V
VCM = 2.5V
0.1 1 10 1k 10k
FREQUENCY (Hz)
1
10
100
100
CURRENT NOISE (pA/
Hz)
VS = 2.5V, 3.3V, 5V
VCM = 0.5V
VCM = 2.5V
LMP7732
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SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
2.9 nV/sqrt(Hz) Low Noise, RRIO Amplifier
Check for Samples: LMP7732
1FEATURES DESCRIPTION
The LMP7732 is a dual low noise, rail-to-rail input
23• (Typical Values, TA= 25°C, VS= 5V) and output, low voltage amplifier. The LMP7732 is
• Input Voltage Noise part of the LMP™ amplifier family and is ideal for
– f = 3 Hz 3.3 nV/√Hz precision and low noise applications with low voltage
requirements.
– f = 1 kHz 2.9 nV/√Hz
• CMRR 130 dB This operational amplifier offers low voltage noise of
2.9 nV/√Hz with a 1/f corner of only 3 Hz. The
• Open Loop Gain 130 dB LMP7732 has bipolar junction input stages with a
• GBW 22 MHz bias current of only 1.5 nA. This low input bias
• Slew Rate 2.4 V/µs current, complemented by the very low level of
voltage noise, makes the LMP7732 an excellent
• THD 0.001% @ f = 10 kHz, AV = 1, RL = 2 kΩchoice for photometry applications.
• Supply Current 4.4 mA The LMP7732 provides a wide GBW of 22 MHz while
• Supply Voltage Range 1.8V to 5.5V consuming only 4 mA of current. This high gain
• Operating Temperature Range −40°C to 125°C bandwidth along with the high open loop gain of 130
• Input Bias Current ±1.5 nA dB enables accurate signal conditioning in
applications with high closed loop gain requirements.
• RRIO The LMP7732 has a supply voltage range of 1.8V to
APPLICATIONS 5.5V, making it an ideal choice for battery operated
portable applications.
• Gas Analysis Instruments The LMP7732 is offered in the 8-Pin SOIC and
• Photometric Instrumentation VSSOP packages.
• Medical Instrumentation The LMP7731 is the single version of this product
and is offered in the 5-Pin SOT-23 and 8-Pin SOIC
packages.
Typical Performance Characteristics
Input Voltage Noise vs. Frequency Input Current Noise vs. Frequency
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2LMP is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMP7732
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
For inputs pins only 2000V
Human Body Model For all other pins 2000V
ESD Tolerance(3) Machine Model 200V
Charge Device Model 1000V
VIN Differential ±2V
Supply Voltage (VS= V+– V−) 6.0V
Storage Temperature Range −65°C to 150°C
Junction Temperature(4) +150°C max
Infrared or Convection (20 sec) 235°C
Soldering Information Wave Soldering Lead Temp. (10 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
Operating Ratings(1)
Temperature Range −40°C to 125°C
Supply Voltage (VS= V+– V–) 1.8V to 5.5V
8-Pin SOIC 190 °C/W
Package Thermal Resistance (θJA)8-Pin VSSOP 235°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
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2.5V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 2.5V, V−= 0V, VCM = V+/2, RL>10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
±500
VCM = 2.0V ±9 ±600
VOS Input Offset Voltage(4) μV
±500
VCM = 0.5V ±9 ±600
VCM = 2.0V ±0.5 ±5.5
TCVOS Input Offset Voltage Temperature Drift μV/°C
VCM = 0.5V ±0.2 ±5.5
±30
VCM = 2.0V ±1 ±45
IBInput Bias Current nA
±50
VCM = 0.5V ±12 ±75
±50
VCM = 2.0V ±1 ±75
IOS Input Offset Current nA
±60
VCM = 0.5V ±11 ±80
TCIOS Input Offset Current Drift VCM = 0.5V and VCM = 2.0V 0.0474 nA/°C
0.15V ≤VCM ≤0.7V 101 120
0.23V ≤VCM ≤0.7V 89
CMRR Common Mode Rejection Ratio dB
1.5V ≤VCM ≤2.35V 105 129
1.5V ≤VCM ≤2.27V 99
105 113
2.5V ≤V+≤5V 101
PSRR Power Supply Rejection Ratio dB
1.8V ≤V+≤5.5V 111
CMVR Common Mode Voltage Range Large Signal CMRR ≥80 dB 0 2.5 V
RL= 10 kΩto V+/2 112 130
VOUT = 0.5V to 2.0V 104
AVOL Open Loop Voltage Gain dB
RL= 2 kΩto V+/2 109 119
VOUT = 0.5V to 2.0V 90
50
RL= 10 kΩto V+/2 4 75
Output Voltage Swing High 50
RL= 2 kΩto V+/2 13 75 mV from
VOUT either rail
50
RL= 10 kΩto V+/2 6 75
Output Voltage Swing Low 50
RL= 2 kΩto V+/2 9 75
Sourcing, VOUT = V+/2 22 31
VIN (diff) = 100 mV 12
IOUT Output Current mA
Sinking, VOUT = V+/2 15 44
VIN (diff) = −100 mV 10
5.4
VCM = 2.0V 4.0 6.8
ISSupply Current mA
6.2
VCM = 0.5V 4.6 7.8
AV= +1, CL= 10 pF, RL= 10 kΩto V+/2
SR Slew Rate 2.4 V/μs
VOUT = 2 VPP
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA. Absolute maximum Ratings indicate junction temperature limits beyond
which the device maybe permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Ambient production test is performed at 25°C with a variance of ±3°C.
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2.5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 2.5V, V−= 0V, VCM = V+/2, RL>10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
GBW Gain Bandwidth CL= 20 pF, RL= 10 kΩto V+/2 21 MHz
GMGain Margin CL= 20 pF, RL= 10 kΩto V+/2 14 dB
ΦMPhase Margin CL= 20 pF, RL= 10 kΩto V+/2 60 deg
Differential Mode 38 kΩ
RIN Input Resistance Common Mode 151 MΩ
THD+N Total Harmonic Distortion + Noise AV= 1, fO= 1 kHz, Amplitude = 1V 0.002 %
f = 1 kHz, VCM = 2.0V 3.0
Input Referred Voltage Noise Density nV/√Hz
enf = 1 kHz, VCM = 0.5V 3.0
Input Voltage Noise 0.1 Hz to 10 Hz 75 nVPP
f = 1 kHz, VCM = 2.0V 1.1
inInput Referred Current Noise Density pA/√Hz
f = 1 kHz, VCM = 0.5V 2.3
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3.3V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3.3V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
±500
VCM = 2.5V ±6 ±600
VOS Input Offset Voltage(4) μV
±500
VCM = 0.5V ±6 ±600
VCM = 2.5V ±0.5 ±5.5
Input Offset Voltage Temperature
TCVOS μV/°C
Drift VCM = 0.5V ±0.2 ±5.5
±30
VCM = 2.5V ±1.5 ±45
IBInput Bias Current nA
±50
VCM = 0.5V ±13 ±77
±50
VCM = 2.5V ±1 ±70
IOS Input Offset Current nA
±60
VCM = 0.5V ±11 ±80
TCIOS Input Offset Current Drift VCM = 0.5V and VCM = 2.5V 0.048 nA/°C
0.15V ≤VCM ≤0.7V 101 120
0.23V ≤VCM ≤0.7V 89
CMRR Common Mode Rejection Ratio dB
1.5V ≤VCM ≤3.15V 105 130
1.5V ≤VCM ≤3.07V 99
2.5V ≤V+≤5.0V 105 113
101
PSRR Power Supply Rejection Ratio dB
1.8V ≤V+≤5.5V 111
CMVR Common Mode Voltage Range Large Signal CMRR ≥80 dB 0 3.3 V
RL= 10 kΩto V+/2 112 130
VOUT = 0.5V to 2.8V 104
AVOL Open Loop Voltage Gain dB
RL= 2 kΩto V+/2 110 119
VOUT = 0.5V to 2.8V 92
50
RL= 10 kΩto V+/2 5 75
Output Voltage Swing High 50
RL= 2 kΩto V+/2 14 75 mV from
VOUT either rail
50
RL= 10 kΩto V+/2 9 75
Output Voltage Swing Low 50
RL= 2 kΩto V+/2 13 75
Sourcing, VOUT = V+/2 28 45
VIN (diff) = 100 mV 22
IOUT Output Current mA
Sinking, VOUT = V+/2 25 48
VIN (diff) = −100 mV 20
5.6
VCM = 2.5V 4.2 mA
7.0
ISSupply Current 6.4
VCM = 0.5V 4.8 8.0
AV= +1, CL= 10 pF, RL= 10 kΩto
SR Slew Rate V+/2 2.4 V/μs
VOUT = 2 VPP
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA. Absolute maximum Ratings indicate junction temperature limits beyond
which the device maybe permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Ambient production test is performed at 25°C with a variance of ±3°C.
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3.3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3.3V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
GBW Gain Bandwidth CL= 20 pF, RL= 10 kΩto V+/2 22 MHz
GMGain Margin CL= 20 pF, RL= 10 kΩto V+/2 14 dB
ΦMPhase Margin CL= 20 pF, RL= 10 kΩto V+/2 62 deg
THD+N Total Harmonic Distortion + Noise AV= 1, fO= 1 kHz, Amplitude = 1V 0.002 %
Differential Mode 38 kΩ
RIN Input Resistance Common Mode 151 MΩ
f = 1 kHz, VCM = 2.5V 2.9 nV/√Hz
Input Referred Voltage Noise
Density
enf = 1 kHz, VCM = 0.5V 2.9
Input Voltage Noise 0.1 Hz to 10 Hz 75 nVPP
f = 1 kHz, VCM = 2.5V 1.1 pA/√Hz
Input Referred Current Noise
inDensity f = 1 kHz, VCM = 0.5V 2.1
5V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
±500
VCM = 4.5V ±6 ±600
VOS Input Offset Voltage(4) μV
±500
VCM = 0.5V ±6 ±600
VCM = 4.5V ±0.5 ±5.5
TCVOS Input Offset Voltage Temperature Drift μV/°C
VCM = 0.5V ±0.2 ±5.5
±30
VCM = 4.5V ±1.5 ±50
IBInput Bias Current nA
±50
VCM = 0.5V ±14 ±85
±50
VCM = 4.5V ±1 ±70
IOS Input Offset Current nA
±65
VCM = 0.5V ±11 ±80
TCIOS Input Offset Current Drift VCM = 0.5V and VCM = 4.5V 0.0482 nA/°C
0.15V ≤VCM ≤0.7V 101 120
0.23V ≤VCM ≤0.7V 89
CMRR Common Mode Rejection Ratio dB
1.5V ≤VCM ≤4.85V 105 130
1.5V ≤VCM ≤4.77V 99
2.5V ≤V+≤5V 105 113
101
PSRR Power Supply Rejection Ratio dB
1.8V ≤V+≤5.5V 111
CMVR Common Mode Voltage Range Large Signal CMRR ≥80 dB 0 5 V
RL= 10 kΩto V+/2 112 130
VOUT = 0.5V to 4.5V 104
AVOL Open Loop Voltage Gain dB
RL= 2 kΩto V+/2 110 119
VOUT = 0.5V to 4.5V 94
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA. Absolute maximum Ratings indicate junction temperature limits beyond
which the device maybe permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Ambient production test is performed at 25°C with a variance of ±3°C.
6Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
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OUT B
1
2
3
45
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-
+
-
+
A
B
LMP7732
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5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
50
RL= 10 kΩto V+/2 8 75
Output Voltage Swing High 50
RL= 2 kΩto V+/2 24 75 mV from
VOUT either rail
50
RL= 10 kΩto V+/2 9 75
Output Voltage Swing Low 50
RL= 2 kΩto V+/2 23 75
Sourcing, VOUT = V+/2 33 47
VIN (diff) = 100 mV 27
IOUT Output Current mA
Sinking, VOUT = V+/2 30 49
VIN (diff) = −100 mV 25
6.0
VCM = 4.5V 4.4 7.4
ISSupply Current mA
6.8
VCM = 0.5V 5.0 8.4
AV= +1, CL= 10 pF, RL= 10 kΩto V+/2
SR Slew Rate 2.4 V/μs
VOUT = 2 VPP
GBW Gain Bandwidth CL= 20 pF, RL= 10 kΩto V+/2 22 MHz
GMGain Margin CL= 20 pF, RL= 10 kΩto V+/2 12 dB
ΦMPhase Margin CL= 20 pF, RL= 10 kΩto V+/2 65 deg
Differential Mode 38 kΩ
RIN Input Resistance Common Mode 151 MΩ
THD+ N Total Harmonic Distortion + Noise AV= 1, fO= 1 kHz, Amplitude = 1V 0.001 %
f = 1 kHz, VCM = 4.5V 2.9
Input Referred Voltage Noise Density nV/√Hz
enf = 1 kHz, VCM = 0.5V 2.9
Input Voltage Noise 0.1 Hz to 10 Hz 75 nVPP
f = 1 kHz, VCM = 4.5V 1.1
inInput Referred Current Noise Density pA/√Hz
f = 1 kHz, VCM = 0.5V 2.2
Connection Diagram
8-Pin SOIC/VSSOP
Figure 1. Top View
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-40 -30 -20 -10 0 10 20 30 40
0
9
PERCENTAGE (%)
VOS (PV)
1
2
3
4
5
6
7
8VS = 2.5V, 5V
VCM = VS - 0.5V
-0.5 0 0.5 1 1.5
0
2
4
6
8
10
12
14
PERCENTAGE (%)
TCVOS (PV/°C)
VS = 2.5V
VCM = 2V
-40 -30 -20 -10 0 10 20 30 40
0
10
PERCENTAGE (%)
VOS (PV)
1
2
3
4
5
6
7
8
9VS = 5V
VCM = 0.5V
-0.5 0 0.5 1 1.5
0
5
10
15
20
25
PERCENTAGE (%)
TCVOS (PV/°C)
VS = 3.3V, 5V
VCM = 0.5V
-40 -30 -20 -10 0 10 20 30 40
0
10
PERCENTAGE (%)
VOS (PV)
1
2
3
4
5
6
7
8
9VS = 2.5V, 3.3V
VCM = 0.5V
-0.5 0 0.5 1 1.5
0
5
10
15
20
25
PERCENTAGE (%)
TCVOS (PV/°C)
VS = 2.5V
VCM = 0.5V
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Typical Performance Characteristics
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Offset Voltage Distribution TCVOS Distribution
Figure 2. Figure 3.
Offset Voltage Distribution TCVOS Distribution
Figure 4. Figure 5.
Offset Voltage Distribution TCVOS Distribution
Figure 6. Figure 7.
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0
10 1k 100k 10M
FREQUENCY (Hz)
-140
-100
-60
PSRR (dB)
1M10k
100
-20
-40
-80
-120
-PSRR
+PSRR
VS = 2.5V
VS = 3.3V VS = 5V & 3.3V
160
100 10k 10M
FREQUENCY (Hz)
0
60
CMRR (dB)
1M
100k
1k
120
100
40
20
80
140 VS = 2.5V, 3.3V, 5V
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
-100
-75
-50
-25
0
25
50
75
100
VOS (PV)
VS = 2.5V, 3.3V, 5V
VCM = 2V, 2.5V, 4.5V
5 TYPICAL PARTS
-40 -20 0 20 40 60 80 100 120
-30
-20
-10
0
10
20
30
40
TEMPERATURE (°C)
VOS (PV)
VS = 2.5V, 3.3V, 5V
VCM = 0.5V
5 TYPICAL PARTS
-40 -30 -20 -10 0 10 20 30 40
VOS (PV)
0
1
2
3
4
5
6
7
8
PERCENTAGE (%)
VS = 3.3V
VCM = 2.5V
-0.5 0 0.5 1 1.5
0
2
4
6
8
10
12
14
PERCENTAGE (%)
TCVOS (PV/°C)
VS = 3.3V, 5V
VCM = 2.5V, 4.5V
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Offset Voltage Distribution TCVOS Distribution
Figure 8. Figure 9.
Offset Voltage vs. Temperature Offset Voltage vs. Temperature
Figure 10. Figure 11.
PSRR vs. Frequency CMRR vs. Frequency
Figure 12. Figure 13.
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050 100 150 200 250 300
TIME (s)
0.0
1.0
2.0
3.0
4.0
5.0
OFFSET VOLTAGE DRIFT (PV)
VS = 5V
RL = 2 k:
5 TYPICAL UNITS
1.5 2 2.5 3 3.5 4 4.5 5 5.5
2
3.4
SLEW RATE (V/Ps)
SUPPLY VOLTAGE (V)
2.2
2.4
2.6
2.8
3
3.2 RISING EDGE
FALLING EDGE
AV = +1
VIN = 1 VPP
RL = 10 k:
CL = 10 pF
0 0.5 1 1.5 2 2.5 3 3.3
-75
-50
-25
0
25
50
100
VOS (PV)
VCM (V)
75
125°C
85°C
25°C
-40°C
VS = 3.3V
0 1 2 3 4 5
-75
-50
-25
0
25
50
75
100
VOS (PV)
VCM (V)
125°C
85°C
25°C
-40°C
VS = 5V
0 0.5 1 1.5 2 2.5
-75
-50
-25
0
25
50
75
100
VOS (PV)
VCM (V)
125°C
85°C
25°C
-40°C
VS = 2.5V
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
-25
-20
-15
-10
-5
0
5
OFFSET VOLTAGE (PV)
25°C
-40°C
125°C
85°C
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Offset Voltage vs. Supply Voltage Offset Voltage vs. VCM
Figure 14. Figure 15.
Offset Voltage vs. VCM Offset Voltage vs. VCM
Figure 16. Figure 17.
Input Offset Voltage Time Drift Slew Rate vs. Supply Voltage
Figure 18. Figure 19.
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0 0.5 1 1.5 2 2.5
-100
-80
-60
-40
-20
0
20
40
60
80
100
INPUT BIAS CURRENT (nA)
VCM (V)
VS = 2.5V
85°C
125°C
25°C
-40°C
0 0.5 1 1.5 2 2.5 3 3.5
-100
-80
-60
-40
-20
0
20
40
60
80
100
INPUT BIAS CURRENT (nA)
VCM (V)
125°C
85°C
25°C
VS = 3.3V
-40°C
0 5 10 15 20 25 30
-800
-600
-400
-200
0
200
400
600
800
1000
VOUT FROM RAIL (mV)
OUTPUT CURRENT (mA)
SOURCE
SINK
VS = 2.5V
VS = 2.5V, 3.3V, 5V
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Time Domain Voltage Noise Time Domain Voltage Noise
Figure 20. Figure 21.
Time Domain Voltage Noise Output Voltage vs. Output Current
Figure 22. Figure 23.
Input Bias Current vs. VCM Input Bias Current vs. VCM
Figure 24. Figure 25.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMP7732
VOUT (VPP)
0.1 1 10
0.0001
0.001
0.01
0.1
1
THD+N (%)
VS = 2.5V
VS = 3.3V
VS = 5V
RL = 100 k:
CL = 10 pF
f = 1 kHz
10 100 1k 10k 100k
FREQUENCY (Hz)
0.0001
0.001
0.01
0.1
1
THD+N (%)
VS = 5V
VS = 3.3V
VS = 2.5V
RL = 100 k:
CL = 10 pF
VO = VS -1V
1k 100k 100M
FREQUENCY (Hz)
-40
0
40
100
GAIN (dB)
10M
1M
10k
80
20
-20
60
-90
0
90
225
180
45
-45
135
PHASE (°)
GAIN
PHASE
VS = 2.5V, CL = 100 pF,
RL = 10 k:
VS = 5V, CL = 20 pF,
RL = 2 k:
VS = 2.5V, 3.3V, 5V
CL = 20 pF, 50 pF, 100 pF
RL = 2 k:, 10 k:
1k 100k 100M
-40
0
40
100
GAIN (dB)
10M
1M
10k
80
20
-20
60
FREQUENCY (Hz)
VS = 5V
RL = 10 k:
CL = 20 pF
GAIN
PHASE
-90
0
90
225
180
45
-45
135
PHASE (°)
-40°C
25°C
85°C
125°C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-100
-80
-60
-40
-20
0
20
40
60
80
100
INPUT BIAS CURRENT (nA)
VCM (V)
VS = 5V
25°C
85°C
125°C
-40°C
1k 100k 100M
FREQUENCY (Hz)
-40
0
40
100
GAIN (dB)
10M
1M
10k
80
20
-20
60
-90
0
90
225
180
45
-45
135
PHASE (°)
GAIN
PHASE
VS = 2.5V, TA = 25°C
VS = 5V, TA = -40°C
VS = 2.5V, 3.3V, 5V
RL = 10 k:
TA = -40°C, 25°C, 85°C, 125°C
LMP7732
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Input Bias Current vs. VCM Open Loop Frequency Response Over Temperature
Figure 26. Figure 27.
Open Loop Frequency Response Open Loop Frequency Response
Figure 28. Figure 29.
THD+N vs. Frequency THD+N vs. Output Voltage
Figure 30. Figure 31.
12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7732
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
0
5
10
15
20
25
30
35
40
VOUT FROM RAIL (mV)
125°C
85°C
25°C
-40°C
RL = 2 k:
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
0
1
2
3
4
5
6
7
SUPPLY CURRENT (mA)
-40°C
25°C
125°C
1 V/DIV
10 Ps/DIV
VS = 5V
VIN = 400 mVPP
f = 10 kHz
AV = +10
RL = 10 k:
CL = 10 pF
200 mV/DIV
10 Ps/DIV
VS = 5V
VIN = 100 mVPP
f = 10 kHz
AV = +10
RL = 10 k:
CL = 10 pF
20 mV/DIV
10 Ps/DIV
VS = 5V
VIN = 100 mVPP
f = 10 kHz
AV = +1
RL = 10 k:
CL = 10 pF
500 mV/DIV
10 Ps/DIV
VS = 5V
VIN = 2 VPP
f = 10 kHz
AV = +1
RL = 10 k:
CL = 10 pF
LMP7732
www.ti.com
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Large Signal Step Response Small Signal Step Response
Figure 32. Figure 33.
Large Signal Step Response Small Signal Step Response
Figure 34. Figure 35.
Supply Current vs. Supply Voltage Output Swing High vs. Supply Voltage
Figure 36. Figure 37.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMP7732
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
10
20
30
40
50
60
ISOURCE (mA)
25°C
85°C
125°C
-40°C
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
0
5
10
15
20
25
30
35
40
VOUT FROM RAIL (mV)
125°C
85°C
25°C -40°C
RL = 2 k:
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
10
20
30
40
50
60
ISINK (mA)
25°C
85°C 125°C
-40°C
LMP7732
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Output Swing Low vs. Supply Voltage Sinking Current vs, Supply Voltage
Figure 38. Figure 39.
Sourcing Current vs. Supply Voltage
Figure 40.
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7732
V+
R1
R2
IN+
IN-
I1
INPUT STAGE
IBIAS CANCELLATION CIRCUIT
Q1 Q2
V+
RC1RC2
LMP7732
www.ti.com
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
APPLICATION NOTES
LMP7732
The LMP7732 is a dual low noise, rail-to-rail input and output, low voltage amplifier.
The low input voltage noise of only 2.9 nV/√Hz with a 1/f corner at 3 Hz makes the LMP7732 ideal for sensor
applications where DC accuracy is of importance.
The LMP7732 has high gain bandwidth of 22 MHz. This wide bandwidth enables the use of the amplifier at
higher gain settings while retaining ample usable bandwidth for the application. This is particularly beneficial
when system designers need to use sensors with very limited output voltage range as it allows larger gains in
one stage which in turn increases signal to noise ratio.
The LMP7732 has a proprietary input bias cancellation circuitry on the input stages. This allows the LMP7732 to
have only about 1.5 nA bias current with a bipolar input stage. This low input bias current, paired with the
inherent lower input voltage noise of bipolar input stages makes the LMP7732 an excellent choice for precision
applications. The combination of low input bias current, low input offset voltage, and low input voltage noise
enables the user to achieve unprecedented accuracy and higher signal integrity.
Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical
support and extensive characterization data is available for sensitive applications or applications with a
constrained error budget.
The LMP7732 comes in the 8-Pin SOIC and VSSOP packages. These small packages are ideal solutions for
area constrained PC boards and portable electronics.
INPUT BIAS CURRENT CANCELLATION
The LMP7732 has proprietary input bias current cancellation circuitry on its input stage.
The LMP7732 has rail-to-rail input. This is achieved by having a p-input and n-input stage in parallel. Figure 41
only shows one of the input stages as the circuitry is symmetrical for both stages.
Figure 41 shows that as the common mode voltage gets closer to one of the extreme ends, current I1
significantly increases. This increased current shows as an increase in voltage drop across resistor R1equal to
I1*R1on IN+ of the amplifier. This voltage contributes to the offset voltage of the amplifier. When common mode
voltage is in the mid-range, the transistors are operating in the linear region and I1is significantly small. The
voltage drop due to I1across R1can be ignored as it is orders of magnitude smaller than the amplifier's input
offset voltage. As the common mode voltage gets closer to one of the rails, the offset voltage generated due to I1
increases and becomes comparable to the amplifiers offset voltage.
Figure 41. Input Bias Current Cancellation
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMP7732
-
+
½
LMP7732
-
+½
LMP7732
0.1 PF
100 k:
10:
2 k:
4.7 PF
24.3 k:
100 k:
0.1 PF
4.3 k:
2.2 PF
22 PF
110 k:
SCOPE
x 1
RIN = 1M
VOLTAGE GAIN = 50,000
LMP7732
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
www.ti.com
INPUT VOLTAGE NOISE MEASUREMENT
The LMP7732 has very low input voltage noise. The peak-to-peak input voltage noise of the LMP7732 can be
measured using the test circuit shown in Figure 42.
Figure 42. 0.1 Hz to 10 Hz Noise Test Circuit
The frequency response of this noise test circuit at the 0.1 Hz corner is defined by only one zero. The test time
for the 0.1 Hz to 10 Hz noise measurement using this configuration should not exceed 10 seconds, as this time
limit acts as an additional zero to reduce or eliminate the contributions of noise from frequencies below 0.1 Hz.
Figure 43 shows typical peak-to-peak noise for the LMP7732 measured with the circuit in Figure 42.
Figure 43. 0.1 Hz to 10 Hz Input Voltage Noise
Measuring the very low peak-to-peak noise performance of the LMP7732, requires special testing attention. In
order to achieve accurate results, the device should be warmed up for at least five minutes. This is so that the
input offset voltage of the op amp settles to a value. During this warm up period, the offset can typically change
by a few µV because the chip temperature increases by about 30°C. If the 10 seconds of the measurement is
selected to include this warm up time, some of this temperature change might show up as the measured noise.
Figure 44 shows the start-up drift of five typical LMP7732 units.
16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7732
ESD R1
IN+
ESD
R2ESD
IN-
ESD
V+
V-V-
V+
050 100 150 200 250 300
TIME (s)
0.0
1.0
2.0
3.0
4.0
5.0
OFFSET VOLTAGE DRIFT (PV)
VS = 5V
RL = 2 k:
5 TYPICAL UNITS
LMP7732
www.ti.com
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
Figure 44. Start-Up Input Offset Voltage Drift
During the peak-to-peak noise measurement, the LMP7732 must be shielded. This prevents offset variations due
to airflow. Offset can vary by a few nV due to this airflow and that can invalidate measurements of input voltage
noise with a magnitude which is in the same range. For similar reasons, sudden motions must also be restricted
in the vicinity of the test area. The feed-through which results from this motion could increase the observed noise
value which in turn would invalidate the measurement.
DIODES BETWEEN THE INPUTS
The LMP7732 has a set of anti-parallel diodes between their input pins, as shown in Figure 45. These diodes are
present to protect the input stage of the amplifiers. At the same time, they limit the amount of differential input
voltage that is allowed on the input pins. A differential signal larger than the voltage needed to turn on the diodes
might cause damage to the diodes. The differential voltage between the input pins should be limited to ±3 diode
drops or the input current needs to be limited to ±20 mA.
Figure 45. Anti-Parallel Diodes between Inputs
DRIVING AN ADC
Analog to Digital Converters, ADCs, usually have a sampling capacitor on their input. When the ADC's input is
directly connected to the output of the amplifier a charging current flows from the amplifier to the ADC. This
charging current causes a momentary glitch that can take some time to settle. There are different ways to
minimize this effect. One way is to slow down the sampling rate. This method gives the amplifier sufficient time to
stabilize its output. Another way to minimize the glitch, caused by the switch capacitor, is to have an external
capacitor connected to the input of the ADC. This capacitor is chosen so that its value is much larger than the
internal switching capacitor and it will hence provide the charge needed to quickly and smoothly charge the
ADC's sampling capacitor. Since this large capacitor will be loading the output of the amplifier as well, an
isolation resistor is needed between the output of the amplifier and this capacitor. The isolation resistor, RISO,
separates the additional load capacitance from the output of the amplifier and will also form a low-pass filter and
can be designed to provide noise reduction as well as anti-aliasing. The draw back of having RISO is that it
reduces signal swing since there is some voltage drop across it.
Figure 46 (a) shows the ADC directly connected to the amplifier. To minimize the glitch in this setting, a slower
sample rate needs to be used. Figure 46 (b) shows RISO and an external capacitor used to minimize the glitch.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMP7732
LMP7732
www.ti.com
SNOSAZ0E –AUGUST 2007–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMP7732
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMP7732MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP77
32MA
LMP7732MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMP77
32MA
LMP7732MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM AZ3A
LMP7732MME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM AZ3A
LMP7732MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM AZ3A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMP7732MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMP7732MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7732MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMP7732MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMP7732MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMP7732MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMP7732MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0
LMP7732MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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