SI8900EDB-T2-E1 - Vishay [Siliconix]

Vishay Siliconix

Si8900EDB

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

www.vishay.com

Bi-Directional N-Channel 20-V (D-S) MOSFET

FEATURES

• TrenchFET® Power MOSFET

• Ultra-Low RSS(on)

• ESD Protected: 4000 V

• MICRO FOOT® Chipscale Packaging

Reduces Footprint Area Profile (0.62 mm)

and On-Resistance Per Footprint Area

APPLICATIONS

• Battery Protection Circuit

- 1-2 Cell Li+/LiP Battery Pack for Portable Devices

PRODUCT SUMMARY

VS1S2 (V) RS1S2(on) (Ω)I

S1S2 (A)

0.024 at VGS = 4.5 V 7

0.026 at VGS = 3.7 V 6.8

0.034 at VGS = 2.5 V 5.0

0.040 at VGS = 1.8 V 5.5

MICRO FOOT

Device Marking:

8900E = P/N Code

xxx = Date/Lot Traceability Code

Bump Side View

G2G1

S1S1

310

S1S1

Backside View

8900E

xxx

Pin 1 Identifier

Ordering Information:

Si8900EDB-T2-E1 (Lead (Pb)-free)

N-Channel

4 kΩ

Notes:

a. Surface Mounted on 1" x 1" FR4 board.

b. The foot is defined as the top surface of the package.

c. Refer to IPC/JEDEC (J-STD-020C), no manual or hand soldering.

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 5 s Steady State Unit

Source1- Source2 Voltage VS1S2 20 V

Gate-Source Voltage VGS ± 12

Continuous Source1- Source2 Current (TJ = 150 °C)aTA = 25 °C IS1S2

75.4

TA = 85 °C 5.1 3.9

Pulsed Source1- Source2 Current ISM 50

Maximum Power DissipationaTA = 25 °C PD

1.8 1 W

TA = 85 °C 0.9 0.5

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

Package Reflow ConditionscIR/Convection 260

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambientat ≤ 5 s RthJA

55 70

°C/W

Steady State 95 120

Maximum Junction-to-FootbSteady State RthJF 12 15

RoHS

COMPLIANT

www.vishay.com

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

Vishay Siliconix

Si8900EDB

Notes:

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.

b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage VGS(th) VSS = VGS, ID = 1.1 mA 0.45 1.0 V

Gate-Body Leakage IGSS

VSS = 0 V, VGS = ± 4.5 V ± 4 µA

VSS = 0 V, VGS = ± 12 V ± 10 mA

Zero Gate Voltage Drain Current IS1S2

VSS = 20 V, VGS = 0 V 1µA

VSS = 20 V, VGS = 0 V, TJ = 85 °C 5

On-State Drain CurrentaIS(on) V

SS = 5 V, VGS = 4.5 V 5A

Source1- Source2 On State ResistanceaRS1S2(on)

VGS = 4.5 V, ISS = 1 A 0.020 0.024

VGS = 3.7 V, ISS = 1 A 0.022 0.026

VGS = 2.5 V, ISS = 1 A 0.026 0.034

VGS = 1.8 V, ISS = 1 A 0.032 0.040

Forward Transconductanceagfs VSS = 10 V, ISS = 1 A 31 S

Dynamicb

Tur n - O n D e l ay Time td(on)

VSS = 10 V, RL = 10 Ω

ISS ≅ 1 A, VGEN = 4.5 V, Rg = 6 Ω

µs

Rise Time tr4.5 7

Turn-Off Delay Time td(off) 55 85

Fall Time tf15 25

Gate-Current vs. Gate-Source Voltage

0 3 6 9 12 15

VGS

- Gate-to-Source Voltage (V)

- Gate Current (mA)IGSS

IGSS at 25 °C (mA)

Gate Current vs. Gate-Source Voltage

0.01

100

10 000

0.1

1000

VGS

- Gate-to-Source Voltage (V)

- Gate Current (I

GSS

µA)

0369 15

TJ = 25 °C

TJ = 150 °C

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

www.vishay.com

Vishay Siliconix

Si8900EDB

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Output Characteristics

On-Resistance vs. Drain Current

On-Resistance vs. Gate-to-Source Voltage

01234

VGS = 5 thru 1.5 V

VDS

- Drain-to-Source Voltage (V)

- Drain Current (A)ID

1 V

0.00

0.01

0.02

0.03

0.04

0.05

0246810

- On-Resistance (Ω)R

DS(on)

- Drain Current (A)

VGS = 4.5 V

VGS = 2.5 V

VGS = 1.8 V

VGS = 3.7 V

0.00

0.02

0.04

0.06

0.08

0.10

012345

- On-Resistance (Ω)R

DS(on)

VGS

- Gate-to-Source Voltage (V)

IS1S2 = 1 A

IS1S2 = 5 A

Transfer Characteristics

On-Resistance vs. Junction Temperature

Threshold Voltage

0.0 0.2 0.4 0.6 0.8 1.0 1.2

25 °C

TC = 125 °C

- 55 °C

VGS

- Gate-to-Source Voltage (V)

- Drain Current (A)ID

0.6

0.8

1.0

1.2

1.4

1.6

- 50 - 25 0 25 50 75 100 125 150

TJ - Junction Temperature (°C)

VGS = 4.5 V

IS1S2 = 1 A

RDS(on) - On-Resistance

(Normalized)

- 0.4

- 0.3

- 0.2

- 0.1

0.0

0.1

0.2

- 50 - 25 0 25 50 75 100 125 150

Variance (V)VGS(th)

TJ - Temperature (°C)

IS1S2 = 1.1 mA

www.vishay.com

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

Vishay Siliconix

Si8900EDB

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Single Pulse Power, Junction-to-Ambient

Power (W)

Time (s)

1 1000100.10.01

100

Normalized Thermal Transient Impedance, Junction-to-Ambient

10-310-21 10 60010-1

10-4100

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1. Duty Cycle, D =

2. Per Unit Base = RthJA = 95 °C/W

3. T JM - TA = PDMZthJA(t)

Notes:

4. Surface Mounted

PDM

Normalized Thermal Transient Impedance, Junction-to-Foot

10-310-2110-1

10-4

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

Document Number: 71830

S-82119-Rev. G, 08-Sep-08

www.vishay.com

Vishay Siliconix

Si8900EDB

PACKAGE OUTLINE

MICRO FOOT: 10-BUMP (2 x 5, 0.8 mm PITCH)

Notes (Unless Otherwise Specified):

1. Laser mark on the silicon die back, coated with a thin metal.

2. Bumps are 95.5Sn/3.8Ag/0.7Cu.

3. Non-solder mask defined copper landing pad.

Notes:

a. Use millimeters as the primary measurement.

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see http://www.vishay.com/ppg?71830.

Recommended Land

Mark on Backside of Die

10 x ∅ 0.30 ~ 0.31

Note 3

Solder Mask ∅ ~ 0.40

8900E

xxx

b Diamerter

S1e

Bump Note 2

Silicon

Dim. MillimetersaInches

Min. Max. Min. Max.

A 0.600 0.650 0.0236 0.0256

A1 0.260 0.290 0.102 0.0114

A2 0.340 0.360 0.0134 0.0142

b 0.370 0.410 0.0146 0.0161

D 4.050 4.060 0.1594 0.1598

E 1.980 2.000 0.0780 0.0787

e 0.750 0.850 0.0295 0.0335

S10.430 0.450 0.0169 0.0177

S2 0.580 0.600 0.0228 0.0236

AN824

Vishay Siliconix

Document Number: 71990

06-Jan-03

www.vishay.com

PCB Design and Assembly Guidelines

For MICRO FOOTr Products

Johnson Zhao

INTRODUCTION

Vishay Siliconix’s MICRO FOOT product family is based on a

wafer-level chip-scale packaging (WL-CSP) technology that

implements a solder bump process to eliminate the need for an

outer package to encase the silicon die. MICRO FOOT

products include power MOSFETs, analog switches, and

power ICs.

For battery powered compact devices, this new packaging

technology reduces board space requirements, improves

thermal performance, and mitigates the parasitic effect typical

of leaded packaged products. For example, the 6−bump

MICRO FOOT Si8902EDB common drain power MOSFET,

which measures just 1.6 mm x 2.4 mm, achieves the same

performance as TSSOP−8 devices in a footprint that is 80%

smaller and with a 50% lower height profile (Figure 1). A

MICRO FOOT analog switch, the 6−bump DG3000DB, offers

low charge injection and 1.4 W on−resistance in a footprint

measuring just 1.08 mm x 1.58 mm (Figure 2).

Vishay Siliconix MICRO FOOT products can be handled with

the same process techniques used for high-volume assembly

of packaged surface-mount devices. With proper attention to

PCB and stencil design, the device will achieve reliable

performance without underfill. The advantage of the device’s

small footprint and short thermal path make it an ideal option

for space-constrained applications in portable devices such as

battery packs, PDAs, cellular phones, and notebook

computers.

This application note discusses the mechanical design and

reliability of MICRO FOOT, and then provides guidelines for

board layout, the assembly process, and the PCB rework

process.

FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and

Si8900EDB

FIGURE 2. Outline of MICRO FOOT CSP & Analog

Switch DG3000DB

0.18 ~ 0.25

321

0.5

1.58

0.5

0.285

1.08

AN824

Vishay Siliconix

www.vishay.com

Document Number: 71990

06-Jan-03

TABLE 1

Main Parameters of Solder Bumps in MICRO FOOT Designs

ÁÁÁÁÁÁÁÁÁÁ

MICRO FOOT CSP

ÁÁÁÁÁÁ

Bump Material

ÁÁÁÁÁÁÁ

Bump Pitch*

ÁÁÁÁÁÁ

Bump Diameter*

ÁÁÁÁÁÁÁ

Bump Height*

ÁÁÁÁÁÁÁÁÁÁ

MICRO FOOT CSP MOSFET

ÁÁÁÁÁÁ

Eutectic Solder:

ÁÁÁÁÁÁÁ

0.8

ÁÁÁÁÁÁ

0.37-0.41

ÁÁÁÁÁÁÁ

0.26-0.29

ÁÁÁÁÁÁÁÁÁÁ

MICRO FOOT CSP Analog Switch

ÁÁÁÁÁÁ

Eutectic Solder:

63Sm

37Pb

ÁÁÁÁÁÁÁ

0.5

ÁÁÁÁÁÁ

0.18-0.25

ÁÁÁÁÁÁÁ

0.14-0.19

ÁÁÁÁÁÁÁÁÁÁ

MICRO FOOT UCSP Analog Switch

ÁÁÁÁÁÁ

63Sm/37Pb

ÁÁÁÁÁÁÁ

0.5

ÁÁÁÁÁÁ

0.32-0.34

ÁÁÁÁÁÁÁ

0.21-0.24

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

* All measurements in millimeters

MICRO FOOT’S DESIGN AND RELIABILITY

As a mechanical, electrical, and thermal connection between

the device and PCB, the solder bumps of MICRO FOOT

products are mounted on the top active surface of the die.

Table 1 shows the main parameters for solder bumps used in

MICRO FOOT products. A silicon nitride passivation layer is

applied to the active area as the last masking process in

fabrication,ensuring that the device passes the pressure pot

test. A green laser is used to mark the backside of the die

without damaging it. Reliability results for MICRO FOOT

products mounted on a FR-4 board without underfill are shown

in Table 2.

TABLE 2

MICRO FOOT Reliability Results

ÁÁÁÁÁÁÁÁÁ

Test Condition C: −65_ to 150_C

ÁÁÁÁÁÁÁ

>500 Cycles

ÁÁÁÁÁÁÁÁÁ

Test condition B: −40_ to 125_C

ÁÁÁÁÁÁÁ

>1000 Cycles

ÁÁÁÁÁÁÁÁÁ

121_C @ 15PSI 100% Humidity Test

ÁÁÁÁÁÁÁ

96 Hours

The main failure mechanism associated with wafer-level

chip-scale packaging is fatigue of the solder joint. The results

shown in Table 2 demonstrate that a high level of reliability can

be achieved with proper board design and assembly

techniques.

BOARD LAYOUT GUIDELINES

Board materials. Vishay Siliconix MICRO FOOT products are

designed to be reliable on most board types, including organic

boards such as FR-4 or polyamide boards. The package

qualification information is based on the test on 0.5-oz. FR-4

and polyamide boards with NSMD pad design.

Land patterns. Two types of land patterns are used for

surface-mount packages. Solder mask defined (SMD) pads

have a solder mask opening smaller than the metal pad

(Figure 3), whereas on-solder mask defined (NSMD) pads

have a metal pad smaller than the solder-mask opening

(Figure 4).

NSMD is recommended for copper etch processes, since it

provides a higher level of control compared to SMD etch

processes. A small-size NSMD pad definition provides more

area (both lateral and vertical) for soldering and more room for

escape routing on the PCB. By contrast, SMD pad definition

introduces a stress concentration point near the solder mask

on the PCB side that may result in solder joint cracking under

extreme fatigue conditions.

Copper pads should be finished with an organic solderability

preservative (OSP) coating. For electroplated

nickel-immersion gold finish pads, the gold thickness must be

less than 0.5 mm to avoid solder joint embrittlement.

FIGURE 3. SMD FIGURE 4. NSMD

Copper

Solder Mask

Copper

Solder Mask

AN824

Vishay Siliconix

Document Number: 71990

06-Jan-03

www.vishay.com

Board pad design. The landing-pad size for MICRO FOOT

products is determined by the bump pitch as shown in Table 3.

The pad pattern is circular to ensure a symmetric,

barrel-shaped solder bump.

TABLE 3

Dimensions of Copper Pad and Solder Mask

Opening in PCB and Stencil Aperture

ÁÁÁ

Pitch

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Copper Pad

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Solder Mask

Opening

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁ

Stencil

Aperture

ÁÁÁ

0.80 mm

ÁÁÁÁÁ

0.30 " 0.01 mm

ÁÁÁÁÁ

0.41 " 0.01 mm

ÁÁÁÁÁ

0.33 " 0.01 mm

in ciircle aperture

ÁÁÁ

0.50 mm

ÁÁÁÁÁ

0.17 " 0.01 mm

ÁÁÁÁÁ

0.27 " 0.01 mm

ÁÁÁÁÁ

0.30 " 0.01 mm

in square aperture

ASSEMBLY PROCESS

MICRO FOOT products’ surface-mount-assembly operations

include solder paste printing, component placement, and

solder reflow as shown in the process flow chart (Figure 5).

FIGURE 5. SMT Assembly Process Flow

Stencil Design

IIncoming Tape and Reel Inspection

Solder Paste Printing

Chip Placement

Reflow

Solder Joint Inspection

Pack and Ship

Stencil design. Stencil design is the key to ensuring

maximum solder paste deposition without compromising the

assembly yield from solder joint defects (such as bridging and

extraneous solder spheres). The stencil aperture is dependent

on the copper pad size, the solder mask opening, and the

quantity of solder paste.

In MICRO FOOT products, the stencil is 0.125-mm (5-mils)

thick. The recommended apertures are shown in Table 3 and

are fabricated by laser cut.

Solder-paste printing. The solder-paste printing process

involves transferring solder paste through pre-defined

apertures via application of pressure.

In MICRO FOOT products, the solder paste used is UP78

No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.

Chip pick-and-placement. MICRO FOOT products can be

picked and placed with standard pick-and-place equipment.

The recommended pick-and-place force is 150 g. Though the

part will self-center during solder reflow, the maximum

placement offset is 0.02 mm.

Reflow Process. MICRO FOOT products can be assembled

using standard SMT reflow processes. Similar to any other

package, the thermal profile at specific board locations must

be determined. Nitrogen purge is recommended during reflow

operation. Figure 6 shows a typical reflow profile.

100

150

200

250

0 100 200 300 400

Thermal Profile

Time (Seconds

FIGURE 6. Reflow Profile

Temperature (_C)

PCB REWORK

To replace MICRO FOOT products on PCB, the rework

procedure is much like the rework process for a standard BGA

or CSP, as long as the rework process duplicates the original

reflow profile. The key steps are as follows:

1. Remove the MICRO FOOT device using a convection

nozzle to create localized heating similar to the original

reflow profile. Preheat from the bottom.

2. Once the nozzle temperature is +190_C, use tweezers to

remove the part to be replaced.

3. Resurface the pads using a temperature-controlled

soldering iron.

4. Apply gel flux to the pad.

5. Use a vacuum needle pick-up tip to pick up the

replacement part, and use a placement jig to placed it

accurately.

6. Reflow the part using the same convection nozzle, and

preheat from the bottom, matching the original reflow

profile.

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Revision: 02-Oct-12 1Document Number: 91000

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