TLE4473GV55-2 - Infineon Technologies

Type Package Marking

TLE 4473 GV55-2 PG-DSO-12-11 (RoHS compliant) TLE4473 GV55-2

Dual Low Dropout Voltage Regulator

TLE 4473 GV55-2

PG-DSO-12-11

Data Sheet 1 Rev. 1.2, 2008-10-28

Features

• Stand-by output 190 mA; 5 V ± 2%

• Main output: 300 mA, 5 V

tracked to the stand-by output

• Low quiescent current consumption

• Disable function separately for both outputs

• Wide operation range: up to 42 V

• Very low dropout voltage

• 2 independent reset circuits

• Watchdog

• Output protected against short circuit

• Wide temperature range: -40 °C to 150 °C

• Overtemperature protection

• Overload protection

• Green product (RoHS compliant)

• AEC qualified

Functional Description

The TLE 4473 is a monolithic integrated voltage regulator with two low dropout outputs,

a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum

of 190 mA. The stand-by regulator transforms an input voltage VI in the range of 5.6 V ≤

VI ≤ 42 V to an output voltage of VQ2 = 5.0 V (±2%). The main output is tracked to the

stand by output voltage and provides also 5 V. A versions of this device with 5 V/3.3 V

and 5 V/2.6 V are also available, please refer to the data sheet TLE 4473 G V53/

TLE 4473 G V52. The Inhibit input INH1 disables the output Q1 only, whereas Inhibit

input INH2 disables both, Q1 and Q2 output. The quiescent current then is 1 µA.

The TLE 4473 is designed to supply microprocessor systems and sensors under the

severe conditions of automotive applications and therefore is equipped with additional

protection functions against overload, short circuit and overtemperature. The device

operates in the wide junction temperature range of -40 °C to 150 °C.

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Data Sheet 2 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

The device features a reset with adjustable power on delay for each of the outputs. In

addition the output for the microcontroller supply comes up with a watchdog in order to

supervise a connected microcontroller

Reset and Watchdog Behavior

The reset output RO2 is in high-state if the voltage on the delay capacitor CD2 is greater

or equal VDU2. The delay capacitor CD2 is charged with the current IDC2 for output

voltages greater than the reset threshold VRT2. If the output voltage gets lower than VRT2

(‘reset condition’) a fast discharge of the delay capacitor CD2 sets in and as soon as VD2

gets lower than VDL2 the reset output RO2 is set to low-level. The time for the delay

capacitor charge is the reset delay time. For the power-on case the charging process of

CD2 starts from 0 V, which leads to the equation:

(1)

for the power-on reset delay time.

When the voltage on the delay capacitor has reached VDU2 and reset was set to high, the

watchdog circuit is enabled and discharges CD2 with the constant current IDD2.

If there is no rising edge observed at the watchdog input, CD2 will be discharge down to

VDL2. Then reset output RO2 will be set to low and CD2 will be charged again with the

current IDC2 until VD2 reaches VDU2 and reset will be set high again.

If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge

period CD2 is charged again and the reset output stays high. After VD2 has reached VDU2,

the periodical cycle starts again.

The watchdog timing is shown in Figure 1. The maximum duration between two

watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher

capacitances on pin D2 result in longer watchdog trigger times:

(2)

If the output voltage Q1 decreases below VRT1 (typ. 4.65 V), the external capacitor CD1

is discharged by the reset generator of the main output. If the voltage on this capacitor

drops below VDL1, a reset signal is generated on pin 2 (RO1). If the output voltage rises

above the reset threshold, CD1 will be charged with the constant current IDC1. After the

power-on-reset time the voltage on the capacitor reaches VDU1 and the reset output will

be set high again. The value of the power-on-reset time can be set within a wide range

depending of the capacitance of CD1 using the above given equation (1) analogous for

Q1.

tDon,

CD2 VDU2

IDC2

-----------------------------=

TWI,tr max 0.34 ms/nF CD2

×=

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TLE 4473 GV55-2

Data Sheet 3 Rev. 1.2, 2008-10-28

Figure 1 Watchdog Timing Schedule

AED03099_4473

RO2

DU2

DL2

()

(

DC2

DD2

)

DC2

DD2

WD, p

WD, L

WD, p

WI, tr

WD, L

(

DU2

DL2

)

DC2

(

DU2

DL2

)

DD2

DU2

DL2

WI, tr

;

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Data Sheet 4 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

Figure 2 Block Diagram with Typical External Components

TLE 4473 GV55-2

TLE4473G V55-2_BLO CKDIAG RAM .VSD

Current and

Saturation

Control,

Overcurrent

Protection

Overtemperature

Shutdown

Bandgap

Reference

Inhibit

Reset

Generator

Watchdog

Current and

Saturation

Control,

Overcurrent

Protection

Inhibit

Reset

Generator

GND

µF

4.7 k

Ω

RO2

µC

Supply

µC

Reset

1WI Watchdog

(from µC)

100 nF

11D2

2RO1

6Q1

µF

4.7 k

Ω

e.g. Senso

Supply

e.g. Senso

Reset

(to µ C )

INH18

µC

INH29

Ignition

VBat

100 nF

10D1

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TLE 4473 GV55-2

Data Sheet 5 Rev. 1.2, 2008-10-28

Application Information

The output voltage is divided by a voltage divider and compared to an internal reference

voltage. A regulation loop controls the Q2 output in order to achieve a stable output

voltage at the Q2 pin. A second regulation loop controls the Q1 output. The reference

voltage for the Q1 is the regulated Q2 potential (tracking regulator).

Figure 2 includes the components needed for a typical application. Maintaining the

stability of the regulation loops requires a capacitor of 10 µF both outputs. A maximum

ESR of 5 Ω is permissible for the Q2 output, while the Q1 output requires a capacitor with

a maximum ESR of 3 Ω. For both output blocking capacitors it is recommended to use

tantalum types in order to stay in the permissible ESR range over the full operating

temperature range.

At the input of the regulator a capacitor is necessary for compensating line influences. A

minimum of 100 nF (ceramic capacitor) is recommended. In addition for compensation

of long input lines of several meters an electrolytic input capacitor of 47 µF … 220 µF

should be placed at the input.

Figure 3 Pin Configuration (top view)

TLE4473GV55-2_PIN OU T.VSD

1WI

RO1

RO2

4Q2

N.C.

INH2

INH1

GND

TLE 4473 GV55-2

(P-DSO-12)

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Data Sheet 6 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

Table 1 Pin Definitions and Functions

Pin No. Symbol Function

1WIWatchdog input; input for watchdog pulses, positive edge

triggered.

2RO1Reset and watchdog output for Q1; open collector output.

Connect to pull-up resistor.

3RO2Reset output 2; open collector output. Connect to pull-up resistor.

4Q2Stand-by regulator output voltage; block to GND with a capacitor

CQ2 ≥ 10 µF, ESR < 5 Ω at 10 kHz.

5N.C.Internally not connected; connect to GND.

6Q1Main regulator output voltage; output voltage tracked to Q2

voltage; block to GND with a capacitor CQ1 ≥ 10 µF, ESR < 3 Ω at

10 kHz

7I Input voltage; block to ground directly at the IC with a ceramic

capacitor.

8INH1

Inhibit input 1; low level disables Q1, integrated pull-down resistor.

9INH2

Inhibit input 2; low level at INH2 and INH1 disables Q2 and Q1,

integrated pull-down resistor.

10 D1 Reset Delay 1; connect to ground via a capacitor to set reset delay

for Q1.

11 D2 Reset Delay 2; connect to ground via a capacitor to set reset delay

and watchdog timing for Q2.

12 GND Ground; connect to heatslug.

Heatslug Interconnect with PCB heatsink area and GND.

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TLE 4473 GV55-2

Data Sheet 7 Rev. 1.2, 2008-10-28

Table 2 Absolute Maximum Ratings

-40 °C < Tj < 150 °C

Parameter Symbol Limit Values Unit Remarks

Min. Max.

Input I

Voltage VI-42 45 V –

Current II– – mA Internally limited

Stand-by Output Q2

Voltage VQ2 -0.3 18 V –

Current IQ2 – – mA Internally limited

Main Output Q1

Voltage VQ1 -0.3 18 V –

Current IQ1 – – mA Internally limited

Inhibit Input INH1

Voltage VINH1 -42 45 V –

Current IINH1 -2 2 mA –

Inhibit Input INH2

Voltage VINH2 -42 45 V –

Current IINH2 -2 2 mA –

Reset Output RO1

Voltage VRO1 -0.3 18 V –

Current IRO1 – – mA Internally limited

Reset Output RO2

Voltage VRO2 -0.3 18 V –

Current IRO2 – – mA Internally limited

Reset Delay D1

Voltage VD1 -0.3 7 V –

Current ID1 -5 5 mA –

Reset Delay D2

Voltage VD-0.3 7 V –

Current ID-5 5 mA –

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Data Sheet 8 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

Note: In the operating range the functions given in the circuit description are fulfilled.

Integrated protection functions are designed to prevent IC destruction under fault

conditions. Protection functions are not designed for continuous repetitive

operation.

Watchdog Input WI

Voltage VRADJ -0.3 7 V –

Current IRADJ -5 5 mA –

Temperatures

Junction temperature Tj-50 150 °C–

Storage temperature Tstg -50 150 °C–

Table 3 Operating Range

Parameter Symbol Limit Values Unit Remarks

Min. Max.

Input voltage VI5.6 42 V –

Junction temperature Tj-40 150 °C–

Thermal Resistances PG-DSO-12-11

Junction pin Rthj-pin –4K/W–

Junction ambient Rthj-a – 115 K/W PCB Heat Sink

Area 0 mm2 1)

1) Package mounted on PCB 80 × 80 × 1.5 mm3; 35µ Cu; 5µ Sn; zero airflow.

Junction ambient Rthj-a – 100 K/W PCB Heat Sink

Area 100 mm2 1)

Junction ambient Rthj-a – 60 K/W PCB Heat Sink

Area 300 mm2 1)

Junction ambient Rthj-a – 48 K/W PCB Heat Sink

Area 600 mm2 1)

Table 2 Absolute Maximum Ratings (cont’d)

-40 °C < Tj < 150 °C

Parameter Symbol Limit Values Unit Remarks

Min. Max.

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TLE 4473 GV55-2

Data Sheet 9 Rev. 1.2, 2008-10-28

Table 4 Electrical Characteristics

VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified

Parameter Symbol Limit Values Unit Test Condition

Min. Typ. Max.

Stand-by Regulator

Output Q2

Output voltage VQ2 4.90 5.0 5.10 V 1 mA < IQ2 < 190 mA;

6 V < VI < 28 V

Output current

limitation

IQ2 200 300 650 mA VQ2 = 4.5 V

Output drop voltage;

VDRQ1 = VI1 - VQ1

VDRQ2 – 200 600 mV IQ2 = 100 mA1)

Load regulation ∆VQ2,Lo –1550mV1 mA < IQ2 < 190 mA

Line regulation ∆VQ2,Li –520mVIQ2 = 1 mA;

6 V < VI < 28 V

Power Supply Ripple

Rejection

PSRR –65–dBfr = 100 Hz;

Vr = 1 Vpp

Current Consumption

Quiescent current;

stand-by

Iq = II - IQ2

Iq– 170 220 µAIQ2 = 500 µA; Tj = 25 °C;

VINH1 < VINH1 OFF (Q1 off)

––245µAIQ2 = 500 µA; Tj = 85 °C;

VINH1 < VINH1 OFF (Q1 off)

––280µAIQ2 = 500 µA;

VINH1 < VINH1 OFF (Q1 off)

–4.55mA

IQ2 = 100 mA;

VINH1 < VINH1 OFF (Q1 off)

Quiescent current;

inhibited

Iq–0.11µAVINH1 = VINH2 = 0 V;

Tj < 85 °C

–0.120µAVINH1 = VINH2 = 0 V

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Data Sheet 10 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

Inhibit Input INH2

Turn-on Voltage VINH2 ON ––2.3VVQ2 on

Turn-off Voltage VINH2 OFF 0.65 – – V VQ2 off

H-input current IINH2 ON -1 3.2 6 µAVINH2 = 5.0 V (see

Page 13)

L-input current IINH2 OFF -1 0.1 1 µA0 V < VINH2 < 0.8 V

Watchdog and Reset Timing D2

Charge current IDC2 6.5 9.0 14.0 µAVD2 = 1 V

Discharge current IDD2 2.0 3.5 5.0 µAVD2 = 1 V

Upper timing

threshold

VDU2 1.5 1.85 2.4 V –

Lower timing

threshold

VDL2 0.3 0.45 0.6 V –

Saturation Voltage VD2,SAT ––100mVVQ2 < VRT2

Watchdog trigger

time

TWI,tr 34 42 51 ms CD2 = 100 nF

Reset delay time TRD2 15 20 25 ms CD2 = 100 nF

Reset reaction time Trr ––5.0µsCD2 = 100 nF

Reset Output RO2

Reset switching

threshold

VRT2 4.55 4.65 4.8 V –

VRT2/VQ2 90 93 96 % –

Reset threshold

headroom

VR2HEAD 200 350 500 mV VQ2 - VRT2

Reset output

sink current

IRO2 1.0––mAVQ2 = 5 V, VD2 = 0 V;

VRO2 = 0.3 V

Reset output

low voltage

VRO2L –0.150.3VVQ2 ≥ 1 V;

IRO2 = 1 mA

Reset high voltage VRO2H 4.5––VRRO2,ext = 4.7 kΩ

Table 4 Electrical Characteristics (cont’d)

VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified

Parameter Symbol Limit Values Unit Test Condition

Min. Typ. Max.

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TLE 4473 GV55-2

Data Sheet 11 Rev. 1.2, 2008-10-28

Main (Tracked) Regulator

Output Q1

Output voltage VQ1 4.875 5.0 5.125 V 1 mA < IQ1 < 200 mA;

6 V < VI < 28 V

Output voltage

tracking accuracy ∆VQ =

VQ2 -VQ1

-25 5 25 mV 1 mA < IQ1 < 200 mA;

6 V < VI < 28 V

Output voltage

tracking accuracy ∆VQ =

VQ2 -VQ1

-25 5 25 mV 1 mA < IQ1 < 300 mA;

8 V < VI < 28 V

Output current

limitation

IQ1 350 500 – mA VQ1 = 4.5 V

Output drop voltage

VDRQ1 = VI - VQ1

VDRQ1 – 300 600 mV IQ1 = 200 mA1)

Load regulation ∆VQ1,Lo – 5 50 mV 5 mA < IQ1 < 300 mA

Line regulation ∆VQ1,Li –525mVIQ1 = 5 mA;

6 V < VI < 28 V

Power Supply Ripple

Rejection

PSRR –65–dBfr = 100 Hz;

Vr = 1 Vpp

Current Consumption

Quiescent current;

Iq = II - IQ1 - IQ2

Iq–1020mAIQ1 = 300 mA;

IQ2 = 500 µA;

VQ1 and VQ2 on

Quiescent current;

Iq = II - IQ1 - IQ2

Iq– 250 500 µAIQ2 = IQ1 = 500 µA;

VQ1 and VQ2 on

Inhibit Input INH1

Turn-on Voltage VINH1 ON ––2.3VVQ1 on

Turn-off Voltage VINH1 OFF 0.7––VVQ1 off

H-input current IINH1 ON -1 3.5 5 µA 3.0 V < VINH1 < 5 V;

(see Page 14)

L-input current IINH1 OFF -1 0.1 1 µA0 V < VINH1 < 0.8 V

Table 4 Electrical Characteristics (cont’d)

VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified

Parameter Symbol Limit Values Unit Test Condition

Min. Typ. Max.

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Data Sheet 12 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

Reset Timing D1

Charge current IDC1 4.0 8.0 14.0 µAVD1 = 1 V

Upper timing

threshold

VDU1 1.6 1.8 2.2 V –

Lower timing

threshold

VDL2 0.3 0.4 0.6 V –

Saturation Voltage VD1,SAT ––100mVVQ1 < VRT1

Reset delay time TRD1 14 20 30 ms CD1 = 100 nF

Reset reaction time Trr ––10µsCD1 = 100 nF

Reset Output RO1

Reset switching

threshold

VRT1 4.5 4.65 4.8 V –

VRT1/VQ1 90 93 96 % –

Reset threshold

headroom

VR1HEAD 200 350 500 mV VQ1 - VRT1

Reset output

sink current

IRO1 1.0––mAVQ1 = 5.0 V; VQ2 = 5.0 V;

VD1 = 0 V; VRO1 = 0.3 V

Reset output

low voltage

VRO1L –0.150.3VVQ1 ≥ 1 V

IRO1 = 1 mA

Reset output high

voltage

VRO1H 4.5––VRRO1,ext = 4.7 kΩ

1) Drop voltage = VI - VQ (measured when the output voltage has dropped 100 mV from the nominal value

obtained at 13.5 V input)

Table 4 Electrical Characteristics (cont’d)

VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified

Parameter Symbol Limit Values Unit Test Condition

Min. Typ. Max.

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Data Sheet 13 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

Typical Performance Characteristics

Output Voltage VQ2 versus

Input Voltage VI

Reset Thresholds VRT1, VRT2 versus

Junction Temperature TJ

Output Voltage VQ2 versus

Junction Temperature TJ

INH2 Input Current versus

Inhibit Voltage

AED03353.VSD

VQ2

123456 V8

RLoad = 50 Ω

VINH2 = 5 V

AED03354.VSD

-40

04080 °C160

VRT1, VRT2

4.55

4.60

4.65

4.70

4.75

4.80

AED03352.VSD

-40

0 40 80 °C 160

VQ2

4.90

4.95

5.00

5.05

5.10

5.15

AED03351.VSD

VINH2

IINH2

123456 V8

µA

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Data Sheet 14 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

INH1 Input Current versus

Inhibit Voltage

AED03350.VSD

VINH1

IINH1

123456 V8

µA

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TLE 4473 GV55-2

Data Sheet 15 Rev. 1.2, 2008-10-28

Package Outline

Figure 4 PG-DSO-12-11 (Plastic Dual Small Outline)

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products

and to be compliant with government regulations the device is available as a green

product. Green products are RoHS-compliant (i.e Pb-free finish on leads and suitable for

Pb-free soldering according to IPC/JEDEC J-STD-020).

712

0.8

(1.55)

2.35 ±0.1

2.6 MAX.

0.1 ±0.3

10.3

(4.4 Mold)

4.2 ±0.1

(1.8 Mold)

±0.1

1.6

Index Marking

+0.13

0.4

5 x 1=5

0.25 MAB

±0.1

5.1

6.4

A±0.1 7.5

B±0.1

7.8 ±0.1

(Heatslug)

0.25 B

+0.075

0.25

-0.035

5˚±3˚

12x

+0.1

1) Does not include plastic or metal protrusion of 0.15 max. per side

STANDOFF

(Body)

(Mold)

(Metal)

712

(Metal)

Heatslug

GPS09349

You can find all of our packages, sorts of packing and others in our

Infineon Internet Page “Products”: http://www.infineon.com/products.

Dimensions in mm

SMD = Surface Mounted Device

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Data Sheet 16 Rev. 1.2, 2008-10-28

TLE 4473 GV55-2

Revision History

Version Date Changes

Rev. 1.2 2008-10-28 Modification according to PCN No. 2007-117-A:

•“Watchdog and Reset Timing D2” on Page 10: Lower

timing threshold VDL2: Max limit change to 0.6V (was 0.5V)

and typ. limit change to 0.45V (was 0.4V).

The change does not impact watchdog or reset timing limits

Rev. 1.1 2007-12-19 Modification according to PCN No. 2007-117-A:

• Page 9: Quiescent current Iq; inhibited

(VINH1 = VINH2 = 0 V; Tj < 150 °C):

Max. limit changed to 20µA (was 15µA).

Rev 1.0 2006-12-21 Initial version final datasheet

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Edition 2008-10-28

Published by

Infineon Technologies AG

81726 München, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values

stated herein and/or any information regarding the application of the device, Infineon Technologies hereby

disclaims any and all warranties and liabilities of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

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