General Description
The MAX260/MAX261/MAX262 CMOS dual second-
order universal switched-capacitor active filters allow
microprocessor control of precise filter functions. No
external components are required for a variety of band-
pass, lowpass, highpass, notch, and allpass configura-
tions. Each device contains two second-order filter
sections that place center frequency, Q, and filter oper-
ating mode under programmed control.
An input clock, along with a 6-bit f0program input,
determine the filter's center or corner frequency without
affecting other filter parameters. The filter Q is also pro-
grammed independently. Separate clock inputs for
each filter section operate with either a crystal, RC net-
work, or external clock generator.
The MAX260 has offset and DC specifications superior
to the MAX261 and MAX262 and a center frequency
(f0) range of 7.5kHz. The MAX261 handles center fre-
quencies to 57kHz, while the MAX262 extends the cen-
ter frequency range to 140kHz by employing lower
clock-to-f0ratios. All devices are available in 24-pin DIP
and small outline packages in commercial, extended,
and military temperature ranges.
Applications
µP-Tuned Filters
Anti-Aliasing Filters
Digital Signal Processing
Adaptive Filters
Signal Analysis
Phase-Locked Loops
Features
♦Filter Design Software Available
♦Microprocessor Interface
♦64-Step Center Frequency Control
♦128-Step Q Control
♦Independent Q and f0Programming
♦Guaranteed Clock to f0Ratio-1% (A grade)
♦75kHz f0Range (MAX262)
♦Single +5V and ±5V Operation
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
________________________________________________________________ Maxim Integrated Products 1
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
LPA
INB
LPB
BPB
N.C.
HPA
N.C.
BPA
TOP VIEW
D0
OSC OUT
GND
V-
CLK OUT
A3
D1
INA
16
15
14
13
9
10
11
12
WR
A0
HPB
A1CLKB
CLKA
A2
V+
MAX260
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
LPA
INB
LPB
BPB
OP IN
HPA
OP OUT
BPA
HPB
D0
OSC OUT
V-
CLK OUT
A3
D1
INA
16
15
14
13
9
10
11
12
WR
GND
A0
A1CLKB
CLKA
A2
V+
MAX261
MAX262
Pin Configurations
Ordering Information
OUTPUT
BPHPLPIN
BPHPLPIN
INPUT
+5V V+
GND
-5V V-
CLKA OSC CLKOUT CLKB
PROGRAM
INPUTS
CRYSTAL
FOURTH-ORDER BANDPASS FILTER
MAX260
MAX261
MAX262
FILTER
A
FILTER
B
Functional Diagram
19-0352; Rev 2; 7/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PACKAGE A C C U R A C Y
MAX260ACNG 0°C to +70°C Plastic DIP 1%
MAX260BCNG 0°C to +70°C Plastic DIP 2%
MAX260AENG -40°C to +85°C Plastic DIP 1%
MAX260BENG -40°C to +85°C Plastic DIP 2%
MAX260ACWG 0°C to +70°C Wide SO 1%
MAX260BCWG 0°C to +70°C Wide SO 2%
MAX260AMRG -55°C to +125°C CERDIP 1%
MAX260BMRG -55°C to +125°C CERDIP 2%
*All devices—24-pin packages 0.3in-wide packages
Ordering Information continued at end of data sheet.
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Total Supply Voltage (V+to V-) .............................................15V
Input Voltage, any pin ..........................(V-- 0.3V) to (V++ 0.3V)
Input Current, any pin ......................................................±50mA
Power Dissipation
Plastic DIP (derate 8.33mW/°C above 70°C) ...............660mW
CERDIP (derate 12.5mW/°C above 70°C) .................1000mW
Wide SO (derate 11.8mW/°C above 70°C) ..................944mW
Operating Temperature Ranges
MAX260/MAX261/MAX262XCXG .......................0°C to +70°C
MAX260/MAX261/MAX262XEXG .....................-40°C to +85°C
MAX260/MAX261/MAX262XMXG ..................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (Soldering, 10s) ................................+300°C
ELECTRICAL CHARACTERISTICS
(V+= +5V, V-= -5V, CLKA= CLKB= ±5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0= 199.49 for
MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
f0 Center Frequency Range See Table 1
Maximum Clock Frequency See Table 1
MAX260A ±0.2 ±1.0
MAX260B ±0.2 ±2.0
MAX261/MAX262A ±0.2 ±1.0
fCLK/f0 Ratio Error (Note 1) TA = TMIN to TMAX
MAX261/MAX262B ±0.2 ±2.0
%
f0 Temperature Coefficient -5 ppm/°C
Q = 8 MAX260A ±1 ±6
Q = 8 MAX260B ±1 ±10
Q = 32 MAX260A ±2 ±10
Q = 32 MAX260B ±2 ±15
Q = 64 MAX260A ±4 ±20
Q = 64 MAX260B ±4 ±25
Q = 8 MAX261/MAX262A ±1 ±6
Q = 8 MAX261/MAX262B ±1 ±10
Q = 32 MAX261/MAX262A ±2 ±10
Q = 32 MAX261/MAX262B ±2 ±15
Q = 64 MAX261/MAX262A ±4 ±20
Q Accuracy (deviation from ideal
continuous filter) (Note 2)
TA = TMIN to
TMAX
Q = 64 MAX261/MAX262B ±4 ±25
%
Q Temperature Coefficient ±20 ppm/°C
MAX260 ±0.1 ±0.3
DC Lowpass Gain Accuracy MAX261/MAX262 ±0.1 ±0.5 dB
MAX260 -5
MAX261/MAX262 -5
Gain Temperature Coefficient Lowpass (at D.C.)
Bandpass (at f0)MAX260/MAX261/MAX262 +20
ppm/°C
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V+= +5V, V-= -5V, CLKA= CLKB= ±5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0= 199.49 for
MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
MAX260A ±0.05 ±0.25
MAX260B ±0.15 ±0.45
MAX261A ±0.40 ±1.00
MAX261B ±0.80 ±1.60
MAX262A ±0.40 ±1.20
TA = TMIN to TMAX, Q = 4
Mode 1
MAX262B ±0.80 ±1.60
MAX260A ±0.075 ±0.30
MAX260B ±0.075 ±0.50
MAX261A ±0.50 ±1.10
MAX261B ±0.90 ±1.60
MAX262A ±0.50 ±1.30
Offset Voltage At Filter
Outputs—LP, BP, HP (Note 3)
Mode 3
MAX262B ±0.90 ±1.60
V
Offset Voltage Temperature
Coefficient
fCLK/f0 = 100.53, Q = 4
TA = TMIN to TMAX ±0.75 mV/°C
Clock Feedthrough ±4 mV
Crosstalk -70 dB
Q = 1, 2nd-Order, LP/BP See Typ. Oper. Char.
4th-Order LP (Figure 26) 90Wideband Noise
4th-Order BP (Figure 24) (Note 4) 100
µVRMS
Harmonic Distortion at f0Q = 4, VIN = 1.5VP-P -67 dB
Supply Voltage Range TA = TMIN to TMAX ±2.37 ±5 ±6.3 V
MAX260 15 20
MAX261 16 20
Power Supply Current (Note 5) TA = TMIN to TMAX
CMOS Level Logic Inputs MAX262 16 20
mA
Shutdown Supply Current Q0A - Q6A = all 0,
CMOS Level Logic Inputs (Note 5) 1.5 mA
INTERNAL AMPLIFIERS
Output Signal Swing TA = TMIN to TMAX, 10kΩ load (Note 6) ±4.75 V
Source 50
Output Signal Circuit Current Sink 2 mA
Power Supply Rejection Ratio 0Hz to 10kHz -70 dB
Gain Bandwidth Product 2.5 MHz
Slew Rate 6V/
µ
s
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (for V± = ±2.5V ±5%)
(V+= +2.37V, V-= -2.37V, CLKA= CLKB= ±2.5V 250kHz for the MAX260 and 1MHz for the MAX261/MAX262, fCLK/f0= 199.49 for
MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
f0 Center Frequency Range (Note 7)
Maximum Clock Frequency (Note 7)
MAX26XA ±0.1 1
fCLK/f0 Ratio Error
(Notes 1, 8) Q = 8 MAX26XB ±0.1 2 %
MAX260A ±2 ±6
Q = 8
fCLK/f0 = 199.49 MAX260B ±2 ±10
MAX261A ±2 ±6
fCLK/f0 = 199.49 MAX261B ±2 ±10
MAX262A ±2 ±6
Q Accuracy (deviation from ideal
continuous filter)
(Notes 2, 8)
fCLK/f0 = 139.80 MAX262B ±2 ±10
%
Output Signal Swing All Outputs (Note 6) ±2 V
Power Supply Current CMOS Level Logic Inputs (Note 5) 7 mA
Shutdown Current CMOS Level Logic Inputs (Note 5) 0.35 mA
Note 1: fCLK/f0accuracy is tested at 199.49 on the MAX260/MAX261, and at 139.8 on the MAX262.
Note 2: Q accuracy tested at Q = 8, 32, and 64. Q of 32 and 64 tested at 1/2 stated clock frequency.
Note 3: The offset voltage is specified for the entire filter. Offset is virtually independent of Q and fCLK/f0ratio setting. The test clock
frequency for mode 3 is 175kHz for the MAX260 and 750kHz for the MAX261/MAX262.
Note 4: Output noise is measured with an RC output smoothing filter at 4 ✕ f0to remove clock feedthrough.
Note 5: TTL logic levels are: HIGH = 2.4V, LOW = 0.8V. CMOS logic levels are: HIGH = 5V, LOW = 0V. Power supply current is typi-
cally 4mA higher with TTL logic and clock input levels.
Note 6: On the MAX260 only, the HP output signal swing is typically 0.75V less than the LP or BP outputs.
Note 7: At ±2.5V supplies, the f0range and maximum clock frequency are typically 75% of values listed in Table 1.
Note 8: fCLK/f0and Q accuracy are a function of the accuracy of internal capacitor ratios. No increase in error is expected at ±2.5V
as compared to ±5V; however, these parameters are only tested to the extent indicated by the MIN or MAX limits.
INTERFACE SPECIFICATIONS (Note 9)
(V+= +5V, V+= -5V, TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WR Pulse Width tWR 250 150 ns
Address Setup tAS 25 ns
Address Hold tAH 0ns
Data Setup tDS 100 50 ns
Data Hold tDH 10 0 ns
Logic Input High VIH
WR, D0, D1, A0–A3, CLKA, CLKB
TA =TMIN to TMAX 2.4 V
Logic Input Low VIL
WR, D0, D1, A0–A3, CLKA, CLKB
TA =TMIN to TMAX 0.8 V
10
60
Input Leakage Current IIN
WR, D0, D1, A0–A3, CLKB
CLKA
TA =TMIN to TMAX
6µA
Input Capacitance CIN WR, D0, D1, A0–A3, CLKA, CLKB15 pF
Note 9: Interface timing specifications are guaranteed by design and are not subject to test.
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
_______________________________________________________________________________________ 5
Pin Description
PIN
MAX260 MAX261/
MAX262
NAME FUNCTION
99V
+Positive supply voltage
17 16 V-Negative supply voltage
18 17 GND
Analog Ground. Connect
to the system ground for
dual supply operation or
mid-supply for single sup-
ply operation. GND should
be well bypassed in single
supply applications.
11 11 CLKA
Input to the oscillator and
clock input to section A.
This clock is internally
divided by 2.
12 12 CLKB
Clock input to filter B. This
clock is internally divided
by 2.
8 8 CLK OUT C l ock outp ut for cr ystal
and R- C osci l l ator op er ati on
19 18 OSC OUT Connects to crystal or R-C
for self-clocked operation
PIN
MAX260 MAX261/
MAX262
NAME FUNCTION
5, 23 5, 23 INA, INBFilter inputs
1, 21 1, 21 BPA, BPBBandpass outputs
24, 22 24, 22 LPA, LPBLowpass outputs
3, 14 3, 20 HPA, HPBHighpass/notch/allpass
outputs
16 15 WR Write enable input
15, 13,
10, 7
14, 13,
10, 7
A0, A1,
A2, A3
Address inputs for f0 and
Q input data locations
20, 6 19, 6 D0, D1 Data inputs for f0 and Q
programming
2 OP OUT
Outp ut of uncom m i tted
op am p on M AX 261/
M AX 262 onl y. P i n 2 i s a no-
connect on the M AX 260.
4 OP IN
Inver ti ng i np ut of uncom -
m i tted op am p on M AX 261/
M AX 262 onl y ( noni nver ti ng
i np ut i s i nter nal l y connected
to g r ound ) . P i n 4 i s a no-
connect on the M AX 260.
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
6 _______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
-20
-10
10
0
20
30
0.2 0.60.4 0.8 1.0 1.2 1.4
Q ERROR vs. CLOCK FREQUENCY
MAX260
MAX260/61/62 toc01
CLOCK FREQUENCY (MHz)
Q ERROR (%)
MODE 4
±5V
25°C
Q = 8
fCLK/f0 → N = 0
MODES 2 & 3
MODE 1
5
10
15
20
25
IDD vs. POWER SUPPLY VOLTAGE
MAX260/61/62 toc02
V+ TO V- (V)
IDD (mA)
5896 7 10 11 12
CLK FREQ = 500KHz
25°C
CONTROL PINS (5V, 0V)
CLOCKS (5V, 0V)
CLOCKS (5V, -5V)
13
15
14
17
16
19
18
20
0.5 1.5 2.5 3.5
IDD vs. CLOCK FREQUENCY
MAX260/61/62 toc03
CLOCK FREQUENCY (MHz)
IDD (mA)
CLOCK (2.4V, 0.8V)
CLOCK (5V, 0V)
±5V
CONTROL PINS (5V, 0V)
25°C
CLOCK (5V, -5V)
-4
0
4
8
12
16
20
0.5 1.51.0 2.0 2.5 3.0 3.5
Q ERROR vs. CLOCK FREQUENCY
MAX261/MAX262
MAX260/61/62 toc04
CLOCK FREQUENCY (MHz)
Q ERROR (%)
MODE 3
MODE 2
MODES 1, 4
±5V
Q = 8
TA = 25°C
→ N = 0
fCLK
f0
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
1.0 1.5 2.0 2.5 3.0 3.5
FCLK/F0 ERROR vs. CLOCK FREQUENCY
MAX261/MAX262
MAX260/61/62 toc05
CLOCK FREQUENCY (MHz)
FCLK/F0 ERROR (%)
MODES 2, 3
MODES 1, 4
±5V
Q = 8
TA = 25°C
fCLK
f0
→ N = 0
0
2
1
4
3
7
6
5
8
0.2 1.00.6 1.4 1.8 2.2 2.8 3.0
OUTPUT SIGNAL SWING
vs. CLOCK FREQUENCY
MAX260/61/62 toc06
CLOCK FREQUENCY (MHz)
PEAK TO PEAK, OUTPUT SWING (V)
MAX261/MAX262 ALL MODES
MAX260 MODE 4
±5V
25°C
Q = 8
fCLK/f0→ N = 0
MAX260 MODES 1, 2, 3
Q = 1 Q = 8 Q = 64
MODE LP BP HP/AP/N LP BP HP/AP/N LP BP HP/AP/N
1 -84 -90 -84 -80 -82 -85 -72 -73 -85
2 -88 -90 -88 -84 -82 -84 -77 -73 -76
3 -84 -90 -88 -80 -82 -82 -73 -73 -74
MAX261/
MAX262
4 -83 -89 -84 -79 -81 -85 -71 -73 -85
1 -87 -89 -86 -81 -81 -86 -73 -73 -86
2 -89 -88 -85 -83 -80 -82 -75 -72 -74
3 -87 -88 -85 -80 -82 -80 -71 -72 -72
MAX260
4 -87 -88 -86 -81 -81 -86 -71 -72 -86
MEASUREMENT
BANDWIDTH Q = 1 Q = 8 Q = 64
Wideband -84 -80 -72
3kHz -87 -87 -86
C Message
Weighted -93 -93 -93
Wideband RMS Noise (db ref. to 2.47VRMS, 7VP-P)±5V Supplies
Note 1: fCLK = 1MHz for MAX261/MAX262, fCLK = 350kHz for MAX260
Note 2: fCLK/f0ratio programmed at N = 63 (see Table 2)
Note 3: Clock feedthrough is removed with an RC lowpass ar 4f0, ie., R = 3.9kΩ,
C = 2000pF for MAX261.
Noise Spectral Distribution
(MAX261, fCLK = 1MHz, dB ref. to 2.47VRMS,
7VP-P)
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
_______________________________________________________________________________________ 7
Introduction
Each MAX260/MAX261/MAX262 contains two second-
order switched-capacitor active filters. Figure 1 shows
the filter's state variable topology, employed with two
cascaded integrators and one summing amplifier. The
MAX261 and MAX262 also contain an uncommitted
amplifier. On-chip switches and capacitors provide
feedback to-control each filter section's f0and Q.
Internal capacitor ratios are primarily responsible for
the accuracy of these parameters. Although these
switched-capacitor networks (SCN) are in fact sampled
systems, their behavior very closely matches that of
continuous filters, such as RC active filters. The ratio of
the clock frequency to the filter center frequency
(fCLK/f0) is kept large so that ideal second-order state-
variable response is maintained.
The MAX262 uses a lower range of sampling (fCLK/f0)
ratios than the MAX260 or MAX261 to allow higher
operating f0frequencies and signal bandwidths. These
reduced sample rates result in somewhat more devia-
tion from ideal continuous filter parameters than with
the MAX260/MAX261. However, these differences can
be compensated using Figure 20 (see Application
Hints) or Maxim's filter design software.
The MAX260 employs auto-zero circuitry not included
in the MAX261 or MAX262. This provides improved DC
characteristics, and improved low-frequency perform-
ance at the expense of high-end f0and signal band-
width. The N/HP/AP outputs of the MAX260 are internal-
ly sample-and-held as a result of its auto-zero
operation. Signal swing at this output is somewhat
reduced as a result (MAX260 only). See Table 1 for
bandwidth comparisons of the three filters.
Maxim also provides design programs that aid in con-
verting filter response specifications into the f0and Q
program codes used by the MAX260 series devices.
This software also precompensates f0and Q when low
sample rates are used.
It is important to note that, in all MAX260 series filters,
the filter's internal sample rate is one half the input
clock rate (CLKAor CLKB) due to an internal division
by two. All clock-related data, tables, and other dis-
cussions in this data sheet refer to the frequency at the
CLKAor CLKBinput, i.e., twice the internal sample rate,
unless specifically stated otherwise.
Quick Look Design Procedure
The MAX260, MAX261, and MAX262, with Maxim's filter
design software, greatly simplify the design procedures
for many active filters. Most designs can be realized
using a three-step process described in this section. If
the design software is not used, or if the filter complexi-
ty is beyond the scope of this section, refer to the
remainder of this data sheet for more detailed applica-
tions and design information.
M1M0
S2
SCNIN
S3S1
MODE
SELECT
SCN
Q0–Q6
(TABLE 3)
F0–F5
(TABLE 2)
S1
SAMPLE-HOLD
MAX260 ONLY
N/HP/AP
BP
LP
S2
S3
+
-
-
SCN = SWITCH-CAPACITOR NETWORK
+
-∫ ∫
SCN
SCN
Σ
S-H
Figure 1. Filter Block Diagram (One Second-Order Section)
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
8 _______________________________________________________________________________________
Step 1—Filter Design
Start with the program “PZ” to determine what type of
filter is needed. This helps determine the type
(Butterworth, Chebyshev, etc.) and the number of poles
for the optimum choice. The program also plots the fre-
quency response and calculates the pole/zero (f0) and
Q values for each second-order section. Each
MAX260/MAX261/MAX262 contains two second-order
sections, and devices can be cascaded for higher
order filters.
MAX260
MAX261*
MAX262*
INA
OUT
IN 5
24
3
1
23
22
(20)14
21
LPA
HPA
BPA
LPB
HPB
BPB
INB
WR
D0
D1
A0
A2
A3
CLKA
CLKB
A1
16(15)
20(19)
6
1
2
3
4
5
6
7
11
24
25
23
22
21
20
19
18
DB-25 MALE PLUG
(BACK VIEW)
12
15(14)
10
7
11
12
9 18(17) 17(16) CLK IN
TTL
(SEE FIGURE 4)
0.1µF 0.1µF
-5V+5V
13
V+V-
GND
*PIN NUMBERS IN ( ) ARE FOR MAX261/MAX262
100 AB$ = "FILTER A" : GOSUB 150 : REM GET DATA FOR SECTION A
110 ADD = 0 : GOSUB 220 : REM WRITE DATA TO THE PRINTER PORT
120 AB$ = "FILTER B" : GOSUB 150 : REM GET DATA FOR B
130 ADD = 32 : GOSUB 220 : REM WRITE DATA TO PRINTER PORT
140 GOTO 100
150 PRINT "MODE (1 to 4, see Table 5) "; AB$; : INPUT M
160 IF M<1 OR M>4 THEN GOTO 150
170 PRINT "CLOCK RATIO (0 to 63, N of Table 2) "; AB$; : INPUT F
180 IF F<0 OR F>63 THEN GOTO 170
190 PRINT "Q (0 to 127, N of Table 3) "; AB$; : INPUT Q
200 IF Q<0 OR Q>127 THEN GOTO 190 ELSE : PRINT
210 RETURN
220 LPRINT CHR$(ADD+M-1); : ADD = ADD+4
230 FOR I = 1 TO 3
240 X = (ADD + (F - 4*INT(F/4))) : LPRINT CHR$(X);
250 F=INT(F/4) : ADD = ADD + 4
260 NEXT I
270 FOR I = 1 TO 4
280 X=(ADD + (Q - 4*INT(Q/4))) : LPRINT CHR$(X);
290 Q=I (Q/4) :: ADD = ADD + 4
300 NEXT I
310 RETURN
Figure 2. Basic Program and Hardware Connections to Parallel Printer Port for “Quick Look” Using a PC
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
_______________________________________________________________________________________ 9
Step 2—Generate Programming
Coefficients
Starting with the f0and Q values obtained in Step 1, use
the program “MPP” to generate the digital coefficients
that program each second-order section's f0and Q. The
program displays values for “N” (“N = _ for f0” and “N =
_ for Q”). N is the decimal equivalent of the binary code
that sets the filter section’s f0or Q. These are the same
“N”s that are listed in Tables 2 and 3.
An input clock frequency and filter mode must also be
selected in this step; however, if a specific-clock rate is
not selected, “GEN” picks one. With regard to mode
selection, mode 1 is the most convenient choice for
most bandpass and lowpass filters. Exceptions are
elliptic bandpass and lowpass filters, which require
mode 3. Highpass filters also use mode 3, while allpass
filters use mode 4. For further information regarding
these filter modes, see the Filter Operating Modes sec-
tion.
Step 3—Loading the Filter
When the N values for the f0and Q of each second-
order filter section are determined, the filter can then be
programmed and operated. What follows is a con-
venient method of programming the filter and evalu-
ating a design if a PC is available.
A short BASIC program loads data into the MAX260/
MAX261/MAX262 through the PC's parallel printer port.
The program asks for the filter mode, as well as the N
values for the f0and Q of each section. These coeffi-
cients are then loaded into the filter in the form of ASCII
characters. This program can be used with or without
Maxim's other filter design software. The program and
the appropriate hardware connections for a Centronics-
type printer port are shown in Figure 2.
Filter Design Software
Maxim provides software programs to help speed the
transition from frequency response design require-
ments to working hardware. A series of programs are
available, including:
Program PZ. Given the requirements, such as center
frequency, Q, passband ripple, and stopband attenua-
tion, PZ calculates the pole frequencies, Q's, zeros,
and the number of stages needed.
Program MPP. For programmed filters, MPP computes
the input codes to use and describes the expected
performance of the design.
Program FR. When a design of one or more stages is
completed, FR checks the final cascaded assembly.
The output frequency response can be compared with
that expected from PZ.
Program PR.BAS Allows a MAX260/MAX261/MAX262
to be programmed through a personal computer. The
mode, f0, and Q of each section are typed in, and the
proper codes are sent to the filter through the comput-
er’s parallel printer port. This program is also provided
in Figure 2.
Other design programs are also included for use with
other Maxim filter products.
Other Filter Products
Maxim has developed a number of other filter products
in addition to the MAX260, MAX261, and MAX262.
PIN-PROGRAMMABLE ACTIVE FILTERS—A dual sec-
ond-order universal filter that needs no external compo-
nents. A microprocessor interface is not required.
MAX263 0.4Hz to 30kHz f0range
MAX264 1Hz to 75kHz f0range
RESISTOR AND PIN-PROGRAMMABLE FILTERS—A
dual second-order universal filter where f0adjustment
beyond pin-programmable resolution employs external
resistors.
MAX265 0.4Hz to 30kHz f0range. Includes two
uncommitted op amps.
MAX266 1Hz to 75kHz f0range. Includes two un-
committed op amps.
MF10 Industry Standard, Resistor Programmed Only
PIN-PROGRAMMABLE BANDPASS FILTERS—A
dual second-order bandpass that needs no external
components. A microprocessor interface is not
required.
MAX267 0.4Hz to 30kHz f0range
MAX268 1Hz to 75kHz f0range
PROGRAMMABLE ANTI-ALIAS FILTER—A program-
mable dual second-order continuous (not switched)
lowpass filter. No clock noise is generated. Designed
for use as an anti-alias filter in front of, or as a smooth-
ing filter following, any sampled filter or system.
MAX270 1kHz to 25kHz Cutoff Frequency Range
5th-ORDER LOW PASS FILTER—Features zero offset
and drift errors for designs requiring high DC accuracy.
MAX280, LT1062 0.1Hz to 20kHz Cutoff Frequency
Range
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
10 ______________________________________________________________________________________
PART Q MODE fCLK f0
1 1 1Hz–400kHz 0.01Hz–4.0kHz
1 2 1Hz–425kHz 0.01Hz–6.0kHz
1 3 1Hz–500kHz 0.01Hz–5.0kHz
1 4 1Hz–400kHz 0.01Hz–4.0kHz
8 1 1Hz–500kHz 0.01Hz–5.0kHz
8 2 1Hz–700kHz 0.01Hz–10.0kH
8 3 1Hz–700kHz 0.01Hz–5.0kHz
8 4 1Hz–600kHz 0.01Hz–4.0kHz
64 1 1Hz–750kHz 0.01Hz–7.5kHz
90 2 1Hz–500kHz 0.01Hz–7.0kHz
64 3 1Hz–400kHz 0.01Hz–4.0kHz
MAX260
64 4 1Hz–750kHz 0.01Hz–7.5kHz
1 1 40Hz–4.0MHz 0.4Hz–40kHz
1 2 40Hz–4.0MHz 0.5Hz–57kHz
1 3 40Hz–4.0MHz 0.4Hz–40kHz
1 4 40Hz–4.0MHz 0.4Hz–40kHz
8 1 40Hz–2.7MHz 0.4Hz–27kHz
8 2 40Hz–2.1MHz 0.5Hz–30kHz
MAX261
PART Q MODE fCLK f0
8 3 40Hz–1.7MHz 0.4Hz–17kHz
8 4 40Hz–2.7MHz 0.4Hz–27kHz
64 1 40Hz–2.0MHz 0.4Hz–20kHz
90 2 40Hz–1.2MHz 0.4Hz–18kHz
64 3 40Hz–1.2MHz 0.4Hz–12kHz
MAX261
64 4 40Hz–2.0MHz 0.4Hz–20kHz
1 1 40Hz–4.0MHz 1.0Hz–100kHz
1 2 40Hz–4.0MHz 1.4Hz–140kHz
1 3 40Hz–4.0MHz 1.0Hz–100kHz
1 4 40Hz–4.0MHz 1.0Hz–100kHz
8 1 40Hz–2.5MHz 1.0Hz–60kHz
6 2 40Hz–1.4MHz 1.4Hz–50kHz
8 3 40Hz–1.4MHz 1.0Hz–35kHz
8 4 40Hz–2.5MHz 1.0Hz–60kHz
64 1 40Hz–1.5MHz 1.0Hz–37kHz
90 2 40Hz–0.9MHz 1.4Hz–32kHz
64 3 40Hz–0.9MHz 1.0Hz–22kHz
MAX262
64 4 40Hz–1.5MHz 1.0Hz–37kHz
Table 1. Typical Clock and Center Frequency Limits
INALPA
N/HP/APABPA
2 6 7
2 4
A0–A3 WR CLKACLKB
OSC OUT CLK OUT OP OUTOP IND0, D1
MODE
A PROGRAM MEMORY
MODE, f0, Q
INTERFACE
LOGIC
÷2
f0
15
QCK
INBLPB
N/HP/APBBPB
2 6 7
MODE
B PROGRAM MEMORY
MODE, f0, Q ÷2
f0
V+
15
QCK
V-
GND
+
-
MAX261/MAX262 ONLY
∫∫ ∫∫
Figure 3. MAX260/MAX261/MAX262 Block Diagram
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 11
fCLK/f0 RATIO
MAX260/MAX261 MAX262 PROGRAM CODE
MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 N F5 F4 F3 F2 F1 F0
100.53 71.09 40.84 28.88 0000000
102.10 72.20 42.41 29.99 1000001
103.67 73.31 43.98 31.10 2000010
105.24 74.42 45.55 32.21 3000011
106.81 75.53 47.12 33.32 4000100
108.38 76.64 48.69 34.43 5000101
109.96 77.75 50.27 35.54 6000110
111.53 78.86 51.84 36.65 7000111
113.10 79.97 53.41 37.76 8001000
114.67 81.08 54.98 38.87 9001001
116.24 82.19 56.55 39.99 10 001010
117.81 83.30 58.12 41.10 11 001011
119.38 84.42 59.69 42.21 12 001100
120.95 85.53 61.26 43.32 13 001101
122.52 86.64 62.83 44.43 14 001110
124.09 87.75 64.40 45.54 15 001111
125.66 88.86 65.97 46.65 16 010000
127.23 89.97 67.54 47.76 17 010001
128.81 91.80 69.12 48.87 18 010010
130.38 92.19 70.69 49.98 19 010011
131.95 93.30 72.26 51.10 20 010100
133.52 94.41 73.83 52.20 21 010101
135.08 95.52 75.40 53.31 22 010110
136.66 96.63 76.97 54.43 23 010111
138.23 97.74 78.53 55.54 24 011000
139.80 98.86 80.11 56.65 25 011001
141.37 99.97 81.68 57.76 26 011010
142.94 101.08 83.25 58.87 27 011011
14.4.51 102.89 84.82 59.98 28 011100
146.08 103.30 86.39 61.09 29 011101
147.65 104.41 87.96 62.20 30 011110
149.23 105.52 89.54 63.31 31 011111
150.80 106.63 91.11 64.42 32 100000
152.37 107.74 92.68 65.53 33 100001
153.98 108.85 94.25 66.64 34 100010
155.51 109.96 95.82 67.75 35 100011
157.08 111.07 97.39 68.86 36 100100
158.65 112.18 98.96 69.98 37 100101
160.22 113.29 100.53 71.09 38 100110
161.79 114.41 102.10 72.20 39 100111
163.36 115.52 102.67 73.31 40 101000
164.93 116.63 105.24 74.42 41 101001
166.50 117.74 106.81 75.53 42 101010
168.08 118.85 108.38 76.64 43 101011
169.65 119.96 109.96 77.75 44 101100
171.22 121.07 111.53 78.86 45 101101
Table 2. fCLK/f0Program Selection Table
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
12 ______________________________________________________________________________________
Detailed Description
f0and Q Programming
Figure 3 shows a block diagram of the MAX260. Each
second-order filter section has its own clock input and
independent f0and Q control. The actual center fre-
quency is a function of the filter's clock rate, 6-bit f0
control word (see Table 2), and operating mode. The Q
of each section is also set by a separate programmed
input (see Table 3). This way, each half of a MAX260/
MAX261/MAX262 is tuned independently so that com-
plex filter polynomials can be realized. Equations that
convert program code numbers to fCLK/f0and Q values
are listed in the notes beneath Tables 2 and 3.
Oscillator and Clock Inputs
The clock circuitry of the MAX260/MAX261/MAX262
can operate with a crystal, resistor-capacitor (RC) net-
work, or an external clock generator as shown in Figure
4. If an RC oscillator is used, the clock rate, fCLK, nomi-
nally equals 0.45/RC.
The duty cycle of the clock at CLKAand CLKBis unim-
portant because the input is internally divided by 2 to
generate the sampling clock for each filter section. It is
important to note that this internal division also halves
the sample rate when considering aliasing and other
sampled system phenomenon.
Microprocessor Interface
f0, Q, and mode-selection data are stored in internal
program memory. The memory contents are updated
by writing to addresses selected by A0–A3. D0, and D1
are the data inputs. A map of the memory locations is
shown in Table 4. Data is stored in the selected
address on the rising edge of WR. Address and data
inputs are TTL and CMOS compatible when the filter is
powered from ±5V. With other power supply voltages,
CMOS logic levels should be used. Interface timing is
shown in Figure 5. Note: Clock inputs CLKAand CLKB
have no relation to the digital interface. They control the
switched-capacitor filter sample rate only.
Some noise may be generated on the filter outputs by
transitions at the logic inputs. If this is objectionable,
fCLK/f0 RATIO
MAX260/MAX261 MAX262 PROGRAM CODE
MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 N F5 F4 F3 F2 F1 F0
172.79 122.18 113.10 79.97 46 101110
174.36 123.29 114.66 81.08 47 101111
175.93 124.40 11624 82.19 48 110000
177.50 125.51 117.81 83.30 49 110001
179.07 126.62 119.38 84.41 50 110010
180.64 127.73 120.95 85.53 51 110011
182.21 128.84 122.52 86.64 52 110100
183.78 129.96 124.09 87.75 53 110101
185.35 131.07 125.66 88.86 54 110110
186.92 132.18 127.23 89.97 55 110111
188.49 133.29 128.81 91.08 56 111000
190.07 134.40 130.38 92.19 57 111001
191.64 135.51 131.95 93.30 58 111010
193.21 136.62 133.52 94.41 59 111011
194.78 137.73 135.09 95.52 60 111100
196.35 138.84 136.66 96.63 61 111101
197.92 139.95 138.23 97.74 62 111110
199.49 141.06 139.80 98.85 63 111111
Table 2. fCLK/f0Program Selection Table (continued)
Note 1: For the MAX260/MAX261, fCLK/f0= (64 + N)π / 2 in modes 1, 3, and 4, where N varies from 0 to 63.
Note 2: For the MAX262, fCLK/f0= (26 s N)π / 2 in modes 1, 3, and 4, where N varies 0 to 63.
Note 3: In mode 2, all fCLK/f0ratios are divided by √2. The functions are then:
MAX260/MAX261 fCLK/f0= 1.11072 (64 + N), MAX262 fCLK/f0= 1.11072 (26 + N)
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 13
PROGRAMMED Q PROGRAM CODE
MODES
1,3,4
MODE
2N Q6Q5Q4Q3Q2Q1Q0
0.500* 0.707* 0* 0 0 0 0 0 0 0
0.504 0.713 1 0 0 0 0 0 0 1
0.508 0.718 2 0 0 0 0 0 1 0
0.512 0.724 3 0 0 0 0 0 1 1
0.516 0.730 4 0 0 0 0 1 0 0
0.520 0.736 5 0 0 0 0 1 0 1
0.525 0.742 6 0 0 0 0 1 1 0
0.529 0.748 7 0 0 0 0 1 1 1
0.533 0.754 8 0 0 0 1 0 0 0
0.538 0.761 9 0 0 0 1 0 0 1
0.542 0.767 10 0 0 0 1 0 1 0
0.547 0.774 11 0 0 0 1 0 1 1
0.552 0.780 12 0 0 0 1 1 0 0
0.556 0.787 13 0 0 0 1 1 0 1
0.561 0.794 14 0 0 0 1 1 1 0
0.566 0.801 15 0 0 0 1 1 1 1
0.571 0.808 16 0 0 1 0 0 0 0
0.577 0.815 17 0 0 1 0 0 0 1
0.582 0.823 18 0 0 1 0 0 1 0
0.587 0.830 19 0 0 1 0 0 1 1
0.593 0.838 20 0 0 1 0 1 0 0
0.598 0.646 21 0 0 1 0 1 0 1
0.604 0.854 22 0 0 1 0 1 1 0
0.609 0.862 23 0 0 1 0 1 1 1
PROGRAMMED Q PROGRAM CODE
MODES
1,3,4
MODE
2N Q6Q5Q4Q3Q2Q1Q0
0.615 0.870 24 0 0 1 1 0 0 0
0.621 0.879 25 0 0 1 1 0 0 1
0.627 0.887 26 0 0 1 1 0 1 0
0.634 0.896 27 0 0 1 1 0 1 1
0.640 0.905 28 0 0 1 1 1 0 0
0.646 0.914 29 0 0 1 1 1 0 1
0.653 0.924 30 0 0 1 1 1 1 0
0.660 0.933 3100 11 11 1
0.667 0.943 3201 00 00 0
0.674 0.953 3301 00 00 1
0.681 0.963 3401 00 01 0
0.688 0.973 3501 00 01 1
0.696 0.984 3601 00 10 0
0.703 0.995 3701 00 10 1
0.711 1.01 3801 00 11 0
0.719 1.02 3901 00 11 1
0.727 1.03 4001 01 00 0
0.736 1.04 4101 01 00 1
0.744 1.05 4201 01 01 0
0.753 1.06 43 0 1 0 1 0 1 1
0.762 1.08 44 0 1 0 1 1 0 0
0.771 1.09 45 0 1 0 1 1 0 1
0.780 1.10 46 0 1 0 1 1 1 0
0.790 1.12 47 0 1 0 1 1 1 1
Table 3. Q Program Selection Table
Note 4: * Writing all 0s into Q0A–Q6A on Filter A activates a low-power shutdown mode. BOTH filter sections are deactivated.
Therefore, this Q value is only achievable in filter B.
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
14 ______________________________________________________________________________________
PROGRAMMED Q PROGRAM CODE
MODES
1,3,4
MODE
2N Q6Q5Q4Q3Q2Q1Q0
0.800 1.13 48 0110000
0.810 1.15 49 0110001
0.821 1.16 50 0110010
0.831 1.18 51 0110011
0.842 1.19 52 0110100
0.853 1.21 53 0110101
0.865 1.22 54 0110110
0.877 1.24 55 0110111
0.889 1.26 56 0111000
0.901 1.27 57 0111001
0.914 1.29 58 0111010
0.928 1.31 59 0111011
0.941 1.33 60 0111100
0.955 1.35 61 0111101
0.969 1.37 62 0111110
0.985 1.39 63 0111111
1.00 1.41 64 1000000
1.02 1.44 65 1000001
1.03 1.46 66 1000010
1.05 1.48 67 1000011
1.07 1.51 68 1000100
1.08 1.53 69 1000101
1.10 1.56 70 1000110
1.12 1.59 71 1000111
1.14 1.62 72 1001000
1.16 1.65 73 1001001
1.19 1.68 74 1001010
1.21 1.71 75 1001011
1.23 1.74 76 1001100
1.25 1.77 77 1001101
1.28 1.81 78 1001110
1.31 1.85 79 1001111
1.33 1.89 80 1010000
1.36 1.93 81 1010001
1.39 1.97 82 1010010
1.42 2.01 83 1010011
1.45 2.06 84 1010100
1.49 2.10 85 1010101
1.52 2.16 86 1010110
1.56 2.21 87 1010111
PROGRAMMED Q PROGRAM CODE
MODES
1,3,4
MODE
2N Q6Q5Q4Q3Q2Q1Q0
1.60 2.26 88 1 0 1 1 0 0 0
1.64 2.32 89 1 0 1 1 0 0 1
1.68 2.40 90 1 0 1 1 0 1 0
1.73 2.45 91 1 0 1 1 0 1 1
1.78 2.51 92 1 0 1 1 1 0 0
1.83 2.59 93 1 0 1 1 1 0 1
1.88 2.66 94 1 0 1 1 1 1 0
1.94 2.74 95 1 0 1 1 1 1 1
2.00 2.83 96 1 1 0 0 0 0 0
2.06 2.92 97 1 1 0 0 0 0 1
2.13 3.02 98 1 1 0 0 0 1 0
2.21 3.12 99 1 1 0 0 0 1 1
2.29 3.23 100 1 1 0 0 1 0 0
2.37 3.35 101 1 1 0 0 1 0 1
2.46 3.48 102 1 1 0 0 1 1 0
2.56 3.62 103 1 1 0 0 1 1 1
2.67 3.77 104 1 1 0 1 0 0 0
2.78 3.96 105 1 1 0 1 0 0 1
2.91 4.11 106 1 1 0 1 0 1 0
3.05 4.31 107 1 1 0 1 0 1 1
3.20 4.53 108 1 1 0 1 1 0 0
3.37 4.76 109 1 1 0 1 1 0 1
3.56 5.03 110 1 1 0 1 1 1 0
3.76 5.32 111 1 1 0 1 1 1 1
4.00 5.66 112 1 1 1 0 0 0 0
4.27 6.03 113 1 1 1 0 0 0 1
4.57 6.46 114 1 1 1 0 0 1 0
4.92 6.96 115 1 1 1 0 0 1 1
5.33 7.54 116 1 1 1 0 1 0 0
5.82 8.23 117 1 1 1 0 1 0 1
6.40 9.05 118 1 1 1 0 1 1 0
7.11 10.1 119 1 1 1 0 1 1 1
8.00 11.3 120 1 1 1 1 0 0 0
9.14 12.9 121 1 1 1 1 0 0 1
10.7 15.1 122 1 1 1 1 0 1 0
12.8 18.1 123 1 1 1 1 0 1 1
16.0 22.6 124 1 1 1 1 1 0 0
21.3 30.2 125 1 1 1 1 1 0 1
32.0 45.3 126 1 1 1 1 1 1 0
64.0 90.5 127 1 1 1 1 1 1 1
Table 3. Q Program Selection Table (continued)
Notes 5) In modes 1, 3, and 4: Q = 64 / (128 - N)
6) In mode 2, the listed Q values are those of mode 1 multiplied by √2. Then Q = 90.51 / (128 - N)
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 15
the digital lines should be buffered from the device by
logic gates as shown in Figure 6.
Shutdown Mode
The MAX260/MAX261/MAX262 enters a shutdown/
standby mode when all zeroes are written to the Q
addresses of filter A (Q0A–Q6A). When shut down,
power consumption with ±5V supplies typically drops
to 10mW. When reactivating the filter after shutdown,
allow 2ms to return to full operation.
Filter Operating Modes
There are several ways in which the summing amplifier
and integrators in each MAX260/MAX261/MAX262 filter
section can be configured. The four most versatile
interconnections (modes) are selected by writing to
inputs M0 and M1 (see Tables 4 and 5). These modes
use no external components. A fifth mode, 3A, makes
use of an additional op amp (included in the MAX261
and MAX262) and external resistors, but uses the same
internal configuration and is selected with the same
programming code, as mode 3.
FILTER B
CLK
OUT
12
CLKB
fCLK = 0.45
RC
8
OSC
OUT
19(18)*
C
R
11
CLKA
FILTER A
FILTER B
CLK
OUT CLKB
OSC
OUT
CLKA
FILTER A
12
8
19(18)*
11
CRYSTAL
*OSC OUT IS PIN 18 ON MAX261/MAX262
FILTER B
CLK
OUT
12
CLKB
OSC
OUT
N.C.
11
CLKA
FILTER A
N.C.
EXTERNAL CLOCK IN
(ANY DUTY CYCLE)
Figure 4. Clock Input Connections
DATA BIT ADDRESS
D0 D1 A3 A2 A1 A0 LOCATION
FILTER A
M0AM1A0000 0
F0AF1A0001 1
F2AF3A0010 2
F4AF5A0011 3
Q0AQ1A0100 4
Q2AQ3A0101 5
Q4AQ5A0110 6
Q6A0111 7
FILTER B
M0BM1B1000 8
F0BF1B1001 9
F2BF3B1010 10
F4BF5B1011 11
Q0BQ1B1100 12
Q2BQ3B1101 13
Q4BQ5B1110 14
Q6B1111 15
Table 4. Program Address Locations
Note: Writing 0 into Q0A–Q6A (address locations 4–7) on filter
A activates shutdown mode. BOTH filter sections deactivate.
D0, D1
WR
VALID DATA
tDS tDH
tWR
VALID ADDRESS
tAS
A0–A3
SEE INTERFACE SPECIFICATIONS FOR TIMING LIMITS
tAH
Figure 5. Interface Timing
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
16 ______________________________________________________________________________________
Figures 7 through 11 show symbolic representations of
the MAX260 filter modes. Only one second-order sec-
tion is shown in each case. The A and B sections of
one MAX260/MAX261/MAX262 can be programmed for
different modes if desired. The f0, fN(notch), Q, and
various output gains in each case are shown in Table 5.
Filter Mode Selection
MODE 1 (Figure 7) is useful when implementing allpole
lowpass and bandpass filters such as Butterworth,
Chebyshev, Basset, etc. It can also be used for notch
filters, but only second-order notches because the rela-
tive pole and zero locations are fixed. Higher order
notch filters require more latitude in f0and 1N, which is
why they are more easily implemented with mode 3A.
1D
3
4
7
8
13
14
2D
3D
4D
6D
WR
5D
1Q
2Q
3Q
20
OCTAL D FLIP-FLOP
74HC374
VCC
5Q
6Q
4Q
A0
A1
A2
D1
D2
A3
2
5
6
12
15
11011
-5V
9
OC CKGND
MAX260
MAX261
MAX262
A0
A1
A2
A3
D2
D1
+5V
V+
-5V
V-
GND
WR
Figure 6. Buffering/Latching Logic Inputs
SCN
IN
SCN NBP
LP
+
-
-
MODE 1
+
-∫ ∫
SCN
Σ
SCN = SWITCHED-CAPACITOR NETWORK
Figure 7. Filter Mode 1: Second-Order Bandpass, Lowpass,
and Notch
MODE M1,
M0
FILTER
FUNCTIONS f0Qf
NHOLP HOBP HON1
(f ➝ 0)
HON2
(f ➝ fCLK/4) OTHER
1 0, 0 LP, BP, N f0-1 -Q -1 -1
2 0, 1 LP, BP, N f0√2-0.5 -Q/√2-0.5 -1
3 1, 0 LP, BP, HP -1 -Q HOHP = -1
-1 -Q HOHP = -1
4 1, 1 LP, BP, AP
SEE TABLE 2
SEE TABLE 3
-2 -2Q HOAP = -1
fZ = f0, QZ = Q
Table 5. Filter Modes for Second-Order Functions
Notes: f0= Center Frequency
fN= Notch Frequency
HOLP = Lowpass Gain at DC
HOBP = Bandpass Gain at f0
HOHP = Highpass Gain as f approaches fCLK/4
HON1 = Notch Gain as f approaches DC
HON2 = Notch Gain as f approaches fCLK/4
HOAP = Allpass Gain
fz, Qz= f and Q of Complex Pole Pair
+R
R
G
H
+R
R
G
L
fR
R
H
L
0
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 17
Mode 1, along with mode 4, supports the highest clock
frequencies (see Table 1) because the input summing
amplifier is outside the filter’s resonant loop (Figure 7).
The gain of the lowpass and notch outputs is 1, while
the bandpass gain at the center frequency is Q. For
bandpass gains other than Q, the filter input or output
can be scaled by a resistive divider or op amp.
MODE 2 (Figure 8) is used for all-pole lowpass and
bandpass filters. Key advantages compared to mode 1
are higher available Qs (see Table 3) and lower output
noise. Mode 2’s available fCLK/f0ratios are √2less than
with mode 1 (see Table 2), so a wider overall range of
f0s can be selected from a single clock when both
modes are used together. This is demonstrated in the
Wide Passband Chebyshev Bandpass design example.
MODE 3 (Figure 9) is the only mode that produces
high-pass filters. The maximum clock frequency is
somewhat less than with mode 1 (see Table 1).
MODE 3A (Figure 10) uses a separate op amp to sum
the highpass and lowpass outputs of mode 3, creating
a separate notch output. This output allows the notch to
be set independently of f0by adjusting the op amp’s
feedback resistor ratio (RH, RL). RH, RL, and RGare
external resistors. Because the notch can be indepen-
dently set, mode 3A is also useful when designing
pole-zero filters such as elliptics.
MODE 4 (Figure 11) is the only mode that provides an
allpass output. This is useful when implementing group
delay equalization. In addition to this, mode 4 can also
be used in all pole lowpass and bandpass filters. Along
with mode 1, it is the fastest operating mode for the fil-
ter, although the gains are different than in mode 1.
When the allpass function is used, note that some
amplitude peaking occurs (approximately 0.3dB when
Q = 8) at f0. Also note that f0and Q sampling errors are
highest in mode 4 (see Figure 20).
SCN
IN
SCN NBP
LP
+
-
-
MODE 2
+
-∫ ∫
SCN
SCN
Σ
Figure 8. Filter Mode 2: Second-Order Bandpass, Lowpass,
and Notch
SCN
IN
SCN HP BP
LP
+
-
-
MODE 3
+
-∫ ∫
SCN
SCN
Σ
SCN = SWITCHED-CAPACITOR NETWORK
Figure 9. Filter Mode 3: Second-Order Bandpass, Lowpass,
and Highpass
SCN
IN
SCN HP
RG
RH
RL
BP
LP
+
-
-
MODE 3A
N
+
-
+
-
∫ ∫
SCN
SCN
Σ
SCN = SWITCHED-CAPACITOR NETWORK
Figure 10. Filter Mode 3a: Second-Order Bandpass, Lowpass,
Highpass, and Notch. For elliptic LP, BP, HP, and Notch, the N
output is used.
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
18 ______________________________________________________________________________________
Description of Filter Functions
BANDPASS (Figure 12)
For all pole bandpass and lowpass filters (Butterworth,
Bessel, Chebyshev) use mode 1 if possible. If appropri-
ate fCLK/f0or Q values are not available in mode 1,
mode 2 provides a selection that is closer to the
required values. Mode 1, however, has the highest
bandwidth (see Table 1). For pole-zero filters, such as
elliptics, see mode 3A.
HOBP = Bandpass output gain at ω= ωo
f0= ω0 / 2π= The center frequency of the complex
pole pair. Input-output phase shift is -180°at f0.
Q = The quality factor of the complex pole pair.
Also the ratio of f0to -3dB bandwidth of the
second-order bandpass response.
LOWPASS See bandpass text. (Figure 13)
HOLP = Lowpass output gain at DC
f0= ω0 / 2π
HIGHPASS (Figure 14)
Mode 3 is the only mode with a highpass output. It
works for all pole filter types such as Butterworth,
Bessel and Chebyshev. Use mode 3A for filters
employing both poles and zeros, such as elliptics.
HOHP = Highpass output gain as f approaches fCLK/4
f0= ω0 / 2π
NOTCH (Figure 15)
Mode 3A is recommended for multi-pole notch filters. In
second-order filters, mode 1 can also be used. The
advantages of mode 1 are higher bandwidth, com-
pared to mode 3 (higher fNcan be implemented), and
no need for external components as required in mode
3A.
HON2 = Notch output gain as f approaches fCLK/4
HON1 = Notch output gain as f approaches DC
fn= ωn / 2π
ALLPASS
Mode 4 is the only configuration in which an allpass
function can be realized.
Gs H s
ss Q
ON n
oo
()
( / )
=+
++
2
2
2
2
2
ω
ωω
Gs H s
ss Q
OHP
oo
()
( / )
=++
2
22ωω
Gs H
ss Q
OLP o
oo
()
( / )
=++
ω
ωω
2
2
2
Gs H sQ
ss Q
OBP o
oo
() ( / )
( / )
=++
ω
ωω
22
SCN
IN
SCN AP
LP
+
-
-
MODE 4
BP
+
-∫ ∫
SCN
Σ
SCN = SWITCHED-CAPACITOR NETWORK
Figure 11. Filter Mode 4: Second-Order Bandpass, Lowpass,
and Allpass
fLfOfH
HOBP
0.707 HOBP
BANDPASS OUTPUT
f(LOG SCALE)
GAIN (V/V)
Figure 12. Second-Order Bandpass Characteristics
Qf
ff
f
ff
QQ
ff
QQ
O
HL
Off
LO
HO
LH
,
=−
=−+
+
=+
+
=
1
2
1
21
1
2
1
21
2
2
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 19
HOAP = Allpass output gain for DC < f < fCLK / 4
f0= ω0 / 2π
Filter Design Procedure
The procedure for most filter designs is to first convert
the required frequency response specifications to f0s
and Qs for the appropriate number of second-order
sections that implement the filter. This can be done by
using design equations or tables in available liter-
ature, or can be conveniently calculated using Maxim's
filter design software. Once the f0s and Qs have been
found, the next step is to turn them into the digital pro-
gram coefficients required by the MAX260/MAX261/
MAX262. An operating mode and clock frequency (or
clock/center frequency ratio) must also be selected.
Next, if the sample rate (fCLK/2) is low enough to cause
significant errors, the selected f0s and Qs should be
corrected to account for sampling effects by using
Figure 20 or Maxim's design software. In most cases,
the sampling errors are small enough to require no cor-
rection, i.e., less than 1%. In any case, with or without
correction, the required f0s and Qs can then be select-
ed from Tables 2 and 3. Maxim's filter design software
Gs H ssQ
ss Q
OAP oo
oo
() ( / )
( / )
=−+
++
2
2
2
2
ωω
ωω
fPfC
HOP
0.707 HOLP
HOLP
LOWPASS OUTPUT
f(LOG SCALE)
GAIN (V/V)
Figure 13. Second-Order Lowpass Characteristics
ffX QQ
fp f Q
HHX
QQ
CO
O
OP OLP
=
+
+
=
=
−−
−
−
11
211
21
11
2
1
111
4
22
2
2
2
fCfP
HOP
0.707 HOHP
HOHP
HIGHPASS OUTPUT
f(LOG SCALE)
GAIN (V/V)
Figure 14. Second-Order Highpass Characteristics
ffX QQ
fp f Q
HHX
QQ
CO
O
OP OHP
=
+
+
=
=
−−
−
−
11
211
21
11
2
1
111
4
22
2
2
2
f(LOG SCALE)
GAIN (V/V)
fN
HON1
HON
HON2
Figure 15. Second-Order Notch Characteristics
TOTAL SECTIONS TOTAL B.W. TOTAL Q
1 1.000 B 1.00 Q
2 0.644 B 1.55 Q
3 0.510 B 1.96 Q
4 0.435 B 2.30 Q
5 0.386 B 2.60 Q
Table 6. Cascading Identical Bandpass
Filter Sections
Note: B = individual stage bandwidth, Q = individual
stage Q.
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
20 ______________________________________________________________________________________
can also perform this last step. The desired f0s and Qs
are stated, and the appropriate digital coefficients are
supplied.
Cascading Filters
In some designs, such as very narrow band filters, sev-
eral second-order sections with identical center fre-
quency can be cascaded. The total Q of the resultant
filter is:
Q is the Q of each individual filter section, and N is the
number of sections. In Table 6, the total Q and band-
width are listed for up to five identical second-order
sections. B is the bandwidth of each section.
In high-order bandpass filters, stages with different f0s
and Qs are also often cascaded. When this happens,
the overall filter gain at the bandpass center frequency
is not simply the product of the individual gains
because f0, the frequency where each sections gain is
specified, is different for each second-order section.
The gain of each section at the cascaded filter's center
frequency must be determined to obtain the total gain.
For all-pole filters the gain, H(f0), as each second-order
section's f0is divided by an adjustment factor, G, to
obtain that section's gain, H(f0BP), at the overall center
frequency:
H1(f0BP) = H(f01) / G1= Section 1’s Gain at f0BP
where F1= f01 / fOBP
G1, Q1, and f01 are the gain adjustment factor, Q, and
f0for the first of the cascaded second-order sections.
The gain of the other sections (2, 3, etc.) at f0BP is
determined the same way. The overall gain is:
H(f0Bp) = H1(f0BP) x H2(f0BP) x etc.
For cascaded filters with zeros (fZ) such as elliptics, the
gain adjustment factor for each stage is:
where F1Z = fz1 / f0BP, and F1is the same as above.
Application Hints
Power Supplies
The MAX260/MAX261/MAX262 can be operated with a
variety of power supply configurations, including +5V to
+12V single supply or ±2.5V to ±5V dual supplies.
When a single supply is used, V-is connected to sys-
tem ground and the filter's GND pin should be biased
at V+/2. The input signal is then either capacitively cou-
pled to the filter input or biased to V+/2. Figure 16
shows circuit connections for single-supply operation.
When power supplies other than ±5V are used, CMOS
input logic levels (HIGH = V+, LOW = GND or V-) are
required for WR, D0, D1, A0–A3, OLKA, and CLKB.
With ±5V supplies, either TTL or CMOS levels can be
used. Note, however, that power consumption at ±5V is
reduced if CLKAand CLKBare driven with ±5V, rather
than TTL or 0 to 5V levels. Operation with +5V or ±2.5V
power lowers power consumption, but also reduces
bandwidth by approximately 25% compared to +12V or
±5V supplies.
Best performance is achieved if V+and V-are bypassed
to ground with 4.7µF electrolytic (Tantalum is preferred.)
and 0.1µF ceramic capacitors. These should be located
as close to the supply pins as possible. The lead length
of the bypass capacitors should be shortest at the V+
and V-pins. When using a single supply, V+and GND
should be bypassed to V-as shown in Figure 16.
Output Swing and Clipping
MAX260/MAX261/MAX262 outputs are designed to
drive 10kΩloads. For the MAX261 and MAX262, all fil-
ter outputs swing to within 0.15V of each supply rail
with a 10kΩload. In the MAX260 only, an internal sam-
ple-hold circuit reduces voltage swing at the N/HP/AP
output compared to LP and BR. N/HP/AP, therefore,
swings to within 1V (10kΩload) of either rail on the
MAX260.
To ensure that the outputs are not driven beyond their
maximum range (output clipping), the peak amplitude
response, individual section gains (HOBP, HOLP,
HOHP), input signal level, and filter offset voltages must
be carefully considered. It is especially important to
check unused outputs for clipping (i.e., the lowpass
output in a bandpass hookup), because overload at
any filter stage severely distorts the overall response.
The maximum signal swing with ±4.75V supplies and a
1.0V filter offset is approximately ±3.5V.
For example, lets assume a fourth-order lowpass filter is
being implemented with a Q of 2 using mode 1. With a
single 5V supply (i.e., ±2.5V with respect to chip GND)
the maximum output signal is ±2V (w.r.t. GND). Since in
G
QF F F F Q
FF
Z
Z
1
11
21
21
2211
212
1
21
2
1
1
( ) ( / )
/
=−
−+
−
G
QF F Q
F
1
11
2211
212
1
1
( ) ( / ) /
=−+
Total Q Q
TN
/
=
−
()
21
1
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 21
mode 1 the maximum signal is 0 times the input signal,
the input should not exceed ±(2/Q)V, or ±1V in this case.
Clock Feedthrough and Noise
Typical wideband noise for MAX260 series devices is
0.5mVP-P from DC to 100kHz. The noise is virtually
independent of clock frequency. In multistage filters,
the section with the highest Q should be placed first for
lower output noise.
The output waveform of the MAX260 series and other
switched capacitor filters appears as a sampled signal
with stepping or “staircasing” of the output waveform
occurring at the internal sample rate (fCLK/2). This step-
ping, if objectionable, can be removed by adding a sin-
gle-pole AC filter. With no input signal, clock-related
feedthrough is approximately 8mVP-P. This can also be
attenuated with an RC-smoothing filter as shown with
the MAX261 in Figure 17.
Some noise also can be generated at the filter outputs
by transitions at the logic inputs. If this is objectionable,
the digital lines should be buffered from the device by
logic gates as shown in Figure 6.
Input Impedance
The input to each filter is the switched capacitor circuit
shown in Figure 18. In the MAX260, the input capacitor
charges to the input voltage VIN during the first half
clock cycle. During the second half-cycle, its charge is
transferred to the feedback capacitor. The resultant
input impedance can be approximated by:
RIN = 1 / (CINfCLK / 2) = 2 / (CINfCLK).
CIN is around 12pF, hence, for a clock frequency of
500kHz, RIN = 333kΩ. The input also has about 5pF of
fixed capacitance to ground.
The MAX261/MAX262 input structure is shown in Figure
19. Here CA= 12pF and CB= 0.016pF and only CBis
switched, so the input resistance is 750 times larger
compared to the MAX260 (RIN = 250MΩ). The
MAX261/MAX262 have a fixed capacitance of approxi-
mately 5pF to ground.
f0and Q at Low Sample Rates
When low fCLK/f0ratios and low Q settings are select-
ed, deviation from ideal continuous filter response can
be noticeable in some designs. This is due to interac-
tion between Q and f0at low fCLK/f0ratios and Qs. The
data in Figure 20 quantifies these differences. Since the
MAX260
MAX261
MAX262
WR
A0–A3
D0, D1
INA
OR
INB
CMOS
LOGIC
LEVELS
V+
V-
GND
0.1µF0.1µF
+5V
4.7µF
4.7kΩ
4.7kΩ
NOTE: OP-AMP LEVEL SHIFT CIRCUIT HAS A GAIN OF 0.5 FROM V*.
VIN
VIN
TO V+
TO GND PIN
2.5kΩ
7.5kΩ
10kΩ
10kΩ
+
-
SEE
NOTE
VIN
4.7µF
5V
0V
5V
0V
ANY DC
0V
Figure 16. Power Supply and Input Connections for Single Supply Operation
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
22 ______________________________________________________________________________________
errors are predictable, the graphs can be used to cor-
rect the selected f0and Q so that the actual realized
parameters are on target. These predicted errors are
not unique to MAX260 series devices and, in fact,
occur with all types of sampled filters. Consequently,
these corrections can be applied to other switched
capacitor filters. In the majority of cases, the errors are
not significant, i.e., less than 1%, and correction is not
needed. However, the MAX262 does employ a lower
range of fCLK/f0ratios than the MAX260 or MAX261 and
is more prone to sampling errors, as the tables show.
Maxim's filter design software applies the previous cor-
rections automatically as a function of desired fCLK/f0,
and Q. Therefore, Figure 20 should not be used when
Maxim's software determines f0and Q. This results in
overcompensation of the sampling errors since the cor-
rection factors are then counted twice.
The data plotted in Figure 20 applies for modes 1 and
3. When using Figure 20 for mode 4, the f0error
obtained from the graph should be multiplied by 1.5
and the Q error should be multiplied by 3.0. In mode 2,
the value of fCLK/f0should be multiplied by √2and the
programmed Q should be divided by √2before using
the graphs.
As with all sampled systems, frequency components of
the input signal above one half the sampling rate are
aliased. In particular, input signal components near the
sampling rate generate difference frequencies that
often fall within the passband of the filter. Such aliased
signals, when they appear at the output, are indistin-
guishable from real input information. For example, the
aliased output signal generated when a 99kHz wave-
form is applied to a filter sampling at 100kHz (fCLK =
200kHz) is 1kHz. This waveform is an attenuated ver-
sion of the output that would result from a true 1kHz
input. Remember that, with the MAX260 series filters,
the nyquist rate (one half the sample rate) is in fact
fCLK/4, because fCLK is internally divided by two.
A simple, passive RC lowpass input filter is usually suf-
ficient to remove input frequencies that can cause
aliasing. In many cases, the input signal itself may be
band limited and require no special anti-alias filtering.
The wideband MAX262 uses lower fCLK/f0ratios than
the MAX260/MAX261 and, for this reason, is more likely
to require input filtering than the MAX260 or MAX281.
Trimming DC Offset
The DC offset voltage at the LP or notch output can be
adjusted with the circuit in Figure 21. This circuit also
uses the input op amp to implement a single-pole anti-
alias filter. Note that the total offset is generally less in
multistage filters than when only one section is used,
MAX261
INABPA
TRACE A
500kHz TTL
TRACE B
OV
OV
OV
A 1V/DIV
B 5mV/DIV
C mV/DIV
1µs/div
TRACE C
C, 1000pF
R, 10kΩ
CLKA
Figure 17. MAX261 Bandpass Output Clock Noise
VIN
CFB
CIN
12pF
~5pF
+
-
fCLK
2
2
CIN fCLK
RIN =
Figure 18. MAX260 Input Model
VIN
CFB
CA 12pF
CB
0.016pF
~5pF +
-
fCLK
2
2
750 CA fCLK
RIN =
Figure 19. MAX261/MAX262 Input Model
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 23
since each offset is typical negative and each section
inverts. When the HP or BP outputs are used, the offset
can be removed with capacitor coupling.
Design Examples
Fourth-Order Chebyshev Bandpass Filter
Figure 22 shows both halves of a MAX260 cascaded to
form a fourth-order Chebyshev bandpass filter. The
desired parameters are:
Center frequency (f0) = 1kHz
Pass bandwidth = 200Hz
Stop bandwidth = 600Hz
Max passband ripple = 0.5dB
Min stopband attenuation = 15dB
From the previous parameters, the order (number of
poles) and the f0and Q of each section can be deter-
mined. Such a derivation is beyond the scope of this
data sheet; however, there are a number of sources
that provide design data for this procedure. These
include look-up tables, design texts, and computer pro-
grams. Design software is available from Maxim to pro-
vide comprehensive solutions for most popular filter
configurations. The A and B section parameters for the
above filter are:
f0A = 904Hz f0B = 1106Hz
QA= 7.05 QB= 7.05
To implement this filter, both halves operate in mode 1
and use the same clock. See Tables 2 and 3. The pro-
grammed parameters are:
CLKA= CLKB= 150kHz
fCLK/f0A = 166.50 (Mode 1, N = 42), actual f0A = 902.4Hz
fCLK/f0B = 136.66 (Mode 1, N = 23), actual f0B =
1099.7Hz
QA= QB= 7.11 (Mode 1, N = 119)
Sampling errors are very small at this fCLK/f0ratio, so
the actual realized Q is very close to 7.05 (see Figure
20 or program MPP in the Filter Design Software sec-
tion). Often the realized Q is not exactly the target value
at high Qs because programming resolution lowers as
Q increases. This does not affect most filter designs,
since three-digit Q accuracy is practically never
required, and a Q resolution of 1 is provided up to Qs
of 10. The overall filter gain at f0is 16.4V/V or 24.3dB
(see the Cascading Filters section). If another gain is
required, amplification or attenuation must be added at
the input, output, or between stages.
0
4
2
8
6
12
10
14
18
16
20
40 80 10060 120 140 160 180 200
fO ERROR vs. fCLK/fO RATIO (MODE 1, 3)
fCLK/fO RATIO
fO ERROR (%)
Q = 0.512
f0 ERROR IS PLOTTED FOR MODES 1 AND 3
MODE 2: MULTIPLY ICLKIO BY √2 and
DIVIDE Q BY √2 BEFORE USING GRAPH
MODE 4: MUTIPLY fO ERROR BY 1.5
Q = 0.512
Q = 0.512
Q = 0.512
Q = 0.512
Q = 0.512
0
-2
-1
-4
-3
-5
-6
-7
40 80 10060 120 140 160 180 200
Q ERROR vs. fCLK/fO RATIO
fCLK/fO RATIO
Q ERROR (%)
Q = 0.5
Q ERROR IS PLOTTED FOR MODES 1 AND 3
MODE 2: MULTIPLY fCLK/fO BY √2 and
DIVIDE Q BY √2 BEFORE USING GRAPH
MODE 4: MUTIPLY Q ERROR BY 1.5
Q = 0.83
Q = 7.11
Q = 3.05
Q = 0.6
Q = 1.21
Figure 20. Sampling Errors in fCLK/f0and Q at Low fCLK/f0and
Q Settings
R2 100kΩ
R3 270kΩ
VIN
+5V
-5V
OFFSET
TRIM
TO
FILTER
INPUT
100kΩ+
-
R1 100kΩ
C1
NOTE: OP AMP INCLUDED WITH MAX261/MAX262
GAIN = -R1/R2
fLP =1
2πR1C2
Figure 21. Circuit for DC Offset Adjustment
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
24 ______________________________________________________________________________________
In Figure 23, a series of response curves are shown for
the previous configuration using a MAX261 with clock
frequencies ranging from 750kHz to 4MHz (f0from
500Hz to 30kHz). Note that the rightmost curve shows
about 2dB of gain peaking compared to the lower fre-
quency curves, indicating the upper limit of usable filter
accuracy at this Q (see Table 1).
Wide Passband Chebyshev Bandpass
In this example (Figure 24), the desired parameters
are:
Center frequency (f0) = 1kHz
Pass bandwidth = 1kHz
Stop bandwidth = 3kHz
Max passband ripple = 1dB
Min stopband attenuation = 20dB
From the previous parameters, we use either lookup
tables, design texts, or Maxim's filter design programs
to generate the order (number of poles), and the f0and
Q of each second-order section. The A and B parame-
ters are:
f0A = 639Hz f0B = 1564Hz
QA= 2.01 QB= 2.01
To implement this filter, section A operates in mode 1
and section B uses mode 2 to provide a wider overall
range of fCLK/f0ratios. This way, one clock frequency
can drive both sections A and B. See Tables 2 and 3.
CLKA= CLKB= 120kHz
fCLK/f0A = 188.49 (Mode 1, N = 56), actual f0A = 636.6Hz
fCLK/f0B = 76.64 (Mode 2, N = 5), actual f0B = 156.5Hz
QA= 2.000 (Mode 1, N = 96), QB= 2.01 (Mode 2, N =
83)
The overall passband gain at f0is 0.64V/V or
-3.9dB.
High-Frequency Chebyshev Bandpass
The same Chebyshev response shape shown in Figure
24 is implemented at higher frequencies with a
MAX262 in Figure 25. The curves show plots for center
frequencies of 15.6kHz, 31.3kHz, and 47kHz. Not only
is this faster than the MAX260 implementation, but
mode 1 can be used in both halves of the MAX262 for
this filter because the range of available fCLK/f0ratios is
wider with the MAX262 than the MAX260.
51
11 12
23 21
MAX260
VIN
INABPA
CLKA
CLK PROGRAM
CLKB
INBBPB
WR, AX, DX
VOUT
40
-60
200 2K1K500 20K10K5K
-35
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEGREES)
-10
15
-180
180
90
0
-90
GAIN
PHASE
Figure 22. Fourth-Order Chebyshev Bandpass Filter
CLKA,B MODE fOA fOB QAQB
150kHz 1 N = 42 N = 23 N = 119 N = 119
30
-30
1K 10K5K2K 100K50K20K
-15
FREQUENCY (Hz)
GAIN (dB)
0
15
Figure 23. MAX261 Fourth-Order Chebyshev Bandpass Using
Coefficients of Figure 22
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
______________________________________________________________________________________ 25
Fourth-Order Butterworth Lowpass
Figure 26 shows a fourth-order Butterworth lowpass
with a cutoff frequency of 3kHz. Sections A and B of a
MAX260 are cascaded. The f0and Q parameters for
each section are:
f0A = 3kHz f0B = 3kHz
QA= 1.307 QB= 0.541
Mode 1 and a 400kHz clock are used. Because of low
Q values, the sampling errors of Figure 20 begin to look
significant in this case. From the graphs, using fCLK/f0
ratio near 133, f0A is about 4% high, f0B is 1.5% high,
QAis -1.2% low, and QBis -0.5% low. If these errors
are not a problem, the corrections can be ignored.
They are included here for best possible accuracy:
CLKA= CLKB= 400kHz
fCLK/f0A = 135.08 (N = 22), f0B = 2961Hz
(-1.3% correction)
fCLK/f0B = 139.80 (N = 25), f0A = 2861Hz
(-4.6% correction)
QA= 1.306 (N = 79, Q resolution prevents +0.5%
correction)
QB= 0.547 (N = 11 +1.1% correction)
Measured wideband noise for this filter is 123µV RMS.
If mode 2 were used, the noise would be 87µV RMS.
For lower noise with either mode, the first section
should have the highest Q (section A in this example).
51
11 12
23 21
MAX260
VIN
INABPA
CLKA
CLK PROGRAM
CLKB
INBBPB
WR, AX, DX
VOUT
10
-70
100 1K500200 10K5K2K
-50
FREQUENCY (Hz)
GAIN (dB)
-30
-10
-180
180
90
PHASE (DEGREES)
0
-90
GAIN
PHASE
Figure 24. Wide Passband Chebyshev Bandpass Filter
CLKA,B MODEAMODEBfOA fOB QAQB
120kHz 1 2 N = 56 N = 5 N = 96 N = 83
51
11 12
23 21
MAX262
VIN
INABPA
CLKA
CLK PROGRAM
CLKB
INBBPB
WR, AX, DX
VOUT
0
-50
1K 10K5K2K 100K50K20K
-40
-30
FREQUENCY (Hz)
GAIN (dB)
-20
-10
fO = 15.6kHz
fCLK = 1MHz
fO = 31.3kHz
fCLK = 2MHz
fO = 47kHz
fCLK = 3MHz
Figure 25. High-Frequency Chebyshev Bandpass Filter
CLKA,B MODE fOA fOB QA QB
1 to 3MHz 1 N = 38 N = 0 N = 96 N = 96
MAX260/MAX261/MAX262
Microprocessor Programmable
Universal Active Filters
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Ordering Information (continued)
PART TEMP RANGE PACKAGE A C C U R A C Y
MAX261ACNG 0°C to +70°C Plastic DIP 1%
MAX261BCNG 0°C to +70°C Plastic DIP 2%
MAX261AENG -40°C to +85°C Plastic DIP 1%
MAX261BENG -40°C to +85°C Plastic DIP 2%
MAX261ACWG 0°C to +70°C Wide SO 1%
MAX261BCWG 0°C to +70°C Wide SO 2%
MAX261AMRG -55°C to +125°C CERDIP 1%
MAX261BMRG -55°C to +125°C CERDIP 2%
MAX262ACNG 0°C to +70°C Plastic DIP 1%
MAX262BCNG 0°C to +70°C Plastic DIP 2%
MAX262AENG -40°C to +85°C Plastic DIP 1%
MAX2G2BENG -40°C to +85°C Plastic DIP 2%
MAX262ACWG 0°C to +70°C Wide SO 1%
MAX262BCWG 0°C to +70°C Wide SO 2%
MAX262AMRG -55°C to +125°C CERDIP 1%
MAX262BMRG -55°C to +125°C CERDIP 2%
*All devices—24-pin packages 0.3in-wide packages
V+
A1
0.199in
(5.055mm)
A2
CLKACLKB
D0
CLK OUT
N.C.(OP IN)
V-
A0 WR
HPB(N.C.)
N.C.(HPA)
HPA(OP OUT)
N.C.(HPB)
BPALPAINBLPBBPB
0.128in
3.251mm
INA
D1
OSC OUT
GND
A3
NOTE: LABELS IN PARENTHESES ( ) ARE FOR MAX261/MAX262 ONLY
Chip Topography
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PRODUCTS
SOLUTIONS
DESIGN
APPNOTES
SUPPORT
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MEMBERS
MAX260
Part Number Table
Notes:
See the MAX260 QuickView Data Sheet for further information on this product family or download the MAX260
full data sheet (PDF, 952kB).
1.
Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales.2.
Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within
one business day.
3.
Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt. More: See full
data sheet or Part Naming Conventions.
4.
* Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product
uses.
5.
Part Number
Free
Sample
Buy
Direct
Package:
TYPE PINS SIZE
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free?
Materials Analysis
MAX260SOFT
RoHS/Lead-Free: No
MAX260BMRG
-55C to +125C
RoHS/Lead-Free: No
MAX260AMRG
-55C to +125C
RoHS/Lead-Free: No
MAX260BCNG+
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24+4*
0C to +70C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260ACNG+
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24+4*
0C to +70C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260ACNG
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24-4*
0C to +70C
RoHS/Lead-Free: No
Materials Analysis
MAX260BCNG
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24-4*
0C to +70C
RoHS/Lead-Free: No
Materials Analysis
MAX260AENG+
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24+4*
-40C to +85C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260BENG
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24-4*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX260BENG+
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24+4*
-40C to +85C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260AENG
PDIP;24 pin;.300"
Dwg: 21-0043D (PDF)
Use pkgcode/variation: N24-4*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX260ACWG+T
0C to +70C
RoHS/Lead-Free: Yes
MAX260BCWG+
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24+3*
0C to +70C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260ACWG+
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24+3*
0C to +70C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260ACWG-T
0C to +70C
RoHS/Lead-Free: No
MAX260BCWG+T
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24+3*
0C to +70C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260BCWG-T
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24-3*
0C to +70C
RoHS/Lead-Free: No
Materials Analysis
MAX260BCWG
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24-3*
0C to +70C
RoHS/Lead-Free: No
Materials Analysis
MAX260ACWG
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24-3*
0C to +70C
RoHS/Lead-Free: No
Materials Analysis
MAX260BEWG+
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24+3*
-40C to +85C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260AEWG+T
-40C to +85C
RoHS/Lead-Free: Yes
MAX260AEWG+
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24+3*
-40C to +85C
RoHS/Lead-Free: Yes
Materials Analysis
MAX260AEWG-T
-40C to +85C
RoHS/Lead-Free: No
MAX260AEWG
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24-3*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX260BEWG-T
-40C to +85C
RoHS/Lead-Free: No
MAX260BEWG
SOIC;24 pin;.300"
Dwg: 21-0042B (PDF)
Use pkgcode/variation: W24-3*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX260BEWG+T
-40C to +85C
RoHS/Lead-Free: Yes
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