2011-2013 Microchip Technology Inc. DS70657G-page 1
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
Operating Conditions
• 3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS
•3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS
Core: 16-Bit dsPIC33E/PIC24E CPU
• Code Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus Hardware Divide
• 32-bit multiply support
Clock Management
• 1.0% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 0.6 mA/MHz Dynamic Current (typical)
•30 µA I
PD Current (typical)
High-Speed PWM
• Up to Three PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• ADC module:
- Configurable as 10-bit, 1.1 Msps with four S&H or
12-bit, 500 ksps with one S&H
- Six analog inputs on 28-pin devices and up to
16 analog inputs on 64-pin devices
• Flexible and Independent ADC Trigger Sources
• Up to Three Op Amp/Comparators with
Direct Connection to the ADC module:
- Additional dedicated comparator
- Programmable references with 32 voltage points
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement
Timers/Output Compare/Input Capture
• 12 General Purpose Timers:
- Five 16-bit and up to two 32-bit timers/counters
- Four OC modules, configurable as timers/counters
- PTG module with two configurable timers/counters
- 32-bit Quadrature Encoder Interface (QEI) module,
configurable as a timer/counter
• Four IC modules
• Peripheral Pin Select (PPS) to allow Function Remap
• Peripheral Trigger Generator (PTG) for Scheduling
Complex Sequences
Communication Interfaces
• Two UART modules (17.5 Mbps)
- With support for LIN/J2602 protocols and IrDA®
• Two 4-Wire SPI modules (15 Mbps)
• ECAN™ module (1 Mbaud) CAN 2.0B Support
•Two I
2C™ modules (up to 1 Mbaud) with SMBus
Support
• PPS to allow Function Remap
• Programmable Cyclic Redundancy Check (CRC)
Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority Arbitration
• UART, SPI, ADC, ECAN, IC, OC and Timers
Input/Output
• Sink/Source 12 mA or 6 mA, Pin-Specific for
Standard VOH/VOL, up to 22 or 14 mA, respectively
for Non-Standard VOH1
• 5V Tolerant Pins
• Selectable Open-Drain, Pull-ups and Pull-Downs
• Up to 5 mA Overvoltage Clamp Current
• External Interrupts on All I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) Planned
• AEC-Q100 REVG (Grade 0, -40ºC to +150ºC) Planned
• Class B Safety Library, IEC 60730
Debugger Development Support
• In-Circuit and In-Application Programming
• Two Program and Two Complex Data Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
16-Bit Microcontrollers and Digital Signal Controllers
with High-Speed PWM, Op Amps and Advanced Analog
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 2 2011-2013 Microchip Technology Inc.
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X AND
PIC24EPXXXGP/MC20X PRODUCT
FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in
Table 1 (General Purpose Families) and Table 2 (Motor
Control Families). Their pinout diagrams appear on the
following pages.
TABLE 1: dsPIC33EPXXXGP50X and PIC24EPXXXGP20X GENERAL PURPOSE FAMILIES
Device
Page Erase Size (Instructions)
Program Flash Memory (Kbytes)
RAM (Kbyte)
Remappable Peripherals
I2C™
CRC Generator
10-Bit/12-Bit ADC (Channels)
Op Amps/Comparators
CTMU
PTG
I/O Pins
Pins
Packages
16-Bit/32-Bit Timers
Input Capture
Output Compare
UART
SPI(2)
ECAN™ Technology
External Interrupts(3)
PIC24EP32GP202 512 32 4
54422—32162/3
(1)Yes Yes 21 28
SPDIP,
SOIC,
SSOP(4),
QFN-S
PIC24EP64GP202 1024 64 8
PIC24EP128GP202 1024 128 16
PIC24EP256GP202 1024 256 32
PIC24EP512GP202 1024 512 48
PIC24EP32GP203 512 32 4 54422—32183/4YesYes2536VTLA
PIC24EP64GP203 1024 64 8
PIC24EP32GP204 512 32 4
54422—32193/4YesYes3544
VTLA(4),
TQFP,
QFN
PIC24EP64GP204 1024 64 8
PIC24EP128GP204 1024 128 16
PIC24EP256GP204 1024 256 32
PIC24EP512GP204 1024 512 48
PIC24EP64GP206 1024 64 8
54422—321163/4YesYes5364
TQFP,
QFN
PIC24EP128GP206 1024 128 16
PIC24EP256GP206 1024 256 32
PIC24EP512GP206 1024 512 48
dsPIC33EP32GP502 512 32 4
54422132162/3
(1)Yes Yes 21 28
SPDIP,
SOIC,
SSOP(4),
QFN-S
dsPIC33EP64GP502 1024 64 8
dsPIC33EP128GP502 1024 128 16
dsPIC33EP256GP502 1024 256 32
dsPIC33EP512GP502 1024 512 48
dsPIC33EP32GP503 512 32 4 54422132183/4YesYes2536VTLA
dsPIC33EP64GP503 1024 64 8
dsPIC33EP32GP504 512 32 4
54422132193/4YesYes3544
VTLA(4),
TQFP,
QFN
dsPIC33EP64GP504 1024 64 8
dsPIC33EP128GP504 1024 128 16
dsPIC33EP256GP504 1024 256 32
dsPIC33EP512GP504 1024 512 48
dsPIC33EP64GP506 1024 64 8
544221321163/4YesYes5364
TQFP,
QFN
dsPIC33EP128GP506 1024 128 16
dsPIC33EP256GP506 1024 256 32
dsPIC33EP512GP506 1024 512 48
Note 1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 “Op Amp/Comparator Module” for details.
2: Only SPI2 is remappable.
3: INT0 is not remappable.
4: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
2011-2013 Microchip Technology Inc. DS70657G-page 3
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X MOTOR CONTROL
FAMILIES
Device
Page Erase Size (Instructions)
Program Flash Memory (Kbytes)
RAM (Kbytes)
Remappable Peripherals
I2C™
CRC Generator
10-Bit/12-Bit ADC (Channels)
Op Amps/Comparators
CTMU
PTG
I/O Pins
Pins
Packages
16-Bit/32-Bit Timers
Input Capture
Output Compare
Motor Control PWM(4)
(Channels)
Quadrature Encoder Interface
UART
SPI(2)
ECAN™ Technology
External Interrupts(3)
PIC24EP32MC202 512 32 4
5446 122—32162/3
(1)Yes Yes 21 28
SPDIP,
SOIC,
SSOP(5),
QFN-S
PIC24EP64MC202 1024 64 8
PIC24EP128MC202 1024 128 16
PIC24EP256MC202 1024 256 32
PIC24EP512MC202 1024 512 48
PIC24EP32MC203 512 32 4 544 6 122—32183/4YesYes2536VTLA
PIC24EP64MC203 1024 64 8
PIC24EP32MC204 512 32 4
5446 122—32193/4YesYes3544
VTLA(5),
TQFP,
QFN
PIC24EP64MC204 1024 64 8
PIC24EP128MC204 1024 128 16
PIC24EP256MC204 1024 256 32
PIC24EP512MC204 1024 512 48
PIC24EP64MC206 1024 64 8
5446 122—321163/4YesYes5364
TQFP,
QFN
PIC24EP128MC206 1024 128 16
PIC24EP256MC206 1024 256 32
PIC24EP512MC206 1024 512 48
dsPIC33EP32MC202 512 32 4
5446 122—32162/3
(1)Yes Yes 21 28
SPDIP,
SOIC,
SSOP(5),
QFN-S
dsPIC33EP64MC202 1024 64 8
dsPIC33EP128MC202 1024 128 16
dsPIC33EP256MC202 1024 256 32
dsPIC33EP512MC202 1024 512 48
dsPIC33EP32MC203 512 32 4 544 6 122—32183/4YesYes2536VTLA
dsPIC33EP64MC203 1024 64 8
dsPIC33EP32MC204 512 32 4
5446 122—32193/4YesYes3544
VTLA(5),
TQFP,
QFN
dsPIC33EP64MC204 1024 64 8
dsPIC33EP128MC204 1024 128 16
dsPIC33EP256MC204 1024 256 32
dsPIC33EP512MC204 1024 512 48
dsPIC33EP64MC206 1024 64 8
5446 122—321163/4YesYes5364
TQFP,
QFN
dsPIC33EP128MC206 1024 128 16
dsPIC33EP256MC206 1024 256 32
dsPIC33EP512MC206 1024 512 48
dsPIC33EP32MC502 512 32 4
5446 122132162/3
(1)Yes Yes 21 28
SPDIP,
SOIC,
SSOP(5),
QFN-S
dsPIC33EP64MC502 1024 64 8
dsPIC33EP128MC502 1024 128 16
dsPIC33EP256MC502 1024 256 32
dsPIC33EP512MC502 1024 512 48
dsPIC33EP32MC503 512 32 4 544 6 122132183/4YesYes2536VTLA
dsPIC33EP64MC503 1024 64 8
Note 1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 “Op Amp/Comparator Module” for details.
2: Only SPI2 is remappable.
3: INT0 is not remappable.
4: Only the PWM Faults are remappable.
5: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 4 2011-2013 Microchip Technology Inc.
dsPIC33EP32MC504 512 32 4
5446 122132193/4YesYes3544
VTLA(5),
TQFP,
QFN
dsPIC33EP64MC504 1024 64 8
dsPIC33EP128MC504 1024 128 16
dsPIC33EP256MC504 1024 256 32
dsPIC33EP512MC504 1024 512 48
dsPIC33EP64MC506 1024 64 8
5446 1221321163/4YesYes5364
TQFP,
QFN
dsPIC33EP128MC506 1024 128 16
dsPIC33EP256MC506 1024 256 32
dsPIC33EP512MC506 1024 512 48
TABLE 2: dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X MOTOR CONTROL
FAMILIES (CONTINUED)
Device
Page Erase Size (Instructions)
Program Flash Memory (Kbytes)
RAM (Kbytes)
Remappable Peripherals
I2C™
CRC Generator
10-Bit/12-Bit ADC (Channels)
Op Amps/Comparators
CTMU
PTG
I/O Pins
Pins
Packages
16-Bit/32-Bit Timers
Input Capture
Output Compare
Motor Control PWM(4)
(Channels)
Quadrature Encoder Interface
UART
SPI(2)
ECAN™ Technology
External Interrupts(3)
Note 1: On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 “Op Amp/Comparator Module” for details.
2: Only SPI2 is remappable.
3: INT0 is not remappable.
4: Only the PWM Faults are remappable.
5: The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.
2011-2013 Microchip Technology Inc. DS70657G-page 5
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams
28-Pin SPDIP/SOIC/SSOP(1,2)
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O Ports”
for more information.
= Pins are up to 5V tolerant
128
227
326
425
524
623
722
821
920
10 19
11 18
12 17
13 16
14 15
PIC24EPXXXGP202
dsPIC33EPXXXGP502
MCLR AV DD
AN0/OA2OUT/RA0 AVSS
AN1/C2IN1+/RA1 RPI47/T5CK/RB15
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 RPI46/T3CK/RB14
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 RPI45/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2 RPI44/RB12
PGED1/AN5/C1IN1-/RP35/RB3 TDI/RP43/RB11
TDO/RP42/RB10
OSC1/CLKI/RA2 VCAP
OSC2/CLKO/RA3 VSS
RP36/RB4 TMS/ASDA1/SDI1/RP41/RB9
CVREF2O/RP20/T1CK/RA4 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VDD SCK1/RP39/INT0/RB7
PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6
VSS
128
227
326
425
524
623
722
821
920
10 19
11 18
12 17
13 16
14 15
PIC24EPXXXMC202
dsPIC33EPXXXMC202/502
MCLR AV DD
AN0/OA2OUT/RA0 AVSS
AN1/C2IN1+/RA1 RPI47/PWM1L/T5CK/RB15
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 RPI46/PWM1H/T3CK/RB14
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1 RPI45/PWM2L/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2 RPI44/PWM2H/RB12
PGED1/AN5/C1IN1-/RP35/RB3 TDI/RP43/PWM3L/RB11
TDO/RP42/PWM3H/RB10
OSC1/CLKI/RA2 VCAP
OSC2/CLKO/RA3 VSS
FLT32/RP36/RB4 TMS/ASDA1/SDI1/RP41/RB9
CVREF2O/RP20/T1CK/RA4 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
VDD SCK1/RP39/INT0/RB7
PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6
VSS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 6 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin QFN-S(1,2,3) = Pins are up to 5V tolerant
28 27 26 25 24 23 22
8 9 10 11 12 13 14
3
18
17
16
15
4
5
7
1
220
19
6
21
PIC24EPXXXGP202
dsPIC33EPXXXGP502
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
SCK1/RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
CVREF2O/RP20/T1CK/RA4
RP36/RB4
RPI45/CTPLS/RB13
RPI44/RB12
TDI/RP43/RB11
TDO/RP42/RB10
VCAP
VSS
TMS/ASDA1/SDI1/RP41/RB9
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
2011-2013 Microchip Technology Inc. DS70657G-page 7
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
28-Pin QFN-S(1,2,3) = Pins are up to 5V tolerant
28 27 26 25 24 23 22
8 9 10 11 12 13 14
3
18
17
16
15
4
5
7
1
220
19
6
21
PIC24EPXXXMC202
dsPIC33EPXXXMC202/502
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
SCK1/RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
CVREF2O/RP20/T1CK/RA4
FLT32/RP36/RB4
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
TDI/RP43/PWM3L/RB11
TDO/RP42/PWM3H/RB10
VCAP
VSS
TMS/ASDA1/SDI1/RP41/RB9
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 8 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued)
36-Pin VTLA(1,2,3)
1
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
7
8
9
34
35
36
16 17 18
27
26
25
= Pins are up to 5V tolerant
PIC24EP32GP203
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
RPI45/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI44/RB12
TDI/RP43/RB11
TDO/RP42/RB10
VCAP
VSS
RP56/RC8
TMS/ASDA1/SDI1/RP41/RB9
SCK1/RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
CVREF2O/RP20/T1CK/RA4
VDD
SCL2/RP36/RB4
VDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EP32GP503
PIC24EP64GP203
dsPIC33EP64GP503
2011-2013 Microchip Technology Inc. DS70657G-page 9
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
36-Pin VTLA(1,2,3) = Pins are up to 5V tolerant
1
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
7
8
9
34
35
36
16 17 18
27
26
25
PIC24EP32MC203
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
RPI45/PWM2L/CTPLS/RB13
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI44/PWM2H/RB12
TDI/RP43/PWM3L/RB11
TDO/RP42/PWM3H/RB10
VCAP
VSS
RP56/RC8
TMS/ASDA1/SDI1/RP41/RB9
SCK1/RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
CVREF2O/RP20/T1CK/RA4
VDD
FLT32/SCL2/RP36/RB4
VDD
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EP32MC203/503
PIC24EP64MC203
dsPIC33EP64MC203/503
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 10 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin TQFP(1,2) = Pins are up to 5V tolerant
44
43
42
41
40
39
38
37
36
35
34
133
232
331
430
529
628
727
826
925
10 24
11 23
12
13
14
15
16
17
18
19
20
21
22
PIC24EPXXXGP204
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8TDO/RA10
RPI45/CTPLS/RB13 PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/RC2
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
SCL2/RP36/RB4
TDI/RA7
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI44/RB12
RP43/RB11
RP42/RB10
VCAP
VSS
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF2O/SDO1/RP20/T1CK/RA4
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
dsPIC33EPXXXGP504
2011-2013 Microchip Technology Inc. DS70657G-page 11
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin TQFP(1,2) = Pins are up to 5V tolerant
44
43
42
41
40
39
38
37
36
35
34
133
232
331
430
529
628
727
826
925
10 24
11 23
12
13
14
15
16
17
18
19
20
21
22
PIC24EPXXXMC204
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8TDO/RA10
RPI45/PWM2L/CTPLS/RB13 PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
FLT32/SCL2/RP36/RB4
TDI/RA7
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
RPI44/PWM2H/RB12
RP43/PWM3L/RB11
RP42/PWM3H/RB10
VCAP
VSS
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF2O/SDO1/RP20/T1CK/RA4
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
dsPIC33EPXXXMC204/504
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 12 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant
PIC24EPXXXGP204
1
12
41 40 39 38 37 36 35 34
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
13 14 15 16 17 18 19
9
10
11 22
20 21
33
32
31
424344
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/RC2
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
SCL2/RP36/RB4
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF2O/SDO1/RP20/T1CK/RA4
RPI45/CTPLS/RB13
RPI44/RB12
RP43/RB11
RP42/RB10
VCAP
VSS
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TDO/RA10
TDI/RA7
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EPXXXGP504
2011-2013 Microchip Technology Inc. DS70657G-page 13
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant
PIC24EPXXXMC204
1
12
41 40 39 38 37 36 35 34
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
13 14 15 16 17 18 19
9
10
11 2220 21
33
32
31
424344
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
FLT32/SCL2/RP36/RB4
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF2O/SDO1/RP20/T1CK/RA4
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
RP43/PWM3L/RB11
RP42/PWM3H/RB10
VCAP
VSS
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TDO/RA10
TDI/RA7
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EPXXXMC204/504
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 14 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin QFN(1,2,3) = Pins are up to 5V tolerant
44 43 42 41 40 39 38 37 36 35
12 13 14 15 16 17 18 19 20 21
3
30
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
232
31
6
22
33
34
PIC24EPXXXGP204
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/RC2
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
SCL2/RP36/RB4
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF2O/SDO1/RP20/T1CK/RA4
RPI45/CTPLS/RB13
RPI44/RB12
RP43/RB11
RP42/RB10
VCAP
VSS
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TDO/RA10
TDI/RA7
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
dsPIC33EPXXXGP504
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
2011-2013 Microchip Technology Inc. DS70657G-page 15
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin QFN(1,2,3) = Pins are up to 5V tolerant
44 43 42 41 40 39 38 37 36 35
12 13 14 15 16 17 18 19 20 21
3
30
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
232
31
6
22
33
34
PIC24EPXXXMC204
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
VDD
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
FLT32/SCL2/RP36/RB4
TCK/CVREF1O/ASCL1/RP40/T4CK/RB8
RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF2O/SDO1/RP20/T1CK/RA4
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
RP43/PWM3L/RB11
RP42/PWM3H/RB10
VCAP
VSS
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TDO/RA10
TDI/RA7
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AVSS
AVDD
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
dsPIC33EPXXXMC204/504
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 16 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
148
247
346
445
544
643
742
841
940
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TDI/RA7
RPI46/T3CK/RB14
RPI47/T5CK/RB15
RP118/RG6
RPI119/RG7
RP120/RG8
MCLR
RPI121/RG9
V
SS
V
DD
AN10/RPI28/RA12
AN9/RPI27/RA11
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/V
REF
-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/V
REF
+/AN3/OA1OUT/RPI33/CTED1/RB1
TDO/RA10
RPI45/CTPLS/RB13
RPI44/RB12
RP43/RB11
RP42/RB10
RP97/RF1
RPI96/RF0
V
DD
V
CAP
RP57/RC9
RD6
RD5
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TCK/CV
REF
1
O
/ASCL1/RP40/T4CK/RB8
RC13
RP39/INT0/RB7
RPI58/RC10
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
RD8
V
SS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
V
DD
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CV
REF
2
O
/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AV
DD
AV
SS
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/RC2
AN11/C1IN2-
(3)
/U1CTS/RC11
V
SS
V
DD
AN12/C2IN2-
(3)
/U2RTS/BCLK2/RE12
AN13/C3IN2-
(3)
/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
SDA2/RPI24/RA8
SCL2/RP36/RB4
dsPIC33EP64GP506
PIC24EP64GP206
PIC24EP128GP206
PIC24EP256GP206
dsPIC33EP128GP506
dsPIC33EP256GP506
dsPIC33EP512GP506
PIC24EP512GP206
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
2011-2013 Microchip Technology Inc. DS70657G-page 17
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
64-Pin TQFP(1,2,3) = Pins are up to 5V tolerant
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
148
247
346
445
544
643
742
841
940
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TDI/RA7
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
RP118/RG6
RPI119/RG7
RP120/RG8
MCLR
RPI121/RG9
V
SS
V
DD
AN10/RPI28/RA12
AN9/RPI27/RA11
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/
VREF
-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/
VREF
+/AN3/OA1OUT/RPI33/CTED1/RB1
TDO/RA10
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
RP43/PWM3L/RB11
RP42/PWM3H/RB10
RP97/RF1
RPI96/RF0
V
DD
V
CAP
RP57/RC9
RD6
RD5
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TCK/CV
REF
1
O
/ASCL1/RP40/T4CK/RB8
RC13
RP39/INT0/RB7
RPI58/RC10
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
RD8
V
SS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
V
DD
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF
2
O
/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AV
DD
AV
SS
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/
BCLK1/
FLT3/RC2
AN11/C1IN2-
(3)
/U1CTS/FLT4/RC11
V
SS
V
DD
AN12/C2IN2-
(3)
/U2RTS/BCLK2/RE12
AN13/C3IN2-
(3)
/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
SDA2/RPI24/RA8
FLT32
/SCL2/RP36/RB4
PIC24EP64MC206
dsPIC33EP64MC206/506
PIC24EP128MC206
PIC24EP256MC206
dsPIC33EP128MC206/506
dsPIC33EP256MC206/506
dsPIC33EP512MC206/506
PIC24EP512MC206
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 18 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued)
64-Pin QFN(1,2,3,4) = Pins are up to 5V tolerant
TDO/RA10
RPI45/CTPLS/RB13
RPI44/RB12
RP43/RB11
RP42/RB10
RP97/RF1
RPI96/RF0
V
DD
V
CAP
RP57/RC9
RD6
RD5
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TCK/
CV
REF
1
O
/ASCL1/RP40/T4CK/RB8
RC13
RP39/INT0/RB7
RPI58/RC10
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
RD8
V
SS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
V
DD
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF
2
O
/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AV
DD
AV
SS
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/
BCLK1/
RC2
AN11/C1IN2-
(3)
/U1CTS/RC11
V
SS
V
DD
AN12/C2IN2-
(3)
/U2RTS/
BCLK2/
RE12
AN13/C3IN2-
(3)
/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
SDA2/RPI24/RA8
SCL2/RP36/RB4
TDI/RA7
RPI46/T3CK/RB14
RPI47/T5CK/RB15
RP118/RG6
RPI119/RG7
RP120/RG8
MCLR
RPI121/RG9
V
SS
V
DD
AN10/RPI28/RA12
AN9/RPI27/RA11
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/
VREF
-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/
VREF
+/AN3/OA1OUT/RPI33/CTED1/RB1
PIC24EP64GP206
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
148
247
346
445
544
643
742
841
940
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: This pin is not available as an input when OPMODE (CMxCON<10>) = 1.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EP64GP506
PIC24EP128GP206
PIC24EP256GP206
dsPIC33EP128GP506
dsPIC33EP256GP506
dsPIC33EP512GP506
PIC24EP512GP206
2011-2013 Microchip Technology Inc. DS70657G-page 19
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
64-Pin QFN(1,2,3,4) = Pins are up to 5V tolerant
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
148
247
346
445
544
643
742
841
940
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TDO/RA10
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
RP43/PWM3L/RB11
RP42/PWM3H/RB10
RP97/RF1
RPI96/RF0
V
DD
V
CAP
RP57/RC9
RD6
RD5
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
TCK/
CV
REF
1
O
/ASCL1/RP40/T4CK/RB8
RC13
RP39/INT0/RB7
RPI58/RC10
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
RD8
V
SS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
V
DD
SCL1/RPI53/RC5
SDA1/RPI52/RC4
SCK1/RPI51/RC3
SDI1/RPI25/RA9
CVREF
2
O
/SDO1/RP20/T1CK/RA4
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AV
DD
AV
SS
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/
BCLK1/
FLT3/RC2
AN11/C1IN2-
(3)
/U1CTS/FLT4/RC11
V
SS
V
DD
AN12/C2IN2-
(3)
/U2RTS/
BCLK2/
RE12
AN13/C3IN2-
(3)
/U2CTS/RE13
AN14/RPI94/RE14
AN15/RPI95/RE15
SDA2/RPI24/RA8
FLT32
/SCL2/RP36/RB4
TDI/RA7
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
RP118/RG6
RPI119/RG7
RP120/RG8
MCLR
RPI121/RG9
V
SS
V
DD
AN10/RPI28/RA12
AN9/RPI27/RA11
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/
VREF
-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/
VREF
+/AN3/OA1OUT/RPI33/CTED1/RB1
PIC24EP64MC206
dsPIC33EP64MC206/506
PIC24EP128MC206
PIC24EP256MC206
dsPIC33EP128MC206/506
dsPIC33EP256MC206/506
dsPIC33EP512MC206/506
PIC24EP512MC206
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select” for available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as change notification (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: This pin is not available as an input when OPMODE (CMxCON<10>) = 1.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 20 2011-2013 Microchip Technology Inc.
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 23
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers and Microcontrollers ......................................................... 27
3.0 CPU............................................................................................................................................................................................ 33
4.0 Memory Organization ................................................................................................................................................................. 43
5.0 Flash Program Memory............................................................................................................................................................ 117
6.0 Resets ..................................................................................................................................................................................... 121
7.0 Interrupt Controller ................................................................................................................................................................... 125
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 137
9.0 Oscillator Configuration ............................................................................................................................................................ 151
10.0 Power-Saving Features............................................................................................................................................................ 161
11.0 I/O Ports ................................................................................................................................................................................... 171
12.0 Timer1 ...................................................................................................................................................................................... 201
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 205
14.0 Input Capture............................................................................................................................................................................ 211
15.0 Output Compare....................................................................................................................................................................... 217
16.0 High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only) ....................................... 223
17.0 Quadrature Encoder Interface (QEI) Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X Devices Only)........... 247
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 263
19.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 271
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 279
21.0 Enhanced CAN (ECAN™) Module (dsPIC33EPXXXGP/MC50X Devices Only) ..................................................................... 285
22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 313
23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 319
24.0 Peripheral Trigger Generator (PTG) Module............................................................................................................................ 335
25.0 Op Amp/Comparator Module ................................................................................................................................................... 353
26.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 371
27.0 Special Features ...................................................................................................................................................................... 377
28.0 Instruction Set Summary .......................................................................................................................................................... 385
29.0 Development Support............................................................................................................................................................... 395
30.0 Electrical Characteristics .......................................................................................................................................................... 399
31.0 High-Temperature Electrical Characteristics............................................................................................................................ 465
32.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 473
33.0 Packaging Information.............................................................................................................................................................. 477
Appendix A: Revision History............................................................................................................................................................. 503
Index ................................................................................................................................................................................................. 513
The Microchip Web Site ..................................................................................................................................................................... 521
Customer Change Notification Service .............................................................................................................................................. 521
Customer Support .............................................................................................................................................................................. 521
Reader Response .............................................................................................................................................................................. 522
Product Identification System............................................................................................................................................................. 523
2011-2013 Microchip Technology Inc. DS70657G-page 21
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department
via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 22 2011-2013 Microchip Technology Inc.
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33E/PIC24E Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
• Section 1. “Introduction” (DS70573)
•Section 2. “CPU” (DS70359)
•Section 3. “Data Memory” (DS70595)
•Section 4. “Program Memory” (DS70613)
•Section 5. “Flash Programming” (DS70609)
•Section 6. “Interrupts” (DS70600)
•Section 7. “Oscillator” (DS70580)
•Section 8. “Reset” (DS70602)
•Section 9. “Watchdog Timer and Power-Saving Modes” (DS70615)
•Section 10. “I/O Ports” (DS70598)
•Section 11. “Timers” (DS70362)
•Section 12. “Input Capture” (DS70352)
•Section 13. “Output Compare” (DS70358)
•Section 14. “High-Speed PWM” (DS70645)
•Section 15. “Quadrature Encoder Interface (QEI)” (DS70601)
•Section 16. “Analog-to-Digital Converter (ADC)” (DS70621)
•Section 17. “UART” (DS70582)
•Section 18. “Serial Peripheral Interface (SPI)” (DS70569)
•Section 19. “Inter-Integrated Circuit (I2C™)” (DS70330)
•Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70353)
•Section 22. “Direct Memory Access (DMA)” (DS70348)
•Section 23. “CodeGuard™ Security” (DS70634)
•Section 24. “Programming and Diagnostics” (DS70608)
•Section 26. “Op Amp/Comparator” (DS70357)
•Section 27. “Programmable Cyclic Redundancy Check (CRC)” (DS70346)
•Section 30. “Device Configuration” (DS70618)
•Section 32. “Peripheral Trigger Generator (PTG)” (DS70669)
•Section 33. “Charge Time Measurement Unit (CTMU)” (DS70661)
Note 1: To access the documents listed below,
browse to the documentation section of the
dsPIC33EP64MC506 product page of the
Microchip web site (www.microchip.com)
or select a family reference manual section
from the following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
2011-2013 Microchip Technology Inc. DS70657G-page 23
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
1.0 DEVICE OVERVIEW This document contains device-specific information for
the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X Digital Signal
Controller (DSC) and Microcontroller (MCU) devices.
dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X
devices contain extensive Digital Signal Processor (DSP)
functionality with a high-performance 16-bit MCU
architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules. Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
FIGURE 1-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
BLOCK DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a com-
prehensive resource. To complement
the information in this data sheet, refer
to the related section of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com)
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
PORTA
Power-up
Timer
Oscillator
Start-up
OSC1/CLKI
MCLR
VDD, VSS
UART1,
Timing
Generation
ECAN1(2) I2C1,
ADC
Timers
Input
Capture
Output
Compare
AVDD, AVSS
UART2
SPI2
SPI1,
Watchdog
Timer
POR/BOR
CRC
I2C2
QEI1(1) PWM(1)
Remappable
Pins
Note 1: This feature or peripheral is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2: This feature or peripheral is only available on dsPIC33EPXXXGP/MC50X devices.
Op Amp/
Comparator
CTMU
PTG
CPU
Refer to Figure 3-1 for CPU diagram details.
16
16
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
PORTS
Peripheral Modules
Timer
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 24 2011-2013 Microchip Technology Inc.
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name(4)Pin
Type
Buffer
Type PPS Description
AN0-AN15 I Analog No Analog input channels.
CLKI
CLKO
I
O
ST/
CMOS
—
No
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
OSC2
I
I/O
ST/
CMOS
—
No
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
REFCLKO O — Yes Reference clock output.
IC1-IC4 I ST Yes Capture Inputs 1 through 4.
OCFA
OCFB
OC1-OC4
I
I
O
ST
ST
—
Yes
No
Yes
Compare Fault A input (for Compare channels).
Compare Fault B input (for Compare channels).
Compare Outputs 1 through 4.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
RA0-RA4, RA7-RA12 I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.
RC0-RC13, RC15 I/O ST No PORTC is a bidirectional I/O port.
RD5, RD6, RD8 I/O ST No PORTD is a bidirectional I/O port.
RE12-RE15 I/O ST No PORTE is a bidirectional I/O port.
RF0, RF1 I/O ST No PORTF is a bidirectional I/O port.
RG6-RG9 I/O ST No PORTG is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
No
Yes
No
No
No
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
CTPLS
CTED1
CTED2
O
I
I
ST
ST
ST
No
No
No
CTMU pulse output.
CTMU External Edge Input 1.
CTMU External Edge Input 2.
U1CTS
U1RTS
U1RX
U1TX
BCLK1
I
O
I
O
O
ST
—
ST
—
ST
No
No
Yes
Yes
No
UART1 Clear-to-Send.
UART1 Ready-to-Send.
UART1 receive.
UART1 transmit.
UART1 IrDA® baud clock output.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select TTL = TTL input buffer
Note 1: This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This pin is available on dsPIC33EPXXXGP/MC50X devices only.
3: This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See
Section 16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X
Devices Only)” for more information.
4: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability.
2011-2013 Microchip Technology Inc. DS70657G-page 25
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
U2CTS
U2RTS
U2RX
U2TX
BCLK2
I
O
I
O
O
ST
—
ST
—
ST
No
No
Yes
Yes
No
UART2 Clear-to-Send.
UART2 Ready-to-Send.
UART2 receive.
UART2 transmit.
UART2 IrDA baud clock output.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
No
No
No
No
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
SCL2
SDA2
ASCL2
ASDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
Alternate synchronous serial clock input/output for I2C2.
Alternate synchronous serial data input/output for I2C2.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
C1RX(2)
C1TX(2)
I
O
ST
—
Yes
Yes
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
FLT1(1), FLT2(1)
FLT3(1), FLT4(1)
FLT32(1,3)
DTCMP1-DTCMP3(1)
PWM1L-PWM3L(1)
PWM1H-PWM3H(1)
SYNCI1(1)
SYNCO1(1)
I
I
I
I
O
O
I
O
ST
ST
ST
ST
—
—
ST
—
Yes
No
No
Yes
No
No
Yes
Yes
PWM Fault Input 1 and 2.
PWM Fault Input 3 and 4.
PWM Fault Input 32 (Class B Fault).
PWM Dead-Time Compensation Input 1 through 3.
PWM Low Output 1 through 3.
PWM High Output 1 through 3.
PWM Synchronization Input 1.
PWM Synchronization Output 1.
INDX1(1)
HOME1(1)
QEA1(1)
QEB1(1)
CNTCMP1(1)
I
I
I
I
O
ST
ST
ST
ST
—
Yes
Yes
Yes
Yes
Yes
Quadrature Encoder Index1 pulse input.
Quadrature Encoder Home1 pulse input.
Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer
external clock/gate input in Timer mode.
Quadrature Encoder Phase B input in QEI1 mode. Auxiliary timer
external clock/gate input in Timer mode.
Quadrature Encoder Compare Output 1.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name(4)Pin
Type
Buffer
Type PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select TTL = TTL input buffer
Note 1: This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This pin is available on dsPIC33EPXXXGP/MC50X devices only.
3: This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See
Section 16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X
Devices Only)” for more information.
4: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 26 2011-2013 Microchip Technology Inc.
C1IN1-
C1IN2-
C1IN1+
OA1OUT
C1OUT
I
I
I
O
O
Analog
Analog
Analog
Analog
—
No
No
No
No
Yes
Op Amp/Comparator 1 Negative Input 1.
Comparator 1 Negative Input 2.
Op Amp/Comparator 1 Positive Input 1.
Op Amp 1 Output.
Comparator 1 Output.
C2IN1-
C2IN2-
C2IN1+
OA2OUT
C2OUT
I
I
I
O
O
Analog
Analog
Analog
Analog
—
No
No
No
No
Yes
Op Amp/Comparator 2 Negative Input 1.
Comparator 2 Negative Input 2.
Op Amp/Comparator 2 Positive Input 1.
Op Amp 2 Output.
Comparator 2 Output.
C3IN1-
C3IN2-
C3IN1+
OA3OUT
C3OUT
I
I
I
O
O
Analog
Analog
Analog
Analog
—
No
No
No
No
Yes
Op Amp/Comparator 3 Negative Input 1.
Comparator 3 Negative Input 2.
Op Amp/Comparator 3 Positive Input 1.
Op Amp 3 Output.
Comparator 3 Output.
C4IN1-
C4IN1+
C4OUT
I
I
O
Analog
Analog
—
No
No
Yes
Comparator 4 Negative Input 1.
Comparator 4 Positive Input 1.
Comparator 4 Output.
CVREF1O
CVREF2O
O
O
Analog
Analog
No
No
Op amp/comparator voltage reference output.
Op amp/comparator voltage reference divided by 2 output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/debugging Communication Channel 1.
Clock input pin for Programming/debugging Communication Channel 1.
Data I/O pin for Programming/debugging Communication Channel 2.
Clock input pin for Programming/debugging Communication Channel 2.
Data I/O pin for Programming/debugging Communication Channel 3.
Clock input pin for Programming/debugging Communication Channel 3.
MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD P P No Positive supply for analog modules. This pin must be connected at all
times.
AVSS P P No Ground reference for analog modules. This pin must be connected at all
times.
VDD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.
VREF+ I Analog No Analog voltage reference (high) input.
VREF- I Analog No Analog voltage reference (low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name(4)Pin
Type
Buffer
Type PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select TTL = TTL input buffer
Note 1: This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This pin is available on dsPIC33EPXXXGP/MC50X devices only.
3: This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See
Section 16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X
Devices Only)” for more information.
4: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability.
2011-2013 Microchip Technology Inc. DS70657G-page 27
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2.0 GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS AND
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families requires attention
to a minimal set of device pin connections before
proceeding with development. The following is a list
of pin names, which must always be connected:
•All V
DD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
•All AV
DD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
•V
CAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
•MCLR
pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
•V
REF+/VREF- pins are used when external voltage
reference for ADC module is implemented
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
•Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended to use ceramic capacitors.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
•Handling high-frequency noise: If the board is
experiencing high-frequency noise, above tens of
MHz, add a second ceramic-type capacitor in
parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
•Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com)
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 28 2011-2013 Microchip Technology Inc.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTION
2.2.1 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3 CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (< 1 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD and must have a capacitor greater
than 4.7 µF (10 µF is recommended), 16V connected
to ground. The type can be ceramic or tantalum. See
Section 30.0 “Electrical Characteristics” for
additional information.
The placement of this capacitor should be close to the
VCAP pin. It is recommended that the trace length not
exceeds one-quarter inch (6 mm). See Section 27.3
“On-Chip Voltage Regulator” for details.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions:
• Device Reset
• Device Programming and Debugging.
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components as shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
dsPIC33E/PIC24E
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
VDD
MCLR
0.1 µF
Ceramic
VCAP
L1(1)
R1
10 µF
Tantalum
Note 1: As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
fFCNV
2
--------------=
f1
2LC
-----------------------=
L1
2fC
----------------------
2
=
(i.e., ADC conversion rate/2)
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C
R1(2)
R(1)
VDD
MCLR
dsPIC33EP/PIC24EP
JP
2011-2013 Microchip Technology Inc. DS70657G-page 29
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
2.5 ICSP Pins
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP con-
nector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB REAL
ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
•“Using MPLAB® ICD 3” (poster) DS51765
•“MPLAB® ICD 3 Design Advisory” DS51764
•“MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
•“Using MPLAB® REAL ICE™ In-Circuit Emulator”
(poster) DS51749
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator. For details, see Section 9.0
“Oscillator Configuration” for details.
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
Guard Ring
Guard Trace
Oscillator Pins
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 30 2011-2013 Microchip Technology Inc.
2.7 Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 3 MHz < FIN < 5.5 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins and drive the output to logic low.
2.9 Application Examples
• Induction heating
• Uninterruptable Power Supplies (UPS)
• DC/AC inverters
• Compressor motor control
• Washing machine 3-phase motor control
• BLDC motor control
• Automotive HVAC, cooling fans, fuel pumps
• Stepper motor control
• Audio and fluid sensor monitoring
• Camera lens focus and stability control
• Speech (playback, hands-free kits, answering
machines, VoIP)
• Consumer audio
• Industrial and building control (security systems
and access control)
• Barcode reading
• Networking: LAN switches, gateways
• Data storage device management
• Smart cards and smart card readers
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-8.
FIGURE 2-4: BOOST CONVERTER IMPLEMENTATION
IPFC
VOUTPUT
ADC Channel Op Amp/ ADC Channel
PWM
k1
k2
k3
FET
dsPIC33EP
VINPUT
Comparator Output
Driver
2011-2013 Microchip Technology Inc. DS70657G-page 31
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 2-5: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
FIGURE 2-6: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER
k1
Op Amp/
Comparator
k2
k7
PWM
PWM
ADC
Channel
ADC
Channel
5V Output
I5V
12V Input
FET
Driver
dsPIC33EP
k5
k4
k3
k6
k7
Op Amp/Comparator
Op Amp/Comparator
ADC Channel
Op Amp/Comparator
ADC
Channel
PWM
PWM
PWM
PWM
PWM
PWM
3.3V Output
12V Input
FET
Driver
FET
Driver
FET
Driver
dsPIC33EP
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 32 2011-2013 Microchip Technology Inc.
FIGURE 2-7: INTERLEAVED PFC
FIGURE 2-8: BEMF VOLTAGE MEASURED USING THE ADC MODULE
VAC
VOUT+
Op Amp/Comparator PWM ADC
PWM
|VAC|
k4k3
FET
dsPIC33EP
Driver
VOUT-
ADC Channel
FET
Driver
Op Amp/
k1k2
Comparator Channel
Op Amp/
Comparator
3-Phase
Inverter
PWM3H
PWM3L
PWM2H
PWM2L
PWM1H
PWM1L
FLTx Fault
BLDC
dsPIC33EP/PIC24EP
AN3
AN4
AN5
AN2
Demand
Phase Terminal Voltage Feedback
R49 R41 R34 R36
R44
R52
2011-2013 Microchip Technology Inc. DS70657G-page 33
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
3.0 CPU
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X CPU have a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for digital
signal processing. The CPU has a 24-bit instruction
word, with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions.
Overhead-free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
3.1 Registers
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X devices have six-
teen, 16-bit working registers in the programmer’s
model. Each of the working registers can act as a data,
address or address offset register. The 16th working
register (W15) operates as a Software Stack Pointer for
interrupts and calls.
3.2 Instruction Set
The instruction set for dsPIC33EPXXXGP50X and
dsPIC33EPXXXMC20X/50X devices has two classes of
instructions: the MCU class of instructions and the DSP
class of instructions. The instruction set for
PIC24EPXXXGP/MC20X devices has the MCU class of
instructions only and does not support DSP instructions.
These two instruction classes are seamlessly integrated
into the architecture and execute from a single execution
unit. The instruction set includes many addressing modes
and was designed for optimum C compiler efficiency.
3.3 Data Space Addressing
The base Data Space can be addressed as 64 Kbytes
(32K words).
The Data Space includes two ranges of memory,
referred to as X and Y data memory. Each memory
range is accessible through its own independent
Address Generation Unit (AGU). The MCU class of
instructions operates solely through the X memory
AGU, which accesses the entire memory map as one
linear Data Space. On dsPIC33EPXXXMC20X/50X
and dsPIC33EPXXXGP50X devices, certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y Data Spaces
have memory locations that are device-specific, and
are described further in the data memory maps in
Section 4.2 “Data Address Space”.
The upper 32 Kbytes of the Data Space memory map
can optionally be mapped into Program Space (PS) at
any 32-Kbyte aligned program word boundary. The
program-to-Data Space mapping feature, known as
Program Space Visibility (PSV), lets any instruction
access Program Space as if it were Data Space.
Moreover, the Base Data Space address is used in
conjunction with a Read or Write Page register
(DSRPAG or DSWPAG) to form an Extended Data
Space (EDS) address. The EDS can be addressed as
8M words or 16 Mbytes. Refer to Section 3. “Data
Memory” (DS70595) and Section 4. “Program
Memory” (DS70613) in the “dsPIC33E/PIC24E Family
Reference Manual” for more details on EDS, PSV and
table accesses.
On the dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X devices, overhead-free circular
buffers (Modulo Addressing) are supported in both X
and Y address spaces. The Modulo Addressing
removes the software boundary checking overhead for
DSP algorithms. The X AGU Circular Addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data re-ordering for radix-2 FFT
algorithms. PIC24EPXXXGP/MC20X devices do not
support Modulo and Bit-Reversed Addressing.
3.4 Addressing Modes
The CPU supports these addressing modes:
• Inherent (no operand)
• Relative
•Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
addressing mode group, depending upon its functional
requirements. As many as six addressing modes are
supported for each instruction.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70359) in the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 34 2011-2013 Microchip Technology Inc.
FIGURE 3-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
CPU BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCL
16
Program Counter
16-Bit ALU
24
24
24
24
X Data Bus
PCU 16
16 16
Divide
Support
Engine(1)
DSP
ROM Latch
16
Y Data Bus(1)
EA MUX
X RAGU
X WAGU
Y AGU(1)
16
24
16
16
16
16
16
16
16
8
Interrupt
Controller PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
RAM(1) X Data
RAM
Address
Latch
Address
Latch
16
Data Latch
16
16
16
X Address Bus
Y Address Bus
24
Literal Data
Program Memory
Address Latch
Power, Reset
and Oscillator
Control Signals
to Various Blocks
Ports
Peripheral
Modules
Note 1: This feature is not available on PIC24EPXXXGP/MC20X devices.
Modules
PCH
IR
16 x 16
W Register Array
2011-2013 Microchip Technology Inc. DS70657G-page 35
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
3.5 Programmer’s Model
The programmer’s model for the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,
and PIC24EPXXXGP/MC20X is shown in Figure 3-2.
All registers in the programmer’s model are memory
mapped and can be manipulated directly by
instructions. Tab l e 3 -1 lists a description of each
register.
In addition to the registers contained in the
programmer’s model, the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/
MC20X devices contain control registers for Modulo
Addressing (dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X devices only), Bit-Reversed
Addressing (dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X devices only) and interrupts.
These registers are described in subsequent
sections of this document.
All registers associated with the programmer’s model
are memory mapped, as shown in Ta b l e 4 - 1 .
TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS
Register(s) Name Description
W0 through W15 Working Register Array
ACCA, ACCB 40-Bit DSP Accumulators
PC 23-Bit Program Counter
SR ALU and DSP Engine STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
DSRPAG Extended Data Space (EDS) Read Page Register
DSWPAG Extended Data Space (EDS) Write Page Register
RCOUNT REPEAT Loop Count Register
DCOUNT(1)DO Loop Count Register
DOSTARTH(1,2), DOSTARTL(1,2)DO Loop Start Address Register (High and Low)
DOENDH(1), DOENDL(1)DO Loop End Address Register (High and Low)
CORCON Contains DSP Engine, DO Loop Control and Trap Status bits
Note 1: This register is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2: The DOSTARTH and DOSTARTL registers are read-only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 36 2011-2013 Microchip Technology Inc.
FIGURE 3-2: PROGRAMMER’S MODEL
NOVZ C
TBLPAG
PC23 PC0
70
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working/Address
Registers
DSP Operand
Registers
W0 (WREG)
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
Frame Pointer/W14
Stack Pointer/W15
DSP Address
Registers
AD39 AD0
AD31
DSP
Accumulators(1) ACCA
ACCB
DSRPAG
90
RA
0
OA(1) OB(1) SA(1) SB(1)
RCOUNT
15 0
Repeat Loop Counter
DCOUNT
15 0
DO Loop Counter and Stack(1)
DOSTART
23 0
DO Loop Start Address and Stack(1)
0
DOEND DO Loop End Address and Stack(1)
IPL2 IPL1
SPLIM Stack Pointer Limit
AD15
23 0
SRL
IPL0
PUSH.s and POP.s shadows
Nested DO Stack
0
0
OAB(1) SAB(1)
X Data Space Read Page Address
DA(1) DC
0
0
0
0
DSWPAG X Data Space Write Page Address
80
Note 1: This feature or bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
CORCON
15 0
CPU Core Control Register
2011-2013 Microchip Technology Inc. DS70657G-page 37
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
3.6 CPU Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
3.6.1 KEY RESOURCES
•Section 2. “CPU” (DS70359)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 38 2011-2013 Microchip Technology Inc.
3.7 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
OA(1)OB(1)SA(1,4)SB(1,4)OAB(1)SAB(1)DA(1)DC
bit 15 bit 8
R/W-0(2,3)R/W-0(2,3)R/W-0(2,3)R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL<2:0> RA N OV Z C
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit(1)
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit(1)
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1,4)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1,4)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit(1)
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1)
1 = Accumulators A or B are saturated or have been saturated at some time
0 = Neither Accumulator A or B are saturated
bit 9 DA: DO Loop Active bit(1)
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
2011-2013 Microchip Technology Inc. DS70657G-page 39
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
4: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 40 2011-2013 Microchip Technology Inc.
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR — US<1:0>(1)EDT(1,2)DL<2:0>(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0
SATA(1)SATB(1)SATDW(1)ACCSAT(1)IPL3(3)SFA RND(1)IF(1)
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing is enabled
0 = Fixed exception processing is enabled
bit 14 Unimplemented: Read as ‘0’
bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits(1)
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit(1,2)
1 = Terminates executing DO loop at end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits(1)
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
bit 7 SATA: ACCA Saturation Enable bit(1)
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit(1)
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit(1)
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit(1)
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2: This bit is always read as ‘0’.
3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
2011-2013 Microchip Technology Inc. DS70657G-page 41
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(3)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2 SFA: Stack Frame Active Status bit
1 = Stack frame is active. W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and
DSWPAG values
0 = Stack frame is not active. W14 and W15 address of EDS or Base Data Space
bit 1 RND: Rounding Mode Select bit(1)
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit(1)
1 = Integer mode is enabled for DSP multiply
0 = Fractional mode is enabled for DSP multiply
REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2: This bit is always read as ‘0’.
3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 42 2011-2013 Microchip Technology Inc.
3.8 Arithmetic Logic Unit (ALU)
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X ALU is 16 bits wide
and is capable of addition, subtraction, bit shifts and
logic operations. Unless otherwise mentioned,
arithmetic operations are two’s complement in nature.
Depending on the operation, the ALU can affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The core CPU incorporates hardware support for both
multiplication and division. This includes a dedicated
hardware multiplier and support hardware for 16-bit
divisor division.
3.8.1 MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed, or mixed-sign operation in
several MCU multiplication modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit signed x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
3.8.2 DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
3.9 DSP Engine
(dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X Devices
Only)
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a 40-bit barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The DSP engine can also perform inherent accumulator-
to-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or integer DSP multiply (IF)
• Signed, unsigned or mixed-sign DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
TABLE 3-2: DSP INSTRUCTIONS
SUMMARY
Instruction Algebraic
Operation
ACC Write
Back
CLR A = 0 Yes
ED A = (x – y)2No
EDAC A = A + (x – y)2No
MAC A = A + (x • y) Yes
MAC A = A + x2No
MOVSAC No change in A Yes
MPY A = x • y No
MPY A = x2No
MPY.N A = – x • y No
MSC A = A – x • y Yes
2011-2013 Microchip Technology Inc. DS70657G-page 43
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.0 MEMORY ORGANIZATION
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X architecture
features separate program and data memory spaces,
and buses. This architecture also allows the direct
access of program memory from the Data Space (DS)
during code execution.
4.1 Program Address Space
The program address memory space of the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit PC during program
execution, or from table operation or Data Space
remapping as described in Section 4.8 “Interfacing
Program and Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD operations, which use TBLPAG<7> to read
Device ID sections of the configuration memory space.
The program memory maps, which are presented by
device family and memory size, are shown in
Figure 4-1 through Figure 4-5.
FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X AND
PIC24EP32GP/MC20X DEVICES
Note: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Program
Memory” (DS70613) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
Reset Address
0x000000
0x000002
Write Latches
User Program
Flash Memory
0x0057EC
0x0057EA
(11K instructions)
0x800000
0xFA0000
0xFA0002
0xFA0004
DEVID
0xFEFFFE
0xFF0000
0xFFFFFE
0xF9FFFE
Unimplemented
(Read ‘
0
’s)
GOTO
Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
Interrupt Vector Table
Configuration Memory Space User Memory Space
Flash Configuration
Bytes
0x005800
0x0057FE
Reserved
0xFF0002
Note: Memory areas are not shown to scale.
0xFF0004
Reserved
0x800FF8
0x800FF6
0x801000
0x800FFE
USERID
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 44 2011-2013 Microchip Technology Inc.
FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X AND
PIC24EP64GP/MC20X DEVICES
Reset Address
0x000000
0x000002
Write Latches
User Program
Flash Memory
0x00AFEC
0x00AFEA
(22K instructions)
0x800000
0xFA0000
0xFA0002
0xFA0004
DEVID
0xFEFFFE
0xFF0000
0xFFFFFE
0xF9FFFE
Unimplemented
(Read ‘
0
’s)
GOTO
Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
Interrupt Vector Table
Configuration Memory Space User Memory Space
Flash Configuration
Bytes
0x00B000
0x00AFFE
Reserved
0xFF0002
Note: Memory areas are not shown to scale.
0xFF0004
Reserved
0x800FF8
0x800FF6
0x801000
0x800FFE
USERID
2011-2013 Microchip Technology Inc. DS70657G-page 45
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-3: PROGRAM MEMORY MAP FOR dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X
AND PIC24EP128GP/MC20X DEVICES
Reset Address
0x000000
0x000002
Write Latches
User Program
Flash Memory
0x0157EC
0x0157EA
(44K instructions)
0x800000
0xFA0000
0xFA0002
0xFA0004
DEVID
0xFEFFFE
0xFF0000
0xFFFFFE
0xF9FFFE
Unimplemented
(Read ‘
0
’s)
GOTO
Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
Interrupt Vector Table
Configuration Memory Space User Memory Space
Flash Configuration
Bytes
0x015800
0x0157FE
Reserved
0xFF0002
Note: Memory areas are not shown to scale.
0xFF0004
Reserved
0x800FF8
0x800FF6
0x801000
0x800FFE
USERID
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 46 2011-2013 Microchip Technology Inc.
FIGURE 4-4: PROGRAM MEMORY MAP FOR dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X
AND PIC24EP256GP/MC20X DEVICES
Reset Address
0x000000
0x000002
Write Latches
User Program
Flash Memory
0x02AFEC
0x02AFEA
(88K instructions)
0x800000
0xFA0000
0xFA0002
0xFA0004
DEVID
0xFEFFFE
0xFF0000
0xFFFFFE
0xF9FFFE
Unimplemented
(Read ‘
0
’s)
GOTO
Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
Interrupt Vector Table
Configuration Memory Space User Memory Space
Flash Configuration
Bytes
0x02B000
0x02AFFE
Reserved
0xFF0002
Note: Memory areas are not shown to scale.
0xFF0004
Reserved
0x800FF8
0x800FF6
0x801000
0x800FFE
USERID
2011-2013 Microchip Technology Inc. DS70657G-page 47
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-5: PROGRAM MEMORY MAP FOR dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X
AND PIC24EP512GP/MC20X DEVICES
Reset Address
0x000000
0x000002
Write Latches
User Program
Flash Memory
0x0557EC
0x0557EA
(175K instructions)
0x800000
0xFA0000
0xFA0002
0xFA0004
DEVID
0xFEFFFE
0xFF0000
0xFFFFFE
0xF9FFFE
Unimplemented
(Read ‘
0
’s)
GOTO
Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
Interrupt Vector Table
Configuration Memory Space User Memory Space
Flash Configuration
Bytes
0x055800
0x0557FE
Reserved
0xFF0002
Note: Memory areas are not shown to scale.
0xFF0004
Reserved
0x800FF8
0x800FF6
0x801000
0x800FFE
USERID
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 48 2011-2013 Microchip Technology Inc.
4.1.1 PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-6).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented, or
decremented by two, during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
4.1.2 INTERRUPT AND TRAP VECTORS
All dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices reserve the
addresses between 0x000000 and 0x000200 for hard-
coded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO instruction is programmed by the
user application at address 0x000000 of Flash
memory, with the actual address for the start of code at
address 0x000002 of Flash memory.
A more detailed discussion of the Interrupt Vector
Tables (IVTs) is provided in Section 7.1 “Interrupt
Vector Table”.
FIGURE 4-6: PROGRAM MEMORY ORGANIZATION
0816
PC Address
0x000000
0x000002
0x000004
0x000006
23
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
least significant word
most significant word
Instruction Width
0x000001
0x000003
0x000005
0x000007
msw
Address (lsw Address)
2011-2013 Microchip Technology Inc. DS70657G-page 49
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.2 Data Address Space
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X CPU has a separate
16-bit-wide data memory space. The Data Space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. The data
memory maps, which are presented by device family
and memory size, are shown in Figure 4-7 through
Figure 4-16.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the Data
Space. This arrangement gives a base Data Space
address range of 64 Kbytes (32K words).
The base Data Space address is used in conjunction
with a Read or Write Page register (DSRPAG or
DSWPAG) to form an Extended Data Space, which has
a total address range of 16 Mbytes.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices implement up to
52 Kbytes of data memory (4 Kbytes of data memory
for Special Function Registers and up to 48K of data
memory for RAM). If an EA points to a location outside
of this area, an all-zero word or byte is returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2 DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve Data Space memory
usage efficiency, the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
Effective Address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] results in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
A data byte read, reads the complete word that
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and
registers are organized as two parallel, byte-wide
entities with shared (word) address decode but
separate write lines. Data byte writes only write to the
corresponding side of the array or register that matches
the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3 SFR SPACE
The first 4 Kbytes of the Near Data Space, from 0x0000
to 0x0FFF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X core and peripheral
modules for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.4 NEAR DATA SPACE
The 8-Kbyte area, between 0x0000 and 0x1FFF, is
referred to as the Near Data Space. Locations in this
space are directly addressable through a 13-bit abso-
lute address field within all memory direct instructions.
Additionally, the whole Data Space is addressable
using MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
Note: The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 50 2011-2013 Microchip Technology Inc.
FIGURE 4-7: DATA MEMORY MAP FOR dsPIC33EP32MC20X/50X AND
dsPIC33EP32GP50X DEVICES
0x0000
0x0FFE
0x17FE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0x17FF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x1FFF 0x1FFE
0x1001 0x1000
0x1801 0x1800
4-Kbyte
SFR Space
4-Kbyte
SRAM Space
0x20000x2001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
0x80000x8001
Note: Memory areas are not shown to scale.
(PSV)
Y Data RAM (Y)
2011-2013 Microchip Technology Inc. DS70657G-page 51
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-8: DATA MEMORY MAP FOR dsPIC33EP64MC20X/50X AND
dsPIC33EP64GP50X DEVICES
0x0000
0x0FFE
0x1FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0x1FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x2FFF 0x2FFE
0x1001 0x1000
0x2001 0x2000
4-Kbyte
SFR Space
8-Kbyte
SRAM Space
0x30000x3001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
0x80000x8001
Note: Memory areas are not shown to scale.
(PSV)
Y Data RAM (Y)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 52 2011-2013 Microchip Technology Inc.
FIGURE 4-9: DATA MEMORY MAP FOR dsPIC33EP128MC20X/50X AND
dsPIC33EP128GP50X DEVICES
0x0000
0x0FFE
0x2FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0x2FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x4FFF 0x4FFE
0x1001 0x1000
0x3001 0x3000
4-Kbyte
SFR Space
16-Kbyte
SRAM Space
0x50000x5001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
0x80000x8001
Note: Memory areas are not shown to scale.
(PSV)
0x1FFE
0x1FFF
0x2001 0x2000
Y Data RAM (Y)
2011-2013 Microchip Technology Inc. DS70657G-page 53
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-10: DATA MEMORY MAP FOR dsPIC33EP256MC20X/50X AND
dsPIC33EP256GP50X DEVICES
0x0000
0x0FFE
0x4FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0x4FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x8FFF 0x8FFE
0x1001 0x1000
0x5001 0x5000
4-Kbyte
SFR Space
32-Kbyte
SRAM Space
0x90000x9001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
Y Data RAM (Y)
Note: Memory areas are not shown to scale.
(PSV)
0x1FFE
0x1FFF
0x2001 0x2000
0x7FFE
0x7FFF
0x8001 0x8000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 54 2011-2013 Microchip Technology Inc.
FIGURE 4-11: DATA MEMORY MAP FOR dsPIC33EP512MC20X/50X AND dsPIC33EP512GP50X
DEVICES
0x0000
0x0FFE
0x7FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0x7FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0xEFFF 0xEFFE
0x1001 0x1000
0x8001 0x8000
4-Kbyte
SFR Space
48-Kbyte
SRAM Space
0xD0000xD001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
Note: Memory areas are not shown to scale.
(PSV)
0x1FFE
0x1FFF
0x2001 0x2000
0x8FFE
0x8FFF
0x9001 0x9000
Y Data RAM (Y)
2011-2013 Microchip Technology Inc. DS70657G-page 55
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-12: DATA MEMORY MAP FOR PIC24EP32GP/MC20X/50X DEVICES
0x0000
0x0FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x1FFF 0x1FFE
0x1001 0x1000
4-Kbyte
SFR Space
4-Kbyte
SRAM Space
0x20000x2001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
0x80000x8001
Note: Memory areas are not shown to scale.
(PSV)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 56 2011-2013 Microchip Technology Inc.
FIGURE 4-13: DATA MEMORY MAP FOR PIC24EP64GP/MC20X/50X DEVICES
0x0000
0x0FFE
0x1FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0x1FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x2FFF 0x2FFE
0x1001 0x1000
0x2001 0x2000
4-Kbyte
SFR Space
8-Kbyte
SRAM Space
0x30000x3001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
0x80000x8001
Note: Memory areas are not shown to scale.
(PSV)
2011-2013 Microchip Technology Inc. DS70657G-page 57
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-14: DATA MEMORY MAP FOR PIC24EP128GP/MC20X/50X DEVICES
0x0000
0x0FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x4FFF 0x4FFE
0x1001 0x1000
4-Kbyte
SFR Space
16-Kbyte
SRAM Space
0x50000x5001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
0x80000x8001
Note: Memory areas are not shown to scale.
(PSV)
0x1FFE
0x1FFF
0x2001 0x2000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 58 2011-2013 Microchip Technology Inc.
FIGURE 4-15: DATA MEMORY MAP FOR PIC24EP256GP/MC20X/50X DEVICES
0x0000
0x0FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0x8FFF 0x8FFE
0x1001 0x1000
4-Kbyte
SFR Space
32-Kbyte
SRAM Space
0x90000x9001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
Note: Memory areas are not shown to scale.
(PSV)
0x1FFE
0x1FFF
0x2001 0x2000
0x7FFE
0x7FFF
0x8001 0x8000
2011-2013 Microchip Technology Inc. DS70657G-page 59
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 4-16: DATA MEMORY MAP FOR PIC24EP512GP/MC20X/50X DEVICES
0x0000
0x0FFE
0xFFFE
LSB
Address
16 Bits
LSBMSB
MSB
Address
0x0001
0x0FFF
0xFFFF
Optionally
Mapped
into Program
Memory Space
0xEFFF 0xEFFE
0x1001 0x1000
4-Kbyte
SFR Space
48-Kbyte
SRAM Space
0xD0000xD001
Data Space
Near
8-Kbyte
SFR Space
X Data RAM (X)
X Data
Unimplemented (X)
Note: Memory areas are not shown to scale.
(PSV)
0x1FFE
0x1FFF
0x2001 0x2000
0x7FFE
0x7FFF
0x8001 0x8000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 60 2011-2013 Microchip Technology Inc.
4.2.5 X AND Y DATA SPACES
The dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X core has two data spaces,
X and Y. These data spaces can be considered either
separate (for some DSP instructions) or as one unified
linear address range (for MCU instructions). The data
spaces are accessed using two Address Generation
Units (AGUs) and separate data paths. This feature
allows certain instructions to concurrently fetch two
words from RAM, thereby enabling efficient execution
of DSP algorithms, such as Finite Impulse Response
(FIR) filtering and Fast Fourier Transform (FFT).
The X Data Space is used by all instructions and
supports all addressing modes. X Data Space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
Data Space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y Data Space is used in concert with the X Data
Space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X Data Space.
Modulo Addressing and Bit-Reversed Addressing are
not present in PIC24EPXXXGP/MC20X devices.
All data memory writes, including in DSP instructions,
view Data Space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
4.3 Memory Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
4.3.1 KEY RESOURCES
•Section 4. “Program Memory” (DS70613)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 61
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.4 Special Function Register Maps
TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
W0 0000 W0 (WREG) xxxx
W1 0002 W1 xxxx
W2 0004 W2 xxxx
W3 0006 W3 xxxx
W4 0008 W4 xxxx
W5 000A W5 xxxx
W6 000C W6 xxxx
W7 000E W7 xxxx
W8 0010 W8 xxxx
W9 0012 W9 xxxx
W10 0014 W10 xxxx
W11 0016 W11 xxxx
W12 0018 W12 xxxx
W13 001A W13 xxxx
W14 001C W14 xxxx
W15 001E W15 xxxx
SPLIM 0020 SPLIM 0000
ACCAL 0022 ACCAL 0000
ACCAH 0024 ACCAH 0000
ACCAU 0026 Sign Extension of ACCA<39> ACCAU 0000
ACCBL 0028 ACCBL 0000
ACCBH 002A ACCBH 0000
ACCBU 002C Sign Extension of ACCB<39> ACCBU 0000
PCL 002E PCL<15:0> —0000
PCH 0030 — — — — — — — — — PCH<6:0> 0000
DSRPAG 0032 — — — — — —DSRPAG<9:0>0001
DSWPAG 0034 — — — — — — — DSWPAG<8:0> 0001
RCOUNT 0036 RCOUNT<15:0> 0000
DCOUNT 0038 DCOUNT<15:0> 0000
DOSTARTL 003A DOSTARTL<15:1> —0000
DOSTARTH 003C — — — — — — — — — —DOSTARTH<5:0>0000
DOENDL 003E DOENDL<15:1> —0000
DOENDH 0040 — — — — — — — — — — DOENDH<5:0> 0000
Legend:
x
= unknown value on Reset,
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 62 2011-2013 Microchip Technology Inc.
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 VAR — US<1:0> EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020
MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000
XMODSRT 0048 XMODSRT<15:0> —0000
XMODEND 004A XMODEND<15:0> —0001
YMODSRT 004C YMODSRT<15:0> —0000
YMODEND 004E YMODEND<15:0> —0001
XBREV 0050 BREN XBREV<14:0> 0000
DISICNT 0052 — — DISICNT<13:0> 0000
TBLPAG 0054 — — — — — — — —TBLPAG<7:0>0000
MSTRPR 0058 MSTRPR<15:0> 0000
TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED)
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend:
x
= unknown value on Reset,
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 63
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGP/MC20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
W0 0000 W0 (WREG) xxxx
W1 0002 W1 xxxx
W2 0004 W2 xxxx
W3 0006 W3 xxxx
W4 0008 W4 xxxx
W5 000A W5 xxxx
W6 000C W6 xxxx
W7 000E W7 xxxx
W8 0010 W8 xxxx
W9 0012 W9 xxxx
W10 0014 W10 xxxx
W11 0016 W11 xxxx
W12 0018 W12 xxxx
W13 001A W13 xxxx
W14 001C W14 xxxx
W15 001E W15 xxxx
SPLIM 0020 SPLIM<15:0> 0000
PCL 002E PCL<15:1> —0000
PCH 0030 — — ——————— PCH<6:0> 0000
DSRPAG 0032 — — — — — —DSRPAG<9:0>0001
DSWPAG 0034 — — — — — — —DSWPAG<8:0>0001
RCOUNT 0036 RCOUNT<15:0> 0000
SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 VAR — ——————————IPL3SFA— — 0020
DISICNT 0052 — — DISICNT<13:0> 0000
TBLPAG 0054 — — ——————TBLPAG<7:0>0000
MSTRPR 0058 MSTRPR<15:0> 0000
Legend:
x
= unknown value on Reset,
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 64 2011-2013 Microchip Technology Inc.
TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF —— SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — — — — — — — — — MI2C2IF SI2C2IF —0000
IFS4 0808 ——CTMUIF— — — — — — — — — CRCIF U2EIF U1EIF —0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF —0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE —— SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — — — — — — — — — MI2C2IE SI2C2IE —0000
IEC4 0828 ——CTMUIE— — — — — — — — — CRCIE U2EIE U1EIE —0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE —0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — — — — — — — — — SPI2IP<2:0> — SPI2EIP<2:0> 0044
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440
IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440
IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040
IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400
IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440
IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444
INTCON1 08C0 NSTDIS OVAERR OVBERR — — — — — — DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —0000
INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000
INTCON3 08C4 — — — — — — — — — —DAEDOOVR— — — — 0000
INTCON4 08C6 — — — — — — — — — — — — — — —SGHT0000
INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 65
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF —— SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF —0000
IFS4 0808 ——CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF —0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000
IFS6 080C — — — — — — — — — — — — — — —PWM3IF0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF —0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE —— SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — —MI2C2IESI2C2IE—0000
IEC4 0828 ——CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE —0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000
IEC6 082C — — — — — — — — — — — — — — —PWM3IE0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE —0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — — — — — — — — — SPI2IP<2:0> — SPI2EIP<2:0> 0044
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440
IPC14 085C — — — — — QEI1IP<2:0> — PSEMIP<2:0> — — — — 0440
IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440
IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040
IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400
IPC24 0870 — — — — — — — — — — — — — PWM3IP<2:0> 4004
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 66 2011-2013 Microchip Technology Inc.
IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400
IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440
IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444
INTCON1 08C0 NSTDIS OVAERR OVBERR — — — — — — DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —0000
INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000
INTCON3 08C4 — — — — — — — — — —DAEDOOVR— — — — 0000
INTCON4 08C6 — — — — — — — — — — — — — — —SGHT0000
INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY (CONTINUED)
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 67
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — — — — — — — — — MI2C2IF SI2C2IF —0000
IFS4 0808 ——CTMUIF — — — — — —C1TXIF—— CRCIF U2EIF U1EIF —0000
IFS6 080C — — — — — — — — — — — — — — —PWM3IF0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF —0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — — — — — — — — — MI2C2IE SI2C2IE —0000
IEC4 0828 ——CTMUIE — — — — — —C1TXIE—— CRCIE U2EIE U1EIE —0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE —0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> —CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
IPC11 0856 — — — — — — — — — — — — — — — — 0000
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440
IPC16 0860 — CRCIP<2:0> —U2EIP<2:0> — U1EIP<2:0> — — — — 4440
IPC17 0862 — — — — — C1TXIP<2:0> — — — — — — — — 0400
IPC19 0866 — — — — — — — — —CTMUIP<2:0>— — — — 0040
IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400
IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440
IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 68 2011-2013 Microchip Technology Inc.
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —0000
INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000
INTCON3 08C4 — — — — — — — — — —DAEDOOVR— — — — 0000
INTCON4 08C6 — — — — — — — — — — — — — — —SGHT0000
INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0> 0000
TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED)
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 69
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF —— SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF —0000
IFS4 0808 ——CTMUIF — — — — — — — — — CRCIF U2EIF U1EIF —0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — — 0000
IFS6 080C — — — — — — — — — — — — — — —PWM3IF0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF
PTGWDTIF PTGSTEPIF
—0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE —— SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE —0000
IEC4 0828 ——CTMUIE — — — — — — — — — CRCIE U2EIE U1EIE —0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000
IEC6 082C — — — — — — — — — — — — — — —PWM3IE0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE
PTGWDTIE PTGSTEPIE
—0000
IPC0 0840 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444
IPC1 0842 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0> 0004
IPC6 084C — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444
IPC8 0850 — — — — — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 0444
IPC9 0852 — — — — — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 0444
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — — 0440
IPC14 085C — — — — — QEI1IP<2:0> — PSEMIP<2:0> — — — — 0440
IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440
IPC19 0866 — — — — — — — — — CTMUIP<2:0> — — — — 0040
IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400
IPC24 0870 — — — — — — — — — — — — — PWM3IP<2:0> 0004
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 70 2011-2013 Microchip Technology Inc.
IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — — 4400
IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — — 4440
IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> — PTG1IP<2:0> 0444
INTCON1
08C0 NSTDIS OVAERR OVBERR COVAERR
COVBERR
OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —0000
INTCON2
08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP 8000
INTCON3
08C4 — — — — — — — — — —DAEDOOVR— — — — 0000
INTCON4
08C6 — — — — — — — — — — — — — — —SGHT0000
INTTREG
08C8 — — — — ILR<3:0> VECNUM<7:0> 0000
TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY (CONTINUED)
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 71
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IFS0 0800 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF
0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF
0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF
0000
IFS3 0806 — — — — — QEI1IF PSEMIF — — — — — — MI2C2IF SI2C2IF —
0000
IFS4 0808 ——CTMUIF — — — — — —C1TXIF—— CRCIF U2EIF U1EIF —
0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — —
0000
IFS6 080C — — — — — — — — — — — — — — —PWM3IF
0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — —
0000
IFS9 0812 — — — — — — — — — PTG3IF PTG2IF PTG1IF PTG0IF PTGWDTIF PTGSTEPIF —
0000
IEC0 0820 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE
0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE
0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE
0000
IEC3 0826 — — — — — QEI1IE PSEMIE — — — — — — MI2C2IE SI2C2IE —
0000
IEC4 0828 ——CTMUIE — — — — — —C1TXIE—— CRCIE U2EIE U1EIE —
0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — —
0000
IEC6 082C — — — — — — — — — — — — — — —PWM3IE
0000
IEC7 082E — — — — — — — — — — — — — — — —
0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — —
0000
IEC9 0832 — — — — — — — — — PTG3IE PTG2IE PTG1IE PTG0IE PTGWDTIE PTGSTEPIE —
0000
IPC0 0840 — T1IP<2:0> —OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0>
4444
IPC1 0842 — T2IP<2:0> —OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0>
4444
IPC2 0844 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0>
4444
IPC3 0846 — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0>
0444
IPC4 0848 — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0>
4444
IPC5 084A — — — — — — — — — — — — — INT1IP<2:0>
0004
IPC6 084C — T4IP<2:0> —OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0>
4444
IPC7 084E — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0>
4444
IPC8 0850 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> —SPI2EIP<2:0>
4444
IPC9 0852 — — — — —IC4IP<2:0>— IC3IP<2:0> — DMA3IP<2:0>
0444
IPC12 0858 — — — — — MI2C2IP<2:0> — SI2C2IP<2:0> — — — —
0440
IPC14 085C — — — — — QEI1IP<2:0> — PSEMIP<2:0> — — — —
0440
IPC16 0860 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — —
4440
IPC17 0862 — — — — — C1TXIP<2:0> — — — — — — — —
0400
IPC19 0866 — — — — — — — — —CTMUIP<2:0>— — — —
0040
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 72 2011-2013 Microchip Technology Inc.
IPC23 086E — PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — —
4400
IPC24 0870 — — — — — — — — — — — — — PWM3IP<2:0>
0004
IPC35 0886 — JTAGIP<2:0> — ICDIP<2:0> — — — — — — — —
4400
IPC36 0888 — PTG0IP<2:0> — PTGWDTIP<2:0> — PTGSTEPIP<2:0> — — — —
4440
IPC37 088A — — — — — PTG3IP<2:0> — PTG2IP<2:0> —PTG1IP<2:0>
0444
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —
0000
INTCON2 08C2 GIE DISI SWTRAP — — — — — — — — — — INT2EP INT1EP INT0EP
8000
INTCON3 08C4 — — — — — — — — — — DAE DOOVR — — — —
0000
INTCON4 08C6 — — — — — — — — — — — — — — —SGHT
0000
INTTREG 08C8 — — — — ILR<3:0> VECNUM<7:0>
0000
TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY (CONTINUED)
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend:
— = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 73
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-8: TIMER1 THROUGH TIMER5 REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TMR1 0100 Timer1 Register xxxx
PR1 0102 Period Register 1 FFFF
T1CON 0104 TON —TSIDL—————— TGATE TCKPS<1:0> — TSYNC TCS —0000
TMR2 0106 Timer2 Register xxxx
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx
TMR3 010A Timer3 Register xxxx
PR2 010C Period Register 2 FFFF
PR3 010E Period Register 3 FFFF
T2CON 0110 TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000
T3CON 0112 TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000
TMR4 0114 Timer4 Register xxxx
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx
TMR5 0118 Timer5 Register xxxx
PR4 011A Period Register 4 FFFF
PR5 011C Period Register 5 FFFF
T4CON 011E TON —TSIDL—————— TGATE TCKPS<1:0> T32 —TCS—0000
T5CON 0120 TON —TSIDL—————— TGATE TCKPS<1:0> ——TCS—0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 74 2011-2013 Microchip Technology Inc.
TABLE 4-9: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
IC1CON1 0140 —— ICSIDL ICTSEL<2:0> ——— ICI<1:0> ICOV ICBNE ICM<2:0> 0000
IC1CON2 0142 ——————— IC32 ICTRIG TRIGSTAT —SYNCSEL<4:0>000D
IC1BUF 0144 Input Capture 1 Buffer Register xxxx
IC1TMR 0146 Input Capture 1 Timer 0000
IC2CON1 0148 —— ICSIDL ICTSEL<2:0> ——— ICI<1:0> ICOV ICBNE ICM<2:0> 0000
IC2CON2 014A ——————— IC32 ICTRIG TRIGSTAT —SYNCSEL<4:0>000D
IC2BUF 014C Input Capture 2 Buffer Register xxxx
IC2TMR 014E Input Capture 2 Timer 0000
IC3CON1 0150 —— ICSIDL ICTSEL<2:0> ——— ICI<1:0> ICOV ICBNE ICM<2:0> 0000
IC3CON2 0152 ——————— IC32 ICTRIG TRIGSTAT —SYNCSEL<4:0>000D
IC3BUF 0154 Input Capture 3 Buffer Register xxxx
IC3TMR 0156 Input Capture 3 Timer 0000
IC4CON1 0158 —— ICSIDL ICTSEL<2:0> ——— ICI<1:0> ICOV ICBNE ICM<2:0> 0000
IC4CON2 015A ——————— IC32 ICTRIG TRIGSTAT —SYNCSEL<4:0>000D
IC4BUF 015C Input Capture 4 Buffer Register xxxx
IC4TMR 015E Input Capture 4 Timer 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 75
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-10: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 4 REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
OC1CON1 0900 —— OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC1RS 0904 Output Compare 1 Secondary Register xxxx
OC1R 0906 Output Compare 1 Register xxxx
OC1TMR 0908 Timer Value 1 Register xxxx
OC2CON1 090A —— OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC2CON2 090C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC2RS 090E Output Compare 2 Secondary Register xxxx
OC2R 0910 Output Compare 2 Register xxxx
OC2TMR 0912 Timer Value 2 Register xxxx
OC3CON1 0914 —— OCSIDL OCTSEL<2:0> — ENFLTB ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC3CON2 0916 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC3RS 0918 Output Compare 3 Secondary Register xxxx
OC3R 091A Output Compare 3 Register xxxx
OC3TMR 091C Timer Value 3 Register xxxx
OC4CON1 091E —— OCSIDL OCTSEL<2:0> ENFLTC ENFLTB ENFLTA OCFLTC OCFLTB OCFLTA TRIGMODE OCM<2:0> 0000
OC4CON2 0920 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0> 000C
OC4RS 0922 Output Compare 4 Secondary Register xxxx
OC4R 0924 Output Compare 4 Register xxxx
OC4TMR 0926 Timer Value 4 Register xxxx
Legend:
x
= unknown value on Reset,
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 76 2011-2013 Microchip Technology Inc.
TABLE 4-11: PTG REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PTGCST 0AC0 PTGEN — PTGSIDL PTGTOGL — PTGSWT PTGSSEN PTGIVIS PTGSTRT PTGWTO — — — —PTGITM<1:0>0000
PTGCON 0AC2 PTGCLK<2:0> PTGDIV<4:0> PTGPWD<3:0> — PTGWDT<2:0> 0000
PTGBTE 0AC4 ADCTS<4:1> IC4TSS IC3TSS IC2TSS IC1TSS OC4CS OC3CS OC2CS OC1CS OC4TSS OC3TSS OC2TSS OC1TSS 0000
PTGHOLD 0AC6 PTGHOLD<15:0> 0000
PTGT0LIM 0AC8 PTGT0LIM<15:0> 0000
PTGT1LIM 0ACA PTGT1LIM<15:0> 0000
PTGSDLIM 0ACC PTGSDLIM<15:0> 0000
PTGC0LIM 0ACE PTGC0LIM<15:0> 0000
PTGC1LIM 0AD0 PTGC1LIM<15:0> 0000
PTGADJ 0AD2 PTGADJ<15:0> 0000
PTGL0 0AD4 PTGL0<15:0> 0000
PTGQPTR 0AD6 — — — — — — — — — — — PTGQPTR<4:0> 0000
PTGQUE0 0AD8 STEP1<7:0> STEP0<7:0> 0000
PTGQUE1 0ADA STEP3<7:0> STEP2<7:0> 0000
PTGQUE2 0ADC STEP5<7:0> STEP4<7:0> 0000
PTGQUE3 0ADE STEP7<7:0> STEP6<7:0> 0000
PTGQUE4 0AE0 STEP9<7:0> STEP8<7:0> 0000
PTGQUE5 0AE2 STEP11<7:0> STEP10<7:0> 0000
PTGQUE6 0AE4 STEP13<7:0> STEP12<7:0> 0000
PTGQUE7 0AE6 STEP15<7:0> STEP14<7:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 77
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-12: PWM REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PTCON 0C00 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000
PTCON2 0C02 — — — — — — — — — — — — — PCLKDIV<2:0> 0000
PTPER 0C04 PTPER<15:0> 00F8
SEVTCMP 0C06 SEVTCMP<15:0> 0000
MDC 0C0A MDC<15:0> 0000
CHOP 0C1A CHPCLKEN — — — — — CHOPCLK<9:0> 0000
PWMKEY 0C1E PWMKEY<15:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: PWM GENERATOR 1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000
IOCON1 0C22 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000
FCLCON1 0C24 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000
PDC1 0C26 PDC1<15:0> FFF8
PHASE1 0C28 PHASE1<15:0> 0000
DTR1 0C2A — — DTR1<13:0> 0000
ALTDTR1 0C2C — — ALTDTR1<13:0> 0000
TRIG1 0C32 TRGCMP<15:0> 0000
TRGCON1 0C34 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000
LEBCON1 0C3A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY1 0C3C — — — — LEB<11:0> 0000
AUXCON1 0C3E — — — — BLANKSEL<3:0> —— CHOPCLK<3:0> CHOPHEN CHOPLEN 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 78 2011-2013 Microchip Technology Inc.
TABLE 4-14: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PWMCON2 0C40 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000
IOCON2 0C42 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000
FCLCON2 0C44 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 00F8
PDC2 0C46 PDC2<15:0> 0000
PHASE2 0C48 PHASE2<15:0> 0000
DTR2 0C4A — — DTR2<13:0> 0000
ALTDTR2 0C4C — — ALTDTR2<13:0> 0000
TRIG2 0C52 TRGCMP<15:0> 0000
TRGCON2 0C54 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000
LEBCON2 0C5A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY2 0C5C — — — — LEB<11:0> 0000
AUXCON2 0C5E — — — — BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15: PWM GENERATOR 3 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PWMCON3 0C60 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP — MTBS CAM XPRES IUE 0000
IOCON3 0C62 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC C000
FCLCON3 0C64 — CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 00F8
PDC3 0C66 PDC3<15:0> 0000
PHASE3 0C68 PHASE3<15:0> 0000
DTR3 0C6A — — DTR3<13:0> 0000
ALTDTR3 0C6C — — ALTDTR3<13:0> 0000
TRIG3 0C72 TRGCMP<15:0> 0000
TRGCON3 0C74 TRGDIV<3:0> — — — — — —TRGSTRT<5:0>0000
LEBCON3 0C7A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY3 0C7C — — — —LEB<11:0>0000
AUXCON3 0C7E — — — — BLANKSEL<3:0> —— CHOPSEL<3:0> CHOPHEN CHOPLEN 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 79
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-16: QEI1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
QEI1CON 01C0 QEIEN — QEISIDL PIMOD<2:0> IMV<1:0> — INTDIV<2:0> CNTPOL GATEN CCM<1:0>
0000
QEI1IOC 01C2 QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA
000x
QEI1STAT 01C4 —— PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN PCIIRQ PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN
0000
POS1CNTL 01C6 POSCNT<15:0>
0000
POS1CNTH 01C8 POSCNT<31:16>
0000
POS1HLD 01CA POSHLD<15:0>
0000
VEL1CNT 01CC VELCNT<15:0>
0000
INT1TMRL 01CE INTTMR<15:0>
0000
INT1TMRH 01D0 INTTMR<31:16>
0000
INT1HLDL 01D2 INTHLD<15:0>
0000
INT1HLDH 01D4 INTHLD<31:16>
0000
INDX1CNTL 01D6 INDXCNT<15:0>
0000
INDX1CNTH 01D8 INDXCNT<31:16>
0000
INDX1HLD 01DA INDXHLD<15:0>
0000
QEI1GECL 01DC QEIGEC<15:0>
0000
QEI1ICL 01DC QEIIC<15:0>
0000
QEI1GECH 01DE QEIGEC<31:16>
0000
QEI1ICH 01DE QEIIC<31:16>
0000
QEI1LECL 01E0 QEILEC<15:0>
0000
QEI1LECH 01E2 QEILEC<31:16>
0000
Legend:
x
= unknown value on Reset, — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 80 2011-2013 Microchip Technology Inc.
TABLE 4-17: I2C1 AND I2C2 REGISTER MAP
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000
I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF
I2C1BRG 0204 — — — — — — — Baud Rate Generator 0000
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000
I2C1ADD 020A — — — — — — I2C1 Address Register 0000
I2C1MSK 020C — — — — — — I2C1 Address Mask 0000
I2C2RCV 0210 — — — — — — — — I2C2 Receive Register 0000
I2C2TRN 0212 — — — — — — — — I2C2 Transmit Register 00FF
I2C2BRG 0214 — — — — — — — Baud Rate Generator 0000
I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000
I2C2ADD 021A — — — — — — I2C2 Address Register 0000
I2C2MSK 021C — — — — — — I2C2 Address Mask 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18: UART1 AND UART2 REGISTER MAP
SFR
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx
U1RXREG 0226 — — — — — — — UART1 Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler 0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx
U2RXREG 0236 — — — — — — — UART2 Receive Register 0000
U2BRG 0238 Baud Rate Generator Prescaler 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 81
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-19: SPI1 AND SPI2 REGISTER MAP
SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
SPI1STAT 0240 SPIEN — SPISIDL —— SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000
SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000
SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000
SPI2STAT 0260 SPIEN — SPISIDL —— SPIBEC<2:0> SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF 0000
SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000
SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000
SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 82 2011-2013 Microchip Technology Inc.
TABLE 4-20: ADC1 REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
ADC1BUF0 0300 ADC1 Data Buffer 0 xxxx
ADC1BUF1 0302 ADC1 Data Buffer 1 xxxx
ADC1BUF2 0304 ADC1 Data Buffer 2 xxxx
ADC1BUF3 0306 ADC1 Data Buffer 3 xxxx
ADC1BUF4 0308 ADC1 Data Buffer 4 xxxx
ADC1BUF5 030A ADC1 Data Buffer 5 xxxx
ADC1BUF6 030C ADC1 Data Buffer 6 xxxx
ADC1BUF7 030E ADC1 Data Buffer 7 xxxx
ADC1BUF8 0310 ADC1 Data Buffer 8 xxxx
ADC1BUF9 0312 ADC1 Data Buffer 9 xxxx
ADC1BUFA 0314 ADC1 Data Buffer 10 xxxx
ADC1BUFB 0316 ADC1 Data Buffer 11 xxxx
ADC1BUFC 0318 ADC1 Data Buffer 12 xxxx
ADC1BUFD 031A ADC1 Data Buffer 13 xxxx
ADC1BUFE 031C ADC1 Data Buffer 14 xxxx
ADC1BUFF 031E ADC1 Data Buffer 15 xxxx
AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> SSRCG SIMSAM ASAM SAMP DONE 0000
AD1CON2 0322 VCFG<2:0> —— CSCNA CHPS<1:0> BUFS SMPI<4:0> BUFM ALTS 0000
AD1CON3 0324 ADRC —— SAMC<4:0> ADCS<7:0> 0000
AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB ————— CH123NA<1:0> CH123SA 0000
AD1CHS0 0328 CH0NB —— CH0SB<4:0> CH0NA —— CH0SA<4:0> 0000
AD1CSSH 032E CSS31 CSS30 — — — CSS26 CSS25 CSS24 — — — — — — — — 0000
AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000
AD1CON4 0332 — — — — — — — ADDMAEN ————— DMABL<2:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 83
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-21: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
C1CTRL1 0400 —— CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> —CANCAP ——WIN0480
C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000
C1VEC 0404 — — —FILHIT<4:0> — ICODE<6:0> 0040
C1FCTRL 0406 DMABS<2:0> — — — — — — — —FSA<4:0>0000
C1FIFO 0408 ——FBP<5:0> —— FNRB<5:0> 0000
C1INTF 040A —— TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000
C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000
C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000
C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000
C1CFG2 0412 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000
C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF
C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000
C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
0400-
041E
See definition when WIN =
x
C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0
0000
C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
0000
C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0
0000
C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
0000
C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0>
0000
C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0>
0000
C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0>
0000
C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0>
xxxx
C1RXD 0440 ECAN1 Receive Data Word
xxxx
C1TXD 0442 ECAN1 Transmit Data Word
xxxx
Legend:
x
= unknown value on Reset, — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 84 2011-2013 Microchip Technology Inc.
TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
0400-
041E
See definition when WIN = x
C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000
C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000
C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000
C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000
C1RXM0SID 0430 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx
C1RXM0EID 0432 EID<15:8> EID<7:0> xxxx
C1RXM1SID 0434 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx
C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx
C1RXM2SID 0438 SID<10:3> SID<2:0> —MIDE—EID<17:16>xxxx
C1RXM2EID 043A EID<15:8> EID<7:0> xxxx
C1RXF0SID 0440 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx
C1RXF1SID 0444 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx
C1RXF2SID 0448 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF2EID 044A EID<15:8> EID<7:0> xxxx
C1RXF3SID 044C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF3EID 044E EID<15:8> EID<7:0> xxxx
C1RXF4SID 0450 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx
C1RXF5SID 0454 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx
C1RXF6SID 0458 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF6EID 045A EID<15:8> EID<7:0> xxxx
C1RXF7SID 045C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF7EID 045E EID<15:8> EID<7:0> xxxx
C1RXF8SID 0460 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx
C1RXF9SID 0464 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx
C1RXF10SID 0468 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF10EID 046A EID<15:8> EID<7:0> xxxx
C1RXF11SID 046C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 85
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
C1RXF11EID 046E EID<15:8> EID<7:0> xxxx
C1RXF12SID 0470 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx
C1RXF13SID 0474 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx
C1RXF14SID 0478 SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF14EID 047A EID<15:8> EID<7:0> xxxx
C1RXF15SID 047C SID<10:3> SID<2:0> — EXIDE —EID<17:16>xxxx
C1RXF15EID 047E EID<15:8> EID<7:0> xxxx
TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY (CONTINUED)
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 86 2011-2013 Microchip Technology Inc.
TABLE 4-24: CRC REGISTER MAP
TABLE 4-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC202/502 AND PIC24EPXXXGP/MC202
DEVICES ONLY
TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC203/503 AND PIC24EPXXXGP/MC203
DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CRCCON1 0640 CRCEN — CSIDL VWORD<4:0> CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0000
CRCCON2 0642 ——— DWIDTH<4:0> — — — PLEN<4:0> 0000
CRCXORL 0644 X<15:1> —0000
CRCXORH 0646 X<31:16> 0000
CRCDATL 0648 CRC Data Input Low Word 0000
CRCDATH 064A CRC Data Input High Word 0000
CRCWDATL 064C CRC Result Low Word 0000
CRCWDATH 064E CRC Result High Word 0000
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the programmable CRC module.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 0680 ——RP35R<5:0>——RP20R<5:0>0000
RPOR1 0682 ——RP37R<5:0>——RP36R<5:0>0000
RPOR2 0684 ——RP39R<5:0>——RP38R<5:0>0000
RPOR3 0686 ——RP41R<5:0>——RP40R<5:0>0000
RPOR4 0688 ——RP43R<5:0>——RP42R<5:0>0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 0680 ——RP35R<5:0>——RP20R<5:0>0000
RPOR1 0682 ——RP37R<5:0>——RP36R<5:0>0000
RPOR2 0684 ——RP39R<5:0>——RP38R<5:0>0000
RPOR3 0686 ——RP41R<5:0>——RP40R<5:0>0000
RPOR4 0688 ——RP43R<5:0>——RP42R<5:0>0000
RPOR5 068A — — — — — — — — — — — — — — — — 0000
RPOR6 068C — — — — — — — — — —RP56R<5:0>0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 87
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-27: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC204/504 AND PIC24EPXXXGP/MC204
DEVICES ONLY
TABLE 4-28: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC206/506 AND PIC24EPXXXGP/MC206
DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 0680 ——RP35R<5:0>——RP20R<5:0>0000
RPOR1 0682 ——RP37R<5:0>——RP36R<5:0>0000
RPOR2 0684 ——RP39R<5:0>——RP38R<5:0>0000
RPOR3 0686 ——RP41R<5:0>——RP40R<5:0>0000
RPOR4 0688 ——RP43R<5:0>——RP42R<5:0>0000
RPOR5 068A ——RP55R<5:0>——RP54R<5:0>0000
RPOR6 068C ——RP57R<5:0>——RP56R<5:0>0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPOR0 0680 ——RP35R<5:0>——RP20R<5:0>0000
RPOR1 0682 ——RP37R<5:0>——RP36R<5:0>0000
RPOR2 0684 ——RP39R<5:0>——RP38R<5:0>0000
RPOR3 0686 ——RP41R<5:0>——RP40R<5:0>0000
RPOR4 0688 ——RP43R<5:0>——RP42R<5:0>0000
RPOR5 068A ——RP55R<5:0>——RP54R<5:0>0000
RPOR6 068C ——RP57R<5:0>——RP56R<5:0>0000
RPOR7 068E ——RP97R<5:0>— — — — — — — — 0000
RPOR8 0690 —— RP118R<5:0> — — — — — — — — 0000
RPOR9 0692 — — — — — — — — — — RP120R<5:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 88 2011-2013 Microchip Technology Inc.
TABLE 4-29: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPINR0 06A0 —INT1R<6:0> — — — — — — — — 0000
RPINR1 06A2 — — — — — — — — —INT2R<6:0>0000
RPINR3 06A6 — — — — — — — — —T2CKR<6:0>0000
RPINR7 06AE — IC2R<6:0> —IC1R<6:0>0000
RPINR8 06B0 — IC4R<6:0> —IC3R<6:0>0000
RPINR11 06B6 — — — — — — — — —OCFAR<6:0>0000
RPINR12 06B8 —FLT2R<6:0> —FLT1R<6:0>0000
RPINR14 06BC — QEB1R<6:0> —QEA1R<6:0>0000
RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000
RPINR18 06C4 — — — — — — — — —U1RXR<6:0>0000
RPINR19 06C6 — — — — — — — — —U2RXR<6:0>0000
RPINR22 06CC — SCK2INR<6:0> —SDI2R<6:0>0000
RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000
RPINR26 06D4 — — — — — — — — — — — — — — — — 0000
RPINR37 06EA —SYNCI1R<6:0> — — — — — — — — 0000
RPINR38 06EC —DTCMP1R<6:0> — — — — — — — — 0000
RPINR39 06EE —DTCMP3R<6:0> —DTCMP2R<6:0>0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-30: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPINR0 06A0 —INT1R<6:0> ————————0000
RPINR1 06A2 — — — — — — — — —INT2R<6:0>0000
RPINR3 06A6 — — — — — — — — —T2CKR<6:0>0000
RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000
RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000
RPINR11 06B6 — — — — — — — — —OCFAR<6:0>0000
RPINR18 06C4 — — — — — — — — —U1RXR<6:0>0000
RPINR19 06C6 — — — — — — — — —U2RXR<6:0>0000
RPINR22 06CC — SCK2INR<6:0> —SDI2R<6:0>0000
RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 89
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-31: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPINR0 06A0 —INT1R<6:0> ————————0000
RPINR1 06A2 —————————INT2R<6:0>0000
RPINR3 06A6 —————————T2CKR<6:0>0000
RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000
RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000
RPINR11 06B6 —————————OCFAR<6:0>0000
RPINR18 06C4 —————————U1RXR<6:0>0000
RPINR19 06C6 —————————U2RXR<6:0>0000
RPINR22 06CC — SCK2INR<6:0> —SDI2R<6:0>0000
RPINR23 06CE ————————— SS2R<6:0> 0000
RPINR26 06D4 —————————C1RXR<6:0>0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-32: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPINR0 06A0 —INT1R<6:0> — — — — — — — — 0000
RPINR1 06A2 — — — — — — — — —INT2R<6:0>0000
RPINR3 06A6 — — — — — — — — —T2CKR<6:0>0000
RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000
RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000
RPINR11 06B6 — — — — — — — — —OCFAR<6:0>0000
RPINR12 06B8 —FLT2R<6:0> —FLT1R<6:0>0000
RPINR14 06BC — QEB1R<6:0> —QEA1R<6:0>0000
RPINR15 06BE — HOME1R<6:0> — INDX1R<6:0> 0000
RPINR18 06C4 — — — — — — — — —U1RXR<6:0>0000
RPINR19 06C6 — — — — — — — — —U2RXR<6:0>0000
RPINR22 06CC — SCK2INR<6:0> —SDI2R<6:0>0000
RPINR23 06CE — — — — — — — — —SS2R<6:0>0000
RPINR26 06D4 — — — — — — — — —C1RXR<6:0>0000
RPINR37 06EA — SYNCI1R<6:0> — — — — — — — — 0000
RPINR38 06EC —DTCMP1R<6:0> — — — — — — — — 0000
RPINR39 06EE —DTCMP3R<6:0> —DTCMP2R<6:0>0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 90 2011-2013 Microchip Technology Inc.
TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RPINR0 06A0 —INT1R<6:0> — — — — — — — — 0000
RPINR1 06A2 — — — — — — — — —INT2R<6:0>0000
RPINR3 06A6 — — — — — — — — —T2CKR<6:0>0000
RPINR7 06AE — IC2R<6:0> — IC1R<6:0> 0000
RPINR8 06B0 — IC4R<6:0> — IC3R<6:0> 0000
RPINR11 06B6 — — — — — — — — —OCFAR<6:0>0000
RPINR12 06B8 —FLT2R<6:0> —FLT1R<6:0>0000
RPINR14 06BC — QEB1R<6:0> — QEA1R<6:0> 0000
RPINR15 06BE —HOME1R<6:0> — INDX1R<6:0> 0000
RPINR18 06C4 — — — — — — — — —U1RXR<6:0>0000
RPINR19 06C6 — — — — — — — — —U2RXR<6:0>0000
RPINR22 06CC —SCK2INR<6:0> —SDI2R<6:0>0000
RPINR23 06CE — — — — — — — — — SS2R<6:0> 0000
RPINR37 06EA —SYNCI1R<6:0> — — — — — — — — 0000
RPINR38 06EC —DTCMP1R<6:0> — — — — — — — — 0000
RPINR39 06EE —DTCMP3R<6:0> —DTCMP2R<6:0>0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 91
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-34: NVM REGISTER MAP
TABLE 4-35: SYSTEM CONTROL REGISTER MAP
TABLE 4-36: REFERENCE CLOCK REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
NVMCON 0728 WR WREN WRERR NVMSIDL — — — — — — — — NVMOP<3:0> 0000
NVMADR 072A NVMADR<15:0> 0000
NVMADRU 072C — — — — — — — — NVMADR<23:16> 0000
NVMKEY 072E — — — — — — — — NVMKEY<7:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
RCON 0740 TRAPR IOPUWR ——VREGSF — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1
OSCCON 0742 —COSC<2:0>— NOSC<2:0> CLKLOCK IOLOCK LOCK —CF—— OSWEN Note 2
CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 0030
PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030
OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on the Configuration Fuses.
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
REFOCON 074E ROON — ROSSLP ROSEL RODIV<3:0> — — — — — — — — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 92 2011-2013 Microchip Technology Inc.
TABLE 4-37: PMD REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY
TABLE 4-38: PMD REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD ——AD1MD0000
PMD2 0762 ———— IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — —CMPMD—— CRCMD — — — — —I2C2MD—0000
PMD4 0766 — — — — — — — — — — — —REFOMDCTMUMD— — 0000
PMD6 076A — — — — — — — — — — — — — — — — 0000
PMD7 076C — — — — — — — — — — —
DMA0MD
PTGMD — — — 0000
DMA1MD
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD ——AD1MD0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — —CMPMD—— CRCMD — — — — —I2C2MD—0000
PMD4 0766 — — — — — — — — — — — —REFOMDCTMUMD— — 0000
PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
PMD7 076C — — — — — — — — — — —
DMA0MD
PTGMD — — — 0000
DMA1MD
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 93
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-39: PMD REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY
TABLE 4-40: PMD REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0760 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD —C1MDAD1MD0000
PMD2 0762 ———— IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — —CMPMD—— CRCMD — — — — —I2C2MD—0000
PMD4 0766 — — — — — — — — — — — —REFOMDCTMUMD— — 0000
PMD6 076A — — — — — — — — — — — — — — — — 0000
PMD7 076C — — — — — — — — — — —
DMA0MD
PTGMD — — — 0000
DMA1MD
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD —C1MDAD1MD0000
PMD2 0762 ———— IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — —CMPMD—— CRCMD — ————I2C2MD—0000
PMD4 0766 — — — — — — — — — — — —REFOMDCTMUMD— — 0000
PMD6 076A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
PMD7 076C — — — — — — — — — — —
DMA0MD
PTGMD — — — 0000
DMA1MD
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 94 2011-2013 Microchip Technology Inc.
TABLE 4-41: PMD REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
PMD1 0760 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD ——AD1MD0000
PMD2 0762 ———— IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 —————CMPMD—— CRCMD — — — — — I2C2MD —0000
PMD4 0766 — — — — — — — — — — — —REFOMDCTMUMD— — 0000
PMD6 076A ————— PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
PMD7 076C — — — — — — — — — — —
DMA0MD
PTGMD — — — 0000
DMA1MD
DMA2MD
DMA3MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 95
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-42: OP AMP/COMPARATOR REGISTER MAP
TABLE 4-44: JTAG INTERFACE REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CMSTAT 0A80 PSIDL — — — C4EVT C3EVT C2EVT C1EVT — — — — C4OUT C3OUT C2OUT C1OUT 0000
CVRCON 0A82 —CVR2OE — — — VREFSEL —— CVREN CVR1OE CVRR CVRSS CVR<3:0> 0000
CM1CON 0A84 CON COE CPOL —— OPMODE CEVT COUT EVPOL<1:0> — CREF ——CCH<1:0>0000
CM1MSKSRC 0A86 —— —— SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM1MSKCON 0A88 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM1FLTR 0A8A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM2CON 0A8C CON COE CPOL —— OPMODE CEVT COUT EVPOL<1:0> — CREF ——CCH<1:0>0000
CM2MSKSRC 0A8E —— —— SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM2MSKCON 0A90 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM2FLTR 0A92 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM3CON(1)0A94 CON COE CPOL —— OPMODE CEVT COUT EVPOL<1:0> — CREF ——CCH<1:0>0000
CM3MSKSRC(1)0A96 —— —— SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM3MSKCON(1)0A98 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM3FLTR(1)0A9A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
CM4CON 0A9C CON COE CPOL — — — CEVT COUT EVPOL<1:0> — CREF ——CCH<1:0>0000
CM4MSKSRC 0A9E —— —— SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000
CM4MSKCON 0AA0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000
CM4FLTR 0AA2 — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers are unavailable on dsPIC33EPXXXGP502/MC502/MC202 and PIC24EP256GP/MC202 (28-pin) devices.
TABLE 4-43: CTMU REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
CTMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000
CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> — — 0000
CTMUICON 033E ITRIM<5:0> IRNG<1:0> — — — — — — — — 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
JDATAH 0FF0 ———— JDATAH<27:16> xxxx
JDATAL 0FF2 JDATAL<15:0> 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 96 2011-2013 Microchip Technology Inc.
TABLE 4-45: DMAC REGISTER MAP
File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
DMA0CON 0B00 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>—— MODE<1:0> 0000
DMA0REQ 0B02 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA0STAL 0B04 STA<15:0> 0000
DMA0STAH 0B06 — — — — — — — —STA<23:16>0000
DMA0STBL 0B08 STB<15:0> 0000
DMA0STBH 0B0A — — — — — — — —STB<23:16>0000
DMA0PAD 0B0C PAD<15:0> 0000
DMA0CNT 0B0E — — CNT<13:0> 0000
DMA1CON 0B10 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>—— MODE<1:0> 0000
DMA1REQ 0B12 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA1STAL 0B14 STA<15:0> 0000
DMA1STAH 0B16 — — — — — — — —STA<23:16>0000
DMA1STBL 0B18 STB<15:0> 0000
DMA1STBH 0B1A — — — — — — — —STB<23:16>0000
DMA1PAD 0B1C PAD<15:0> 0000
DMA1CNT 0B1E — — CNT<13:0> 0000
DMA2CON 0B20 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>—— MODE<1:0> 0000
DMA2REQ 0B22 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA2STAL 0B24 STA<15:0> 0000
DMA2STAH 0B26 — — — — — — — —STA<23:16>0000
DMA2STBL 0B28 STB<15:0> 0000
DMA2STBH 0B2A — — — — — — — —STB<23:16>0000
DMA2PAD 0B2C PAD<15:0> 0000
DMA2CNT 0B2E — — CNT<13:0> 0000
DMA3CON 0B30 CHEN SIZE DIR HALF NULLW — — — — —AMODE<1:0>—— MODE<1:0> 0000
DMA3REQ 0B32 FORCE — — — — — — — IRQSEL<7:0> 00FF
DMA3STAL 0B34 STA<15:0> 0000
DMA3STAH 0B36 — — — — — — — —STA<23:16>0000
DMA3STBL 0B38 STB<15:0> 0000
DMA3STBH 0B3A — — — — — — — —STB<23:16>0000
DMA3PAD 0B3C PAD<15:0> 0000
DMA3CNT 0B3E — — CNT<13:0> 0000
DMAPWC 0BF0 — — — — — — — — — — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0 0000
DMARQC 0BF2 — — — — — — — — — — — — RQCOL3 RQCOL2 RQCOL1 RQCOL0 0000
DMAPPS 0BF4 — — — — — — — — — — — — PPST3 PPST2 PPST1 PPST0 0000
DMALCA 0BF6 — — — — — — — — — — — — LSTCH<3:0> 000F
DSADRL 0BF8 DSADR<15:0> 0000
DSADRH 0BFA — — — — — — — — DSADR<23:16> 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 97
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-46: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
TABLE 4-47: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
TABLE 4-48: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 0E00 — — — TRISA12 TRISA11 TRISA10 TRISA9 TRISA8 TRISA7 —— TRISA4 —— TRISA1 TRISA0 1F93
PORTA 0E02 — — — RA12 RA11 RA10 RA9 RA8 RA7 ——RA4——RA1RA00000
LATA 0E04 — — — LATA12 LATA11 LATA10 LATA9 LATA8 LATA7 ——LATA4—— LA1TA1 LA0TA0 0000
ODCA 0E06 — — — ODCA12 ODCA11 ODCA10 ODCA9 ODCA8 ODCA7 —— ODCA4 —— ODCA1 ODCA0 0000
CNENA 0E08 — — — CNIEA12 CNIEA11 CNIEA10 CNIEA9 CNIEA8 CNIEA7 —— CNIEA4 —— CNIEA1 CNIEA0 0000
CNPUA 0E0A — — — CNPUA12 CNPUA11 CNPUA10 CNPUA9 CNPUA8 CNPUA7 —— CNPUA4 —— CNPUA1 CNPUA0 0000
CNPDA 0E0C — — — CNPDA12 CNPDA11 CNPDA10 CNPDA9 CNPDA8 CNPDA7 —— CNPDA4 —— CNPDA1 CNPDA0 0000
ANSELA 0E0E — — — ANSA12 ANSA11 — — — — — —ANSA4—— ANSA1 ANSA0 1813
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — —ANSB8———— ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISC 0E20 TRISC15 — TRISC13 TRISC12 TRISC11 TRISC10 TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 BFFF
PORTC 0E22 RC15 — RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx
LATC 0E24 LATC15 — LATC13 LATC12 LATC11 LATC10 LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx
ODCC 0E26 ODCC15 — ODCC13 ODCC12 ODCC11 ODCC10 ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000
CNENC 0E28 CNIEC15 — CNIEC13 CNIEC12 CNIEC11 CNIEC10 CNIEC9 CNIEC8 CNIEC7 CNIEC6 CNIEC5 CNIEC4 CNIEC3 CNIEC2 CNIEC1 CNIEC0 0000
CNPUC 0E2A CNPUC15 — CNPUC13 CNPUC12 CNPUC11 CNPUC10 CNPUC9 CNPUC8 CNPUC7 CNPUC6 CNPUC5 CNPUC4 CNPUC3 CNPUC2 CNPUC1 CNPUC0 0000
CNPDC 0E2C CNPDC15 — CNPDC13 CNPDC12 CNPDC11 CNPDC10 CNPDC9 CNPDC8 CNPDC7 CNPDC6 CNPDC5 CNPDC4 CNPDC3 CNPDC2 CNPDC1 CNPDC0 0000
ANSELC 0E2E — — — — ANSC11 — — — — — — — — ANSC2 ANSC1 ANSC0 0807
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 98 2011-2013 Microchip Technology Inc.
TABLE 4-49: PORTD REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
TABLE 4-50: PORTE REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
TABLE 4-51: PORTF REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISD 0E30 — — — — — — —TRISD8— TRISD6 TRISD5 —————0160
PORTD 0E32 — — — — — — — RD8 — RD6 RD5 —————xxxx
LATD 0E34 — — — — — — —LATD8—LATD6LATD5—————xxxx
ODCD 0E36 — — — — — — — ODCD8 — ODCD6 ODCD5 —————0000
CNEND 0E38 — — — — — — —CNIED8— CNIED6 CNIED5 —————0000
CNPUD 0E3A — — — — — — — CNPUD8 — CNPUD6 CNPUD5 —————0000
CNPDD 0E3C — — — — — — — CNPDD8 — CNPDD6 CNPDD5 —————0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISE 0E40 TRISE15 TRISE14 TRISE13 TRISE12 — — — — — — — — — — — — F000
PORTE 0E42 RE15 RE14 RE13 RE12 — — — — — — — — — — — — xxxx
LATE 0E44 LATE15 LATE14 LATE13 LATE12 — — — — — — — — — — — — xxxx
ODCE 0E46 ODCE15 ODCE14 ODCE13 ODCE12 — — — — — — — — — — — — 0000
CNENE 0E48 CNIEE15 CNIEE14 CNIEE13 CNIEE12 — — — — — — — — — — — — 0000
CNPUE 0E4A CNPUE15 CNPUE14 CNPUE13 CNPUE12 — — — — — — — — — — — — 0000
CNPDE 0E4C CNPDE15 CNPDE14 CNPDE13 CNPDE12 — — — — — — — — — — — — 0000
ANSELE 0E4E ANSE15 ANSE14 ANSE13 ANSE12 — — — — — — — — — — — — 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISF 0E50 — — — — — — — — — — — — — — TRISF1 TRISF0 0173
PORTF 0E52 — — — — — — — — — — — — — —RF1RF0xxxx
LATF 0E54 — — — — — — — — — — — — — — LATF1 LATF0 xxxx
ODCF 0E56 — — — — — — — — — — — — — — ODCF1 ODCF0 0000
CNENF 0E58 — — — — — — — — — — — — — — CNIEF1 CNIEF0 0000
CNPUF 0E5A — — — — — — — — — — — — — — CNPUF1 CNPUF0 0000
CNPDF 0E5C — — — — — — — — — — — — — — CNPDF1 CNPDF0 0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 99
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-52: PORTG REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISG 0E60 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 ——————03C0
PORTG 0E62 — — — — — — RG9 RG8 RG7 RG6 ——————xxxx
LATG 0E64 — — — — — — LATG9 L ATG8 LATG7 LATG6 ——————xxxx
ODCG 0E66 — — — — — — ODCG9 ODCG8 ODCG7 ODCG6 ——————0000
CNENG 0E68 — — — — — — CNIEG9 CNIEG8 CNIEG7 CNIEG6 ——————0000
CNPUG 0E6A — — — — — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 ——————0000
CNPDG 0E6C — — — — — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 ——————0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 100 2011-2013 Microchip Technology Inc.
TABLE 4-53: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
TABLE 4-54: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
TABLE 4-55: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 0E00 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 —— TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F
PORTA 0E02 — — — — — RA10 RA9 RA8 RA7 —— RA4 RA3 RA2 RA1 RA0 0000
LATA 0E04 — — — — — LATA10 LATA9 LATA8 LATA7 —— LATA4 LATA3 LATA2 LA1TA1 LA0TA0 0000
ODCA 0E06 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 —— ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
CNENA 0E08 — — — — — CNIEA10 CNIEA9 CNIEA8 CNIEA7 —— CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000
CNPUA 0E0A — — — — — CNPUA10 CNPUA9 CNPUA8 CNPUA7 —— CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000
CNPDA 0E0C — — — — — CNPDA10 CNPDA9 CNPDA8 CNPDA7 —— CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000
ANSELA 0E0E — — — — — — — — — — —ANSA4 —— ANSA1 ANSA0 0013
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — —ANSB8— — — — ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISC 0E20 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF
PORTC 0E22 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx
LATC 0E24 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx
ODCC 0E26 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000
CNENC 0E28 — — — — — — CNIEC9 CNIEC8 CNIEC7 CNIEC6 CNIEC5 CNIEC4 CNIEC3 CNIEC2 CNIEC1 CNIEC0 0000
CNPUC 0E2A — — — — — — CNPUC9 CNPUC8 CNPUC7 CNPUC6 CNPUC5 CNPUC4 CNPUC3 CNPUC2 CNPUC1 CNPUC0 0000
CNPDC 0E2C — — — — — — CNPDC9 CNPDC8 CNPDC7 CNPDC6 CNPDC5 CNPDC4 CNPDC3 CNPDC2 CNPDC1 CNPDC0 0000
ANSELC 0E2E — — — — — — — — — — — — — ANSC2 ANSC1 ANSC0 0007
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 101
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 4-56: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
TABLE 4-57: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
TABLE 4-58: PORTC REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 0E00 — — — — — — — TRISA8 — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 011F
PORTA 0E02 — — — — — — —RA8— — — RA4 RA3 RA2 RA1 RA0 0000
LATA 0E04 — — — — — — —LATA8— — — LATA4 LATA3 LATA2 LA1TA1 LA0TA0 0000
ODCA 0E06 — — — — — — — ODCA8 — — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
CNENA 0E08 — — — — — — — CNIEA8 — — — CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000
CNPUA 0E0A — — — — — — — CNPUA8 — — — CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000
CNPDA 0E0C — — — — — — — CNPDA8 — — — CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000
ANSELA 0E0E — — — — — — — — — — —ANSA4 —— ANSA1 ANSA0 0013
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — —ANSB8— — — — ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISC 0E20 — — — — — — —TRISC8— — — — — — TRISC1 TRISC0 0107
PORTC 0E22 — — — — — — — RC8 — — — — — — RC1 RC0 xxxx
LATC 0E24 — — — — — — —LATC8— — — — — —LATC1LATC0xxxx
ODCC 0E26 — — — — — — — ODCC8 — — — — — — ODCC1 ODCC0 0000
CNENC 0E28 — — — — — — — CNIEC8 — — — — — — CNIEC1 CNIEC0 0000
CNPUC 0E2A — — — — — — — CNPUC8 — — — — — — CNPUC1 CNPUC0 0000
CNPDC 0E2C — — — — — — — CNPDC8 — — — — — — CNPDC1 CNPDC0 0000
ANSELC 0E2E — — — — — — — — — — — — — — ANSC1 ANSC0 0007
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 102 2011-2013 Microchip Technology Inc.
TABLE 4-59: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY
TABLE 4-60: PORTB REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISA 0E00 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001C
PORTA 0E02 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 0000
LATA 0E04 — — — — — — — — — — — LATA4 LATA3 LATA2 LA1TA1 LA0TA0 0000
ODCA 0E06 — — — — — — — — — — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
CNENA 0E08 — — — — — — — — — — — CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000
CNPUA 0E0A — — — — — — — — — — — CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000
CNPDA 0E0C — — — — — — — — — — — CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000
ANSELA 0E0E — — — — — — — — — — —ANSA4 —— ANSA1 ANSA0 0013
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All
Resets
TRISB 0E10 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
PORTB 0E12 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
LATB 0E14 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
ODCB 0E16 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
CNENB 0E18 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
CNPUB 0E1A CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
CNPDB 0E1C CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
ANSELB 0E1E — — — — — — —ANSB8— — — — ANSB3 ANSB2 ANSB1 ANSB0 010F
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2013 Microchip Technology Inc. DS70657G-page 103
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.4.1 PAGED MEMORY SCHEME
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X architecture
extends the available Data Space through a paging
scheme, which allows the available Data Space to
be accessed using MOV instructions in a linear
fashion for pre- and post-modified Effective
Addresses (EA). The upper half of the base Data
Space address is used in conjunction with the Data
Space Page registers, the 10-bit Read Page register
(DSRPAG) or the 9-bit Write Page register
(DSWPAG), to form an Extended Data Space (EDS)
address or Program Space Visibility (PSV) address.
The Data Space Page registers are located in the
SFR space.
Construction of the EDS address is shown in
Figure 4-1. When DSRPAG<9> = 0 and the base
address bit, EA<15> = 1, the DSRPAG<8:0> bits are
concatenated onto EA<14:0> to form the 24-bit EDS
read address. Similarly, when base address bit,
EA<15> = 1, DSWPAG<8:0> are concatenated onto
EA<14:0> to form the 24-bit EDS write address.
EXAMPLE 4-1: EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION
1
DSRPAG<8:0>
9 Bits
EA
15 Bits
Select
Byte24-Bit EDS EA
Select
EA
(DSRPAG = don’t care) No EDS Access
Select16-Bit DS EA
Byte
EA<15> = 0
DSRPAG
0
EA<15>
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
= 1?
DSRPAG<9>
Y
N
Generate
PSV Address
0
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 104 2011-2013 Microchip Technology Inc.
EXAMPLE 4-2: EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION
The paged memory scheme provides access to
multiple 32-Kbyte windows in the EDS and PSV
memory. The Data Space Page registers, DSxPAG, in
combination with the upper half of Data Space address,
can provide up to 16 Mbytes of additional address
space in the EDS and 8 Mbytes (DSRPAG only) of PSV
address space. The paged data memory space is
shown in Example 4-3.
The Program Space (PS) can be accessed with a
DSRPAG of 0x200 or greater. Only reads from PS are
supported using the DSRPAG. Writes to PS are not
supported, so DSWPAG is dedicated to DS, including
EDS only. The Data Space and EDS can be read from,
and written to, using DSRPAG and DSWPAG,
respectively.
1
DSWPAG<8:0>
9 Bits
EA
15 Bits
Byte24-Bit EDS EA
Select
EA
(DSWPAG = don’t care)
No EDS Access
Select16-Bit DS EA
Byte
EA<15> = 0
EA<15>
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
Generate
PSV Address
0
2011-2013 Microchip Technology Inc. DS70657G-page 105
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
EXAMPLE 4-3: PAGED DATA MEMORY SPACE
0x0000
Program Memory
0x0000
0x7FFF
0x7FFF
EDS Page 0x001
0x0000
SFR Registers
0x0FFF
0x1000
Up to 8-Kbyte
0x2FFF
Local Data Space EDS
(DSRPAG<9:0>/DSWPAG<8:0>)
Reserved
(Will produce an
address error trap)
32-Kbyte
EDS Window
0xFFFF
0x3000
Page 0
Program Space
0x00_0000
0x7F_FFFF
(lsw – <15:0>)
0x0000
(DSRPAG = 0x001)
(DSWPAG = 0x001)
EDS Page 0x1FF
(DSRPAG = 0x1FF)
(DSWPAG = 0x1FF)
EDS Page 0x200
(DSRPAG = 0x200)
PSV
Program
Memory
EDS Page 0x2FF
(DSRPAG = 0x2FF)
EDS Page 0x300
(DSRPAG = 0x300)
EDS Page 0x3FF
(DSRPAG = 0x3FF)
0x7FFF
0x0000
0x7FFF
0x0000
0x7FFF
0x0000
0x7FFF
0x0000
0x7FFF
DS_Addr<14:0>
DS_Addr<15:0>
(lsw)
PSV
Program
Memory
(MSB)
Table Address Space
(TBLPAG<7:0>)
Program Memory
0x00_0000
0x7F_FFFF
(MSB – <23:16>)
0x0000 (TBLPAG = 0x00)
0xFFFF
DS_Addr<15:0>
lsw Using
TBLRDL/TBLWTL
MSB Using
TBLRDH/TBLWTH
0x0000 (TBLPAG = 0x7F)
0xFFFF
lsw Using
TBLRDL/TBLWTL
MSB Using
TBLRDH/TBLWTH
(Instruction & Data)
No writes allowed
No writes allowed
No writes allowed
No writes allowed
RAM
0x7FFF
0x8000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 106 2011-2013 Microchip Technology Inc.
Allocating different Page registers for read and write
access allows the architecture to support data
movement between different pages in data memory.
This is accomplished by setting the DSRPAG register
value to the page from which you want to read, and
configuring the DSWPAG register to the page to which
it needs to be written. Data can also be moved from
different PSV to EDS pages, by configuring the
DSRPAG and DSWPAG registers to address PSV and
EDS space, respectively. The data can be moved
between pages by a single instruction.
When an EDS or PSV page overflow or underflow
occurs, EA<15> is cleared as a result of the register
indirect EA calculation. An overflow or underflow of the
EA in the EDS or PSV pages can occur at the page
boundaries when:
• The initial address prior to modification addresses
an EDS or PSV page
• The EA calculation uses Pre- or Post-Modified
Register Indirect Addressing; however, this does
not include Register Offset Addressing
In general, when an overflow is detected, the DSxPAG
register is incremented and the EA<15> bit is set to
keep the base address within the EDS or PSV window.
When an underflow is detected, the DSxPAG register is
decremented and the EA<15> bit is set to keep the
base address within the EDS or PSV window. This
creates a linear EDS and PSV address space, but only
when using Register Indirect Addressing modes.
Exceptions to the operation described above arise
when entering and exiting the boundaries of Page 0,
EDS and PSV spaces. Ta b l e 4 - 6 1 lists the effects of
overflow and underflow scenarios at different
boundaries.
In the following cases, when overflow or underflow
occurs, the EA<15> bit is set and the DSxPAG is not
modified; therefore, the EA will wrap to the beginning of
the current page:
• Register Indirect with Register Offset Addressing
• Modulo Addressing
• Bit-Reversed Addressing
TABLE 4-61: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS and
PSV SPACE BOUNDARIES(2,3,4)
O/U,
R/W Operation
Before After
DSxPAG DS
EA<15>
Page
Description DSxPAG DS
EA<15>
Page
Description
O,
Read
[++Wn]
or
[Wn++]
DSRPAG = 0x1FF 1EDS: Last page DSRPAG = 0x1FF 0See Note 1
O,
Read
DSRPAG = 0x2FF 1PSV: Last lsw
page
DSRPAG = 0x300 1PSV: First MSB
page
O,
Read
DSRPAG = 0x3FF 1PSV: Last MSB
page
DSRPAG = 0x3FF 0See Note 1
O,
Write
DSWPAG = 0x1FF 1EDS: Last page DSWPAG = 0x1FF 0See Note 1
U,
Read
[--Wn]
or
[Wn--]
DSRPAG = 0x001 1PSV page DSRPAG = 0x001 0See Note 1
U,
Read
DSRPAG = 0x200 1PSV: First lsw
page
DSRPAG = 0x200 0See Note 1
U,
Read
DSRPAG = 0x300 1PSV: First MSB
page
DSRPAG = 0x2FF 1PSV: Last lsw
page
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x8000).
2: An EDS access with DSxPAG = 0x000 will generate an address error trap.
3: Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate
an address error trap.
4: Pseudo-Linear Addressing is not supported for large offsets.
2011-2013 Microchip Technology Inc. DS70657G-page 107
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4.4.2 EXTENDED X DATA SPACE
The lower portion of the base address space range,
between 0x0000 and 0x2FFF, is always accessible
regardless of the contents of the Data Space Page
registers. It is indirectly addressable through the
register indirect instructions. It can be regarded as
being located in the default EDS Page 0 (i.e., EDS
address range of 0x000000 to 0x002FFF with the base
address bit, EA<15> = 0, for this address range).
However, Page 0 cannot be accessed through the
upper 32 Kbytes, 0x8000 to 0xFFFF, of base Data
Space, in combination with DSRPAG = 0x00 or
DSWPAG = 0x00. Consequently, DSRPAG and
DSWPAG are initialized to 0x001 at Reset.
The remaining pages, including both EDS and PSV
pages, are only accessible using the DSRPAG or
DSWPAG registers in combination with the upper
32 Kbytes, 0x8000 to 0xFFFF, of the base address,
where base address bit, EA<15> = 1.
For example, when DSRPAG = 0x01 or
DSWPAG = 0x01, accesses to the upper 32 Kbytes,
0x8000 to 0xFFFF, of the Data Space will map to the
EDS address range of 0x008000 to 0x00FFFF. When
DSRPAG = 0x02 or DSWPAG = 0x02, accesses to the
upper 32 Kbytes of the Data Space will map to the EDS
address range of 0x010000 to 0x017FFF and so on, as
shown in the EDS memory map in Figure 4-17.
For more information on the PSV page access using
Data Space Page registers, refer to Section 4.5
“Program Space Visibility from Data Space” in
Section 4. “Program Memory” (DS70613) of the
“dsPIC33E/PIC24E Family Reference Manual”.
FIGURE 4-17: EDS MEMORY MAP
Note 1: DSxPAG should not be used to access
Page 0. An EDS access with DSxPAG
set to 0x000 will generate an address
error trap.
2: Clearing the DSxPAG in software has no
effect.
0x008000
0x010000
0x018000
PAGE 3
PAGE 2
PAGE 1FD
0xFE8000
0xFF0000
0xFF8000
PAGE 1FF
PAGE 1FE
SFR/DS
0x0000
0xFFFF
EDS EA Address (24 bits)
DS
Conventional
EA<15:0>
0x8000
(PAGE 0)
(DSRPAG<8:0>, EA<14:0>)
(DSWPAG<8:0>, EA<14:0>)
PAGE 1
DSRPAG<9> = 0
DS Address
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DS70657G-page 108 2011-2013 Microchip Technology Inc.
4.4.3 DATA MEMORY ARBITRATION AND
BUS MASTER PRIORITY
EDS accesses from bus masters in the system are
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA and the ICD module. In the
event of coincidental access to a bus by the bus
masters, the arbiter determines which bus master
access has the highest priority. The other bus masters
are suspended and processed after the access of the
bus by the bus master with the highest priority.
By default, the CPU is Bus Master 0 (M0) with the
highest priority and the ICD is Bus Master 4 (M4) with
the lowest priority. The remaining bus master (DMA
controller) is allocated to M3 (M1 and M2 are reserved
and cannot be used). The user application may raise or
lower the priority of the DMA controller to be above that
of the CPU by setting the appropriate bits in the EDS
Bus Master Priority Control (MSTRPR) register. All bus
masters with raised priorities will maintain the same
priority relationship relative to each other (i.e., M1
being highest and M3 being lowest, with M2 in
between). Also, all the bus masters with priorities below
that of the CPU maintain the same priority relationship
relative to each other. The priority schemes for bus
masters with different MSTRPR values are tabulated in
Table 4-62.
This bus master priority control allows the user
application to manipulate the real-time response of the
system, either statically during initialization or
dynamically in response to real-time events.
TABLE 4-62: DATA MEMORY BUS
ARBITER PRIORITY
FIGURE 4-18: ARBITER ARCHITECTURE
Priority
MSTRPR<15:0> Bit Setting(1)
0x0000 0x0020
M0 (highest) CPU DMA
M1 Reserved CPU
M2 Reserved Reserved
M3 DMA Reserved
M4 (lowest) ICD ICD
Note 1: All other values of MSTRPR<15:0> are
reserved.
ICD
Reserved
Data Memory Arbiter
M0 M1 M2 M3 M4
MSTRPR<15:0>
DMA CPU
SRAM
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4.4.4 SOFTWARE STACK
The W15 register serves as a dedicated software Stack
Pointer (SP) and is automatically modified by exception
processing, subroutine calls and returns; however,
W15 can be referenced by any instruction in the same
manner as all other W registers. This simplifies
reading, writing and manipulating of the Stack Pointer
(for example, creating stack frames).
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SP points to valid RAM in all
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,
and PIC24EPXXXGP/MC20X devices, and permits
stack availability for non-maskable trap exceptions.
These can occur before the SP is initialized by the user
software. You can reprogram the SP during initialization
to any location within Data Space.
The Stack Pointer always points to the first available
free word and fills the software stack working from
lower toward higher addresses. Figure 4-19
illustrates how it pre-decrements for a stack pop
(read) and post-increments for a stack push (writes).
When the PC is pushed onto the stack, PC<15:0> are
pushed onto the first available stack word, then
PC<22:16> are pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in Figure 4-19. During exception processing,
the MSB of the PC is concatenated with the lower 8 bits
of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
FIGURE 4-19: CALL STACK FRAME
Note: To protect against misaligned stack
accesses, W15<0> is fixed to ‘0’ by the
hardware.
Note 1: To maintain system Stack Pointer (W15)
coherency, W15 is never subject to
(EDS) paging, and is therefore restricted
to an address range of 0x0000 to
0xFFFF. The same applies to the W14
when used as a Stack Frame Pointer
(SFA = 1).
2: As the stack can be placed in, and can
access X and Y spaces, care must be
taken regarding its use, particularly with
regard to local automatic variables in a C
development environment
<Free Word>
PC<15:1>
b‘000000000’
015
W15 (before CALL)
W15 (after CALL)
Stack Grows Toward
Higher Address
0x0000
PC<22:16>
CALL SUBR
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DS70657G-page 110 2011-2013 Microchip Technology Inc.
4.5 Instruction Addressing Modes
The addressing modes shown in Ta b l e 4 - 6 3 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.5.1 FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire Data Space.
4.5.2 MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W reg-
ister fetched from data memory or a 5-bit literal. The
result location can either be a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
TABLE 4-63: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Note: Not all instructions support all the
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn form the Effective Address (EA).
Register Indirect Post-Modified The contents of Wn form the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset
(Register Indexed)
The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
2011-2013 Microchip Technology Inc. DS70657G-page 111
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4.5.3 MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions, which apply to
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices, and the
DSP accumulator class of instructions, which
apply to the dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X devices, provide a greater
degree of addressing flexibility than other instructions.
In addition to the addressing modes supported by most
MCU instructions, move and accumulator instructions
also support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
In summary, the following addressing modes are
supported by move and accumulator instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-Bit Literal
• 16-Bit Literal
4.5.4 MAC INSTRUCTIONS
(dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X DEVICES
ONLY)
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the Data Pointers through register indirect
tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must therefore, be valid addresses within
X Data Space for W8 and W9, and Y Data Space for
W10 and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
• Register Indirect
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
4.5.5 OTHER INSTRUCTIONS
Besides the addressing modes outlined previously, some
instructions use literal constants of various sizes. For
example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ULNK, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as a NOP, do not have any operands.
Note: For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared by both source and destination (but
typically only used by one).
Note: Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
Note: Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
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DS70657G-page 112 2011-2013 Microchip Technology Inc.
4.6 Modulo Addressing
(dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X Devices
Only)
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or Pro-
gram Space (since the Data Pointer mechanism is
essentially the same for both). One circular buffer can be
supported in each of the X (which also provides the point-
ers into Program Space) and Y data spaces. Modulo
Addressing can operate on any W Register Pointer. How-
ever, it is not advisable to use W14 or W15 for Modulo
Addressing since these two registers are used as the
Stack Frame Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be config-
ured to operate in only one direction, as there are certain
restrictions on the buffer start address (for incrementing
buffers) or end address (for decrementing buffers),
based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
4.6.1 START AND END ADDRESS
The Modulo Addressing scheme requires that a
starting and ending address be specified, and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-1).
The length of a circular buffer is not directly specified. It
is determined by the difference between the corre-
sponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.6.2 W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that
operate with Modulo Addressing:
• If XWM = 1111, X RAGU and X WAGU Modulo
Addressing is disabled
• If YWM = 1111, Y AGU Modulo Addressing is
disabled
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-1). Modulo Addressing is
enabled for X Data Space when XWM is set to any
value other than ‘1111’ and the XMODEN bit is set
(MODCON<15>).
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
Data Space when YWM is set to any value other than
‘1111’ and the YMODEN bit is set at MODCON<14>.
FIGURE 4-20: MODULO ADDRESSING OPERATION EXAMPLE
Note: Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
0x1100
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
Byte
Address
MOV #0x1100, W0
MOV W0, XMODSRT ;set modulo start address
MOV #0x1163, W0
MOV W0, MODEND ;set modulo end address
MOV #0x8001, W0
MOV W0, MODCON ;enable W1, X AGU for modulo
MOV #0x0000, W0 ;W0 holds buffer fill value
MOV #0x1110, W1 ;point W1 to buffer
DO AGAIN, #0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
AGAIN: INC W0, W0 ;increment the fill value
2011-2013 Microchip Technology Inc. DS70657G-page 113
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4.6.3 MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
4.7 Bit-Reversed Addressing
(dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X Devices
Only)
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.7.1 BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWMx bits (W register selection) in the MODCON
register are any value other than ‘1111’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Addressing modifier, or
‘pivot point’, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
does not function for any other addressing mode or for
byte-sized data and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB) and the offset associated with the
Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.
Note: The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (such
as [W7 + W2]) is used, Modulo
Addressing correction is performed but
the contents of the register remain
unchanged.
Note: All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note: Modulo Addressing and Bit-Reversed
Addressing can be enabled simultaneously
using the same W register, but Bit-
Reversed Addressing operation will always
take precedence for data writes when
enabled.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 114 2011-2013 Microchip Technology Inc.
FIGURE 4-21: BIT-REVERSED ADDRESSING EXAMPLE
TABLE 4-64: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0000 00000 0
0001 11000 8
0010 20100 4
0011 31100 12
0100 40010 2
0101 51010 10
0110 60110 6
0111 71110 14
1000 80001 1
1001 91001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15
b3 b2 b1 0
b2 b3 b4 0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
Bit-Reversed Address
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
b7 b6 b5 b1
b7 b6 b5 b4
b11 b10 b9 b8
b11 b10 b9 b8
b15 b14 b13 b12
b15 b14 b13 b12
Sequential Address
Pivot Point
2011-2013 Microchip Technology Inc. DS70657G-page 115
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
4.8 Interfacing Program and Data
Memory Spaces
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X architecture uses a
24-bit-wide Program Space (PS) and a 16-bit-wide
Data Space (DS). The architecture is also a modified
Harvard scheme, meaning that data can also be
present in the Program Space. To use this data suc-
cessfully, it must be accessed in a way that preserves
the alignment of information in both spaces.
Aside from normal execution, the architecture of the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices provides two
methods by which Program Space can be accessed
during operation:
• Using table instructions to access individual bytes
or words anywhere in the Program Space
• Remapping a portion of the Program Space into
the Data Space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
TABLE 4-65: PROGRAM SPACE ADDRESS CONSTRUCTION
FIGURE 4-22: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Access Type Access
Space
Program Space Address
<23> <22:16> <15> <14:1> <0>
Instruction Access
(Code Execution)
User 0PC<22:1> 0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
User TBLPAG<7:0> Data EA<15:0>
0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
0
Program Counter
23 Bits
Program Counter(1)
TBLPAG
8 Bits
EA
16 Bits
Byte Select
0
1/0
User/Configuration
Table Operations(2)
Space Select
24 Bits
1/0
Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain
word alignment of data in the Program and Data Spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted in the
configuration memory space.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 116 2011-2013 Microchip Technology Inc.
4.8.1 DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the Program Space without going
through Data Space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a Program Space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to Data Space addresses.
Program memory can thus be regarded as two 16-bit-
wide word address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDH and TBLWTH access the space that
contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from Program Space.
Both function as either byte or word operations.
•TBLRDL (Table Read Low):
- In Word mode, this instruction maps the
lower word of the Program Space
location (P<15:0>) to a data address
(D<15:0>)
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
•TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. The ‘phantom’ byte
(D<15:8>) is always ‘0’.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address in the TBLRDL instruc-
tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a Program Space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user application
and configuration spaces. When TBLPAG<7> = 0, the
table page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
FIGURE 4-23: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
081623
00000000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
23 15 0
TBLPAG
02
0x000000
0x800000
0x020000
0x030000
Program Space
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
2011-2013 Microchip Technology Inc. DS70657G-page 117
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
5.0 FLASH PROGRAM MEMORY
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices contain
internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire VDD range.
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
ICSP allows for a dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X device to be serially programmed while in the
end application circuit. This is done with two lines for
programming clock and programming data (one of the
alternate programming pin pairs: PGECx/PGEDx), and
three other lines for power (VDD), ground (VSS) and
Master Clear (MCLR). This allows customers to
manufacture boards with unprogrammed devices and
then program the device just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
application can write program memory data a single
program memory word, and erase program memory in
blocks or ‘pages’ of 1024 instructions (3072 bytes) at a
time.
5.1 Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits<7:0> of the TBLPAG register and the
Effective Address (EA) from a W register, specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 5. “Flash Programming”
(DS70609) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
0
Program Counter
24 Bits
Program Counter
TBLPAG Reg
8 Bits
Working Reg EA
16 Bits
Byte
24-Bit EA
0
1/0
Select
Using
Table Instruction
Using
User/Configuration
Space Select
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 118 2011-2013 Microchip Technology Inc.
5.2 RTSP Operation
RTSP allows the user application to erase a single
page of memory and to program two instruction words
at a time. See the General Purpose and Motor Control
Family tables (Table 1 and Table 2, respectively) for the
page sizes of each device.
For more information on erasing and programming
Flash memory, refer to Section 5. “Flash Program-
ming” (DS70609) in the “dsPIC33E/PIC24E Family
Reference Manual”.
5.3 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the programming
operation is finished.
For erase and program times, refer to Parameters D137a
and D137b (Page Erase Time), and D138a and
D138b (Word Write Cycle Time) in Table 30-14 in
Section 30.0 “Electrical Characteristics”.
Setting the WR bit (NVMCON<15>) starts the opera-
tion and the WR bit is automatically cleared when the
operation is finished.
5.3.1 PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
Programmers can program two adjacent words
(24 bits x 2) of program Flash memory at a time on
every other word address boundary (0x000002,
0x000006, 0x00000A, etc.). To do this, it is necessary
to erase the page that contains the desired address of
the location the user wants to change.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions follow-
ing the start of the programming sequence should be
NOPs.
Refer to Section 5. “Flash Programming” (DS70609)
in the “dsPIC33E/PIC24E Family Reference Manual”
for details and codes examples on programming using
RTSP.
5.4 Flash Memory Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
5.4.1 KEY RESOURCES
•Section 5. “Flash Programming” (DS70609)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
5.5 Control Registers
Four SFRs are used to read and write the program
Flash memory: NVMCON, NVMKEY, NVMADRU and
NVMADR.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY (Register 5-4) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must
consecutively write 0x55 and 0xAA to the NVMKEY
register.
There are two NVM Address registers: NVMADRU and
NVMADR. These two registers, when concatenated,
form the 24-bit Effective Address (EA) of the selected
word for programming operations or the selected page
for erase operations.
The NVMADRU register is used to hold the upper 8 bits
of the EA, while the NVMADR register is used to hold
the lower 16 bits of the EA.
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 119
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0(1)R/W-0(1)R/W-0(1)R/W-0 U-0 U-0 U-0 U-0
WR WREN WRERR NVMSIDL(2)— — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0(1)R/W-0(1)R/W-0(1)R/W-0(1)
— — — —NVMOP<3:0>
(3,4)
bit 7 bit 0
Legend: SO = Settable Only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12 NVMSIDL: NVM Stop in Idle Control bit(2)
1 = Flash voltage regulator goes into Standby mode during Idle mode
0 = Flash voltage regulator is active during Idle mode
bit 11-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,3,4)
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
0011 = Memory page erase operation
0010 = Reserved
0001 = Memory double-word program operation(5)
0000 = Reserved
Note 1: These bits can only be reset on a POR.
2: If this bit is set, there will be minimal power savings (IIDLE) and upon exiting Idle mode, there is a delay
(TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 120 2011-2013 Microchip Technology Inc.
REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY REGISTER
REGISTER 5-2: NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
NVMADRU<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 NVMADRU<7:0>: Nonvolatile Memory Upper Write Address bits
Selects the upper 8 bits of the location to program or erase in program Flash memory. This register
may be read or written by the user application.
REGISTER 5-3: NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
NVMADR<15:8>
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
NVMADR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 NVMADR<15:0>: Nonvolatile Memory Lower Write Address bits
Selects the lower 16 bits of the location to program or erase in program Flash memory. This register
may be read or written by the user application.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits
2011-2013 Microchip Technology Inc. DS70657G-page 121
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
6.0 RESETS
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
•MCLR
: Master Clear Pin Reset
•SWR: RESET Instruction
• WDTO: Watchdog Timer Time-out Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 6-1).
A POR clears all the bits, except for the POR and BOR
bits (RCON<1:0>), that are set. The user application
can set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
For all Resets, the default clock source is determined
by the FNOSC<2:0> bits in the FOSCSEL Configura-
tion register. The value of the FNOSC<2:0> bits is
loaded into NOSC<2:0> (OSCCON<10:8>) on Reset,
which in turn, initializes the system clock.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 8. “Reset” (DS70602) of
the “dsPIC33E/PIC24E Family Reference
Manual”, which is available from the Micro-
chip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Refer to the specific peripheral section or
Section 4.0 “Memory Organization” of
this manual for register Reset states.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
MCLR
VDD
BOR
Sleep or Idle
RESET Instruction
WDT
Module
Glitch Filter
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
VDD Rise
Detect
POR
Configuration Mismatch
Security Reset
Internal
Regulator
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 122 2011-2013 Microchip Technology Inc.
6.1 Reset Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
6.1.1 KEY RESOURCES
•Section 8. “Reset” (DS70602)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 123
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR ——VREGSF —CMVREGS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
EXTR SWR SWDTEN(2)WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11 VREGSF: Flash Voltage Regulator Standby During Sleep bit
1 = Flash voltage regulator is active during Sleep
0 = Flash voltage regulator goes into Standby mode during Sleep
bit 10 Unimplemented: Read as ‘0’
bit 9 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred.
0 = A Configuration Mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software RESET (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 124 2011-2013 Microchip Technology Inc.
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
2011-2013 Microchip Technology Inc. DS70657G-page 125
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
7.0 INTERRUPT CONTROLLER
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X interrupt controller
reduces the numerous peripheral interrupt request sig-
nals to a single interrupt request signal to the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X CPU.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
traps
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with a unique vector
for each interrupt or exception source
• Fixed priority within a specified user priority level
• Fixed interrupt entry and return latencies
7.1 Interrupt Vector Table
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X Interrupt Vector
Table (IVT), shown in Figure 7-1, resides in program
memory starting at location, 000004h. The IVT
contains seven non-maskable trap vectors and up to
246 sources of interrupt. In general, each interrupt
source has its own vector. Each interrupt vector
contains a 24-bit-wide address. The value programmed
into each interrupt vector location is the starting
address of the associated Interrupt Service Routine
(ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.
7.2 Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices clear their
registers in response to a Reset, which forces the PC
to zero. The device then begins program execution at
location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Interrupts”
(DS70600) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Any unimplemented or unused vector
locations in the IVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 126 2011-2013 Microchip Technology Inc.
FIGURE 7-1: dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
INTERRUPT VECTOR TABLE
IVT
Decreasing Natural Order Priority
Reset – GOTO Instruction 0x000000
Reset – GOTO Address 0x000002
Oscillator Fail Trap Vector 0x000004
Address Error Trap Vector 0x000006
Generic Hard Trap Vector 0x000008
Stack Error Trap Vector 0x00000A
Math Error Trap Vector 0x00000C
DMAC Error Trap Vector 0x00000E
Generic Soft Trap Vector 0x000010
Reserved 0x000012
Interrupt Vector 0 0x000014
Interrupt Vector 1 0x000016
::
::
::
Interrupt Vector 52 0x00007C
Interrupt Vector 53 0x00007E
Interrupt Vector 54 0x000080
::
::
::
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
Interrupt Vector 118 0x000100
Interrupt Vector 119 0x000102
Interrupt Vector 120 0x000104
::
::
::
Interrupt Vector 244 0x0001FC
Interrupt Vector 245 0x0001FE
START OF CODE 0x000200
See Ta bl e 7 - 1 for
Interrupt Vector Details
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 7-1: INTERRUPT VECTOR DETAILS
Interrupt Source Vector
#
IRQ
#IVT Address
Interrupt Bit Location
Flag Enable Priority
Highest Natural Order Priority
INT0 – External Interrupt 0 8 0 0x000014 IFS0<0> IEC0<0> IPC0<2:0>
IC1 – Input Capture 1 9 1 0x000016 IFS0<1> IEC0<1> IPC0<6:4>
OC1 – Output Compare 1 10 2 0x000018 IFS0<2> IEC0<2> IPC0<10:8>
T1 – Timer1 11 3 0x00001A IFS0<3> IEC0<3> IPC0<14:12>
DMA0 – DMA Channel 0 12 4 0x00001C IFS0<4> IEC0<4> IPC1<2:0>
IC2 – Input Capture 2 13 5 0x00001E IFS0<5> IEC0<5> IPC1<6:4>
OC2 – Output Compare 2 14 6 0x000020 IFS0<6> IEC0<6> IPC1<10:8>
T2 – Timer2 15 7 0x000022 IFS0<7> IEC0<7> IPC1<14:12>
T3 – Timer3 16 8 0x000024 IFS0<8> IEC0<8> IPC2<2:0>
SPI1E – SPI1 Error 17 9 0x000026 IFS0<9> IEC0<9> IPC2<6:4>
SPI1 – SPI1 Transfer Done 18 10 0x000028 IFS0<10> IEC0<10> IPC2<10:8>
U1RX – UART1 Receiver 19 11 0x00002A IFS0<11> IEC0<11> IPC2<14:12>
U1TX – UART1 Transmitter 20 12 0x00002C IFS0<12> IEC0<12> IPC3<2:0>
AD1 – ADC1 Convert Done 21 13 0x00002E IFS0<13> IEC0<13> IPC3<6:4>
DMA1 – DMA Channel 1 22 14 0x000030 IFS0<14> IEC0<14> IPC3<10:8>
Reserved 23 15 0x000032 — — —
SI2C1 – I2C1 Slave Event 24 16 0x000034 IFS1<0> IEC1<0> IPC4<2:0>
MI2C1 – I2C1 Master Event 25 17 0x000036 IFS1<1> IEC1<1> IPC4<6:4>
CM – Comparator Combined Event 26 18 0x000038 IFS1<2> IEC1<2> IPC4<10:8>
CN – Input Change Interrupt 27 19 0x00003A IFS1<3> IEC1<3> IPC4<14:12>
INT1 – External Interrupt 1 28 20 0x00003C IFS1<4> IEC1<4> IPC5<2:0>
Reserved 29-31 21-23 0x00003E-0x000042 — — —
DMA2 – DMA Channel 2 32 24 0x000044 IFS1<8> IEC1<8> IPC6<2:0>
OC3 – Output Compare 3 33 25 0x000046 IFS1<9> IEC1<9> IPC6<6:4>
OC4 – Output Compare 4 34 26 0x000048 IFS1<10> IEC1<10> IPC6<10:8>
T4 – Timer4 35 27 0x00004A IFS1<11> IEC1<11> IPC6<14:12>
T5 – Timer5 36 28 0x00004C IFS1<12> IEC1<12> IPC7<2:0>
INT2 – External Interrupt 2 37 29 0x00004E IFS1<13> IEC1<13> IPC7<6:4>
U2RX – UART2 Receiver 38 30 0x000050 IFS1<14> IEC1<14> IPC7<10:8>
U2TX – UART2 Transmitter 39 31 0x000052 IFS1<15> IEC1<15> IPC7<14:12>
SPI2E – SPI2 Error 40 32 0x000054 IFS2<0> IEC2<0> IPC8<2:0>
SPI2 – SPI2 Transfer Done 41 33 0x000056 IFS2<1> IEC2<1> IPC8<6:4>
C1RX – CAN1 RX Data Ready(1)42 34 0x000058 IFS2<2> IEC2<2> IPC8<10:8>
C1 – CAN1 Event(1)43 35 0x00005A IFS2<3> IEC2<3> IPC8<14:12>
DMA3 – DMA Channel 3 44 36 0x00005C IFS2<4> IEC2<4> IPC9<2:0>
IC3 – Input Capture 3 45 37 0x00005E IFS2<5> IEC2<5> IPC9<6:4>
IC4 – Input Capture 4 46 38 0x000060 IFS2<6> IEC2<6> IPC9<10:8>
Reserved 47-56 39-48 0x000062-0x000074 — — —
SI2C2 – I2C2 Slave Event 57 49 0x000076 IFS3<1> IEC3<1> IPC12<6:4>
MI2C2 – I2C2 Master Event 58 50 0x000078 IFS3<2> IEC3<2> IPC12<10:8>
Reserved 59-64 51-56 0x00007A-0x000084 — — —
PSEM – PWM Special Event Match(2)65 57 0x000086 IFS3<9> IEC3<9> IPC14<6:4>
Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.
2: This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 128 2011-2013 Microchip Technology Inc.
QEI1 – QEI1 Position Counter Compare(2)66 58 0x000088 IFS3<10> IEC3<10> IPC14<10:8>
Reserved 67-72 59-64 0x00008A-0x000094 — — —
U1E – UART1 Error Interrupt 73 65 0x000096 IFS4<1> IEC4<1> IPC16<6:4>
U2E – UART2 Error Interrupt 74 66 0x000098 IFS4<2> IEC4<2> IPC16<10:8>
CRC – CRC Generator Interrupt 75 67 0x00009A IFS4<3> IEC4<3> IPC16<14:12>
Reserved 76-77 68-69 0x00009C-0x00009E — — —
C1TX – CAN1 TX Data Request(1)78 70 0x000A0 IFS4<6> IEC4<6> IPC17<10:8>
Reserved 79-84 71-76 0x0000A2-0x0000AC — — —
CTMU – CTMU Interrupt 85 77 0x0000AE IFS4<13> IEC4<13> IPC19<6:4>
Reserved 86-101 78-93 0x0000B0-0x0000CE — — —
PWM1 – PWM Generator 1(2)102 94 0x0000D0 IFS5<14> IEC5<14> IPC23<10:8>
PWM2 – PWM Generator 2(2)103 95 0x0000D2 IFS5<15> IEC5<15> IPC23<14:12>
PWM3 – PWM Generator 3(2)104 96 0x0000D4 IFS6<0> IEC6<0> IPC24<2:0>
Reserved 105-149 97-141 0x0001D6-0x00012E — — —
ICD – ICD Application 150 142 0x000142 IFS8<14> IEC8<14> IPC35<10:8>
JTAG – JTAG Programming 151 143 0x000130 IFS8<15> IEC8<15> IPC35<14:12>
Reserved 152 144 0x000134 — — —
PTGSTEP – PTG Step 153 145 0x000136 IFS9<1> IEC9<1> IPC36<6:4>
PTGWDT – PTG Watchdog Time-out 154 146 0x000138 IFS9<2> IEC9<2> IPC36<10:8>
PTG0 – PTG Interrupt 0 155 147 0x00013A IFS9<3> IEC9<3> IPC36<14:12>
PTG1 – PTG Interrupt 1 156 148 0x00013C IFS9<4> IEC9<4> IPC37<2:0>
PTG2 – PTG Interrupt 2 157 149 0x00013E IFS9<5> IEC9<5> IPC37<6:4>
PTG3 – PTG Interrupt 3 158 150 0x000140 IFS9<6> IEC9<6> IPC37<10:8>
Reserved 159-245 151-245 0x000142-0x0001FE — — —
Lowest Natural Order Priority
TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Source Vector
#
IRQ
#IVT Address
Interrupt Bit Location
Flag Enable Priority
Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.
2: This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 129
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
7.3 Interrupt Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
7.3.1 KEY RESOURCES
•Section 6. “Interrupts” (DS70600)
• Code Samples
• Application Notes
• Software Libraries
•Webinars
•All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
7.4 Interrupt Control and Status
Registers
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices implement the
following registers for the interrupt controller:
• INTCON1
• INTCON2
• INTCON3
• INTCON4
•INTTREG
7.4.1 INTCON1 THROUGH INTCON4
Global interrupt control functions are controlled from
INTCON1, INTCON2, INTCON3 and INTCON4.
INTCON1 contains the Interrupt Nesting Disable bit,
(NSTDIS) as well as the control and status flags for the
processor trap sources.
The INTCON2 register controls external interrupt
request signal behavior and also contains the Global
Interrupt Enable bit (GIE).
INTCON3 contains the status flags for the DMA and
DO stack overflow status trap sources.
The INTCON4 register contains the software
generated hard trap status bit (SGHT).
7.4.2 IFSx
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.4.3 IECx
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.4.4 IPCx
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
7.4.5 INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into vector number
(VECNUM<7:0>) and Interrupt level bit (ILR<3:0>)
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
7.4.6 STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the
interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
For more information on these registers refer to
Section 2. “CPU” (DS70359) in the “dsPIC33E/
PIC24E Family Reference Manual”.
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user
software can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 7-3
through Register 7-7 in the following pages.
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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REGISTER 7-1: SR: CPU STATUS REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0(3)R/W-0(3)R/W-0(3)R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL<2:0>(2)RA NOV Z C
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
2011-2013 Microchip Technology Inc. DS70657G-page 131
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REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR —US<1:0> EDT DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3(2)SFA RND IF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing is enabled
0 = Fixed exception processing is enabled
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
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DS70657G-page 132 2011-2013 Microchip Technology Inc.
REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NSTDIS OVAERR(1)OVBERR(1)COVAERR(1)COVBERR(1)OVATE(1)OVBTE(1)COVTE(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
SFTACERR(1)DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit(1)
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit(1)
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit(1)
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit(1)
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit(1)
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit(1)
1 = Trap overflow of Accumulator B
0 = Trap is disabled
bit 8 COVTE: Catastrophic Overflow Trap Enable bit(1)
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap is disabled
bit 7 SFTACERR: Shift Accumulator Error Status bit(1)
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6 DIV0ERR: Divide-by-Zero Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 5 DMACERR: DMAC Trap Flag bit
1 = DMAC trap has occurred
0 = DMAC trap has not occurred
Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 133
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 4 MATHERR: Math Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0 Unimplemented: Read as ‘0’
REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 134 2011-2013 Microchip Technology Inc.
REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
GIE DISI SWTRAP — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 GIE: Global Interrupt Enable bit
1 = Interrupts and associated IE bits are enabled
0 = Interrupts are disabled, but traps are still enabled
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13 SWTRAP: Software Trap Status bit
1 = Software trap is enabled
0 = Software trap is disabled
bit 12-3 Unimplemented: Read as ‘0’
bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
2011-2013 Microchip Technology Inc. DS70657G-page 135
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 7-5: INTCON3: INTERRUPT CONTROL REGISTER 3
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
——DAEDOOVR— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5 DAE: DMA Address Error Soft Trap Status bit
1 = DMA address error soft trap has occurred
0 = DMA address error soft trap has not occurred
bit 4 DOOVR: DO Stack Overflow Soft Trap Status bit
1 = DO stack overflow soft trap has occurred
0 = DO stack overflow soft trap has not occurred
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 7-6: INTCON4: INTERRUPT CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SGHT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 Unimplemented: Read as ‘0’
bit 0 SGHT: Software Generated Hard Trap Status bit
1 = Software generated hard trap has occurred
0 = Software generated hard trap has not occurred
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 136 2011-2013 Microchip Technology Inc.
REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — —ILR<3:0>
bit 15 bit 8
U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
VECNUM<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt bits
11111111 = 255, Reserved; do not use
•
•
•
00001001 = 9, IC1 – Input Capture 1
00001000 = 8, INT0 – External Interrupt 0
00000111 = 7, Reserved; do not use
00000110 = 6, Generic soft error trap
00000101 = 5, DMAC error trap
00000100 = 4, Math error trap
00000011 = 3, Stack error trap
00000010 = 2, Generic hard trap
00000001 = 1, Address error trap
00000000 = 0, Oscillator fail trap
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
8.0 DIRECT MEMORY ACCESS
(DMA)
The DMA controller transfers data between Peripheral
Data registers and Data Space SRAM
In addition, DMA can access the entire data memory
space. The Data Memory Bus Arbiter is utilized when
either the CPU or DMA attempts to access SRAM,
resulting in potential DMA or CPU stalls.
The DMA controller supports 4 independent channels.
Each channel can be configured for transfers to or from
selected peripherals. Some of the peripherals
supported by the DMA controller include:
• ECAN™
• Analog-to-Digital Converter (ADC)
• Serial Peripheral Interface (SPI)
•UART
• Input Capture
• Output Compare
Refer to Table 8 -1 for a complete list of supported
peripherals.
FIGURE 8-1: DMA CONTROLLER
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 22. “Direct Memory
Access (DMA)” (DS70348) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
DMAPERIPHERAL
Data Memory
SRAM
(see Figure 4-18)
Arbiter
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 138 2011-2013 Microchip Technology Inc.
In addition, DMA transfers can be triggered by timers
as well as external interrupts. Each DMA channel is
unidirectional. Two DMA channels must be allocated to
read and write to a peripheral. If more than one channel
receives a request to transfer data, a simple fixed
priority scheme based on channel number, dictates
which channel completes the transfer and which
channel, or channels, are left pending. Each DMA
channel moves a block of data, after which, it generates
an interrupt to the CPU to indicate that the block is
available for processing.
The DMA controller provides these functional
capabilities:
• Four DMA channels
• Register Indirect with Post-Increment
Addressing mode
• Register Indirect without Post-Increment
Addressing mode
• Peripheral Indirect Addressing mode (peripheral
generates destination address)
• CPU interrupt after half or full block
transfer complete
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or automatic (peripheral DMA
requests) transfer initiation
• One-Shot or Auto-Repeat Block Transfer modes
• Ping-Pong mode (automatic switch between two
SRAM start addresses after each block transfer is
complete)
• DMA request for each channel can be selected
from any supported interrupt source
• Debug support features
The peripherals that can utilize DMA are listed in
Table 8-1.
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
Peripheral to DMA Association DMAxREQ Register
IRQSEL<7:0> Bits
DMAxPAD Register
(Values to Read from
Peripheral)
DMAxPAD Register
(Values to Write to
Peripheral)
INT0 – External Interrupt 0 00000000 ——
IC1 – Input Capture 1 00000001 0x0144 (IC1BUF) —
IC2 – Input Capture 2 00000101 0x014C (IC2BUF) —
IC3 – Input Capture 3 00100101 0x0154 (IC3BUF) —
IC4 – Input Capture 4 00100110 0x015C (IC4BUF) —
OC1 – Output Compare 1 00000010 — 0x0906 (OC1R)
0x0904 (OC1RS)
OC2 – Output Compare 2 00000110 — 0x0910 (OC2R)
0x090E (OC2RS)
OC3 – Output Compare 3 00011001 — 0x091A (OC3R)
0x0918 (OC3RS)
OC4 – Output Compare 4 00011010 — 0x0924 (OC4R)
0x0922 (OC4RS)
TMR2 – Timer2 00000111 ——
TMR3 – Timer3 00001000 ——
TMR4 – Timer4 00011011 ——
TMR5 – Timer5 00011100 ——
SPI1 Transfer Done 00001010 0x0248 (SPI1BUF) 0x0248 (SPI1BUF)
SPI2 Transfer Done 00100001 0x0268 (SPI2BUF) 0x0268 (SPI2BUF)
UART1RX – UART1 Receiver 00001011 0x0226 (U1RXREG) —
UART1TX – UART1 Transmitter 00001100 — 0x0224 (U1TXREG)
UART2RX – UART2 Receiver 00011110 0x0236 (U2RXREG) —
UART2TX – UART2 Transmitter 00011111 — 0x0234 (U2TXREG)
ECAN1 – RX Data Ready 00100010 0x0440 (C1RXD) —
ECAN1 – TX Data Request 01000110 — 0x0442 (C1TXD)
ADC1 – ADC1 Convert Done 00001101 0x0300 (ADC1BUF0) —
2011-2013 Microchip Technology Inc. DS70657G-page 139
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 8-2: DMA CONTROLLER BLOCK DIAGRAM
8.1 DMA Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
8.1.1 KEY RESOURCES
•Section 22. “Direct Memory Access (DMA)”
(DS70348)
• Code Samples
• Application Notes
• Software Libraries
•Webinars
•All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
8.2 DMAC Registers
Each DMAC Channel x (where x = 0 through 3)
contains the following registers:
• 16-Bit DMA Channel Control register (DMAxCON)
• 16-Bit DMA Channel IRQ Select register (DMAxREQ)
• 32-Bit DMA RAM Primary Start Address register
(DMAxSTA)
• 32-Bit DMA RAM Secondary Start Address register
(DMAxSTB)
• 16-Bit DMA Peripheral Address register (DMAxPAD)
• 14-Bit DMA Transfer Count register (DMAxCNT)
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA and DSADR) are common to all
DMAC channels. These status registers provide infor-
mation on write and request collisions, as well as on
last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
CPU
Arbiter
Peripheral
Non-DMA
DMA X-Bus
Peripheral Indirect Address
DMA
Control
DMA Controller
DMA
CPU Peripheral X-Bus
IRQ to DMA
and Interrupt
Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
0123
SRAM
Channels Peripheral 1
DMA
Ready
CPU DMA
Peripheral 3
DMA
Ready
CPU DMA
Peripheral 2
DMA
Ready
CPU DMA
Note: CPU and DMA address buses are not shown for clarity.
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 140 2011-2013 Microchip Technology Inc.
REGISTER 8-1: DMAXCON: DMA CHANNEL X CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
CHEN SIZE DIR HALF NULLW — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
——AMODE<1:0>——MODE<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHEN: DMA Channel Enable bit
1 = Channel is enabled
0 = Channel is disabled
bit 14 SIZE: DMA Data Transfer Size bit
1 =Byte
0 =Word
bit 13 DIR: DMA Transfer Direction bit (source/destination bus select)
1 = Reads from RAM address, writes to peripheral address
0 = Reads from peripheral address, writes to RAM address
bit 12 HALF: DMA Block Transfer Interrupt Select bit
1 = Initiates interrupt when half of the data has been moved
0 = Initiates interrupt when all of the data has been moved
bit 11 NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to RAM write (DIR bit must also be clear)
0 = Normal operation
bit 10-6 Unimplemented: Read as ‘0’
bit 5-4 AMODE<1:0>: DMA Channel Addressing Mode Select bits
11 = Reserved
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer)
10 = Continuous, Ping-Pong modes are enabled
01 = One-Shot, Ping-Pong modes are disabled
00 = Continuous, Ping-Pong modes are disabled
2011-2013 Microchip Technology Inc. DS70657G-page 141
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 8-2: DMAXREQ: DMA CHANNEL X IRQ SELECT REGISTER
R/S-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
FORCE(1)— — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQSEL<7:0>
bit 7 bit 0
Legend: S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FORCE: Force DMA Transfer bit(1)
1 = Forces a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA request
bit 14-8 Unimplemented: Read as ‘0’
bit 7-0 IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits
01000110 = ECAN1 – TX Data Request(2)
00100110 = IC4 – Input Capture 4
00100101 = IC3 – Input Capture 3
00100010 = ECAN1 – RX Data Ready(2)
00100001 = SPI2 Transfer Done
00011111 = UART2TX – UART2 Transmitter
00011110 = UART2RX – UART2 Receiver
00011100 = TMR5 – Timer5
00011011 = TMR4 – Timer4
00011010 = OC4 – Output Compare 4
00011001 = OC3 – Output Compare 3
00001101 = ADC1 – ADC1 Convert done
00001100 = UART1TX – UART1 Transmitter
00001011 = UART1RX – UART1 Receiver
00001010 = SPI1 – Transfer Done
00001000 = TMR3 – Timer3
00000111 = TMR2 – Timer2
00000110 = OC2 – Output Compare 2
00000101 = IC2 – Input Capture 2
00000010 = OC1 – Output Compare 1
00000001 = IC1 – Input Capture 1
00000000 = INT0 – External Interrupt 0
Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the
forced DMA transfer is complete or the channel is disabled (CHEN = 0).
2: This selection is available in dsPIC33EPXXXGP/MC50X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 142 2011-2013 Microchip Technology Inc.
REGISTER 8-3: DMAXSTAH: DMA CHANNEL X START ADDRESS REGISTER A (HIGH)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STA<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 STA<23:16>: Primary Start Address bits (source or destination)
REGISTER 8-4: DMAXSTAL: DMA CHANNEL X START ADDRESS REGISTER A (LOW)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STA<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STA<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STA<15:0>: Primary Start Address bits (source or destination)
2011-2013 Microchip Technology Inc. DS70657G-page 143
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 8-5: DMAXSTBH: DMA CHANNEL X START ADDRESS REGISTER B (HIGH)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STB<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 STB<23:16>: Secondary Start Address bits (source or destination)
REGISTER 8-6: DMAXSTBL: DMA CHANNEL X START ADDRESS REGISTER B (LOW)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STB<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STB<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STB<15:0>: Secondary Start Address bits (source or destination)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 144 2011-2013 Microchip Technology Inc.
REGISTER 8-7: DMAXPAD: DMA CHANNEL X PERIPHERAL ADDRESS REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PAD<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PAD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PAD<15:0>: Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
REGISTER 8-8: DMAXCNT: DMA CHANNEL X TRANSFER COUNT REGISTER(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CNT<13:8>(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CNT<7:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 CNT<13:0>: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: The number of DMA transfers = CNT<13:0> + 1.
2011-2013 Microchip Technology Inc. DS70657G-page 145
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 8-9: DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 DSADR<23:16>: Most Recent DMA Address Accessed by DMA bits
REGISTER 8-10: DSADRL: DMA MOST RECENT RAM LOW ADDRESS REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 146 2011-2013 Microchip Technology Inc.
REGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 PWCOL3: DMA Channel 3 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 2 PWCOL2: DMA Channel 2 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 1 PWCOL1: DMA Channel 1 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
bit 0 PWCOL0: DMA Channel 0 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
2011-2013 Microchip Technology Inc. DS70657G-page 147
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — RQCOL3 RQCOL2 RQCOL1 RQCOL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 RQCOL3: DMA Channel 3 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision detected
0 = No request collision detected
bit 2 RQCOL2: DMA Channel 2 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision detected
0 = No request collision detected
bit 1 RQCOL1: DMA Channel 1 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision detected
0 = No request collision detected
bit 0 RQCOL0: DMA Channel 0 Transfer Request Collision Flag bit
1 = User force and interrupt-based request collision detected
0 = No request collision detected
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 148 2011-2013 Microchip Technology Inc.
REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1
— — — — LSTCH<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3-0 LSTCH<3:0>: Last DMAC Channel Active Status bits
1111 = No DMA transfer has occurred since system Reset
1110 = Reserved
•
•
•
0100 = Reserved
0011 = Last data transfer was handled by Channel 3
0010 = Last data transfer was handled by Channel 2
0001 = Last data transfer was handled by Channel 1
0000 = Last data transfer was handled by Channel 0
2011-2013 Microchip Technology Inc. DS70657G-page 149
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — PPST3 PPST2 PPST1 PPST0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 PPST3: DMA Channel 3 Ping-Pong Mode Status Flag bit
1 = DMASTB3 register selected
0 = DMASTA3 register selected
bit 2 PPST2: DMA Channel 2 Ping-Pong Mode Status Flag bit
1 = DMASTB2 register selected
0 = DMASTA2 register selected
bit 1 PPST1: DMA Channel 1 Ping-Pong Mode Status Flag bit
1 = DMASTB1 register selected
0 = DMASTA1 register selected
bit 0 PPST0: DMA Channel 0 Ping-Pong Mode Status Flag bit
1 = DMASTB0 register selected
0 = DMASTA0 register selected
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 150 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 151
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
9.0 OSCILLATOR CONFIGURATION The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X oscillator system
provides:
• On-chip Phase-Locked Loop (PLL) to boost inter-
nal operating frequency on select internal and
external oscillator sources
• On-the-fly clock switching between various clock
sources
• Doze mode for system power savings
• Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or
shutdown
• Configuration bits for clock source selection
A simplified diagram of the oscillator system is shown
in Figure 9-1.
FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 7. “Oscillator” (DS70580) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note 1: See Figure 9-2 for PLL and FVCO details.
2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 Mmust be
connected.
3: The term, FP, refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU.
Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY
will be different when Doze mode is used with a doze ratio of 1:2 or lower.
XTPLL, HSPLL,
XT, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FRCDIVN
FRCDIV16
ECPLL, FRCPLL
NOSC<2:0> FNOSC<2:0>
Reset
FRC
Oscillator
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
÷ 16
Clock Switch
S7
Clock Fail
÷ 2
TUN<5:0>
PLL(1)
FCY(3)
FOSC
FRCDIV
DOZE
FSCM
POSCCLK
FRCCLK
FVCO(1)
OSC2
OSC1
Primary Oscillator
R(2)
POSCMD<1:0>
FP(3)
÷ N
ROSEL RODIV<3:0>
REFCLKO
POSCCLK
RPn
F
OSC
Reference Clock Generation
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 152 2011-2013 Microchip Technology Inc.
9.1 CPU Clocking System
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X family of devices
provides six system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase Locked Loop (PLL)
• FRC Oscillator with Postscaler
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
Instruction execution speed or device operating
frequency, FCY, is given by Equation 9-1.
EQUATION 9-1: DEVICE OPERATING
FREQUENCY
Figure 9-2 is a block diagram of the PLL module.
Equation 9-2 provides the relationship between input
frequency (FIN) and output frequency (FOSC).
Equation 9-3 provides the relationship between input
frequency (FIN) and VCO frequency (FSYS).
FIGURE 9-2: PLL BLOCK DIAGRAM
EQUATION 9-2: FOSC CALCULATION
EQUATION 9-3: FVCO CALCULATION
FCY = Fosc/2
÷ N1
÷ M
÷ N2
PFD VCO
PLLPRE<4:0>
PLLDIV<8:0>
PLLPOST<1:0>
0.8 MHz < FPLLI(1) < 8.0 MHz
120 MHZ < FSYS(1) < 340 MHZ
FOSC(1) 120 MHz @ +125ºC
FIN FPLLI FSYS FOSC
Note 1: This frequency range must be met at all times.
FOSC(1) 140 MHz @ +85ºC
FOSC FIN M
N1N2
---------------------
FIN PLLDIV 2+
PLLPRE 2+2PLLPOST 1+
----------------------------------------------------------------------------------------
==
Where:
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
FSYS FIN M
N1
-------
FIN PLLDIV 2+
PLLPRE 2+
-------------------------------------
==
2011-2013 Microchip Technology Inc. DS70657G-page 153
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
9.2 Oscillator Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
9.2.1 KEY RESOURCES
•Section 7. “Oscillator” (DS70580)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See
Notes
Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2
Low-Power RC Oscillator (LPRC) Internal xx 101 1
Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011
Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011
Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010 1
Fast RC Oscillator (FRC) with Divide-by-N and
PLL (FRCPLL)
Internal xx 001 1
Fast RC Oscillator (FRC) Internal xx 000 1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 154 2011-2013 Microchip Technology Inc.
9.3 Oscillator Control Registers
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
—COSC<2:0>—NOSC<2:0>
(2)
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0
CLKLOCK IOLOCK LOCK —CF
(3)—— OSWEN
bit 7 bit 0
Legend: y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7 CLKLOCK: Clock Lock Enable bit
1 = If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and
PLL configurations may be modified
0 = Clock and PLL selections are not locked, configurations may be modified
bit 6 IOLOCK: I/O Lock Enable bit
1 = I/O lock is active
0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70580) in the
“dsPIC33E/PIC24E Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and trigger an oscillator failure trap.
2011-2013 Microchip Technology Inc. DS70657G-page 155
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 4 Unimplemented: Read as ‘0’
bit 3 CF: Clock Fail Detect bit(3)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
bit 2-1 Unimplemented: Read as ‘0’
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70580) in the
“dsPIC33E/PIC24E Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and trigger an oscillator failure trap.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 156 2011-2013 Microchip Technology Inc.
REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
ROI DOZE<2:0>(1)DOZEN(2,3)FRCDIV<2:0>
bit 15 bit 8
R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLLPOST<1:0> — PLLPRE<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set
to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(1)
111 = FCY divided by 128
110 = FCY divided by 64
101 = FCY divided by 32
100 = FCY divided by 16
011 = FCY divided by 8 (default)
010 = FCY divided by 4
001 = FCY divided by 2
000 = FCY divided by 1
bit 11 DOZEN: Doze Mode Enable bit(2,3)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio is forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default)
bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
01 = Output divided by 4 (default)
00 = Output divided by 2
bit 5 Unimplemented: Read as ‘0’
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
2011-2013 Microchip Technology Inc. DS70657G-page 157
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
•
•
•
00001 = Input divided by 3
00000 = Input divided by 2 (default)
REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 158 2011-2013 Microchip Technology Inc.
REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —PLLDIV<8>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
PLLDIV<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2
2011-2013 Microchip Technology Inc. DS70657G-page 159
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation of 1.453% (7.477 MHz)
011110 = Center frequency + 1.406% (7.474 MHz)
000001 = Center frequency + 0.047% (7.373 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency – 0.047% (7.367 MHz)
100001 = Center frequency – 1.453% (7.263 MHz)
100000 = Minimum frequency deviation of -1.5% (7.259 MHz)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 160 2011-2013 Microchip Technology Inc.
REGISTER 9-5: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON — ROSSLP ROSEL RODIV<3:0>(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator output is enabled on REFCLK pin(2)
0 = Reference oscillator output is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to run in Sleep
0 = Reference oscillator output is disabled in Sleep
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal used as the reference clock
0 = System clock used as the reference clock
bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1)
1111 = Reference clock divided by 32,768
1110 = Reference clock divided by 16,384
1101 = Reference clock divided by 8,192
1100 = Reference clock divided by 4,096
1011 = Reference clock divided by 2,048
1010 = Reference clock divided by 1,024
1001 = Reference clock divided by 512
1000 = Reference clock divided by 256
0111 = Reference clock divided by 128
0110 = Reference clock divided by 64
0101 = Reference clock divided by 32
0100 = Reference clock divided by 16
0011 = Reference clock divided by 8
0010 = Reference clock divided by 4
0001 = Reference clock divided by 2
0000 = Reference clock
bit 7-0 Unimplemented: Read as ‘0’
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.
2011-2013 Microchip Technology Inc. DS70657G-page 161
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
10.0 POWER-SAVING FEATURES
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices provide
the ability to manage power consumption by
selectively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and
a reduction in the number of peripherals being
clocked constitutes lower consumed power.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices can manage
power consumption in four ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
10.1 Clock Frequency and Clock
Switching
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or high-
precision oscillators by simply changing the NOSCx
bits (OSCCON<10:8>). The process of changing a
system clock during operation, as well as limitations to
the process, are discussed in more detail in
Section 9.0 “Oscillator Configuration”.
10.2 Instruction-Based Power-Saving
Modes
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices have two
special power-saving modes that are entered
through the execution of a special PWRSAV
instruction. Sleep mode stops clock operation and
halts all code execution. Idle mode halts the CPU
and code execution, but allows peripheral modules
to continue operation. The assembler syntax of the
PWRSAV instruction is shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 9. “Watchdog Timer and
Power-Saving Modes” (DS70615) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
PWRSAV #SLEEP_MODE ; Put the device into Sleep mode
PWRSAV #IDLE_MODE ; Put the device into Idle mode
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 162 2011-2013 Microchip Technology Inc.
10.2.1 SLEEP MODE
The following occurs in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals can continue
to operate. This includes items such as the Input
Change Notification (ICN) on the I/O ports or
peripherals that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled.
The device wakes up from Sleep mode on any of these
events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
For optimal power savings, the internal regulator and
the Flash regulator can be configured to go into
Standby when Sleep mode is entered by clearing the
VREGS (RCON<8>) and VREGSF (RCON<11>) bits
(default configuration).
If the application requires a faster wake-up time, and
can accept higher current requirements, the VREGS
(RCON<8>) and VREGSF (RCON<11>) bits can be set
to keep the internal regulator and the Flash regulator
active during Sleep mode.
10.2.2 IDLE MODE
The following occurs in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device wakes from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAV instruction or the first instruction in the
Interrupt Service Routine (ISR).
All peripherals also have the option to discontinue
operation when Idle mode is entered to allow for
increased power savings. This option is selectable in
the control register of each peripheral; for example, the
TSIDL bit in the Timer1 Control register (T1CON<13>).
10.2.3 INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
2011-2013 Microchip Technology Inc. DS70657G-page 163
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
10.3 Doze Mode
The preferred strategies for reducing power consumption
are changing clock speed and invoking one of the power-
saving modes. In some circumstances, this cannot be
practical. For example, it may be necessary for an
application to maintain uninterrupted synchronous
communication, even while it is doing nothing else.
Reducing system clock speed can introduce
communication errors, while using a power-saving mode
can stop communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible configu-
rations, from 1:1 to 1:128, with 1:1 being the default
setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the ECAN™ module has been configured
for 500 kbps, based on this device operating speed. If
the device is placed in Doze mode with a clock fre-
quency ratio of 1:4, the ECAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
10.4 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have effect and read
values are invalid.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC® DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
10.5 Power-Saving Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
10.5.1 KEY RESOURCES
•Section 9. “Watchdog Timer and Power-Saving
Modes” (DS70615)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable
module operation).
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 164 2011-2013 Microchip Technology Inc.
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
T5MD T4MD T3MD T2MD T1MD QEI1MD(1)PWMMD(1)—
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
I2C1MD U2MD U1MD SPI2MD SPI1MD —C1MD
(2)AD1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 T5MD: Timer5 Module Disable bit
1 = Timer5 module is disabled
0 = Timer5 module is enabled
bit 14 T4MD: Timer4 Module Disable bit
1 = Timer4 module is disabled
0 = Timer4 module is enabled
bit 13 T3MD: Timer3 Module Disable bit
1 = Timer3 module is disabled
0 = Timer3 module is enabled
bit 12 T2MD: Timer2 Module Disable bit
1 = Timer2 module is disabled
0 = Timer2 module is enabled
bit 11 T1MD: Timer1 Module Disable bit
1 = Timer1 module is disabled
0 = Timer1 module is enabled
bit 10 QEI1MD: QEI1 Module Disable bit(1)
1 = QEI1 module is disabled
0 = QEI1 module is enabled
bit 9 PWMMD: PWM Module Disable bit(1)
1 = PWM module is disabled
0 = PWM module is enabled
bit 8 Unimplemented: Read as ‘0’
bit 7 I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6 U2MD: UART2 Module Disable bit
1 = UART2 module is disabled
0 = UART2 module is enabled
bit 5 U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4 SPI2MD: SPI2 Module Disable bit
1 = SPI2 module is disabled
0 = SPI2 module is enabled
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 165
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 3 SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
bit 2 Unimplemented: Read as ‘0’
bit 1 C1MD: ECAN1 Module Disable bit(2)
1 = ECAN1 module is disabled
0 = ECAN1 module is enabled
bit 0 AD1MD: ADC1 Module Disable bit
1 = ADC1 module is disabled
0 = ADC1 module is enabled
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 166 2011-2013 Microchip Technology Inc.
REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— IC4MD IC3MD IC2MD IC1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— OC4MD OC3MD OC2MD OC1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11 IC4MD: Input Capture 4 Module Disable bit
1 = Input Capture 4 module is disabled
0 = Input Capture 4 module is enabled
bit 10 IC3MD: Input Capture 3 Module Disable bit
1 = Input Capture 3 module is disabled
0 = Input Capture 3 module is enabled
bit 9 IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled
0 = Input Capture 2 module is enabled
bit 8 IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
bit 7-4 Unimplemented: Read as ‘0’
bit 3 OC4MD: Output Compare 4 Module Disable bit
1 = Output Compare 4 module is disabled
0 = Output Compare 4 module is enabled
bit 2 OC3MD: Output Compare 3 Module Disable bit
1 = Output Compare 3 module is disabled
0 = Output Compare 3 module is enabled
bit 1 OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
bit 0 OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
2011-2013 Microchip Technology Inc. DS70657G-page 167
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
— — — — —CMPMD— —
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
CRCMD — — — — — I2C2MD —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled
bit 9-8 Unimplemented: Read as ‘0’
bit 7 CRCMD: CRC Module Disable bit
1 = CRC module is disabled
0 = CRC module is enabled
bit 6-2 Unimplemented: Read as ‘0’
bit 1 I2C2MD: I2C2 Module Disable bit
1 = I2C2 module is disabled
0 = I2C2 module is enabled
bit 0 Unimplemented: Read as ‘0’
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0
————REFOMDCTMUMD— —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 REFOMD: Reference Clock Module Disable bit
1 = Reference clock module is disabled
0 = Reference clock module is enabled
bit 2 CTMUMD: CTMU Module Disable bit
1 = CTMU module is disabled
0 = CTMU module is enabled
bit 1-0 Unimplemented: Read as ‘0’
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 168 2011-2013 Microchip Technology Inc.
REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — —PWM3MD
(1)PWM2MD(1)PWM1MD(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 PWM3MD: PWM3 Module Disable bit(1)
1 = PWM3 module is disabled
0 = PWM3 module is enabled
bit 9 PWM2MD: PWM2 Module Disable bit(1)
1 = PWM2 module is disabled
0 = PWM2 module is enabled
bit 8 PWM1MD: PWM1 Module Disable bit(1)
1 = PWM1 module is disabled
0 = PWM1 module is enabled
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This bit is available on dsPIC33EPXXXMC50X/20X and PIC24EPXXXMC20X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 169
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
— — —
DMA0MD(1)
PTGMD — — —
DMA1MD(1)
DMA2MD(1)
DMA3MD(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 DMA0MD: DMA0 Module Disable bit(1)
1 = DMA0 module is disabled
0 = DMA0 module is enabled
DMA1MD: DMA1 Module Disable bit(1)
1 = DMA1 module is disabled
0 = DMA1 module is enabled
DMA2MD: DMA2 Module Disable bit(1)
1 = DMA2 module is disabled
0 = DMA2 module is enabled
DMA3MD: DMA3 Module Disable bit(1)
1 = DMA3 module is disabled
0 = DMA3 module is enabled
bit 3 PTGMD: PTG Module Disable bit
1 = PTG module is disabled
0 = PTG module is enabled
bit 2-0 Unimplemented: Read as ‘0’
Note 1: This single bit enables and disables all four DMA channels.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 170 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 171
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
11.0 I/O PORTS
Many of the device pins are shared among the peripher-
als and the parallel I/O ports. All I/O input ports feature
Schmitt Trigger inputs for improved noise immunity.
11.1 Parallel I/O (PIO) Ports
Generally, a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1
illustrates how ports are shared with other peripherals
and the associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as a
general purpose output pin is disabled. The I/O pin can
be read, but the output driver for the parallel port bit is
disabled. If a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin can be driven by a port.
All port pins have eight registers directly associated with
their operation as digital I/O. The data direction register
(TRISx) determines whether the pin is an input or an out-
put. If the data direction bit is a ‘1’, then the pin is an input.
All port pins are defined as inputs after a Reset. Reads
from the latch (LATx) read the latch. Writes to the latch
write the latch. Reads from the port (PORTx) read the
port pins, while writes to the port pins write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device is disabled.
This means the corresponding LATx and TRISx
registers and the port pin are read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 10. “I/O Ports” (DS70598) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
QD
CK
WR LAT +
TRIS Latch
I/O Pin
WR Port
Data Bus
QD
CK
Data Latch
Read Port
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data Output Enable
Peripheral Input Data
I/O
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Output Data
Input Data
Peripheral Module Enable
Read LAT
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 172 2011-2013 Microchip Technology Inc.
11.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs other than VDD by using external pull-up
resistors. The maximum open-drain voltage allowed
on any pin is the same as the maximum VIH
specification for that particular pin.
See the “Pin Diagrams” section for the available
5V tolerant pins and Table 3 0-11 for the maximum
VIH specification for each pin.
11.2 Configuring Analog and Digital
Port Pins
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs or outputs must have their corresponding
ANSEL and TRIS bits set. In order to use port pins for
I/O functionality with digital modules, such as Timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
Pins with analog functions affected by the ANSELx
registers are listed with a buffer type of analog in the
Pinout I/O Descriptions (see Table 1-1).
If the TRIS bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
comparator module.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
11.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP, as shown in Example 11-1.
11.3 Input Change Notification (ICN)
The Input Change Notification function of the I/O ports
allows devices to generate interrupt requests to the
processor in response to a Change-of-State (COS) on
selected input pins. This feature can detect input
Change-of-States even in Sleep mode, when the clocks
are disabled. Every I/O port pin can be selected
(enabled) for generating an interrupt request on a
Change-of-State.
Three control registers are associated with the CN
functionality of each I/O port. The CNENx registers
contain the CN interrupt enable control bits for each of
the input pins. Setting any of these bits enables a CN
interrupt for the corresponding pins.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups and pull-
downs act as a current source or sink source
connected to the pin and eliminate the need for
external resistors when push-button, or keypad
devices are connected. The pull-ups and pull-downs
are enabled separately, using the CNPUx and the
CNPDx registers, which contain the control bits for
each of the pins. Setting any of the control bits
enables the weak pull-ups and/or pull-downs for the
corresponding pins.
EXAMPLE 11-1: PORT WRITE/READ
EXAMPLE
Note: Pull-ups and pull-downs on change notifi-
cation pins should always be disabled
when the port pin is configured as a digital
output.
MOV 0xFF00, W0 ; Configure PORTB<15:8>
; as inputs
MOV W0, TRISB ; and PORTB<7:0>
; as outputs
NOP ; Delay 1 cycle
BTSS PORTB, #13 ; Next Instruction
2011-2013 Microchip Technology Inc. DS70657G-page 173
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
11.4 Peripheral Pin Select (PPS)
A major challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. The
challenge is even greater on low pin count devices. In
an application where more than one peripheral needs
to be assigned to a single pin, inconvenient work-
arounds in application code, or a complete redesign,
may be the only option.
Peripheral Pin Select configuration provides an
alternative to these choices by enabling peripheral set
selection and their placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, users can better tailor the device to
their entire application, rather than trimming the
application to fit the device.
The Peripheral Pin Select configuration feature oper-
ates over a fixed subset of digital I/O pins. Users may
independently map the input and/or output of most dig-
ital peripherals to any one of these I/O pins. Hardware
safeguards are included that prevent accidental or
spurious changes to the peripheral mapping once it has
been established.
11.4.1 AVAILABLE PINS
The number of available pins is dependent on the
particular device and its pin count. Pins that support the
Peripheral Pin Select feature include the label, “RPn” or
“RPIn”, in their full pin designation, where “n” is the
remappable pin number. “RP” is used to designate pins
that support both remappable input and output
functions, while “RPI” indicates pins that support
remappable input functions only.
11.4.2 AVAILABLE PERIPHERALS
The peripherals managed by the Peripheral Pin Select
are all digital-only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.
In comparison, some digital-only peripheral modules
are never included in the Peripheral Pin Select feature.
This is because the peripheral’s function requires
special I/O circuitry on a specific port and cannot be
easily connected to multiple pins. These modules
include I2C™ and the PWM. A similar requirement
excludes all modules with analog inputs, such as the
ADC Converter.
A key difference between remappable and non-
remappable peripherals is that remappable peripherals
are not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
11.4.3 CONTROLLING PERIPHERAL PIN
SELECT
Peripheral Pin Select features are controlled through
two sets of SFRs: one to map peripheral inputs and one
to map outputs. Because they are separately con-
trolled, a particular peripheral’s input and output (if the
peripheral has both) can be placed on any selectable
function pin without constraint.
The association of a peripheral to a peripheral-
selectable pin is handled in two different ways,
depending on whether an input or output is being
mapped.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 174 2011-2013 Microchip Technology Inc.
11.4.4 INPUT MAPPING
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. That is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-1
through Register 11-17). Each register contains sets of
7-bit fields, with each set associated with one of the
remappable peripherals. Programming a given periph-
eral’s bit field with an appropriate 7-bit value maps the
RPn pin with the corresponding value to that peripheral.
For any given device, the valid range of values for any
bit field corresponds to the maximum number of
Peripheral Pin Selections supported by the device.
For example, Figure 11-2 illustrates remappable pin
selection for the U1RX input.
FIGURE 11-2: REMAPPABLE INPUT FOR
U1RX
11.4.4.1 Virtual Connections
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices support virtual
(internal) connections to the output of the op amp/
comparator module (see Figure 25-1 in Section 25.0
“Op Amp/Comparator Module”), and the PTG
module (see Section 24.0 “Peripheral Trigger
Generator (PTG) Module”).
In addition, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X devices support virtual connec-
tions to the filtered QEI module inputs: FINDX1,
FHOME1, FINDX2 and FHOME2 (see Figure 17-1
in Section 17.0 “Quadrature Encoder Interface
(QEI) Module (dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X Devices Only)”.
Virtual connections provide a simple way of inter-
peripheral connection without utilizing a physical pin.
For example, by setting the FLT1R<6:0> bits of the
RPINR12 register to the value of ‘b0000001, the
output of the analog comparator, C1OUT, will be
connected to the PWM Fault 1 input, which allows the
analog comparator to trigger PWM Faults without the
use of an actual physical pin on the device.
Virtual connection to the QEI module allows
peripherals to be connected to the QEI digital filter
input. To utilize this filter, the QEI module must be
enabled and its inputs must be connected to a physical
RPn pin. Example 11-2 illustrates how the input
capture module can be connected to the QEI digital
filter.
EXAMPLE 11-2: CONNECTING IC1 TO THE HOME1 QEI1 DIGITAL FILTER INPUT ON PIN 43 OF
THE dsPIC33EPXXXMC206 DEVICE
RP0
RP1
RP3
0
1
2
U1RX Input
U1RXR<6:0>
to Peripheral
RPn
n
Note: For input only, Peripheral Pin Select func-
tionality does not have priority over TRISx
settings. Therefore, when configuring an
RPn pin for input, the corresponding bit in
the TRISx register must also be configured
for input (set to ‘1’).
RPINR15 = 0x2500; /* Connect the QEI1 HOME1 input to RP37 (pin 43) */
RPINR7 = 0x009; /* Connect the IC1 input to the digital filter on the FHOME1 input */
QEI1IOC = 0x4000; /* Enable the QEI digital filter */
QEI1CON = 0x8000; /* Enable the QEI module */
2011-2013 Microchip Technology Inc. DS70657G-page 175
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Input Name(1)Function Name Register Configuration Bits
External Interrupt 1 INT1 RPINR0 INT1R<6:0>
External Interrupt 2 INT2 RPINR1 INT2R<6:0>
Timer2 External Clock T2CK RPINR3 T2CKR<6:0>
Input Capture 1 IC1 RPINR7 IC1R<6:0>
Input Capture 2 IC2 RPINR7 IC2R<6:0>
Input Capture 3 IC3 RPINR8 IC3R<6:0>
Input Capture 4 IC4 RPINR8 IC4R<6:0>
Output Compare Fault A OCFA RPINR11 OCFAR<6:0>
PWM Fault 1(3) FLT1 RPINR12 FLT1R<6:0>
PWM Fault 2(3) FLT2 RPINR12 FLT2R<6:0>
QEI1 Phase A(3) QEA1 RPINR14 QEA1R<6:0>
QEI1 Phase B(3) QEB1 RPINR14 QEB1R<6:0>
QEI1 Index(3) INDX1 RPINR15 INDX1R<6:0>
QEI1 Home(3) HOME1 RPINR15 HOM1R<6:0>
UART1 Receive U1RX RPINR18 U1RXR<6:0>
UART2 Receive U2RX RPINR19 U2RXR<6:0>
SPI2 Data Input SDI2 RPINR22 SDI2R<6:0>
SPI2 Clock Input SCK2 RPINR22 SCK2R<6:0>
SPI2 Slave Select SS2 RPINR23 SS2R<6:0>
CAN1 Receive(2)C1RX RPINR26 C1RXR<6:0>
PWM Synch Input 1(3)SYNCI1 RPINR37 SYNCI1R<6:0>
PWM Dead-Time Compensation 1(3)DTCMP1 RPINR38 DTCMP1R<6:0>
PWM Dead-Time Compensation 2(3)DTCMP2 RPINR39 DTCMP2R<6:0>
PWM Dead-Time Compensation 3(3)DTCMP3 RPINR39 DTCMP3R<6:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
2: This input source is available on dsPIC33EPXXXGP/MC50X devices only.
3: This input source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 176 2011-2013 Microchip Technology Inc.
TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES
Peripheral Pin
Select Input
Register Value
Input/
Output Pin Assignment
Peripheral Pin
Select Input
Register Value
Input/
Output Pin Assignment
000 0000 IV
SS 010 1101 IRPI45
000 0001 IC1OUT
(1) 010 1110 IRPI46
000 0010 IC2OUT
(1)010 1111 IRPI47
000 0011 IC3OUT
(1)011 0000 — —
000 0100 IC4OUT
(1)011 0001 — —
000 0101 — — 011 0010 — —
000 0110 IPTGO30
(1)011 0011 IRPI51
000 0111 IPTGO31
(1)011 0100 IRPI52
000 1000 I FINDX1(1,2) 011 0101 IRPI53
000 1001 IFHOME1
(1,2) 011 0110 I/O RP54
000 1010 — — 011 0111 I/O RP55
000 1011 — — 011 1000 I/O RP56
000 1100 — — 011 1001 I/O RP57
000 1101 — — 011 1010 IRPI58
000 1110 — — 011 1011 — —
000 1111 — — 011 1100 — —
001 0000 — — 011 1101 — —
001 0001 — — 011 1110 — —
001 0010 — — 011 1111 — —
001 0011 — — 100 0000 — —
001 0100 I/O RP20 100 0001 — —
001 0101 — — 100 0010 — —
001 0110 — — 100 0011 — —
001 0111 — — 100 0100 — —
001 1000 IRPI24 100 0101 — —
001 1001 IRPI25 100 0110 — —
001 1010 — — 100 0111 — —
001 1011 IRPI27 100 1000 — —
001 1100 IRPI28 100 1001 — —
001 1101 — — 100 1010 — —
001 1110 — — 100 1011 — —
001 1111 — — 100 1100 — —
010 0000 IRPI32 100 1101 — —
010 0001 IRPI33 100 1110 — —
010 0010 IRPI34 100 1111 — —
010 0011 I/O RP35 101 0000 — —
010 0100 I/O RP36 101 0001 — —
010 0101 I/O RP37 101 0010 — —
010 0110 I/O RP38 101 0011 — —
010 0111 I/O RP39 101 0100 — —
Legend: Shaded rows indicate PPS Input register values that are unimplemented.
Note 1: See Section 11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment.
2: These inputs are available on dsPIC33EPXXXGP/MC50X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 177
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
010 1000 I/O RP40 101 0101 — —
010 1001 I/O RP41 101 0110 — —
010 1010 I/O RP42 101 0111 — —
010 1011 I/O RP43 101 1000 — —
010 1100 IRPI44 101 1001 — —
101 1010 — — 110 1101 — —
101 1011 — — 110 1110 — —
101 1100 — — 110 1111 — —
101 1101 — — 111 0000 — —
101 1110 IRPI94 111 0001 — —
101 1111 IRPI95 111 0010 — —
110 0000 IRPI96 111 0011 — —
110 0001 I/O RP97 111 0100 — —
110 0010 — — 111 0101 — —
110 0011 — — 111 0110 I/O RP118
110 0100 — — 111 0111 IRPI119
110 0101 — — 111 1000 I/O RP120
110 0110 — — 111 1001 IRPI121
110 0111 — — 111 1010 — —
110 1000 — — 111 1011 — —
110 1001 — — 111 1100 — —
110 1010 — — 111 1101 — —
110 1011 — — 111 1110 — —
110 1100 — — 111 1111 — —
TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED)
Peripheral Pin
Select Input
Register Value
Input/
Output Pin Assignment
Peripheral Pin
Select Input
Register Value
Input/
Output Pin Assignment
Legend: Shaded rows indicate PPS Input register values that are unimplemented.
Note 1: See Section 11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment.
2: These inputs are available on dsPIC33EPXXXGP/MC50X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 178 2011-2013 Microchip Technology Inc.
11.4.4.2 Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 6-bit fields, with each set associated with one RPn
pin (see Register 11-18 through Register 11-27). The
value of the bit field corresponds to one of the periph-
erals and that peripheral’s output is mapped to the pin
(see Table 11-3 and Figure 11-3).
A null output is associated with the output register
Reset value of ‘0’. This is done to ensure that remap-
pable outputs remain disconnected from all output pins
by default.
FIGURE 11-3: MULTIPLEXING REMAPPABLE
OUTPUT FOR RPn
11.4.4.3 Mapping Limitations
The control schema of the peripheral select pins is not lim-
ited to a small range of fixed peripheral configurations.
There are no mutual or hardware-enforced lockouts
between any of the peripheral mapping SFRs. Literally
any combination of peripheral mappings across any or all
of the RPn pins is possible. This includes both many-to-
one and one-to-many mappings of peripheral inputs and
outputs to pins. While such mappings may be technically
possible from a configuration point of view, they may not
be supportable from an electrical point of view.
RPnR<5:0>
0
49
1
Default
U1TX Output
SDO2 Output 2
REFCLKO Output
48
QEI1CCMP Output
Output Data RPn
TABLE 11-3: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Function RPnR<5:0> Output Name
Default PORT 000000 RPn tied to Default Pin
U1TX 000001 RPn tied to UART1 Transmit
U2TX 000011 RPn tied to UART2 Transmit
SDO2 001000 RPn tied to SPI2 Data Output
SCK2 001001 RPn tied to SPI2 Clock Output
SS2 001010 RPn tied to SPI2 Slave Select
C1TX(2)001110 RPn tied to CAN1 Transmit
OC1 010000 RPn tied to Output Compare 1 Output
OC2 010001 RPn tied to Output Compare 2 Output
OC3 010010 RPn tied to Output Compare 3 Output
OC4 010011 RPn tied to Output Compare 4 Output
C1OUT 011000 RPn tied to Comparator Output 1
C2OUT 011001 RPn tied to Comparator Output 2
C3OUT 011010 RPn tied to Comparator Output 3
SYNCO1(1)101101 RPn tied to PWM Primary Time Base Sync Output
QEI1CCMP(1)101111 RPn tied to QEI 1 Counter Comparator Output
REFCLKO 110001 RPn tied to Reference Clock Output
C4OUT 110010 RPn tied to Comparator Output 4
Note 1: This function is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2: This function is available in dsPIC33EPXXXGP/MC50X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 179
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
11.5 I/O Helpful Tips
1. In some cases, certain pins, as defined in
Table 30-11, under “Injection Current”, have inter-
nal protection diodes to VDD and VSS. The term,
“Injection Current”, is also referred to as “Clamp
Current”. On designated pins, with sufficient exter-
nal current-limiting precautions by the user, I/O pin
input voltages are allowed to be greater or less
than the data sheet absolute maximum ratings,
with respect to the VSS and VDD supplies. Note
that when the user application forward biases
either of the high or low side internal input clamp
diodes, that the resulting current being injected
into the device, that is clamped internally by the
VDD and VSS power rails, may affect the ADC
accuracy by four to six counts.
2. I/O pins that are shared with any analog input pin
(i.e., ANx) are always analog pins by default after
any Reset. Consequently, configuring a pin as an
analog input pin automatically disables the digital
input pin buffer and any attempt to read the digital
input level by reading PORTx or LATx will always
return a ‘0’, regardless of the digital logic level on
the pin. To use a pin as a digital I/O pin on a shared
ANx pin, the user application needs to configure the
Analog Pin Configuration registers in the I/O ports
module (i.e., ANSELx) by setting the appropriate bit
that corresponds to that I/O port pin to a ‘0’.
3. Most I/O pins have multiple functions. Referring to
the device pin diagrams in this data sheet, the prior-
ities of the functions allocated to any pins are
indicated by reading the pin name from left-to-right.
The left most function name takes precedence over
any function to its right in the naming convention.
For example: AN16/T2CK/T7CK/RC1. This indi-
cates that AN16 is the highest priority in this
example and will supersede all other functions to its
right in the list. Those other functions to its right,
even if enabled, would not work as long as any
other function to its left was enabled. This rule
applies to all of the functions listed for a given pin.
4. Each pin has an internal weak pull-up resistor and
pull-down resistor that can be configured using the
CNPUx and CNPDx registers, respectively. These
resistors eliminate the need for external resistors
in certain applications. The internal pull-up is up to
~(VDD – 0.8), not VDD. This value is still above the
minimum VIH of CMOS and TTL devices.
5. When driving LEDs directly, the I/O pin can source
or sink more current than what is specified in the
VOH/IOH and VOL/IOL DC characteristic specifica-
tion. The respective IOH and IOL current rating only
applies to maintaining the corresponding output at
or above the VOH, and at or below the VOL levels.
However, for LEDs, unlike digital inputs of an
externally connected device, they are not gov-
erned by the same minimum VIH/VIL levels. An I/O
pin output can safely sink or source any current
less than that listed in the absolute maximum
rating section of this data sheet. For example:
VOH = 2.4v @ IOH = -8 mA and VDD = 3.3V
The maximum output current sourced by any 8 mA
I/O pin = 12 mA.
LED source current < 12 mA is technically
permitted. Refer to the VOH/IOH graphs in
Section 30.0 “Electrical Characteristics” for
additional information.
6. The Peripheral Pin Select (PPS) pin mapping rules
are as follows:
a) Only one “output” function can be active on
a given pin at any time, regardless if it is a
dedicated or remappable function (one pin,
one output).
b) It is possible to assign a “remappable output”
function to multiple pins and externally short or
tie them together for increased current drive.
c) If any “dedicated output” function is enabled
on a pin, it will take precedence over any
remappable “output” function.
d) If any “dedicated digital” (input or output) func-
tion is enabled on a pin, any number of “input”
remappable functions can be mapped to the
same pin.
e) If any “dedicated analog” function(s) are
enabled on a given pin, “digital input(s)” of any
kind will all be disabled, although a single “dig-
ital output”, at the user’s cautionary discretion,
can be enabled and active as long as there is
no signal contention with an external analog
input signal. For example, it is possible for the
ADC to convert the digital output logic level, or
to toggle a digital output on a comparator or
ADC input provided there is no external
analog input, such as for a built-in self-test.
f) Any number of “input” remappable functions
can be mapped to the same pin(s) at the same
time, including to any pin with a single output
from either a dedicated or remappable “output”.
Note: Although it is not possible to use a digital
input pin when its analog function is
enabled, it is possible to use the digital I/O
output function, TRISx = 0x0, while the
analog function is also enabled. However,
this is not recommended, particularly if the
analog input is connected to an external
analog voltage source, which would
create signal contention between the
analog signal and the output pin driver.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 180 2011-2013 Microchip Technology Inc.
g) The TRIS registers control only the digital I/O
output buffer. Any other dedicated or remappa-
ble active “output” will automatically override
the TRIS setting. The TRIS register does not
control the digital logic “input” buffer. Remap-
pable digital “inputs” do not automatically
override TRIS settings, which means that the
TRIS bit must be set to input for pins with only
remappable input function(s) assigned
h) All analog pins are enabled by default after any
Reset and the corresponding digital input
buffer on the pin has been disabled. Only the
Analog Pin Select registers control the digital
input buffer, not the TRIS register. The user
must disable the analog function on a pin using
the Analog Pin Select registers in order to use
any “digital input(s)” on a corresponding pin, no
exceptions.
11.6 I/O Ports Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
11.6.1 KEY RESOURCES
•Section 2. “I/O Ports” (DS70598)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 181
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
11.7 Peripheral Pin Select Registers
REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—INT1R<6:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 INT1R<6:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7-0 Unimplemented: Read as ‘0’
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DS70657G-page 182 2011-2013 Microchip Technology Inc.
REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—INT2R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-0 INT2R<6:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—T2CKR<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-0 T2CKR<6:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
2011-2013 Microchip Technology Inc. DS70657G-page 183
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— IC2R<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— IC1R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 IC2R<6:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7 Unimplemented: Read as ‘0’
bit 6-0 IC1R<6:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 184 2011-2013 Microchip Technology Inc.
REGISTER 11-5: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— IC4R<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— IC3R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 IC4R<6:0>: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7 Unimplemented: Read as ‘0’
bit 6-0 IC3R<6:0>: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
2011-2013 Microchip Technology Inc. DS70657G-page 185
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—OCFAR<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-0 OCFAR<6:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 186 2011-2013 Microchip Technology Inc.
REGISTER 11-7: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—FLT2R<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—FLT1R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 FLT2R<6:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7 Unimplemented: Read as ‘0’
bit 6-0 FLT1R<6:0>: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
2011-2013 Microchip Technology Inc. DS70657G-page 187
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-8: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— QEB1R<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— QEA1R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 QEB1R<6:0>: Assign B (QEB) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7 Unimplemented: Read as ‘0’
bit 6-0 QEA1R<6:0>: Assign A (QEA) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 188 2011-2013 Microchip Technology Inc.
REGISTER 11-9: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— HOME1R<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— INDX1R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 HOME1R<6:0>: Assign QEI1 HOME1 (HOME1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7 Unimplemented: Read as ‘0’
bit 6-0 IND1XR<6:0>: Assign QEI1 INDEX1 (INDX1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
2011-2013 Microchip Technology Inc. DS70657G-page 189
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-10: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—U1RXR<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-0 U1RXR<6:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
REGISTER 11-11: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—U2RXR<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-0 U2RXR<6:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 190 2011-2013 Microchip Technology Inc.
REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SCK2INR<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—SDI2R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8
SCK2INR
<6:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7 Unimplemented: Read as ‘0’
bit 6-0
SDI2R
<6:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
2011-2013 Microchip Technology Inc. DS70657G-page 191
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SS2R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 6-0
SS2R
<6:0>: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
REGISTER 11-14: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26
(dsPIC33EPXXXGP/MC50X DEVICES ONLY)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—C1RXR<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-0 C1RXR<6:0>: Assign CAN1 RX Input (CRX1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 192 2011-2013 Microchip Technology Inc.
REGISTER 11-15: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37
(dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SYNCI1R<6:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 SYNCI1R<6:0>: Assign PWM Synchronization Input 1 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7-0 Unimplemented: Read as ‘0’
2011-2013 Microchip Technology Inc. DS70657G-page 193
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-16: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38
(dsPIC33EPXXXMC02X AND PIC24EPXXXMC20X DEVICES ONLY)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—DTCMP1R<6:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 DTCMP1R<6:0>: Assign PWM Dead-Time Compensation Input 1 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7-0 Unimplemented: Read as ‘0’
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 194 2011-2013 Microchip Technology Inc.
REGISTER 11-17: RPINR39: PERIPHERAL PIN SELECT INPUT REGISTER 39
(dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—DTCMP3R<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—DTCMP2R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 DTCMP3R<6:0>: Assign PWM Dead-Time Compensation Input 3 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7 Unimplemented: Read as ‘0’
bit 6-0 DTCMP2R<6:0>: Assign PWM Dead-Time Compensation Input 2 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111001 = Input tied to RPI121
.
.
.
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
2011-2013 Microchip Technology Inc. DS70657G-page 195
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-18: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP35R<5:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP20R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP20R<5:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-19: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP37R<5:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP36R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP37R<5:0>: Peripheral Output Function is Assigned to RP37 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP36R<5:0>: Peripheral Output Function is Assigned to RP36 Output Pin bits
(see Table 11-3 for peripheral function numbers)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 196 2011-2013 Microchip Technology Inc.
REGISTER 11-20: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP39R<5:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP38R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP39R<5:0>: Peripheral Output Function is Assigned to RP39 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP38R<5:0>: Peripheral Output Function is Assigned to RP38 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-21: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP41R<5:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP40R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP41R<5:0>: Peripheral Output Function is Assigned to RP41 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP40R<5:0>: Peripheral Output Function is Assigned to RP40 Output Pin bits
(see Table 11-3 for peripheral function numbers)
2011-2013 Microchip Technology Inc. DS70657G-page 197
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-22: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP43R<5:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP42R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP43R<5:0>: Peripheral Output Function is Assigned to RP43 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP42R<5:0>: Peripheral Output Function is Assigned to RP42 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-23: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP55R<5:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP54R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP55R<5:0>: Peripheral Output Function is Assigned to RP55 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP54R<5:0>: Peripheral Output Function is Assigned to RP54 Output Pin bits
(see Table 11-3 for peripheral function numbers)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 198 2011-2013 Microchip Technology Inc.
REGISTER 11-24: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP57R<5:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP56R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP57R<5:0>: Peripheral Output Function is Assigned to RP57 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RP56R<5:0>: Peripheral Output Function is Assigned to RP56 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-25: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——RP97R<5:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP97R<5:0>: Peripheral Output Function is Assigned to RP97 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-0 Unimplemented: Read as ‘0’
2011-2013 Microchip Technology Inc. DS70657G-page 199
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 11-26: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP118R<5:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 RP118R<5:0>: Peripheral Output Function is Assigned to RP118 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-0 Unimplemented: Read as ‘0’
REGISTER 11-27: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— RP120R<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 RP120R<5:0>: Peripheral Output Function is Assigned to RP120 Output Pin bits
(see Table 11-3 for peripheral function numbers)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 200 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 201
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
12.0 TIMER1
The Timer1 module is a 16-bit timer that can operate as
a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated in Asynchronous Counter mode
from an external clock source
• The external clock input (T1CK) can optionally be
synchronized to the internal device clock and the
clock synchronization is performed after the prescaler
A block diagram of Timer1 is shown in Figure 12-1.
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
T1CON<2>
• Timer Gate Control bit (TGATE): T1CON<6>
Timer control bit setting for different operating modes
are given in the Table 12-1.
TABLE 12-1: TIMER MODE SETTINGS
FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70362) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Mode TCS TGATE TSYNC
Timer 00x
Gated Timer 01x
Synchronous
Counter
1x1
Asynchronous
Counter
1x0
TGATE
TCS
00
10
x1
PR1
TGATE
Set T1IF Flag
0
1
TSYNC
1
0
Sync
Equal
Reset
T1CK Prescaler
(/n)
TCKPS<1:0>
Gate
Sync
FP(1)
Falling Edge
Detect
TCKPS<1:0>
Note 1: FP is the peripheral clock.
Latch Data
CLK
T1CLK
CTMU
Edge Control
Logic
TMR1
Comparator
Prescaler
(/n)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 202 2011-2013 Microchip Technology Inc.
12.1 Timer1 Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
12.1.1 KEY RESOURCES
•Section 11. “Timers” (DS70362)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 203
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
12.2 Timer1 Control Register
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1)—TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
— TGATE TCKPS<1:0> — TSYNC(1)TCS(1)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer1 On bit(1)
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer1 Clock Source Select bit(1)
1 = External clock is from pin, T1CK (on the rising edge)
0 = Internal clock (FP)
bit 0 Unimplemented: Read as ‘0’
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 204 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 205
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
13.0 TIMER2/3 AND TIMER4/5
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent
16-bit timers with selectable operating modes.
As 32-bit timers, Timer2/3 and Timer4/5 operate in
three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and
Timer3) with all 16-Bit Operating modes (except
Asynchronous Counter mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
Modules (Timer2 and Timer3 only)
• ADC1 Event Trigger (32-bit timer pairs, and
Timer3 and Timer5 only)
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed previously, except for the event trigger;
this is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, and
T4CON, T5CON registers. T2CON and T4CON are
shown in generic form in Register 13-1. T3CON and
T5CON are shown in Register 13-2.
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word (lsw); Timer3 and Timer5
are the most significant word (msw) of the 32-bit timers.
A block diagram for an example 32-bit timer pair
(Timer2/3 and Timer4/5) is shown in Figure 13-3.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70362) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
Note: Only Timer2, 3, 4 and 5 can trigger a DMA
data transfer.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 206 2011-2013 Microchip Technology Inc.
FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2 AND 4)
FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3 AND 5)
Note 1: FP is the peripheral clock.
TGATE
TCS
00
10
x1
PRx
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
Gate
Sync
FP(1)
Falling Edge
Detect
TCKPS<1:0> Latch Data
CLK
TxCLK
TMRx
Comparator
Prescaler
(/n)
Prescaler
(/n) Sync
Note 1: FP is the peripheral clock.
2: The ADC trigger is available on TMR3 and TMR5 only.
TGATE
TCS
00
10
x1
PRx
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
Gate
Sync
FP(1)
Falling Edge
Detect
TCKPS<1:0> Latch Data
CLK
TxCLK
TMRx
Comparator
Prescaler
(/n)
Prescaler
(/n) Sync
ADC Start of
Conversion Trigger
(2)
2011-2013 Microchip Technology Inc. DS70657G-page 207
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 13-3: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
13.1 Timerx Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
13.1.1 KEY RESOURCES
•Section 11. “Timers” (DS70362)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
TGATE
TCS
00
10
x1
Comparator
TGATE
Set TyIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
FP(1)
TCKPS<1:0>
Note 1: The ADC trigger is available on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs.
2: Timerx is a Type B timer (x = 2 and 4).
3: Timery is a Type C timer (x = 3 and 5).
Latch
Data
CLK
ADC
PRx
TMRyHLD
Data Bus<15:0>
mswlsw
Prescaler
(/n)
Prescaler
(/n)
Sync
Gate
Sync
Falling Edge
Detect
PRy
TMRx TMRy
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 208 2011-2013 Microchip Technology Inc.
13.2 Timer Control Registers
REGISTER 13-1: TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON —TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
— TGATE TCKPS<1:0> T32 —TCS
(1)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timerx On bit
When T32 = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When T32 = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timerx Clock Source Select bit(1)
1 = External clock is from pin, TxCK (on the rising edge)
0 = Internal clock (FP)
bit 0 Unimplemented: Read as ‘0’
Note 1: The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
2011-2013 Microchip Technology Inc. DS70657G-page 209
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 13-2: TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1)—TSIDL
(2)— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
—TGATE
(1)TCKPS<1:0>(1)——TCS
(1,3)—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timery On bit(1)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timery Stop in Idle Mode bit(2)
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timery Clock Source Select bit(1,3)
1 = External clock is from pin, TyCK (on the rising edge)
0 = Internal clock (FP)
bit 0 Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all timers. See the “Pin Diagrams” section for the available pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 210 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 211
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
14.0 INPUT CAPTURE The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices support up
to four input capture channels.
Key features of the input capture module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 31 user-selectable
Trigger/Sync sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to six clock sources available for each module,
driving a separate internal 16-bit counter
FIGURE 14-1: INPUT CAPTURE x MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “Input Cap-
ture” (DS70352) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
ICxBUF
4-Level FIFO Buffer
ICx Pin
ICM<2:0>
Set ICxIF
Edge Detect Logic
ICI<1:0>
ICOV, ICBNE
Interrupt
Logic
System Bus
Prescaler
Counter
1:1/4/16
and
Clock Synchronizer
Event and
Trigger and
Sync Logic
Clock
Select
IC Clock
Sources
Trigger and
Sync Sources
ICTSEL<2:0>
SYNCSEL<4:0>
Trigger(1)
16
16
16
ICxTMR
Increment
Reset
Note 1: The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the Trigger/Sync source must be changed to another source option.
PTG Trigger
Input
CTMU Edge
Control Logic
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 212 2011-2013 Microchip Technology Inc.
14.1 Input Capture Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
14.1.1 KEY RESOURCES
•Section 12. “Input Capture” (DS70352)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 213
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
14.2 Input Capture Registers
REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
—— ICSIDL ICTSEL<2:0> — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/HC/HS-0 R/HC/HS-0 R/W-0 R/W-0 R/W-0
— ICI<1:0> ICOV ICBNE ICM<2:0>
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 ICSIDL: Input Capture Stop in Idle Control bit
1 = Input capture will Halt in CPU Idle mode
0 = Input capture will continue to operate in CPU Idle mode
bit 12-10 ICTSEL<12:10>: Input Capture Timer Select bits
111 = Peripheral clock (FP) is the clock source of the ICx
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the ICx
010 = T4CLK is the clock source of the ICx
001 = T2CLK is the clock source of the ICx
000 = T3CLK is the clock source of the ICx
bit 9-7 Unimplemented: Read as ‘0’
bit 6-5 ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0> = 001 or 111)
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture buffer overflow occurred
0 = No input capture buffer overflow occurred
bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture Mode Select bits
111 = Input capture functions as interrupt pin only in CPU Sleep and Idle modes (rising edge detect
only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Capture mode, every 16th rising edge (Prescaler Capture mode)
100 = Capture mode, every 4th rising edge (Prescaler Capture mode)
011 = Capture mode, every rising edge (Simple Capture mode)
010 = Capture mode, every falling edge (Simple Capture mode)
001 = Capture mode, every edge rising and falling (Edge Detect mode (ICI<1:0>) is not used in this mode)
000 = Input capture module is turned off
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 214 2011-2013 Microchip Technology Inc.
REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —IC32
bit 15 bit 8
R/W-0 R/W/HS-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1
ICTRIG(2)TRIGSTAT(3)— SYNCSEL<4:0>(4)
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 IC32: Input Capture 32-Bit Timer Mode Select bit (Cascade mode)
1 = Odd IC and Even IC form a single 32-bit input capture module(1)
0 = Cascade module operation is disabled
bit 7
ICTRIG:
Input Capture
Trigger Operation Select bit(2)
1
= Input source used to trigger the input capture timer (Trigger mode)
0 = Input source used to synchronize the input capture timer to a timer of another module
(Synchronization mode)
bit 6 TRIGSTAT: Timer Trigger Status bit(3)
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
bit 5 Unimplemented: Read as ‘0’
Note 1: The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set and
cleared in software.
4: Do not use the ICx module as its own Sync or Trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
6: Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO8 = IC1
PTGO9 = IC2
PTGO10 = IC3
PTGO11 = IC4
2011-2013 Microchip Technology Inc. DS70657G-page 215
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 4-0 SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4)
11111 = No Sync or Trigger source for ICx
11110 = Reserved
11101 = Reserved
11100 = CTMU module synchronizes or triggers ICx
11011 = ADC1 module synchronizes or triggers ICx(5)
11010 = CMP3 module synchronizes or triggers ICx(5)
11001 = CMP2 module synchronizes or triggers ICx(5)
11000 = CMP1 module synchronizes or triggers ICx(5)
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 module synchronizes or triggers ICx
10010 = IC3 module synchronizes or triggers ICx
10001 = IC2 module synchronizes or triggers ICx
10000 = IC1 module synchronizes or triggers ICx
01111 = Timer5 synchronizes or triggers ICx
01110 = Timer4 synchronizes or triggers ICx
01101 = Timer3 synchronizes or triggers ICx (default)
01100 = Timer2 synchronizes or triggers ICx
01011 = Timer1 synchronizes or triggers ICx
01010 = PTGOx module synchronizes or triggers ICx(6)
01001 = Reserved
01000 = Reserved
00111 = Reserved
00110 = Reserved
00101 = Reserved
00100 = OC4 module synchronizes or triggers ICx
00011 = OC3 module synchronizes or triggers ICx
00010 = OC2 module synchronizes or triggers ICx
00001 = OC1 module synchronizes or triggers ICx
00000 = No Sync or Trigger source for ICx
REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
Note 1: The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set and
cleared in software.
4: Do not use the ICx module as its own Sync or Trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
6: Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO8 = IC1
PTGO9 = IC2
PTGO10 = IC3
PTGO11 = IC4
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 216 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 217
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
15.0 OUTPUT COMPARE The Output Compare module can select one of eight
available clock sources for its time base. The module
compares the value of the timer with the value of one or
two compare registers depending on the operating
mode selected. The state of the output pin changes
when the timer value matches the compare register
value. The output compare module generates either a
single output pulse or a sequence of output pulses, by
changing the state of the output pin on the compare
match events. The output compare module can also
generate interrupts on compare match events and
trigger DMA data transfers.
FIGURE 15-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 13. “Output Compare”
(DS70358) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: See Section 13. “Output Compare”
(DS70358) in the “dsPIC33E/PIC24E
Family Reference Manual” for OCxR and
OCxRS register restrictions.
OCxR Buffer
Comparator
OCxTMR
OCxCON1
OCxCON2
OCx Interrupt
OCx Pin
OCxRS Buffer
Comparator
Match
Match
Trigger and
Sync Logic
Clock
Select
Increment
Reset
OC Clock
Sources
Trigger and
Sync Sources
Reset
Match Event
OCFA
OCxR
OCxRS
Event
Event
Rollover
Rollover/Reset
Rollover/Reset
OCx Synchronization/Trigger Event
OCFB
SYNCSEL<4:0>
Trigger
(1)
Note 1: The Trigger/Sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the Trigger/Sync source must be changed to another source option.
PTG Trigger Input
CTMU Edge
Control Logic
OC Output and
Fault Logic
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 218 2011-2013 Microchip Technology Inc.
15.1 Output Compare Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
15.1.1 KEY RESOURCES
•Section 13. “Output Compare” (DS70358)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 219
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
15.2 Output Compare Control Registers
REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
—— OCSIDL OCTSEL<2:0> —ENFLTB
bit 15 bit 8
R/W-0 U-0 R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0
ENFLTA — OCFLTB OCFLTA TRIGMODE OCM<2:0>
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x Halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-10 OCTSEL<2:0>: Output Compare x Clock Select bits
111 = Peripheral clock (FP)
110 = Reserved
101 = PTGOx clock(2)
100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the OCx
010 = T4CLK is the clock source of the OCx
001 = T3CLK is the clock source of the OCx
000 = T2CLK is the clock source of the OCx
bit 9 Unimplemented: Read as ‘0’
bit 8 ENFLTB: Fault B Input Enable bit
1 = Output Compare Fault B input (OCFB) is enabled
0 = Output Compare Fault B input (OCFB) is disabled
bit 7 ENFLTA: Fault A Input Enable bit
1 = Output Compare Fault A input (OCFA) is enabled
0 = Output Compare Fault A input (OCFA) is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 OCFLTB: PWM Fault B Condition Status bit
1 = PWM Fault B condition on OCFB pin has occurred
0 = No PWM Fault B condition on OCFB pin has occurred
bit 4 OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on OCFA pin has occurred
0 = No PWM Fault A condition on OCFA pin has occurred
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.
2: Each Output Compare x module (OCx) has one PTG clock source. See Section 24.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO4 = OC1
PTGO5 = OC2
PTGO6 = OC3
PTGO7 = OC4
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 220 2011-2013 Microchip Technology Inc.
bit 3 TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is cleared only by software
bit 2-0 OCM<2:0>: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when
OCxTMR = OCxRS(1)
110 = Edge-Aligned PWM mode: Output set high when OCxTMR = 0 and set low when OCxTMR = OCxR(1)
101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces
OCx pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces
OCx pin high
000 = Output compare channel is disabled
REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.
2: Each Output Compare x module (OCx) has one PTG clock source. See Section 24.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO4 = OC1
PTGO5 = OC2
PTGO6 = OC3
PTGO7 = OC4
2011-2013 Microchip Technology Inc. DS70657G-page 221
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
FLTMD FLTOUT FLTTRIEN OCINV — — —OC32
bit 15 bit 8
R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0
OCTRIG TRIGSTAT OCTRIS SYNCSEL<4:0>
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTx bit is
cleared in software and a new PWM period starts
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
bit 14 FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
bit 13 FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on a Fault condition
0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
bit 12 OCINV: Output Compare x Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 11-9 Unimplemented: Read as ‘0’
bit 8 OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
bit 7 OCTRIG: Output Compare x Trigger/Sync Select bit
1 = Triggers OCx from the source designated by the SYNCSELx bits
0 = Synchronizes OCx with the source designated by the SYNCSELx bits
bit 6 TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5 OCTRIS: Output Compare x Output Pin Direction Select bit
1 = OCx is tri-stated
0 = Output Compare x module drives the OCx pin
Note 1: Do not use the OCx module as its own Synchronization or Trigger source.
2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy
module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it.
3: Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0
“Peripheral Trigger Generator (PTG) Module” for more information.
PTGO0 = OC1
PTGO1 = OC2
PTGO2 = OC3
PTGO3 = OC4
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 222 2011-2013 Microchip Technology Inc.
bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111 = OCxRS compare event is used for synchronization
11110 = INT2 pin synchronizes or triggers OCx
11101 = INT1 pin synchronizes or triggers OCx
11100 = CTMU module synchronizes or triggers OCx
11011 = ADC1 module synchronizes or triggers OCx
11010 = CMP3 module synchronizes or triggers OCx
11001 = CMP2 module synchronizes or triggers OCx
11000 = CMP1 module synchronizes or triggers OCx
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 input capture event synchronizes or triggers OCx
10010 = IC3 input capture event synchronizes or triggers OCx
10001 = IC2 input capture event synchronizes or triggers OCx
10000 = IC1 input capture event synchronizes or triggers OCx
01111 = Timer5 synchronizes or triggers OCx
01110 = Timer4 synchronizes or triggers OCx
01101 = Timer3 synchronizes or triggers OCx
01100 = Timer2 synchronizes or triggers OCx (default)
01011 = Timer1 synchronizes or triggers OCx
01010 = PTGOx synchronizes or triggers OCx(3)
01001 = Reserved
01000 = Reserved
00111 = Reserved
00110 = Reserved
00101 = Reserved
00100 = OC4 module synchronizes or triggers OCx(1,2)
00011 = OC3 module synchronizes or triggers OCx(1,2)
00010 = OC2 module synchronizes or triggers OCx(1,2)
00001 = OC1 module synchronizes or triggers OCx(1,2)
00000 = No Sync or Trigger source for OCx
REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
Note 1: Do not use the OCx module as its own Synchronization or Trigger source.
2: When the OCy module is turned OFF, it sends a trigger out signal. If the OCx module uses the OCy
module as a Trigger source, the OCy module must be unselected as a Trigger source prior to disabling it.
3: Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0
“Peripheral Trigger Generator (PTG) Module” for more information.
PTGO0 = OC1
PTGO1 = OC2
PTGO2 = OC3
PTGO3 = OC4
2011-2013 Microchip Technology Inc. DS70657G-page 223
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
16.0 HIGH-SPEED PWM MODULE
(dsPIC33EPXXXMC20X/50X
AND PIC24EPXXXMC20X
DEVICES ONLY)
The dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X devices support a dedicated
Pulse-Width Modulation (PWM) module with up to
6 outputs.
The high-speed PWMx module consists of the
following major features:
• Three PWM generators
• Two PWM outputs per PWM generator
• Individual period and duty cycle for each PWM pair
• Duty cycle, dead time, phase shift and frequency
resolution of 8.32 ns
• Independent Fault and current-limit inputs for
six PWM outputs
• Redundant output
• Center-Aligned PWM mode
• Output override control
• Chop mode (also known as Gated mode)
• Special Event Trigger
• Prescaler for input clock
• PWMxL and PWMxH output pin swapping
• Independent PWM frequency, duty cycle and
phase-shift changes for each PWM generator
• Dead-time compensation
• Enhanced Leading-Edge Blanking (LEB)
functionality
• Frequency resolution enhancement
• PWM capture functionality
The high-speed PWMx module contains up to three
PWM generators. Each PWM generator provides two
PWM outputs: PWMxH and PWMxL. The master time
base generator provides a synchronous signal as a
common time base to synchronize the various PWM
outputs. The individual PWM outputs are available on
the output pins of the device. The input Fault signals
and current-limit signals, when enabled, can monitor
and protect the system by placing the PWM outputs
into a known “safe” state.
Each PWMx can generate a trigger to the ADC module
to sample the analog signal at a specific instance dur-
ing the PWM period. In addition, the high-speed PWMx
module also generates a Special Event Trigger to the
ADC module based on either of the two master time
bases.
The high-speed PWMx module can synchronize itself
with an external signal or can act as a synchronizing
source to any external device. The SYNCI1 input pin
that utilizes PPS, can synchronize the high-speed
PWMx module with an external signal. The SYNCO1
pin is an output pin that provides a synchronous signal
to an external device.
Figure 16-1 illustrates an architectural overview of the
high-speed PWMx module and its interconnection with
the CPU and other peripherals.
16.1 PWM Faults
The PWMx module incorporates multiple external Fault
inputs to include FLT1 and FLT2 which are re-
mappable using the PPS feature, FLT3 and FLT4 which
are available only on the larger 44-pin and 64-pin
packages, and FLT32 which has been implemented
with Class B safety features, and is available on a
fixed pin on all dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X devices.
These Faults provide a safe and reliable way to safely
shut down the PWM outputs when the Fault input is
asserted.
16.1.1 PWM FAULTS AT RESET
During any Reset event, the PWMx module maintains
ownership of the Class B Fault, FLT32. At Reset, this
Fault is enabled in Latched mode to ensure the fail-safe
power-up of the application. The application software
must clear the PWM Fault before enabling the high-
speed motor control PWMx module. To clear the Fault
condition, the FLT32 pin must first be pulled low
externally or the internal pull-down resistor in the
CNPDx register can be enabled.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “High-Speed
PWM” (DS70645) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: In Edge-Aligned PWM mode, the duty
cycle, dead time, phase shift and
frequency resolution are 8.32 ns.
Note: The Fault mode may be changed using
the FLTMOD<1:0> bits (FCLCON<1:0>),
regardless of the state of FLT32.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 224 2011-2013 Microchip Technology Inc.
16.1.2 WRITE-PROTECTED REGISTERS
On dsPIC33EPXXXMC20X/50X and
PIC24EPXXXMC20X devices, write protection is
implemented for the IOCONx and FCLCONx registers.
The write protection feature prevents any inadvertent
writes to these registers. This protection feature can be
controlled by the PWMLOCK Configuration bit
(FOSCSEL<6>). The default state of the write
protection feature is enabled (PWMLOCK = 1). The
write protection feature can be disabled by configuring,
PWMLOCK = 0.
To gain write access to these locked registers, the user
application must write two consecutive values of
(0xABCD and 0x4321) to the PWMKEY register to
perform the unlock operation. The write access to the
IOCONx or FCLCONx registers must be the next SFR
access following the unlock process. There can be no
other SFR accesses during the unlock process and
subsequent write access. To write to both the IOCONx
and FCLCONx registers requires two unlock operations.
The correct unlocking sequence is described in
Example 16-1.
EXAMPLE 16-1: PWMx WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
; FLT32 pin must be pulled low externally in order to clear and disable the fault
; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd,w10 ; Load first unlock key to w10 register
mov #0x4321,w11 ; Load second unlock key to w11 register
mov #0x0000,w0 ; Load desired value of FCLCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0,FCLCON1 ; Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register
; Writing to IOCON1 register requires unlock sequence
mov #0xabcd,w10 ; Load first unlock key to w10 register
mov #0x4321,w11 ; Load second unlock key to w11 register
mov #0xF000,w0 ; Load desired value of IOCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0,IOCON1 ; Write desired value to IOCON1 register
2011-2013 Microchip Technology Inc. DS70657G-page 225
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 16-1: HIGH-SPEED PWMx MODULE ARCHITECTURAL OVERVIEW
CPU
PWM
Generator 1
PWM
Generator 3
SYNCI1
SYNCO1
PWM1H
PWM1L
PWM1 Interrupt(1)
PWM2H
PWM2L
PWM2 Interrupt(1)
PWM3H
PWM3L
PWM3 Interrupt(1)
Synchronization Signal
Data Bus
ADC Module FLT1-FLT4, FLT32
Synchronization Signal
Synchronization Signal
Primary Trigger
Primary Special
DTCMP1-DTCMP3
Fault, Current-Limit and
Dead-Time Compensation
Event Trigger
Master Time Base
Fault, Current-Limit
and Dead-Time Compensation
Fault, Current-Limit
and Dead-Time Compensation
FOSC
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. Refer to the “dsPIC33E/PIC24E Family Reference Manual”, Section 14. “High-Speed
PWM” (DS70645) for more information.
PWM
Generator 2
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FIGURE 16-2: HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM
MUX
PTMRx
PDCx
PWMCONx,
PTCON, PTCON2
IOCONx
DTRx
PWMxL
PWMxH
FLTx
PWM1L
PWM1H
FCLCONx
MDC
PHASEx
LEBCONx,
ALTDTRx
User Override Logic
Current-Limit
PWM Output Mode
Control Logic
Logic
Pin
Control
Logic
Fault and
Current-Limit
Logic
PWM Generator 1
FLTx
PWM Generator 2 and PWM Generator 3
Interrupt
Logic(1)
Module Control and Timing
Master Duty Cycle Register
Synchronization Synchronization
Master PeriodMaster Period
Master Duty CycleMaster Duty Cycle
SYNCI1
SYNCO1
SEVTCMP
Comparator
Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR Primary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
Comparator
Dead-Time
Fault Override Logic
Override Logic
DTCMPx
DTCMP1
FOSC
PWMKEY IOCONx and FCLCONx Unlock Register
AUXCONx LEBDLYx
PTG Trigger
Input
PTG Trigger Input
PTG Trigger Input
TRGCONx
PWMCAPx
ADC Trigger
Comparator
TRIGx
16-Bit Data Bus
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. Refer to the “dsPIC33E/PIC24E Family Reference Manual”, Section 14. “High-Speed
PWM” (DS70645) for more information.
2011-2013 Microchip Technology Inc. DS70657G-page 227
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
16.2 PWM Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
16.2.1 KEY RESOURCES
•Section 14. “High-Speed PWM” (DS70645)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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16.3 PWMx Control Registers
REGISTER 16-1: PTCON: PWMx TIME BASE CONTROL REGISTER
R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN — PTSIDL SESTAT SEIEN EIPU(1)SYNCPOL(1)SYNCOEN(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN(1)SYNCSRC<2:0>(1)SEVTPS<3:0>(1)
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTEN: PWMx Module Enable bit
1 = PWMx module is enabled
0 = PWMx module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 PTSIDL: PWMx Time Base Stop in Idle Mode bit
1 = PWMx time base halts in CPU Idle mode
0 = PWMx time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWMx cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCI1/SYNCO1 polarity is inverted (active-low)
0 = SYNCI1/SYNCO1 is active-high
bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
2011-2013 Microchip Technology Inc. DS70657G-page 229
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)
111 = Reserved
•
•
•
100 = Reserved
011 = PTGO17(2)
010 = PTGO16(2)
001 = Reserved
000 = SYNCI 1 input from PPS
bit 3-0 SEVTPS<3:0>: PWMx Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event
REGISTER 16-1: PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED)
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 230 2011-2013 Microchip Technology Inc.
REGISTER 16-2: PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64
101 = Divide-by-32
100 = Divide-by-16
011 = Divide-by-8
010 = Divide-by-4
001 = Divide-by-2
000 = Divide-by-1, maximum PWMx timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2011-2013 Microchip Technology Inc. DS70657G-page 231
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-3: PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PTPER<15:8>
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
PTPER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits
REGISTER 16-4: SEVTCMP: PWMx PRIMARY SPECIAL EVENT COMPARE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 232 2011-2013 Microchip Technology Inc.
REGISTER 16-5: CHOP: PWMx CHOP CLOCK GENERATOR REGISTER
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN — — — — —CHOP<9:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHOP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10 Unimplemented: Read as ‘0’
bit 9-0 CHOP<9:0>: Chop Clock Divider bits
The frequency of the chop clock signal is given by the following expression:
Chop Frequency = (FP/PCLKDIV<2:0)/(CHOP<9:0> + 1)
REGISTER 16-6: MDC: PWMx MASTER DUTY CYCLE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: PWMx Master Duty Cycle Value bits
2011-2013 Microchip Technology Inc. DS70657G-page 233
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-7: PWMCONx: PWMx CONTROL REGISTER
HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT(1)CLSTAT(1)TRGSTAT FLTIEN CLIEN TRGIEN ITB(2)MDCS(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
DTC<1:0> DTCP(3)—MTBSCAM
(2,4)XPRES(5)IUE(2)
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
bit 14 CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit(2)
1 = PHASEx register provides time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
bit 8 MDCS: Master Duty Cycle Register Select bit(2)
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx register provides duty cycle information for this PWM generator
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: These bits should not be changed after the PWMx is enabled (PTEN = 1).
3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
4: The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
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bit 7-6 DTC<1:0>: Dead-Time Control bits
11 = Dead-Time Compensation mode
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for Complementary Output mode
00 = Positive dead time is actively applied for all output modes
bit 5 DTCP: Dead-Time Compensation Polarity bit(3)
When Set to ‘1’:
If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.
If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.
When Set to ‘0’:
If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened.
If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened.
bit 4 Unimplemented: Read as ‘0’
bit 3 MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and as the clock source
for the PWM generation logic (if secondary time base is available)
0 = PWM generator uses the primary master time base for synchronization and as the clock source
for the PWM generation logic
bit 2 CAM: Center-Aligned Mode Enable bit(2,4)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1 XPRES: External PWMx Reset Control bit(5)
1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base
mode
0 = External pins do not affect PWMx time base
bit 0 IUE: Immediate Update Enable bit(2)
1 = Updates to the active MDC/PDCx/DTx/ALTDTRx/PHASEx registers are immediate
0 = Updates to the active MDC/PDCx/DTx/ALTDTRx/PHASEx registers are synchronized to the
PWMx period boundary
REGISTER 16-7: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: These bits should not be changed after the PWMx is enabled (PTEN = 1).
3: DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
4: The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
5: To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
2011-2013 Microchip Technology Inc. DS70657G-page 235
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-8: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PDCx<15:0>: PWMx Generator # Duty Cycle Value bits
REGISTER 16-9: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWM Generator bits
Note 1: If ITB (PWMCONx<9>) = 0, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCON<11:10>) = 00, 01 or 10),
PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs
2: If ITB (PWMCONx<9>) = 1, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10),
PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL
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REGISTER 16-10: DTRx: PWMx DEAD-TIME REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——DTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTRx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 16-11: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— ALTDTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALTDTRx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
2011-2013 Microchip Technology Inc. DS70657G-page 237
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-12: TRGCONx: PWMx TRIGGER CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
TRGDIV<3:0> — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——TRGSTRT<5:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits
1111 = Trigger output for every 16th trigger event
1110 = Trigger output for every 15th trigger event
1101 = Trigger output for every 14th trigger event
1100 = Trigger output for every 13th trigger event
1011 = Trigger output for every 12th trigger event
1010 = Trigger output for every 11th trigger event
1001 = Trigger output for every 10th trigger event
1000 = Trigger output for every 9th trigger event
0111 = Trigger output for every 8th trigger event
0110 = Trigger output for every 7th trigger event
0101 = Trigger output for every 6th trigger event
0100 = Trigger output for every 5th trigger event
0011 = Trigger output for every 4th trigger event
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 11-6 Unimplemented: Read as ‘0’
bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits(1)
111111 = Waits 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010 = Waits 2 PWM cycles before generating the first trigger event after the module is enabled
000001 = Waits 1 PWM cycle before generating the first trigger event after the module is enabled
000000 = Waits 0 PWM cycles before generating the first trigger event after the module is enabled
Note 1: The secondary PWM generator cannot generate PWMx trigger interrupts.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 238 2011-2013 Microchip Technology Inc.
REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER(2)
R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PENH PENL POLH POLL PMOD<1:0>(1)OVRENH OVRENL
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PENH: PWMxH Output Pin Ownership bit
1 = PWMx module controls PWMxH pin
0 = GPIO module controls PWMxH pin
bit 14 PENL: PWMxL Output Pin Ownership bit
1 = PWMx module controls PWMxL pin
0 = GPIO module controls PWMxL pin
bit 13 POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12 POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10 PMOD<1:0>: PWMx # I/O Pin Mode bits(1)
11 = Reserved; do not use
10 = PWMx I/O pin pair is in the Push-Pull Output mode
01 = PWMx I/O pin pair is in the Redundant Output mode
00 = PWMx I/O pin pair is in the Complementary Output mode
bit 9 OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT<1> controls output on PWMxH pin
0 = PWMx generator controls PWMxH pin
bit 8 OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT<0> controls output on PWMxL pin
0 = PWMx generator controls PWMxL pin
bit 7-6 OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, PWMxH is driven to the state specified by OVRDAT<1>.
If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT<0>.
bit 5-4 FLTDAT<1:0>: Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits
If Fault is active, PWMxH is driven to the state specified by FLTDAT<1>.
If Fault is active, PWMxL is driven to the state specified by FLTDAT<0>.
bit 3-2 CLDAT<1:0>: Data for PWMxH and PWMxL Pins if CLMOD is Enabled bits
If current-limit is active, PWMxH is driven to the state specified by CLDAT<1>.
If current-limit is active, PWMxL is driven to the state specified by CLDAT<0>.
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
2011-2013 Microchip Technology Inc. DS70657G-page 239
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to PWMxL pins; PWMxL output signal is connected to
PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base
0 = Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary
REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER(2) (CONTINUED)
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 240 2011-2013 Microchip Technology Inc.
REGISTER 16-14: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TRGCMP<15:0>: Trigger Control Value bits
When the primary PWMx functions in local time base, this register contains the compare values that
can trigger the ADC module.
2011-2013 Microchip Technology Inc. DS70657G-page 241
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CLSRC<4:0> CLPOL(2)CLMOD
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
FLTSRC<4:0> FLTPOL(2)FLTMOD<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM Generator # bits
11111 = Fault 32
11110 = Reserved
•
•
•
01100 = Reserved
01011 = Comparator 4
01010 = Op Amp/Comparator 3
01001 = Op Amp/Comparator 2
01000 = Op Amp/Comparator 1
00111 = Reserved
00110 = Reserved
00101 = Reserved
00100 = Reserved
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1 (default)
bit 9 CLPOL: Current-Limit Polarity for PWM Generator # bit(2)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8 CLMOD: Current-Limit Mode Enable for PWM Generator # bit
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
Note 1: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 242 2011-2013 Microchip Technology Inc.
bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits
11111 = Fault 32 (default)
11110 = Reserved
•
•
•
01100 = Reserved
01011 = Comparator 4
01010 = Op Amp/Comparator 3
01001 = Op Amp/Comparator 2
01000 = Op Amp/Comparator 1
00111 = Reserved
00110 = Reserved
00101 = Reserved
00100 = Reserved
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1
bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(2)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0 FLTMOD<1:0>: Fault Mode for PWM Generator # bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle)
00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition)
REGISTER 16-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER(1)
Note 1: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2011-2013 Microchip Technology Inc. DS70657G-page 243
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-16: LEBCONx: PWMx LEADING-EDGE BLANKING CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PHR PHF PLR PLF FLTLEBEN CLLEBEN — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——BCH
(1)BCL(1)BPHH BPHL BPLH BPLL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxH
bit 14 PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxH
bit 13 PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxL
bit 12 PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxL
bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected Fault input
0 = Leading-Edge Blanking is not applied to selected Fault input
bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input
0 = Leading-Edge Blanking is not applied to selected current-limit input
bit 9-6 Unimplemented: Read as ‘0’
bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high
0 = No blanking when selected blanking signal is high
bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low
0 = No blanking when selected blanking signal is low
bit 3 BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high
0 = No blanking when PWMxH output is high
bit 2 BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low
0 = No blanking when PWMxH output is low
bit 1 BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high
0 = No blanking when PWMxL output is high
bit 0 BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low
0 = No blanking when PWMxL output is low
Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 244 2011-2013 Microchip Technology Inc.
REGISTER 16-17: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LEB<11:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEB<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
2011-2013 Microchip Technology Inc. DS70657G-page 245
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 16-18: AUXCONx: PWMx AUXILIARY CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — BLANKSEL<3:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CHOPSEL<3:0> CHOPHEN CHOPLEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 BLANKSEL<3:0>: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals (if enabled via the
BCH and BCL bits in the LEBCONx register).
1001 = Reserved
•
•
•
0100 = Reserved
0011 = PWM3H selected as state blank source
0010 = PWM2H selected as state blank source
0001 = PWM1H selected as state blank source
0000 = No state blanking
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHOPSEL<3:0>: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (CHOP) the selected PWMx outputs.
1001 = Reserved
•
•
•
0100 = Reserved
0011 = PWM3H selected as CHOP clock source
0010 = PWM2H selected as CHOP clock source
0001 = PWM1H selected as CHOP clock source
0000 = Chop clock generator selected as CHOP clock source
bit 1 CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0 CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 246 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 247
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
17.0 QUADRATURE ENCODER
INTERFACE (QEI) MODULE
(dsPIC33EPXXXMC20X/50X
and PIC24EPXXXMC20X
DEVICES ONLY)
This chapter describes the Quadrature Encoder Inter-
face (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining mechanical position data.
The operational features of the QEI module include:
• 32-Bit Position Counter
• 32-Bit Index Pulse Counter
• 32-Bit Interval Timer
• 16-Bit Velocity Counter
• 32-Bit Position Initialization/Capture/Compare
High register
• 32-Bit Position Compare Low register
• x4 Quadrature Count mode
• External Up/Down Count mode
• External Gated Count mode
• External Gated Timer mode
• Internal Timer mode
Figure 17-1 illustrates the QEI block diagram.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 15. “Quadrature
Encoder Interface (QEI)” (DS70601) of
the “dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 248 2011-2013 Microchip Technology Inc.
FIGURE 17-1: QEI BLOCK DIAGRAM
Quadrature
Decoder
Logic
CNTCMPx
QEBx
QEAx
INDXx
COUNT
DIR
FP COUNT COUNT_EN
32-Bit Greater Than or Equal
Compare Register
32-Bit Index Counter Register
Digital
Filter
HOMEx FHOMEx
Data Bus
32-Bit Greater Than
Data Bus
COUNT_EN
CNT_DIR
CNT_DIR
FINDXx
FINDXx
PCHEQ
32-Bit Interval Timer
16-Bit Index Counter
Hold Register
32-Bit Interval
Timer Register
Hold Register
COUNT_EN
FP
PCHGE
EXTCNT
EXTCNT
DIR_GATE
16-Bit Velocity
COUNT_ENCNT_DIR
Counter Register
PCLLE
PCHGE
DIVCLK
DIR
CNT_DIR
DIR_GATE
1’b0
PCLLE
CNTPOL
DIR_GATE
GATEN
0
1
DIVCLK
or Equal Comparator
32-Bit Less Than
PCLLE
or Equal Comparator
PCLEQ
PCHGE
QFDIV
CCM
INTDIV
(VELxCNT)
(INTxTMR)
(INTxHLD)
(INDXxCNT)
(INDXxHLD)
INDXxCNTL
INDXxCNTH POSxCNTLPOSxCNTH
(QEI1GEC)(1)
32-Bit Less Than or Equal
Compare Register
(QEI1LEC)
16-Bit Position Counter
Hold Register
(POSxHLD)
32-Bit Initialization and
Capture Register
(QEI1IC)(1)
QCAPEN
Note 1: These registers map to the same memory location.
OUTFNC
FLTREN
(POSxCNT)
32-Bit Position Counter Register
2011-2013 Microchip Technology Inc. DS70657G-page 249
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
17.1 QEI Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
17.1.1 KEY RESOURCES
•Section 15. “Quadrature Encoder Interface”
(DS70601)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 250 2011-2013 Microchip Technology Inc.
17.2 QEI Control Registers
REGISTER 17-1: QEI1CON: QEI CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIEN — QEISIDL PIMOD<2:0>(1)IMV1(2)IMV0(2)
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— INTDIV<2:0>(3)CNTPOL GATEN CCM<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 QEIEN: Quadrature Encoder Interface Module Counter Enable bit
1 = Module counters are enabled
0 = Module counters are disabled, but SFRs can be read or written to
bit 14 Unimplemented: Read as ‘0’
bit 13 QEISIDL: QEI Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10 PIMOD<2:0>: Position Counter Initialization Mode Select bits(1)
111 = Reserved
110 = Modulo Count mode for position counter
101 = Resets the position counter when the position counter equals QEI1GEC register
100 = Second index event after home event initializes position counter with contents of QEI1IC register
011 = First index event after home event initializes position counter with contents of QEI1IC register
010 = Next index input event initializes the position counter with contents of QEI1IC register
001 = Every index input event resets the position counter
000 = Index input event does not affect position counter
bit 9 IMV1: Index Match Value for Phase B bit(2)
1 = Phase B match occurs when QEB = 1
0 = Phase B match occurs when QEB = 0
bit 8 IMV0: Index Match Value for Phase A bit(2)
1 = Phase A match occurs when QEA = 1
0 = Phase A match occurs when QEA = 0
bit 7 Unimplemented: Read as ‘0’
Note 1: When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
2: When CCM<1:0> = 00 and QEA and QEB values match Index Match Value (IMV), the POSCNTH and
POSCNTL registers are reset. QEA/QEB signals used for index match have swap and polarity values
applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
3: The selected clock rate should be at least twice the expected maximum quadrature count rate.
2011-2013 Microchip Technology Inc. DS70657G-page 251
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 6-4 INTDIV<2:0>: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter),
velocity counter and index counter internal clock divider select)(3)
111 = 1:128 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
bit 3 CNTPOL: Position and Index Counter/Timer Direction Select bit
1 = Counter direction is negative unless modified by external up/down signal
0 = Counter direction is positive unless modified by external up/down signal
bit 2 GATEN: External Count Gate Enable bit
1 = External gate signal controls position counter operation
0 = External gate signal does not affect position counter/timer operation
bit 1-0 CCM<1:0>: Counter Control Mode Selection bits
11 = Internal Timer mode with optional external count is selected
10 = External clock count with optional external count is selected
01 = External clock count with external up/down direction is selected
00 = Quadrature Encoder Interface (x4 mode) Count mode is selected
REGISTER 17-1: QEI1CON: QEI CONTROL REGISTER (CONTINUED)
Note 1: When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
2: When CCM<1:0> = 00 and QEA and QEB values match Index Match Value (IMV), the POSCNTH and
POSCNTL registers are reset. QEA/QEB signals used for index match have swap and polarity values
applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
3: The selected clock rate should be at least twice the expected maximum quadrature count rate.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 252 2011-2013 Microchip Technology Inc.
REGISTER 17-2: QEI1IOC: QEI I/O CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QCAPEN FLTREN QFDIV<2:0> OUTFNC<1:0> SWPAB
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R-x R-x R-x R-x
HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 QCAPEN: Position Counter Input Capture Enable bit
1 = Positive edge detect of Home input triggers a position capture event
0 = Positive edge detect of Home input does not trigger a position capture event
bit 14 FLTREN: QEAx/QEBx/INDXx/HOMEx Digital Filter Enable bit
1 = Input pin digital filter is enabled
0 = Input pin digital filter is disabled (bypassed)
bit 13-11 QFDIV<2:0>: QEAx/QEBx/INDXx/HOMEx Digital Input Filter Clock Divide Select bits
111 = 1:128 clock divide
110 = 1:64 clock divide
101 = 1:32 clock divide
100 = 1:16 clock divide
011 = 1:8 clock divide
010 = 1:4 clock divide
001 = 1:2 clock divide
000 = 1:1 clock divide
bit 10-9 OUTFNC<1:0>: QEI Module Output Function Mode Select bits
11 = The CTNCMPx pin goes high when QEI1LEC POSxCNT QEI1GEC
10 = The CTNCMPx pin goes high when POSxCNT QEI1LEC
01 = The CTNCMPx pin goes high when POSxCNT QEI1GEC
00 = Output is disabled
bit 8 SWPAB: Swap QEA and QEB Inputs bit
1 = QEAx and QEBx are swapped prior to quadrature decoder logic
0 = QEAx and QEBx are not swapped
bit 7 HOMPOL: HOMEx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 6 IDXPOL: INDXx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 5 QEBPOL: QEBx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 4 QEAPOL: QEAx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 3 HOME: Status of HOMEx Input Pin After Polarity Control
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
2011-2013 Microchip Technology Inc. DS70657G-page 253
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 2 INDEX: Status of INDXx Input Pin After Polarity Control
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
bit 1 QEB: Status of QEBx Input Pin After Polarity Control And SWPAB Pin Swapping
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
bit 0 QEA: Status of QEAx Input Pin After Polarity Control And SWPAB Pin Swapping
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
REGISTER 17-2: QEI1IOC: QEI I/O CONTROL REGISTER (CONTINUED)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 254 2011-2013 Microchip Technology Inc.
REGISTER 17-3: QEI1STAT: QEI STATUS REGISTER
U-0 U-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0
—— PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN
bit 15 bit 8
HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0
PCIIRQ(1)PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN
bit 7 bit 0
Legend: HS = Hardware Settable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit
1 = POSxCNT ≥ QEI1GEC
0 = POSxCNT < QEI1GEC
bit 12 PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 11 PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit
1 = POSxCNT ≤ QEI1LEC
0 = POSxCNT > QEI1LEC
bit 10 PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 9 POSOVIRQ: Position Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has occurred
bit 8 POSOVIEN: Position Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 7 PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit(1)
1 = POSxCNT was reinitialized
0 = POSxCNT was not reinitialized
bit 6 PCIIEN: Position Counter (Homing) Initialization Process Complete interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5 VELOVIRQ: Velocity Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has not occurred
bit 4 VELOVIEN: Velocity Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 3 HOMIRQ: Status Flag for Home Event Status bit
1 = Home event has occurred
0 = No Home event has occurred
Note 1: This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’.
2011-2013 Microchip Technology Inc. DS70657G-page 255
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 2 HOMIEN: Home Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1 IDXIRQ: Status Flag for Index Event Status bit
1 = Index event has occurred
0 = No Index event has occurred
bit 0 IDXIEN: Index Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
REGISTER 17-3: QEI1STAT: QEI STATUS REGISTER (CONTINUED)
Note 1: This status bit is only applicable to PIMOD<2:0> modes, ‘011’ and ‘100’.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 256 2011-2013 Microchip Technology Inc.
REGISTER 17-4: POSxCNTH: POSITION COUNTER HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POSCNT<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POSCNT<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 POSCNT<31:16>: High Word Used to Form 32-Bit Position Counter Register (POSxCNT) bits
REGISTER 17-5: POSxCNTL: POSITION COUNTER LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POSCNT<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POSCNT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 POSCNT<15:0>: Low Word Used to Form 32-Bit Position Counter Register (POSxCNT) bits
REGISTER 17-6: POSxHLD: POSITION COUNTER HOLD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POSHLD<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
POSHLD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 POSHLD<15:0>: Hold Register for Reading and Writing POSxCNTH bits
2011-2013 Microchip Technology Inc. DS70657G-page 257
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 17-7: VELxCNT: VELOCITY COUNTER REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VELCNT<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VELCNT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 VELCNT<15:0>: Velocity Counter bits
REGISTER 17-8: INDXxCNTH: INDEX COUNTER HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INDXCNT<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INDXCNT<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INDXCNT<31:16>: High Word Used to Form 32-Bit Index Counter Register (INDXxCNT) bits
REGISTER 17-9: INDXxCNTL: INDEX COUNTER LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INDXCNT<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INDXCNT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INDXCNT<15:0>: Low Word Used to Form 32-Bit Index Counter Register (INDXxCNT) bits
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 258 2011-2013 Microchip Technology Inc.
REGISTER 17-10: INDXxHLD: INDEX COUNTER HOLD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INDXHLD<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INDXHLD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INDXHLD<15:0>: Hold Register for Reading and Writing INDXxCNTH bits
REGISTER 17-11: QEI1ICH: INITIALIZATION/CAPTURE HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIIC<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIIC<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIIC<31:16>: High Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits
REGISTER 17-12: QEI1ICL: INITIALIZATION/CAPTURE LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIIC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIIC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIIC<15:0>: Low Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits
2011-2013 Microchip Technology Inc. DS70657G-page 259
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 17-13: QEI1LECH: LESS THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEILEC<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEILEC<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEILEC<31:16>: High Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits
REGISTER 17-14: QEI1LECL: LESS THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEILEC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEILEC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEILEC<15:0>: Low Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 260 2011-2013 Microchip Technology Inc.
REGISTER 17-15: QEI1GECH: GREATER THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIGEC<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIGEC<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIGEC<31:16>: High Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits
REGISTER 17-16: QEI1GECL: GREATER THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIGEC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEIGEC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 QEIGEC<15:0>: Low Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits
REGISTER 17-17: INTxTMRH: INTERVAL TIMER HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTTMR<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTTMR<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTTMR<31:16>: High Word Used to Form 32-Bit Interval Timer Register (INTxTMR) bits
2011-2013 Microchip Technology Inc. DS70657G-page 261
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 17-18: INTxTMRL: INTERVAL TIMER LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTTMR<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTTMR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTTMR<15:0>: Low Word Used to Form 32-Bit Interval Timer Register (INTxTMR) bits
REGISTER 17-19: INTxHLDH: INTERVAL TIMER HOLD HIGH WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTHLD<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTHLD<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTHLD<31:16>: Hold Register for Reading and Writing INTxTMRH bits
REGISTER 17-20: INTxHLDL: INTERVAL TIMER HOLD LOW WORD REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTHLD<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTHLD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 INTHLD<15:0>: Hold Register for Reading and Writing INTxTMRL bits
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 262 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 263
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
18.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The SPI module is a synchronous serial interface,
useful for communicating with other peripheral or
microcontroller devices. These peripheral devices can
be serial EEPROMs, shift registers, display drivers,
ADC Converters, etc. The SPI module is compatible
with Motorola® SPI and SIOP interfaces.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X device family offers
two SPI modules on a single device. These modules,
which are designated as SPI1 and SPI2, are function-
ally identical. Each SPI module includes an eight-word
FIFO buffer and allows DMA bus connections. When
using the SPI module with DMA, FIFO operation can be
disabled.
The SPI1 module uses dedicated pins which allow for
a higher speed when using SPI1. The SPI2 module
takes advantage of the Peripheral Pin Select (PPS)
feature to allow for greater flexibility in pin configuration
of the SPI2 module, but results in a lower maximum
speed for SPI2. See Section 30.0 “Electrical
Characteristics” for more information.
The SPIx serial interface consists of four pins, as
follows:
• SDIx: Serial Data Input
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
• SSx/FSYNCx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPIx module can be configured to operate with
two, three or four pins. In 3-pin mode, SSx is not used.
In 2-pin mode, neither SDOx nor SSx is used.
Figure 18-1 illustrates the block diagram of the SPIx
module in Standard and Enhanced modes.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 18. “Serial Peripheral
Interface (SPI)” (DS70569) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1 and SPI2. Special Function
Registers follow a similar notation. For
example, SPIxCON refers to the control
register for the SPI1 and SPI2 module.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 264 2011-2013 Microchip Technology Inc.
FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM
Internal Data Bus
SDIx
SDOx
SSx/FSYNCx
SCKx
bit 0
Shift Control
Edge
Select
FP
Primary
1:1/4/16/64
Enable
Prescaler
Sync
Control
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Note 1: In Standard mode, the FIFO is only one level deep.
Clock
Control
Secondary
Prescaler
1:1 to 1:8
SPIxSR
8-Level FIFO
Receive Buffer
(1)
8-Level FIFO
Transmit Buffer
(1)
SPIxBUF
2011-2013 Microchip Technology Inc. DS70657G-page 265
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
18.1 SPI Helpful Tips
1. In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2<13>) = 1, use a
pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on
SSx.
2. In Non-Framed 3-Wire mode, (i.e., not using
SSx from a master):
a) If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx.
b) If CKP = 0, always place a pull-down
resistor on SSx.
3. FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
4. In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPIx data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
To avoid invalid slave read data to the master, the
user’s master software must ensure enough time for
slave software to fill its write buffer before the user
application initiates a master write/read cycle. It is
always advisable to preload the SPIxBUF Transmit
register in advance of the next master transaction
cycle. SPIxBUF is transferred to the SPIx Shift register
and is empty once the data transmission begins.
18.2 SPI Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
18.2.1 KEY RESOURCES
•Section 18. “Serial Peripheral Interface (SPI)”
(DS70569)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: This insures that the first frame
transmission after initialization is not
shifted or corrupted.
Note: This will insure that during power-up and
initialization the master/slave will not lose
Sync due to an errant SCKx transition that
would cause the slave to accumulate data
shift errors for both transmit and receive
appearing as corrupted data.
Note: Not all third-party devices support Frame
mode timing. Refer to the SPIx
specifications in Section 30.0 “Electrical
Characteristics” for details.
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 266 2011-2013 Microchip Technology Inc.
18.3 SPIx Control Registers
REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SPIEN — SPISIDL —— SPIBEC<2:0>
bit 15 bit 8
R/W-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R-0, HS, HC
SRMPT SPIROV SRXMPT SISEL<2:0> SPITBF SPIRBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 SPIEN: SPIx Enable bit
1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables the module
bit 14 Unimplemented: Read as ‘0’
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues the module operation when device enters Idle mode
0 = Continues the module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPIx transfers that are pending.
Slave mode:
Number of SPIx transfers that are unread.
bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive the data
0 = SPIx Shift register is not empty
bit 6 SPIROV: SPIx Receive Overflow Flag bit
1
= A new byte/word is completely received and discarded; the user application has not read the previous
data in the SPIxBUF register
0 = No overflow has occurred
bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when last bit is shifted into SPIxSR and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR and as a result, the TX FIFO has one open
memory location
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read and as a result, the buffer is empty
(SRXMPT bit set)
2011-2013 Microchip Technology Inc. DS70657G-page 267
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
Standard Buffer mode:
Automatically set in hardware when core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is incomplete, SPIxRXB is empty
Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread
buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from
SPIxSR.
REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
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REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK DISSDO MODE16 SMP CKE(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN(2)CKP MSTEN SPRE<2:0>(3)PPRE<1:0>(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 DISSCK: Disable SCKx Pin bit (SPIx Master modes only)
1 = Internal SPIx clock is disabled, pin functions as I/O
0 = Internal SPIx clock is enabled
bit 11 DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at end of data output time
0 = Input data is sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by the module; pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.
2011-2013 Microchip Technology Inc. DS70657G-page 269
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 (CONTINUED)
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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REGISTER 18-3: SPIXCON2: SPIX CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD FRMPOL — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — FRMDLY SPIBEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin is used as Frame Sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14 SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
bit 13 FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame Sync pulse is active-high
0 = Frame Sync pulse is active-low
bit 12-2 Unimplemented: Read as ‘0’
bit 1 FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with first bit clock
0 = Frame Sync pulse precedes first bit clock
bit 0 SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Standard mode)
2011-2013 Microchip Technology Inc. DS70657G-page 271
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
19.0 INTER-INTEGRATED
CIRCUIT™ (I2C™)
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X family of devices
contains two Inter-Integrated Circuit (I2C) modules:
I2C1 and I2C2.
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard, with a 16-bit interface.
The I2C module has a 2-pin interface:
• The SCLx pin is clock
• The SDAx pin is data
The I2C module offers the following key features:
•I
2C interface supporting both Master and Slave
modes of operation
•I
2C Slave mode supports 7 and 10-bit addressing
•I
2C Master mode supports 7 and 10-bit addressing
•I
2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
•I
2C supports multi-master operation, detects bus
collision and arbitrates accordingly
• Intelligent Platform Management Interface (IPMI)
support
• System Management Bus (SMBus) support
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 19. “Inter-Integrated
Circuit™ (I2C™)” (DS70330) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 272 2011-2013 Microchip Technology Inc.
FIGURE 19-1: I2Cx BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
SCLx/ASCLx
SDAx/ASDAx
Shift
Match Detect
Start and Stop
Bit Detect
Clock
Address Match
Clock
Stretching
I2CxTRN
LSb
Shift Clock
BRG Down Counter
Reload
Control
FP/2
Start and Stop
Bit Generation
Acknowledge
Generation
Collision
Detect
I2CxCON
I2CxSTAT
Control Logic
Read
LSb
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
I2CxMSK
I2CxRCV
I2CxADD
2011-2013 Microchip Technology Inc. DS70657G-page 273
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
19.1 I2C Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
19.1.1 KEY RESOURCES
•Section 19. “Inter-Integrated Circuit (I2C)”
(DS70330)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 274 2011-2013 Microchip Technology Inc.
19.2 I2C Control Registers
REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL IPMIEN(1)A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave
address byte reception. Hardware is clear at the end of every slave data byte reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at the beginning of every
slave data byte transmission. Hardware is clear at the end of every slave address byte reception.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit(1)
1 = IPMI mode is enabled; all addresses are Acknowledged
0 = IPMI mode disabled
bit 10 A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception)
0 = General call address disabled
Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’.
2011-2013 Microchip Technology Inc. DS70657G-page 275
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware
is clear at the end of the master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware is clear at the end of the eighth bit of the master receive
data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of the master Stop
sequence.
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of the
master Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start
sequence.
0 = Start condition is not in progress
REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’.
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REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend:
C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware is set or clear at the end of slave Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No bus collision detected
Hardware is set at detection of a bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when address matches general call address. Hardware is clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2nd byte of the matched 10-bit address. Hardware is clear at Stop
detection.
bit 7 IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5 D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at a device address match. Hardware is set by reception of a slave byte.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
2011-2013 Microchip Technology Inc. DS70657G-page 277
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
bit 2 R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – Indicates data transfer is output from the slave
0 = Write – Indicates data transfer is input to the slave
Hardware is set or clear after reception of an I2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads
I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of a data transmission.
REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
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REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK9 AMSK8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0 AMSK<9:0>: Address Mask Select bits
For 10-Bit Address:
1 = Enables masking for bit Ax of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax; bit match is required in this position
For 7-Bit Address (I2CxMSK<6:0> only):
1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax + 1; bit match is required in this position
2011-2013 Microchip Technology Inc. DS70657G-page 279
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
20.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X family of devices
contains two UART modules.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X device family. The UART is a full-duplex
asynchronous system that can communicate with
peripheral devices, such as personal computers, LIN/
J2602, RS-232 and RS-485 interfaces. The module also
supports a hardware flow control option with the UxCTS
and UxRTS pins, and also includes an IrDA® encoder and
decoder.
The primary features of the UARTx module are:
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
• Baud Rates Ranging from 4.375 Mbps to 67 bps at
16x mode at 70 MIPS
• Baud Rates Ranging from 17.5 Mbps to 267 bps at
4x mode at 70 MIPS
• 4-Deep First-In First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for all UARTx Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
FIGURE 20-1: UARTx SIMPLIFIED BLOCK DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 17. “UART” (DS70582) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Hardware flow control using UxRTS and
UxCTS is not available on all pin count
devices. See the “Pin Diagrams” section
for availability.
UxRX
Hardware Flow Control
UARTx Receiver
UARTx Transmitter UxTX
Baud Rate Generator
UxRTS/BCLKx
UxCTS
IrDA®
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 280 2011-2013 Microchip Technology Inc.
20.1 UART Helpful Tips
1. In multi-node, direct-connect UART networks,
UART receive inputs react to the
complementary logic level defined by the
URXINV bit (UxMODE<4>), which defines the
Idle state, the default of which is logic high (i.e.,
URXINV = 0). Because remote devices do not
initialize at the same time, it is likely that one of
the devices, because the RX line is floating, will
trigger a Start bit detection and will cause the
first byte received, after the device has been ini-
tialized, to be invalid. To avoid this situation, the
user should use a pull-up or pull-down resistor
on the RX pin depending on the value of the
URXINV bit.
a) If URXINV = 0, use a pull-up resistor on the
RX pin.
b) If URXINV = 1, use a pull-down resistor on
the RX pin.
2. The first character received on a wake-up from
Sleep mode caused by activity on the UxRX pin
of the UARTx module will be invalid. In Sleep
mode, peripheral clocks are disabled. By the
time the oscillator system has restarted and
stabilized from Sleep mode, the baud rate bit
sampling clock, relative to the incoming UxRX
bit timing, is no longer synchronized, resulting in
the first character being invalid; this is to be
expected.
20.2 UART Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
20.2.1 KEY RESOURCES
•Section 17. “UART” (DS70582)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 281
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
20.3 UARTx Control Registers
REGISTER 20-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
UARTEN(1)— USIDL IREN(2)RTSMD —UEN<1:0>
bit 15 bit 8
R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimal
bit 14 Unimplemented: Read as ‘0’
bit 13 USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 =UxRTS
pin is in Simplex mode
0 =UxRTS
pin is in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches(3)
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used(4)
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches(4)
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge; bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for information
on enabling the UARTx module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This feature is only available on 44-pin and 64-pin devices.
4: This feature is only available on 64-pin devices.
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bit 5 ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
bit 4 URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for information
on enabling the UARTx module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This feature is only available on 44-pin and 64-pin devices.
4: This feature is only available on 64-pin devices.
2011-2013 Microchip Technology Inc. DS70657G-page 283
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1)UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0
URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: HC = Hardware Clearable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14 UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA encoded, UxTX Idle state is ‘1’
0 = IrDA encoded, UxTX Idle state is ‘0’
bit 12 Unimplemented: Read as ‘0’
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled
by the PORT
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for
information on enabling the UARTx module for transmit operation.
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bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (10 transition) resets the
receiver buffer and the UxRSR to the empty state
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
Note 1: Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for
information on enabling the UARTx module for transmit operation.
2011-2013 Microchip Technology Inc. DS70657G-page 285
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
21.0 ENHANCED CAN (ECAN™)
MODULE (dsPIC33EPXXXGP/
MC50X DEVICES ONLY)
21.1 Overview
The Enhanced Controller Area Network (ECAN)
module is a serial interface, useful for communicat-
ing with other CAN modules or microcontroller
devices. This interface/protocol was designed to
allow communications within noisy environments.
The dsPIC33EPXXXGP/MC50X devices contain one
ECAN module.
The ECAN module is a communication controller
implementing the CAN 2.0 A/B protocol, as defined in
the BOSCH CAN specification. The module supports
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B
Active versions of the protocol. The module implemen-
tation is a full CAN system. The CAN specification is
not covered within this data sheet. The reader can refer
to the BOSCH CAN specification for further details.
The ECAN module features are as follows:
• Implementation of the CAN protocol, CAN 1.2,
CAN2.0A and CAN2.0B
• Standard and extended data frames
• 0-8 bytes data length
• Programmable bit rate up to 1 Mbit/sec
• Automatic response to remote transmission
requests
• Up to eight transmit buffers with application speci-
fied prioritization and abort capability (each buffer
can contain up to 8 bytes of data)
• Up to 32 receive buffers (each buffer can contain
up to 8 bytes of data)
• Up to 16 full (Standard/Extended Identifier)
acceptance filters
• Three full acceptance filter masks
• DeviceNet™ addressing support
• Programmable wake-up functionality with
integrated low-pass filter
• Programmable Loopback mode supports self-test
operation
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to Input Capture (IC2) module
for time-stamping and network synchronization
• Low-power Sleep and Idle mode
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Enhanced
Controller Area Network (ECAN™)”
(DS70353) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 286 2011-2013 Microchip Technology Inc.
FIGURE 21-1: ECAN™ MODULE BLOCK DIAGRAM
Message Assembly
CAN Protocol
Engine
CxTx
Buffer
CxRx
RxF14 Filter
RxF13 Filter
RxF12 Filter
RxF11 Filter
RxF10 Filter
RxF9 Filter
RxF8 Filter
RxF7 Filter
RxF6 Filter
RxF5 Filter
RxF4 Filter
RxF3 Filter
RxF2 Filter
RxF1 Filter
RxF0 Filter
Transmit Byte
Sequencer
RxM1 Mask
RxM0 Mask
Control
Configuration
Logic
CPU
Bus
Interrupts
TRB0 TX/RX Buffer Control Register
RxF15 Filter
RxM2 Mask
TRB7 TX/RX Buffer Control Register
TRB6 TX/RX Buffer Control Register
TRB5 TX/RX Buffer Control Register
TRB4 TX/RX Buffer Control Register
TRB3 TX/RX Buffer Control Register
TRB2 TX/RX Buffer Control Register
TRB1 TX/RX Buffer Control Register
DMA Controller
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
21.2 Modes of Operation
The ECAN module can operate in one of several
operation modes selected by the user. These modes
include:
• Initialization mode
• Disable mode
• Normal Operation mode
• Listen Only mode
• Listen All Messages mode
• Loopback mode
Modes are requested by setting the REQOP<2:0> bits
(CxCTRL1<10:8>). Entry into a mode is Acknowledged
by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>).
The module does not change the mode and the
OPMODEx bits until a change in mode is acceptable,
generally during bus Idle time, which is defined as at least
11 consecutive recessive bits.
21.3 ECAN Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
21.3.1 KEY RESOURCES
•Section 21. “Enhanced Controller Area Network
(ECAN™)” (DS70353)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 288 2011-2013 Microchip Technology Inc.
21.4 ECAN Control Registers
REGISTER 21-1: CxCTRL1: ECANx CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
—— CSIDL ABAT CANCKS REQOP<2:0>
bit 15 bit 8
R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0
OPMODE<2:0> — CANCAP ——WIN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CSIDL: ECAN Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions are aborted
bit 11 CANCKS: ECAN Module Clock (FCAN) Source Select bit
1 = FCAN is equal to 2 * FP
0 = FCAN is equal to FP
bit 10-8 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 7-5 OPMODE<2:0>: Operation Mode bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 4 Unimplemented: Read as ‘0’
bit 3 CANCAP: CAN Message Receive Timer Capture Event Enable bit
1 = Enables input capture based on CAN message receive
0 = Disables CAN capture
bit 2-1 Unimplemented: Read as ‘0’
bit 0 WIN: SFR Map Window Select bit
1 = Uses filter window
0 = Uses buffer window
2011-2013 Microchip Technology Inc. DS70657G-page 289
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-2: CxCTRL2: ECANx CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — DNCNT<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111 = Invalid selection
10001 = Compares up to Data Byte 3, bit 6 with EID<17>
•
•
•
00001 = Compares up to Data Byte 1, bit 7 with EID<0>
00000 = Does not compare data bytes
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REGISTER 21-3: CxVEC: ECANx INTERRUPT CODE REGISTER
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — —FILHIT<4:0>
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— ICODE<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT<4:0>: Filter Hit Number bits
10000-11111 = Reserved
01111 = Filter 15
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111 = Reserved
1000100 = FIFO almost full interrupt
1000011 = Receiver overflow interrupt
1000010 = Wake-up interrupt
1000001 = Error interrupt
1000000 = No interrupt
•
•
•
0010000-0111111 = Reserved
0001111 = RB15 buffer interrupt
•
•
•
0001001 = RB9 buffer interrupt
0001000 = RB8 buffer interrupt
0000111 = TRB7 buffer interrupt
0000110 = TRB6 buffer interrupt
0000101 = TRB5 buffer interrupt
0000100 = TRB4 buffer interrupt
0000011 = TRB3 buffer interrupt
0000010 = TRB2 buffer interrupt
0000001 = TRB1 buffer interrupt
0000000 = TRB0 buffer interrupt
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-4: CxFCTRL: ECANx FIFO CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
DMABS<2:0> — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — FSA<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 DMABS<2:0>: DMA Buffer Size bits
111 = Reserved
110 = 32 buffers in RAM
101 = 24 buffers in RAM
100 = 16 buffers in RAM
011 = 12 buffers in RAM
010 = 8 buffers in RAM
001 = 6 buffers in RAM
000 = 4 buffers in RAM
bit 12-5 Unimplemented: Read as ‘0’
bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits
11111 = Read Buffer RB31
11110 = Read Buffer RB30
•
•
•
00001 = TX/RX Buffer TRB1
00000 = TX/RX Buffer TRB0
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REGISTER 21-5: CxFIFO: ECANx FIFO STATUS REGISTER
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
—— FBP<5:0>
bit 15 bit 8
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
—— FNRB<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
—— TXBO TXBP RXBP TXWAR RXWAR EWARN
bit 15 bit 8
R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0
IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 TXBO: Transmitter in Error State Bus Off bit
1 = Transmitter is in Bus Off state
0 = Transmitter is not in Bus Off state
bit 12 TXBP: Transmitter in Error State Bus Passive bit
1 = Transmitter is in Bus Passive state
0 = Transmitter is not in Bus Passive state
bit 11 RXBP: Receiver in Error State Bus Passive bit
1 = Receiver is in Bus Passive state
0 = Receiver is not in Bus Passive state
bit 10 TXWAR: Transmitter in Error State Warning bit
1 = Transmitter is in Error Warning state
0 = Transmitter is not in Error Warning state
bit 9 RXWAR: Receiver in Error State Warning bit
1 = Receiver is in Error Warning state
0 = Receiver is not in Error Warning state
bit 8 EWARN: Transmitter or Receiver in Error State Warning bit
1 = Transmitter or receiver is in Error Warning state
0 = Transmitter or receiver is not in Error Warning state
bit 7 IVRIF: Invalid Message Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8>)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4 Unimplemented: Read as ‘0’
bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
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DS70657G-page 294 2011-2013 Microchip Technology Inc.
bit 1 RBIF: RX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0 TBIF: TX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER (CONTINUED)
2011-2013 Microchip Technology Inc. DS70657G-page 295
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REGISTER 21-7: CxINTE: ECANx INTERRUPT ENABLE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 IVRIE: Invalid Message Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6 WAKIE: Bus Wake-up Activity Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5 ERRIE: Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4 Unimplemented: Read as ‘0’
bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 296 2011-2013 Microchip Technology Inc.
REGISTER 21-8: CxEC: ECANx TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TERRCNT<7:0>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RERRCNT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 TERRCNT<7:0>: Transmit Error Count bits
bit 7-0 RERRCNT<7:0>: Receive Error Count bits
REGISTER 21-9: CxCFG1: ECANx BAUD RATE CONFIGURATION REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SJW<1:0> BRP<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-6 SJW<1:0>: Synchronization Jump Width bits
11 = Length is 4 x TQ
10 = Length is 3 x TQ
01 = Length is 2 x TQ
00 = Length is 1 x TQ
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
11 1111 = TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010 = TQ = 2 x 3 x 1/FCAN
00 0001 = TQ = 2 x 2 x 1/FCAN
00 0000 = TQ = 2 x 1 x 1/FCAN
2011-2013 Microchip Technology Inc. DS70657G-page 297
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-10: CxCFG2: ECANx BAUD RATE CONFIGURATION REGISTER 2
U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x
— WAKFIL — — — SEG2PH<2:0>
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1 = Uses CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 13-11 Unimplemented: Read as ‘0’
bit 10-8 SEG2PH<2:0>: Phase Segment 2 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7 SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable
0 = Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater
bit 6 SAM: Sample of the CAN Bus Line bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 2-0 PRSEG<2:0>: Propagation Time Segment bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 298 2011-2013 Microchip Technology Inc.
REGISTER 21-11: CxFEN1: ECANx ACCEPTANCE FILTER ENABLE REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 FLTEN<15:0>: Enable Filter n to Accept Messages bits
1 = Enables Filter n
0 = Disables Filter n
REGISTER 21-12: CxBUFPNT1: ECANx FILTER 0-3 BUFFER POINTER REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F3BP<3:0> F2BP<3:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F1BP<3:0> F0BP<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 F3BP<3:0>: RX Buffer Mask for Filter 3 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8 F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bits<15:12>)
bit 7-4 F1BP<3:0>: RX Buffer Mask for Filter 1 bits (same values as bits<15:12>)
bit 3-0 F0BP<3:0>: RX Buffer Mask for Filter 0 bits (same values as bits<15:12>)
2011-2013 Microchip Technology Inc. DS70657G-page 299
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-13: CxBUFPNT2: ECANx FILTER 4-7 BUFFER POINTER REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F7BP<3:0> F6BP<3:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F5BP<3:0> F4BP<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 F7BP<3:0>: RX Buffer Mask for Filter 7 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8 F6BP<3:0>: RX Buffer Mask for Filter 6 bits (same values as bits<15:12>)
bit 7-4 F5BP<3:0>: RX Buffer Mask for Filter 5 bits (same values as bits<15:12>)
bit 3-0 F4BP<3:0>: RX Buffer Mask for Filter 4 bits (same values as bits<15:12>)
REGISTER 21-14: CxBUFPNT3: ECANx FILTER 8-11 BUFFER POINTER REGISTER 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F11BP<3:0> F10BP<3:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F9BP<3:0> F8BP<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 F11BP<3:0>: RX Buffer Mask for Filter 11 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8 F10BP<3:0>: RX Buffer Mask for Filter 10 bits (same values as bits<15:12>)
bit 7-4 F9BP<3:0>: RX Buffer Mask for Filter 9 bits (same values as bits<15:12>)
bit 3-0 F8BP<3:0>: RX Buffer Mask for Filter 8 bits (same values as bits<15:12>)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 300 2011-2013 Microchip Technology Inc.
REGISTER 21-15: CxBUFPNT4: ECANx FILTER 12-15 BUFFER POINTER REGISTER 4
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F15BP<3:0> F14BP<3:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F13BP<3:0> F12BP<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 F15BP<3:0>: RX Buffer Mask for Filter 15 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8 F14BP<3:0>: RX Buffer Mask for Filter 14 bits (same values as bits<15:12>)
bit 7-4 F13BP<3:0>: RX Buffer Mask for Filter 13 bits (same values as bits<15:12>)
bit 3-0 F12BP<3:0>: RX Buffer Mask for Filter 12 bits (same values as bits<15:12>)
2011-2013 Microchip Technology Inc. DS70657G-page 301
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-16: CxRXFnSID: ECANx ACCEPTANCE FILTER n STANDARD IDENTIFIER
REGISTER (n = 0-15)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID2 SID1 SID0 — EXIDE —EID17EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 SID<10:0>: Standard Identifier bits
1 = Message address bit, SIDx, must be ‘1’ to match filter
0 = Message address bit, SIDx, must be ‘0’ to match filter
bit 4 Unimplemented: Read as ‘0’
bit 3 EXIDE: Extended Identifier Enable bit
If MIDE = 1:
1 = Matches only messages with Extended Identifier addresses
0 = Matches only messages with Standard Identifier addresses
If MIDE = 0:
Ignores EXIDE bit.
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID<17:16>: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
0 = Message address bit, EIDx, must be ‘0’ to match filter
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 302 2011-2013 Microchip Technology Inc.
REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER
REGISTER (n = 0-15)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 EID<15:0>: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
0 = Message address bit, EIDx, must be ‘0’ to match filter
REGISTER 21-18: CxFMSKSEL1:
ECAN
x
FILTER 7-0 MASK SELECTION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bits
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bits<15:14>)
bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bits (same values as bits<15:14>)
bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bits (same values as bits<15:14>)
bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bits (same values as bits<15:14>)
bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bits (same values as bits<15:14>)
bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bits (same values as bits<15:14>)
bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bits (same values as bits<15:14>)
2011-2013 Microchip Technology Inc. DS70657G-page 303
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-19: CxFMSKSEL2:
ECAN
x
FILTER 15-8 MASK SELECTION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bits
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12 F14MSK<1:0>: Mask Source for Filter 14 bits (same values as bits<15:14>)
bit 11-10 F13MSK<1:0>: Mask Source for Filter 13 bits (same values as bits<15:14>)
bit 9-8 F12MSK<1:0>: Mask Source for Filter 12 bits (same values as bits<15:14>)
bit 7-6 F11MSK<1:0>: Mask Source for Filter 11 bits (same values as bits<15:14>)
bit 5-4 F10MSK<1:0>: Mask Source for Filter 10 bits (same values as bits<15:14>)
bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bits (same values as bits<15:14>)
bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bits (same values as bits<15:14>)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 304 2011-2013 Microchip Technology Inc.
REGISTER 21-20: CxRXMnSID:
ECAN
x
ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER
REGISTER (n = 0-2)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID2 SID1 SID0 —MIDE —EID17EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 SID<10:0>: Standard Identifier bits
1 = Includes bit, SIDx, in filter comparison
0 = SIDx bit is a don’t care in filter comparison
bit 4 Unimplemented: Read as ‘0’
bit 3 MIDE: Identifier Receive Mode bit
1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in the filter
0 = Matches either standard or extended address message if filters match (i.e., if (Filter SID) = (Message
SID) or if (Filter SID/EID) = (Message SID/EID))
bit 2 Unimplemented: Read as ‘0’
bit 1-0 EID<17:16>: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison
0 = EIDx bit is a don’t care in filter comparison
REGISTER 21-21: CxRXMnEID:
ECAN
x
ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER
REGISTER (n = 0-2)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 EID<15:0>: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison
0 = EIDx bit is a don’t care in filter comparison
2011-2013 Microchip Technology Inc. DS70657G-page 305
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-22: CxRXFUL1: ECANx RECEIVE BUFFER FULL REGISTER 1
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits
1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)
REGISTER 21-23: CxRXFUL2: ECANx RECEIVE BUFFER FULL REGISTER 2
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits
1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 306 2011-2013 Microchip Technology Inc.
REGISTER 21-24: CxRXOVF1: ECANx RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)
REGISTER 21-25: CxRXOVF2: ECANx RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24
bit 15 bit 8
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)
2011-2013 Microchip Technology Inc. DS70657G-page 307
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER mn CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI<1:0>
bit 15 bit 8
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXENm TXABTm(1)TXLARBm(1)TXERRm(1)TXREQm RTRENm TXmPRI<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 See Definition for bits<7:0>, Controls Buffer n
bit 7 TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
bit 6 TXABTm: Message Aborted bit(1)
1 = Message was aborted
0 = Message completed transmission successfully
bit 5 TXLARBm: Message Lost Arbitration bit(1)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERRm: Error Detected During Transmission bit(1)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQm: Message Send Request bit
1 = Requests that a message be sent; the bit automatically clears when the message is successfully
sent
0 = Clearing the bit to ‘0’ while set requests a message abort
bit 2 RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1: This bit is cleared when TXREQ is set.
Note: The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 308 2011-2013 Microchip Technology Inc.
21.5 ECAN Message Buffers
ECAN Message Buffers are part of RAM memory. They
are not ECAN Special Function Registers. The user
application must directly write into the RAM area that is
configured for ECAN Message Buffers. The location
and size of the buffer area is defined by the user
application.
BUFFER 21-1:
ECAN™
MESSAGE BUFFER WORD 0
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — SID10 SID9 SID8 SID7 SID6
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-2 SID<10:0>: Standard Identifier bits
bit 1 SRR: Substitute Remote Request bit
When IDE = 0:
1 = Message will request remote transmission
0 = Normal message
When IDE = 1:
The SRR bit must be set to ‘1’.
bit 0 IDE: Extended Identifier bit
1 = Message will transmit Extended Identifier
0 = Message will transmit Standard Identifier
BUFFER 21-2:
ECAN™
MESSAGE BUFFER WORD 1
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — — EID17 EID16 EID15 EID14
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-0 EID<17:6>: Extended Identifier bits
2011-2013 Microchip Technology Inc. DS70657G-page 309
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
(
BUFFER 21-3:
ECAN™
MESSAGE BUFFER WORD 2
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1
bit 15 bit 8
U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — — RB0 DLC3 DLC2 DLC1 DLC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 EID<5:0>: Extended Identifier bits
bit 9 RTR: Remote Transmission Request bit
When IDE = 1:
1 = Message will request remote transmission
0 = Normal message
When IDE = 0:
The RTR bit is ignored.
bit 8 RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
bit 7-5 Unimplemented: Read as ‘0’
bit 4 RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
bit 3-0 DLC<3:0>: Data Length Code bits
BUFFER 21-4: ECAN
™
MESSAGE BUFFER WORD 3
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 1
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Byte 1<15:8>: ECAN Message Byte 0 bits
bit 7-0 Byte 0<7:0>: ECAN Message Byte 1 bits
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 310 2011-2013 Microchip Technology Inc.
BUFFER 21-5: ECAN
™
MESSAGE BUFFER WORD 4
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 3
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Byte 3<15:8>: ECAN Message Byte 3 bits
bit 7-0 Byte 2<7:0>: ECAN Message Byte 2 bits
BUFFER 21-6: ECAN
™
MESSAGE BUFFER WORD 5
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 5
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 4
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Byte 5<15:8>: ECAN Message Byte 5 bits
bit 7-0 Byte 4<7:0>: ECAN Message Byte 4 bits
2011-2013 Microchip Technology Inc. DS70657G-page 311
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
BUFFER 21-7: ECAN
™
MESSAGE BUFFER WORD 6
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 7
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Byte 6
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Byte 7<15:8>: ECAN Message Byte 7 bits
bit 7-0 Byte 6<7:0>: ECAN Message Byte 6 bits
BUFFER 21-8:
ECAN™
MESSAGE BUFFER WORD 7
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — FILHIT<4:0>(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT<4:0>: Filter Hit Code bits(1)
Encodes number of filter that resulted in writing this buffer.
bit 7-0 Unimplemented: Read as ‘0’
Note 1: Only written by module for receive buffers, unused for transmit buffers.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 312 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 313
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
22.0 CHARGE TIME
MEASUREMENT UNIT (CTMU)
The Charge Time Measurement Unit is a flexible analog
module that provides accurate differential time measure-
ment between pulse sources, as well as asynchronous
pulse generation. Its key features include:
• Four Edge Input Trigger Sources
• Polarity Control for Each Edge Source
• Control of Edge Sequence
• Control of Response to Edges
• Precise Time Measurement Resolution of 1 ns
• Accurate Current Source Suitable for Capacitive
Measurement
• On-Chip Temperature Measurement using a
Built-in Diode
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance
or generate output pulses that are independent of the
system clock.
The CTMU module is ideal for interfacing with
capacitive-based sensors.The CTMU is controlled
through three registers: CTMUCON1, CTMUCON2
and CTMUICON. CTMUCON1 and CTMUCON2
enable the module and control edge source selection,
edge source polarity selection and edge sequencing.
The CTMUICON register controls the selection and
trim of the current source.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 33. “Charge
Time Measurement Unit (CTMU)”
(DS70661) in the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available on the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 314 2011-2013 Microchip Technology Inc.
FIGURE 22-1: CTMU BLOCK DIAGRAM
22.1 CTMU Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
22.1.1 KEY RESOURCES
•Section 33. “Charge Time Measurement Unit
(CTMU)” (DS70661)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
CTED1
CTED2
Current Source
Edge
Control
Logic
CTMUCON1 or CTMUCON2
Pulse
Generator
CTMUI to ADC
CMP1
Timer1
OC1
Current
Control
ITRIM<5:0>
IRNG<1:0>
CTMUICON
CTMU
Control
Logic
EDG1STAT
EDG2STAT
Analog-to-Digital
CTPLS
IC1
CMP1
C1IN1-
CDelay
CTMU TEMP
CTMU
Temperature
Sensor
Current Control Selection TGEN EDG1STAT, EDG2STAT
CTMU TEMP 0EDG1STAT = EDG2STAT
CTMUI to ADC 0EDG1STAT EDG2STAT
CTMUP 1EDG1STAT EDG2STAT
No Connect 1EDG1STAT = EDG2STAT
Trigger
TGEN
CTMUP
External Capacitor
for Pulse Generation
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 315
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
22.2 CTMU Control Registers
REGISTER 22-1: CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN(1)CTTRIG
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11 EDGEN: Edge Enable bit
1 = Hardware modules are used to trigger edges (TMRx, CTEDx, etc.)
0 = Software is used to trigger edges (manual set of EDGxSTAT)
bit 10 EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9 IDISSEN: Analog Current Source Control bit(1)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8 CTTRIG: ADC Trigger Control bit
1 = CTMU triggers ADC start of conversion
0 = CTMU does not trigger ADC start of conversion
bit 7-0 Unimplemented: Read as ‘0’
Note 1: The ADC module Sample-and-Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC
must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 316 2011-2013 Microchip Technology Inc.
REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
EDG2MOD EDG2POL EDG2SEL<3:0> — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 EDG1MOD: Edge 1 Edge Sampling Mode Selection bit
1 = Edge 1 is edge-sensitive
0 = Edge 1 is level-sensitive
bit 14 EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bits
1xxx = Reserved
01xx = Reserved
0011 = CTED1 pin
0010 = CTED2 pin
0001 = OC1 module
0000 = Timer1 module
bit 9 EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the edge source.
1 = Edge 2 has occurred
0 = Edge 2 has not occurred
bit 8 EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the edge source.
1 = Edge 1 has occurred
0 = Edge 1 has not occurred
bit 7 EDG2MOD: Edge 2 Edge Sampling Mode Selection bit
1 = Edge 2 is edge-sensitive
0 = Edge 2 is level-sensitive
bit 6 EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits
1111 = Reserved
01xx = Reserved
0100 = CMP1 module
0011 = CTED2 pin
0010 = CTED1 pin
0001 = OC1 module
0000 = IC1 module
bit 1-0 Unimplemented: Read as ‘0’
2011-2013 Microchip Technology Inc. DS70657G-page 317
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 22-3: CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ITRIM<5:0> IRNG<1:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 ITRIM<5:0>: Current Source Trim bits
011111 = Maximum positive change from nominal current + 62%
011110 = Maximum positive change from nominal current + 60%
•
•
•
000010 = Minimum positive change from nominal current + 4%
000001 = Minimum positive change from nominal current + 2%
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current – 2%
111110 = Minimum negative change from nominal current – 4%
•
•
•
100010 = Maximum negative change from nominal current – 60%
100001 = Maximum negative change from nominal current – 62%
bit 9-8 IRNG<1:0>: Current Source Range Select bits
11 = 100 Base Current(2)
10 = 10 Base Current(2)
01 = Base Current Level(2)
00 = 1000 Base Current(1,2)
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This current range is not available to be used with the internal temperature measurement diode.
2: Refer to the CTMU Current Source Specifications (Table 30-56) in Section 30.0 “Electrical
Characteristics” for the current range selection values.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 318 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 319
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
23.0 10-BIT/12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices have one
ADC module. The ADC module supports up to
16 analog input channels.
On ADC1, the AD12B bit (AD1CON1<10>) allows the
ADC module to be configured by the user as either a
10-bit, 4 Sample-and-Hold (S&H) ADC (default
configuration) or a 12-bit, 1 S&H ADC.
23.1 Key Features
23.1.1 10-BIT ADC CONFIGURATION
The 10-bit ADC configuration has the following key
features:
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 16 analog input pins
• Connections to three internal op amps
• Connections to the Charge Time Measurement Unit
(CTMU) and temperature measurement diode
• Channel selection and triggering can be controlled
by the Peripheral Trigger Generator (PTG)
• External voltage reference input pins
• Simultaneous sampling of:
- Up to four analog input pins
- Three op amp outputs
- Combinations of analog inputs and op amp
outputs
• Automatic Channel Scan mode
• Selectable conversion Trigger source
• Selectable Buffer Fill modes
• Four result alignment options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle modes
23.1.2 12-BIT ADC CONFIGURATION
The 12-bit ADC configuration supports all the features
listed above, with the exception of the following:
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only one S&H amplifier in the 12-bit
configuration; therefore, simultaneous sampling
of multiple channels is not supported.
Depending on the particular device pinout, the ADC
can have up to 16 analog input pins, designated AN0
through AN15. These analog inputs are shared with
op amp inputs and outputs, comparator inputs, and
external voltage references. When op amp/comparator
functionality is enabled, or an external voltage refer-
ence is used, the analog input that shares that pin is no
longer available. The actual number of analog input
pins, op amps and external voltage reference input
configuration depends on the specific device.
A block diagram of the ADC module is shown in
Figure 23-1. Figure 23-2 provides a diagram of the
ADC conversion clock period.
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Analog-to-
Digital Converter (ADC)” (DS70621) of
the “dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: The ADC module needs to be disabled
before modifying the AD12B bit.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 320 2011-2013 Microchip Technology Inc.
FIGURE 23-1: ADC MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS
0
1
+
–
CMP1
/OA1
0x
10
11
VREFL
VREFL
VREFL
+
–
CH0
0
1
VREFL
AN0-ANx
OA1-OA3
CH0Sx
CH0Nx
CH123Nx
00000
11111
OPMODE
OPMODE
OPMODE
A
B
1
0
CH0SA<4:0>(3)
CH0SB<4:0>(3)
CH0Sx
CH0Nx
CH0NA(3)
CH0NB(3)
CSCNA
CH123Sx
CH123Nx
CH123SA
CH123SB
CH123NA<2:0>
CH123NB<2:0>
S&H1
Alternate Input
Selection
Channel Scan
This diagram depicts all of the available
ADC connection options to the four S&H
amplifiers, which are designated: CH0,
CH1, CH2 and CH3.
The ANx analog pins or op amp outputs
are connected to the CH0-CH3 amplifi-
ers through the multiplexers, controlled
by the SFR control bits, CH0Sx,
CHONx, CH123Sx and CH123Nx.
A
B
A
B
A
B
+
–
CH1
+
–
CH2
+
–
CH3
0
1
CH123x
+
–OA2
0
1
CH123Sx
0x
10
11
CH123Nx
0x
10
11
CH123Nx
+
–OA3(5)
CH123Sx
AN0/OA2OUT/RA0
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
AN9/RPI27/RA11
AN1/C2IN1+/RA1
AN10/RPI28/RA12
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
AN8/C3IN1+/U1RTS/BCLK1/RC2
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN11/C1IN2-/U1CTS/RC11
+
–OA1
VREF+(1) AVDD AVSSVREF-(1)
VCFG<2:0> ADC1BUF0(4)
ADC1BUF1(4)
ADC1BUF2(4)
ADC1BUFF(4)
ADC1BUFE(4)
From CTMU
Current Source (CTMUI)
CTMU Temp
S&H2
S&H3
S&H0
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
3: These bits can be updated with Step commands from the PTG module. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information.
4: When ADDMAEN (AD1CON4<8>) = 1, enabling DMA, only ADC1BUF0 is used.
5: OA3 is not available for 28-pin devices.
Open
ALTS (MUXA/MUXB)
SAR ADC
VREFH VREFL
2011-2013 Microchip Technology Inc. DS70657G-page 321
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 23-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
1
0
ADC Conversion
Clock Multiplier
1, 2, 3, 4, 5,..., 256
AD1CON3<15>
TP(1)
TAD
6
AD1CON3<7:0>
Note 1: TP = 1/FP.
2: See the ADC electrical specifications in Section 30.0 “Electrical Characteristics” for the
exact RC clock value.
ADC Internal
RC Clock(2)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 322 2011-2013 Microchip Technology Inc.
23.2 ADC Helpful Tips
1. The SMPIx control bits in the AD1CON2 register:
a) Determine when the ADC interrupt flag is
set and an interrupt is generated, if
enabled.
b) When the CSCNA bit in the AD1CON2 reg-
isters is set to ‘1’, this determines when the
ADC analog scan channel list, defined in
the AD1CSSL/AD1CSSH registers, starts
over from the beginning.
c) When the DMA peripheral is not used
(ADDMAEN = 0), this determines when the
ADC Result Buffer Pointer to ADC1BUF0-
ADC1BUFF gets reset back to the
beginning at ADC1BUF0.
d) When the DMA peripheral is used
(ADDMAEN = 1), this determines when the
DMA Address Pointer is incremented after a
sample/conversion operation. ADC1BUF0 is
the only ADC buffer used in this mode. The
ADC Result Buffer Pointer to ADC1BUF0-
ADC1BUFF gets reset back to the beginning
at ADC1BUF0. The DMA address is
incremented after completion of every 32nd
sample/conversion operation. Conversion
results are stored in the ADC1BUF0 register
for transfer to RAM using DMA.
2. When the DMA module is disabled
(ADDMAEN = 0), the ADC has 16 result buffers.
ADC conversion results are stored sequentially
in ADC1BUF0-ADC1BUFF, regardless of which
analog inputs are being used subject to the
SMPIx bits and the condition described in 1c)
above. There is no relationship between the
ANx input being measured and which ADC
buffer (ADC1BUF0-ADC1BUFF) that the
conversion results will be placed in.
3. When the DMA module is enabled
(ADDMAEN = 1), the ADC module has only
1 ADC result buffer (i.e., ADC1BUF0) per ADC
peripheral and the ADC conversion result must
be read, either by the CPU or DMA controller,
before the next ADC conversion is complete to
avoid overwriting the previous value.
4. The DONE bit (AD1CON1<0>) is only cleared at
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely, even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this behav-
ior because the CPU code execution is faster
than the ADC. As a result, in Manual Sample
mode, particularly where the user’s code is set-
ting the SAMP bit (AD1CON1<1>), the DONE bit
should also be cleared by the user application
just before setting the SAMP bit.
5. Enabling op amps, comparator inputs and exter-
nal voltage references can limit the availability of
analog inputs (ANx pins). For example, when Op
Amp 2 is enabled, the pins for AN0, AN1 and AN2
are used by the op amp’s inputs and output. This
negates the usefulness of Alternate Input mode
since the MUXA selections use AN0-AN2. Care-
fully study the ADC block diagram to determine
the configuration that will best suit your applica-
tion. Configuration examples are available in
Section 16. “Analog-to-Digital Converter
(ADC)” (DS70621) in the “dsPIC33E/PIC24E
Family Reference Manual”.
23.3 ADC Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
23.3.1 KEY RESOURCES
•Section 16. “Analog-to-Digital Converter
(ADC)” (DS70621)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
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23.4 ADC Control Registers
REGISTER 23-1: AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
ADON — ADSIDL ADDMABM —AD12B FORM<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC, HS R/C-0, HC, HS
SSRC<2:0> SSRCG SIMSAM ASAM SAMP DONE(3)
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: ADC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 ADDMABM: DMA Buffer Build Mode bit
1 = DMA buffers are written in the order of conversion; the module provides an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer
0 = DMA buffers are written in Scatter/Gather mode; the module provides a Scatter/Gather address to
the DMA channel, based on the index of the analog input and the size of the DMA buffer.
bit 11 Unimplemented: Read as ‘0’
bit 10 AD12B: ADC 10-Bit or 12-Bit Operation Mode bit
1 = 12-bit, 1-channel ADC operation
0 = 10-bit, 4-channel ADC operation
bit 9-8 FORM<1:0>: Data Output Format bits
For 10-Bit Operation:
11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)
00 = Integer (DOUT = 0000 00dd dddd dddd)
For 12-Bit Operation:
11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>)
10 = Fractional (DOUT = dddd dddd dddd 0000)
01 = Signed integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>)
00 = Integer (DOUT = 0000 dddd dddd dddd)
Note 1: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
2: This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
3: Do not clear the DONE bit in software if Auto-Sample is enabled (ASAM = 1).
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bit 7-5 SSRC<2:0>: Sample Trigger Source Select bits
If SSRCG = 1:
111 = Reserved
110 = PTGO15 primary trigger compare ends sampling and starts conversion(1)
101 = PTGO14 primary trigger compare ends sampling and starts conversion(1)
100 = PTGO13 primary trigger compare ends sampling and starts conversion(1)
011 = PTGO12 primary trigger compare ends sampling and starts conversion(1)
010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion(2)
001 = PWM Generator 2 primary trigger compare ends sampling and starts conversion(2)
000 = PWM Generator 1 primary trigger compare ends sampling and starts conversion(2)
If SSRCG = 0:
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU ends sampling and starts conversion
101 = Reserved
100 = Timer5 compare ends sampling and starts conversion
011 = PWM primary Special Event Trigger ends sampling and starts conversion(2)
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on the INT0 pin ends sampling and starts conversion
000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode)
bit 4 SSRCG: Sample Trigger Source Group bit
See SSRC<2:0> for details.
bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)
In 12-bit mode (AD21B = 1), SIMSAM is Unimplemented and is Read as ‘0’:
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or samples CH0 and CH1
simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after the last conversion; SAMP bit is auto-set
0 = Sampling begins when the SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
1 = ADC Sample-and-Hold amplifiers are sampling
0 = ADC Sample-and-Hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If
SSRC<2:0> = 000, software can write ‘0’ to end sampling and start conversion. If SSRC<2:0> 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADC Conversion Status bit(3)
1 = ADC conversion cycle has completed
0 = ADC conversion has not started or is in progress
Automatically set by hardware when the A/D conversion is complete. Software can write ‘0’ to clear the
DONE status bit (software is not allowed to write ‘1’). Clearing this bit does NOT affect any operation in
progress. Automatically cleared by hardware at the start of a new conversion.
REGISTER 23-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
Note 1: See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
2: This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
3: Do not clear the DONE bit in software if Auto-Sample is enabled (ASAM = 1).
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REGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
VCFG<2:0> —— CSCNA CHPS<1:0>
bit 15 bit 8
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS SMPI<4:0> BUFM ALTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits
bit 12-11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit
1 = Scans inputs for CH0+ during Sample MUXA
0 = Does not scan inputs
bit 9-8 CHPS<1:0>: Channel Select bits
In 12-bit mode (AD21B = 1), the CHPS<1:0> bits are Unimplemented and are Read as ‘0’:
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling the second half of the buffer; the user application should access data in the
first half of the buffer
0 = ADC is currently filling the first half of the buffer; the user application should access data in the
second half of the buffer
bit 6-2 SMPI<4:0>: Increment Rate bits
When ADDMAEN = 0:
x1111 = Generates interrupt after completion of every 16th sample/conversion operation
x1110 = Generates interrupt after completion of every 15th sample/conversion operation
•
•
•
x0001 = Generates interrupt after completion of every 2nd sample/conversion operation
x0000 = Generates interrupt after completion of every sample/conversion operation
When ADDMAEN = 1:
11111 = Increments the DMA address after completion of every 32nd sample/conversion operation
11110 = Increments the DMA address after completion of every 31st sample/conversion operation
•
•
•
00001 = Increments the DMA address after completion of every 2nd sample/conversion operation
00000 = Increments the DMA address after completion of every sample/conversion operation
Value VREFH VREFL
000 AVDD Avss
001 External VREF+Avss
010 AVDD External VREF-
011 External VREF+ External VREF-
1xx AVDD AVSS
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bit 1 BUFM: Buffer Fill Mode Select bit
1 = Starts the buffer filling the first half of the buffer on the first interrupt and the second half of the
buffer on next interrupt
0 = Always starts filling the buffer from the start address.
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample MUXA on first sample and Sample MUXB on next sample
0 = Always uses channel input selects for Sample MUXA
REGISTER 23-2: AD1CON2: ADC1 CONTROL REGISTER 2 (CONTINUED)
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REGISTER 23-3: AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC —— SAMC<4:0>(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS<7:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: ADC Conversion Clock Source bit
1 = ADC internal RC clock
0 = Clock derived from system clock
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111 = TP • (ADCS<7:0> + 1) = TP •256 = TAD
•
•
•
00000010 = TP • (ADCS<7:0> + 1) = TP •3 = TAD
00000001 = TP • (ADCS<7:0> + 1) = TP •2 = TAD
00000000 = TP • (ADCS<7:0> + 1) = TP •1 = TAD
Note 1: This bit is only used if SSRC<2:0> (AD1CON1<7:5>) = 111 and SSRCG (AD1CON1<4>) = 0.
2: This bit is not used if ADRC (AD1CON3<15>) = 1.
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REGISTER 23-4: AD1CON4: ADC1 CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — ADDMAEN
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — DMABL<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 ADDMAEN: ADC DMA Enable bit
1 = Conversion results are stored in the ADC1BUF0 register for transfer to RAM using DMA
0 = Conversion results are stored in ADC1BUF0 through ADC1BUFF registers; DMA will not be used
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits
111 = Allocates 128 words of buffer to each analog input
110 = Allocates 64 words of buffer to each analog input
101 = Allocates 32 words of buffer to each analog input
100 = Allocates 16 words of buffer to each analog input
011 = Allocates 8 words of buffer to each analog input
010 = Allocates 4 words of buffer to each analog input
001 = Allocates 2 words of buffer to each analog input
000 = Allocates 1 word of buffer to each analog input
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 23-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NB<1:0> CH123SB
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CH123NA<1:0> CH123SA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXB bits
In 12-bit mode (AD21B = 1), CH123NB is Unimplemented and is Read as ‘0’:
bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample MUXB bit
In 12-bit mode (AD21B = 1), CH123SB is Unimplemented and is Read as ‘0’:
bit 7-3 Unimplemented: Read as ‘0’
bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample MUXA bits
In 12-bit mode (AD21B = 1), CH123NA is Unimplemented and is Read as ‘0’:
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
Value ADC Channel
CH1 CH2 CH3
11 AN9 AN10 AN11
10(1,2)OA3/AN6 AN7 AN8
0x VREFL VREFL VREFL
Value ADC Channel
CH1 CH2 CH3
1(2)OA1/AN3 OA2/AN0 OA3/AN6
0(1,2)OA2/AN0 AN1 AN2
Value ADC Channel
CH1 CH2 CH3
11 AN9 AN10 AN11
10(1,2)OA3/AN6 AN7 AN8
0x VREFL VREFL VREFL
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bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample MUXA bit
In 12-bit mode (AD21B = 1), CH123SA is Unimplemented and is Read as ‘0’:
REGISTER 23-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED)
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
Value ADC Channel
CH1 CH2 CH3
1(2)OA1/AN3 OA2/AN0 OA3/AN6
0(1,2)OA2/AN0 AN1 AN2
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REGISTER 23-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB —— CH0SB<4:0>(1)
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA —— CH0SA<4:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for Sample MUXB bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample MUXB bits(1)
11111 = Open; use this selection with CTMU capacitive and time measurement
11110 = Channel 0 positive input is connected to the CTMU temperature measurement diode (CTMU TEMP)
11101 = Reserved
11100 = Reserved
11011 = Reserved
11010 = Channel 0 positive input is the output of OA3/AN6(2,3)
11001 = Channel 0 positive input is the output of OA2/AN0(2)
11000 = Channel 0 positive input is the output of OA1/AN3(2)
10111 = Reserved
•
•
•
10000 = Reserved
01111 = Channel 0 positive input is AN15(3)
01110 = Channel 0 positive input is AN14(3)
01101 = Channel 0 positive input is AN13(3)
•
•
•
00010 = Channel 0 positive input is AN2(3)
00001 = Channel 0 positive input is AN1(3)
00000 = Channel 0 positive input is AN0(3)
bit 7 CH0NA: Channel 0 Negative Input Select for Sample MUXA bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
bit 6-5 Unimplemented: Read as ‘0’
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1); otherwise,
the ANx input is used.
3: See the “Pin Diagrams” section for the available analog channels for each device.
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bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample MUXA bits(1)
11111 = Open; use this selection with CTMU capacitive and time measurement
11110 = Channel 0 positive input is connected to the CTMU temperature measurement diode (CTMU TEMP)
11101 = Reserved
11100 = Reserved
11011 = Reserved
11010 = Channel 0 positive input is the output of OA3/AN6(2,3)
11001 = Channel 0 positive input is the output of OA2/AN0(2)
11000 = Channel 0 positive input is the output of OA1/AN3(2)
10110 = Reserved
•
•
•
10000 = Reserved
01111 = Channel 0 positive input is AN15(1,3)
01110 = Channel 0 positive input is AN14(1,3)
01101 = Channel 0 positive input is AN13(1,3)
•
•
•
00010 = Channel 0 positive input is AN2(1,3)
00001 = Channel 0 positive input is AN1(1,3)
00000 = Channel 0 positive input is AN0(1,3)
REGISTER 23-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED)
Note 1: AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1); otherwise,
the ANx input is used.
3: See the “Pin Diagrams” section for the available analog channels for each device.
2011-2013 Microchip Technology Inc. DS70657G-page 333
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 23-7: AD1CSSH: ADC1 INPUT SCAN SELECT REGISTER HIGH(1)
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
CSS31 CSS30 — — —CSS26
(2)CSS25(2)CSS24(2)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CSS31: ADC Input Scan Selection bit
1 = Selects CTMU capacitive and time measurement for input scan (Open)
0 = Skips CTMU capacitive and time measurement for input scan (Open)
bit 14 CSS30: ADC Input Scan Selection bit
1 = Selects CTMU on-chip temperature measurement for input scan (CTMU TEMP)
0 = Skips CTMU on-chip temperature measurement for input scan (CTMU TEMP)
bit 13-11 Unimplemented: Read as ‘0’
bit 10 CSS26: ADC Input Scan Selection bit(2)
1 = Selects OA3/AN6 for input scan
0 = Skips OA3/AN6 for input scan
bit 9 CSS25: ADC Input Scan Selection bit(2)
1 = Selects OA2/AN0 for input scan
0 = Skips OA2/AN0 for input scan
bit 8 CSS24: ADC Input Scan Selection bit(2)
1 = Selects OA1/AN3 for input scan
0 = Skips OA1/AN3 for input scan
bit 7-0 Unimplemented: Read as ‘0’
Note 1: All AD1CSSH bits can be selected by user software. However, inputs selected for scan, without a
corresponding input on the device, convert VREFL.
2: The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
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REGISTER 23-8: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CSS<15:0>: ADC Input Scan Selection bits
1 = Selects ANx for input scan
0 = Skips ANx for input scan
Note 1: On devices with less than 16 analog inputs, all AD1CSSL bits can be selected by the user. However,
inputs selected for scan, without a corresponding input on the device, convert VREFL.
2: CSSx = ANx, where x = 0-15.
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
24.0 PERIPHERAL TRIGGER
GENERATOR (PTG) MODULE
24.1 Module Introduction
The Peripheral Trigger Generator (PTG) provides a
means to schedule complex high-speed peripheral
operations that would be difficult to achieve using soft-
ware. The PTG module uses 8-bit commands, called
“Steps”, that the user writes to the PTG Queue regis-
ters (PTGQUE0-PTQUE7), which perform operations,
such as wait for input signal, generate output trigger
and wait for timer.
The PTG module has the following major features:
• Multiple clock sources
• Two 16-bit general purpose timers
• Two 16-bit general limit counters
• Configurable for rising or falling edge triggering
• Generates processor interrupts to include:
- Four configurable processor interrupts
- Interrupt on a Step event in Single-Step mode
- Interrupt on a PTG Watchdog Timer time-out
• Able to receive trigger signals from these
peripherals:
-ADC
-PWM
- Output Compare
- Input Capture
- Op Amp/Comparator
-INT2
• Able to trigger or synchronize to these
peripherals:
- Watchdog Timer
- Output Compare
- Input Capture
-ADC
-PWM
- Op Amp/Comparator
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 32. Peripheral
Trigger Generator (PTG)” (DS70669) of
the “dsPIC33E/PIC24E Family Refer-
ence Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
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FIGURE 24-1: PTG BLOCK DIAGRAM
16-Bit Data Bus
PTGQPTR<4:0>
Command
Decoder
PTGHOLD
PTGADJ
PTG Watchdog
Timer(1)
PTG Control Logic
PTGWDTIF
PTG General
Purpose
Timerx
PTG Loop
Counter x
Clock Inputs
FP
TAD
T1CLK
T2CLK
T3CLK
PTGCLK<2:0>
PTGL0<15:0> PTGTxLIM<15:0> PTGCxLIM<15:0>
PTGBTE<15:0>
PTGO0
PTGSDLIM<15:0>
PTG Step
Delay Timer
PWM
OC1
OC2
IC1
CMPx
ADC
INT2
PTGCON<15:0>
PTG Interrupts Trigger Outputs
AD1CHS0<15:0>
Step Command
Step Command
PTGSTEPIF
Trigger Inputs
PTGO31
•
•
•
PTG0IF
PTG3IF
•
•
•
Step Command
Step Command
FOSC
PTGDIV<4:0>
PTGCST<15:0>
Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.
PTGQUE0
PTGQUE1
PTGQUE2
PTGQUE3
PTGQUE5
PTGQUE4
PTGQUE6
PTGQUE7
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24.2 PTG Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
24.2.1 KEY RESOURCES
•Section 32. “Peripheral Trigger Generator”
(DS70669)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
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24.3 PTG Control Registers
REGISTER 24-1: PTGCST: PTG CONTROL/STATUS REGISTER
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
PTGEN — PTGSIDL PTGTOGL —PTGSWT
(2)PTGSSEN PTGIVIS
bit 15 bit 8
R/W-0 HS-0 U-0 U-0 U-0 U-0 R/W-0
PTGSTRT PTGWDTO — — — —PTGITM<1:0>
(1)
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTGEN: Module Enable bit
1 = PTG module is enabled
0 = PTG module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 PTGSIDL: PTG Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 PTGTOGL: PTG TRIG Output Toggle Mode bit
1 = Toggle state of the PTGOx for each execution of the PTGTRIG command
0 = Each execution of the PTGTRIG command will generate a single PTGOx pulse determined by the
value in the PTGPWDx bits
bit 11 Unimplemented: Read as ‘0’
bit 10 PTGSWT: PTG Software Trigger bit(2)
1 = Triggers the PTG module
0 = No action (clearing this bit will have no effect)
bit 9 PTGSSEN: PTG Enable Single-Step bit
1 = Enables Single-Step mode
0 = Disables Single-Step mode
bit 8 PTGIVIS: PTG Counter/Timer Visibility Control bit
1 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the current values of their
corresponding counter/timer registers (PTGSD, PTGCx, PTGTx)
0 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the value previously written
to those limit registers
bit 7 PTGSTRT: PTG Start Sequencer bit
1 = Starts to sequentially execute commands (Continuous mode)
0 = Stops executing commands
bit 6 PTGWDTO: PTG Watchdog Timer Time-out Status bit
1 = PTG Watchdog Timer has timed out
0 = PTG Watchdog Timer has not timed out.
bit 5-2 Unimplemented: Read as ‘0’
Note 1: These bits apply to the PTGWHI and PTGWLO commands only.
2: This bit is only used with the PTGCTRL Step command software trigger option.
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bit 1-0 PTGITM<1:0>: PTG Input Trigger Command Operating Mode bits(1)
11 = Single level detect with Step delay not executed on exit of command (regardless of the PTGCTRL
command)
10 = Single level detect with Step delay executed on exit of command
01 = Continuous edge detect with Step delay not executed on exit of command (regardless of the
PTGCTRL command)
00 = Continuous edge detect with Step delay executed on exit of command
REGISTER 24-1: PTGCST: PTG CONTROL/STATUS REGISTER (CONTINUED)
Note 1: These bits apply to the PTGWHI and PTGWLO commands only.
2: This bit is only used with the PTGCTRL Step command software trigger option.
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REGISTER 24-2: PTGCON: PTG CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGCLK<2:0> PTGDIV<4:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
PTGPWD<3:0> — PTGWDT<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 PTGCLK<2:0>: Select PTG Module Clock Source bits
111 = Reserved
110 = Reserved
101 = PTG module clock source will be T3CLK
100 = PTG module clock source will be T2CLK
011 = PTG module clock source will be T1CLK
010 = PTG module clock source will be T
AD
001 = PTG module clock source will be FOSC
000 = PTG module clock source will be FP
bit 12-8 PTGDIV<4:0>: PTG Module Clock Prescaler (divider) bits
11111 = Divide-by-32
11110 = Divide-by-31
•
•
•
00001 = Divide-by-2
00000 = Divide-by-1
bit 7-4 PTGPWD<3:0>: PTG Trigger Output Pulse Width bits
1111 = All trigger outputs are 16 PTG clock cycles wide
1110 = All trigger outputs are 15 PTG clock cycles wide
•
•
•
0001 = All trigger outputs are 2 PTG clock cycles wide
0000 = All trigger outputs are 1 PTG clock cycle wide
bit 3 Unimplemented: Read as ‘0’
bit 2-0 PTGWDT<2:0>: Select PTG Watchdog Timer Time-out Count Value bits
111 = Watchdog Timer will time-out after 512 PTG clocks
110 = Watchdog Timer will time-out after 256 PTG clocks
101 = Watchdog Timer will time-out after 128 PTG clocks
100 = Watchdog Timer will time-out after 64 PTG clocks
011 = Watchdog Timer will time-out after 32 PTG clocks
010 = Watchdog Timer will time-out after 16 PTG clocks
001 = Watchdog Timer will time-out after 8 PTG clocks
000 = Watchdog Timer is disabled
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REGISTER 24-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCTS4 ADCTS3 ADCTS2 ADCTS1 IC4TSS IC3TSS IC2TSS IC1TSS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OC4CS OC3CS OC2CS OC1CS OC4TSS OC3TSS OC2TSS OC1TSS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADCTS4: Sample Trigger PTGO15 for ADC bit
1 = Generates Trigger when the broadcast command is executed
0 = Does not generate Trigger when the broadcast command is executed
bit 14 ADCTS3: Sample Trigger PTGO14 for ADC bit
1 = Generates Trigger when the broadcast command is executed
0 = Does not generate Trigger when the broadcast command is executed
bit 13 ADCTS2: Sample Trigger PTGO13 for ADC bit
1 = Generates Trigger when the broadcast command is executed
0 = Does not generate Trigger when the broadcast command is executed
bit 12 ADCTS1: Sample Trigger PTGO12 for ADC bit
1 = Generates Trigger when the broadcast command is executed
0 = Does not generate Trigger when the broadcast command is executed
bit 11 IC4TSS: Trigger/Synchronization Source for IC4 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 10 IC3TSS: Trigger/Synchronization Source for IC3 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 9 IC2TSS: Trigger/Synchronization Source for IC2 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 8 IC1TSS: Trigger/Synchronization Source for IC1 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 7 OC4CS: Clock Source for OC4 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
bit 6 OC3CS: Clock Source for OC3 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
bit 5 OC2CS: Clock Source for OC2 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.
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bit 4 OC1CS: Clock Source for OC1 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
bit 3 OC4TSS: Trigger/Synchronization Source for OC4 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 2 OC3TSS: Trigger/Synchronization Source for OC3 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 1 OC2TSS: Trigger/Synchronization Source for OC2 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
bit 0 OC1TSS: Trigger/Synchronization Source for OC1 bit
1 = Generates Trigger/Synchronization when the broadcast command is executed
0 = Does not generate Trigger/Synchronization when the broadcast command is executed
REGISTER 24-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) (CONTINUED)
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.
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REGISTER 24-4: PTGT0LIM: PTG TIMER0 LIMIT REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGT0LIM<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGT0LIM<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGT0LIM<15:0>: PTG Timer0 Limit Register bits
General Purpose Timer0 Limit register (effective only with a PTGT0 Step command).
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 24-5: PTGT1LIM: PTG TIMER1 LIMIT REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGT1LIM<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGT1LIM<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGT1LIM<15:0>: PTG Timer1 Limit Register bits
General Purpose Timer1 Limit register (effective only with a PTGT1 Step command).
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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REGISTER 24-6: PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGSDLIM<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGSDLIM<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGSDLIM<15:0>: PTG Step Delay Limit Register bits
Holds a PTG Step delay value representing the number of additional PTG clocks between the start of
a Step command and the completion of a Step command.
Note 1: A base Step delay of one PTG clock is added to any value written to the PTGSDLIM register
(Step Delay = (PTGSDLIM) + 1).
2: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 24-7: PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGC0LIM<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGC0LIM<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGC0LIM<15:0>: PTG Counter 0 Limit Register bits
May be used to specify the loop count for the PTGJMPC0 Step command or as a limit register for the
General Purpose Counter 0.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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REGISTER 24-8: PTGC1LIM: PTG COUNTER 1 LIMIT REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGC1LIM<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGC1LIM<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGC1LIM<15:0>: PTG Counter 1 Limit Register bits
May be used to specify the loop count for the PTGJMPC1 Step command or as a limit register for the
General Purpose Counter 1.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 24-9: PTGHOLD: PTG HOLD REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGHOLD<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGHOLD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGHOLD<15:0>: PTG General Purpose Hold Register bits
Holds user-supplied data to be copied to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 registers
with the PTGCOPY command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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REGISTER 24-10: PTGADJ: PTG ADJUST REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGADJ<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGADJ<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGADJ<15:0>: PTG Adjust Register bits
This register holds user-supplied data to be added to the PTGTxLIM, PTGCxLIM, PTGSDLIM or
PTGL0 registers with the PTGADD command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 24-11: PTGL0: PTG LITERAL 0 REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGL0<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTGL0<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTGL0<15:0>: PTG Literal 0 Register bits
This register holds the 16-bit value to be written to the AD1CHS0 register with the PTGCTRL Step
command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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REGISTER 24-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —PTGQPTR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Unimplemented: Read as ‘0’
bit 4-0 PTGQPTR<4:0>: PTG Step Queue Pointer Register bits
This register points to the currently active Step command in the Step queue.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 24-13: PTGQUEx: PTG STEP QUEUE REGISTER x (x = 0-7)(1,3)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STEP(2x + 1)<7:0>(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STEP(2x)<7:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 STEP(2x + 1)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x + 1) command byte.
bit 7-0 STEP(2x)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x) command byte.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: Refer to Table 24-1 for the Step command encoding.
3: The Step registers maintain their values on any type of Reset.
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24.4 Step Commands and Format
TABLE 24-1: PTG STEP COMMAND FORMAT
Step Command Byte:
STEPx<7:0>
CMD<3:0> OPTION<3:0>
bit 7 bit 4 bit 3 bit 0
bit 7-4 CMD<3:0> Step
Command Command Description
0000 PTGCTRL Execute control command as described by OPTION<3:0>.
0001 PTGADD Add contents of PTGADJ register to target register as described by
OPTION<3:0>.
PTGCOPY Copy contents of PTGHOLD register to target register as described by
OPTION<3:0>.
001x PTGSTRB Copy the value contained in CMD<0>:OPTION<3:0> to the CH0SA<4:0> bits
(AD1CHS0<4:0>).
0100 PTGWHI Wait for a low-to-high edge input from the selected PTG trigger input as
described by OPTION<3:0>.
0101 PTGWLO Wait for a high-to-low edge input from the selected PTG trigger input as
described by OPTION<3:0>.
0110 Reserved Reserved.
0111 PTGIRQ Generate individual interrupt request as described by OPTION3<:0>.
100x PTGTRIG Generate individual trigger output as described by <<CMD<0>:OPTION<3:0>>.
101x PTGJMP Copy the value indicated in <<CMD<0>:OPTION<3:0>> to the Queue Pointer
(PTGQPTR) and jump to that Step queue.
110x PTGJMPC0 PTGC0 = PTGC0LIM: Increment the Queue Pointer (PTGQPTR).
PTGC0 PTGC0LIM: Increment Counter 0 (PTGC0) and copy the value
indicated in <<CMD<0>:OPTION<3:0>> to the Queue Pointer (PTGQPTR),
and jump to that Step queue
111x PTGJMPC1 PTGC1 = PTGC1LIM: Increment the Queue Pointer (PTGQPTR).
PTGC1 PTGC1LIM: Increment Counter 1 (PTGC1) and copy the value
indicated in <<CMD<0>:OPTION<3:0>> to the Queue Pointer (PTGQPTR),
and jump to that Step queue.
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
2: Refer to Table 24-2 for the trigger output descriptions.
3: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
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TABLE 24-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0 Step
Command OPTION<3:0> Option Description
PTGCTRL(1)0000 Reserved.
0001 Reserved.
0010 Disable Step Delay Timer (PTGSD).
0011 Reserved.
0100 Reserved.
0101 Reserved.
0110 Enable Step Delay Timer (PTGSD).
0111 Reserved.
1000 Start and wait for the PTG Timer0 to match the Timer0 Limit Register.
1001 Start and wait for the PTG Timer1 to match the Timer1 Limit Register.
1010 Reserved.
1011 Wait for the software trigger bit transition from low-to-high before continuing
(PTGSWT = 0 to 1).
1100 Copy contents of the Counter 0 register to the AD1CHS0 register.
1101 Copy contents of the Counter 1 register to the AD1CHS0 register.
1110 Copy contents of the Literal 0 register to the AD1CHS0 register.
1111 Generate triggers indicated in the Broadcast Trigger Enable register
(PTGBTE).
PTGADD(1)0000 Add contents of the PTGADJ register to the Counter 0 Limit register (PTGC0LIM).
0001 Add contents of the PTGADJ register to the Counter 1 Limit register (PTGC1LIM).
0010 Add contents of the PTGADJ register to the Timer0 Limit register (PTGT0LIM).
0011 Add contents of the PTGADJ register to the Timer1 Limit register (PTGT1LIM).
0100 Add contents of the PTGADJ register to the Step Delay Limit register (PTGSDLIM).
0101 Add contents of the PTGADJ register to the Literal 0 register (PTGL0).
0110 Reserved.
0111 Reserved.
PTGCOPY(1)1000 Copy contents of the PTGHOLD register to the Counter 0 Limit register
(PTGC0LIM).
1001 Copy contents of the PTGHOLD register to the Counter 1 Limit register
(PTGC1LIM).
1010 Copy contents of the PTGHOLD register to the Timer0 Limit register
(PTGT0LIM).
1011 Copy contents of the PTGHOLD register to the Timer1 Limit register
(PTGT1LIM).
1100 Copy contents of the PTGHOLD register to the Step Delay Limit register
(PTGSDLIM).
1101 Copy contents of the PTGHOLD register to the Literal 0 register (PTGL0).
1110 Reserved.
1111 Reserved.
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
2: Refer to Table 24-2 for the trigger output descriptions.
3: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 350 2011-2013 Microchip Technology Inc.
TABLE 24-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0 Step
Command OPTION<3:0> Option Description
PTGWHI(1)
or
PTGWLO(1)
0000 PWM Special Event Trigger.(3)
0001 PWM master time base synchronization output.(3)
0010 PWM1 interrupt.(3)
0011 PWM2 interrupt.(3)
0100 PWM3 interrupt.(3)
0101 Reserved.
0110 Reserved.
0111 OC1 Trigger event.
1000 OC2 Trigger event.
1001 IC1 Trigger event.
1010 CMP1 Trigger event.
1011 CMP2 Trigger event.
1100 CMP3 Trigger event.
1101 CMP4 Trigger event.
1110 ADC conversion done interrupt.
1111 INT2 external interrupt.
PTGIRQ(1)0000 Generate PTG Interrupt 0.
0001 Generate PTG Interrupt 1.
0010 Generate PTG Interrupt 2.
0011 Generate PTG Interrupt 3.
0100 Reserved.
•
•
•
•
•
•
1111 Reserved.
PTGTRIG(2)00000 PTGO0.
00001 PTGO1.
•
•
•
•
•
•
11110 PTGO30.
11111 PTGO31.
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
2: Refer to Table 24-2 for the trigger output descriptions.
3: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2011-2013 Microchip Technology Inc. DS70657G-page 351
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 24-2: PTG OUTPUT DESCRIPTIONS
PTG Output
Number PTG Output Description
PTGO0 Trigger/Synchronization Source for OC1
PTGO1 Trigger/Synchronization Source for OC2
PTGO2 Trigger/Synchronization Source for OC3
PTGO3 Trigger/Synchronization Source for OC4
PTGO4 Clock Source for OC1
PTGO5 Clock Source for OC2
PTGO6 Clock Source for OC3
PTGO7 Clock Source for OC4
PTGO8 Trigger/Synchronization Source for IC1
PTGO9 Trigger/Synchronization Source for IC2
PTGO10 Trigger/Synchronization Source for IC3
PTGO11 Trigger/Synchronization Source for IC4
PTGO12 Sample Trigger for ADC
PTGO13 Sample Trigger for ADC
PTGO14 Sample Trigger for ADC
PTGO15 Sample Trigger for ADC
PTGO16 PWM Time Base Synchronous Source for PWM(1)
PTGO17 PWM Time Base Synchronous Source for PWM(1)
PTGO18 Mask Input Select for Op Amp/Comparator
PTGO19 Mask Input Select for Op Amp/Comparator
PTGO20 Reserved
PTGO21 Reserved
PTGO22 Reserved
PTGO23 Reserved
PTGO24 Reserved
PTGO25 Reserved
PTGO26 Reserved
PTGO27 Reserved
PTGO28 Reserved
PTGO29 Reserved
PTGO30 PTG Output to PPS Input Selection
PTGO31 PTG Output to PPS Input Selection
Note 1: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 352 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 353
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
25.0 OP AMP/COMPARATOR
MODULE
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices contain up
to four comparators, which can be configured in various
ways. Comparators, CMP1, CMP2 and CMP3, also
have the option to be configured as op amps, with the
output being brought to an external pin for gain/filtering
connections. As shown in Figure 25-1, individual
comparator options are specified by the comparator
module’s Special Function Register (SFR) control bits.
These options allow users to:
• Select the edge for trigger and interrupt generation
• Configure the comparator voltage reference
• Configure output blanking and masking
• Configure as a comparator or op amp
(CMP1, CMP2 and CMP3 only)
FIGURE 25-1: OP AMP/COMPARATOR x MODULE BLOCK DIAGRAM (MODULES 1, 2 AND 3)
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 26. “Op Amp/
Comparator” (DS70357) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Op Amp/Comparator 3 is not available on
the dsPIC33EPXXXGP502/MC502/MC202
and PIC24EP256GP/MC202 (28-pin)
devices.
Note: Not all op amp/comparator input/output
connections are available on all devices.
See the “Pin Diagrams” section for
available connections.
Blanking
Function
Digital
Filter
CxOUT
(1)
(see Figure 25-4)(see Figure 25-5)
PTG Trigger
Input
0
1
00
01
CxIN1+
CVREFIN(1)
CxIN1-
CXIN2-(1)
Note 1: This input/output is not available as a selection when configured as an op amp (OPMODE (CMxCON<10>) = 1).
2: This module can be configured either as an op amp or a comparator using the OPMODE bit.
3: When configured as an op amp (OPMODE = 1), the ADC samples the op amp output; otherwise, the ADC
samples the ANx pin.
CMPx
–
+
VIN-
VIN+
CCH<1:0> (CMxCON<1:0>)
CREF (CMxCON<4>)
Op Amp/Comparator(2)
Op Ampx
–
+
OAx/ANx
(3)
OAxOUT/ANx
OPMODE (CMxCON<10>)
(to ADC)
RINT
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 354 2011-2013 Microchip Technology Inc.
FIGURE 25-2: COMPARATOR MODULE BLOCK DIAGRAM (MODULE 4)
FIGURE 25-3: OP AMP/COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CMP4
Blanking
Function
Digital
Filter
(see Figure 25-4)(see Figure 25-5)
–
+
VIN+
C4OUT
Trigger
Output
C4IN1+
CVREFIN
VIN-
1
0
11
00
CCH<1:0> (CM4CON<1:0>)
OA3/AN6
C4IN1-
CREF (CMxCON<4>)
01
10
OA1/AN3
OA2/AN0
8R
R
CVREN
CVRSS = 0
AVDD
VREF+CVRSS = 1
8R
R
R
R
R
R
R
16 Steps
CVRR
CVREF1O
CVR3
CVR2
CVR1
CVR0
CVRCON<3:0>
AVSS
CVRSRC
CVR1OE
CVREFIN
VREFSEL
CVREF2O(1)
CVR2OE
Note 1: This reference is (AVDD + AVSS)/2.
AVSS
AVDD
1
0
16-to-1 MUX
(CVRCON<6>)
(CVRCON<14>)
(CVRCON<10>)
2011-2013 Microchip Technology Inc. DS70657G-page 355
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 25-4: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM
FIGURE 25-5: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM
SELSRCA<3:0>
SELSRCB<3:0>
SELSRCC<3:0>
AND
CMxMSKCON
MUX A
MAI
MBI
MCI
Comparator Output
To Digital
Signals
Filter
OR
Blanking
Blanking
Blanking
Signals
Signals
ANDI
MASK
“AND-OR” Function
HLMS
MUX BMUX C
Blanking
Logic
(CMxMSKCON<15)
(CMxMSKSRC<11:8)
(CMxMSKSRC<7:4)
(CMxMSKSRC<3:0>)
MBI
MCI
MAI
MBI
MCI
MAI
CXOUT
CFLTREN
Digital Filter
TxCLK
(1,2)
SYNCO1
(3)
FP
(4)
FOSC
(4)
CFSEL<2:0>
CFDIV
Note 1: See the Type C Timer Block Diagram (Figure 13-2).
2: See the Type B Timer Block Diagram (Figure 13-1).
3: See the High-Speed PWMx Module Register Interconnection Diagram (Figure 16-2).
4: See the Oscillator System Diagram (Figure 9-1).
From Blanking Logic
1xx
010
000
001
1
0
(CM
xFLTR<6:4>)
(CM
xFLTR<3>)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 356 2011-2013 Microchip Technology Inc.
25.1 Op Amp Application
Considerations
There are two configurations to take into consider-
ation when designing with the op amp modules that
are available in the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X devices. Configuration A (see Figure 25-6)
takes advantage of the internal connection to the ADC
module to route the output of the op amp directly to the
ADC for measurement. Configuration B (see
Figure 25-7) requires that the designer externally route
the output of the op amp (OAxOUT) to a separate ana-
log input pin (ANy) on the device. Table 30-55 in
Section 30.0 “Electrical Characteristics” describes
the performance characteristics for the op amps, distin-
guishing between the two configuration types where
applicable.
25.1.1 OP AMP CONFIGURATION A
Figure 25-6 shows a typical inverting amplifier circuit
taking advantage of the internal connections from the
op amp output to the input of the ADC. The advantage of
this configuration is that the user does not need to con-
sume another analog input (ANy) on the device, and
allows the user to simultaneously sample all three op
amps with the ADC module, if needed. However, the
presence of the internal resistance, RINT1, adds an error
in the feedback path. Since RINT1 is an internal resis-
tance, in relation to the op amp output (VOAxOUT) and
ADC internal connection (VADC), RINT1 must be included
in the numerator term of the transfer function. See
Table 30-53 in Section 30.0 “Electrical Characteris-
tics” for the typical value of RINT1. Table 30-60 and
Table 30-61 in Section 30.0 “Electrical Characteris-
tics” describe the minimum sample time (TSAMP)
requirements for the ADC module in this configuration.
Figure 25-6 also defines the equations that should be
used when calculating the expected voltages at points,
VADC and VOAXOUT.
FIGURE 25-6: OP AMP CONFIGURATION A
–
+
CxIN1-
CxIN1+
R1
ADC(3)
OAxOUT
RINT1(1)
RFEEDBACK(2)
OAx
(to ADC)
Op Ampx
Note 1: See Table 30-53 for the Typical value.
2: See Table 30-53 for the Minimum value for the feedback resistor.
3: See Table 30-60 and Table 30-61 for the minimum sample time (TSAMP).
4: CVREF1O or CVREF2O are two options that are available for supplying bias voltage to the op amps.
VIN
VADC
(VOAXOUT)
VOAxOUT
RFEEDBACK
R1
------------------------------
Bias Voltage V–IN
=
VADC
RFEEDBACK RINT1
+
R1
---------------------------------------------------
Bias Voltage V–IN
=
Bias
Voltage
(4)
2011-2013 Microchip Technology Inc. DS70657G-page 357
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
25.1.2 OP AMP CONFIGURATION B
Figure 25-7 shows a typical inverting amplifier circuit
with the output of the op amp (OAxOUT) externally
routed to a separate analog input pin (ANy) on the
device. This op amp configuration is slightly different in
terms of the op amp output and the ADC input
connection, therefore, RINT1 is not included in the
transfer function. However, this configuration requires
the designer to externally route the op amp output
(OAxOUT) to another analog input pin (ANy). See
Table 30-53 in Section 30.0 “Electrical Characteris-
tics” for the typical value of RINT1. Table 30-60 and
Table 30-61 in Section 30.0 “Electrical Characteris-
tics” describe the minimum sample time (TSAMP)
requirements for the ADC module in this configuration.
Figure 25-7 also defines the equation to be used to
calculate the expected voltage at point VOAXOUT. This
is the typical inverting amplifier equation.
25.2 Op Amp/Comparator Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
25.2.1 KEY RESOURCES
•Section 26. “Op Amp/Comparator” (DS70357)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
FIGURE 25-7: OP AMP CONFIGURATION B
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
ADC(3)
OAxOUT
RFEEDBACK(2)
ANy
Note 1: See Table 30-53 for the Typical value.
2: See Table 30-53 for the Minimum value for the feedback resistor.
3: See Table 30-60 and Table 30-61 for the minimum sample time (T
SAMP).
4: CVREF1O or CVREF2O are two options that are available for supplying bias voltage to the op amps.
–
+
Op Ampx (VOAXOUT)
RINT1(1)
VOAxOUT
RFEEDBACK
R1
------------------------------
Bias Voltage V–IN
=
CxIN1-
CxIN1+
R1
VIN
Bias
Voltage(4)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 358 2011-2013 Microchip Technology Inc.
25.3 Op Amp/Comparator Registers
REGISTER 25-1: CMSTAT: OP AMP/COMPARATOR STATUS REGISTER
R/W-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
PSIDL — — —C4EVT
(1)C3EVT(1)C2EVT(1)C1EVT(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — —C4OUT
(2)C3OUT(2)C2OUT(2)C1OUT(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues operation of all comparators when device enters Idle mode
0 = Continues operation of all comparators in Idle mode
bit 14-12 Unimplemented: Read as ‘0’
bit 11 C4EVT: Op Amp/Comparator 4 Event Status bit(1)
1 = Op amp/comparator event occurred
0 = Op amp/comparator event did not occur
bit 10 C3EVT: Comparator 3 Event Status bit(1)
1 = Comparator event occurred
0 = Comparator event did not occur
bit 9 C2EVT: Comparator 2 Event Status bit(1)
1 = Comparator event occurred
0 = Comparator event did not occur
bit 8 C1EVT: Comparator 1 Event Status bit(1)
1 = Comparator event occurred
0 = Comparator event did not occur
bit 7-4 Unimplemented: Read as ‘0’
bit 3 C4OUT: Comparator 4 Output Status bit(2)
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 2 C3OUT: Comparator 3 Output Status bit(2)
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register,
CMxCON<9>.
2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON<8>.
2011-2013 Microchip Technology Inc. DS70657G-page 359
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 1 C2OUT: Comparator 2 Output Status bit(2)
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 0 C1OUT: Comparator 1 Output Status bit(2)
When CPOL = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
REGISTER 25-1: CMSTAT: OP AMP/COMPARATOR STATUS REGISTER (CONTINUED)
Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register,
CMxCON<9>.
2: Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON<8>.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 360 2011-2013 Microchip Technology Inc.
REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2 OR 3)
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
CON COE CPOL —— OPMODE CEVT COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
EVPOL<1:0> —CREF
(1)—— CCH<1:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CON: Op Amp/Comparator Enable bit
1 = Op amp/comparator is enabled
0 = Op amp/comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-11 Unimplemented: Read as ‘0’
bit 10 OPMODE: Op Amp/Comparator Operation Mode Select bit
1 = Circuit operates as an op amp
0 = Circuit operates as a comparator
bit 9 CEVT: Comparator Event bit
1 = Comparator event according to the EVPOL<1:0> settings occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8 COUT: Comparator Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1 (inverted polarity):
1 = VIN+ < VIN-
0 = VIN+ > VIN-
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2: This input is not available when OPMODE (CMxCON<10>) = 1.
2011-2013 Microchip Technology Inc. DS70657G-page 361
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity-selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output
00 = Trigger/event/interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to internal CVREFIN voltage(2)
0 = VIN+ input connects to CxIN1+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Op Amp/Comparator Channel Select bits(1)
11 = Unimplemented
10 = Unimplemented
01 = Inverting input of the comparator connects to the CxIN2- pin(2)
00 = Inverting input of the op amp/comparator connects to the CxIN1- pin
REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2 OR 3) (CONTINUED)
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2: This input is not available when OPMODE (CMxCON<10>) = 1.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 362 2011-2013 Microchip Technology Inc.
REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
CON COE CPOL — — —CEVTCOUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
EVPOL<1:0> —CREF
(1)—— CCH<1:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-10 Unimplemented: Read as ‘0’
bit 9 CEVT: Comparator Event bit
1 = Comparator event according to EVPOL<1:0> settings occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8 COUT: Comparator Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CPOL = 1 (inverted polarity):
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2011-2013 Microchip Technology Inc. DS70657G-page 363
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to internal CVREFIN voltage
0 = VIN+ input connects to C4IN1+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Channel Select bits(1)
11 = VIN- input of comparator connects to OA3/AN6
10 = VIN- input of comparator connects to OA2/AN0
01 = VIN- input of comparator connects to OA1/AN3
00 = VIN- input of comparator connects to C4IN1-
REGISTER 25-3: CM4CON: COMPARATOR 4 CONTROL REGISTER (CONTINUED)
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 364 2011-2013 Microchip Technology Inc.
REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT
CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0
— — — — SELSRCC<3:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SELSRCB<3:0> SELSRCA<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 SELSRCC<3:0>: Mask C Input Select bits
1111 = FLT4
1110 = FLT2
1101 = PTGO19
1100 = PTGO18
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
bit 7-4 SELSRCB<3:0>: Mask B Input Select bits
1111 = FLT4
1110 = FLT2
1101 = PTGO19
1100 = PTGO18
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
2011-2013 Microchip Technology Inc. DS70657G-page 365
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 3-0 SELSRCA<3:0>: Mask A Input Select bits
1111 = FLT4
1110 = FLT2
1101 = PTGO19
1100 = PTGO18
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
REGISTER 25-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT
CONTROL REGISTER (CONTINUED)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 366 2011-2013 Microchip Technology Inc.
REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING
CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 HLMS: High or Low-Level Masking Select bits
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 14 Unimplemented: Read as ‘0’
bit 13 OCEN: OR Gate C Input Enable bit
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
bit 12 OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
bit 11 OBEN: OR Gate B Input Enable bit
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
bit 10 OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
bit 9 OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
bit 8 OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
bit 7 NAGS: AND Gate Output Inverted Enable bit
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
bit 6 PAGS: AND Gate Output Enable bit
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
bit 5 ACEN: AND Gate C Input Enable bit
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
bit 4 ACNEN: AND Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate
2011-2013 Microchip Technology Inc. DS70657G-page 367
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 3 ABEN: AND Gate B Input Enable bit
1 = MBI is connected to AND gate
0 = MBI is not connected to AND gate
bit 2 ABNEN: AND Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to AND gate
0 = Inverted MBI is not connected to AND gate
bit 1 AAEN: AND Gate A Input Enable bit
1 = MAI is connected to AND gate
0 = MAI is not connected to AND gate
bit 0 AANEN: AND Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to AND gate
0 = Inverted MAI is not connected to AND gate
REGISTER 25-5: CMxMSKCON: COMPARATOR x MASK GATING
CONTROL REGISTER (CONTINUED)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 368 2011-2013 Microchip Technology Inc.
REGISTER 25-6: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 I-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CFSEL<2:0> CFLTREN CFDIV<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = T5CLK(1)
110 = T4CLK(2)
101 = T3CLK(1)
100 = T2CLK(2)
011 = Reserved
010 = SYNCO1(3)
001 = FOSC(4)
000 = FP(4)
bit 3 CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
Note 1: See the Type C Timer Block Diagram (Figure 13-2).
2: See the Type B Timer Block Diagram (Figure 13-1).
3: See the High-Speed PWMx Module Register Interconnection Diagram (Figure 16-2).
4: See the Oscillator System Diagram (Figure 9-1).
2011-2013 Microchip Technology Inc. DS70657G-page 369
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 25-7: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0
—CVR2OE
(1)— — — VREFSEL — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVR1OE(1)CVRR CVRSS CVR<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 CVR2OE: Comparator Voltage Reference 2 Output Enable bit(1)
1 = (AVDD – AVSS)/2 is connected to the CVREF2O pin
0 = (AVDD – AVSS)/2 is disconnected from the CVREF2O pin
bit 13-11 Unimplemented: Read as ‘0’
bit 10 VREFSEL: Comparator Voltage Reference Select bit
1 = CVREFIN = VREF+
0 = CVREFIN is generated by the resistor network
bit 9-8 Unimplemented: Read as ‘0’
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6 CVR1OE: Comparator Voltage Reference 1 Output Enable bit(1)
1 = Voltage level is output on the CVREF1O pin
0 = Voltage level is disconnected from then CVREF1O pin
bit 5 CVRR: Comparator Voltage Reference Range Selection bit
1 = CVRSRC/24 step-size
0 = CVRSRC/32 step-size
bit 4 CVRSS: Comparator Voltage Reference Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (AVSS)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0> Comparator Voltage Reference Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1:
CVREFIN = (CVR<3:0>/24) (CVRSRC)
When CVRR = 0:
CVREFIN = (CVRSRC/4) + (CVR<3:0>/32) (CVRSRC)
Note 1: CVRxOE overrides the TRISx and the ANSELx bit settings.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 370 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 371
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
26.0 PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
The programmable CRC generator offers the following
features:
• User-programmable (up to 32nd order)
polynomial CRC equation
• Interrupt output
• Data FIFO
The programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
up to 32 bits
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable interrupt output
• Data FIFO
A simplified block diagram of the CRC generator is
shown in Figure 26-1. A simple version of the CRC shift
engine is shown in Figure 26-2.
FIGURE 26-1: CRC BLOCK DIAGRAM
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “Program-
mable Cyclic Redundancy Check
(CRC)” (DS70346) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Variable FIFO
(4x32, 8x16 or 16x8)
CRCDATH CRCDATL
Shift Buffer
CRC Shift Engine
CRCWDATH CRCWDATL
LENDIAN
10
CRCISEL
1
0
FIFO Empty Event
Shift Complete Event
Set CRCIF
2 * FP Shift Clock
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 372 2011-2013 Microchip Technology Inc.
FIGURE 26-2: CRC SHIFT ENGINE DETAIL
26.1 Overview
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN<4:0> bits
(CRCCON2<4:0>).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the
equation; functionally, this includes an XOR operation
on the corresponding bit in the CRC engine. Clearing
the bit disables the XOR.
For example, consider two CRC polynomials, one a
16-bit equation and the other a 32-bit equation:
To program these polynomials into the CRC generator,
set the register bits as shown in Table 26-1.
Note that the appropriate positions are set to ‘1’ to
indicate that they are used in the equation (for example,
X26 and X23). The 0 bit required by the equation is
always XORed; thus, X0 is a don’t care. For a poly-
nomial of length N, it is assumed that the Nth bit will
always be used, regardless of the bit setting. Therefore,
for a polynomial length of 32, there is no 32nd bit in the
CRCxOR register.
TABLE 26-1: CRC SETUP EXAMPLES FOR
16 AND 32-BIT POLYNOMIAL
26.2 Programmable CRC Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
26.2.1 KEY RESOURCES
•Section 27. “Programmable Cyclic Redundancy
Check (CRC)” (DS70346)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33E/PIC24E Family Reference
Manual” Sections
• Development Tools
CRCWDATH CRCWDATL
Bit 0 Bit 1 Bit n(2)
X(1)(1)
Read/Write Bus
Shift Buffer
Data Bit 2
X(2)(1) X(n)(1)
Note 1: Each XOR stage of the shift engine is programmable. See text for details.
2: Polynomial length n is determined by ([PLEN<4:0>] + 1).
x16 + x12 + x5 + 1
and
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7
+ x5 + x4 + x2 + x + 1
CRC Control
Bits
Bit Values
16-bit
Polynomial
32-bit
Polynomial
PLEN<4:0> 01111 11111
X<31:16> 0000 0000
0000 000x
0000 0100
1100 0001
X<15:0> 0001 0000
0010 000x
0001 1101
1011 011x
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464
2011-2013 Microchip Technology Inc. DS70657G-page 373
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
26.3 Programmable CRC Registers
REGISTER 26-1: CRCCON1: CRC CONTROL REGISTER 1
R/W-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0
CRCEN — CSIDL VWORD<4:0>
bit 15 bit 8
R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CRCEN: CRC Enable bit
1 = CRC module is enabled
0 = CRC module is disabled; all state machines, pointers and CRCWDAT/CRCDAT are reset, other
SFRs are not reset
bit 14 Unimplemented: Read as ‘0’
bit 13 CSIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8 VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0> > 7
or 16 when PLEN<4:0> 7.
bit 7 CRCFUL: FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6 CRCMPT: FIFO Empty Bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5 CRCISEL: CRC Interrupt Selection bit
1 = Interrupt on FIFO is empty; final word of data is still shifting through CRC
0 = Interrupt on shift is complete and CRCWDAT results are ready
bit 4 CRCGO: Start CRC bit
1 = Starts CRC serial shifter
0 = CRC serial shifter is turned off
bit 3 LENDIAN: Data Word Little-Endian Configuration bit
1 = Data word is shifted into the CRC starting with the LSb (little endian)
0 = Data word is shifted into the CRC starting with the MSb (big endian)
bit 2-0 Unimplemented: Read as ‘0’
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 374 2011-2013 Microchip Technology Inc.
REGISTER 26-2: CRCCON2: CRC CONTROL REGISTER 2
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DWIDTH<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — PLEN<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 DWIDTH<4:0>: Data Width Select bits
These bits set the width of the data word (DWIDTH<4:0> + 1).
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 PLEN<4:0>: Polynomial Length Select bits
These bits set the length of the polynomial (Polynomial Length = PLEN<4:0> + 1).
2011-2013 Microchip Technology Inc. DS70657G-page 375
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 26-3: CRCXORH: CRC XOR POLYNOMIAL HIGH REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
X<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
X<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 X<31:16>: XOR of Polynomial Term Xn Enable bits
REGISTER 26-4: CRCXORL: CRC XOR POLYNOMIAL LOW REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
X<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
X<7:1> —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits
bit 0 Unimplemented: Read as ‘0’
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 376 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 377
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
27.0 SPECIAL FEATURES
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
27.1 Configuration Bits
In dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices, the
Configuration bytes are implemented as volatile mem-
ory. This means that configuration data must be
programmed each time the device is powered up.
Configuration data is stored in at the top of the on-chip
program memory space, known as the Flash Configura-
tion bytes. Their specific locations are shown in
Table 27-1. The configuration data is automatically
loaded from the Flash Configuration bytes to the proper
Configuration Shadow registers during device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration bytes for configuration data in their
code for the compiler. This is to make certain that pro-
gram code is not stored in this address when the code
is compiled.
The upper 2 bytes of all Flash Configuration Words in
program memory should always be ‘1111 1111 1111
1111’. This makes them appear to be NOP instructions
in the remote event that their locations are ever
executed by accident. Since Configuration bits are not
implemented in the corresponding locations, writing
‘1’s to these locations has no effect on device
operation.
The Configuration Flash bytes map is shown in
Table 27-1.
Note: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
Note: Configuration data is reloaded on all types
of device Resets.
Note: Performing a page erase operation on the
last page of program memory clears the
Flash Configuration bytes, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 378 2011-2013 Microchip Technology Inc.
TABLE 27-1: CONFIGURATION BYTE REGISTER MAP
File
Name Address
Device
Memory
Size
(Kbytes)
Bits 23-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved 0057EC 32
— — — — — — — — —
00AFEC 64
0157EC 128
02AFEC 256
0557EC 512
Reserved 0057EE 32
— — — — — — — — —
00AFEE 64
0157EE 128
02AFEE 256
0557EE 512
FICD 0057F0 32
— Reserved(3)— JTAGEN Reserved(2)Reserved(3)—ICS<1:0>
00AFF0 64
0157F0 128
02AFF0 256
0557F0 512
FPOR 0057F2 32
— WDTWIN<1:0> ALTI2C2 ALTI2C1 Reserved(3)— — —
00AFF2 64
0157F2 128
02AFF2 256
0557F2 512
FWDT 0057F4 32
— FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
00AFF4 64
0157F4 128
02AFF4 256
0557F4 512
FOSC 0057F6 32
— FCKSM<1:0> IOL1WAY —— OSCIOFNC POSCMD<1:0>
00AFF6 64
0157F6 128
02AFF6 256
0557F6 512
FOSC-
SEL
0057F8 32
— IESO PWMLOCK(1)— — —FNOSC<2:0>
00AFF8 64
0157F8 128
02AFF8 256
0557F8 512
FGS 0057FA 32
— — — — — — — GCP GWRP
00AFFA 64
0157FA 128
02AFFA 256
0557FA 512
Reserved 0057FC 32
— — — — — — — — —
00AFFC 64
0157FC 128
02AFFC 256
0557FC 512
Reserved 057FFE 32
— — — — — — — — —
00AFFE 64
0157FE 128
02AFFE 256
0557FE 512
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2: This bit is reserved and must be programmed as ‘0’.
3: These bits are reserved and must be programmed as ‘1’.
2011-2013 Microchip Technology Inc. DS70657G-page 379
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 27-2: CONFIGURATION BITS DESCRIPTION
Bit Field Description
GCP General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = Code protection is enabled for the entire program memory space
GWRP General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO Two-Speed Oscillator Start-up Enable bit
1 = Start up device with FRC, then automatically switch to the user-selected oscillator
source when ready
0 = Start up device with user-selected oscillator source
PWMLOCK(1)PWM Lock Enable bit
1 = Certain PWM registers may only be written after a key sequence
0 = PWM registers may be written without a key sequence
FNOSC<2:0> Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Reserved; do not use
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved; do not use
011 = Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
FCKSM<1:0> Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSCIOFNC OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is a general purpose digital I/O pin
POSCMD<1:0> Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
FWDTEN Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled. Clearing the
SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing
the SWDTEN bit in the RCON register)
WINDIS Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
PLLKEN PLL Lock Enable bit
1 = PLL lock is enabled
0 = PLL lock is disabled
WDTPRE Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 380 2011-2013 Microchip Technology Inc.
WDTPOST<3:0> Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
WDTWIN<1:0> Watchdog Window Select bits
11 = WDT window is 25% of WDT period
10 = WDT window is 37.5% of WDT period
01 = WDT window is 50% of WDT period
00 = WDT window is 75% of WDT period
ALTI2C1 Alternate I2C1 pin
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
ALTI2C2 Alternate I2C2 pin
1 = I2C2 is mapped to the SDA2/SCL2 pins
0 = I2C2 is mapped to the ASDA2/ASCL2 pins
JTAGEN JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS<1:0> ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
TABLE 27-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Description
Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2011-2013 Microchip Technology Inc. DS70657G-page 381
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 27-1: DEVID: DEVICE ID REGISTER
RRRRRRRR
DEVID<23:16>(1)
bit 23 bit 16
RRRRRRRR
DEVID<15:8>(1)
bit 15 bit 8
RRRRRRRR
DEVID<7:0>(1)
bit 7 bit 0
Legend: R = Read-Only bit U = Unimplemented bit
bit 23-0 DEVID<23:0>: Device Identifier bits(1)
Note 1: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for the list of device ID values.
REGISTER 27-2: DEVREV: DEVICE REVISION REGISTER
RRRRRRRR
DEVREV<23:16>(1)
bit 23 bit 16
RRRRRRRR
DEVREV<15:8>(1)
bit 15 bit 8
RRRRRRRR
DEVREV<7:0>(1)
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-0 DEVREV<23:0>: Device Revision bits(1)
Note 1: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for the list of device revision values.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 382 2011-2013 Microchip Technology Inc.
27.2 User ID Words
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices contain four
User ID Words, located at addresses, 0x800FF8
through 0x800FFE. The User ID Words can be used for
storing product information such as serial numbers,
system manufacturing dates, manufacturing lot
numbers and other application-specific information.
The User ID Words register map is shown in
Table 27-3.
TABLE 27-3: USER ID WORDS REGISTER
MAP
27.3 On-Chip Voltage Regulator
All the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X devices power their core digital logic at a
nominal 1.8V. This can create a conflict for designs that
are required to operate at a higher typical voltage, such
as 3.3V. To simplify system design, all devices in the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X family incorporate an on-
chip regulator that allows the device to run its core logic
from VDD.
The regulator provides power to the core from the other
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such
as tantalum or ceramic) must be connected to the VCAP
pin (Figure 27-1). This helps to maintain the stability of
the regulator. The recommended value for the filter
capacitor is provided in Table 30-5 located in
Section 30.0 “Electrical Characteristics”.
FIGURE 27-1: CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
27.4 Brown-out Reset (BOR)
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage, VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT Time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM is applied. The total delay in this case is
TFSCM. Refer to Parameter SY35 in Table 30-22 of
Section 30.0 “Electrical Characteristics” for specific
TFSCM values.
The BOR status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
File Name Address Bits 23-16 Bits 15-0
FUID0 0x800FF8 —UID0
FUID1 0x800FFA —UID1
FUID2 0x800FFC —UID2
FUID3 0x800FFE —UID3
Legend: — = unimplemented, read as ‘1’.
Note: It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
Note 1: These are typical operating voltages.
Refer to Table 30-5 located in
Section 30.1 “DC Characteristics” for
the full operating ranges of VDD and VCAP.
2: It is important for the low-ESR capacitor
to be placed as close as possible to the
VCAP pin.
3: Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.
VDD
VCAP
VSS
dsPIC33E/PIC24E
3.3V
CEFC
2011-2013 Microchip Technology Inc. DS70657G-page 383
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
27.5 Watchdog Timer (WDT)
For dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
27.5.1 PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a WDT Time-
out period (TWDT), as shown in Parameter SY12 in
Table 30-22.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
•By a CLRWDT instruction during normal execution
27.5.2 SLEEP AND IDLE MODES
If the WDT is enabled, it continues to run during Sleep or
Idle modes. When the WDT time-out occurs, the device
wakes the device and code execution continues from
where the PWRSAV instruction was executed. The corre-
sponding SLEEP or IDLE bit (RCON<3,2>) needs to be
cleared in software after the device wakes up.
27.5.3 ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software
when the FWDTEN Configuration bit has been
programmed to ‘0’. The WDT is enabled in software
by setting the SWDTEN control bit (RCON<5>). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user application
to enable the WDT for critical code segments and
disable the WDT during non-critical segments for
maximum power savings.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
27.5.4 WDT WINDOW
The Watchdog Timer has an optional Windowed mode,
enabled by programming the WINDIS bit in the WDT
Configuration register (FWDT<6>). In the Windowed
mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Window select bits (WDTWIN<1:0>).
FIGURE 27-2: WDT BLOCK DIAGRAM
Note: The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
0
1
WDTPRE WDTPOST<3:0>
Watchdog Timer
Prescaler
(Divide-by-N1)
Postscaler
(Divide-by-N2)
Sleep/Idle
WDT
WDT Window Select
WINDIS
WDT
CLRWDT Instruction
SWDTEN
FWDTEN
LPRC Clock
RS RS
Wake-up
Reset
WDTWIN<1:0>
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 384 2011-2013 Microchip Technology Inc.
27.6 JTAG Interface
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices implement a
JTAG interface, which supports boundary scan device
testing. Detailed information on this interface is
provided in future revisions of the document.
27.7 In-Circuit Serial Programming
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices can be
serially programmed while in the end application circuit.
This is done with two lines for clock and data, and three
other lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the device just before shipping the
product. Serial programming also allows the most recent
firmware or a custom firmware to be programmed. Refer
to the “dsPIC33E/PIC24E Flash Programming
Specification for Devices with Volatile Configuration Bits”
(DS70663) for details about In-Circuit Serial
Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
27.8 In-Circuit Debugger
When MPLAB® ICD 3 or REAL ICE™ is selected as a
debugger, the in-circuit debugging functionality is
enabled. This function allows simple debugging func-
tions when used with MPLAB IDE. Debugging function-
ality is controlled through the PGECx (Emulation/
Debug Clock) and PGEDx (Emulation/Debug Data) pin
functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).
27.9 Code Protection and
CodeGuard™ Security
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X devices offer basic
implementation of CodeGuard Security that supports
only General Segment (GS) security. This feature helps
protect individual Intellectual Property.
Note: Refer to Section 24. “Programming and
Diagnostics” (DS70608) of the
“dsPIC33E/PIC24E Family Reference
Manual” for further information on usage,
configuration and operation of the JTAG
interface.
Note: Refer to Section 23. “CodeGuard™
Security” (DS70634) of the “dsPIC33E/
PIC24E Family Reference Manual” for
further information on usage, configuration
and operation of CodeGuard Security.
2011-2013 Microchip Technology Inc. DS70657G-page 385
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
28.0 INSTRUCTION SET SUMMARY
The dsPIC33EP instruction set is almost identical to
that of the dsPIC30F and dsPIC33F. The PIC24EP
instruction set is almost identical to that of the PIC24F
and PIC24H.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• DSP operations
• Control operations
Table 28-1 lists the general symbols used in describing
the instructions.
The dsPIC33E instruction set summary in Tab l e 2 8- 2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
Note: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 386 2011-2013 Microchip Technology Inc.
Most instructions are a single word. Certain double-word
instructions are designed to provide all the required
information in these 48 bits. In the second word, the
8MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it executes as a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the instruction,
or a PSV or table read is performed, or an SFR register is
read. In these cases, the execution takes multiple
instruction cycles with the additional instruction cycle(s)
executed as a NOP. Certain instructions that involve
skipping over the subsequent instruction require either
two or three cycles if the skip is performed, depending on
whether the instruction being skipped is a single-word or
two-word instruction. Moreover, double-word moves
require two cycles.
Note: For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s Reference Manual”
(DS70157).
For more information on instructions that
take more than one instruction cycle to
execute, refer to Section 2. “CPU” of
the “dsPIC33E/PIC24E Family Refer-
ence Manual” (DS70359), particularly
Section 2.8, “Instruction Flow Types”.
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field Description
#text Means literal defined by “text”
(text) Means “content of text”
[text] Means “the location addressed by text”
{ } Optional field or operation
a {b, c, d} a is selected from the set of values b, c, d
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator write back destination address register {W13, [W13]+ = 2}
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit5 5-bit unsigned literal {0...31}
lit8 8-bit unsigned literal {0...255}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14 14-bit unsigned literal {0...16384}
lit16 16-bit unsigned literal {0...65535}
lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None Field does not require an entry, can be blank
OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Slit16 16-bit signed literal {-32768...32767}
Slit6 6-bit signed literal {-16...16}
Wb Base W register {W0...W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
2011-2013 Microchip Technology Inc. DS70657G-page 387
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Wm,Wn Dividend, Divisor working register pair (direct addressing)
Wm*Wm Multiplicand and Multiplier working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn One of 16 working registers {W0...W15}
Wnd One of 16 destination working registers {W0...W15}
Wns One of 16 source working registers {W0...W15}
WREG W0 (working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X Data Space Prefetch Address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy Y Data Space Prefetch Address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 388 2011-2013 Microchip Technology Inc.
TABLE 28-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
1ADD ADD Acc(1)Add Accumulators 1 1 OA,OB,SA,SB
ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6BRA BRA C,Expr Branch if Carry 1 1 (4) None
BRA GE,Expr Branch if greater than or equal 1 1 (4) None
BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (4) None
BRA GT,Expr Branch if greater than 1 1 (4) None
BRA GTU,Expr Branch if unsigned greater than 1 1 (4) None
BRA LE,Expr Branch if less than or equal 1 1 (4) None
BRA LEU,Expr Branch if unsigned less than or equal 1 1 (4) None
BRA LT,Expr Branch if less than 1 1 (4) None
BRA LTU,Expr Branch if unsigned less than 1 1 (4) None
BRA N,Expr Branch if Negative 1 1 (4) None
BRA NC,Expr Branch if Not Carry 1 1 (4) None
BRA NN,Expr Branch if Not Negative 1 1 (4) None
BRA NOV,Expr Branch if Not Overflow 1 1 (4) None
BRA NZ,Expr Branch if Not Zero 1 1 (4) None
BRA OA,Expr(1)Branch if Accumulator A overflow 1 1 (4) None
BRA OB,Expr(1)Branch if Accumulator B overflow 1 1 (4) None
BRA OV,Expr(1)Branch if Overflow 1 1 (4) None
BRA SA,Expr(1)Branch if Accumulator A saturated 1 1 (4) None
BRA SB,Expr(1)Branch if Accumulator B saturated 1 1 (4) None
BRA Expr Branch Unconditionally 1 4 None
BRA Z,Expr Branch if Zero 1 1 (4) None
BRA Wn Computed Branch 1 4 None
7BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
8BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None
BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 389
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
9BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1
(2 or 3)
None
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1
(2 or 3)
None
11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1
(2 or 3)
None
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1
(2 or 3)
None
12 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
14 CALL CALL lit23 Call subroutine 2 4 SFA
CALL Wn Call indirect subroutine 1 4 SFA
CALL.L Wn Call indirect subroutine (long address) 1 4 SFA
15 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB(1)Clear Accumulator 1 1 OA,OB,SA,SB
16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
17 COM COM f f = f 11 N,Z
COM f,WREG WREG = f 11 N,Z
COM Ws,Wd Wd = Ws 11 N,Z
18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit8 Compare Wb with lit8 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit8 Compare Wb with lit8, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1 1 C,DC,N,OV,Z
21 CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, skip if = 1 1
(2 or 3)
None
CPBEQ CPBEQ Wb,Wn,Expr Compare Wb with Wn, branch if = 1 1 (5) None
22 CPSGT CPSGT Wb,Wn Compare Wb with Wn, skip if > 1 1
(2 or 3)
None
CPBGT CPBGT Wb,Wn,Expr Compare Wb with Wn, branch if > 1 1 (5) None
23 CPSLT CPSLT Wb,Wn Compare Wb with Wn, skip if < 1 1
(2 or 3)
None
CPBLT CPBLT Wb,Wn,Expr Compare Wb with Wn, branch if < 1 1 (5) None
24 CPSNE CPSNE Wb,Wn Compare Wb with Wn, skip if 11
(2 or 3)
None
CPBNE CPBNE Wb,Wn,Expr Compare Wb with Wn, branch if 11 (5) None
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 390 2011-2013 Microchip Technology Inc.
25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C
26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None
29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV
30 DIVF DIVF Wm,Wn(1)Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
31 DO DO #lit15,Expr(1)Do code to PC + Expr, lit15 + 1 times 2 2 None
DO Wn,Expr(1)Do code to PC + Expr, (Wn) + 1 times 2 2 None
32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd(1)Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd(1)Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
38 GOTO GOTO Expr Go to address 2 4 None
GOTO Wn Go to indirect 1 4 None
GOTO.L Wn Go to indirect (long address) 1 4 None
39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
41 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
43 LNK LNK #lit14 Link Frame Pointer 1 1 SFA
44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB(1)Multiply and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1)Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 391
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
46 MOV MOV f,Wn Move f to Wn 1 1 None
MOV f Move f to f 1 1 None
MOV f,WREG Move f to WREG 1 1 None
MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 None
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
47 MOVPAG MOVPAG #lit10,DSRPAG Move 10-bit literal to DSRPAG 1 1 None
MOVPAG #lit9,DSWPAG Move 9-bit literal to DSWPAG 1 1 None
MOVPAG #lit8,TBLPAG Move 8-bit literal to TBLPAG 1 1 None
MOVPAG Ws, DSRPAG Move Ws<9:0> to DSRPAG 1 1 None
MOVPAG Ws, DSWPAG Move Ws<8:0> to DSWPAG 1 1 None
MOVPAG Ws, TBLPAG Move Ws<7:0> to TBLPAG 1 1 None
48 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB(1)Prefetch and store accumulator 1 1 None
49 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1)Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(1)Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
50 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(1)-(Multiply Wm by Wn) to Accumulator 1 1 None
51 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB(1)Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
52 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) *
signed(Ws)
11 None
MUL.SS Wb,Ws,Acc(1)Accumulator = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) *
unsigned(Ws)
11 None
MUL.SU Wb,Ws,Acc(1)Accumulator = signed(Wb) *
unsigned(Ws)
11 None
MUL.SU Wb,#lit5,Acc(1)Accumulator = signed(Wb) * unsigned(lit5) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *
signed(Ws)
11 None
MUL.US Wb,Ws,Acc(1)Accumulator = unsigned(Wb) *
signed(Ws)
11 None
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
11 None
MUL.UU Wb,#lit5,Acc(1)Accumulator = unsigned(Wb) *
unsigned(lit5)
11 None
MUL.UU Wb,Ws,Acc(1)Accumulator = unsigned(Wb) *
unsigned(Ws)
11 None
MULW.SS Wb,Ws,Wnd Wnd = signed(Wb) * signed(Ws) 1 1 None
MULW.SU Wb,Ws,Wnd Wnd = signed(Wb) * unsigned(Ws) 1 1 None
MULW.US Wb,Ws,Wnd Wnd = unsigned(Wb) * signed(Ws) 1 1 None
MULW.UU Wb,Ws,Wnd Wnd = unsigned(Wb) * unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) *
unsigned(lit5)
11 None
MUL.SU Wb,#lit5,Wnd Wnd = signed(Wb) * unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
11 None
MUL.UU Wb,#lit5,Wnd Wnd = unsigned(Wb) * unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 392 2011-2013 Microchip Technology Inc.
53 NEG NEG Acc(1)Negate Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
NEG f f = f + 1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
54 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
55 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
12 None
POP.S Pop Shadow Registers 1 1 All
56 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
12 None
PUSH.S Push Shadow Registers 1 1 None
57 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
58 RCALL RCALL Expr Relative Call 1 4 SFA
RCALL Wn Computed Call 1 4 SFA
59 REPEAT REPEAT #lit15 Repeat Next Instruction lit15 + 1 times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None
60 RESET RESET Software device Reset 1 1 None
61 RETFIE RETFIE Return from interrupt 1 6 (5) SFA
62 RETLW RETLW #lit10,Wn Return with literal in Wn 1 6 (5) SFA
63 RETURN RETURN Return from Subroutine 1 6 (5) SFA
64 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
65 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
66 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
67 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
68 SAC SAC Acc,#Slit4,Wdo(1)Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo(1)Store Rounded Accumulator 1 1 None
69 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z
70 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
71 SFTAC SFTAC Acc,Wn(1)Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6(1)Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2011-2013 Microchip Technology Inc. DS70657G-page 393
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
72 SL SL f f = Left Shift f 1 1 C,N,OV,Z
SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
73 SUB SUB Acc(1)Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
74 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
75 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
76 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z
77 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None
SWAP Wn Wn = byte swap Wn 1 1 None
78 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 5 None
79 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 5 None
80 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
81 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
82 ULNK ULNK Unlink Frame Pointer 1 1 SFA
83 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
84 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic Assembly Syntax Description # of
Words
# of
Cycles
Status Flags
Affected
Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 394 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 395
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
29.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
29.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 396 2011-2013 Microchip Technology Inc.
29.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
29.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
29.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
29.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
29.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
2011-2013 Microchip Technology Inc. DS70657G-page 397
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
29.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
29.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
29.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip’s most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer’s PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
29.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer’s PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 398 2011-2013 Microchip Technology Inc.
29.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
29.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
29.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2011-2013 Microchip Technology Inc. DS70657G-page 399
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X electrical characteristics. Additional information will be provided in future revisions of this document as it
becomes available.
Absolute maximum ratings for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
Functional operation of the device at these or any other conditions above the parameters indicated in the operation
listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS(3) ................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) .................................................. -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3) .................................................. -0.3V to +3.6V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................300 mA
Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin..................................................................................................25 mA
Maximum current sunk by all ports(2,4).................................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Tab l e 3 0- 2 ).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
4: Exceptions are: dsPIC33EPXXXGP502, dsPIC33EPXXXMC202/502 and PIC24EPXXXGP/MC202 devices,
which have a maximum sink/source capability of 130 mA.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 400 2011-2013 Microchip Technology Inc.
30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS VS. VOLTAGE
Characteristic VDD Range
(in Volts)
Temp Range
(in °C)
Maximum MIPS
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
— 3.0V to 3.6V(1)-40°C to +85°C 70
— 3.0V to 3.6V(1)-40°C to +125°C 60
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, op amp/comparator and
comparator voltage reference) may have degraded performance. Device functionality is tested but not
characterized. Refer to Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
TABLE 30-2: THERMAL OPERATING CONDITIONS
Rating Symbol Min. Typ. Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ-40 — +125 °C
Operating Ambient Temperature Range TA-40 — +85 °C
Extended Temperature Devices
Operating Junction Temperature Range TJ-40 — +140 °C
Operating Ambient Temperature Range TA-40 — +125 °C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD – IOH) PDPINT + PI/OW
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ. Max. Unit Notes
Package Thermal Resistance, 64-Pin QFN JA 28.0 — °C/W 1
Package Thermal Resistance, 64-Pin TQFP 10x10 mm JA 48.3 — °C/W 1
Package Thermal Resistance, 44-Pin QFN JA 29.0 — °C/W 1
Package Thermal Resistance, 44-Pin TQFP 10x10 mm JA 49.8 — °C/W 1
Package Thermal Resistance, 44-Pin VTLA 6x6 mm JA 25.2 — °C/W 1
Package Thermal Resistance, 36-Pin VTLA 5x5 mm JA 28.5 — °C/W 1
Package Thermal Resistance, 28-Pin QFN-S JA 30.0 — °C/W 1
Package Thermal Resistance, 28-Pin SSOP JA 71.0 — °C/W 1
Package Thermal Resistance, 28-Pin SOIC JA 69.7 — °C/W 1
Package Thermal Resistance, 28-Pin SPDIP JA 60.0 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
2011-2013 Microchip Technology Inc. DS70657G-page 401
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS
TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions (see Note 1): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Operating Voltage
DC10 VDD Supply Voltage 3.0 — 3.6 V
DC16 VPOR VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
——VSS V
DC17 SVDD VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.03 — — V/ms 0V-1V in 100 ms
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, op amp/comparator and
comparator voltage reference) may have degraded performance. Device functionality is tested but not
characterized. Refer to parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
Standard Operating Conditions (unless otherwise stated):
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristics Min. Typ. Max. Units Comments
CEFC External Filter Capacitor
Value(1)
4.7 10 — F Capacitor must have a low
series resistance (< 1 ohm)
Note 1: Typical VCAP voltage = 1.8 volts when VDD VDDMIN.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 402 2011-2013 Microchip Technology Inc.
TABLE 30-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typ. Max. Units Conditions
Operating Current (IDD)(1)
DC20d 9 15 mA -40°C
3.3V 10 MIPS
DC20a 9 15 mA +25°C
DC20b 9 15 mA +85°C
DC20c 9 15 mA +125°C
DC22d 16 25 mA -40°C
3.3V 20 MIPS
DC22a 16 25 mA +25°C
DC22b 16 25 mA +85°C
DC22c 16 25 mA +125°C
DC24d 27 35 mA -40°C
3.3V 40 MIPS
DC24a 27 35 mA +25°C
DC24b 27 35 mA +85°C
DC24c 27 35 mA +125°C
DC25d 36 55 mA -40°C
3.3V 60 MIPS
DC25a 36 55 mA +25°C
DC25b 36 55 mA +85°C
DC25c 36 55 mA +125°C
DC26d 41 60 mA -40°C
3.3V 70 MIPSDC26a 41 60 mA +25°C
DC26b 41 60 mA +85°C
Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
zeroed)
• CPU is executing while(1) statement
• JTAG is disabled
2011-2013 Microchip Technology Inc. DS70657G-page 403
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
No. Typ. Max. Units Conditions
Idle Current (IIDLE)(1)
DC40d 3 8 mA -40°C
3.3V 10 MIPS
DC40a 3 8 mA +25°C
DC40b 3 8 mA +85°C
DC40c 3 8 mA +125°C
DC42d 6 12 mA -40°C
3.3V 20 MIPS
DC42a 6 12 mA +25°C
DC42b 6 12 mA +85°C
DC42c 6 12 mA +125°C
DC44d 11 18 mA -40°C
3.3V 40 MIPS
DC44a 11 18 mA +25°C
18DC44b 11 mA +85°C
18DC44c 11 mA +125°C
DC45d 17 27 mA -40°C
3.3V 60 MIPS
DC45a 17 27 mA +25°C
27DC45b 17 mA +85°C
27DC45c 17 mA +125°C
DC46d 20 35 mA -40°C
3.3V 70 MIPSDC46a 20 35 mA +25°C
35DC46b 20 mA +85°C
Note 1: Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
zeroed)
• The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to standby while the device is in
Idle mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep
mode)
• JTAG is disabled
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 404 2011-2013 Microchip Technology Inc.
TABLE 30-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Parameter
No. Typ. Max. Units Conditions
Power-Down Current (IPD)(1) – dsPIC33EP32GP50X, dsPIC33EP32MC20X/50X and PIC24EP32GP/MC20X
DC60d 30 100 A -40°C
3.3V
DC60a 35 100 A+25°C
DC60b 150 200 A+85°C
DC60c 250 500 A +125°C
Power-Down Current (IPD)(1) – dsPIC33EP64GP50X, dsPIC33EP64MC20X/50X and PIC24EP64GP/MC20X
DC60d 25 100 A -40°C
3.3V
DC60a 30 100 A+25°C
DC60b 150 350 A+85°C
DC60c 350 800 A +125°C
Power-Down Current (IPD)(1) – dsPIC33EP128GP50X, dsPIC33EP128MC20X/50X and PIC24EP128GP/MC20X
DC60d 30 100 A -40°C
3.3V
DC60a 35 100 A+25°C
DC60b 150 350 A+85°C
DC60c 550 1000 A +125°C
Power-Down Current (IPD)(1) – dsPIC33EP256GP50X, dsPIC33EP256MC20X/50X and PIC24EP256GP/MC20X
DC60d 35 100 A -40°C
3.3V
DC60a 40 100 A+25°C
DC60b 250 450 A+85°C
DC60c 1000 1200 A +125°C
Power-Down Current (IPD)(1) – dsPIC33EP512GP50X, dsPIC33EP512MC20X/50X and PIC24EP512GP/MC20X
DC60d 40 — A -40°C
3.3V
DC60a 45 — A+25°C
DC60b 350 — A+85°C
DC60c 1500 — A +125°C
Note 1: IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (PMDx bits are all set)
• The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to standby while the device is in Sleep
mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep
mode)
• JTAG is disabled
2011-2013 Microchip Technology Inc. DS70657G-page 405
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-9: DC CHARACTERISTICS: WATCHDOG TIMER DELTA CURRENT (IWDT)(1)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Parameter No. Typ. Max. Units Conditions
DC61d 8 — A-40°C
3.3V
DC61a 10 — A +25°C
DC61b 12 — A +85°C
DC61c 13 — A +125°C
Note 1: The IWDT current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. All parameters are characterized but not tested during manufacturing.
TABLE 30-10: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Parameter No. Typ. Max. Doze
Ratio Units Conditions
Doze Current (IDOZE)(1)
DC73a(2)35 — 1:2 mA -40°C 3.3V FOSC = 140 MHz
DC73g 20 30 1:128 mA
DC70a(2)35 — 1:2 mA +25°C 3.3V FOSC = 140 MHz
DC70g 20 30 1:128 mA
DC71a(2)35 — 1:2 mA +85°C 3.3V FOSC = 140 MHz
DC71g 20 30 1:128 mA
DC72a(2)28 — 1:2 mA +125°C 3.3V FOSC = 120 MHz
DC72g 15 30 1:128 mA
Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
•MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are
zeroed)
• CPU is executing while(1) statement
• JTAG is disabled
2: Parameter is characterized but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 406 2011-2013 Microchip Technology Inc.
TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
VIL Input Low Voltage
DI10 Any I/O Pin and MCLR VSS —0.2VDD V
DI18 I/O Pins with SDAx, SCLx VSS —0.3 VDD V SMBus disabled
DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled
VIH Input High Voltage
DI20 I/O Pins Not 5V Tolerant 0.8 VDD —VDD V(Note 3)
I/O Pins 5V Tolerant and
MCLR
0.8 VDD —5.5V(Note 3)
I/O Pins with SDAx, SCLx 0.8 VDD — 5.5 V SMBus disabled
I/O Pins with SDAx, SCLx 2.1 — 5.5 V SMBus enabled
ICNPU Change Notification
Pull-up Current
DI30 150 250 550 AV
DD = 3.3V, VPIN = VSS
ICNPD Change Notification
Pull-Down Current(4)
DI31 20 50 100 AVDD = 3.3V, VPIN = VDD
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
2: Negative current is defined as current sourced by the pin.
3: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
4: VIL source < (VSS – 0.3). Characterized but not tested.
5: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
6: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
7: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2011-2013 Microchip Technology Inc. DS70657G-page 407
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
IIL Input Leakage Current(1,2)
DI50 I/O Pins 5V Tolerant(3)-1 — +1 AVSS VPIN VDD,
Pin at high-impedance
DI51 I/O Pins Not 5V Tolerant(3)-1 — +1 AVSS VPIN VDD,
Pin at high-impedance,
-40°C T
A +85°C
DI51a I/O Pins Not 5V Tolerant(3)-1 — +1 A Analog pins shared with
external reference pins,
-40°C T
A +85°C
DI51b I/O Pins Not 5V Tolerant(3)-1 — +1 AVSS VPIN VDD,
Pin at high-impedance,
-40°C T
A +125°C
DI51c I/O Pins Not 5V Tolerant(3)-1 — +1 A Analog pins shared with
external reference pins,
-40°C T
A +125°C
DI55 MCLR -5 — +5 AVSS VPIN VDD
DI56 OSC1 -5 — +5 AVSS VPIN VDD,
XT and HS modes
TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
2: Negative current is defined as current sourced by the pin.
3: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
4: VIL source < (VSS – 0.3). Characterized but not tested.
5: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
6: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
7: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 408 2011-2013 Microchip Technology Inc.
IICL Input Low Injection Current
DI60a 0 — -5(4,7)mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
IICH Input High Injection Current
DI60b 0 — +5(5,6,7)mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(6)
IICT Total Input Injection Current
DI60c (sum of all I/O and control
pins)
-20(8)—+20
(8)mA Absolute instantaneous sum
of all ± input injection cur-
rents from all I/O pins
(| I
ICL + | IICH |) IICT
TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
2: Negative current is defined as current sourced by the pin.
3: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
4: VIL source < (VSS – 0.3). Characterized but not tested.
5: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
6: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
7: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
8: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2011-2013 Microchip Technology Inc. DS70657G-page 409
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
DO10 VOL Output Low Voltage
4x Sink Driver Pins(2)
——0.4VVDD = 3.3V,
I
OL
6 mA, -40°C
T
A
+85°C
I
OL
5 mA, +85°C
T
A
+125°C
Output Low Voltage
8x Sink Driver Pins(3)
——0.4VVDD = 3.3V,
I
OL
12 mA, -40°C
T
A
+85°C
I
OL
8 mA, +85°C
T
A
+125°C
DO20 VOH Output High Voltage
4x Source Driver Pins(2)
2.4 — — V IOH -10 mA, VDD = 3.3V
Output High Voltage
8x Source Driver Pins(3)
2.4 — — V IOH -15 mA, VDD = 3.3V
DO20A VOH1Output High Voltage
4x Source Driver Pins(2)
1.5(1)—— VIOH -14 mA, VDD = 3.3V
2.0(1)—— IOH -12 mA, VDD = 3.3V
3.0(1)—— IOH -7 mA, VDD = 3.3V
Output High Voltage
8x Source Driver Pins(3)
1.5(1)—— VIOH -22 mA, VDD = 3.3V
2.0(1)—— IOH -18 mA, VDD = 3.3V
3.0(1)—— IOH -10 mA, VDD = 3.3V
Note 1: Parameters are characterized but not tested.
2: Includes all I/O pins that are not 8x Sink Driver pins (see below).
3: Includes the following pins:
For devices with less than 64 pins: RA3, RA4, RA9, RB<7:15> and RC3
For 64-pin devices: RA4, RA9, RB<7:15>, RC3 and RC15
TABLE 30-13: ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min.(2)Typ. Max. Units Conditions
BO10 VBOR BOR Event on VDD Transition
High-to-Low
2.65 — 2.95 V VDD
(Notes 2 and 3)
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance.
2: Parameters are for design guidance only and are not tested in manufacturing.
3: The VBOR specification is relative to VDD.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 410 2011-2013 Microchip Technology Inc.
TABLE 30-14: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(1)Max. Units Conditions
Program Flash Memory
D130 EPCell Endurance 10,000 — — E/W -40C to +125C
D131 VPR VDD for Read 3.0 — 3.6 V
D132b VPEW VDD for Self-Timed Write 3.0 — 3.6 V
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated, -40C to +125C
D135 IDDP Supply Current during
Programming(2)
—10 —mA
D136 IPEAK Instantaneous Peak Current
During Start-up
——150mA
D137a TPE Page Erase Time 17.7 — 22.9 ms TPE = 146893 FRC cycles,
T
A = +85°C (See Note 3)
D137b TPE Page Erase Time 17.5 — 23.1 ms TPE = 146893 FRC cycles,
T
A = +125°C (See Note 3)
D138a TWW Word Write Cycle Time 41.7 — 53.8 µs TWW = 346 FRC cycles,
T
A = +85°C (See Note 3)
D138b TWW Word Write Cycle Time 41.2 — 54.4 µs TWW = 346 FRC cycles,
T
A = +125°C (See Note 3)
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: Parameter characterized but not tested in manufacturing.
3: Other conditions: FRC = 7.37 MHz, TUN<5:0> = 011111 (for Minimum), TUN<5:0> = 100000 (for
Maximum). This parameter depends on the FRC accuracy (see Table 30-19) and the value of the FRC
Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and
Maximum time, see Section 5.3 “Programming Operations”.
2011-2013 Microchip Technology Inc. DS70657G-page 411
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
30.2 AC Characteristics and Timing
Parameters
This section defines dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X AC characteristics and timing parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 30.1 “DC
Characteristics”.
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes, when
external clock is used to drive
OSC1
DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode
DO58 CBSCLx, SDAx — — 400 pF In I2C™ mode
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 412 2011-2013 Microchip Technology Inc.
FIGURE 30-2: EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4
OSC1
CLKO
Q1 Q2 Q3 Q4
OS20
OS25
OS30 OS30
OS40
OS41
OS31 OS31
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symb Characteristic Min. Typ.(1)Max. Units Conditions
OS10 FIN External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC — 60 MHz EC
Oscillator Crystal Frequency 3.5
10
—
—
10
25
MHz
MHz
XT
HS
OS20 TOSC TOSC = 1/FOSC 8.33 — DC ns +125ºC
TOSC = 1/FOSC 7.14 — DC ns +85ºC
OS25 TCY Instruction Cycle Time(2)16.67 — DC ns +125ºC
Instruction Cycle Time(2)14.28 — DC ns +85ºC
OS30 TosL,
To s H
External Clock in (OSC1)
High or Low Time
0.45 x TOSC — 0.55 x TOSC ns EC
OS31 TosR,
To s F
External Clock in (OSC1)
Rise or Fall Time
— — 20 ns EC
OS40 TckR CLKO Rise Time(3,4) —5.2—ns
OS41 TckF CLKO Fall Time(3,4)—5.2—ns
OS42 GMExternal Oscillator
Transconductance(4)
— 12 — mA/V HS, VDD = 3.3V,
TA = +25ºC
—6—mA/VXT, V
DD = 3.3V,
TA = +25ºC
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: This parameter is characterized, but not tested in manufacturing.
2011-2013 Microchip Technology Inc. DS70657G-page 413
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(1)Max. Units Conditions
OS50 FPLLI PLL Voltage Controlled Oscillator
(VCO) Input Frequency Range
0.8 — 8.0 MHz ECPLL, XTPLL modes
OS51 FSYS On-Chip VCO System Frequency 120 — 340 MHz
OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 ms
OS53 DCLK CLKO Stability (Jitter)(2)-3 0.5 3 %
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases, or communication clocks used by the application, use the following formula:
For example, if FOSC = 120 MHz and the SPIx bit rate = 10 MHz, the effective jitter is as follows:
Effective Jitter DCLK
FOSC
Time Base or Communication Clock
---------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------=
Effective Jitter DCLK
120
10
---------
--------------DCLK
12
--------------DCLK
3.464
--------------===
TABLE 30-19: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Characteristic Min. Typ. Max. Units Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a FRC -1.5 0.5 +1.5 % -40°C TA -10°C VDD = 3.0-3.6V
-1 0.5 +1 % -10°C T
A +85°C VDD = 3.0-3.6V
F20b FRC -2 1 +2 % +85°C T
A +125°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Characteristic Min. Typ. Max. Units Conditions
LPRC @ 32.768 kHz(1)
F21a LPRC -30 — +30 % -40°C TA -10°C VDD = 3.0-3.6V
-20 — +20 % -10°C TA +85°C VDD = 3.0-3.6V
F21b LPRC -30 — +30 % +85°C T
A +125°C VDD = 3.0-3.6V
Note 1: The change of LPRC frequency as VDD changes.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 414 2011-2013 Microchip Technology Inc.
FIGURE 30-3: I/O TIMING CHARACTERISTICS
FIGURE 30-4: BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
Note: Refer to Figure 30-1 for load conditions.
I/O Pin
(Input)
I/O Pin
(Output)
DI35
Old Value New Value
DI40
DO31
DO32
TABLE 30-21: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C
T
A
+85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(1)Max. Units Conditions
DO31 TIOR Port Output Rise Time — 5 10 ns
DO32 TIOF Port Output Fall Time — 5 10 ns
DI35 TINP INTx Pin High or Low Time (input) 20 — — ns
DI40 TRBP CNx High or Low Time (input) 2 — — TCY
Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
MCLR
(SY20)
BOR
(SY30)
TMCLR
TBOR
Reset Sequence
CPU Starts Fetching Code
Various Delays (depending on configuration)
2011-2013 Microchip Technology Inc. DS70657G-page 415
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SY00 TPU Power-up Period — 400 600 s
SY10 TOST Oscillator Start-up Time — 1024 TOSC ——TOSC = OSC1 period
SY12 TWDT Watchdog Timer
Time-out Period
0.85 — 1.15 ms WDTPRE = 0, WDTPOST = 0000,
using LPRC tolerances indicated
in F21 (see Table 30-20) at +85ºC
3.4 — 4.6 ms WDTPRE = 1, WDTPOST = 0000,
using LPRC tolerances indicated
in F21 (see Table 30-20) at +85ºC
SY13 TIOZ I/O High-Impedance
from MCLR Low or
Watchdog Timer Reset
0.68 0.72 1.2 s
SY20 TMCLR MCLR Pulse Width (low) 2 — — s
SY30 TBOR BOR Pulse Width (low) 1 — — s
SY35 TFSCM Fail-Safe Clock Monitor
Delay
— 500 900 s -40°C to +85°C
SY36 TVREG Voltage Regulator
Standby-to-Active mode
Transition Time
——30s
SY37 TOSCDFRC FRC Oscillator Start-up
Delay
46 48 54 s
SY38 TOSCDLPRC LPRC Oscillator Start-up
Delay
——70s
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 416 2011-2013 Microchip Technology Inc.
FIGURE 30-5: TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
Note: Refer to Figure 30-1 for load conditions.
Tx11
Tx15
Tx10
Tx20
TMRx
OS60
TxCK
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(2)Min. Typ. Max. Units Conditions
TA10 TTXH T1CK High
Time
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
— — ns Must also meet
Parameter TA15,
N = prescaler value
(1, 8, 64, 256)
Asynchronous 35 — — ns
TA11 TTXLT1CK Low
Time
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
— — ns Must also meet
Parameter TA15,
N = prescaler value
(1, 8, 64, 256)
Asynchronous 10 — — ns
TA15 TTXP T1CK Input
Period
Synchronous
mode
Greater of:
40 or
(2 T
CY + 40)/N
— — ns N = prescale value
(1, 8, 64, 256)
OS60 Ft1 T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON<1>))
DC — 50 kHz
TA20 TCKEXTMRL Delay from External T1CK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 ns
Note 1: Timer1 is a Type A.
2: These parameters are characterized, but are not tested in manufacturing.
2011-2013 Microchip Technology Inc. DS70657G-page 417
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-24: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ. Max. Units Conditions
TB10 TtxH TxCK High
Time
Synchronous
mode
Greater of:
20 or
(T
CY + 20)/N
— — ns Must also meet
Parameter TB15,
N = prescale
value
(1, 8, 64, 256)
TB11 TtxL TxCK Low
Time
Synchronous
mode
Greater of:
20 or
(T
CY + 20)/N
— — ns Must also meet
Parameter TB15,
N = prescale
value
(1, 8, 64, 256)
TB15 TtxP TxCK
Input
Period
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
— — ns N = prescale
value
(1, 8, 64, 256)
TB20 TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
TABLE 30-25: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ. Max. Units Conditions
TC10 TtxH TxCK High
Time
Synchronous TCY + 20 — — ns Must also meet
Parameter TC15
TC11 TtxL TxCK Low
Time
Synchronous TCY + 20 — — ns Must also meet
Parameter TC15
TC15 TtxP TxCK Input
Period
Synchronous,
with prescaler
2 T
CY + 40 — — ns N = prescale
value
(1, 8, 64, 256)
TC20 T
CKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40 — 1.75 TCY + 40 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 418 2011-2013 Microchip Technology Inc.
FIGURE 30-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10 IC11
IC15
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-26: INPUT CAPTURE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param.
No. Symbol Characteristics(1)Min. Max. Units Conditions
IC10 TCCL ICx Input Low Time Greater of
12.5 + 25 or
(0.5 TCY/N) + 25
— ns Must also meet
Parameter IC15
N = prescale value
(1, 4, 16)
IC11 TCCH ICx Input High Time Greater of
12.5 + 25 or
(0.5 TCY/N) + 25
— ns Must also meet
Parameter IC15
IC15 TCCP ICx Input Period Greater of
25 + 50
or
(1 TCY/N) + 50
—ns
Note 1: These parameters are characterized, but not tested in manufacturing.
2011-2013 Microchip Technology Inc. DS70657G-page 419
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-7: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
FIGURE 30-8: OCx/PWMx MODULE TIMING CHARACTERISTICS
OCx
OC11 OC10
(Output Compare x
Note: Refer to Figure 30-1 for load conditions.
or PWMx Mode)
TABLE 30-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ. Max. Units Conditions
OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32
OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31
Note 1: These parameters are characterized but not tested in manufacturing.
OCFA
OCx
OC20
OC15
TABLE 30-28: OCx/PWMx MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ. Max. Units Conditions
OC15 TFD Fault Input to PWMx I/O
Change
——TCY + 20 ns
OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 420 2011-2013 Microchip Technology Inc.
FIGURE 30-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
FIGURE 30-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
TABLE 30-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ. Max. Units Conditions
MP10 TFPWM PWMx Output Fall Time — — — ns See Parameter DO32
MP11 TRPWM PWMx Output Rise Time — — — ns See Parameter DO31
MP20 TFD Fault Input to PWMx
I/O Change
——15ns
MP30 TFH Fault Input Pulse Width 15 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
Fault Input
PWMx
MP30
MP20
(active-low)
PWMx
MP11 MP10
Note: Refer to Figure 30-1 for load conditions.
2011-2013 Microchip Technology Inc. DS70657G-page 421
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-11: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS
(dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
TQ11
TQ15
TQ10
TQ20
QEB
POSCNT
TABLE 30-30: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
(dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ. Max. Units Conditions
TQ10 TtQH TQCK High
Time
Synchronous,
with prescaler
Greater of 12.5 + 25
or
(0.5 T
CY/N) + 25
— — ns Must also meet
Parameter TQ15
TQ11 TtQL TQCK Low
Time
Synchronous,
with prescaler
Greater of 12.5 + 25
or
(0.5 T
CY/N) + 25
— — ns Must also meet
Parameter TQ15
TQ15 TtQP TQCP Input
Period
Synchronous,
with prescaler
Greater of 25 + 50
or
(1 TCY/N) + 50
——ns
TQ20 TCKEXTMRL Delay from External TQCK
Clock Edge to Timer
Increment
—1T
CY —
Note 1: These parameters are characterized but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 422 2011-2013 Microchip Technology Inc.
FIGURE 30-12: QEA/QEB INPUT CHARACTERISTICS
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
TQ30
TQ35
TQ31
QEA
(input)
TQ30
TQ35
TQ31
QEB
(input)
TQ36
QEB
Internal
TQ40TQ41
TABLE 30-31: QUADRATURE DECODER TIMING REQUIREMENTS
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Typ.(2)Max. Units Conditions
TQ30 TQUL Quadrature Input Low Time 6 TCY —ns
TQ31 TQUH Quadrature Input High Time 6 TCY —ns
TQ35 TQUIN Quadrature Input Period 12 TCY —ns
TQ36 TQUP Quadrature Phase Period 3 TCY —ns
TQ40 TQUFL Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, 128
and 256 (Note 3)
TQ41 TQUFH Filter Time to Recognize High,
with Digital Filter
3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, 128
and 256 (Note 3)
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 15. “Quadrature Encoder
Interface (QEI)” (DS70601) in the “dsPIC33E/PIC24E Family Reference Manual”. Please see the
Microchip web site for the latest family reference manual sections.
2011-2013 Microchip Technology Inc. DS70657G-page 423
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-13: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
QEA
(input)
Ungated
Index
QEB
(input)
TQ55
Index Internal
Position Counter
Reset
TQ50
TQ51
TABLE 30-32: QEI INDEX PULSE TIMING REQUIREMENTS
(dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Max. Units Conditions
TQ50 TqiL Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TQ51 TqiH Filter Time to Recognize High,
with Digital Filter
3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TQ55 Tqidxr Index Pulse Recognized to Position
Counter Reset (ungated index)
3 T
CY —ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but
index pulse recognition occurs on the falling edge.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 424 2011-2013 Microchip Technology Inc.
TABLE 30-33: SPI2 MAXIMUM DATA/CLOCK RATE SUMMARY
FIGURE 30-14: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE CKP SMP
15 MHz Table 30-33 ——0,10,10,1
9 MHz — Table 30-34 —10,11
9 MHz — Table 30-35 —00,11
15 MHz — — Table 30-36 100
11 MHz — — Table 30-37 110
15 MHz — — Table 30-38 010
11 MHz — — Table 30-39 000
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
2011-2013 Microchip Technology Inc. DS70657G-page 425
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-15: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
TABLE 30-34: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP10 FscP Maximum SCK2 Frequency — — 15 MHz (Note 3)
SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
—620ns
SP36 TdiV2scH,
TdiV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
SP36
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 426 2011-2013 Microchip Technology Inc.
FIGURE 30-16: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
TABLE 30-35: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP10 FscP Maximum SCK2 Frequency — — 9 MHz (Note 3)
SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
—620ns
SP36 TdoV2sc,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 ——ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data
Input to SCK2 Edge
30 ——ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI2 Data Input
to SCK2 Edge
30 ——ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPI2 pins.
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
SP36
SP41
MSb In LSb In
Bit 14 - - - -1
SDI2
SP40
2011-2013 Microchip Technology Inc. DS70657G-page 427
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-17: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
TABLE 30-36: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP10 FscP Maximum SCK2 Frequency — — 9 MHz -40ºC to +125ºC
(Note 3)
SP20 TscF SCK2 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK2 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 ——ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data
Input to SCK2 Edge
30 ——ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI2 Data Input
to SCK2 Edge
30 ——ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPI2 pins.
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SDI2
SP10
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
MSb In LSb In
Bit 14 - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
SP36
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 428 2011-2013 Microchip Technology Inc.
FIGURE 30-18: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SS2
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SP50
SP60
SDI2
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 30-1 for load conditions.
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 429
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-37: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK2 Input
Frequency
— — Lesser
of FP
or 15
MHz (Note 3)
SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120 — — ns
SP51 TssH2doZ SS2 to SDO2 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH
TscL2ssH
SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4)
SP60 TssL2doV SDO2 Data Output Valid after
SS2 Edge
— — 50 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 430 2011-2013 Microchip Technology Inc.
FIGURE 30-19: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SS2
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SP50
SP60
SDI2
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 30-1 for load conditions.
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 431
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-38: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK2 Input
Frequency
— — Lesser
of FP
or 11
MHz (Note 3)
SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120 — — ns
SP51 TssH2doZ SS2 to SDO2 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH
TscL2ssH
SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4)
SP60 TssL2doV SDO2 Data Output Valid after
SS2 Edge
— — 50 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 432 2011-2013 Microchip Technology Inc.
FIGURE 30-20: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SS2
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
MSb In Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 30-1 for load conditions.
SDI2
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 433
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-39: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK2 Input Frequency — — 15 MHz (Note 3)
SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120 — — ns
SP51 TssH2doZ SS2 to SDO2 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH
TscL2ssH
SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4)
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 434 2011-2013 Microchip Technology Inc.
FIGURE 30-21: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SS2
SCK2
(CKP = 0)
SCK2
(CKP = 1)
SDO2
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
MSb In Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 30-1 for load conditions.
SDI2
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 435
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-40: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK2 Input Frequency — — 11 MHz (Note 3)
SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO31
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120 — — ns
SP51 TssH2doZ SS2 to SDO2 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH
TscL2ssH
SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4)
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 436 2011-2013 Microchip Technology Inc.
TABLE 30-41: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY
FIGURE 30-22: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE CKP SMP
15 MHz Table 30-42 ——0,10,10,1
10 MHz — Table 30-43 —10,11
10 MHz — Table 30-44 —00,11
15 MHz — — Table 30-45 100
11 MHz — — Table 30-46 110
15 MHz — — Table 30-47 010
11 MHz — — Table 30-48 000
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
2011-2013 Microchip Technology Inc. DS70657G-page 437
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-23: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
TABLE 30-42: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP10 FscP Maximum SCK1 Frequency — — 15 MHz (Note 3)
SP20 TscF SCK1 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK1 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
—620ns
SP36 TdiV2scH,
TdiV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 — — ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
SP36
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 438 2011-2013 Microchip Technology Inc.
FIGURE 30-24: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
TABLE 30-43: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP10 FscP Maximum SCK1 Frequency — — 10 MHz (Note 3)
SP20 TscF SCK1 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK1 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
—620ns
SP36 TdoV2sc,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 ——ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data
Input to SCK1 Edge
30 ——ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI1 Data Input
to SCK1 Edge
30 ——ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPI1 pins.
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SP10
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
SP36
SP41
MSb In LSb In
Bit 14 - - - -1
SDI1
SP40
2011-2013 Microchip Technology Inc. DS70657G-page 439
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 30-25: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
TABLE 30-44: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP10 FscP Maximum SCK1 Frequency — — 10 MHz -40ºC to +125ºC
(Note 3)
SP20 TscF SCK1 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK1 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
—620ns
SP36 TdoV2scH,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 ——ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data
Input to SCK1 Edge
30 ——ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI1 Data Input
to SCK1 Edge
30 ——ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPI1 pins.
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SDI1
SP10
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
MSb In LSb In
Bit 14 - - - -1
SP30, SP31
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
SP36
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 440 2011-2013 Microchip Technology Inc.
FIGURE 30-26: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SS1
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SP50
SP60
SDI1
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 30-1 for load conditions.
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 441
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-45: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK1 Input
Frequency
— — Lesser of
FP or 15
MHz (Note 3)
SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120 — — ns
SP51 TssH2doZ SS1 to SDO1 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH
TscL2ssH
SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4)
SP60 TssL2doV SDO1 Data Output Valid after
SS1 Edge
— — 50 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 442 2011-2013 Microchip Technology Inc.
FIGURE 30-27: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SS1
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SP50
SP60
SDI1
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP35
SP52
SP73
SP72
SP72
SP73
SP70
SP40
SP41
Note: Refer to Figure 30-1 for load conditions.
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 443
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-46: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK1 Input
Frequency
— — Lesser of
FP or 11
MHz (Note 3)
SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120 — — ns
SP51 TssH2doZ SS1 to SDO1 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH,
TscL2ssH
SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4)
SP60 TssL2doV SDO1 Data Output Valid after
SS1 Edge
— — 50 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not
violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 444 2011-2013 Microchip Technology Inc.
FIGURE 30-28: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SS1
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
MSb In Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 30-1 for load conditions.
SDI1
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 445
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-47: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK1 Input Frequency — — 15 MHz (Note 3)
SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120 — — ns
SP51 TssH2doZ SS1 to SDO1 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH,
TscL2ssH
SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4)
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 446 2011-2013 Microchip Technology Inc.
FIGURE 30-29: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SS1
SCK1
(CKP = 0)
SCK1
(CKP = 1)
SDO1
SP50
SP40
SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
MSb In Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP70
Note: Refer to Figure 30-1 for load conditions.
SDI1
SP36
2011-2013 Microchip Technology Inc. DS70657G-page 447
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-48: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
SP70 FscP Maximum SCK1 Input Frequency — — 11 MHz (Note 3)
SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120 — — ns
SP51 TssH2doZ SS1 to SDO1 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH,
TscL2ssH
SS1 after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4)
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 448 2011-2013 Microchip Technology Inc.
FIGURE 30-30: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
FIGURE 30-31: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM31 IM34
SCLx
SDAx
Start
Condition
Stop
Condition
IM30 IM33
Note: Refer to Figure 30-1 for load conditions.
IM11 IM10 IM33
IM11
IM10
IM20
IM26
IM25
IM40 IM40 IM45
IM21
SCLx
SDAx
In
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
2011-2013 Microchip Technology Inc. DS70657G-page 449
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-49: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic(4)Min.(1)Max. Units Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode(2)TCY/2 (BRG + 2) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode(2)TCY/2 (BRG + 2) — s
IM20 TF:SCL SDAx and SCLx
Fall Time
100 kHz mode — 300 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)— 100 ns
IM21 TR:SCL SDAx and SCLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(2)— 300 ns
IM25 T
SU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(2)40 — ns
IM26 THD:DAT Data Input
Hold Time
100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode(2)0.2 — s
IM30 T
SU:STA Start Condition
Setup Time
100 kHz mode TCY/2 (BRG + 2) — s Only relevant for
Repeated Start
condition
400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode(2)TCY/2 (BRG + 2) — s
IM31 THD:STA Start Condition
Hold Time
100 kHz mode TCY/2 (BRG + 2) — s After this period, the
first clock pulse is
generated
400 kHz mode TCY/2 (BRG +2) — s
1 MHz mode(2)TCY/2 (BRG + 2) — s
IM33 TSU:STO Stop Condition
Setup Time
100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode(2)TCY/2 (BRG + 2) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s
Hold Time 400 kHz mode T
CY/2 (BRG + 2) — s
1 MHz mode(2)TCY/2 (BRG + 2) — s
IM40 T
AA:SCL Output Valid
From Clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(2)— 400 ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode(2)0.5 — s
IM50 CBBus Capacitive Loading — 400 pF
IM51 TPGD Pulse Gobbler Delay 65 390 ns (Note 3)
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit
(I2C™)” (DS70330) in the “dsPIC33E/PIC24E Family Reference Manual”. Please see the Microchip web
site for the latest family reference manual sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
4: These parameters are characterized, but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 450 2011-2013 Microchip Technology Inc.
FIGURE 30-32: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
FIGURE 30-33: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS31 IS34
SCLx
SDAx
Start
Condition
Stop
Condition
IS30 IS33
IS30 IS31 IS33
IS11
IS10
IS20
IS25
IS40 IS40 IS45
IS21
SCLx
SDAx
In
SDAx
Out
IS26
2011-2013 Microchip Technology Inc. DS70657G-page 451
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-50: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for
Extended
Param.
No. Symbol Characteristic(3)Min. Max. Units Conditions
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s
400 kHz mode 1.3 — s
1 MHz mode(1)0.5 — s
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1)0.5 — s
IS20 TF:SCL SDAx and SCLx
Fall Time
100 kHz mode — 300 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)—100ns
IS21 TR:SCL SDAx and SCLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1)—300ns
IS25 TSU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode(1)100 — ns
IS26 THD:DAT Data Input
Hold Time
100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode(1)00.3s
IS30 TSU:STA Start Condition
Setup Time
100 kHz mode 4.7 — s Only relevant for Repeated
Start condition
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS31 THD:STA Start Condition
Hold Time
100 kHz mode 4.0 — s After this period, the first
clock pulse is generated
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 — s
IS33 TSU:STO Stop Condition
Setup Time
100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
1 MHz mode(1)0.6 — s
IS34 THD:STO Stop Condition
Hold Time
100 kHz mode 4 — s
400 kHz mode 0.6 — s
1 MHz mode(1)0.25 s
IS40 TAA:SCL Output Valid
From Clock
100 kHz mode 0 3500 ns
400 kHz mode 0 1000 ns
1 MHz mode(1)0350ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
1 MHz mode(1)0.5 — s
IS50 CBBus Capacitive Loading — 400 pF
IS51 TPGD Pulse Gobbler Delay 65 390 ns (Note 2)
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: Typical value for this parameter is 130 ns.
3: These parameters are characterized, but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 452 2011-2013 Microchip Technology Inc.
FIGURE 30-34: ECANx MODULE I/O TIMING CHARACTERISTICS
TABLE 30-51: ECANx MODULE I/O TIMING REQUIREMENTS
FIGURE 30-35: UARTx MODULE I/O TIMING CHARACTERISTICS
TABLE 30-52: UARTx MODULE I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
CA10 TIOF Port Output Fall Time — — — ns See Parameter DO32
CA11 TIOR Port Output Rise Time — — — ns See Parameter DO31
CA20 TCWF Pulse Width to Trigger
CAN Wake-up Filter
120 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +125°C
Param
No. Symbol Characteristic(1)Min. Typ.(2)Max. Units Conditions
UA10 TUABAUD UARTx Baud Time 66.67 — — ns
UA11 FBAUD UARTx Baud Frequency — — 15 Mbps
UA20 T
CWF Start Bit Pulse Width to Trigger
UARTx Wake-up
500 — — ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
CxTx Pin
(output)
CA10 CA11
Old Value New Value
CA20
CxRx Pin
(input)
UA20
UxRX MSb In LSb In
Bit 6-1
UA10
UXTX
2011-2013 Microchip Technology Inc. DS70657G-page 453
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(2)Max. Units Conditions
Comparator AC Characteristics
CM10 TRESP Response Time(3)— 19 — ns V+ input step of 100 mV,
V- input held at VDD/2
CM11 TMC2OV Comparator Mode
Change to Output Valid
——10µs
Comparator DC Characteristics
CM30 VOFFSET Comparator Offset
Voltage
—±1040 mV
CM31 VHYST Input Hysteresis
Voltage(3)
—30—mV
CM32 TRISE/
TFALL
Comparator Output Rise/
Fall Time(3)
— 20 — ns 1 pF load capacitance
on input
CM33 VGAIN Open-Loop Voltage
Gain(3)
—90— db
CM34 VICM Input Common-Mode
Voltage
AVSS —AVDD V
Op Amp AC Characteristics
CM20 SRSlew Rate(3)— 9 — V/µs 10 pF load
CM21a PMPhase Margin
(Configuration A)(3,4)
— 55 — Degree G = 100V/V; 10 pF load
CM21b PMPhase Margin
(Configuration B)(3,5)
— 40 — Degree G = 100V/V; 10 pF load
CM22 GMGain Margin(3) — 20 — db G = 100V/V; 10 pF load
CM23a GBW Gain Bandwidth
(Configuration A)(3,4)
— 10 — MHz 10 pF load
CM23b GBW Gain Bandwidth
(Configuration B)(3,5)
— 6 — MHz 10 pF load
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and
maximum BOR values.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: Parameter is characterized but not tested in manufacturing.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: Resistances can vary by ±10% between op amps.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 454 2011-2013 Microchip Technology Inc.
Op Amp DC Characteristics
CM40 VCMR Common-Mode Input
Voltage Range
AVSS — AVDD V
CM41 CMRR Common-Mode
Rejection Ratio(3)
—40— dbVCM = AVDD/2
CM42 VOFFSET Op Amp Offset
Voltage(3)
— ±5—mV
CM43 VGAIN Open-Loop Voltage
Gain(3)
—90— db
CM44 IOS Input Offset Current — — — — See pad leakage
currents in Table 30-11
CM45 IBInput Bias Current — — — — See pad leakage
currents in Table 30-11
CM46 IOUT Output Current — — 420 µA With minimum value of
RFEEDBACK (CM48)
CM48 RFEEDBACK Feedback Resistance
Value
8——k
CM49a VOADC Output Voltage
Measured at OAx Using
ADC(3,4)
AVSS + 0.077
AVSS + 0.037
AVSS + 0.018
—
—
—
AVDD – 0.077
AVDD – 0.037
AVDD – 0.018
V
V
V
IOUT = 420 µA
IOUT = 200 µA
IOUT = 100 µA
CM49b VOUT Output Voltage
Measured at OAxOUT
Pin(3,4,5)
AVSS + 0.210
AVSS + 0.100
AVSS + 0.050
—
—
—
AVDD – 0.210
AVDD – 0.100
AVDD – 0.050
V
V
V
IOUT = 420 µA
IOUT = 200 µA
IOUT = 100 µA
CM51 RINT1(6)Internal Resistance 1
(Configuration A
and B)(3,4,5)
198 264 317 Min = -40ºC
Typ = +25ºC
Max = +125ºC
TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(2)Max. Units Conditions
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and
maximum BOR values.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
3: Parameter is characterized but not tested in manufacturing.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: Resistances can vary by ±10% between op amps.
2011-2013 Microchip Technology Inc. DS70657G-page 455
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-55: OP AMP/COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
TABLE 30-54: OP AMP/COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (see Note 2): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
VR310 TSET Settling Time — 1 10 s(Note 1)
Note 1: Settling time is measured while CVRR = 1 and CVR<3:0> bits transition from ‘0000’ to ‘1111’.
2: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum
and maximum BOR values.
DC CHARACTERISTICS
Standard Operating Conditions (see Note 1): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristics Min. Typ. Max. Units Conditions
VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb
VRD311 CVRAA Absolute Accuracy(2)—±25—mVCVRSRC = 3.3V
VRD313 CVRSRC Input Reference Voltage 0 — AVDD + 0.3 V
VRD314 CVROUT Buffer Output
Resistance(2)
—1.5k—
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum
and maximum BOR values.
2: Parameter is characterized but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 456 2011-2013 Microchip Technology Inc.
TABLE 30-56: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions:3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
CTMU Current Source
CTMUI1 IOUT1 Base Range(1)0.29 — 0.77 µA CTMUICON<9:8> = 01
CTMUI2 IOUT2 10x Range(1)3.85 — 7.7 µA CTMUICON<9:8> = 10
CTMUI3 IOUT3 100x Range(1)38.5 — 77 µA CTMUICON<9:8> = 11
CTMUI4 IOUT4 1000x Range(1)385 — 770 µA CTMUICON<9:8> = 00
CTMUFV1 VFTemperature Diode Forward
Voltage(1,2)
—0.598— VTA = +25ºC,
CTMUICON<9:8> = 01
—0.658— VT
A = +25ºC,
CTMUICON<9:8> = 10
—0.721— VT
A = +25ºC,
CTMUICON<9:8> = 11
CTMUFV2 VFVR Temperature Diode Rate of
Change(1,2,3)
— -1.92 — mV/ºC CTMUICON<9:8> = 01
— -1.74 — mV/ºC CTMUICON<9:8> = 10
— -1.56 — mV/ºC CTMUICON<9:8> = 11
Note 1: Nominal value at center point of current trim range (CTMUICON<15:10> = 000000).
2: Parameters are characterized but not tested in manufacturing.
3: Measurements taken with the following conditions:
•VREF+ = AVDD = 3.3V
• ADC configured for 10-bit mode
• ADC module configured for conversion speed of 500 ksps
• All PMDx bits are cleared (PMDx = 0)
• Executing a while(1) statement
• Device operating from the FRC with no PLL
2011-2013 Microchip Technology Inc. DS70657G-page 457
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-57: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Device Supply
AD01 AVDD Module VDD Supply Greater of
VDD – 0.3
or 3.0
— Lesser of
VDD + 0.3
or 3.6
V
AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.5 — AVDD VVREFH = VREF+
VREFL = VREF- (Note 1)
AD05a 3.0 — 3.6 V VREFH = AVDD
VREFL = AVSS = 0
AD06 VREFL Reference Voltage Low AVSS —AVDD – 2.5 V (Note 1)
AD06a 0 — 0 V VREFH = AVDD
VREFL = AVSS = 0
AD07 VREF Absolute Reference
Voltage
2.5 — 3.6 V VREF = VREFH - VREFL
AD08 IREF Current Drain —
—
—
—
10
600
A
A
ADC off
ADC on
AD09 IAD Operating Current(2)— 5 — mA ADC operating in 10-bit mode
(Note 1)
— 2 — mA ADC operating in 12-bit mode
(Note 1)
Analog Input
AD12 VINH Input Voltage Range
VINH
VINL —VREFH V This voltage reflects Sample-and-
Hold Channels 0, 1, 2 and 3
(CH0-CH3), positive input
AD13 VINL Input Voltage Range
VINL
VREFL —AVSS + 1V V This voltage reflects Sample-and-
Hold Channels 0, 1, 2 and 3
(CH0-CH3), negative input
AD17 RIN Recommended
Impedance of Analog
Voltage Source
——200Impedance to achieve maximum
performance of ADC
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and
maximum BOR values.
2: Parameter is characterized but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 458 2011-2013 Microchip Technology Inc.
TABLE 30-58: ADC MODULE SPECIFICATIONS (12-BIT MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
ADC Accuracy (12-Bit Mode)
AD20a Nr Resolution 12 Data Bits bits
AD21a INL Integral Nonlinearity -2.5 — 2.5 LSb -40°C T
A +85°C (Note 2)
-5.5 — 5.5 LSb +85°C TA +125°C (Note 2)
AD22a DNL Differential Nonlinearity -1 — 1 LSb -40°C T
A +85°C (Note 2)
-1 — 1 LSb +85°C TA +125°C (Note 2)
AD23a GERR Gain Error(3)-10 — 10 LSb -40°C TA +85°C (Note 2)
-10 — 10 LSb +85°C T
A +125°C (Note 2)
AD24a EOFF Offset Error -5 — 5 LSb -40°C TA +85°C (Note 2)
-5 — 5 LSb +85°C TA +125°C (Note 2)
AD25a — Monotonicity — — — — Guaranteed
Dynamic Performance (12-Bit Mode)
AD30a THD Total Harmonic Distortion(3)—75—dB
AD31a SINAD Signal to Noise and
Distortion(3)
—68—dB
AD32a SFDR Spurious Free Dynamic
Range(3)
—80—dB
AD33a FNYQ Input Signal Bandwidth(3)—250—kHz
AD34a ENOB Effective Number of Bits(3)11.09 11.3 — bits
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum
and maximum BOR values.
2: For all accuracy specifications, VINL = AVSS = VREFL = 0V and AVDD = VREFH = 3.6V.
3: Parameters are characterized but not tested in manufacturing.
2011-2013 Microchip Technology Inc. DS70657G-page 459
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-59: ADC MODULE SPECIFICATIONS (10-BIT MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
ADC Accuracy (10-Bit Mode)
AD20b Nr Resolution 10 Data Bits bits
AD21b INL Integral Nonlinearity -0.625 — 0.625 LSb -40°C T
A +85°C (Note 2)
-1.5 — 1.5 LSb +85°C TA +125°C (Note 2)
AD22b DNL Differential Nonlinearity -0.25 — 0.25 LSb -40°C T
A +85°C (Note 2)
-0.25 — 0.25 LSb +85°C TA +125°C (Note 2)
AD23b GERR Gain Error -2.5 — 2.5 LSb -40°C TA +85°C (Note 2)
-2.5 — 2.5 LSb +85°C T
A +125°C (Note 2)
AD24b EOFF Offset Error -1.25 — 1.25 LSb -40°C TA +85°C (Note 2)
-1.25 — 1.25 LSb +85°C TA +125°C (Note 2)
AD25b — Monotonicity — — — — Guaranteed
Dynamic Performance (10-Bit Mode)
AD30b THD Total Harmonic Distortion(3)—64—dB
AD31b SINAD Signal to Noise and
Distortion(3)
—57—dB
AD32b SFDR Spurious Free Dynamic
Range(3)
—72—dB
AD33b FNYQ Input Signal Bandwidth(3)—550—kHz
AD34b ENOB Effective Number of Bits(3)—9.4—bits
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum
and maximum BOR values.
2: For all accuracy specifications, VINL = AVSS = VREFL = 0V and AVDD = VREFH = 3.6V.
3: Parameters are characterized but not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 460 2011-2013 Microchip Technology Inc.
FIGURE 30-36: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 0, SSRC<2:0> = 000, SSRCG = 0)
AD55
TSAMP
Clear SAMPSet SAMP
AD61
ADCLK
Instruction
SAMP
AD60
DONE
AD1IF
1 2 3 4 5 6 87
1– Software sets AD1CON1. SAMP to start sampling.
2– Sampling starts after discharge period. TSAMP is described in
3– Software clears AD1CON1. SAMP to start conversion.
4– Sampling ends, conversion sequence starts.
5– Convert bit 11.
9– One TAD for end of conversion.
AD50
9
6– Convert bit 10.
7– Convert bit 1.
8– Convert bit 0.
Execution
“dsPIC33E/PIC24E Family Reference Manual”.
Section 16. “Analog-to-Digital Converter (ADC)” (DS70621) of the
2011-2013 Microchip Technology Inc. DS70657G-page 461
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-60: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Clock Parameters
AD50 TAD ADC Clock Period 117.6 — — ns
AD51 tRC
ADC Internal RC Oscillator Period
(2)
—250— ns
Conversion Rate
AD55 tCONV Conversion Time — 14 TAD ns
AD56 FCNV Throughput Rate — — 500 ksps
AD57a TSAMP Sample Time when Sampling any
ANx Input
3 TAD —— —
AD57b TSAMP Sample Time when Sampling the Op
Amp Outputs (Configuration A and
Configuration B)(4,5)
3 TAD —— —
Timing Parameters
AD60 tPCS Conversion Start from Sample
Trigger(
2
,3)
2 TAD —3 TAD — Auto-convert trigger is
not selected
AD61 tPSS Sample Start from Setting
Sample (SAMP) bit(
2
,3)
2 TAD —3 TAD —
AD62 tCSS Conversion Completion to
Sample Start (ASAM = 1)(
2
,3)
— 0.5 TAD ——
AD63 tDPU Time to Stabilize Analog Stage
from ADC Off to ADC On(
2
,3)
——20s(Note 6)
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum
and maximum BOR values.
2: Parameters are characterized but not tested in manufacturing.
3: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the
module is turned on (ADON (AD1CON1<15>) = 1). During this time, the ADC result is indeterminate.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 462 2011-2013 Microchip Technology Inc.
FIGURE 30-37: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000, SSRCG = 0)
FIGURE 30-38: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SSRCG = 0, SAMC<4:0> = 00010)
AD55
TSAMP
Clear SAMPSet SAMP
AD61
ADCLK
Instruction
SAMP
AD60
DONE
AD1IF
1 2 3 4 5 6 8 5 6 7
1– Software sets AD1CON1. SAMP to start sampling.
2– Sampling starts after discharge period. TSAMP is described in
3– Software clears AD1CON1. SAMP to start conversion.
4– Sampling ends, conversion sequence starts.
5– Convert bit 9.
8– One TAD for end of conversion.
AD50
7
AD55
8
6– Convert bit 8.
7– Convert bit 0.
Execution
“dsPIC33E/PIC24E Family Reference Manual”.
Section 16. “Analog-to-Digital Converter (ADC)” (DS70621) of the
1 2 3 4 5 6 4 5 6 8
1– Software sets AD1CON1. ADON to start AD operation.
2– Sampling starts after discharge period. TSAMP is described in
3– Convert bit 9.
4– Convert bit 8.
5– Convert bit 0.
7 3
6– One TAD for end of conversion.
7– Begin conversion of next channel.
8– Sample for time specified by SAMC<4:0>.
ADCLK
Instruction Set ADON
Execution
SAMP
TSAMP
AD1IF
DONE
AD55 AD55 TSAMP AD55
AD50
Section 16. “Analog-to-Digital Converter (ADC)” (DS70621)
of the “dsPIC33E/PIC24E Family Reference Manual”.
AD62
2011-2013 Microchip Technology Inc. DS70657G-page 463
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-61: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Clock Parameters
AD50 T
AD ADC Clock Period 76 — — ns
AD51 tRC
ADC Internal RC Oscillator Period
(2)
—250— ns
Conversion Rate
AD55 tCONV Conversion Time — 12 TAD ——
AD56 FCNV Throughput Rate — — 1.1 Msps Using simultaneous
sampling
AD57a T
SAMP Sample Time when Sampling any
ANx Input
2 TAD ———
AD57b T
SAMP Sample Time when Sampling the
Op Amp Outputs (Configuration A
and Configuration B)(4,5)
4 TAD ———
Timing Parameters
AD60 tPCS Conversion Start from Sample
Trigger(
2,
3)
2 TAD —3 TAD — Auto-convert trigger is
not selected
AD61 tPSS Sample Start from Setting
Sample (SAMP) bit(
2,
3))
2 TAD —3 TAD —
AD62 tCSS Conversion Completion to
Sample Start (ASAM = 1)(
2,
3)
—0.5 TAD ——
AD63 tDPU Time to Stabilize Analog Stage
from ADC Off to ADC On(
2,
3)
——20s(Note 6)
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum
and maximum BOR values.
2: Parameters are characterized but not tested in manufacturing.
3: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: The parameter, tDPU, is the time required for the ADC module to stabilize at the appropriate level when the
module is turned on (ADON (AD1CON1<15>) = 1). During this time, the ADC result is indeterminate.
TABLE 30-62: DMA MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Characteristic Min. Typ.(1)Max. Units Conditions
DM1 DMA Byte/Word Transfer Latency 1 TCY(2)——ns
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because DMA transfers use the CPU data bus, this time is dependent on other functions on the bus.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 464 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 465
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
31.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C.
The specifications between -40°C to +150°C are identical to those shown in Section 30.0 “Electrical Characteristics”
for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
Parameters in this section begin with an H, which denotes High temperature. For example, Parameter DC10 in
Section 30.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10.
Absolute maximum ratings for the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
high-temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can
affect device reliability. Functional operation of the device at these or any other conditions above the parameters
indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias(2).........................................................................................................-40°C to +150°C
Storage temperature .............................................................................................................................. -65°C to +160°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(3) .................................................... -0.3V to 3.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) .................................................... -0.3V to 5.5V
Maximum current out of VSS pin .............................................................................................................................60 mA
Maximum current into VDD pin(4).............................................................................................................................60 mA
Maximum junction temperature............................................................................................................................. +155°C
Maximum current sourced/sunk by any 4x I/O pin..................................................................................................10 mA
Maximum current sourced/sunk by any 8x I/O pin..................................................................................................15 mA
Maximum current sunk by all ports combined ........................................................................................................70 mA
Maximum current sourced by all ports combined(4)................................................................................................70 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which
the total operating time from +125°C to +150°C will be greater than 1,000 hours is not warranted without
prior written approval from Microchip Technology Inc.
3: Refer to the “Pin Diagrams” section for 5V tolerant pins.
4: Maximum allowable current is a function of device maximum power dissipation (see Tab l e 3 1- 2 ).
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 466 2011-2013 Microchip Technology Inc.
31.1 High-Temperature DC Characteristics
TABLE 31-1: OPERATING MIPS VS. VOLTAGE
TABLE 31-2: THERMAL OPERATING CONDITIONS
TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Characteristic VDD Range
(in Volts)
Temperature Range
(in °C)
Max MIPS
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
HDC5 3.0 to 3.6V(1)-40°C to +150°C 40
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules, such as the ADC, may have degraded
performance. Device functionality is tested but not characterized.
Rating Symbol Min Typ Max Unit
High-Temperature Devices
Operating Junction Temperature Range TJ-40 — +155 °C
Operating Ambient Temperature Range TA-40 — +150 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH) PDPINT + PI/OW
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Parameter
No. Symbol Characteristic Min Typ Max Units Conditions
Operating Voltage
HDC10 Supply Voltage
VDD — 3.0 3.3 3.6 V -40°C to +150°C
2011-2013 Microchip Technology Inc. DS70657G-page 467
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
TABLE 31-6: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Parameter
No. Typical Max Units Conditions
Power-Down Current (IPD)
HDC60e 750 2500 A +150°C 3.3V Base Power-Down Current
(Notes 1, 3)
HDC61c 15 — A +150°C 3.3V Watchdog Timer Current: IWDT
(Notes 2, 4)
Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off and VREGS (RCON<8>) = 1.
2: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
3: These currents are measured on the device containing the most memory in this family.
4: These parameters are characterized, but are not tested in manufacturing.
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A +150°C
Parameter
No. Typical Max Units Conditions
HDC20 9 15 mA +150°C 3.3V 10 MIPS
HDC22 16 25 mA +150°C 3.3V 20 MIPS
HDC23 30 50 mA +150°C 3.3V 40 MIPS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Parameter
No. Typical Max Doze
Ratio Units Conditions
HDC72a 24 35 1:2 mA
+150°C 3.3V 40 MIPSHDC72f(1)14 — 1:64 mA
HDC72g(1)12 — 1:128 mA
Note 1: Parameters with Doze ratios of 1:64 and 1:128 are characterized, but are not tested in manufacturing.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 468 2011-2013 Microchip Technology Inc.
TABLE 31-7: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
HDO10 VOL Output Low Voltage
4x Sink Driver Pins(2)
——0.4VIOL 5mA, VDD = 3.3V
(Note 1)
Output Low Voltage
8x Sink Driver Pins(3)
——0.4VIOL 8 mA, VDD = 3.3V
(Note 1)
HDO20 VOH Output High Voltage
4x Source Driver Pins(2)
2.4 — — V IOH -10 mA, VDD = 3.3V
(Note 1)
Output High Voltage
8x Source Driver Pins(3)
2.4 — — V IOH 15 mA, VDD = 3.3V
(Note 1)
HDO20A VOH1Output High Voltage
4x Source Driver Pins(2)
1.5 — — V IOH -3.9 mA, VDD = 3.3V
(Note 1)
2.0 — — IOH -3.7 mA, VDD = 3.3V
(Note 1)
3.0 — — IOH -2 mA, VDD = 3.3V
(Note 1)
Output High Voltage
8x Source Driver Pins(3)
1.5 — — V IOH -7.5 mA, VDD = 3.3V
(Note 1)
2.0 — — IOH -6.8 mA, VDD = 3.3V
(Note 1)
3.0 — — IOH -3 mA, VDD = 3.3V
(Note 1)
Note 1: Parameters are characterized, but not tested.
2: Includes all I/O pins that are not 8x Sink Driver pins (see below).
3: Includes the following pins:
For devices with less than 64 pins: RA3, RA4, RA9, RB<7:15> and RC3
For 64-pin devices: RA4, RA9, RB<7:15>, RC3 and RC15
2011-2013 Microchip Technology Inc. DS70657G-page 469
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
31.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X AC characteristics and
timing parameters for high-temperature devices.
However, all AC timing specifications in this section are
the same as those in Section 30.2 “AC Characteristics
and Timing Parameters”, with the exception of the
parameters listed in this section.
Parameters in this section begin with an H, which denotes
High temperature. For example, Parameter OS53 in
Section 30.2 “AC Characteristics and Timing
Parameters” is the Industrial and Extended temperature
equivalent of HOS53.
TABLE 31-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 31-9: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Operating voltage VDD range as described in Table 31-1.
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Param
No. Symbol Characteristic Min Typ Max Units Conditions
HOS53 DCLK CLKO Stability (Jitter)(1)-5 0.5 5 % Measured over 100 ms
period
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time
bases or communication clocks use this formula:
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
Peripheral Clock Jitter DCLK
FOSC
Peripheral Bit Rate Clock
--------------------------------------------------------------
------------------------------------------------------------------------=
For example: FOSC = 32 MHz, DCLK = 5%, SPIx bit rate clock (i.e., SCKx) is 2 MHz.
SPI SCK Jitter DCLK
32 MHz
2 MHz
--------------------
------------------------------5%
16
----------5%
4
--------1.25%====
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 470 2011-2013 Microchip Technology Inc.
TABLE 31-10: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA+150°C
Param
No. Characteristic Min Typ Max Units Conditions
LPRC @ 32.768 kHz(1,2)
HF21 LPRC -30 — +30 % -40°C TA +150°C VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 27.5 “Watchdog
Timer (WDT)” for more information.
2011-2013 Microchip Technology Inc. DS70657G-page 471
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 31-11: ADC MODULE SPECIFICATIONS (12-BIT MODE)
TABLE 31-12: ADC MODULE SPECIFICATIONS (10-BIT MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Param
No. Symbol Characteristic Min Typ Max Units Conditions
ADC Accuracy (12-Bit Mode)(1)
HAD20a Nr Resolution(3)12 Data Bits bits
HAD21a INL Integral Nonlinearity -5.5 — 5.5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD22a DNL Differential Nonlinearity -1 — 1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD23a GERR Gain Error -10 — 10 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD24a EOFF Offset Error -5 — 5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Dynamic Performance (12-Bit Mode)(2)
HAD33a FNYQ Input Signal Bandwidth — — 200 kHz
Note 1: These parameters are characterized, but are tested at 20 ksps only.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Param
No. Symbol Characteristic Min Typ Max Units Conditions
ADC Accuracy (10-Bit Mode)(1)
HAD20b Nr Resolution(3)10 Data Bits bits
HAD21b INL Integral Nonlinearity -1.5 — 1.5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD22b DNL Differential Nonlinearity -0.25 — 0.25 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD23b GERR Gain Error -2.5 — 2.5 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD24b EOFF Offset Error -1.25 — 1.25 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Dynamic Performance (10-Bit Mode)(2)
HAD33b FNYQ Input Signal Bandwidth — — 400 kHz
Note 1: These parameters are characterized, but are tested at 20 ksps only.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 472 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 473
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
32.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
FIGURE 32-1: VOH – 4x DRIVER PINS
FIGURE 32-2: VOH – 8x DRIVER PINS
FIGURE 32-3: VOL – 4x DRIVER PINS
FIGURE 32-4: VOL – 8x DRIVER PINS
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
-0.050
-0.045
-0.040
-0.035
-0.030
-0.025
-0.020
IOH(A)
VOH (V)
-0.050
-0.045
-0.040
-0.035
-0.030
-0.025
-0.020
-0.015
-0.010
-0.005
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOH (V)
3V
3.3V
3.6V
Absolute Maximum
-0.080
-0.070
-0.060
-0.050
-0.040
0 030
IOH(A)
VOH(V)
-0.080
-0.070
-0.060
-0.050
-0.040
-0.030
-0.020
-0.010
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOH(V)
3V
3.3V
3.6V
Absolute Maximum
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
IOH(A)
VOL(V)
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOL(V)
3V
3.3V
3.6V
Absolute Maximum
0020
0.030
0.040
0.050
0.060
0.070
0.080
IOH(A)
VOL(V) 8X
0.000
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOL(V) 8X
3V
3.3V
3.6V
Absolute Maximum
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 474 2011-2013 Microchip Technology Inc.
FIGURE 32-5: TYPICAL IPD CURRENT @ VDD = 3.3V
FIGURE 32-6: TYPICAL IDD CURRENT @ VDD = 3.3V
FIGURE 32-7: TYPICAL IDOZE CURRENT @ VDD = 3.3V
FIGURE 32-8: TYPICAL IIDLE CURRENT @ VDD = 3.3V
200.00
300.00
400.00
500.00
600.00
700.00
800.00
IPD Current (µA)
0.00
100.00
200.00
300.00
400.00
500.00
600.00
700.00
800.00
-40-30-20-10 0 102030405060708090100110120
IPD Current (µA)
Temperature (Celsius)
0
10
20
30
40
50
0 20406080
32K
64K
128K
256K
MIPS
IDD (mA)
15.00
20.00
25.00
30.00
35.00
40.00
45.00
O
ZE
Current (mA)
0.00
5.00
10.00
15.00
20.00
25.00
30.00
35.00
40.00
45.00
1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
I
DOZE
Current (mA)
Doze Ratio
10.00
15.00
20.00
25.00
IDLE
Current (mA)
0.00
5.00
10.00
15.00
20.00
25.00
0 10203040506070
I
IDLE
Current (mA)
MIPS
IIDLE (EC)
IIDLE (EC+PLL)
2011-2013 Microchip Technology Inc. DS70657G-page 475
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 32-9: TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 32-10: TYPICAL LPRC FREQUENCY @ VDD = 3.3V
FIGURE 32-11: TYPICAL CTMU TEMPERATURE DIODE
FORWARD VOLTAGE
7310
7320
7330
7340
7350
7360
7370
7380
FRC Frequency (kHz)
7280
7290
7300
7310
7320
7330
7340
7350
7360
7370
7380
-40-30-20-10 0 102030405060708090100110120
FRC Frequency (kHz)
Temperature (Celsius)
31
32
33
LPRC Frequency (kHz)
30
31
32
33
-40-30-20-100 102030405060708090100110120
LPRC Frequency (kHz)
Temperature (Celsius)
0.550
0.600
0.650
0.700
0.750
0.800
0.850
Forward Voltage (V)
0.350
0.400
0.450
0.500
0.550
0.600
0.650
0.700
0.750
0.800
0.850
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Forward Voltage (V)
Temperature (Celsius)
VF = 0.598
VF = 0.658
VF = 0.721
65 µA, V
FVR
= -1.56 mV/ºC
6.5 µA, V
FVR
= -1.74 mV/ºC
0.65 µA, V
FVR
= -1.92 mV/ºC
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 476 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 477
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
33.0 PACKAGING INFORMATION
33.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
28-Lead SPDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33EP64GP
1310017
502-I/SP
3
e
28-Lead SOIC (.300”)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
dsPIC33EP64GP
1310017
502-I/SO
3
e
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
dsPIC33EP64
GP502-I/SS
1310017
3
e
XXXXXXXX
28-Lead QFN-S (6x6x0.9 mm)
XXXXXXXX
YYWWNNN
33EP64GP
Example
502-I/MM
1310017
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 478 2011-2013 Microchip Technology Inc.
33.1 Package Marking Information (Continued)
XXXXXXXXXX
36-Lead VTLA (TLA)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
XXXXXXXXXX
44-Lead VTLA (TLA)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
504-I/TL
1310017
33EP64GP
3
e
Example
504-I/TL
1310017
33EP64GP
3
e
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
33EP64GP
504-I/PT
1310017
3
e
XXXXXXXXXXX
44-Lead QFN (8x8x0.9 mm)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
33EP64GP
Example
504-I/ML
1310017
3
e
2011-2013 Microchip Technology Inc. DS70657G-page 479
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
33.1 Package Marking Information (Continued)
XXXXXXXXXXX
64-Lead QFN (9x9x0.9 mm)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
dsPIC33EP
Example
64GP506
1310017
3
e
-I/MR
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
dsPIC33EP
64GP506
1310017
-I/PT
3
e
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 480 2011-2013 Microchip Technology Inc.
33.2 Package Details
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2011-2013 Microchip Technology Inc. DS70657G-page 481
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 482 2011-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc. DS70657G-page 483
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 484 2011-2013 Microchip Technology Inc.
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2011-2013 Microchip Technology Inc. DS70657G-page 485
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 486 2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc. DS70657G-page 487
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 490 2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc. DS70657G-page 491
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 492 2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc. DS70657G-page 493
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
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dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 494 2011-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc. DS70657G-page 495
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 496 2011-2013 Microchip Technology Inc.
2011-2013 Microchip Technology Inc. DS70657G-page 497
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 498 2011-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2013 Microchip Technology Inc. DS70657G-page 499
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 500 2011-2013 Microchip Technology Inc.
64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 64
Lead Pitch e 0.50 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 – 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ0° 3.5° 7°
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 – 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top α11° 12° 13°
Mold Draft Angle Bottom β11° 12° 13°
D
D1
E
E1
e
b
N
NOTE 1123 NOTE 2
c
L
A1
L1
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φ
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Microchip Technology Drawing C04-085B
2011-2013 Microchip Technology Inc. DS70657G-page 501
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 502 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 503
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
APPENDIX A: REVISION HISTORY
Revision A (April 2011)
This is the initial released version of the document.
Revision B (July 2011)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in Tab le A-1 .
TABLE A-1: MAJOR SECTION UPDATES
Section Name Update Description
“High-Performance, 16-bit
Digital Signal Controllers
and Microcontrollers”
Changed all pin diagrams references of VLAP to TLA.
Section 4.0 “Memory
Organization”
Updated the All Resets values for CLKDIV and PLLFBD in the System Control
Register Map (see Table 4-35).
Section 5.0 “Flash Program
Memory”
Updated “one word” to “two words” in the first paragraph of Section 5.2 “RTSP
Operation”.
Section 9.0 “Oscillator
Configuration”
Updated the PLL Block Diagram (see Figure 9-2).
Updated the Oscillator Mode, Fast RC Oscillator (FRC) with divide-by-N and PLL
(FRCPLL), by changing (FRCDIVN + PLL) to (FRCPLL).
Changed (FRCDIVN + PLL) to (FRCPLL) for COSC<2:0> = 001 and
NOSC<2:0> = 001 in the Oscillator Control Register (see Register 9-1).
Changed the POR value from 0 to 1 for the DOZE<1:0> bits, from 1 to 0 for the
FRCDIV<0> bit, and from 0 to 1 for the PLLPOST<0> bit; Updated the default
definitions for the DOZE<2:0> and FRCDIV<2:0> bits and updated all bit definitions
for the PLLPOST<1:0> bits in the Clock Divisor Register (see Register 9-2).
Changed the POR value from 0 to 1 for the PLLDIV<5:4> bits and updated the default
definitions for all PLLDIV<8:0> bits in the PLL Feedback Division Register (see
Register 9-2).
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Updated the bit definitions for the IRNG<1:0> bits in the CTMU Current Control
Register (see Register 22-3).
Section 25.0 “Op amp/
Comparator Module”
Updated the voltage reference block diagrams (see Figure 25-1 and Figure 25-2).
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 504 2011-2013 Microchip Technology Inc.
Section 30.0 “Electrical
Characteristics”
Removed Voltage on VCAP with respect to Vss and added Note 5 in Absolute
Maximum Ratings(1).
Removed parameter DC18 (VCORE) and Note 3 from the DC Temperature and
Voltage Specifications (see Table 30-4).
Updated Note 1 in the DC Characteristics: Operating Current (IDD) (see Table 30-6).
Updated Note 1 in the DC Characteristics: Idle Current (IIDLE) (see Table 30-7).
Changed the Typical values for parameters DC60a-DC60d and updated Note 1 in the
DC Characteristics: Power-down Current (IPD) (see Table 30-8).
Updated Note 1 in the DC Characteristics: Doze Current (IDOZE) (see Table 30-9).
Updated Note 2 in the Electrical Characteristics: BOR (see Table 30-12).
Updated parameters CM20 and CM31, and added parameters CM44 and CM45 in
the AC/DC Characteristics: Op amp/Comparator (see Table 30-14).
Added the Op amp/Comparator Reference Voltage Settling Time Specifications (see
Table 30-15).
Added Op amp/Comparator Voltage Reference DC Specifications (see Table 30-16).
Updated Internal FRC Accuracy parameter F20a (see Table 30-21).
Updated the Typical value and Units for parameter CTMUI1, and added parameters
CTMUI4, CTMUFV1, and CTMUFV2 to the CTMU Current Source Specifications (see
Table 30-55).
Section 31.0 “Packaging
Information”
Updated packages by replacing references of VLAP with TLA.
“Product Identification
System”
Changed VLAP to TLA.
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
2011-2013 Microchip Technology Inc. DS70657G-page 505
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Revision C (December 2011)
This revision includes typographical and formatting
changes throughout the data sheet text.
In addition, where applicable, new sections were added
to each peripheral chapter that provide information and
links to related resources, as well as helpful tips. For
examples, see Section 20.1 “UART Helpful Tips”
and Section 3.6 “CPU Resources”.
All occurrences of TLA were updated to VTLA
throughout the document, with the exception of the pin
diagrams (updated diagrams were not available at time
of publication).
A new chapter, Section 31.0 “DC and AC Device
Characteristics Graphs”, was added.
All other major changes are referenced by their
respective section in Tabl e A - 2.
TABLE A-2: MAJOR SECTION UPDATES
Section Name Update Description
“16-bit Microcontrollers
and Digital Signal
Controllers (up to 256 KB
Flash and 32 KB SRAM)
with High-Speed PWM, Op
amps, and Advanced
Analog”
The content on the first page of this section was extensively reworked to provide the
reader with the key features and functionality of this device family in an “at-a-glance”
format.
Section 1.0 “Device
Overview”
Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and
PIC24EPXXXGP/MC20X Block Diagram (see Figure 1-1), which now contains a CPU
block and a reference to the CPU diagram.
Updated the description and Note references in the Pinout I/O Descriptions for these
pins: C1IN2-, C2IN2-, C3IN2-, OA1OUT, OA2OUT, and OA3OUT (see Table 1-1).
Section 2.0 “Guidelines for
Getting Started with 16-bit
Digital Signal Controllers
and Microcontrollers”
Updated the Recommended Minimum Connection diagram (see Figure 2-1).
Section 3.0 “CPU” Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and
PIC24EPXXXGP/MC20X CPU Block Diagram (see Figure 3-1).
Updated the Status register definition in the Programmer’s Model (see Figure 3-2).
Section 4.0 “Memory
Organization”
Updated the Data Memory Maps (see Figure 4-6 and Figure 4-11).
Removed the DCB<1:0> bits from the OC1CON2, OC2CON2, OC3CON2, and
OC4CON2 registers in the Output Compare 1 Through Output Compare 4 Register
Map (see Table 4-10).
Added the TRIG1 and TRGCON1 registers to the PWM1 Generator 1 Register Map
(see Table 4-13).
Added the TRIG2 and TRGCON2 registers to the PWM1 Generator 1 Register Map
(see Table 4-14).
Added the TRIG3 and TRGCON3 registers to the PWM1 Generator 1 Register Map
(see Table 4-15).
Updated the second note in Section 4.7.1 “Bit-Reversed Addressing
Implementation”.
Section 8.0 “Direct Memory
Access (DMA)”
Updated the DMA Controller diagram (see Figure 8-1).
Section 14.0 “Input
Capture”
Updated the bit values for the ICx clock source of the ICTSEL<12:10> bits in the
ICxCON1 register (see Register 14-1).
Section 15.0 “Output
Compare”
Updated the bit values for the OCx clock source of the OCTSEL<2:0> bits in the
OCxCON1 register (see Register 15-1).
Removed the DCB<1:0> bits from the Output Compare x Control Register 2 (see
Register 15-2).
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 506 2011-2013 Microchip Technology Inc.
Section 16.0 “High-Speed
PWM Module
(dsPIC33EPXXXMC20X/50X
and PIC24EPXXXMC20X
Devices Only)”
Updated the High-Speed PWM Module Register Interconnection Diagram (see
Figure 16-2).
Added the TRGCONx and TRIGx registers (see Register 16-12 and Register 16-14,
respectively).
Section 21.0 “Enhanced
CAN (ECAN™) Module
(dsPIC33EPXXXGP/MC50X
Devices Only)”
Updated the CANCKS bit value definitions in CiCTRL1: ECAN Control Register 1
(see Register 21-1).
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Updated the IRNG<1:0> bit value definitions and added Note 2 in the CTMU Current
Control Register (see Register 22-3).
Section 25.0 “Op amp/
Comparator Module”
Updated the Op amp/Comparator I/O Operating Modes Diagram (see Figure 25-1).
Updated the User-programmable Blanking Function Block Diagram (see Figure 25-3).
Updated the Digital Filter Interconnect Block Diagram (see Figure 25-4).
Added Section 25.1 “Op amp Application Considerations”.
Added Note 2 to the Comparator Control Register (see Register 25-2).
Updated the bit definitions in the Comparator Mask Gating Control Register (see
Register 25-5).
Section 27.0 “Special
Features”
Updated the FICD Configuration Register, updated Note 1, and added Note 3 in the
Configuration Byte Register Map (see Table 27-1).
Added Section 27.2 “User ID Words”.
Section 30.0 “Electrical
Characteristics”
Updated the following Absolute Maximum Ratings:
• Maximum current out of VSS pin
• Maximum current into VDD pin
Added Note 1 to the Operating MIPS vs. Voltage (see Table 30-1).
Updated all Idle Current (IIDLE) Typical and Maximum DC Characteristics values (see
Table 30-7).
Updated all Doze Current (IDOZE) Typical and Maximum DC Characteristics values
(see Table 30-9).
Added Note 2, removed parameter CM24, updated the Typical values parameters
CM10, CM20, CM21, CM32, CM41, CM44, and CM45, and updated the Minimum
values for CM40 and CM41, and the Maximum value for CM40 in the AC/DC
Characteristics: Op amp/Comparator (see Table 30-14).
Updated Note 2 and the Typical value for parameter VR310 in the Op amp/
Comparator Reference Voltage Settling Time Specifications (see Table 30-15).
Added Note 1, removed parameter VRD312, and added parameter VRD314 to the
Op amp/Comparator Voltage Reference DC Specifications (see Table 30-16).
Updated the Minimum, Typical, and Maximum values for Internal LPRC Accuracy
(see Table 30-22).
Updated the Minimum, Typical, and Maximum values for parameter SY37 in the
Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing
Requirements (see Table 30-24).
The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock
Rate Summary (see Table 30-35)
TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
2011-2013 Microchip Technology Inc. DS70657G-page 507
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Section 30.0 “Electrical
Characteristics”
(Continued)
These SPI2 Timing Requirements were updated:
• Maximum value for parameter SP10 and the minimum clock period value for
SCKx in Note 3 (see Table 30-36, Table 30-37, and Table 30-38)
• Maximum value for parameter SP70 and the minimum clock period value for
SCKx in Note 3 (see Table 30-40 and Table 30-42)
• The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock
Rate Summary (see Table 30-43)
These SPI1 Timing Requirements were updated:
• Maximum value for parameters SP10 and the minimum clock period value for
SCKx in Note 3 (see Table 30-44, Table 30-45, and Table 30-46)
• Maximum value for parameters SP70 and the minimum clock period value for
SCKx in Note 3 (see Table 30-47 through Table 30-50)
• Minimum value for parameters SP40 and SP41 see Table 30-44 through
Table 30-50)
Updated all Typical values for the CTMU Current Source Specifications (see
Table 30-55).
Updated Note1, the Maximum value for parameter AD06, the Minimum value for
AD07, and the Typical values for AD09 in the ADC Module Specifications (see
Table 30-56).
Added Note 1 to the ADC Module Specifications (12-bit Mode) (see Table 30-57).
Added Note 1 to the ADC Module Specifications (10-bit Mode) (see Table 30-58).
Updated the Minimum and Maximum values for parameter AD21b in the 10-bit Mode
ADC Module Specifications (see Table 30-58).
Updated Note 2 in the ADC Conversion (12-bit Mode) Timing Requirements (see
Table 30-59).
Updated Note 1 in the ADC Conversion (10-bit Mode) Timing Requirements (see
Table 30-60).
TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 508 2011-2013 Microchip Technology Inc.
Revision D (December 2011)
This revision includes typographical and formatting
changes throughout the data sheet text.
All other major changes are referenced by their
respective section in Tab le A-3 .
TABLE A-3: MAJOR SECTION UPDATES
Section Name Update Description
“16-bit Microcontrollers
and Digital Signal
Controllers (up to 512 KB
Flash and 48 KB SRAM)
with High-Speed PWM, Op
amps, and Advanced
Analog”
Removed the Analog Comparators column and updated the Op amps/Comparators
column in Table 1 and Table 2.
Section 21.0 “Enhanced
CAN (ECAN™) Module
(dsPIC33EPXXXGP/MC50X
Devices Only)”
Updated the CANCKS bit value definitions in CiCTRL1: ECAN Control Register 1
(see Register 21-1).
Section 30.0 “Electrical
Characteristics”
Updated the VBOR specifications and/or its related note in the following electrical
characteristics tables:
•Table30-1
•Table30-4
•Table30-12
•Table30-14
•Table30-15
•Table30-16
•Table30-56
•Table30-57
•Table30-58
•Table30-59
•Table30-60
2011-2013 Microchip Technology Inc. DS70657G-page 509
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Revision E (April 2012)
This revision includes typographical and formatting
changes throughout the data sheet text.
All other major changes are referenced by their
respective section in Tab le A-3 .
TABLE A-4: MAJOR SECTION UPDATES
Section Name Update Description
“16-bit Microcontrollers
and Digital Signal
Controllers (up to 512 KB
Flash and 48 KB SRAM)
with High-Speed PWM, Op
amps, and Advanced
Analog”
The following 512 KB devices were added to the General Purpose Families table (see
Tab l e 1 ):
• PIC24EP512GP202
• PIC24EP512GP204
• PIC24EP512GP206
• dsPIC33EP512GP502
• dsPIC33EP512GP504
• dsPIC33EP512GP506
The following 512 KB devices were added to the Motor Control Families table (see
Tab l e 2 ):
• PIC24EP512MC202
• PIC24EP512MC204
• PIC24EP512MC206
• dsPIC33EP512MC202
• dsPIC33EP512MC204
• dsPIC33EP512MC206
• dsPIC33EP512MC502
• dsPIC33EP512MC504
• dsPIC33EP512MC506
Certain Pin Diagrams were updated to include the new 512 KB devices.
Section 4.0 “Memory
Organization”
Added a Program Memory Map for the new 512 KB devices (see Figure 4-4).
Added a Data Memory Map for the new dsPIC 512 KB devices (see Figure 4-11).
Added a Data Memory Map for the new PIC24 512 KB devices (see Figure 4-16).
Section 7.0 “Interrupt
Controller”
Updated the VECNUM bits in the INTTREG register (see Register 7-7).
Section 11.0 “I/O Ports” Added tip 6 to Section 11.5 “I/O Helpful Tips”.
Section 27.0 “Special
Features”
The following modifications were made to the Configuration Byte Register Map (see
Table 27-1):
• Added the column Device Memory Size (KB)
• Removed Notes 1 through 4
• Added addresses for the new 512 KB devices
Section 30.0 “Electrical
Characteristics”
Updated the Minimum value for parameter DC10 (see Table 30-4).
Added Power-Down Current (Ipd) parameters for the new 512 KB devices (see
Table 30-8).
Updated the Minimum value for parameter CM34 (see Table 30-53).
Updated the Minimum and Maximum values and the Conditions for paramteer SY12
(see Table 30-22).
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 510 2011-2013 Microchip Technology Inc.
Revision F (November 2012)
Removed “Preliminary” from data sheet footer.
Revision G (March 2013)
This revision includes the following global changes:
• changes “FLTx” pin function to “FLTx” on all
occurrences
• adds Section 31.0 “High-Temperature Electrical
Characteristics” for high-temperature (+150°C)
data
This revision also includes minor typographical and
formatting changes throughout the text.
Other major changes are referenced by their respective
section in Table A-5.
TABLE A-5: MAJOR SECTION UPDATES
Section Name Update Description
Cover Section • Changes internal oscillator specification to 1.0%
• Changes I/O sink/source values to 12 mA or 6 mA
• Corrects 44-pin VTLA pin diagram (pin 32 now shows as 5V tolerant)
Section 4.0 “Memory
Organization”
• Deletes references to Configuration shadow registers
• Corrects the spelling of the JTAGIP and PTGWDTIP bits throughout
• Corrects the Reset value of all IOCON registers as C000h
• Adds footnote to Ta b l e 4 - 4 2 to indicate the absence of Comparator 3 in 28-pin
devices
Section 6.0 “Resets” • Removes references to cold and warm Resets, and clarifies the initial configuration of
the device clock source on all Resets
Section 7.0 “Interrupt
Controller”
• Corrects the definition of GIE as “Global Interrupt Enable” (not “General”)
Section 9.0 “Oscillator
Configuration”
• Clarifies the behavior of the CF bit when cleared in software
• Removes POR behavior footnotes from all control registers
• Corrects the tuning range of the TUN<5:0> bits in Register 9-4 to an overall range
±1.5%
Section 13.0 “Timer2/3 and
Timer4/5”
• Clarifies the presence of the ADC Trigger in 16-bit Timer3 and Timer5, as well as the
32-bit timers
Section 15.0 “Output
Compare”
• Corrects the first trigger source for SYNCSEL<4:0> (OCxCON2<4:0>) as OCxRS
match
Section 16.0 “High-Speed
PWM Module”
• Clarifies the source of the PWM interrupts in Figure 16-1
• Corrects the Reset states of IOCONx<15:14> in Register 16-13 as ‘11’
Section 17.0 “Quadrature
Encoder Interface (QEI)
Module”
• Clarifies the operation of the IMV<1:0> bits (QEICON<9:8>) with updated text and
additional notes
• Corrects the first prescaler value for QFVDIV<2:0> (QEI1OC<13:11>), now 1:128
Section 23.0 “10-Bit/12-Bit
Analog-to-Digital Converter
(ADC)”
• Adds note to Figure 23-1 that Op Amp 3 is not available in 28-pin devices
• Changes “sample clock” to “sample trigger” in AD1CON1 (Register 23-1)
• Clarifies footnotes on op amp usage in Registers 23-5 and 23-6
Section 25.0 “Op Amp/
Comparator Module”
• Adds Note text to indicate that Comparator 3 is unavailable in 28-pin devices
• Splits Figure 25-1 into two figures for clearer presentation (Figure 25-1 for Op amp/
Comparators 1 through 3, Figure 25-2 for Comparator 4). Subsequent figures are
renumbered accordingly.
• Corrects reference description in xxxxx (now (AVDD+AVSS)/2)
• Changes CMSTAT<15> in Register 25-1 to “PSIDL”
Section 27.0 “Special
Features”
• Corrects the addresses of all Configuration bytes for 512 Kbyte devices
2011-2013 Microchip Technology Inc. DS70657G-page 511
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Section 30.0 “Electrical
Characteristics”
• Throughout: qualifies all footnotes relating to the operation of analog modules below
VDDMIN (replaces “will have” with “may have”)
• Throughout: changes all references of SPI timing parameter symbol “TscP” to “FscP”
•Table 30-1: changes VDD range to 3.0V to 3.6V
•Table 30-4: removes parameter DC12 (Ram Retention Voltage)
•Table 30-7: updates Maximum values at 10 and 20 MIPS
•Table 30-8: adds Maximum IPD values, and removes all IWDT entries
• Adds new Ta b le 3 0 - 9 (Watchdog Timer Delta Current) with consolidated values
removed from Ta b l e 3 0 -8 . All subsequent tabes are renumbered accordingly.
•Table 30-10: adds footnote for all parameters for 1:2 Doze ratio
•Table 30-11:
- changes Minimum and Maximum values for D120 and D130
- adds Minimum and Maximum values for D131
- adds Minimum and Maximum values for D150 through D156, and removes
Typical values
•Table 30-12:
- reformats table for readability
- changes IOL conditions for DO10
•Table 30-14: adds footnote to D135
•Table 30-17: changes Minimum and Maximum values for OS30
•Table 30-19:
- splits temperature range and adds new values for F20a
- reduces temperature range for F20b to extended temperatures only
•Table 30-20:
- splits temperature range and adds new values for F21a
- reduces temperature range for F20b to extended temperatures only
•Table 30-53:
- adds Maximum value to CM30
- adds footnote (“Parameter characterized...”) to multiple parameters
•Table 30-55: adds Minimum and Maximum values for all CTMUI specifications, and
removes Typical values
•Table 30-57: adds new footnote to AD09
•Table 30-58:
- removes all specifications for accuracy with external voltage references
- removes Typical values for AD23a and AD24a
- replaces Minimum and Maximum values for AD21a, AD22a, AD23a and AD24a
with new values, split by Industrial and Extended temperatures
- removes Maximum value of AD30
- removes Minimum values from AD31a and AD32a
- adds or changes Typical values for AD30, AD31a, AD32a and AD33a
•Table 30-59:
- removes all specifications for accuracy with external voltage references
- removes Maximum value of AD30
- removes Typical values for AD23b and AD24b
- replaces Minimum and Maximum values for AD21b, AD22b, AD23b and AD24b
with new values, split by Industrial and Extended temperatures
- removes Minimum and Maximum values from AD31b, AD32b, AD33b and AD34b
- adds or changes Typical values for AD30, AD31a, AD32a and AD33a
•Table 30-61: Adds footnote to AD51
Section 32.0 “DC and AC
Device Characteristics
Graphs”
• Updates Figure 32-8 (Typical IDD @ 3.3V) with individual current vs. processor speed
curves for the different program memory sizes
Section 33.0 “Packaging
Information”
• Replaces drawing C04-149C (64-pin QFN, 7.15 x 7.15 exposed pad) with C04-154A
(64-pin QFN, 5.4 x 5.4 exposed pad)
TABLE A-5: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 512 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 513
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
INDEX
A
Absolute Maximum Ratings .............................................. 399
AC Characteristics .................................................... 411, 469
ADC Module.............................................................. 457
ADC Module (10-Bit Mode)............................... 459, 471
ADC Module (12-Bit Mode)............................... 458, 471
Capacitive Loading Requirements on
Output Pins ....................................................... 411
Internal FRC Accuracy.............................................. 413
Internal LPRC Accuracy............................................ 413
Load Conditions ................................................ 411, 469
Op Amp/Comparator Voltage Reference
Settling Time Specifications.............................. 455
SPI1 Maximum Data/Clock Rate Summary .............. 436
SPI2 Maximum Data Clock Rate Summary .............. 424
ADC
Control Registers ...................................................... 323
Helpful Tips ............................................................... 322
Key Features............................................................. 319
Resources................................................................. 322
Arithmetic Logic Unit (ALU)................................................. 42
Assembler
MPASM Assembler................................................... 396
B
Bit-Reversed Addressing .................................................. 113
Example .................................................................... 114
Implementation ......................................................... 113
Sequence Table (16-Entry)....................................... 114
Block Diagrams
16-Bit Timer1 Module................................................ 201
ADC Conversion Clock Period.................................. 321
ADC with Connection Options for ANx Pins
and Op Amps.................................................... 320
Arbiter Architecture ................................................... 108
Comparator (Module 4)............................................. 354
Connections for On-Chip Voltage Regulator............. 382
CPU Core.................................................................... 34
CRC Module ............................................................. 371
CRC Shift Engine...................................................... 372
CTMU Module........................................................... 314
Digital Filter Interconnect .......................................... 355
DMA Controller ......................................................... 139
DMA Module ............................................................. 137
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X............................. 23
ECAN Module ........................................................... 286
High-Speed PWMx Architectural Overview .............. 225
High-Speed PWMx Register Interconnection ........... 226
I2Cx Module.............................................................. 272
Input Capture x ......................................................... 211
Multiplexing Remappable Output for RPn................. 178
Op Amp Configuration A........................................... 356
Op Amp Configuration B........................................... 357
Op Amp/Comparator (Modules 1, 2, 3)..................... 353
Op Amp/Comparator Voltage Reference Module ..... 354
Oscillator System...................................................... 151
Output Compare x Module........................................ 217
PLL............................................................................ 152
PTG Module.............................................................. 336
Quadrature Encoder Interface .................................. 248
Remappable Input for U1RX..................................... 174
Reset System............................................................ 121
Shared Port Structure............................................... 171
SPIx Module ............................................................. 264
Type B Timer (Timer2 and Timer4) .......................... 206
Type B/Type C Timer Pair (32-Bit Timer) ................. 207
Type C Timer (Timer3 and Timer5) .......................... 206
UARTx Module ......................................................... 279
User-Programmable Blanking Function.................... 355
Watchdog Timer (WDT)............................................ 383
Brown-out Reset (BOR).................................................... 382
C
C Compilers
MPLAB C18.............................................................. 396
Charge Time Measurement Unit. See CTMU.
Code Examples
IC1 Connection to QEI1 Input on Pin 43
of dsPIC33EPXXXMC206 ................................ 174
Port Write/Read ........................................................ 172
PWMx Write-Protected Register
Unlock Sequence ............................................. 224
PWRSAV Instruction Syntax .................................... 161
Code Protection........................................................ 377, 384
CodeGuard Security ................................................. 377, 384
Configuration Bits ............................................................. 377
Description................................................................ 379
Configuration Byte Register Map...................................... 378
Configuring Analog and Digital Port Pins.......................... 172
CPU
Clocking System Options ......................................... 152
Fast RC (FRC) Oscillator.................................. 152
FRC Oscillator with PLL ................................... 152
FRC Oscillator with Postscaler......................... 152
Low-Power RC (LPRC) Oscillator .................... 152
Primary (XT, HS, EC) Oscillator ....................... 152
Primary Oscillator with PLL .............................. 152
Control Register.......................................................... 38
Control Registers........................................................ 38
Resources .................................................................. 37
CTMU
Control Registers...................................................... 315
Resources ................................................................ 314
Customer Change Notification Service............................. 520
Customer Notification Service .......................................... 520
Customer Support............................................................. 520
D
Data Address Space........................................................... 49
Memory Map for dsPIC33EP128MC20X/50X,
dsPIC33EP128GP50X Devices.......................... 52
Memory Map for dsPIC33EP256MC20X/50X,
dsPIC33EP256GP50X Devices.......................... 53
Memory Map for dsPIC33EP32MC20X/50X,
dsPIC33EP32GP50X Devices............................ 50
Memory Map for dsPIC33EP512MC20X/50X,
dsPIC33EP512GP50X Devices.......................... 54
Memory Map for dsPIC33EP64MC20X/50X,
dsPIC33EP64GP50X Devices............................ 51
Memory Map for PIC24EP128GP/MC20X/50X
Devices............................................................... 57
Memory Map for PIC24EP256GP/MC20X/50X
Devices............................................................... 58
Memory Map for PIC24EP32GP/MC20X/50X
Devices............................................................... 55
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 514 2011-2013 Microchip Technology Inc.
Memory Map for PIC24EP512GP/MC20X/50X
Devices ............................................................... 59
Memory Map for PIC24EP64GP/MC20X/50X
Devices ............................................................... 56
Near Data Space ........................................................ 49
Organization, Alignment..............................................49
SFR Space.................................................................. 49
Width........................................................................... 49
Data Memory
Arbitration and Bus Master Priority ........................... 108
Data Space
Extended X ............................................................... 107
Paged Memory Scheme ........................................... 103
DC and AC Characteristics
Graphs and Tables ................................................... 473
DC Characteristics
BOR .......................................................................... 409
Doze Current (IDOZE) ........................................ 405, 467
High Temperature ..................................................... 466
I/O Pin Input Specifications....................................... 406
I/O Pin Output Specifications ............................ 409, 468
Idle Current (IIDLE) .................................................... 403
Operating Current (IDD)..................................... 402, 467
Operating MIPS vs. Voltage.............................. 400, 466
Power-Down Current (IPD) ................................ 404, 467
Program Memory ...................................................... 410
Temperature and Voltage ......................................... 466
Temperature and Voltage Specifications .................. 401
Thermal Operating Conditions .................................. 466
Watchdog Timer Delta Current ................................. 405
Development Support ....................................................... 395
DMA Controller
Channel to Peripheral Associations .......................... 138
Control Registers ...................................................... 139
DMAxCNT......................................................... 139
DMAxCON ........................................................ 139
DMAxPAD......................................................... 139
DMAxREQ ........................................................ 139
DMAxSTA ......................................................... 139
DMAxSTB ......................................................... 139
Resources................................................................. 139
Supported Peripherals .............................................. 137
Doze Mode........................................................................163
DSP Engine.........................................................................42
E
ECAN Message Buffers
Word 0 ......................................................................308
Word 1 ......................................................................308
Word 2 ......................................................................309
Word 3 ......................................................................309
Word 4 ......................................................................310
Word 5 ......................................................................310
Word 6 ......................................................................311
Word 7 ......................................................................311
ECAN Module
Control Registers ...................................................... 288
Modes of Operation .................................................. 287
Overview ................................................................... 285
Resources................................................................. 287
Electrical Characteristics...................................................399
AC ..................................................................... 411, 469
Enhanced CAN Module .................................................... 285
Equations
Device Operating Frequency .................................... 152
FOSC Calculation ...................................................... 152
FVCO Calculation ...................................................... 152
Errata .................................................................................. 20
F
Filter Capacitor (CEFC) Specifications .............................. 401
Flash Program Memory .................................................... 117
Control Registers...................................................... 118
Operations ................................................................ 118
Programming Algorithm............................................ 120
Resources ................................................................ 118
RTSP Operation ....................................................... 118
Table Instructions ..................................................... 117
Flexible Configuration ....................................................... 377
H
High-Speed PWM ............................................................. 223
Control Registers...................................................... 228
Faults........................................................................ 223
Resources ................................................................ 227
High-Temperature Electrical Characteristics .................... 465
Absolute Maximum Ratings ...................................... 465
I
I/O Ports............................................................................ 171
Helpful Tips............................................................... 179
Parallel I/O (PIO) ...................................................... 171
Resources ................................................................ 180
Write/Read Timing.................................................... 172
In-Circuit Debugger........................................................... 384
In-Circuit Emulation .......................................................... 377
In-Circuit Serial Programming (ICSP)....................... 377, 384
Input Capture.................................................................... 211
Control Registers...................................................... 213
Resources ................................................................ 212
Input Change Notification (ICN)........................................ 172
Instruction Addressing Modes .......................................... 110
File Register Instructions .......................................... 110
Fundamental Modes Supported ............................... 110
MAC Instructions ...................................................... 111
MCU Instructions ...................................................... 110
Move and Accumulator Instructions.......................... 111
Other Instructions ..................................................... 111
Instruction Set
Summary
Overview........................................................... 388
Instruction Set Summary .................................................. 385
Symbols Used in Opcode Descriptions .................... 386
Inter-Integrated Circuit (I2C) ............................................. 271
Control Registers...................................................... 274
Resources ................................................................ 273
Internal RC Oscillator
Use with WDT........................................................... 383
Internet Address ............................................................... 520
2011-2013 Microchip Technology Inc. DS70657G-page 515
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Interrupt Controller
Control and Status Registers .................................... 129
INTCON1 .......................................................... 129
INTCON2 .......................................................... 129
INTCON3 .......................................................... 129
INTCON4 .......................................................... 129
INTTREG .......................................................... 129
Interrupt Vector Details ............................................. 127
Interrupt Vector Table (IVT) ...................................... 125
Reset Sequence ....................................................... 125
Resources................................................................. 129
J
JTAG Boundary Scan Interface ........................................ 377
JTAG Interface.................................................................. 384
M
Memory Maps
Extended Data Space ............................................... 107
Memory Organization.......................................................... 43
Resources................................................................... 60
Microchip Internet Web Site.............................................. 520
Modulo Addressing ........................................................... 112
Applicability ............................................................... 113
Operation Example ................................................... 112
Start and End Address.............................................. 112
W Address Register Selection .................................. 112
MPLAB ASM30 Assembler, Linker, Librarian ................... 396
MPLAB Integrated Development
Environment Software............................................... 395
MPLAB PM3 Device Programmer .................................... 398
MPLAB REAL ICE In-Circuit Emulator System................. 397
MPLINK Object Linker/MPLIB Object Librarian ................ 396
O
Op Amp
Application Considerations ....................................... 356
Configuration A ................................................. 356
Configuration B ................................................. 357
Op Amp/Comparator......................................................... 353
Control Registers ...................................................... 358
Resources................................................................. 357
Open-Drain Configuration ................................................. 172
Oscillator
Control Registers ...................................................... 154
Resources................................................................. 153
Output Compare ............................................................... 217
Control Registers ...................................................... 219
Resources................................................................. 218
P
Packaging ......................................................................... 477
Details ....................................................................... 500
Marking ............................................................. 477, 479
Peripheral Module Disable (PMD) .................................... 163
Peripheral Pin Select (PPS).............................................. 173
Available Peripherals ................................................ 173
Available Pins ........................................................... 173
Control ...................................................................... 173
Control Registers ...................................................... 181
Input Mapping ........................................................... 174
Output Selection for Remappable Pins..................... 178
Pin Selection for Selectable Input Sources............... 176
Selectable Input Sources .......................................... 175
Peripheral Trigger Generator (PTG) Module .................... 335
Pinout I/O Descriptions (table) ............................................ 24
Power-Saving Features .................................................... 161
Clock Frequency....................................................... 161
Clock Switching ........................................................ 161
Instruction-Based Modes .......................................... 161
Idle.................................................................... 162
Interrupts Coincident with Power Save
Instructions ............................................... 162
Sleep ................................................................ 162
Resources ................................................................ 163
Program Address Space..................................................... 43
Construction ............................................................. 115
Data Access from Program Memory Using
Table Instructions ............................................. 116
Data Access from, Address Generation ................... 115
Memory Map (dsPIC33EP128GP50X,
dsPIC33EP128MC20X/50X,
PIC24EP128GP/MC20X Devices).......................... 45
Memory Map (dsPIC33EP256GP50X,
dsPIC33EP256MC20X/50X,
PIC24EP256GP/MC20X Devices).......................... 46
Memory Map (dsPIC33EP32GP50X,
dsPIC33EP32MC20X/50X,
PIC24EP32GP/MC20X Devices)............................ 43
Memory Map (dsPIC33EP512GP50X,
dsPIC33EP512MC20X/50X,
PIC24EP512GP/MC20X Devices).......................... 47
Memory Map (dsPIC33EP64GP50X,
dsPIC33EP64MC20X/50X,
PIC24EP64GP/MC20X Devices)............................ 44
Table Read High Instructions
TBLRDH ........................................................... 116
Table Read Low Instructions (TBLRDL)................... 116
Program Memory
Organization ............................................................... 48
Reset Vector............................................................... 48
Programmable CRC Generator ........................................ 371
Control Registers...................................................... 373
Overview................................................................... 372
Resources ................................................................ 372
Programmer’s Model .......................................................... 35
Register Description ................................................... 35
PTG
Control Registers...................................................... 338
Introduction............................................................... 335
Output Descriptions .................................................. 351
Resources ................................................................ 337
Step Commands and Format ................................... 348
Q
QEI
Control Registers...................................................... 250
Resources ................................................................ 249
Quadrature Encoder Interface (QEI)................................. 247
R
Reader Response............................................................. 521
Register Maps
ADC1 .......................................................................... 82
CPU Core (dsPIC33EPXXXMC20X/50X,
dsPIC33EPXXXGP50X Devices) ....................... 61
CPU Core (PIC24EPXXXGP/MC20X Devices).......... 63
CRC............................................................................ 86
CTMU ......................................................................... 95
DMAC ......................................................................... 96
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 516 2011-2013 Microchip Technology Inc.
ECAN1 (When WIN (C1CTRL) = 0 or 1)
for dsPIC33EPXXXMC/GP50X Devices ............. 83
ECAN1 (When WIN (C1CTRL) = 0)
for dsPIC33EPXXXMC/GP50X Devices ............. 83
ECAN1 (WIN (C1CTRL) = 1) for
dsPIC33EPXXXMC/GP50X Devices .................. 84
I2C1 and I2C2............................................................. 80
Input Capture 1 through Input Capture 4 .................... 74
Interrupt Controller
(dsPIC33EPXXXGP50X Devices) ...................... 67
Interrupt Controller
(dsPIC33EPXXXMC20X Devices) ...................... 69
Interrupt Controller
(dsPIC33EPXXXMC50X Devices) ...................... 71
Interrupt Controller
(PIC24EPXXXGP20X Devices) .......................... 64
Interrupt Controller
(PIC24EPXXXMC20X Devices).......................... 65
JTAG Interface............................................................ 95
NVM ............................................................................ 91
Op Amp/Comparator...................................................95
Output Compare 1 through Output Compare 4........... 75
Peripheral Pin Select Input
(dsPIC33EPXXXGP50X Devices) ...................... 89
Peripheral Pin Select Input
(dsPIC33EPXXXMC20X Devices) ...................... 90
Peripheral Pin Select Input
(dsPIC33EPXXXMC50X Devices) ...................... 89
Peripheral Pin Select Input
(PIC24EPXXXGP20X Devices) .......................... 88
Peripheral Pin Select Input
(PIC24EPXXXMC20X Devices).......................... 88
Peripheral Pin Select Output
(dsPIC33EPXXXGP/MC202/502,
PIC24EPXXXGP/MC202 Devices) ..................... 86
Peripheral Pin Select Output
(dsPIC33EPXXXGP/MC203/503,
PIC24EPXXXGP/MC203 Devices) ..................... 86
Peripheral Pin Select Output
(dsPIC33EPXXXGP/MC204/504,
PIC24EPXXXGP/MC204 Devices) ..................... 87
Peripheral Pin Select Output
(dsPIC33EPXXXGP/MC206/506,
PIC24EPXXGP/MC206 Devices)........................ 87
PMD (dsPIC33EPXXXGP50X Devices) ..................... 93
PMD (dsPIC33EPXXXMC20X Devices) ..................... 94
PMD (dsPIC33EPXXXMC50X Devices) ..................... 93
PMD (PIC24EPXXXGP20X Devices) ......................... 92
PMD (PIC24EPXXXMC20X Devices)......................... 92
PORTA (PIC24EPXXXGP/MC202,
dsPIC33EPXXXGP/MC202/502 Devices) ........ 102
PORTA (PIC24EPXXXGP/MC203,
dsPIC33EPXXXGP/MC203/503 Devices) ........ 101
PORTA (PIC24EPXXXGP/MC204,
dsPIC33EPXXXGP/MC204/504 Devices) ........ 100
PORTA (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) .......... 97
PORTB (PIC24EPXXXGP/MC202,
dsPIC33EPXXXGP/MC202/502 Devices) ........ 102
PORTB (PIC24EPXXXGP/MC203,
dsPIC33EPXXXGP/MC203/503 Devices) ........ 101
PORTB (PIC24EPXXXGP/MC204,
dsPIC33EPXXXGP/MC204/504 Devices) ........ 100
PORTB (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) .......... 97
PORTC (PIC23EPXXXGP/MC203,
dsPIC33EPXXXGP/MC203/503 Devices) ........ 101
PORTC (PIC24EPXXXGP/MC204,
dsPIC33EPXXXGP/MC204/504 Devices) ........ 100
PORTC (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) .......... 97
PORTD (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) .......... 98
PORTE (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) .......... 98
PORTF (PIC24EPXXXGP/MC206,
dsPIC33EPXXXGP/MC206/506 Devices) .......... 98
PORTG (PIC24EPXXXGP/MC206 and
dsPIC33EPXXXGP/MC206/506 Devices) .......... 99
PTG ............................................................................ 76
PWM (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices)........................... 77
PWM Generator 1 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices)........................... 77
PWM Generator 2 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices)........................... 78
PWM Generator 3 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices)........................... 78
QEI1 (dsPIC33EPXXXMC20X/50X,
PIC24EPXXXMC20X Devices)........................... 79
Reference Clock ......................................................... 91
SPI1 and SPI2 ............................................................ 81
System Control ........................................................... 91
Timer1 through Timer5 ............................................... 73
UART1 and UART2 .................................................... 80
Registers
AD1CHS0 (ADC1 Input Channel 0 Select)............... 331
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 329
AD1CON1 (ADC1 Control 1) .................................... 323
AD1CON2 (ADC1 Control 2) .................................... 325
AD1CON3 (ADC1 Control 3) .................................... 327
AD1CON4 (ADC1 Control 4) .................................... 328
AD1CSSH (ADC1 Input Scan Select High) .............. 333
AD1CSSL (ADC1 Input Scan Select Low)................ 334
ALTDTRx (PWMx Alternate Dead-Time).................. 236
AUXCONx (PWMx Auxiliary Control) ....................... 245
CHOP (PWMx Chop Clock Generator)..................... 232
CLKDIV (Clock Divisor) ............................................ 156
CM4CON (Comparator 4 Control) ............................ 362
CMSTAT (Op Amp/Comparator Status) ................... 358
CMxCON (Comparator x Control, x = 1,2,3)............. 360
CMxFLTR (Comparator x Filter Control)................... 368
CMxMSKCON (Comparator x Mask
Gating Control) ................................................. 366
CMxMSKSRC (Comparator x Mask
Source Select Control) ..................................... 364
CORCON (Core Control).................................... 40, 131
CRCCON1 (CRC Control 1) ..................................... 373
CRCCON2 (CRC Control 2) ..................................... 374
CRCXORH (CRC XOR Polynomial High)................. 375
CRCXORL (CRC XOR Polynomial Low) .................. 375
CTMUCON1 (CTMU Control 1) ................................ 315
CTMUCON2 (CTMU Control 2) ................................ 316
CTMUICON (CTMU Current Control)....................... 317
CVRCON (Comparator Voltage
Reference Control) ........................................... 369
CxBUFPNT1 (ECANx Filter 0-3 Buffer Pointer 1)..... 298
CxBUFPNT2 (ECANx Filter 4-7 Buffer Pointer 2)..... 299
CxBUFPNT3 (ECANx Filter 8-11 Buffer Pointer 3)... 299
2011-2013 Microchip Technology Inc. DS70657G-page 517
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
CxBUFPNT4 (ECANx Filter 12-15
Buffer Pointer 4)................................................ 300
CxCFG1 (ECANx Baud Rate Configuration 1) ......... 296
CxCFG2 (ECANx Baud Rate Configuration 2) ......... 297
CxCTRL1 (ECANx Control 1) ................................... 288
CxCTRL2 (ECANx Control 2) ................................... 289
CxEC (ECANx Transmit/Receive Error Count)......... 296
CxFCTRL (ECANx FIFO Control)............................. 291
CxFEN1 (ECANx Acceptance Filter Enable 1) ......... 298
CxFIFO (ECANx FIFO Status).................................. 292
CxFMSKSEL1 (ECANx Filter 7-0
Mask Selection) ................................................ 302
CxFMSKSEL2 (ECANx Filter 15-8
Mask Selection) ................................................ 303
CxINTE (ECANx Interrupt Enable)............................ 295
CxINTF (ECANx Interrupt Flag) ................................ 293
CxRXFnEID (ECANx Acceptance Filter n
Extended Identifier)........................................... 302
CxRXFnSID (ECANx Acceptance Filter n
Standard Identifier) ........................................... 301
CxRXFUL1 (ECANx Receive Buffer Full 1) .............. 305
CxRXFUL2 (ECANx Receive Buffer Full 2) .............. 305
CxRXMnEID (ECANx Acceptance Filter Mask n
Extended Identifier)........................................... 304
CxRXMnSID (ECANx Acceptance Filter Mask n
Standard Identifier) ........................................... 304
CxRXOVF1 (ECANx Receive Buffer Overflow 1) ..... 306
CxRXOVF2 (ECANx Receive Buffer Overflow 2) ..... 306
CxTRmnCON (ECANx TX/RX Buffer mn Control).... 307
CxVEC (ECANx Interrupt Code) ............................... 290
DEVID (Device ID) .................................................... 381
DEVREV (Device Revision)...................................... 381
DMALCA (DMA Last Channel Active Status) ........... 148
DMAPPS (DMA Ping-Pong Status) .......................... 149
DMAPWC (DMA Peripheral Write
Collision Status)................................................ 146
DMARQC (DMA Request Collision Status) .............. 147
DMAxCNT (DMA Channel x Transfer Count) ........... 144
DMAxCON (DMA Channel x Control) ....................... 140
DMAxPAD (DMA Channel x Peripheral Address)..... 144
DMAxREQ (DMA Channel x IRQ Select) ................. 141
DMAxSTAH (DMA Channel x
Start Address A, High) ...................................... 142
DMAxSTAL (DMA Channel x
Start Address A, Low)....................................... 142
DMAxSTBH (DMA Channel x
Start Address B, High) ...................................... 143
DMAxSTBL (DMA Channel x Start
Address B, Low) ............................................... 143
DSADRH (DMA Most Recent RAM
High Address) ................................................... 145
DSADRL (DMA Most Recent RAM Low Address) .... 145
DTRx (PWMx Dead-Time) ........................................ 236
FCLCONx (PWMx Fault Current-Limit Control) ........ 241
I2CxCON (I2Cx Control) ........................................... 274
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 278
I2CxSTAT (I2Cx Status) ........................................... 276
ICxCON1 (Input Capture x Control 1)....................... 213
ICxCON2 (Input Capture x Control 2)....................... 214
INDXxCNTH (Index Counter High Word).................. 257
INDXxCNTL (Index Counter Low Word) ................... 257
INDXxHLD (Index Counter Hold) .............................. 258
INTCON1 (Interrupt Control 1).................................. 132
INTCON2 (Interrupt Control 2).................................. 134
INTCON2 (Interrupt Control 3).................................. 135
INTCON4 (Interrupt Control 4) ................................. 135
INTTREG Interrupt Control and Status Register ...... 136
INTxHLDH (Interval Timer Hold High Word) ............ 261
INTxHLDL (Interval Timer Hold Low Word).............. 261
INTxTMRH (Interval Timer High Word) .................... 260
INTxTMRL (Interval Timer Low Word)...................... 261
IOCONx (PWMx I/O Control).................................... 238
LEBCONx (PWMx Leading-Edge
Blanking Control).............................................. 243
LEBDLYx (PWMx Leading-Edge Blanking Delay).... 244
MDC (PWMx Master Duty Cycle)............................. 232
NVMADR (Nonvolatile Memory Lower Address)...... 120
NVMADRU (Nonvolatile Memory Upper Address) ... 120
NVMCON (Nonvolatile Memory (NVM) Control) ...... 119
NVMKEY (Nonvolatile Memory Key) ........................ 120
OCxCON1 (Output Compare x Control 1) ................ 219
OCxCON2 (Output Compare x Control 2) ................ 221
OSCCON (Oscillator Control)................................... 154
OSCTUN (FRC Oscillator Tuning)............................ 159
PDCx (PWMx Generator Duty Cycle)....................... 235
PHASEx (PWMx Primary Phase-Shift)..................... 235
PLLFBD (PLL Feedback Divisor) ............................. 158
PMD1 (Peripheral Module Disable Control 1) .......... 164
PMD2 (Peripheral Module Disable Control 2) .......... 166
PMD3 (Peripheral Module Disable Control 3) .......... 167
PMD4 (Peripheral Module Disable Control 4) .......... 167
PMD6 (Peripheral Module Disable Control 6) .......... 168
PMD7 (Peripheral Module Disable Control 7) .......... 169
POSxCNTH (Position Counter High Word) .............. 256
POSxCNTL (Position Counter Low Word)................ 256
POSxHLD (Position Counter Hold)........................... 256
PTCON (PWMx Time Base Control) ........................ 228
PTCON2 (PWMx Primary Master Clock
Divider Select) .................................................. 230
PTGADJ (PTG Adjust).............................................. 346
PTGBTE (PTG Broadcast Trigger Enable)............... 341
PTGC0LIM (PTG Counter 0 Limit) ........................... 344
PTGC1LIM (PTG Counter 1 Limit) ........................... 345
PTGCON (PTG Control)........................................... 340
PTGCST (PTG Control/Status) ................................ 338
PTGHOLD (PTG Hold)............................................. 345
PTGL0 (PTG Literal 0).............................................. 346
PTGQPTR (PTG Step Queue Pointer)..................... 347
PTGQUEx (PTG Step Queue x)............................... 347
PTGSDLIM (PTG Step Delay Limit) ......................... 344
PTGT0LIM (PTG Timer0 Limit) ................................ 343
PTGT1LIM (PTG Timer1 Limit) ................................ 343
PTPER (PWMx Primary Master Time Base
Period).............................................................. 231
PWMCONx (PWMx Control) .................................... 233
QEI1CON (QEI Control) ........................................... 250
QEI1GECH (Greater Than or Equal Compare
High Word) ....................................................... 260
QEI1GECL (Greater Than or Equal Compare
Low Word) ........................................................ 260
QEI1ICH (Initialization/Capture High Word) ............. 258
QEI1ICL (Initialization/Capture Low Word)............... 258
QEI1IOC (QEI I/O Control) ....................................... 252
QEI1LECH (Less Than or Equal Compare
High Word) ....................................................... 259
QEI1LECL (Less Than or Equal Compare
Low Word) ........................................................ 259
QEI1STAT (QEI Status) ........................................... 254
RCON (Reset Control).............................................. 123
REFOCON (Reference Oscillator Control) ............... 160
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 518 2011-2013 Microchip Technology Inc.
RPINR0 (Peripheral Pin Select Input 0).................... 181
RPINR1 (Peripheral Pin Select Input 1).................... 182
RPINR11 (Peripheral Pin Select Input 11)................ 185
RPINR12 (Peripheral Pin Select Input 12)................ 186
RPINR14 (Peripheral Pin Select Input 14)................ 187
RPINR15 (Peripheral Pin Select Input 15)................ 188
RPINR18 (Peripheral Pin Select Input 18)................ 189
RPINR19 (Peripheral Pin Select Input 19)................ 189
RPINR22 (Peripheral Pin Select Input 22)................ 190
RPINR23 (Peripheral Pin Select Input 23)................ 191
RPINR26 (Peripheral Pin Select Input 26)................ 191
RPINR3 (Peripheral Pin Select Input 3).................... 182
RPINR37 (Peripheral Pin Select Input 37)................ 192
RPINR38 (Peripheral Pin Select Input 38)................ 193
RPINR39 (Peripheral Pin Select Input 39)................ 194
RPINR7 (Peripheral Pin Select Input 7).................... 183
RPINR8 (Peripheral Pin Select Input 8).................... 184
RPOR0 (Peripheral Pin Select Output 0) .................. 195
RPOR1 (Peripheral Pin Select Output 1) .................. 195
RPOR2 (Peripheral Pin Select Output 2) .................. 196
RPOR3 (Peripheral Pin Select Output 3) .................. 196
RPOR4 (Peripheral Pin Select Output 4) .................. 197
RPOR5 (Peripheral Pin Select Output 5) .................. 197
RPOR6 (Peripheral Pin Select Output 6) .................. 198
RPOR7 (Peripheral Pin Select Output 7) .................. 198
RPOR8 (Peripheral Pin Select Output 8) .................. 199
RPOR9 (Peripheral Pin Select Output 9) .................. 199
SEVTCMP (PWMx Primary Special Event
Compare) .......................................................... 231
SPIxCON1 (SPIx Control 1)...................................... 268
SPIxCON2 (SPIx Control 2)...................................... 270
SPIxSTAT (SPIx Status and Control) ....................... 266
SR (CPU STATUS)............................................. 38, 130
T1CON (Timer1 Control)........................................... 203
TRGCONx (PWMx Trigger Control).......................... 237
TRIGx (PWMx Primary Trigger Compare Value) ...... 240
TxCON (Timer2 and Timer4 Control)........................ 208
TyCON (Timer3 and Timer5 Control)........................ 209
UxMODE (UARTx Mode).......................................... 281
UxSTA (UARTx Status and Control)......................... 283
VELxCNT (Velocity Counter) .................................... 257
Resets ............................................................................... 121
Brown-out Reset (BOR) ............................................ 121
Configuration Mismatch Reset (CM).........................121
Illegal Condition Reset (IOPUWR) ............................121
Illegal Opcode ................................................... 121
Security ............................................................. 121
Uninitialized W Register....................................121
Master Clear (MCLR) Pin Reset ............................... 121
Power-on Reset (POR) ............................................. 121
RESET Instruction (SWR)......................................... 121
Resources................................................................. 122
Trap Conflict Reset (TRAPR)....................................121
Watchdog Timer Time-out Reset (WDTO)................ 121
Resources Required for Digital PFC ............................. 30, 32
Revision History ................................................................ 503
S
Serial Peripheral Interface (SPI) ....................................... 263
Software Simulator (MPLAB SIM)..................................... 397
Software Stack Pointer, Frame Pointer
CALL Stack Frame.................................................... 109
Special Features of the CPU............................................. 377
SPI
Control Registers...................................................... 266
Helpful Tips............................................................... 265
Resources ................................................................ 265
T
Temperature and Voltage Specifications
AC..................................................................... 411, 469
Thermal Operating Conditions.......................................... 400
Thermal Packaging Characteristics .................................. 400
Timer1............................................................................... 201
Control Register........................................................ 203
Resources ................................................................ 202
Timer2/3 and Timer4/5 ..................................................... 205
Control Registers...................................................... 208
Resources ................................................................ 207
Timing Diagrams
10-Bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 0, SSRC<2:0> = 000, SSRCG = 0).... 462
10-Bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111, SSRCG = 0,
SAMC<4:0> = 00010)....................................... 462
12-Bit ADC Conversion (ASAM = 0,
SSRC<2:0> = 000, SSRCG = 0) ...................... 460
BOR and Master Clear Reset ................................... 414
ECAN I/O.................................................................. 452
External Clock........................................................... 412
High-Speed PWMx Fault .......................................... 420
High-Speed PWMx Module ...................................... 420
I/O Characteristics .................................................... 414
I2Cx Bus Data (Master Mode) .................................. 448
I2Cx Bus Data (Slave Mode) .................................... 450
I2Cx Bus Start/Stop Bits (Master Mode)................... 448
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 450
Input Capture x (ICx) ................................................ 418
OCx/PWMx............................................................... 419
Output Compare x (OCx).......................................... 419
QEA/QEB Input ........................................................ 422
QEI Module Index Pulse ........................................... 423
SPI1 Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) ........................................... 439
SPI1 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) ........................................... 438
SPI1 Master Mode (Half-Duplex, Transmit Only,
CKE = 0)........................................................... 436
SPI1 Master Mode (Half-Duplex, Transmit Only,
CKE = 1)........................................................... 437
SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ........................................... 446
SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ........................................... 444
SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ........................................... 440
SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ........................................... 442
SPI2 Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) ........................................... 427
SPI2 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) ........................................... 426
SPI2 Master Mode (Half-Duplex, Transmit Only,
CKE = 0)........................................................... 424
SPI2 Master Mode (Half-Duplex, Transmit Only,
CKE = 1)........................................................... 425
2011-2013 Microchip Technology Inc. DS70657G-page 519
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
SPI2 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ........................................... 434
SPI2 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ........................................... 432
SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ........................................... 428
SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ........................................... 430
Timer1-Timer5 External Clock .................................. 416
TimerQ (QEI Module) External Clock ....................... 421
UARTx I/O................................................................. 452
Timing Requirements
DMA Module ............................................................. 463
External Clock........................................................... 412
I/O ............................................................................. 414
Timing Specifications
10-Bit ADC Conversion Requirements ..................... 463
12-Bit ADC Conversion Requirements ..................... 461
CTMU Current Source Requirements....................... 456
ECANx I/O Requirements ......................................... 452
High-Speed PWMx Requirements ............................ 420
I2Cx Bus Data Requirements (Master Mode) ........... 449
I2Cx Bus Data Requirements (Slave Mode) ............. 451
Input Capture x Requirements .................................. 418
OCx/PWMx Mode Requirements.............................. 419
Op Amp/Comparator Requirements ......................... 453
Op Amp/Comparator Voltage Reference
Requirements ................................................... 455
Output Compare x Requirements ............................. 419
PLL Clock.......................................................... 413, 469
QEI External Clock Requirements ............................ 421
QEI Index Pulse Requirements................................. 423
Quadrature Decoder Requirements.......................... 422
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer Requirements......................... 415
SPI1 Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) Requirements .................... 439
SPI1 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements .................... 438
SPI1 Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 437
SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements.................... 447
SPI1 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements.................... 445
SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements.................... 441
SPI1 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements.................... 443
SPI2 Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) Requirements.................... 427
SPI2 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements.................... 426
SPI2 Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 425
SPI2 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements.................... 435
SPI2 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements.................... 433
SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements.................... 429
SPI2 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements.................... 431
Timer1 External Clock Requirements ....................... 416
Timer2/Timer4 External Clock Requirements........... 417
Timer3/Timer5 External Clock Requirements........... 417
UARTx I/O Requirements......................................... 452
U
Universal Asynchronous Receiver Transmitter (UART) ... 279
Control Registers...................................................... 281
Helpful Tips............................................................... 279
Resources ................................................................ 280
User ID Words .................................................................. 382
V
Voltage Regulator (On-Chip) ............................................ 382
W
Watchdog Timer (WDT)............................................ 377, 383
Programming Considerations................................... 383
WWW Address ................................................................. 520
WWW, On-Line Support ..................................................... 20
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 520 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 521
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
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Questions (FAQs), technical support requests,
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•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 522 2011-2013 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
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Please list the following information, and use this outline to provide us with your comments about this document.
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DS70657GdsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2011-2013 Microchip Technology Inc. DS70657G-page 523
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Architecture: 33 = 16-bit Digital Signal Controller
24 = 16-bit Microcontroller
Flash Memory Family: EP = Enhanced Performance
Product Group: GP = General Purpose family
MC = Motor Control family
Pin Count: 02 = 28-pin
03 = 36-pin
04 = 44-pin
06 = 64-pin
Temperature Range: I=-40C to+85C (Industrial)
E=-40C to+125C (Extended)
Package: ML = Plastic Quad, No Lead Package - (44-pin) 8x8 mm body (QFN)
MM = Plastic Quad, No Lead Package - (28-pin) 6x6 mm body (QFN-S)
MR = Plastic Quad, No Lead Package - (64-pin) 9x9 mm body (QFN)
PT = Plastic Thin Quad Flatpack - (44-pin) 10x10 mm body (TQFP)
PT = Plastic Thin Quad Flatpack - (64-pin) 10x10 mm body (TQFP)
SO = Plastic Small Outline, Wide - (28-pin) 7.50 mil body (SOIC)
SP = Skinny Plastic Dual In-Line - (28-pin) 300 mil body (SPDIP)
SS = Plastic Shrink Small Outline - (28-pin) 5.30 mm body (SSOP)
TL = Very Thin Leadless Array - (36-pin) 5x5 mm body (VTLA)
TL = Very Thin Leadless Array - (44-pin) 6x6 mm body (VTLA)
Examples:
dsPIC33EP64MC504-I/PT:
dsPIC33, Enhanced Performance,
64-Kbyte program memory,
Motor Control, 44-pin,
Industrial temperature,
TQFP package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (Kbyte)
Product Group
Pin Count
Temperature Range
Package
Pattern
dsPIC 33 EP 64 MC5 04 T I / PT - XXX
Tape and Reel Flag (if applicable)
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 524 2011-2013 Microchip Technology Inc.
NOTES:
2011-2013 Microchip Technology Inc. DS70657G-page 525
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-050-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS70657G-page 526 . 2011-2013 Microchip Technology Inc.
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Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
11/29/12
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Microchip:
DSPIC33EP32MC202-I/SS PIC24EP512GP202-E/MM PIC24EP512GP202-E/SO PIC24EP512GP202-E/SP
PIC24EP512GP202-H/MM PIC24EP512GP202-H/SO PIC24EP512GP202-H/SP PIC24EP512GP202-I/MM
PIC24EP512GP202-I/SO PIC24EP512GP202-I/SP PIC24EP512GP202T-I/MM PIC24EP512GP202T-I/SO
PIC24EP512GP204-E/ML PIC24EP512GP204-E/PT PIC24EP512GP204-E/TL PIC24EP512GP204-H/ML
PIC24EP512GP204-H/PT PIC24EP512GP204-H/TL PIC24EP512GP204-I/ML PIC24EP512GP204-I/PT
PIC24EP512GP204-I/TL PIC24EP512GP204T-I/ML PIC24EP512GP204T-I/PT PIC24EP512GP204T-I/TL
PIC24EP512GP206-E/MR PIC24EP512GP206-E/PT PIC24EP512GP206-H/MR PIC24EP512GP206-H/PT
PIC24EP512GP206-I/MR PIC24EP512GP206-I/PT PIC24EP512GP206T-I/MR PIC24EP512GP206T-I/PT
PIC24EP512MC202-E/MM PIC24EP512MC202-E/SO PIC24EP512MC202-E/SP PIC24EP512MC202-H/MM
PIC24EP512MC202-H/SO PIC24EP512MC202-H/SP PIC24EP512MC202-I/MM PIC24EP512MC202-I/SO
PIC24EP512MC202-I/SP PIC24EP512MC202T-I/MM PIC24EP512MC202T-I/SO PIC24EP512MC204-E/ML
PIC24EP512MC204-E/PT PIC24EP512MC204-E/TL PIC24EP512MC204-H/ML PIC24EP512MC204-H/PT
PIC24EP512MC204-H/TL PIC24EP512MC204-I/ML PIC24EP512MC204-I/PT PIC24EP512MC204-I/TL
PIC24EP512MC204T-I/ML PIC24EP512MC204T-I/PT PIC24EP512MC204T-I/TL PIC24EP512MC206-E/MR
PIC24EP512MC206-E/PT PIC24EP512MC206-H/MR PIC24EP512MC206-H/PT PIC24EP512MC206-I/MR
PIC24EP512MC206-I/PT PIC24EP512MC206T-I/MR PIC24EP512MC206T-I/PT DSPIC33EP512MC202-H/SO
DSPIC33EP512MC202-I/SO DSPIC33EP512MC202T-I/MM DSPIC33EP512MC202T-I/SO DSPIC33EP512MC204-
E/ML DSPIC33EP512MC204-E/PT DSPIC33EP512MC204-E/TL DSPIC33EP512MC204-H/ML
DSPIC33EP512MC204-H/PT DSPIC33EP512MC204-H/TL DSPIC33EP512MC204-I/ML DSPIC33EP512MC204-I/PT
DSPIC33EP512MC204-I/TL DSPIC33EP512GP502T-I/SO DSPIC33EP512GP504-E/ML DSPIC33EP512GP504-E/PT
DSPIC33EP512GP504-E/TL DSPIC33EP512GP504-H/ML DSPIC33EP512MC202-H/SP DSPIC33EP512MC202-
I/MM DSPIC33EP512MC202-I/SP DSPIC33EP512GP504-H/PT DSPIC33EP512GP504-H/TL DSPIC33EP512GP504-
I/ML DSPIC33EP512GP504-I/PT DSPIC33EP512GP504-I/TL DSPIC33EP512GP504T-I/ML DSPIC33EP512GP504T-
I/PT DSPIC33EP512GP504T-I/TL DSPIC33EP512GP506-E/MR DSPIC33EP512GP506-E/PT
DSPIC33EP512GP506-H/MR DSPIC33EP512GP506-H/PT DSPIC33EP512GP506-I/MR DSPIC33EP512GP506-I/PT
DSPIC33EP512GP506T-I/MR DSPIC33EP512GP506T-I/PT
