PEB22554 - Siemens Semiconductors

QuadFALC

http://www.siemens.de/semiconductor/falc

Product Brief

QuadFALC™

PEB 22554

Quad E1/T1/J1 Framer & Line

Interface Component for Long

and Short Haul Applications

Applications

■Wirele s s Ba ses t at ion s

■T1/E1/J1 ATM Gateways

■T1/E1/J1 Fram e Relay Gateways

■T1/E1/J1 Channel & Data

Service Units (CSU, DSU)

■ISDN PRI, PBXs

■T1/E1/J1 Internet Access Equip.

■LAN/WAN Router

■SONET/SDH Add/Drop MUXs

■T1/E1/ J1 Mul t ip lex er

■Digital Access Cross-Connect

Syste ms (D ACS )

Features

Analog Line Interface

■Quad analog receive & transmit

circuitry long haul & short haul

for E1/T1/J1 applications

■Clock & data recovery

■Crystal-less wander and jitter

attenuation/compensation acc.

TR 62411, ETS-TBR 12/13

■Low frequency reference clock

■Programmable transmit pulse

shape for flexible pulse generation

■Transmit line monitoring

■Power down function per channel

Frame Aligner

■ITU-T G. 704 Frame alignment/

synthesis for 2048/1544 Kbit/s

■Programmable Frame Formats:

E1: Double- & CRC Multiframe

T1: F4, F12 (D4), Ext. Super

Frame (ESF), F72 (SLC96)

■CRC-4 performance monitoring

■Alar m & pe rf o rm a nc e

monitoring per second

■Detects & generates LOS (red),

AIS (blue) & RAI (yellow) alarms

■System bus data rate scalable

from 1 . 54 4 MH z up t o 16 MHz

■Mux/Demux of 4 channels into a

8.192 or 6.176 Mbit/s data bus

Signaling Controller

■4 HDLC/LAPD co ntroller (Q.921)

with deep FIFO buffers (64 bytes)

■CAS controller with serial CAS

in/output to system interface

■ANSI T1.403-Bit Oriented

Messages (BOM)

■Time Slot 0 SA8-4 bit handling

via FIFOs

General Features

■8/16-Bit µP interface Intel or

Motorola type

■34 maskable interrupt sources

■Meets japanese requirements

as: JT G. 703, 704, 706, I.431

■Test functions e.g. PRBS,

Local-, Remote- & Payload Loop

■Software & functional compatible

to PEB 2 255 FALC-LH

■Internal/external second timer

■Typ. 180 mW power consumption

per channel

■3.3 V power supply

■JTAG Boundary scan

IEEE1149.1

■P-TQFP-144 package 20 x 20 mm

body size, 0.5 pin pitch

The demand for increasing band-

width in existing infrastructure

results in more and more

multiport system solutions.

Based on PEB 2255 FALC-LH the

QuadFALC is perfectly suited to

realise generic, software config-

urable E1/T1/J1 applications.

By including framing, line inter-

face and signaling controller for

four Primary Rate Interfaces in a

single device the QuadFALC

offers outstanding performance

and functionality. Boardspace

and power consumption are

reduced dramatically.

Relying on the well established

software architecture of the

FALC54 and FALC-LH family and

their comprehensive support

mate r i al th e QuadFAL C ca n b e

designed in with minimum effort.

Published by Semiconductor Group

Siemens Aktiengesellschaft

How to reach us:

http://www.siemens.de/semiconductor

Please note that any information contained in this

publication may be subject to change. Siemens

reserves the right to make changes to or to

discontinue any product or service identified in this

publication without notice.

Please contact our regional offices to receive the

latest version of the relevant information to verify,

before placing orders, that the information being

relied upon is current.

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AUS

CDN

FIN

IND

MAL

ROK

RUS

SGP

USA

VRC

AIRL

Software Configuration Tool

Application Wizard actively supports the user

during the design phase.

The QuadFALC functionality is explained in detail.

An individual device driver source code can be

automatically generated.

Application Wizard for Communication Systems

Semiconductor Group

QuadFALC Data Sheet

Documentation

Beginners Mode

Expert Mode

QuadFALC Homepage

QuadFALC Application Wizard

for Communication Systems

Ordering No. B119-H7263-X-X-7600

Printed in Germany

PS 08985.

QuadFALC PEB 225 54 Block Dia

ram

Documentation and Support Package

Availability

The QuadFALC device is available with complete documentation and

support package. A dedicated engineering support team is there to

assist you. Please contact your local Siemens office for further details.

QuadFALC PEB 225 54 Application Examples

Frame Relay over E1/T1/J1 using QuadFALC, MUNICH128X and MTSL

ATM over E1/T1/J1 Interworking Unit

■Data Sheet

■Application Notes

■Hardware Evaluation System

EASY 22554 with WINEASY

Software for MS Windows95/NT

■CD-ROM Support Package

■Support Software (low level

driv er , LA PD Pr ot o co l S/W)

■Application Wizard: Configura-

tion Software for MS Windows95

& NT for device initialisation

Switching Network

Transmission Line

Analog / Digital

Line Interface

Short and Long Haul

Clock &

Data

Recovery

Coding &

Clocking

Unit CAS

Controller

Receive

Jitter

Compensation

Transmit

Jitter

Compensation

HDLC / BOM

Controller

System Interface

JTAG 1149.1 µP Interface

Frame

Aligner

PEB 22554

QuadFALC PEB 2047

MTSL

PEB 20324

MUNICH128X

T1/E1/J1

System Bus

CPU MEM

E1/T1 Layer Processing

PCM UTOPIA

AAL1 or PHY TC

Sublayer Processing Processing

ATM Layer

Up to 8

E1/T1/J1

PEB 22554

QuadFALC

PEB 22554

QuadFALC

PXB 4240

IWE8

RAM

ATM Layer

e.g. PXB

4350 ALP

Backplane