74LVC11 Triple 3-input AND gate Rev. 6 -- 17 November 2011 Product data sheet 1. General description The 74LVC11 provides three 3-input AND functions. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC11D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVC11DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVC11PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC11BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm SOT762-1 74LVC11 NXP Semiconductors Triple 3-input AND gate 4. Functional diagram 1 1 1A 2 13 2 1B 13 1C 3 2A 4 2B 5 2C 9 3A 10 3B 11 3C 1Y 12 12 & 6 3 2Y 4 6 5 A 3Y 9 8 & 10 8 Y B 11 C mna792 mna793 Fig 1. & Logic symbol Fig 2. IEC logic symbol mna794 Fig 3. Logic diagram for one gate 5. Pinning information 1A terminal 1 index area 14 VCC 5.1 Pinning 1 14 VCC 1B 2 13 1C 1B 2 13 1C 2A 3 12 1Y 2A 3 12 1Y 2B 4 1 1A 2Y 6 9 3A GND 7 8 3Y 11 11 3C 5 GND(1) 10 3B 2Y 6 9 8 5 4 3Y 10 3B 2C 2B 2C 7 11 3C GND 11 3A 001aad044 Transparent top view 001aad043 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A 1, 3, 9 data input 1B, 2B, 3B 2, 4, 10 data input 1C, 2C, 3C 13, 5, 11 data input 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 2 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate Table 2. Pin description ...continued Symbol Pin Description 1Y, 2Y, 3Y 12, 6, 8 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function selection[1] Input Output nA nB nC nY L X X L X L X L X X L L H H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don't care 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] VO = 0 V to VCC Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA 0.5 VCC + 0.5 V - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Ptot total power dissipation - 500 mW Tstg storage temperature 65 +150 C Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 C the value of PD derates linearly with 8 mW/K. For (T)SSOP14 packages: above 60 C the value of PD derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C the value of PD derates linearly with 4.5 mW/K. 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 3 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage functional Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature 40 - +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 40 C to +85 C Conditions VCC = 1.2 V Product data sheet Unit Min Max Min Max 1.08 - - 1.08 - V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V VCC = 1.65 V to 1.95 V - - 0.35 VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V 0.35 VCC V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VI = VIH or VIL IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A input leakage VCC = 3.6 V; VI = 5.5 V or GND current 74LVC11 40 C to +125 C Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 4 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate Table 6. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Min Typ[1] Max Min Max Unit ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter propagation delay tpd 40 C to +85 C Conditions Min Max Min Max - 14.0 - - - ns VCC = 1.65 V to 1.95 V 1.0 4.7 12.2 1.0 14.1 ns VCC = 2.3 V to 2.7 V 1.5 2.8 6.9 1.5 8.0 ns VCC = 2.7 V 1.5 2.9 7.0 1.5 8.1 ns VCC = 3.0 V to 3.6 V 1.5 2.5 6.2 1.5 7.2 ns VCC = 1.65 V to 1.95 V - 3.1 - - - pF VCC = 2.3 V to 2.7 V - 6.2 - - - pF VCC = 3.0 V to 3.6 V - 9.0 - - - pF nA, nB, nC to nY; see Figure 6 [2] VCC = 1.2 V power dissipation capacitance CPD [1] 40 C to +125 C Unit Typ[1] per gate; VI = GND to VCC [3] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 5 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate 11. AC waveforms VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VI nA, nB, nC input VM VCC GND tPLH tPHL VOH PULSE GENERATOR VI VO DUT RT CL RL VM nY output VOL mna795 001aaf615 VM = 1.5 V at VCC 2.7 V Test data is given in Table 8. Definitions for test circuit: VM = 0.5 VCC at VCC < 2.7 V. RL = Load resistance. VOL and VOH are typical output voltage levels that occur with the output load. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Table 8. Input (nA, nB and nC) to output (nY) propagation delays Fig 7. Load circuitry for measuring switching times Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC 2 ns 30 pF 1 k 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k 2.3 V to 2.7 V VCC 2 ns 30 pF 500 2.7 V 2.7 V 2.5 ns 50 pF 500 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 6 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 7 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 Fig 9. REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT337-1 (SSOP14) 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 8 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 10. Package outline SOT402-1 (TSSOP14) 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 9 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 11. Package outline SOT762-1 (DHVQFN14) 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 10 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate 13. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC11 v.6 20111117 Product data sheet - 74LVC11 v.5 * * Modifications: Legal pages updated. Table 6, bodyrow ICC: condition VCC changed. 74LVC11 v.5 20111025 Product data sheet - 74LVC11 v.4 74LVC11 v.4 20040113 Product specification - 74LVC11 v.3 74LVC11 v.3 19980428 Product specification - 74LVC11 v.2 74LVC11 v.2 19980428 Product specification - 74LVC11 v.1 74LVC11 v.1 - - - - 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 11 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 12 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 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Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 -- 17 November 2011 (c) NXP B.V. 2011. All rights reserved. 13 of 14 74LVC11 NXP Semiconductors Triple 3-input AND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 November 2011 Document identifier: 74LVC11