1. General description
The 74LVC11 provides three 3-input AND functions.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B ex ce ed s 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 Cto+85C and 40 Cto+125C
3. Ordering information
74LVC11
Triple 3-input AND gate
Rev. 6 — 17 November 2011 Product data sheet
Table 1. Ordering information
Type number Package
Temperatu re range Name Description Version
74LVC11D 40 Cto+125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74LVC11DB 40 Cto+125C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm SOT337-1
74LVC11PW 40 Cto+125C TSSOP14 plastic thin shrink small outl ine package; 14 leads;
body width 4.4 mm SOT402-1
74LVC11BQ 40 Cto+125C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 30.85 mm
SOT762-1
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 2 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate
mna793
3Y
3C
11 3B
10 3A
92C
52B
42A
31C
13 1B
21A
1
8
2Y 6
1Y 12
mna792
12
&
&
&
6
8
13
2
1
5
4
3
11
10
9
mna794
A
B
C
Y
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14
11
1A V
CC
1B 1C
2A 1Y
2B 3C
2C 3B
2Y 3A
GND 3Y
001aad043
1
2
3
4
5
6
7 8
10
9
12
11
14
13
001aad044
11
GND(1)
Transparent top view
2Y 3A
2C 3B
2B 3C
2A 1Y
1B 1C
GND
3Y
1A
VCC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A 1, 3, 9 data input
1B, 2B, 3B 2, 4, 10 data input
1C, 2C, 3C 13, 5, 11 data input
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 3 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C the value of PDderates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C the value of PDderates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C the value of PDderates linearly with 4.5 mW/K.
1Y, 2Y, 3Y 12, 6, 8 data output
GND 7 ground (0 V)
VCC 14 supply voltage
Table 2. Pin description …continued
Symbol Pin Description
Table 3. Function selection[1]
Input Output
nA nB nC nY
LXXL
XLXL
XXLL
HHHH
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA
VOoutput voltage [2] 0.5 VCC + 0.5 V
IOoutput curren t VO = 0 V to VCC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125 C[3] -500 mW
Tstg storage temperature 65 +150 C
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 4 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall
rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V; VI=5.5VorGND - 0.1 5-20 A
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 5 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs
ICC supply
current VCC = 3.6 V; VI=V
CC or GND;
IO=0A -0.110 - 40A
ICC additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI=V
CC 0.6 V; IO=0A
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-5.0- - -pF
Table 6. Static characteristics …continued
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay nA, nB, nC to nY; see Figure 6 [2]
VCC = 1.2 V - 14.0 - - - ns
VCC = 1.65 V to 1.95 V 1.0 4.7 12.2 1.0 14.1 ns
VCC = 2.3 V to 2.7 V 1.5 2.8 6.9 1.5 8.0 ns
VCC = 2.7 V 1.5 2.9 7.0 1.5 8.1 ns
VCC = 3.0 V to 3.6 V 1.5 2.5 6.2 1.5 7.2 ns
CPD power dissipation
capacitance per gate ; V I=GNDtoV
CC [3]
VCC = 1.65 V to 1.95 V - 3.1 - - - pF
VCC = 2.3 V to 2.7 V - 6.2 - - - pF
VCC = 3.0 V to 3.6 V - 9.0 - - - pF
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 6 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
11. AC waveforms
VM=1.5VatV
CC 2.7 V
VM=0.5 VCC at VCC <2.7V.
VOL and VOH are typical output voltage levels that occur
with the output load.
Test data is given in Table 8. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe
capacitance.
RT = Termination resistance should be equal to output
impedance Zo of the pulse generator.
Fig 6. Input (nA, nB and nC) to output (nY)
propagation delays Fig 7. Load circuitry for measuring switching times
mna795
nA, nB, nC input
nY output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aaf615
V
CC
V
I
V
O
DUT
CL
RTRL
PULSE
GENERATOR
Table 8. Test data
Supply voltage Input Load
VItr, tfCLRL
1.2 V VCC 2 ns 30 pF 1 k
1.65 V to 1.95 V VCC 2 ns 30 pF 1 k
2.3 V to 2.7 V VCC 2 ns 30 pF 500
2.7 V 2.7 V 2.5ns 50pF 500
3.0Vto3.6V 2.7V 2.5ns 50pF 500
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 7 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
12. Package outline
Fig 8. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 8 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
Fig 9. Package outline SOT337-1 (SSOP14)
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 9 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
Fig 10. Package outline SOT402-1 (TSSOP14)
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 10 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
Fig 11. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 11 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
13. Abbreviations
14. Revision history
Table 9. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC11 v.6 20111117 Product data sheet - 74LVC11 v.5
Modifications: •Legal pages updated.
•Table 6, bodyrow ICC: condition VCC changed.
74LVC11 v.5 20111025 Product data sheet - 74LVC11 v.4
74LVC11 v.4 20040113 Product specification - 74LVC11 v.3
74LVC11 v.3 19980428 Product specification - 74LVC11 v.2
74LVC11 v.2 19980428 Product specification - 74LVC11 v.1
74LVC11 v.1----
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 12 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be lia ble for any indirect, incidental,
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profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
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contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
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Suitability for use — NXP Semiconductors products are not designed,
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malfunction of an NXP Semiconductors product can reasonably be expected
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damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or cust omer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default ,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third part y
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
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other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC11 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 17 November 2011 13 of 14
NXP Semiconductors 74LVC11
Triple 3-input AND gate
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
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liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC11
Triple 3-input AND gate
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 17 Novem ber 2011
Document identifier: 74LVC11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14