600 mA, Ultralow Noise,
High PSRR, RF Linear Regulator
Data Sheet
ADM7155
Rev. B Document Feedback
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FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.4 V
Maximum load current: 600 mA
Low noise
0.9 µV rms total integrated noise from 100 Hz to 100 kHz
1.6 µV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.5 nV/√Hz from 10 kHz to 1 MHz
PSRR: >90 dB from 200 Hz to 200 kHz; 57 dB at 1 MHz
Dropout voltage: 120 mV typical at VOUT = 3.3 V, IOUT = 600 mA
Initial accuracy: ±0.5%
Accuracy over line, load, and temperature: −2.0% (minimum),
+1.5% (maximum)
Quiescent current, IGND = 4 mA at no load
Low shutdown current: 0.2 μA
Stable with a 10 µF ceramic output capacitor
8-lead LFCSP and 8-lead SOIC packages
Precision enable
Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications: PLLs, VCOs, and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
GENERAL DESCRIPTION
The ADM7155 is an adjustable linear regulator that operates
from 2.3 V to 5.5 V and provides up to 600 mA of load current.
Output voltages from 1.2 V to 3.4 V are possible depending on
the model. Using an advanced proprietary architecture, it
provides high power supply rejection and ultralow noise,
achieving excellent line and load transient response with only a
10 µF ceramic output capacitor.
The ADM7155 is available in four models that optimize power
dissipation and PSRR performance as a function of input and
output voltage. See Table 9 and Table 10 for selection guides.
The ADM7155 regulator typical output noise is 0.9 μV rms from
100 Hz to 100 kHz for fixed output voltage options and 1.5 nV/√Hz
for noise spectral density from 10 kHz to 1 MHz. The ADM7155
is available in 8-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC
packages, making it not only a very compact solution but also
providing excellent thermal performance for applications requiring
up to 600 mA of load current in a small, low profile footprint.
TYPICAL APPLICATION CIRCUIT
Figure 1. Regulated 3.0 V Output from 3.5 V Input
Figure 2. Noise Spectral Density for Different Values of CBYP
Table 1. Related Devices
Model
Input
Voltage
Output
Current
Fixed/
Adj1 Package
ADM7150ACP 4.5 V to 16 V 800 mA Fixed 8-Lead LFCSP
ADM7150ARD 4.5 V to 16 V 800 mA Fixed 8-Lead SOIC
ADM7151ACP 4.5 V to 16 V 800 mA Adj 8-Lead LFCSP
ADM7151ARD 4.5 V to 16 V 800 mA Adj 8-Lead SOIC
ADM7154ACP 2.3 V to 5.5 V 600 mA Fixed 8-Lead LFCSP
ADM7154ARD 2.3 V to 5.5 V 600 mA Fixed 8-Lead SOIC
1 Adj means adjustable.
VOUT
REF_SENSE
REF REF = 1.2V
VIN
EN
ADM7155
GND
C
REF
1µF
C
IN
10µF C
OUT
10µF
OFF
ON
V
IN
= 3.5V V
OUT
= 3.0V
V
OUT
= 1.2V × ( R1 + R2) /R2
1kΩ < R2 < 200kΩ
BYP
C
BYP
1µF
V
BYP
VREG
C
REG
10µF
V
REG
R1
R2
12325-001
NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 1M0.1 110 100 1k 10k 100k
0.1
1
10
100
10k
1k
NOISE FLOOR
1.0µF
3.3µF
10µF
33µF
100µF
330µF
1000µF
12325-002
ADM7155 Data Sheet
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 15
ADIsimPower Design Tool ....................................................... 15
Capacitor Selection .................................................................... 15
Undervoltage Lockout (UVLO) ............................................... 16
Programmable Precision Enable .............................................. 17
Start-Up Time ............................................................................. 17
REF, BYP, and VREG Pins......................................................... 18
Current-Limit and Thermal Overload Protection ................. 18
Thermal Considerations ............................................................ 18
Printed Circuit Board Layout Considerations ............................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
9/15—Rev. A to Rev. B
Changed 3.0 V to 2.4 V .................................................................. 14
12/14—Rev. 0 to Rev. A
Changes to Figure 35 to Figure 40 ................................................ 12
Changes to Figure 45 ...................................................................... 15
10/14—Revision 0: Initial Version
Data Sheet ADM7155
Rev. B | Page 3 of 24
SPECIFICATIONS
VIN = VOUT_MAX + 0.5 V, EN = VIN; ILOAD = 10 mA; CIN = COUT = CREG = 10 µF; CREF = CBYP = 1 µF; TA = 25°C for typical specifications; TJ =
−40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE V
IN
2.3 5.5 V
LOAD CURRENT I
LOAD
600 mA
OPERATING SUPPLY CURRENT I
GND
I
LOAD
= 0 µA 4.0 7.0 mA
I
LOAD
= 600 mA 6.5 10 mA
SHUTDOWN CURRENT I
IN_SD
EN = GND 0.2 2 µA
NOISE
Output Noise OUT
NOISE
10 Hz to 100 kHz, V
OUT
= 1.2 V to 3.4 V 1.6 µV rms
100 Hz to 100 kHz, V
OUT
= 1.2 V to 3.4 V 0.9 µV rms
Noise Spectral Density OUT
NSD
10 kHz to 1 MHz, V
OUT
= 1.2 V to 3.4 V 1.5 nV/√Hz
POWER SUPPLY REJECTION RATIO PSRR I
OUT
= 400 mA
ADM7155-01 1 kHz to 100 kHz, V
IN
= 2.3 V 92 dB
1 MHz, V
IN
= 2.3 V 65 dB
ADM7155-02 1 kHz to 100 kHz, V
IN
= 2.9 V 94 dB
1 MHz, V
IN
= 2.9 V 61 dB
ADM7155-03 1 kHz to 100 kHz, V
IN
= 3.4 V 94 dB
1 MHz, V
IN
= 3.4 V 57 dB
ADM7155-04 1 kHz to 100 kHz, V
IN
= 3.9 V 94 dB
1 MHz, V
IN
= 3.9 V 57 dB
OUTPUT VOLTAGE ACCURACY V
OUT
= V
REF
Initial Accuracy V
OUT
I
LOAD
= 10 mA, T
J
= +25°C −0.5 +0.5 %
1 mA < I
LOAD
< 600 mA, T
J
= −40°C to +85°C −2.0 +1.5 %
1 mA < I
LOAD
< 600 mA −2.0 +2.0 %
REGULATION
Line ∆V
OUT
/∆V
IN
V
IN
= V
OUT_MAX
+ 0.5 V to 5.5 V −0.02 +0.02 %/V
Load1 ∆V
OUT
/∆I
OUT
I
OUT
= 1 mA to 600 mA 0.3 1.6 %/A
CURRENT-LIMIT THRESHOLD2 I
LIMIT
V
22 mA
V
700 960 1200 mA
DROPOUT VOLTAGE3 V
DROPOUT
I
OUT
= 400 mA, V
OUT
= 3.3 V 80 130 mV
I
OUT
= 600 mA, V
OUT
= 3.3 V 120 210 mV
PULL-DOWN RESISTANCE
VOUT V
OUT_PULL
EN = 0 V, V
OUT
= 1 V, V
IN
= 5.5 V 550 Ω
REG V
REG_PULL
EN = 0 V, V
REG
= 1 V, V
IN
= 5.5 V 33 kΩ
VREF_PULL
EN = 0 V, VREF = 1 V, VIN = 5.5 V
620
Ω
BYP V
BYP_PULL
EN = 0 V, V
BYP
= 1 V, V
IN
= 5.5 V 400 Ω
START-UP TIME4
V
t
STARTUP
V
OUT
= 3.3 V 1.2 ms
V
t
REG_STARTUP
V
OUT
= 3.3 V 0.55 ms
V
t
REF_STARTUP
V
OUT
= 3.3 V 0.44 ms
Threshold TS
SD
T
J
rising 150 °C
Hysteresis TS
SD_HYS
15 °C
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising UVLO
RISE
2.29 V
Falling UVLO
FALL
1.95 V
Hysteresis UVLO
HYS
200 mV
ADM7155 Data Sheet
Rev. B | Page 4 of 24
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
V
THRESHOLDS
Rising V
REG_UVLORISE
1.94 V
Falling V
REG_UVLOFALL
1.60 V
Hysteresis V
REG_UVLOHYS
185 mV
PRECISION EN INPUT 2.3 V ≤ V
IN
≤ 5.5 V
Logic High EN
HIGH
1.13 1.22 1.31 V
Logic Low EN
LOW
1.05 1.13 1.22 V
Logic Hysteresis EN
HYS
90 mV
Leakage Current I
EN-LKG
EN = V
IN
or GND 0.01 1 µA
1 Based on an endpoint calculation using 1 mA and 600 mA loads.
2 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output
voltages above 2.3 V.
4 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
5 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
Table 3. Input and Output Capacitors, Recommended Specifications
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
MINIMUM CAPACITANCE
Input1 C
IN
T
A
= −40°C to +125°C 7.0 µF
Regulator1 C
REG
T
A
= −40°C to +125°C 7.0 µF
Output1 C
OUT
T
A
= −40°C to +125°C 7.0 µF
Bypass
CBYP
TA = −40°C to +125°C
0.1
µF
Reference C
REF
T
A
= −40°C to +125°C 0.7 µF
CAPACITOR ESR
C
REG
, C
OUT
, C
IN
, C
REF
R
ESR
T
A
= −40°C to +125°C 0.001 0.2 Ω
C
BYP
R
ESR
T
A
= −40°C to +125°C 0.001 2.0 Ω
1 The minimum input, regulator, and output capacitances must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADM7155
Rev. B | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VIN to GND −0.3 V to +7 V
VREG to GND
−0.3 V to VIN, or +4 V
(whichever is less)
VOUT to GND −0.3 V to VREG, or +4 V
(whichever is less)
BYP to VOUT ±0.3 V
EN to GND
−0.3 V to +7 V
BYP to GND −0.3 V to VREG, or +4 V
(whichever is less)
REF to GND −0.3 V to VREG, or +4 V
(whichever is less)
REF_SENSE to GND −0.3 V to +4 V
Storage Temperature Range
−65°C to +150°C
Junction Temperature 150°C
Operating Ambient Temperature
Range
−40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADM7155 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temper-
ature may need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit provided
that the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer PCB. The
junction-to-ambient thermal resistance is highly dependent on
the application and PCB layout. In applications where high
maximum power dissipation exists, close attention to thermal
PCB design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer PCB. JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the PCB temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type θ
JA
θ
JC
Ψ
JB
Unit
8-Lead LFCSP 36.7 23.5 13.3 °C/W
8-Lead SOIC 36.9 27.1 18.6 °C/W
ESD CAUTION
ADM7155 Data Sheet
Rev. B | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 8-Lead LFCSP Pin Configuration
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 VREG Regulated Input Supply Voltage to LDO Amplifier. Bypass VREG to GND with a 10 µF or greater
capacitor.
2
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 10 µF or greater capacitor.
3 BYP Low Noise Bypass Capacitor. Connect a 1 µF capacitor from the BYP pin to GND to reduce noise. Do not
connect a load to ground.
4 GND Ground Connection.
5 REF_SENSE Reference Sense. Connect Pin 5 to the REF pin. Do not connect Pin 5 to VOUT or GND.
6 REF
Low Noise Reference Voltage Output. Bypass REF to GND with a 1 µF capacitor. Short REF_SENSE to REF
for fixed output voltages. Do not connect a load to ground.
7 EN Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
8 VIN Regulator Input Supply Voltage. Bypass VIN to GND with a 10 µF or greater capacitor.
EP Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances
thermal performance, and it is electrically connected to GND inside the package. Connect the EP to the
ground plane on the board to ensure proper operation.
3BYP
4GND
1VREG
2VOUT
6REF
5 REF_SENSE
8 VIN
7 EN
ADM7155
TOP VIEW
(No t t o Scale)
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. T HE E X P OSE D P AD E NHANCE S
THE RM AL PERFO RM ANCE , AND I T I S E LECTRI CALL Y
CONNECTED TO GND I NS IDE THE P ACKAGE. CO NNE CT
THE EP TO THE GRO UND P LANE ON T HE BOARD T O
ENSURE P ROPE R OPE RATI ON.
12325-003
ADM7155
TOP VIEW
(No t t o Scale)
VREG
1
VOUT
2
BYP
3
GND
4
VIN
8
EN
7
REF
6
REF_SENSE
5
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. T HE E X P OSE D P AD E NHANCE S
THE RM AL PERFO RM ANCE , AND I T I S E LECTRI CALL Y
CONNECTED TO GND I NS IDE THE P ACKAGE. CO NNE CT
THE EP TO THE GRO UND P LANE ON T HE BOARD T O
ENSURE P ROPE R OPE RATI ON.
12325-004
Data Sheet ADM7155
Rev. B | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.5 V, or VIN = 2.3 V, whichever is greater; VEN = VIN; IOUT = 10 mA; CIN = COUT = CREG = 10 µF; CREF = CBYP = 1 µF;
TA = 25°C, unless otherwise noted.
Figure 5. Shutdown Current vs. Temperature at
Various Input Voltages, VOUT = 1.8 V
Figure 6. Output Voltage (VOUT) vs. Junction Temperature (TJ) at Various
Loads, VOUT = 3.3 V
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads,
VOUT = 3.3 V
Figure 9. Ground Current vs. Junction Temperature (TJ) at Various Loads,
VOUT = 3.3 V
Figure 10. Ground Current vs. Load Current (ILOAD), VOUT = 3.3 V
SHUT DO WN CURRENT (µA)
TEMPERATURE (°C)
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
–50 –25 025 50 75 100 125
VIN = 2.3V
VIN = 2.4V
VIN = 2.6V
VIN = 3.0V
VIN = 4.0V
VIN = 5.5V
12325-005
V
OUT
(V)
JUNCTION TEM P E RATURE ( °C) 1258525–5–40
3.26
3.27
3.34
3.33
3.32
3.31
3.30
3.29
3.28 I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-006
V
OUT
(V)
I
LOAD
(mA) 1000100101
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.34
3.33
12325-007
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.34
3.33
VOUT (V)
VIN (V) 5.5
5.04.54.03.5
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 200mA
ILOAD = 400mA
ILOAD = 600mA
12325-008
GRO UND CURRE NT (mA)
JUNCTION TEM P E RATURE ( °C) 1258525–5–40
0
10
9
8
7
6
5
4
3
2
1
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-009
GRO UND CURRE NT (mA)
I
LOAD
(mA) 1000100101
0
10
9
8
7
6
5
4
3
2
1
12325-010
ADM7155 Data Sheet
Rev. B | Page 8 of 24
Figure 11. Ground Current vs. Input Voltage (VIN) at Various Loads,
VOUT = 3.3 V
Figure 12. Dropout Voltage vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
VOUT = 3.3 V
Figure 14. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 3.3 V
Figure 15. Output Voltage (VOUT) vs. Junction Temperature (TJ) at Various
Loads, VOUT = 1.2 V
Figure 16. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.2 V
GRO UND CURRE NT (mA)
VIN (V) 5.5
5.0
4.54.03.5
0
10
9
8
7
6
5
4
3
2
1
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 200mA
ILOAD = 400mA
ILOAD = 600mA
12325-011
DROPOUT VOLTAGE (mV)
I
LOAD
(mA) 1000100101
0
160
140
120
100
80
60
40
20
12325-012
V
OUT
(V)
V
IN
(V) 3.83.73.63.53.43.33.1 3.2
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
I
LOAD
= 5mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-013
GRO UND CURRE NT (µA)
V
IN
(V) 3.8
3.7
3.63.53.43.33.1 3.2
0
1
2
3
4
5
6
7
8
9
10
I
LOAD
= 5mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-014
VOUT (V)
JUNCTION TEM P E RATURE ( °C) 1258525–5–40
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 200mA
ILOAD = 400mA
ILOAD = 600mA
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
12325-015
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
VOUT (V)
ILOAD ( mA) 1000100101
12325-016
Data Sheet ADM7155
Rev. B | Page 9 of 24
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads,
VOUT = 1.2 V
Figure 18. Ground Current vs. Junction Temperature (TJ) at Various Loads,
VOUT = 1.2 V
Figure 19. Ground Current vs. Load Current (ILOAD), VOUT = 1.2 V
Figure 20. Ground Current vs. Input Voltage (VIN) at Different Loads,
VOUT = 1.2 V
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Loads, VOUT = 3.3 V, VIN = 4.1 V
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Headroom Voltages, VOUT = 3.3 V, 400 mA Load
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
VOUT (V)
VIN (V) 5.55.04.54.03.53.02.52.0
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 200mA
ILOAD = 400mA
ILOAD = 600mA
12325-017
GRO UND CURRE NT (mA)
JUNCTION TEM P E RATURE ( °C) 1258525–5–40
0
10
9
8
7
6
5
4
3
2
1
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-018
GRO UND CURRE NT (mA)
I
LOAD
(mA) 1000100101
0
10
9
8
7
6
5
4
3
2
1
12325-019
0
10
9
8
7
6
5
4
3
2
1
GRO UND CURRE NT (mA)
V
IN
(V) 5.5
5.0
4.54.03.53.02.52.0
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-020
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–140
–120
–100
–80
–60
–40
–20
0I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-021
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–140
–120
–100
–80
–60
–40
–20
0
800mV
600mV
500mV
400mV
300mV
250mV
200mV
150mV
12325-022
ADM7155 Data Sheet
Rev. B | Page 10 of 24
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at
Different Frequencies, VOUT = 3.3 V, 400 mA Load
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Loads, VOUT = 1.2 V, VIN = 2.4 V
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Headroom Voltages, VOUT = 1.2 V, 400 mA Load
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
Different Frequencies, VOUT = 1.2 V, 400 mA Load
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency, Different CBYP,
VOUT = 3.3 V, 400 mA Load, 500 mV Headroom
Figure 28. RMS Output Noise vs. Load Current (ILOAD)
PSRR ( dB)
HEADROOM ( V ) 0.80.70.60.50.40.30.20.1
–140
–120
–100
–80
–60
–40
–20
0
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
12325-023
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M
110 100 1k 10k 100k 1M
–140
–120
–100
–80
–60
–40
–20
0I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-024
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–140
–120
–100
–80
–60
–40
–20
0
2.0V
1.5V
1.3V
1.2V
1.1V
12325-025
PSRR ( dB)
HEADROOM ( V ) 2.01.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
–140
–120
–100
–80
–60
–40
–20
010Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
12325-026
PSRR ( dB)
FRE Q UE NCY ( Hz ) 10M110 100 1k 10k 100k 1M
–140
–120
–100
–80
–60
–40
–20
01µF
10µF
100µF
1000µF
12325-027
OUTPUT NOI S E ( µV rms)
LOAD CURRENT ( mA) 100010 100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0 10Hz TO 100kHz
100Hz T O 100kHz
12325-028
Data Sheet ADM7155
Rev. B | Page 11 of 24
Figure 29. RMS Output Noise vs. Output Voltage
Figure 30. Output Noise Spectral Density,
10 Hz to 10 MHz, ILOAD = 100 mA
Figure 31. Output Noise Spectral Density,
0.1 Hz to 1 MHz, ILOAD = 10 mA
Figure 32. Output Noise Spectral Density, 0.1 Hz to 10 MHz, ILOAD = 100 mA
Figure 33. Output Noise Spectral Density at Various Loads,
0.1 Hz to 1 MHz
Figure 34. Output Noise Spectral Density at Various Loads,
10 Hz to 10 MHz
OUTPUT NOI S E ( µV rms)
OUTPUT VOLTAGE (V) 3.51.0 1.5 2.0 2.5 3.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0 10Hz TO 100kHz
100Hz T O 100kHz
12325-034
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 10M10 100 1k 10k 100k 1M
0.1
1
10
100
1k
12325-029
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 1M0.1 110 100 1k 10k 100k
0.1
1
10
100
10k
1k
12325-030
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 10M0.1 110 100 1k 10k 100k 1M
0.1
1
10
100
1k
10k
12325-002
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 1M0.1 110 100 1k 10k 100k
0.1
1
10
100
1k
10k I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-070
OUTPUT NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 10M10 100 1k 10k 100k 1M
0.1
1
10
100
1k I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 400mA
I
LOAD
= 600mA
12325-031
ADM7155 Data Sheet
Rev. B | Page 12 of 24
Figure 35. Load Transient Response, ILOAD = 10 mA to 510 mA,
VOUT = 3.3 V, VIN = 3.8 V, CH1 = IOUT, CH2 = VOUT
Figure 36. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 3.3 V, VIN = 3.8 V, CH1 = IOUT, CH2 = VOUT
Figure 37. Load Transient Response, ILOAD = 10 mA to 510 mA,
VOUT = 1.8 V, VIN = 2.3 V, CH1 = IOUT, CH2 = VOUT
Figure 38. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 1.8 V, VIN = 2.3 V, CH1 = IOUT, CH2 = VOUT
Figure 39. Line Transient Response, 1 V Input Step, ILOAD = 600 mA,
VOUT = 3.3 V, VIN = 3.9 V, CH1 = VIN, CH2 = VOUT
Figure 40. Line Transient Response, 1 V Input Step, ILOAD = 600 mA,
VOUT = 1.8 V, VIN = 2.4 V, CH1 = VIN, CH2 = VOUT
CH1 200mA Ω
BW
CH2 5mV
BW
M4.0µs A CH1 212mA
T 10.2%
1
2
T
12325-135
CH1 200mA Ω
BW
CH2 5mV
BW
M4.0µs A CH1 212mA
T 10.2%
1
2
T
12325-136
CH1 200mA Ω
BW
CH2 5mV
BW
M4.0µs A CH1 204mA
T 10.4%
1
2
T
12325-137
CH1 200mA Ω
BW
M4µs A CH1 532mA
T 10.6%
1
2
CH2 5mV
BW
T
12325-138
CH1 1V
BW
M400ns A CH1 4.38V
T 10.4%
1
2
CH2 1mV
BW
T
12325-139
CH1 1V BWM400ns A CH1 3.5V
T 11.4%
1
CH2 1mV BW
T
2
12325-140
Data Sheet ADM7155
Rev. B | Page 13 of 24
Figure 41. VOUT Start-Up Time After VEN Rising, Different Output Voltages,
VIN = 5 V
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
012345678910
V
OUT
(V)
TIME (ms)
ENABL E (V
EN
)
1.2V
1.8V
3.3V
12325-141
ADM7155 Data Sheet
Rev. B | Page 14 of 24
THEORY OF OPERATION
The ADM7155 is an ultralow noise, high power supply rejection
ratio (PSRR) linear regulator targeting radio frequency (RF)
applications. The input voltage range is 2.3 V to 5.5 V, and it
can deliver up to 600 mA of load current. Typical shutdown
current consumption is 0.2 µA at room temperature.
Optimized for use with 10 µF ceramic capacitors, the ADM7155
provides excellent transient performance.
Figure 42. Simplified Internal Block Diagram
Internally, the ADM7155 consists of a reference, an error
amplifier, and a P-channel MOSFET pass transistor. Output
current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to pass and increasing the
output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to pass and decreasing the output voltage.
By heavily filtering the reference voltage, the ADM7155 is able
to achieve 1.5 nV/√Hz output typical from 10 kHz to 1 MHz.
Because the error amplifier is always in unity gain, the output
noise is independent of the output voltage.
To maintain very high PSRR over a wide frequency range, the
ADM7155 architecture uses an internal active ripple filter. This
stage isolates the low output noise LDO from noise on the VIN
pin. The result is that the PSRR of the ADM7155 is significantly
higher over a wider frequency range than any single stage LDO.
The ADM7155 output voltage can be adjusted between 1.2 V
and 3.4 V and is available in four models that optimize the
input voltage and output voltage ranges to keep power
dissipation as low as possible without compromising PSRR
performance. The output voltage is determined by an external
voltage divider according to the following equation:
VOUT = 1.2 V × (1 + R1/R2)
Figure 43. Typical Adjustable Output Voltage Application Schematic
The R2 value must be greater than 1 kΩ to prevent excessive
loading of the reference voltage appearing on the REF pin. To
minimize errors in the output voltage caused by the REF_SENSE
pin input current, the R2 value must be less than 200 kΩ. For
example, when R1 and R2 each equal 200 kΩ, the output
voltage is 2.4 V. The output voltage error introduced by the
REF_SENSE pin input current is 10 mV or 0.33%, assuming a
maximum REF_SENSE pin input current of 100 nA at TJ =
125°C.
The ADM7155 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is high,
VOUT turns on, and when EN is low, VOUT turns off. For
automatic startup, tie EN to VIN.
Figure 44. Simplified ESD Protection Block Diagram
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 44).
12325-042
VREG GND
VOUT
VIN
EN
REF
REF_SENSE
1.2V RE FERE NCE
SHUTDOWN
ACTIVE RIPPLE
FILTER
CURRENT-LIMIT,
THERMAL
PROTECT
OTA
BYP
ADM7155-03 V
REG
= 3.2V
ADM7155-04 V
REG
= 3.6V
ADM7155-01 V
REG
= 2.1V
ADM7155-02 V
REG
= 2.6V
VOUT
REF
REF_SENSE
GND
VIN
EN
BYP
VREG
V
BYP
V
REG
ADM7155-04
C
REG
10µF
C
BYP
1µF
C
REF
1µF
V
OUT
= 1.2V × ( 1 + R1/R2)
1kΩ < R2 < 200kΩ
C
IN
10µF C
OUT
10µF
OFF
ON
V
IN
= 4.0V V
OUT
= 3.3V
R1
R2
12325-200
VREG
VIN
REF_SENSE
REF
VOUT
BYP
GND
EN
7V 4V
4V
4V
4V
4V 4V
4V
4V
7V
7V
12325-043
Data Sheet ADM7155
Rev. B | Page 15 of 24
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
The ADM7155 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance within minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and device count,
taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about, and to obtain ADIsimPower design tools,
visit www.analog.com/ADIsimPower.
CAPACITOR SELECTION
Multilayer ceramic capacitors (MLCCs) combine small size, low
ESR, low ESL, and wide operating temperature range, making
them an ideal choice for bypass capacitors. They are not without
faults, however. Depending on the dielectric material, the
capacitance can vary dramatically with temperature, dc bias,
and ac signal level. Therefore, selecting the proper capacitor
results in the best circuit performance.
Output Capacitor
The ADM7155 is designed for operation with ceramic
capacitors but functions with most commonly used capacitors
when care is taken with regard to the effective series resistance
(ESR) value. The ESR of the output capacitor affects the stability
of the LDO control loop. A minimum of 10 µF capacitance with
an ESR of 0.2 Ω or less is recommended to ensure the stability
of the ADM7155. Output capacitance also affects transient
response to changes in load current. Using a larger value of
output capacitance improves the transient response of the
ADM7155 to large changes in load current. Figure 45 shows the
transient responses for an output capacitance value of 10 µF.
Figure 45. Output Transient Response, VOUT = 3.3 V, COUT = 10 µF,
CH1 = Load Current, CH2 = VOUT
Input and VREG Capacitor
Connecting a 10 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered.
To maintain the best possible stability and PSRR performance,
connect a 10 µF capacitor from VREG to GND. When more
than 10 µF of output capacitance is required, increase the input
and the VREG capacitors, CREG, to match it.
REF Capacitor
The REF capacitor, CREF, is necessary to stabilize the reference
amplifier. Connect at least a 1 µF capacitor between REF and GND.
BYP Capacitor
The BYP capacitor, CBYP, is necessary to filter the reference
buffer. A 1 µF capacitor is typically connected between BYP and
GND. Capacitors as small as 0.1 µF can be used; however, the
output noise voltage of the LDO increases as a result.
In addition, the BYP capacitor value can be increased to reduce
the noise below 1 kHz at the expense of increasing the start-up
time of the LDO. Very large values of CBYP significantly reduce
the noise below 10 Hz. Tantalum capacitors are recommended
for capacitors larger than approximately 33 µF because solid
tantalum capacitors are less prone to microphonic noise issues.
A 1 μF ceramic capacitor in parallel with the larger tantalum
capacitor is recommended to ensure good noise performance at
higher frequencies.
Figure 46. RMS Noise vs. CBYP
CH1 200mA Ω BWM4µs A CH1 212mA
T 10.2%
1
CH2 5mV BW
2
T
12325-144
OUTPUT NOI S E ( µV rms)
C
BYP
(µF) 1000110 100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0 10Hz TO 100kHz
100Hz T O 100kHz
12325-045
ADM7155 Data Sheet
Rev. B | Page 16 of 24
Figure 47. Noise Spectral Density vs. Frequency for
Different Capacitances (CBYP)
Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADM7155 if they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with different
behavior over temperature and applied voltage. Capacitors must
have a dielectric adequate to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V
are recommended. However, Y5V and Z5U dielectrics are
not recommended because of their poor temperature and dc
bias characteristics.
Figure 48 depicts the capacitance vs. dc bias voltage of a 1206,
10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~±15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
Figure 48. Capacitance vs. DC Bias Voltage
Use Equation 1 to determine the worst case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
In this example, the worst case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and CBIAS is 9.72 µF at 5 V, as shown in Figure 48.
Substituting these values in Equation 1 yields
CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADM7155, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADM7155 also incorporates an internal UVLO circuit to
disable the output voltage when the input voltage is less than the
minimum input voltage rating of the regulator. The upper and
lower thresholds are internally fixed with about 200 mV of
hysteresis.
Figure 49. Typical UVLO Behavior at Different Temperatures, VOUT = 3.3 V
Figure 49 shows the typical hysteresis of the UVLO function.
This hysteresis prevents on/off oscillations that can occur when
caused by noise on the input voltage as it passes through the
threshold points.
NOISE SPECTRAL DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz ) 1M0.1 110 100 1k 10k 100k
0.1
1
10
100
10k
1k
NOISE FLOOR
1.0µF
3.3µF
10µF
33µF
100µF
330µF
1000µF
12325-046
CAPACITANCE ( µF )
DC BIAS V OL TAG E ( V ) 1004826
0
12
10
8
6
4
2
12325-047
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V) 2.302.252.202.152.102.052.001.951.90
0
2.5
2.0
1.5
1.0
0.5
–40°C
+25°C
+125°C
12325-048
Data Sheet ADM7155
Rev. B | Page 17 of 24
PROGRAMMABLE PRECISION ENABLE
The ADM7155 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 50,
when a rising voltage on EN crosses the upper threshold,
nominally 1.22 V, V OUT turns on. When a falling voltage on EN
crosses the lower threshold, nominally 1.13 V, V OUT turns off.
The hysteresis of the EN threshold is approximately 90 mV.
Figure 50. Typical VOUT Response to EN Pin Operation
Figure 51. Typical VOUT Response to EN Pin Operation (VEN),
VOUT = 3.3 V, VIN = 5 V, CBYP = 1 µF
Figure 52. Typical EN Threshold vs. Input Voltages (VIN) for Different
Temperatures
The upper and lower thresholds are user programmable and can
be set higher than the nominal 1.22 V threshold by using two
resistors. The resistance values, REN1 and REN2, can be
determined from
REN1 = REN2 × (VIN − 1.22 V)/1.22 V
where:
REN2 typically ranges from 10 kΩ to 100 kΩ.
VIN is the desired turn-on voltage.
The hysteresis voltage increases by the factor
(REN1 + REN2)/REN1
For the example shown in Figure 53, the EN threshold is 2.44 V
with a hysteresis of 200 mV.
Figure 53. Typical EN Pin Voltage Divider
Figure 53 shows the typical hysteresis of the EN pin. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
START-UP TIME
The ADM7155 uses an internal soft start to limit the inrush
current when the output is enabled. The start-up time for a
3.3 V output is approximately 1.2 ms from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value.
The rise time in seconds of the output voltage (10% to 90%) is
approximately
0.0012 × CBYP
where CBYP is in microfarads.
V
OUT
(V)
EN PIN VOLTAGE (V) 1.31.21.11.0
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
–40°C
–5°C
+25°C
+85°C
+125°C
12325-049
V
OUT
(V)
TIME (ms) 4.03.63.22.82.42.01.61.20.80.40
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
ENABL E (V
EN
)
V
OUT
12325-050
EN T HRES HOL D ( V )
INPUT VOLTAGE (V) 5.55.04.54.03.53.02.5
1.100
1.250
1.225
1.200
1.175
1.150
1.125
–40°C RISING
+25° C RISING
+125° C RISING
–40°C FAL LI NG
+25° C FAL LI NG
+125° C FAL LI NG
12325-051
VOUT
REF_SENSE
REF REF = 1.2V
VIN
EN
ADM7155
GND
C
REF
1µF
C
IN
10µF C
OUT
10µF
OFF
ON
V
IN
= 3.5V V
OUT
= 3.0V
BYP
C
BYP
1µF
VREG
C
REG
10µF
100kΩ
V
OUT
= 1.2V × ( R1 + R2) /R2
1kΩ < R2 < 200kΩ
100kΩ
V
BYP
V
REG
R1
R2
12325-052
ADM7155 Data Sheet
Rev. B | Page 18 of 24
Figure 54. Typical Start-Up Behavior with CBYP = 1 µF to 10 µF
Figure 55. Typical Start-Up Behavior with CBYP = 10 µF to 330 µF
REF, BYP, AND VREG PINS
REF, BYP, and VREG generate voltages internally (VREF, VBYP,
and VREG) that require external bypass capacitors for proper
operation. Do not, under any circumstances, connect any loads
to these pins, because doing so compromises the noise and
PSRR performance of the ADM7155. Using larger values of
CBYP, CREF, and CREG is acceptable but can increase the start-up
time, as described in the Start-Up Time section.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADM7155 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADM7155 is designed to current limit when the
output load reaches 960 mA (typical). When the output load
exceeds 960 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C. Under extreme
conditions (that is, high ambient temperature and/or high
power dissipation), when the junction temperature starts to rise
above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C, the output is turned on again, and the output current is
restored to its operating value.
Consider the case where a hard short from VOUT to GND
occurs. At first, the ADM7155 current limits, so that only
960 mA is conducted into the short. If self heating of the
junction is great enough to cause its temperature to rise above
150°C, thermal shutdown activates, turning off the output and
reducing the output current to zero. As the junction tempera-
ture cools and drops below 135°C, the output turns on and
conducts 900 mA into the short, again causing the junction
temperature to rise above 150°C. This thermal oscillation
between 135°C and 150°C causes a current oscillation between
900 mA and 0 mA that continues for as long as the short
remains at the output.
Current-limit and thermal limit protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperature does not exceed 150°C.
THERMAL CONSIDERATIONS
In applications with a low input to output voltage differential,
the ADM7155 does not dissipate much heat. However, in
applications with high ambient temperature and/or high input
voltage, the heat dissipated in the package may become large
enough that it causes the junction temperature of the die to
exceed the maximum junction temperature of 150°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature decreases below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera-
ture rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADM7155 must not exceed 150°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances
between the junction and ambient air (θJA). The θJA number is
dependent on the package assembly compounds that are used
and the amount of copper used to solder the package GND pin
and exposed pad to the PCB.
Table 7 shows typical θJA values of the 8-lead SOIC and 8-lead
LFCSP packages for various PCB copper sizes.
Table 8 shows the typical ΨJB values of the 8-lead SOIC and
8-lead LFCSP.
V
OUT
(V)
TIME (ms) 4035302520151050
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5 ENABLE ( V
EN
)
C
BYP
= 1µF
C
BYP
= 3.3µF
C
BYP
= 10µF
12325-053
VOUT (V)
TIME (ms) 200180160
140120100806040200
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
ENABL E (VEN)
CBYP = 10µ F
CBYP = 33µ F
CBYP = 100µ F
CBYP = 330µ F
12325-054
Data Sheet ADM7155
Rev. B | Page 19 of 24
Table 7. Typical θJA Values
θ
JA
(°C/W)
Copper Size (mm
2
) 8-Lead LFCSP 8-Lead SOIC
25
1
165.1 165
100 125.8 126.4
500 68.1 69.8
1000 56.4 57.8
6400 42.1 43.6
1 Device soldered to minimum size pin traces.
Table 8. Typical ΨJB Values
Package Ψ
JB
(°C/W)
8-Lead LFCSP 15.1
8-Lead SOIC 17.9
The junction temperature of the ADM7155 is calculated from
the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND) (3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation caused by ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA) (4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current,
there exists a minimum copper size requirement for the PCB to
ensure that the junction temperature does not rise above 150°C.
The heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins and
exposed pad of the ADM7155. Adding thermal planes
underneath the package also improves thermal performance.
However, as shown in Table 7, a point of diminishing returns is
eventually reached, beyond which an increase in the copper
area does not yield significant reduction in the junction to
ambient thermal resistance.
Figure 56 to Figure 61 show junction temperature calculations
for different ambient temperatures, power dissipation, and areas
of PCB copper.
Figure 56. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 25°C
Figure 57. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 50°C
Figure 58. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 85°C
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W)
6400mm2
500mm2
25mm2
TJ MAX
25
35
45
55
65
75
85
95
105
115
125
135
145
155
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
12325-055
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W)
1.8 2.0 2.2 2.4
1.61.4
1.21.0
0.80.6
0.4
0.2
0
50
60
70
80
90
100
110
120
140
160
130
150
6400mm
2
500mm
2
25mm
2
T
J
MAX
12325-056
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W) 1.50.8 0.9 1.0 1.1 1.2 1.3 1.40.70.60.50.40.30.20.10
65
75
85
95
105
115
125
135
155
145
6400mm
2
500mm
2
25mm
2
T
J
MAX
12325-057
ADM7155 Data Sheet
Rev. B | Page 20 of 24
Figure 59. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
Figure 60. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
Figure 61. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Thermal Characterization Parameter (ΨJB)
When board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 62 and Figure 63). Maximum
junction temperature (TJ) is calculated from the board
temperature (TB) and power dissipation (PD) using the following
formula:
TJ = TB + (PD × ΨJB) (5)
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP
package and 17.9°C/W for the 8-lead SOIC package.
Figure 62. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP
Figure 63. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
PSRR PERFORMANCE
The ADM7155 is available in four models that optimize power
dissipation and PSRR performance as a function of input and
output voltage. See Table 9 and Table 10 for selection guides.
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W) 2.82.62.4 3.02.22.01.81.61.41.21.00.80.60.40.20
25
155
145
125
102
85
65
45
135
115
95
75
55
35
6400mm
2
500mm
2
25mm
2
T
J
MAX
12325-058
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W)
1.8 2.0 2.2 2.4
1.61.4
1.2
1.00.8
0.60.40.2
0
50
60
70
80
90
100
110
120
130
160
150
140
6400mm
2
500mm
2
25mm
2
T
J
MAX
12325-059
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W) 2.01.6 1.81.41.21.00.80.60.40.20
65
75
85
95
105
115
125
135
155
145
6400mm
2
500mm
2
25mm
2
T
J
MAX
12325-060
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W) 9.08.58.07.06.0 7.56.55.55.04.54.03.53.02.52.01.51.00.50
0
160
140
120
100
80
60
40
20
T
B
= 25° C
T
B
= 50° C
T
B
= 65° C
T
B
= 85° C
T
J
MAX
12325-061
JUNCTION TEM P E RATURE ( °C)
TOTAL POWER DISSIPATION (W)
5.5 7.57.06.56.05.04.54.03.53.02.52.01.51.00.50
0
160
140
120
100
80
60
40
20
T
B
= 25° C
T
B
= 50° C
T
B
= 65° C
T
B
= 85° C
T
J
MAX
12325-062
Data Sheet ADM7155
Rev. B | Page 21 of 24
Table 9. Model Selection Guide for PSRR
Model V
OUT
_
MAX
(V)
PSRR (dB) at 600 mA; V
IN
= V
OUT
_
MAX
+ 0.5 V PSRR (dB) at 400 mA; V
IN
= V
OUT
_
MAX
+ 0.5 V
10 kHz 100 kHz 1 MHz 10 kHz 100 kHz 1 MHz
ADM7155-01 1.8 101 92 60 102 92 65
ADM7155-02 2.3 101 94 57 101 93 61
ADM7155-03 2.9 103 94 51 102 94 57
ADM7155-04 3.4 103 94 51 102 94 57
Table 10. Model Selection Guide for Input Voltage
Model V
OUT
Range (V) Minimum V
IN
at 600 mA Load
ADM7155-01
1.2 to 1.8
2.3 V
ADM7155-02 1.2 to 2.3 2.9 V
ADM7155-03 1.2 to 2.9 3.4 V
ADM7155-04 1.2 to 3.4 3.9 V
ADM7155 Data Sheet
Rev. B | Page 22 of 24
PCB LAYOUT CONSIDERATIONS
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Place the bypass capacitors (CREG, CREF,
and CBYP) for VREG, VREF, and VBYP close to the respective pins
(VREG, REF, and BYP) and GND. Use of an 0805, 0603, or
0402 size capacitor achieves the smallest possible footprint
solution on boards where area is limited.
Figure 64. Example 8-Lead LFCSP PCB Layout
Figure 65. Example 8-Lead SOIC PCB Layout
12325-063
12325-064
Data Sheet ADM7155
Rev. B | Page 23 of 24
OUTLINE DIMENSIONS
Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-21)
Dimensions shown in millimeters
Figure 67. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
2.54
2.44
2.34
0.50
0.40
0.30
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.20 M IN
0.05 M AX
0.02 NO M
0.50 BSC
EXPOSED
PAD
PIN 1
INDICATOR
(R 0. 20)
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
12-03-2013-A
PKG-004371
3.10
3.00 SQ
2.90
COMPLIANT TO JE DE C S TANDARDS MS-012-AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 M AX
0.05 NO M
3.81 REF
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BSC
SEATING
PLANE
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
ADM7155 Data Sheet
Rev. B | Page 24 of 24
ORDERING GUIDE
Model1
Temperature Range
Output Voltage Range (V)
Package Description
Package Option
Branding
ADM7155ACPZ-01-R7 −40°C to +125°C 1.2 to 1.8 8-Lead LFCSP_WD CP-8-21 LQ8
ADM7155ACPZ-02-R7 −40°C to +125°C 1.2 to 2.4 8-Lead LFCSP_WD CP-8-21 LQ9
ADM7155ACPZ-03-R7 −40°C to +125°C 1.2 to 2.9 8-Lead LFCSP_WD CP-8-21 LQA
ADM7155ACPZ-04-R7 −40°C to +125°C 1.2 to 3.4 8-Lead LFCSP_WD CP-8-21 LQV
ADM7155ARDZ-01-R7 −40°C to +125°C 1.2 to 1.8 8-Lead SOIC_N_EP RD-8-1
ADM7155ARDZ-02-R7 −40°C to +125°C 1.2 to 2.4 8-Lead SOIC_N_EP RD-8-1
ADM7155ARDZ-03-R7 −40°C to +125°C 1.2 to 2.9 8-Lead SOIC_N_EP RD-8-1
ADM7155ARDZ-04-R7 −40°C to +125°C 1.2 to 3.4 8-Lead SOIC_N_EP RD-8-1
ADM7155CP-02-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D12325-0-9/15(B)
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