IM1486-120 - Innovative Microdevices, Inc.

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

FEATURES

128K bytes of user NV SRAM.

Real time quartz clock/clender keeps track of

hunderedths of seconds, seconds, minutes, hours,

days, date of the month, month, and years with leap

year compensation valid up to 2100.

Will operate in 32-pin JEDEC footprint

Watchdog timer restarts an out-of-control processor.

Alarm function schedules real-time related activities

such as system wakeup.

Embedded lithium energy cell maintains

time,watchdog, user RAM, and alarm information.

Programmable interrupts and square wave outputs.

All registers are individually addressable via the

address and data bus.

Accuracy is better than +/- 1 minute/month at 25OC.

Greater than 10 years of timekeeping in the absence

of Vcc @ 25OC.

Interrupt signals active in power-down mode.

PIN CONFIGURATION

DESCRIPTION

The IM1486 SRAM + RTC + Watchdog is self con-

tained realtime clock,alaram, watchdog timer, and in-

terval timer in 32-pin JEDEC DIP package. The IM1486

contains an embedded lithium energy source and a

quartz crystal which eliminates the need for any exter-

nal circuitry. Data contained within 128K by 8-bit

memory and the timekeeping registers can be read or

written in the same manner as bytewide static RAM.

The timekeeping registers are located in the first 14

bytes of memory space. Data is maintained in the RAM

+ RTC + W atchdog by intelligent control circuitry which

detects the status of Vcc and write protects memory

when Vcc is out of tolerance. The lithium energy source

can maintain data and real time for over ten years in

the absence of Vcc. Timekeeper information includes

hundredths of seconds, seconds, minutes, hours, day

date, month, and year . The date at the end of the months

with less than 31 days, including correction for leap

year.

INTB(INTB)

A16

A14

A12

I/O0

I/O1

I/O2

GND

PIN DESCRIPTION

INTB(INTB) - Interrupt Output B(open drain)

A0-A16 - Address Inputs

I/O0-I/O7 - Data Input/Output

CE - Chip Enable

OE - Output Enable

WE - Write Enable

Vcc - +5 Volts

GND - Ground

INTA/SQW - Interrupt Output A/Square Wave

Output (INTA is open drain)

IM1486 128K X 8

32-PIN ENCAPSULATED

PACKAGE

ORDERING INFORMATION

IM1486 - 120 RTC AND 128K X 8 NVRAM

120 ns access

1 32

2 31

3 30

4 29

5 28

6 27

7 26

8 25

9 24

10 23

11 22

12 21

13 20

14 19

15 18

16 17

Vcc

A15

INTA/SQW

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

INNOVATIVE MICRODEVICES INC.Phone/Fax-440-322-8083.Website:www.innovativemicrodevices.com

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

BLOCK DIAGRAM

OSCILLATOR DIVIDE COUNTER

DIVIDE

BY 4

1024 Hz

SQW

DELAY

DATA I/O BUFFERS

A0-A16

ADDRESS DECODE

ADN COUNTROL

RTC REGISTERS

COMMAND

USER RAM

128K X 8

TD INT

WD INT INTA

INTB(INTB)

INTERNAL

COUNTER

EXTERNAL

SWAP

PINS

POWER

SWITCH

Vcc (VBAT)

QUARTZ

CRYSTAL

DQ0 - DQ7

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

OPERATIION - READ REGISTERS

The IM1486 executes a read cucle whenever WE is

inactive(High) and CE (Chip Enable) and OE (Output

Enable) are active (Low). The unique address speci-

fied by the address inputs(A0-A16) defines which of

the registers is to be accessed. Valid data will be avail-

able to the eight data output drivers within tACC (Access

Time) after the last address input signal is stable, pro-

viding that CE and OE access times are also satisfied.

If OE and CE access times are not satisfied, then data

access must be measured from the latter occuring

signal(CE or OE) and the limiting parameter is either

tCO for CE or tOE for OE rather than address access.

OPERATION - WRITE REGISTERS

The IM1486 is in the write mode whenever the WE(write

enable) and CE(Chip enable) signals are in the

active(Low) state after the address inputs are stable.

The latter occuring falling edge of CE or WE will deter-

mine the start of the write cycle. The write cycle is ter-

minated by the earlier rising edge of CE or WE. All ad-

dress inputs must be kept valid through out the write

cycle. WE must return to the high state for a minimum

recovery state(tWR) before another cycle can be initi-

ated. Data must be valid on the databus with sufficient

data set-up(tDS) and data hold time(tDH) with respect to

the earlier rising edge of CE or WE. The OE control

signal should be kept inactive(High) during write cycle

to avoid bus contention. However , if the output bus has

been enabled(CE and OE active), then WE will disable

the outputs in tODW from its falling edge.

DATA RETENTION

The RAM + Timekeeper provides full functional capa-

bility when Vcc is greater than 4.5 volts and write-pro-

tects the register contents at 4.25 volts typical. Data is

maintained in the absence of Vcc without any additional

support circuitry. The IM1486 constantly monitors Vcc.

Should the supply voltage decay, the RAM + Time-

keeper wiil automatically write-protect itself and all in-

puts to the registers become “don’t care”. The two in-

terrupts INTA and INTB(INTB) and the internal clock

and timers continue to run regardless of the level of

Vcc. However, it is important to insure that the pull-up

resistors used with the interrupt pins are never pulled

up to a value that is greater than Vcc + 0.3V. As Vcc

falls below approximately 3.0 volts, a power switching

circuit turns the internal lithium energy source on to

maintain the clock and timer data and functionality.

During power-up, when Vcc rises above approximately

3.0 volts, the power switching circuit connects external

Vcc and disconnects the internal lithium energy source.

Normal operation can resume after Vcc exceeds 4.5

volts for a period of 200ms.

RAM + TIMEKEEPER REGISTERS

The RAM + Timekeeper has 14 registers which are eight

bits wide that contain all of the timekeeping, alarm,

watchdog and control information. The clock calender,

alarm and watchdog registers are memory locations

which contain external(user-accessible) and internal

copies of the data. The external copies are indepen-

dent of internal functions except that they are updated

periodically by the simultaneous transfer of the

incremented internal copy. The command Register bits

are affected by both internal and external functions.

This registers will be discussed later. Registers 0, 1, 2,

4, 6, 8, 9 and A contain time of day and dae informa-

tion. Time of day information is stored in BCD. Regis-

ters 3, 5, and 7 contain the T ime of Day Alarm informa-

tion. Time of Day Alarm information is stored in BCD.

in this register is binary. Registers Cand D are the

Watchdog Alarm Registers and information which is

stored in these two registers is in BCD. Register E

through 1FFFF are user bytes and can be used to

maintain data at the user ’s discretion.

TIME OF THE DAY REGISTERS

Registers 0, 1, 2, 4, 6, 8, 9, and A contain T ime of Day

data in BCD. Ten bits within these eight registers are

not used and will always read zero regardless of how

they are written. Bits 6 and 7 in the Months Registers(9)

are binary bits. When set to logic zero, EOSC (Bit 7)

enables the real time clock oscillator. This bit is set to

logic one as shipped from Innovative Microdevices to

prevent lithium energy consumption during storage and

shipment. This bit will normally be turned on by the

user during device initialization.However, the oscillator

can be turned on and off as necessary by setting this

bit to the appropriate level. Bit 6 of this same byte con-

trols the INTA/ Square Wave Output (pin 30). When

set to logic 0 the output pin will output a 1024 Hz square

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

wave siganl.When set to logic one the Square Wave

Output pin is available for interrupt A output (INT A) only .

Bit 6 of the Hours register is defined as the 12 or 24

hour select bit. When set to logic one, the 12 hour for-

mat is selected. In the 12 hour format, bit 5 is the AM/

PM bit with logic one being PM. In the 24 hour mode,

bit 5 is the second 10 hour bit(20-23 hours). The Time

of Day registers are updated every 0.01 seconds from

the real time Clock, except when the TE bit (bit 7 of

ning. The preferred method of synchronizing data ac-

cess to and from the RAM + Timekeeper is to access

the Command register by doing a write cycle to ad-

dress location 0B and setting the TE bit (Transfer En-

able bit) to a logic zero. This will freeze the External

time of Day register at the present recorded time, al-

lowing access to occur without danger of simultaneous

update. When the watch registers have been read or

written, a second write cycle to location 0B, setting the

TE bit to a logic one, will put the T ime of Day Registers

back to being updated every 0.01 second. No time is

lost in the real time clock because the internal copy of

the time of day register buffer is continually incremented

while the external memory registers are frozen. An al-

ternate method of reading and writing Time of Day reg-

isters is to ignore synchronization. However , any singal

read may give erroneous data as the real time clock

may be in the process of updating the external memory

registers as data is being read. The internal copies of

seconds through years are incremented, and the T ime

of Day Alarm is checked during the period that hun-

dreds of seconds read 99 and are transfered to the

external register when hundredths of seconds roll from

99 to 00. A way of making sure data is valid is to do

multiple reads and compare. Writing the registers can

also produce erroneous results for the same reasons.

A way of making sure that the write cycle has caused

proper update is to do read verifies and re-execute the

write cycle if data is not correct. While the possibility of

erroneous results from reads and write cycle has been

stated, it is worth nothing that the probability of an in-

correct result is kept to a minimum due to the redudant

structure of the RAM + Timekeeper.

TIME OF DAY ALARM REGISTERS

Registers 3, 5, and 7 contain the Time of Day Alarm

Rgisters. Bits 3, 4, 5, and 6 of Register 7 will always

read zero regardless of how they are written. Bit 7 of

Registers 3, 5, and 7 are mask bits. When all of the

mask bits are logic zero, a Time of Day Alarm will only

occur when Registers 2, 4, and 6 match the values

stored in Registers 3, 5, and 7. An alarm will be gener-

ated every day when bit 7 of Register 7 is set to a logic

one. Similarly, an alarm is generated every hour when

bit 7 of Registers 7 and 5 is set to a logic 1. When bit 7

of Registers 7, 5, and 3 is set to logic 1 an alarm will

occur every minute when register 1 (seconds) rolls from

59 to 00.

Time of Day Alarm Registers are written and read in

the same format as the Time of Day Registers. The

T ime of Day Alarm Flag and Interrupt is always cleared

when Alarm Registers are read or written.

WATCHDOG ALARM REGISTERS

Registers C and D contain the time for the Watchdog

Alarm. The two registers contain a time count from

00.01 to 99.99 seconds in BCD. The value written into

the Watchdog Alarm Registers can be written or read

in any order. Any access to Register C or D will cause

the Watchdog Alarm to reinitialize and clears the Watch-

dog flag Bit and the Watchdog Interrupt Output. When

a new value is entered or the Watchdog Registers are

read, the Watchdog Timer will start counting down from

the entered value to zero. When zero is reached, the

Watchdog Interrupt Output will go to the active state.

The Watchdog Timer Countdown is interrupted and

reinitialized back to the entered value every time either

of the registers are accessed. In this manner , controlled

periodic accesses to the Watchdog Timer can prevent

the Watchdog Alarm from going to an active level. If

access does not occur , countdown alarm will be repeti-

tive. The Watchdog Alarm Registers always read the

entered value. The actual count-down register is inter-

nal and is not readable. Writing registers C and D to

zero will disable the Watchdog Alarm feature.

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

IM1486 RAM + TIMEKEEPER REGISTERS

SSERDDA7tiB6tiB5tiB4tiB3tiB2tiB1tiB0tiBegnaR

0SDNOCES1.0SDNOCES10.099-00

10 SDNOCES01SDNOCES95-00

20 SETUNIM01SETUNIM95-00

3M MRALANIM01MRALANIM95-00

4042/21SRUOH

P/A+21-10

32-00

5M42/21MRALARH

P/A+21-10

32-00

6 00000 SYAD70-10

7 M0000 MRALAYAD70-10

800 ETAD01ETAD13-10

9CSOEWQSE0OM01SHTNOM21-10

ASRAEY01SRAEY99-00

BETWSPIMAWMDTFAWFDT

CSDNOCES1.0SDNOCES10.099-00

DSDNOCES01SDNOCES99-00

FFFF1

10 10

A/P

IBH LO PU LVL

USER RAM AREA END

USER RAM AREA START

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

COMMAND REGISTER

Address location 0Bh is the Command register where

mask bits, control bits and flag bits reside. The

operation of each bit is as follows:

TE - Bit 7 T ransfer enable - This bit when set to a logic

0 will disable the transfer of data between internal and

external clock registers. The contents in the external

clock registers are now frozen and reads or writes will

not be affected with updates. This bit must be set to a

logic 1 to allow updates.

IPSW - Bit 6 Interrupt switch - When set to a logic 1,

INTA is the Time of day Alarm and INTB (INTB) is the

Watchdog Alarm. When set to logic 0, this bit reverses

the output pins. INTA is now the Watchdog Alarm out-

put and INTB(INTB) is the Time of Day Alarm output.

The INTA/SQW output pin shares both the interrupt A

and square wave ouput function. INTA and the square

wave function(SQW) should never be simultaneously

enabled or a conflict may occur.

IBH/LO - Bit 5 Interrupt B Sink or Source Current - When

this bit is set to a logic 1 and Vcc is applied, INTB/

(INTB) will source current (see DC characteristics IOH).

When this bit is set to a logic 0, INTB will sink current

(see DC characteristics IOL).

PU/LVL - Bit 4 Interrupt pulse mode or level mode -

This bit determines whether both interrupts will output

a pulse or level signal. When set to a logic 0, INTA and

INTB/(INTB) will be in the level mode. When this bit is

set to a logic 1, the pulse mode is selected and INTA

will sink current for a minimum of 3 ms and then re-

lease. INTB/(INTB) will either sink or source current,

depending on the condition of Bit 5, for a minimum of 3

ms and then release.

TDM - Bit 2 Time of Day Alarm Mask - when this bit is

set to a logic 0, the T ime of Day Alarm Interrupt output

will be activated. The Activated state is determined by

bits 0, 4, 5, and 6 of the COMMAND REGISTER. When

this bit is set to a logic 1, the Time of Day Alarm inter-

rupt output is deactivated.

WAF - Bit 1 Watchdog Alarm Flag - This bit is set to a

logic 1 when a watchdog alarm interrupt occurs. This

bit is read only.

The bit is reset when any of the W atchdog Alarm regis-

ters are accessed.

When the interrupt is in the pulse mode (see bit 4 defi-

nition), this flag will be in the logic 1 state only during

the time the interrupt is active.

TDF - Bit 0 Time of Day Flag - This is a read only bit.

This bit is set to a logic 1 when a Time of Day alarm

has occured. The time the alarm occured can be de-

termined by reading the Time of Day Alarm registers.

This bit is reset to a logic 0 state when any of the T ime

of Day Alarm registers are accessed.

When the interrupt is in the pulse mode (see bit 4 defi-

nition), this flag will be in the logic 1 state only during

the time the interrupt is active.

WAM - Bit 3 Watchdog Alarm Mask - When this bit is

set to a logic 0, the Watchdog Interrupt output will be

activated. The activated state is determined by bits 1,

4, 5, and 6 of the COMMAND REGISTER. When this

bit is set to a logic 1, the Watchdog interrupt output is

deactivated.

SRETSIGER

SETUNIM)3(SRUOH)5(SYAD)7(

111 ETUNIMREPECNOMRALA

011 HCTAMETUNIMNEHWMRALA

001 HCTAMSETUNIMDNASRUOHNEHWMRALA

000 SYADDNA,SETUNIM,SRUOHNEHWMRALA

HCTAM

TIME OF DAY ALARM MASK BITS

REMARKS

NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTING PRODUCE ILLOGICAL OPERATION

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

ABSOLUTE MAXIMUM RATINGS*

Voltage on any Pin Relative to Ground - 0.3 V to + 7.0 V

Operating Temperature 0OC to 70OC

Storage Temperature - 40OC to + 70OC

Soldering Temperature 260OC for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITONS

DC ELECTRICAL CHARACTERISTICS

(0OC to 70OC)

(0OC to 70OC; Vcc = 5V +/- 10%)

RETEMARAPLOBMYSNIMPYTXAMSTINU

egatloVylppuSccV5.40.55.5V

1cigoLtupnIV

2.23.0+ccVV

0cigoLtupnIV

3.0-8.0+V

RETEMARAPLOBMYSNIMPYTXAMSTINUSETON

tnerruCegakaeLtupnII

0.1-0.1+Au

tnerruCegakaeltuptuOI

0.1-0.1+Au

tnerruCegakaeLO/II

OIL

0.1-0.1+Au

V4.2@tnerruCtuptuOI

0.1-Am

V4.0@tnerruCtuptuOI

1.2Am31

V2.2=ECtnerruCybdnatSI

1SCC

0.30.7Am

5.0-ccV=ECtnerruCybdnatSI

2SCC

0.4Am

tnerruCevitcAI

58Am

egatloVnoitcetorPetirWV

52.4V

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

CAPACITANCE

LOBMYSRETEMARAPPYT.XAMSTINU

ecnaticapaCtupnI751Fp

TUO

tuptuO

ecnaticapaC 751Fp

tuptuO/tupnI

ecnaticapaC 751Fp

AC ELECTRICAL CHARACTERISTICS

(tA = 25OC)

(0OC to 70OC; Vcc = 5V +/- 10%)

AC TEST CONDITIONS

Input Levels : 0V to 3V

Transition Times : 5ns

SRETEMARAPLOBMYS.NIM.XAMSTINUSETON

emITelcyCdaeRt

021sn1

emiTsseccAt

CCA

021sn

dilaVtuptuOotEOt

001sn

dilaVtuptuOotECt

021sn

evitcAtuptuOotECroEOt

EOC

01sn

noitceleseDmorfZhgiHtuptuOt

04sn

sserddAmorfdloHtuptuO

egnahC t

01sn

emiTelcyCetirWt

021sn

htdiWesluPetirWt

011sn3

emiTputeSsserddAt

0sn

emiTyrevoceRetirWt

01sn

EWmorfZhgiHtuptuOt

WDO

04sn

EWmorfevitcAtuptuOt

WEO

01sn

emiTputeSataDt

58sn4

EWmorfemiTdloHataDt

01sn5,4

htdiWesluPBTNI,ATNIt

WPI

3sm21,11

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

WRITE CYCLE 1 (Notes 2, 6, 7)

READ CYCLE (Note 1)

Address VIH VIH

VIH VIL

VIH

VIH VIL

VIH

tCOE

tOD

VOL

VOH

VOL

DOUT OUTPUT

DATA

VALID

VIL VIL

tACC

tCO

tOH

tRC

tOE

tAW

VIL VIL

VIH VIH

VIH

VIL VIL

tAW

tWP tWR

tODW tOEW

High

Impedance

DOUT tDS tDH1

VIL

VIH

VIH Data In

Stable

DIN

tWC

ADDRESS

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

WRITE CYCLE 2 (Notes 2, 8)

VIH VIL VIL VIH

VIL VIL

tODW

tCOE

tDS tDH

VIL

VIH

VIH Data In

Stable

DIN

VIL VIL

VIH VIH

tAW tWP

tWR

DOUT

ADDRESSES

tWC

POWER-UP / POWER-DOWN CONDITION

TIMING DIAGRAM: INTERRUPT OUTPUTS PULSE MODE (NOTES 11, 12)

Vcc

POWER FAIL

VIH

tREC

4.5V

4.25V

4.0V

VIH tPF tF

4.5V

4.25V 4.0V

VBAT

tFB

INTA, INTB

INTB

tIPW

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog

AC ELECTRICAL CHARACTERISTICS POWER-UP/POWER DOWN TIMING

(0OC to 70OC)

RETEMARAPLOBMYSNIMXAMSTINUSETON

liaFrewoPothgiHECt

0sn

pUrewoPtayrevoceRt

CER

002sm

rewoPetaRwelSccV

nwoD t

V5.4<ccV<0.4 003su

rewoPetaRwelSccV

nwoD t

52.4<ccV<0.3

01su

rewoPetaRwelSccV

nwoD t

V0.4>ccV>5.4

0su

noitneteRataDdetcepxEt

01sraey9

AC TEST CONDITONS

Output Load : 50pF + 1TTL Gate

Input Pulse Levels : 0 - 3.0V

Timing Measurement Reference Levels

Input : 1.5V

Output : 1.5 V

Input Pulse Rise and Fail Times : 5ns.

NOTES :

1. WE is high for a read cycle.

2. OE = VI H or VIL . If OE = VI H during write cycle, the output buffers remain in a high impedance state.

3. tWP is specified as the logical AND of the CE and WE. tWP is measured from the latter of CE of WE going low

to the earlier of CE or WE going high.

4. tDS or tDH are measured from the earlier of CE or WE going high.

5. tDH is measured from WE going high. If CE is used to terminate the write cycle, then t DH = 20 ns.

6. If the CE low transition occurs simultaneously with or later than the WE low transition Write Cycle 1, the ouput

bufers remain in a high impedance state during this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers

remain in a high impedance state during this period.

8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transiton, the output

buffers remain in a high impedance state during this period.

9. Each IM1486 is marked with a four digit date code mm-yy. mm designates the month of manufacture. yy

designates the year of manufacture. The expected tDR is defined as starting at the data of manufacture.

10. All voltages are referenced to ground.

11. Applies to both interrupts pins when the alarms are set to pulse.

12. Interrupt Output occurs within 100 ns on the alarm condition existing.

13. Both INTA and INTB (INTB) are open drain outputs.

WARNING :

Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

G E

DIM IN INCHES MIN. MAX.

A 1.720 1.740

B 0.720 0.740

C 0.395 0.415

D 0.090 0.120

E 0.015 0.021

F 0.120 0.160

G 0.090 0.110

H 0.590 0.630

J 0.008 0.012

INNOVATIVE

IM1486 - 120

SRAM + RTC + WATCHDOG

mm-yy

INNOVATIVE IM1486Y-120

SRAM + RTC + Watchdog