MCF5407 ColdFire(R) Integrated Microprocessor User's Manual MCF5407UM/D Rev. 0.1, 11/2001 ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. 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Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Document Comments: FAX (512) 895-2638, Attn: TECD Applications Engineering (c) Motorola Inc., 2001. All rights reserved. Overview Part I: MCF5407 Processor Core 1 Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Part II SIM Overview 6 Phase-Locked Loop (PLL) 7 I2C Module 8 Interrupt Controller 9 Chip-Select Module 10 Synchronous/Asynchronous DRAM Controller Module 11 Part III: Peripheral Module Part III DMA Controller Module 12 Timer Module 13 UART Modules 14 Parallel Port (General-Purpose I/O) 15 Part IV: Hardware Interface Part IV Mechanical Data 16 Signal Descriptions 17 Bus Operation 18 IEEE 1149.1 Test Access Port (JTAG) 19 Electrical Specifications 20 Appendix A: Migration A Appendix B: Memory Map B Glossary of Terms and Abbreviations GLO Index IND IND B GLO IND 1 Part I Overview Part I: MCF5407 Processor Core 2 ColdFire Core 3 Hardware Multiply/Accumulate (MAC) Unit 4 Local Memory 5 Debug Support Part II Part II: System Integration Module (SIM) 6 SIM Overview 7 Phase-Locked Loop (PLL) 8 I2C Module 9 Interrupt Controller 10 Chip-Select Module 11 Synchronous/Asynchronous DRAM Controller Module Part III Part III: Peripheral Module 12 DMA Controller Module 13 Timer Module 14 UART Modules 15 Parallel Port (General-Purpose I/O) Part IV Part IV: Hardware Interface 16 Mechanical Data 17 Signal Descriptions 18 Bus Operation 19 IEEE 1149.1 Test Access Port (JTAG) 20 Electrical Specifications A Appendix A: Migration B Appendix B: Memory Map GLO Glossary of Terms and Abbreviations IND Index CONTENTS Paragraph Number Title Page Number Chapter 1 Overview 1.1 1.2 1.2.1 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.2 1.3.2.1 1.3.2.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.8.1 1.3.8.2 1.3.8.3 1.3.8.4 1.3.8.5 1.3.9 1.3.10 1.4 1.4.1 1.4.2 Features ............................................................................................................... 1-1 MCF5407 Features.............................................................................................. 1-4 Process ............................................................................................................ 1-7 ColdFire Module Description ............................................................................. 1-7 ColdFire Core ................................................................................................. 1-7 Instruction Fetch Pipeline (IFP).................................................................. 1-7 Operand Execution Pipeline (OEP) ............................................................ 1-8 MAC Module.............................................................................................. 1-8 Integer Divide Module................................................................................ 1-8 Harvard Architecture ...................................................................................... 1-8 16-Kbyte Instruction Cache/8-Kbyte Data Cache ...................................... 1-9 Internal 2-Kbyte SRAMs ............................................................................ 1-9 DRAM Controller ........................................................................................... 1-9 DMA Controller.............................................................................................. 1-9 UART Modules............................................................................................. 1-10 Timer Module ............................................................................................... 1-11 I2C Module ................................................................................................... 1-11 System Interface ........................................................................................... 1-11 External Bus Interface .............................................................................. 1-11 Chip Selects .............................................................................................. 1-11 16-Bit Parallel Port Interface .................................................................... 1-12 Interrupt Controller ................................................................................... 1-12 JTAG......................................................................................................... 1-12 System Debug Interface................................................................................ 1-12 PLL Module.................................................................................................. 1-13 Programming Model, Addressing Modes, and Instruction Set......................... 1-13 Programming Model ..................................................................................... 1-15 User Registers ............................................................................................... 1-15 Contents v CONTENTS Paragraph Number 1.4.3 1.4.4 Title Page Number Supervisor Registers ..................................................................................... 1-16 Instruction Set ............................................................................................... 1-16 Part I MCF5407 Processor Core Chapter 2 ColdFire Core 2.1 2.1.1 2.1.2 2.1.2.1 2.1.2.1.1 2.1.2.2 2.1.2.2.1 2.1.2.2.2 2.1.2.2.3 2.1.2.3 2.1.3 2.2 2.2.1 2.2.1.1 2.2.1.2 2.2.1.3 2.2.1.4 2.2.1.5 2.2.1.6 2.2.2 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.2.5 2.2.2.6 2.3 2.4 2.4.1 2.4.2 2.5 2.6 2.6.1 vi Features and Enhancements................................................................................ 2-1 Clock-Multiplied Microprocessor Core.......................................................... 2-2 Enhanced Pipelines ......................................................................................... 2-2 Instruction Fetch Pipeline (IFP).................................................................. 2-4 Branch Acceleration ............................................................................... 2-4 Operand Execution Pipeline (OEP) ............................................................ 2-4 Illegal Opcode Handling......................................................................... 2-5 Hardware Multiply/Accumulate (MAC) Unit ........................................ 2-5 Hardware Divide Unit............................................................................. 2-6 Harvard Memory Architecture ................................................................... 2-6 Debug Module Enhancements ........................................................................ 2-6 Programming Model ........................................................................................... 2-7 User Programming Model .............................................................................. 2-8 Data Registers (D0-D7) ............................................................................. 2-8 Address Registers (A0-A6) ........................................................................ 2-9 Stack Pointer (A7, SP) ................................................................................ 2-9 Program Counter (PC) ................................................................................ 2-9 Condition Code Register (CCR) ................................................................. 2-9 MAC Programming Model....................................................................... 2-10 Supervisor Programming Model................................................................... 2-10 Status Register (SR).................................................................................. 2-11 Vector Base Register (VBR) .................................................................... 2-12 Cache Control Register (CACR) .............................................................. 2-12 Access Control Registers (ACR0-ACR3)................................................ 2-12 RAM Base Address Registers (RAMBAR0 and RAMBAR1) ................ 2-12 Module Base Address Register (MBAR) ................................................. 2-12 Integer Data Formats......................................................................................... 2-13 Organization of Data in Registers..................................................................... 2-13 Organization of Integer Data Formats in Registers ...................................... 2-13 Organization of Integer Data Formats in Memory ....................................... 2-14 Addressing Mode Summary ............................................................................. 2-15 Instruction Set Summary................................................................................... 2-15 Additions to the Instruction Set Architecture ............................................... 2-18 MCF5407 User's Manual CONTENTS Paragraph Number 2.6.2 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8 2.8.1 2.8.2 2.9 Title Page Number Instruction Set Summary .............................................................................. Execution Timings ............................................................................................ MOVE Instruction Execution Timing .......................................................... Execution Timings--One-Operand Instructions .......................................... Execution Timings--Two-Operand Instructions.......................................... Miscellaneous Instruction Execution Times................................................. Branch Instruction Execution Times ............................................................ Exception Processing Overview ....................................................................... Exception Stack Frame Definition................................................................ Processor Exceptions .................................................................................... ColdFire Instruction Set Architecture Enhancements....................................... 2-19 2-23 2-25 2-26 2-27 2-29 2-30 2-31 2-32 2-34 2-36 Chapter 3 Hardware Multiply/Accumulate (MAC) Unit 3.1 3.1.0.1 3.1.0.2 3.1.0.3 3.1.0.4 3.2 Overview............................................................................................................. MAC Programming Model......................................................................... General Operation....................................................................................... MAC Instruction Set Summary .................................................................. Data Representation.................................................................................... MAC Instruction Execution Timings.................................................................. 3-1 3-2 3-3 3-4 3-4 3-5 Chapter 4 Local Memory 4.1 4.2 4.3 4.4 4.4.1 4.5 4.5.1 4.6 4.7 4.8 4.8.1 4.8.2 4.9 4.9.1 4.9.1.1 4.9.1.2 4.9.1.3 Interactions between Local Memory Modules ................................................... 4-1 SRAM Overview ................................................................................................ 4-1 SRAM Operation ................................................................................................ 4-2 SRAM Programming Model............................................................................... 4-3 SRAM Base Address Registers (RAMBAR0/RAMBAR1)........................... 4-3 SRAM Initialization............................................................................................ 4-4 SRAM Initialization Code .............................................................................. 4-5 Power Management ............................................................................................ 4-6 Cache Overview.................................................................................................. 4-6 Cache Organization............................................................................................. 4-8 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified............. 4-8 The Cache at Start-Up..................................................................................... 4-9 Cache Operation................................................................................................ 4-11 Caching Modes ............................................................................................. 4-13 Cacheable Accesses .................................................................................. 4-14 Write-Through Mode (Data Cache Only)................................................. 4-14 Copyback Mode (Data Cache Only)......................................................... 4-14 Contents vii CONTENTS Paragraph Number 4.9.2 4.9.3 4.9.3.1 4.9.3.2 4.9.3.3 4.9.3.4 4.9.4 4.9.5 4.9.5.1 4.9.5.2 4.9.5.2.1 4.9.5.2.2 4.9.6 4.10 4.10.1 4.10.2 4.11 4.12 4.12.1 4.12.2 4.13 Title Page Number Cache-Inhibited Accesses ............................................................................. Cache Protocol.............................................................................................. Read Miss ................................................................................................. Write Miss (Data Cache Only) ................................................................. Read Hit .................................................................................................... Write Hit (Data Cache Only) .................................................................... Cache Coherency (Data Cache Only)........................................................... Memory Accesses for Cache Maintenance................................................... Cache Filling............................................................................................. Cache Pushes ............................................................................................ Push and Store Buffers ......................................................................... Push and Store Buffer Bus Operation................................................... Cache Locking .............................................................................................. Cache Registers................................................................................................. Cache Control Register (CACR) .................................................................. Access Control Registers (ACR0-ACR3).................................................... Cache Management........................................................................................... Cache Operation Summary ............................................................................... Instruction Cache State Transitions .............................................................. Data Cache State Transitions........................................................................ Cache Initialization Code.................................................................................. 4-14 4-15 4-16 4-16 4-16 4-17 4-17 4-17 4-17 4-18 4-18 4-18 4-19 4-21 4-21 4-23 4-24 4-27 4-27 4-28 4-32 Chapter 5 Debug Support 5.1 5.2 5.2.1 5.3 5.3.1 5.3.2 5.3.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 viii Overview............................................................................................................. 5-1 Signal Descriptions ............................................................................................. 5-2 Processor Status/Debug Data (PSTDDATA[7:0]) ......................................... 5-3 Real-Time Trace Support.................................................................................... 5-4 Begin Execution of Taken Branch (PST = 0x5) ............................................. 5-6 Processor Stopped or Breakpoint State Change (PST = 0xE) ........................ 5-7 Processor Halted (PST = 0xF) ........................................................................ 5-7 Programming Model ........................................................................................... 5-8 Address Attribute Trigger Registers (AATR, AATR1)................................ 5-10 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) ............. 5-12 BDM Address Attribute Register (BAAR)................................................... 5-12 Configuration/Status Register (CSR)............................................................ 5-13 Data Breakpoint/Mask Registers (DBR/DBR1, DBMR/DBMR1) ............ 5-15 Program Counter Breakpoint/Mask Registers (PBR, PBR1, PBR2, PBR3, PBMR) ........................................................ 5-16 Trigger Definition Register (TDR) ............................................................... 5-18 Extended Trigger Definition Register (XTDR) ............................................ 5-19 MCF5407 User's Manual CONTENTS Paragraph Number 5.4.9 5.5 5.5.1 5.5.2 5.5.2.1 5.5.2.2 5.5.3 5.5.3.1 5.5.3.1.1 5.5.3.2 5.5.3.3 5.5.3.3.1 5.5.3.3.2 5.5.3.3.3 5.5.3.3.4 5.5.3.3.5 5.5.3.3.6 5.5.3.3.7 5.5.3.3.8 5.5.3.3.9 5.5.3.3.10 5.5.3.3.11 5.5.3.3.12 5.5.3.3.13 5.6 5.6.1 5.6.1.1 5.6.2 5.7 5.8 5.8.1 5.8.2 Title Page Number Resulting Set of Possible Trigger Combinations.......................................... Background Debug Mode (BDM) .................................................................... CPU Halt....................................................................................................... BDM Serial Interface.................................................................................... Receive Packet Format ............................................................................. Transmit Packet Format............................................................................ BDM Command Set...................................................................................... ColdFire BDM Command Format............................................................ Extension Words as Required............................................................... Command Sequence Diagrams................................................................. Command Set Descriptions ...................................................................... Read A/D Register (RAREG/RDREG) ..................................................... Write A/D Register (WAREG/WDREG)................................................... Read Memory Location (READ)............................................................ Write Memory Location (WRITE) ......................................................... Dump Memory Block (DUMP) .............................................................. Fill Memory Block (FILL) ..................................................................... Resume Execution (GO)........................................................................ No Operation (NOP) .............................................................................. Synchronize PC to the PSTDDATA Lines (SYNC_PC) ........................ Read Control Register (RCREG) ............................................................ Write Control Register (WCREG) .......................................................... Read Debug Module Register (RDMREG) ............................................. Write Debug Module Register (WDMREG) ........................................... Real-Time Debug Support ................................................................................ Theory of Operation...................................................................................... Emulator Mode ......................................................................................... Concurrent BDM and Processor Operation .................................................. Motorola-Recommended BDM Pinout............................................................. Debug C Definition of PSTDDATA Outputs................................................... User Instruction Set ...................................................................................... Supervisor Instruction Set............................................................................. 5-21 5-22 5-22 5-24 5-25 5-26 5-26 5-27 5-28 5-28 5-30 5-30 5-31 5-32 5-33 5-35 5-37 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-45 5-46 5-48 5-48 5-49 5-49 5-50 5-53 Part II System Integration Module (SIM) Chapter 6 SIM Overview 6.1 6.2 6.2.1 Features ............................................................................................................... 6-1 Programming Model ........................................................................................... 6-3 SIM Register Memory Map............................................................................ 6-3 Contents ix CONTENTS Paragraph Number 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.10.1 6.2.10.1.1 6.2.10.1.2 Title Page Number Module Base Address Register (MBAR) ....................................................... 6-4 Reset Status Register (RSR) ........................................................................... 6-5 Software Watchdog Timer.............................................................................. 6-6 System Protection Control Register (SYPCR) ............................................... 6-8 Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9 Software Watchdog Service Register (SWSR)............................................... 6-9 PLL Clock Control for CPU STOP Instruction ............................................ 6-10 Pin Assignment Register (PAR) ................................................................... 6-10 Bus Arbitration Control ................................................................................ 6-11 Default Bus Master Park Register (MPARK) .......................................... 6-11 Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12 Arbitration between Internal and External Masters for Accessing Internal Resources ......................................................... 6-14 Chapter 7 Phase-Locked Loop (PLL) 7.1 7.1.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 7.4.1 7.4.2 7.5 Overview............................................................................................................. PLL:PCLK Ratios........................................................................................... PLL Operation .................................................................................................... Reset/Initialization .......................................................................................... Normal Mode.................................................................................................. Reduced-Power Mode..................................................................................... PLL Control Register (PLLCR)...................................................................... PLL Port List....................................................................................................... Timing Relationships .......................................................................................... PCLK, PSTCLK, and BCLKO ....................................................................... RSTI Timing ................................................................................................... PLL Power Supply Filter Circuit ........................................................................ 7-1 7-2 7-2 7-2 7-2 7-3 7-3 7-4 7-4 7-4 7-5 7-6 Chapter 8 I2C Module 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.5 x Overview............................................................................................................. Interface Features................................................................................................ I2C System Configuration................................................................................... I2C Protocol ........................................................................................................ Arbitration Procedure ..................................................................................... Clock Synchronization.................................................................................... Handshaking ................................................................................................... Clock Stretching ............................................................................................. Programming Model ........................................................................................... MCF5407 User's Manual 8-1 8-1 8-3 8-3 8-4 8-5 8-5 8-5 8-6 CONTENTS Paragraph Number 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 Title Page Number I2C Address Register (IADR) ......................................................................... 8-6 I2C Frequency Divider Register (IFDR)......................................................... 8-6 I2C Control Register (I2CR) ........................................................................... 8-7 I2C Status Register (I2SR).............................................................................. 8-8 I2C Data I/O Register (I2DR) ......................................................................... 8-9 I2C Programming Examples ............................................................................. 8-10 Initialization Sequence.................................................................................. 8-10 Generation of START................................................................................... 8-10 Post-Transfer Software Response................................................................. 8-11 Generation of STOP...................................................................................... 8-12 Generation of Repeated START................................................................... 8-12 Slave Mode ................................................................................................... 8-13 Arbitration Lost............................................................................................. 8-13 Chapter 9 Interrupt Controller 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 Overview............................................................................................................. Interrupt Controller Registers ............................................................................. Interrupt Control Registers (ICR0-ICR9) ...................................................... Autovector Register (AVR) ............................................................................ Interrupt Pending and Mask Registers (IPR and IMR)................................... Interrupt Port Assignment Register (IRQPAR) .............................................. 9-1 9-2 9-3 9-5 9-6 9-7 Chapter 10 Chip-Select Module 10.1 10.2 10.3 10.3.1 10.3.1.1 10.3.1.2 10.4 10.4.1 10.4.1.1 10.4.1.2 10.4.1.3 10.4.1.4 Overview........................................................................................................... Chip-Select Module Signals ............................................................................. Chip-Select Operation....................................................................................... General Chip-Select Operation..................................................................... 8-, 16-, and 32-Bit Port Sizing.................................................................. Global Chip-Select Operation................................................................... Chip-Select Registers........................................................................................ Chip-Select Module Registers ...................................................................... Chip-Select Address Registers (CSAR0-CSAR7) ................................... Chip-Select Mask Registers (CSMR0-CSMR7)...................................... Chip-Select Control Registers (CSCR0-CSCR7) .................................... Code Example........................................................................................... 10-1 10-1 10-2 10-3 10-4 10-4 10-5 10-6 10-6 10-7 10-8 10-9 Chapter 11 Synchronous/Asynchronous DRAM Controller Module Contents xi CONTENTS Paragraph Number 11.1 11.1.1 11.1.2 11.2 11.2.1 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.3 11.3.3.1 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.4 11.4.1 11.4.2 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 11.4.4 11.4.4.1 11.4.4.2 11.4.4.3 11.4.4.4 11.4.4.5 11.4.4.6 11.4.5 11.4.5.1 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 xii Title Page Number Overview........................................................................................................... 11-1 Definitions .................................................................................................... 11-2 Block Diagram and Major Components ....................................................... 11-2 DRAM Controller Operation ............................................................................ 11-3 DRAM Controller Registers ......................................................................... 11-3 Asynchronous Operation .................................................................................. 11-4 DRAM Controller Signals in Asynchronous Mode...................................... 11-4 Asynchronous Register Set........................................................................... 11-4 DRAM Control Register (DCR) in Asynchronous Mode ........................ 11-4 DRAM Address and Control Registers (DACR0/DACR1) ..................... 11-5 DRAM Controller Mask Registers (DMR0/DMR1) ................................ 11-7 General Asynchronous Operation Guidelines .............................................. 11-8 Non-Page-Mode Operation..................................................................... 11-11 Burst Page-Mode Operation ................................................................... 11-12 Continuous Page Mode........................................................................... 11-13 Extended Data Out (EDO) Operation..................................................... 11-15 Refresh Operation ................................................................................... 11-16 Synchronous Operation................................................................................... 11-16 DRAM Controller Signals in Synchronous Mode...................................... 11-17 Using Edge Select (EDGESEL) ................................................................. 11-18 Synchronous Register Set ........................................................................... 11-19 DRAM Control Register (DCR) in Synchronous Mode......................... 11-19 DRAM Address and Control Registers (DACR0/DACR1) in Synchronous Mode ......................................................................... 11-20 DRAM Controller Mask Registers (DMR0/DMR1) .............................. 11-22 General Synchronous Operation Guidelines............................................... 11-23 Address Multiplexing ............................................................................. 11-23 Interfacing Example................................................................................ 11-27 Burst Page Mode..................................................................................... 11-27 Continuous Page Mode........................................................................... 11-29 Auto-Refresh Operation.......................................................................... 11-31 Self-Refresh Operation ........................................................................... 11-32 Initialization Sequence................................................................................ 11-32 Mode Register Settings........................................................................... 11-33 SDRAM Example ........................................................................................... 11-34 SDRAM Interface Configuration................................................................ 11-34 DCR Initialization....................................................................................... 11-35 DACR Initialization.................................................................................... 11-35 DMR Initialization...................................................................................... 11-37 Mode Register Initialization ....................................................................... 11-38 Initialization Code....................................................................................... 11-39 MCF5407 User's Manual CONTENTS Paragraph Number Title Page Number Part III Peripheral Module Chapter 12 DMA Controller Module 12.1 12.1.1 12.2 12.3 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.5 12.5.1 12.5.2 12.5.2.1 12.5.2.2 12.5.3 12.5.3.1 12.5.3.2 12.5.4 12.5.4.1 12.5.4.2 12.5.4.3 12.5.5 Overview........................................................................................................... 12-1 DMA Module Features ................................................................................. 12-2 DMA Signal Description .................................................................................. 12-2 DMA Transfer Overview.................................................................................. 12-4 DMA Controller Module Programming Model................................................ 12-5 Source Address Registers (SAR0-SAR3) .................................................... 12-7 Destination Address Registers (DAR0-DAR3) ........................................... 12-7 Byte Count Registers (BCR0-BCR3)........................................................... 12-7 DMA Control Registers (DCR0-DCR3)...................................................... 12-8 DMA Status Registers (DSR0-DSR3) ....................................................... 12-10 DMA Interrupt Vector Registers (DIVR0-DIVR3) ................................... 12-11 DMA Controller Module Functional Description........................................... 12-11 Transfer Requests (Cycle-Steal and Continuous Modes) ........................... 12-12 Data Transfer Modes .................................................................................. 12-12 Dual-Address Transfers .......................................................................... 12-12 Single-Address Transfers........................................................................ 12-13 Channel Initialization and Startup .............................................................. 12-13 Channel Prioritization ............................................................................. 12-13 Programming the DMA Controller Module ........................................... 12-13 Data Transfer .............................................................................................. 12-14 External Request and Acknowledge Operation ...................................... 12-14 Auto-Alignment ...................................................................................... 12-17 Bandwidth Control.................................................................................. 12-18 Termination................................................................................................. 12-18 Chapter 13 Timer Module 13.1 13.1.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 Overview........................................................................................................... Key Features ................................................................................................. General-Purpose Timer Units ........................................................................... General-Purpose Timer Programming Model .................................................. Timer Mode Registers (TMR0/TMR1) ........................................................ Timer Reference Registers (TRR0/TRR1) ................................................... Timer Capture Registers (TCR0/TCR1)....................................................... Timer Counters (TCN0/TCN1) .................................................................... Contents 13-1 13-2 13-2 13-2 13-3 13-4 13-4 13-5 xiii CONTENTS Paragraph Number 13.3.5 13.4 13.5 Title Page Number Timer Event Registers (TER0/TER1)........................................................... 13-5 Code Example................................................................................................... 13-6 Calculating Time-Out Values ........................................................................... 13-7 Chapter 14 UART Modules 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.3.10 14.3.11 14.3.12 14.3.13 14.3.14 14.3.15 14.3.16 14.3.17 14.3.18 14.3.19 14.4 14.5 14.5.1 14.5.1.1 14.5.1.2 14.5.1.2.1 14.5.1.2.2 14.5.2 14.5.2.1 14.5.2.2 14.5.2.2.1 14.5.2.3 14.5.2.4 xiv Overview........................................................................................................... 14-1 Serial Module Overview ................................................................................... 14-2 Register Descriptions ........................................................................................ 14-3 UART Mode Registers 1 (UMR1n).............................................................. 14-5 UART Mode Register 2 (UMR2n) ............................................................... 14-7 Rx FIFO Threshold Register (RXLVL)........................................................ 14-8 Modem Control Register (MODCTL).......................................................... 14-9 Tx FIFO Threshold Register (TXLVL) ...................................................... 14-10 UART Status Registers (USRn) ................................................................. 14-10 UART Clock-Select Registers (UCSRn).................................................... 14-12 Receive Samples Available Register (RSMP)............................................ 14-12 Transmit Space Available Register (TSPC) ............................................... 14-13 UART Command Registers (UCRn) .......................................................... 14-13 UART Receiver Buffers (URBn) ............................................................... 14-15 UART Transmitter Buffers (UTBn) ........................................................... 14-16 UART Input Port Change Registers (UIPCRn).......................................... 14-17 UART Auxiliary Control Register (UACRn)............................................. 14-17 UART Interrupt Status/Mask Registers (UISRn/UIMRn).......................... 14-18 UART Divider Upper/Lower Registers (UDUn/UDLn) ............................ 14-19 UART Interrupt Vector Register (UIVRn)................................................. 14-20 UART Input Port Register (UIPn) .............................................................. 14-20 UART Output Port Data Registers (UOP1n/UOP0n)................................. 14-21 UART Module Signal Definitions .................................................................. 14-21 Operation......................................................................................................... 14-23 Transmitter/Receiver Clock Source............................................................ 14-23 Programmable Divider............................................................................ 14-24 Calculating Baud Rates........................................................................... 14-24 CLKIN Baud Rates............................................................................. 14-24 External Clock .................................................................................... 14-25 Transmitter and Receiver Operating Modes............................................... 14-25 Transmitting in UART Mode ................................................................. 14-26 Transmitter in Modem Mode (UART1) ................................................. 14-27 AC `97 Low-Power Mode .................................................................. 14-29 Receiver .................................................................................................. 14-29 UART1 in UART Mode ......................................................................... 14-31 MCF5407 User's Manual CONTENTS Paragraph Number 14.5.2.4.1 14.5.2.5 14.5.2.6 14.5.3 14.5.3.1 14.5.3.2 14.5.3.3 14.5.4 14.5.5 14.5.5.1 14.5.5.2 14.5.5.3 14.5.6 14.5.6.1 Title Page Number Receiver in Modem Mode (UART1).................................................. FIFO Stack in UART0............................................................................ FIFOs in UART1 .................................................................................... Looping Modes ........................................................................................... Automatic Echo Mode ............................................................................ Local Loop-Back Mode .......................................................................... Remote Loop-Back Mode....................................................................... Multidrop Mode.......................................................................................... Bus Operation ............................................................................................. Read Cycles ............................................................................................ Write Cycles ........................................................................................... Interrupt Acknowledge Cycles ............................................................... Programming .............................................................................................. UART Module Initialization Sequence .................................................. 14-31 14-32 14-33 14-34 14-34 14-34 14-35 14-35 14-37 14-37 14-37 14-37 14-37 14-38 Chapter 15 Parallel Port (General-Purpose I/O) 15.1 15.1.1 15.1.2 15.1.3 15.1.4 Parallel Port Operation...................................................................................... Pin Assignment Register (PAR) ................................................................... Port A Data Direction Register (PADDR).................................................... Port A Data Register (PADAT) .................................................................... Code Example............................................................................................... 15-1 15-1 15-2 15-2 15-4 Part IV Hardware Interface Chapter 16 Mechanical Data 16.1 16.2 16.3 16.4 Package ............................................................................................................. Pinout ................................................................................................................ Mechanical Diagram......................................................................................... Case Drawing.................................................................................................... 16-1 16-1 16-8 16-9 Chapter 17 Signal Descriptions 17.1 17.2 17.2.1 Overview........................................................................................................... 17-1 MCF5407 Bus Signals ...................................................................................... 17-7 Address Bus .................................................................................................. 17-7 Contents xv CONTENTS Paragraph Number 17.2.1.1 17.2.1.2 17.2.2 17.2.3 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 17.3 17.3.1 17.4 17.4.1 17.4.2 17.4.3 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 17.5.5.1 17.5.5.2 17.5.5.3 17.5.5.4 17.5.6 17.5.6.1 17.6 17.6.1 17.6.2 17.6.3 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.8 17.8.1 xvi Title Page Number Address Bus (A[23:0]).............................................................................. 17-7 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7 Data Bus (D[31:0]) ....................................................................................... 17-8 Read/Write (R/W)......................................................................................... 17-8 Size (SIZ[1:0]) .............................................................................................. 17-8 Transfer Start (TS) ........................................................................................ 17-9 Address Strobe (AS) ..................................................................................... 17-9 Transfer Acknowledge (TA) ......................................................................... 17-9 Transfer In Progress (TIP/PP7)................................................................... 17-10 Transfer Type (TT[1:0]/PP[1:0]) ................................................................ 17-10 Transfer Modifier (TM[2:0]/PP[4:2]/DACK[1:0])..................................... 17-10 Interrupt Control Signals................................................................................. 17-12 Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, and IRQ7)....... 17-12 Bus Arbitration Signals................................................................................... 17-12 Bus Request (BR) ....................................................................................... 17-12 Bus Grant (BG).......................................................................................... 17-12 Bus Driven (BD)......................................................................................... 17-13 Clock and Reset Signals.................................................................................. 17-13 Reset In (RSTI)........................................................................................... 17-13 Clock Input (CLKIN).................................................................................. 17-13 Bus Clock Output (BCLKO) ...................................................................... 17-13 Reset Out (RSTO)....................................................................................... 17-13 Data/Configuration Pins (D[7:0]) ............................................................... 17-14 D[7:5,3]--Boot Chip-Select (CS0) Configuration ................................. 17-14 D7--Auto Acknowledge Configuration (AA_CONFIG) ...................... 17-14 D[6:5]--Port Size Configuration (PS_CONFIG[1:0]) ........................... 17-14 D3--Byte-Enable Configuration (BE_CONFIG) .................................. 17-15 D4--Address Configuration (ADDR_CONFIG) ....................................... 17-15 D[2:0]--Divide Control (DIVIDE[2:0]) ................................................ 17-15 Chip-Select Module Signals ........................................................................... 17-15 Chip-Select (CS[7:0]) ................................................................................. 17-15 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16 Output Enable (OE) .................................................................................... 17-16 DRAM Controller Signals .............................................................................. 17-16 Row Address Strobes (RAS[1:0])............................................................... 17-16 Column Address Strobes (CAS[3:0]) ......................................................... 17-16 DRAM Write (DRAMW)........................................................................... 17-16 Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17 Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17 Synchronous DRAM Clock Enable (SCKE) .............................................. 17-17 Synchronous Edge Select (EDGESEL) ...................................................... 17-17 DMA Controller Module Signals.................................................................... 17-17 DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-17 MCF5407 User's Manual CONTENTS Paragraph Number 17.8.2 17.9 17.9.1 17.9.2 17.9.3 17.9.4 17.10 17.10.1 17.10.2 17.11 17.12 17.12.1 17.12.2 17.13 17.13.1 17.13.2 17.13.3 17.13.4 17.14 17.14.1 17.14.2 17.14.3 17.14.4 17.14.5 Title Page Number Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) ................ Serial Module Signals ..................................................................................... Transmitter Serial Data Output (TxD)........................................................ Receiver Serial Data Input (RxD)............................................................... Clear to Send (CTS).................................................................................... Request to Send (RTS) ............................................................................... Timer Module Signals..................................................................................... Timer Inputs (TIN[1:0]).............................................................................. Timer Outputs (TOUT1, TOUT0) .............................................................. Parallel I/O Port (PP[15:0]) ............................................................................ I2C Module Signals......................................................................................... I2C Serial Clock (SCL) ............................................................................... I2C Serial Data (SDA) ................................................................................ Debug and Test Signals .................................................................................. Test Mode (MTMOD[3:0]) ........................................................................ High Impedance (HIZ)................................................................................ Processor Clock Output (PSTCLK)............................................................ Processor Status Debug Data (PSTDDATA[7:0])...................................... Debug Module/JTAG Signals......................................................................... Test Reset/Development Serial Clock (TRST/DSCLK) ............................ Test Mode Select/Breakpoint (TMS/BKPT) .............................................. Test Data Input/Development Serial Input (TDI/DSI) ............................... Test Data Output/Development Serial Output (TDO/DSO)....................... Test Clock (TCK) ....................................................................................... 17-18 17-18 17-18 17-19 17-19 17-19 17-19 17-19 17-19 17-19 17-20 17-20 17-20 17-20 17-20 17-20 17-20 17-21 17-21 17-21 17-21 17-22 17-22 17-22 Chapter 18 Bus Operation 18.1 18.2 18.3 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 18.4.7 18.4.7.1 18.4.7.2 18.4.7.3 Features ............................................................................................................. 18-1 Bus and Control Signals.................................................................................... 18-1 Bus Characteristics............................................................................................ 18-2 Data Transfer Operation ................................................................................... 18-2 Bus Cycle Execution..................................................................................... 18-4 Data Transfer Cycle States ........................................................................... 18-5 Read Cycle.................................................................................................... 18-7 Write Cycle ................................................................................................... 18-8 Fast-Termination Cycles............................................................................... 18-9 Back-to-Back Bus Cycles ........................................................................... 18-10 Burst Cycles................................................................................................ 18-11 Line Transfers ......................................................................................... 18-12 Line Read Bus Cycles............................................................................. 18-12 Line Write Bus Cycles............................................................................ 18-14 Contents xvii CONTENTS Paragraph Number 18.4.7.4 18.5 18.6 18.7 18.7.1 18.7.2 18.8 18.8.1 18.9 18.9.1 18.9.2 18.10 18.10.1 18.10.2 Title Page Number Transfers Using Mixed Port Sizes .......................................................... Misaligned Operands ...................................................................................... Bus Errors ....................................................................................................... Interrupt Exceptions........................................................................................ Level 7 Interrupts........................................................................................ Interrupt-Acknowledge Cycle..................................................................... Bus Arbitration................................................................................................ Bus Arbitration Signals............................................................................... General Operation of External Master Transfers............................................ Two-Device Bus Arbitration Protocol (Two-Wire Mode) ......................... Multiple External Bus Device Arbitration Protocol (Three-Wire Mode)... Reset Operation............................................................................................... Master Reset ............................................................................................... Software Watchdog Reset........................................................................... 18-15 18-16 18-17 18-17 18-18 18-19 18-20 18-21 18-21 18-25 18-29 18-33 18-34 18-35 Chapter 19 IEEE 1149.1 Test Access Port (JTAG) 19.1 19.2 19.3 19.4 19.4.1 19.4.2 19.4.3 19.4.4 19.5 19.6 19.7 Overview........................................................................................................... 19-1 JTAG Signal Descriptions ............................................................................... 19-2 TAP Controller.................................................................................................. 19-3 JTAG Register Descriptions ............................................................................. 19-4 JTAG Instruction Shift Register .................................................................. 19-5 IDCODE Register ......................................................................................... 19-6 JTAG Boundary-Scan Register .................................................................... 19-7 JTAG Bypass Register................................................................................ 19-10 Restrictions ..................................................................................................... 19-10 Disabling IEEE Standard 1149.1 Operation ................................................... 19-10 Obtaining the IEEE Standard 1149.1.............................................................. 19-11 Chapter 20 Electrical Specifications 20.1 20.1.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 xviii General Parameters ........................................................................................... 20-1 Supply Voltage Sequencing and Separation Cautions.................................. 20-3 Clock Timing Specifications............................................................................. 20-4 Input/Output AC Timing Specifications........................................................... 20-6 Reset Timing Specifications ........................................................................... 20-15 Debug AC Timing Specifications................................................................... 20-16 Timer Module AC Timing Specifications ...................................................... 20-17 I2C Input/Output Timing Specifications......................................................... 20-18 UART Module AC Timing Specifications ..................................................... 20-19 MCF5407 User's Manual CONTENTS Paragraph Number 20.9 20.10 20.11 Title Page Number Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-22 DMA Timing Specifications........................................................................... 20-23 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-24 Appendix A Migrating from the ColdFire MCF5307 to the MCF5407 A.1 A.2 A.3 A.4 A.5 A.6 A.6.1 A.6.2 A.7 A.8 A.8.1 A.8.2 A.8.2.1 A.8.3 A.8.3.1 A.8.3.2 A.8.3.3 A.8.3.4 A.8.3.5 A.8.4 A.8.5 A.8.6 A.9 A.10 A.11 Overview............................................................................................................ A-1 Instruction Set Additions ................................................................................... A-2 Enhanced Memories........................................................................................... A-3 On-Chip DMA Modifications............................................................................ A-4 UART Enhancements ........................................................................................ A-5 Timing Differences ............................................................................................ A-6 Phase-Locked Loop (PLL)............................................................................. A-6 Timing Relationships..................................................................................... A-7 Reset Initialization Modifications...................................................................... A-8 Revision C Debug ............................................................................................ A-10 Debug Interrupts and Interrupt Requests in Emulator Mode .................................................................................... A-10 On-Chip Breakpoint Registers..................................................................... A-12 Write Debug Module Register (wdmreg) ................................................ A-12 Debug Programming Model ........................................................................ A-14 Address Breakpoint 1 Registers (ABLR1, ABHR1) ............................... A-14 Address Attribute Breakpoint Register 1 (AATR1) ................................ A-14 Program Counter Breakpoint Registers 1-3 (PBR1-PBR3) ................... A-14 Data Breakpoint Register 1 (DBR1, DBMR1) ........................................ A-15 Extended Trigger Definition Register (XTDR) ....................................... A-15 Debug Interrupt Exception Vectors ............................................................. A-15 Processor Status and Debug Data Output Signals ....................................... A-16 Debug C Summary....................................................................................... A-17 Voltage Input Changes..................................................................................... A-17 PLL Power Supply Filter Circuit ..................................................................... A-18 Pin-Assignment Compatibility......................................................................... A-18 Appendix B List of Memory Maps Contents xix CONTENTS Paragraph Number xx Title MCF5407 User's Manual Page Number ILLUSTRATIONS Figure Number 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 5-1 5-2 5-3 5-4 5-5 5-6 Title Page Number MCF5407 Block Diagram............................................................................................. 1-2 UART Module Block Diagram................................................................................... 1-10 PLL Module ................................................................................................................ 1-13 ColdFire MCF5407 Programming Model .................................................................. 1-15 ColdFire Enhanced Pipeline ......................................................................................... 2-3 ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-5 ColdFire Programming Model...................................................................................... 2-8 Condition Code Register (CCR) ................................................................................... 2-9 Status Register (SR).................................................................................................... 2-11 Vector Base Register (VBR)....................................................................................... 2-12 Organization of Integer Data Formats in Data Registers............................................ 2-13 Organization of Integer Data Formats in Address Registers ...................................... 2-14 Memory Operand Addressing..................................................................................... 2-14 Exception Stack Frame Form...................................................................................... 2-33 ColdFire MAC Multiplication and Accumulation........................................................ 3-2 MAC Programming Model ........................................................................................... 3-2 SRAM Base Address Registers (RAMBARn) ............................................................. 4-3 Data Cache Organization .............................................................................................. 4-7 Data Cache Organization and Line Format .................................................................. 4-8 Data Cache--A: at Reset, B: after Invalidation, C and D: Loading Pattern............... 4-10 Data Caching Operation.............................................................................................. 4-11 Write-Miss in Copyback Mode................................................................................... 4-16 Data Cache Locking.................................................................................................... 4-20 Cache Control Register (CACR) ................................................................................ 4-21 Access Control Register Format (ACRn) ................................................................... 4-24 An Format (Data Cache)............................................................................................. 4-25 An Format (Instruction Cache) ................................................................................... 4-25 Instruction Cache Line State Diagram........................................................................ 4-27 Data Cache Line State Diagram--Copyback Mode ................................................... 4-28 Data Cache Line State Diagram--Write-Through Mode ........................................... 4-29 Processor/Debug Module Interface............................................................................... 5-1 PSTCLK Timing........................................................................................................... 5-3 PSTDDATA: Single-Cycle Instruction Timing............................................................ 5-3 Example JMP Instruction Output on PSTDDATA....................................................... 5-6 Debug Programming Model ......................................................................................... 5-9 Address Attribute Trigger Registers (AATR, AATR1).............................................. 5-11 Illustrations xxi ILLUSTRATIONS Figure Page Title Number Number 5-7 Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)............................ 5-12 5-8 BDM Address Attribute Register (BAAR)................................................................. 5-13 5-9 Configuration/Status Register (CSR).......................................................................... 5-13 5-10 Data Breakpoint/Mask Registers (DBR/DBR1 and DBMR/DBMR1)....................... 5-16 5-11 Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3) ........................ 5-17 5-12 Program Counter Breakpoint Mask Register (PBMR) ............................................... 5-17 5-13 Trigger Definition Register (TDR) ............................................................................. 5-18 5-14 Extended Trigger Definition Register (XTDR) .......................................................... 5-20 5-15 BDM Serial Interface Timing ..................................................................................... 5-24 5-16 Receive BDM Packet.................................................................................................. 5-25 5-17 Transmit BDM Packet ................................................................................................ 5-26 5-18 BDM Command Format ............................................................................................. 5-27 5-19 Command Sequence Diagram..................................................................................... 5-29 RAREG/RDREG Command Sequence............................................................................ 5-30 5-21 RAREG/RDREG Command Format ............................................................................... 5-30 5-20 WAREG/WDREG Command Sequence .......................................................................... 5-31 5-23 WAREG/WDREG Command Format.............................................................................. 5-31 5-22 READ Command Sequence.......................................................................................... 5-32 5-25 5-24 read Command/Result Formats................................................................................... 5-32 WRITE Command Format ............................................................................................ 5-33 5-26 WRITE Command Sequence ........................................................................................ 5-34 5-27 DUMP Command/Result Formats ................................................................................ 5-35 5-28 DUMP Command Sequence ......................................................................................... 5-36 5-29 FILL Command Format................................................................................................ 5-37 5-30 FILL Command Sequence............................................................................................ 5-38 5-31 GO Command Sequence.............................................................................................. 5-39 5-33 GO Command Format.................................................................................................. 5-39 5-32 NOP Command Sequence ............................................................................................ 5-40 5-35 NOP Command Format................................................................................................ 5-40 5-34 SYNC_PC Command Sequence .................................................................................... 5-41 5-37 SYNC_PC Command Format........................................................................................ 5-41 5-36 RCREG Command Sequence........................................................................................ 5-42 5-39 RCREG Command/Result Formats............................................................................... 5-42 5-38 WCREG Command Sequence ....................................................................................... 5-43 5-41 WCREG Command/Result Formats.............................................................................. 5-43 5-40 RDMREG Command Sequence..................................................................................... 5-44 5-43 RDMREG bdm Command/Result Formats.................................................................... 5-44 5-42 WDMREG Command Sequence .................................................................................... 5-45 5-45 WDMREG BDM Command Format.............................................................................. 5-45 5-44 5-46 Recommended BDM Connector................................................................................. 5-49 6-1 SIM Block Diagram...................................................................................................... 6-1 6-2 Module Base Address Register (MBAR) ..................................................................... 6-4 6-3 Reset Status Register (RSR) ......................................................................................... 6-5 xxii MCF5407 User's Manual ILLUSTRATIONS Figure Number 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 Title Page Number MCF5407 Embedded System Recovery from Unterminated Access........................... 6-7 System Protection Control Register (SYPCR) ............................................................ 6-8 Software Watchdog Interrupt Vector Register (SWIVR)............................................ 6-9 Software Watchdog Service Register (SWSR)............................................................ 6-9 Pin Assignment Register (PAR) ................................................................................. 6-10 Default Bus Master Register (MPARK) ..................................................................... 6-11 Round Robin Arbitration (PARK = 00)...................................................................... 6-12 Park on Master Core Priority (PARK = 01) ............................................................... 6-13 Park on DMA Module Priority (PARK = 10)............................................................. 6-13 Park on Current Master Priority (PARK = 01) ........................................................... 6-14 PLL Module Block Diagram ........................................................................................ 7-1 PLL Control Register (PLLCR).................................................................................... 7-3 CLKIN, PCLK, PSTCLK, and BCLKO Timing .......................................................... 7-5 Reset and Initialization Timing..................................................................................... 7-6 PLL Power Supply Filter Circuit ................................................................................. 7-6 I2C Module Block Diagram .......................................................................................... 8-2 I2C Standard Communication Protocol ........................................................................ 8-3 Repeated START .......................................................................................................... 8-4 Synchronized Clock SCL.............................................................................................. 8-5 I2C Address Register (IADR) ....................................................................................... 8-6 I2C Frequency Divider Register (IFDR)....................................................................... 8-7 I2C Control Register (I2CR) ......................................................................................... 8-8 I2CR Status Register (I2SR) ......................................................................................... 8-9 I2C Data I/O Register (I2DR) ..................................................................................... 8-10 Flow-Chart of Typical I2C Interrupt Routine............................................................. 8-14 Interrupt Controller Block Diagram.............................................................................. 9-1 Interrupt Control Registers (ICR0-ICR9) .................................................................... 9-3 Autovector Register (AVR) .......................................................................................... 9-5 Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR) ......................... 9-7 Interrupt Port Assignment Register (IRQPAR) ............................................................ 9-7 Connections for External Memory Port Sizes ............................................................ 10-4 Chip Select Address Registers (CSAR0-CSAR7) ..................................................... 10-6 Chip Select Mask Registers (CSMRn) ....................................................................... 10-7 Chip-Select Control Registers (CSCR0-CSCR7) ...................................................... 10-8 Asynchronous/Synchronous DRAM Controller Block Diagram ............................... 11-2 DRAM Control Register (DCR) (Asynchronous Mode) ............................................ 11-5 DRAM Address and Control Registers (DACR0/DACR1)........................................ 11-6 DRAM Controller Mask Registers (DMR0 and DMR1)............................................ 11-7 Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4) .......................... 11-11 Basic Non-Page-Mode Operation RCD = 1, RNCN = 0 (5-5-5-5) .......................... 11-12 Burst Page-Mode Read Operation (4-3-3-3)............................................................. 11-13 Burst Page-Mode Write Operation (4-3-3-3)............................................................ 11-13 Continuous Page-Mode Operation............................................................................ 11-14 Illustrations xxiii ILLUSTRATIONS Figure Page Title Number Number 11-10 Write Hit in Continuous Page Mode......................................................................... 11-15 11-11 EDO Read Operation (3-2-2-2) ................................................................................ 11-15 11-12 DRAM Access Delayed by Refresh ......................................................................... 11-16 11-13 MCF5407 SDRAM Interface.................................................................................... 11-18 11-14 Using EDGESEL to Change Signal Timing............................................................. 11-19 11-15 DRAM Control Register (DCR) (Synchronous Mode) ............................................ 11-19 11-16 DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20 11-17 DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22 11-18 Burst Read SDRAM Access ..................................................................................... 11-28 11-19 Burst Write SDRAM Access .................................................................................... 11-29 11-20 Synchronous, Continuous Page-Mode Access--Consecutive Reads....................... 11-30 11-21 Synchronous, Continuous Page-Mode Access--Read after Write........................... 11-31 11-22 Auto-Refresh Operation............................................................................................ 11-32 11-23 Self-Refresh Operation ............................................................................................. 11-32 11-24 Mode Register Set (mrs) Command ......................................................................... 11-34 11-25 Initialization Values for DCR ................................................................................... 11-35 11-26 SDRAM Configuration............................................................................................. 11-36 11-27 DACR Register Configuration.................................................................................. 11-36 11-28 DMR0 Register ......................................................................................................... 11-37 11-29 Mode Register Mapping to MCF5407 A[31:0] ........................................................ 11-38 12-1 DMA Signal Diagram ................................................................................................. 12-1 12-2 MCF5307/MCF5407 TM[2:0] Pin Remapping .......................................................... 12-4 12-3 Dual-Address Transfer................................................................................................ 12-4 12-4 Single-Address Transfers............................................................................................ 12-5 12-6 Destination Address Registers (DARn) ...................................................................... 12-7 12-5 Source Address Registers (SARn) .............................................................................. 12-7 12-7 Byte Count Registers (BCRn)..................................................................................... 12-8 12-8 DMA Control Registers (DCRn) ............................................................................... 12-8 12-9 DMA Status Registers (DSRn) ................................................................................ 12-10 12-10 DMA Interrupt Vector Registers (DIVRn) ............................................................... 12-11 12-11 DREQ Timing Constraints, Dual-Address DMA Transfer....................................... 12-15 12-12 Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer ................... 12-16 12-13 Single-Address DMA Transfer ................................................................................. 12-17 13-1 Timer Block Diagram ................................................................................................. 13-1 13-2 Timer Mode Registers (TMR0/TMR1) ...................................................................... 13-3 13-3 Timer Reference Registers (TRR0/TRR1) ................................................................. 13-4 13-4 Timer Capture Register (TCR0/TCR1) ...................................................................... 13-5 13-5 Timer Counters (TCN0/TCN1)................................................................................... 13-5 13-6 Timer Event Registers (TER0/TER1)......................................................................... 13-5 14-1 Simplified Block Diagram .......................................................................................... 14-1 14-2 UART Mode Registers 1 (UMR1n)............................................................................ 14-6 14-3 UART Mode Register 2 (UMR2n) ............................................................................. 14-7 14-4 Rx FIFO Threshold Register (RXLVL)...................................................................... 14-8 xxiv MCF5407 User's Manual ILLUSTRATIONS Figure Number 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-24 14-23 14-25 14-26 14-27 14-28 14-29 14-30 14-31 14-32 14-33 14-34 14-35 14-36 14-37 14-38 14-39 15-1 15-2 15-3 16-1 16-2 16-3 17-1 17-2 Title Page Number Modem Control Register (MODCTL) ........................................................................ 14-9 Tx FIFO Threshold Register (TXLVL) .................................................................... 14-10 UART Status Register (USRn) ................................................................................. 14-10 UART Clock-Select Register (UCSRn).................................................................... 14-12 Receive Samples Available Register (RSMP).......................................................... 14-13 Tx Space Available Register (TSPC) ....................................................................... 14-13 UART Command Register (UCRn).......................................................................... 14-14 UART Receiver Buffer for UART0 (URB0)............................................................ 14-16 UART Receiver Buffer for UART1 (URB1)............................................................ 14-16 UART Transmitter Buffer for UART0 (UTB0) ....................................................... 14-16 UART Transmitter Buffer for UART1 (UTB1) ....................................................... 14-17 UART Input Port Change Register (UIPCRn).......................................................... 14-17 UART Auxiliary Control Register (UACRn) ........................................................... 14-18 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-18 UART Divider Upper Register (UDUn)................................................................... 14-19 UART Divider Lower Register (UDLn)................................................................... 14-19 UART Interrupt Vector Register (UIVRn) ............................................................... 14-20 UART Input Port Register (UIPn) ............................................................................ 14-20 UART Block Diagram Showing External and Internal Interface Signals ................ 14-21 UART Output Port Data 1 Register (UOP1/UOP0) ................................................. 14-21 UART/RS-232 Interface ........................................................................................... 14-23 UART1/CODEC Interface........................................................................................ 14-23 UART1/AC '97 Interface ......................................................................................... 14-23 Clocking Source Diagram......................................................................................... 14-24 Transmitter and Receiver Functional Diagram......................................................... 14-25 Transmitter Timing Diagram .................................................................................... 14-27 16-Bit CODEC Interface Timing (lsb First) ............................................................. 14-27 8-Bit CODEC Interface Timing (msb First) ............................................................. 14-28 AC `97 Interface Timing........................................................................................... 14-28 Receiver Timing........................................................................................................ 14-30 Automatic Echo ........................................................................................................ 14-34 Local Loop-Back ...................................................................................................... 14-34 Remote Loop-Back ................................................................................................... 14-35 Multidrop Mode Timing Diagram ............................................................................ 14-36 UART Mode Programming Flowchart ..................................................................... 14-39 Parallel Port Pin Assignment Register (PAR) ............................................................ 15-1 Port A Data Direction Register (PADDR).................................................................. 15-2 Port A Data Register (PADAT) .................................................................................. 15-3 Mechanical Diagram................................................................................................... 16-9 MCF5407 Case Drawing (General View) ................................................................ 16-10 Case Drawing (Details)............................................................................................. 16-11 MCF5407 Block Diagram with Signal Interfaces ...................................................... 17-2 MCF5307 to MCF5407 TM[2:0] Pin Remapping .................................................... 17-18 Illustrations xxv ILLUSTRATIONS Figure Page Title Number Number 18-1 Signal Relationship to CLKIN for Non-DRAM Access............................................. 18-2 18-2 Connections for External Memory Port Sizes ............................................................ 18-4 18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4 18-4 Data Transfer State Transition Diagram ..................................................................... 18-6 18-5 Read Cycle Flowchart................................................................................................. 18-7 18-6 Basic Read Bus Cycle................................................................................................. 18-8 18-7 Write Cycle Flowchart................................................................................................ 18-9 18-8 Basic Write Bus Cycle ................................................................................................ 18-9 18-9 Read Cycle with Fast Termination ........................................................................... 18-10 18-10 Write Cycle with Fast Termination........................................................................... 18-10 18-11 Back-to-Back Bus Cycles ......................................................................................... 18-11 18-12 Line Read Burst (2-1-1-1), External Termination .................................................... 18-12 18-13 Line Read Burst (2-1-1-1), Internal Termination ..................................................... 18-13 18-14 Line Read Burst (3-2-2-2), External Termination .................................................... 18-13 18-15 Line Read Burst-Inhibited, Fast, External Termination............................................ 18-14 18-16 Line Write Burst (2-1-1-1), Internal/External Termination...................................... 18-14 18-17 Line Write Burst (3-2-2-2) with One Wait State, Internal Termination ................... 18-15 18-18 Line Write Burst-Inhibited, Internal Termination .................................................... 18-15 18-19 Longword Read from an 8-Bit Port, External Termination...................................... 18-16 18-20 Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16 18-21 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17 18-22 Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 18-17 18-23 Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20 18-24 Basic No-Wait-State External Master Access .......................................................... 18-22 18-25 External Master Burst Line Access to 32-Bit Port.................................................... 18-24 18-26 MCF5407 Two-Wire Mode Bus Arbitration Interface............................................. 18-25 18-27 Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26 18-28 Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27 18-29 MCF5407 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28 18-30 Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30 18-31 Three-Wire Bus Arbitration...................................................................................... 18-31 18-32 Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32 18-33 Master Reset Timing................................................................................................. 18-34 18-34 Software Watchdog Reset Timing ............................................................................ 18-35 19-1 JTAG Test Logic Block Diagram ............................................................................... 19-2 19-2 JTAG TAP Controller State Machine......................................................................... 19-4 19-3 IDCODE Register ....................................................................................................... 19-6 19-4 Disabling JTAG in JTAG Mode ............................................................................... 19-11 19-5 Disabling JTAG in Debug Mode .............................................................................. 19-11 20-1 Supply Voltage Sequencing and Separation Cautions................................................ 20-3 20-2 Example Circuit to Control Supply Sequencing......................................................... 20-4 20-3 CLKIN-to-Core Clock Frequency Ranges.................................................................. 20-4 20-4 Clock Timing .............................................................................................................. 20-5 xxvi MCF5407 User's Manual ILLUSTRATIONS Figure Number 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 20-21 20-22 20-23 20-24 A-1 A-2 A-3 A-4 A-5 A-6 A-7 Title Page Number PSTCLK Timing......................................................................................................... 20-6 AC Timings--Normal Read and Write Bus Cycles ................................................... 20-8 SDRAM Read Cycle with EDGESEL Tied to Buffered CLKIN ............................... 20-9 SDRAM Write Cycle with EDGESEL Tied to Buffered CLKIN ............................ 20-10 SDRAM Read Cycle with EDGESEL Tied High..................................................... 20-11 SDRAM Write Cycle with EDGESEL Tied High.................................................... 20-12 SDRAM Read Cycle with EDGESEL Tied Low ..................................................... 20-13 SDRAM Write Cycle with EDGESEL Tied Low .................................................... 20-14 AC Output Timing--High Impedance...................................................................... 20-14 Reset Timing............................................................................................................. 20-15 Real-Time Trace AC Timing .................................................................................... 20-16 BDM Serial Port AC Timing .................................................................................... 20-16 Timer Module AC Timing ........................................................................................ 20-17 I2C Input/Output Timings ......................................................................................... 20-19 UART0 and UART1 Module AC Timing--UART Mode ....................................... 20-20 UART1 in 8- and 16-bit CODEC Mode ................................................................... 20-21 UART1 in AC `97 Mode .......................................................................................... 20-21 General-Purpose I/O Timing..................................................................................... 20-22 DMA Timing ............................................................................................................ 20-23 IEEE 1149.1 (JTAG) AC Timing ............................................................................. 20-25 MCF5307 to MCF5407 TM[2:0] Pin Remapping ....................................................... A-5 Simplified Block Diagram ........................................................................................... A-6 PLL Module................................................................................................................. A-7 Exception Stack Frame Form .................................................................................... A-11 Write Debug Module Register Command (WDMREG)............................................... A-12 WDMREG Command Sequence................................................................................... A-13 PLL Power Supply Filter Circuit............................................................................... A-18 Illustrations xxvii ILLUSTRATIONS Figure Number xxviii Title MCF5407 User's Manual Page Number 9/1/00 TABLES Table Number 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 Title Page Number User-Level Registers................................................................................................... 1-15 Supervisor-Level Registers......................................................................................... 1-16 CCR Field Descriptions ............................................................................................. 2-10 MOVEC Register Map ............................................................................................... 2-11 Status Field Descriptions ............................................................................................ 2-11 Integer Data Formats................................................................................................... 2-13 ColdFire Effective Addressing Modes........................................................................ 2-15 Notational Conventions .............................................................................................. 2-16 ColdFire ISA_B Extension Summary......................................................................... 2-19 User-Level Instruction Set Summary.......................................................................... 2-19 Supervisor-Level Instruction Set Summary................................................................ 2-23 Misaligned Operand References ................................................................................. 2-24 Move Byte and Word Execution Times...................................................................... 2-25 Move Long Execution Times...................................................................................... 2-25 Miscellaneous Move Execution Times....................................................................... 2-26 One-Operand Instruction Execution Times ................................................................ 2-27 Two-Operand Instruction Execution Times................................................................ 2-27 Miscellaneous Instruction Execution Times............................................................... 2-29 Branch Instruction Execution Times .......................................................................... 2-30 Bcc Instruction Execution Times................................................................................ 2-30 Exception Vector Assignments................................................................................... 2-32 Format Field Encoding ............................................................................................... 2-33 Fault Status Encodings................................................................................................ 2-33 MCF5407 Exceptions ................................................................................................. 2-34 MAC Instruction Summary........................................................................................... 3-4 Two-Operand MAC Instruction Execution Times ....................................................... 3-5 MAC Move Instruction Execution Times..................................................................... 3-6 RAMBARn Field Description ...................................................................................... 4-3 Examples of Typical RAMBAR Settings ..................................................................... 4-6 Valid and Modified Bit Settings ................................................................................... 4-8 CACR Field Descriptions ........................................................................................... 4-21 ACRn Field Descriptions............................................................................................ 4-24 Instruction Cache Line State Transitions.................................................................... 4-27 Data Cache Line State Transitions.............................................................................. 4-29 Data Cache Line State Transitions (Current State Invalid) ........................................ 4-30 Data Cache Line State Transitions (Current State Valid)........................................... 4-31 Tables xxix TABLES Table Number 4-10 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 xxx Title Page Number Data Cache Line State Transitions (Current State Modified)..................................... 4-31 Debug Module Signals.................................................................................................. 5-2 PSTDDATA: Sequential Execution of Single-Cycle Instructions .............................. 5-3 PSTDDATA: Data Operand Captured.......................................................................... 5-4 Processor Status Encoding............................................................................................ 5-5 0xE Status Posting ........................................................................................................ 5-7 BDM/Breakpoint Registers........................................................................................... 5-9 AATR and AATR1 Field Descriptions....................................................................... 5-11 ABLR and ABLR1 Field Description......................................................................... 5-12 ABHR and ABHR1 Field Description........................................................................ 5-12 BAAR Field Descriptions ........................................................................................... 5-13 CSR Field Descriptions............................................................................................... 5-14 DBRn Field Descriptions............................................................................................ 5-16 DBMRn Field Descriptions ........................................................................................ 5-16 Access Size and Operand Data Location .................................................................... 5-16 PBR, PBR1, PBR2, PBR3 Field Descriptions............................................................ 5-17 PBMR Field Descriptions ........................................................................................... 5-17 TDR Field Descriptions .............................................................................................. 5-19 XTDR Field Descriptions ........................................................................................... 5-20 Receive BDM Packet Field Description ..................................................................... 5-25 Transmit BDM Packet Field Description ................................................................... 5-26 BDM Command Summary ......................................................................................... 5-26 BDM Field Descriptions ............................................................................................. 5-27 Control Register Map.................................................................................................. 5-42 Definition of DRc Encoding--Read........................................................................... 5-44 PSTDDATA Nibble/CSR[BSTAT] Breakpoint Response......................................... 5-46 Exception Vector Assignments................................................................................... 5-47 PSTDDATA Specification for User-Mode Instructions............................................. 5-50 PSTDDATA Specification for Supervisor-Mode Instructions ................................... 5-54 SIM Registers .............................................................................................................. 6-3 MBAR Field Descriptions ............................................................................................ 6-5 RSR Field Descriptions................................................................................................. 6-6 SYPCR Field Descriptions ........................................................................................... 6-8 PLLIPL Settings.......................................................................................................... 6-10 MPARK Field Descriptions........................................................................................ 6-11 Divide Ratio Encodings ............................................................................................... 7-2 PLLCR Field Descriptions............................................................................................ 7-3 PLL Module Input SIgnals............................................................................................ 7-4 PLL Module Output Signals ......................................................................................... 7-4 I2C Interface Memory Map........................................................................................... 8-6 I2C Address Register Field Descriptions ...................................................................... 8-6 IFDR Field Descriptions ............................................................................................... 8-7 I2CR Field Descriptions................................................................................................ 8-8 MCF5407 User's Manual TABLES Table Number 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 Title Page Number I2SR Field Descriptions................................................................................................ 8-9 Interrupt Controller Registers ....................................................................................... 9-2 Interrupt Control Registers ........................................................................................... 9-2 ICRn Field Descriptions ............................................................................................... 9-3 Interrupt Priority Scheme.............................................................................................. 9-4 AVR Field Descriptions................................................................................................ 9-6 Autovector Register Bit Assignments........................................................................... 9-6 IPR and IMR Field Descriptions................................................................................... 9-7 IRQPAR Field Descriptions ......................................................................................... 9-8 Chip-Select Module Signals ....................................................................................... 10-1 Byte Enables/Byte Write Enable Signal Settings ....................................................... 10-2 Accesses by Matches in CSCRs and DACRs ............................................................. 10-3 D7/AA, Automatic Acknowledge of Boot CS0.......................................................... 10-4 D[6:5]/PS[1:0], Port Size of Boot CS0 ....................................................................... 10-5 D3/BE_CONFIG0, BE[3:0] Boot Configuration ....................................................... 10-5 Chip-Select Registers.................................................................................................. 10-5 CSARn Field Description ........................................................................................... 10-7 CSMRn Field Descriptions ......................................................................................... 10-7 CSCRn Field Descriptions.......................................................................................... 10-8 DRAM Controller Registers ....................................................................................... 11-3 SDRAM Signal Summary .......................................................................................... 11-4 DCR Field Descriptions (Asynchronous Mode)......................................................... 11-5 DACR0/DACR1 Field Description ............................................................................ 11-6 DMR0/DMR1 Field Descriptions............................................................................... 11-7 Generic Address Multiplexing Scheme ...................................................................... 11-8 DRAM Addressing for Byte-Wide Memories.......................................................... 11-10 DRAM Addressing for 16-Bit Wide Memories........................................................ 11-10 DRAM Addressing for 32-Bit Wide Memories........................................................ 11-11 SDRAM Commands ................................................................................................. 11-17 Synchronous DRAM Signal Connections ................................................................ 11-17 DCR Field Descriptions (Synchronous Mode) ......................................................... 11-19 DACR0/DACR1 Field Descriptions (Synchronous Mode)...................................... 11-21 DMR0/DMR1 Field Descriptions............................................................................. 11-23 MCF5407 to SDRAM Interface (8-Bit Port, 9-Column Address Lines).................. 11-24 MCF5407 to SDRAM Interface (8-Bit Port,10-Column Address Lines)................. 11-24 MCF5407 to SDRAM Interface (8-Bit Port,11-Column Address Lines)................. 11-24 MCF5407 to SDRAM Interface (8-Bit Port,12-Column Address Lines)................. 11-24 MCF5407 to SDRAM Interface (8-Bit Port,13-Column Address Lines)................. 11-25 MCF5407 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)................ 11-25 MCF5407 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)................ 11-25 MCF5407 to SDRAM Interface (16-Bit Port, 10-Column Address Lines).............. 11-25 MCF5407 to SDRAM Interface (16-Bit Port, 11-Column Address Lines).............. 11-25 MCF5407 to SDRAM Interface (16-Bit Port, 12-Column Address Lines).............. 11-26 Tables xxxi TABLES Table Number 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 15-1 15-2 xxxii Title Page Number MCF5407 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ............. 11-26 MCF5407 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 11-26 MCF5407 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 11-26 MCF5407 to SDRAM Interface (32-Bit Port, 10-Column Address Lines).............. 11-26 MCF5407 to SDRAM Interface (32-Bit Port, 11-Column Address Lines).............. 11-27 MCF5407 to SDRAM Interface (32-Bit Port, 12-Column Address Lines).............. 11-27 SDRAM Hardware Connections............................................................................... 11-27 SDRAM Example Specifications ............................................................................. 11-34 SDRAM Hardware Connections............................................................................... 11-35 DCR Initialization Values......................................................................................... 11-35 DACR Initialization Values...................................................................................... 11-36 DMR0 Initialization Values...................................................................................... 11-37 Mode Register Initialization ..................................................................................... 11-38 DMA Signals .............................................................................................................. 12-2 MCF5407 Signal Configurations for PP[4:2]/TM[2:0]/DACK[1:0] .......................... 12-3 Memory Map for DMA Controller Module Registers................................................ 12-6 DCRn Field Descriptions............................................................................................ 12-8 DSRn Field Descriptions .......................................................................................... 12-10 General-Purpose Timer Module Memory Map .......................................................... 13-3 TMRn Field Descriptions ........................................................................................... 13-4 TERn Field Descriptions............................................................................................. 13-6 Time-Out Values (in Seconds)--TRR[REF] = 0xFFFF(162-MHz Processor Clock) 13-7 UART Module Programming Model.......................................................................... 14-4 UMR1n Field Descriptions ......................................................................................... 14-6 UMR2n Field Descriptions ......................................................................................... 14-7 RXLVL Field Descriptions......................................................................................... 14-8 Modem Control Register (MODCTL) Field Descriptions.......................................... 14-9 TXLVL Field Descriptions ....................................................................................... 14-10 USRn Field Descriptions .......................................................................................... 14-11 UCSRn Field Descriptions........................................................................................ 14-12 RSMP Field Descriptions ......................................................................................... 14-13 TSPC Field Descriptions........................................................................................... 14-13 UCRn Field Descriptions.......................................................................................... 14-14 UIPCRn Field Descriptions ...................................................................................... 14-17 UACRn Field Descriptions ....................................................................................... 14-18 UISRn/UIMRn Field Descriptions ........................................................................... 14-19 UIVRn Field Descriptions ........................................................................................ 14-20 UIPn Field Descriptions............................................................................................ 14-20 UOP1/UOP0 Field Descriptions ............................................................................... 14-21 UART Module Signals ............................................................................................. 14-22 UART Module Initialization Sequence .................................................................... 14-38 Parallel Port Pin Descriptions ..................................................................................... 15-2 PADDR Field Description .......................................................................................... 15-2 MCF5407 User's Manual TABLES Table Number 15-3 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 20-5 20-6 Title Page Number Relationship between PADAT Register and Parallel Port Pin (PP) ........................... 15-3 Pins 1-52 (Left, Top-to-Bottom) ................................................................................ 16-1 Pins 53-104 (Bottom, Left-to-Right).......................................................................... 16-3 Pins 105-156 (Right, Bottom-to-Top)........................................................................ 16-5 Pins 157-208 (Top, Right-to-Left) ............................................................................. 16-6 Dimensions ............................................................................................................... 16-11 MCF5407 Signal Index............................................................................................... 17-3 MCF5407 Alphabetical Signal Index ......................................................................... 17-5 Data Pin Configuration ............................................................................................... 17-8 Bus Cycle Size Encoding............................................................................................ 17-9 Bus Cycle Transfer Type Encoding.......................................................................... 17-10 TM[2:0] Encodings for TT = 00 (Normal Access)................................................... 17-10 TM2 Encoding for DMA as Master (TT = 01) ......................................................... 17-11 TM[1:0] Encoding for DMA as Master (TT = 01) ................................................... 17-11 TM[2:0] Encodings for TT = 10 (Emulator Access) ................................................ 17-11 TM[2:0] Encodings for TT = 11 (Interrupt Level) ................................................... 17-12 Data Pin Configuration ............................................................................................. 17-14 D7 Selection of CS0 Automatic Acknowledge ........................................................ 17-14 D6 and D5 Selection of CS0 Port Size ..................................................................... 17-14 D3/BE_CONFIG, BE[3:0] Boot Configuration ....................................................... 17-15 D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-15 ColdFire Bus Signal Summary ................................................................................... 18-1 Bus Cycle Size Encoding............................................................................................ 18-3 Accesses by Matches in CSCRs and DACRs ............................................................. 18-5 Bus Cycle States ......................................................................................................... 18-6 Allowable Line Access Patterns ............................................................................... 18-12 MCF5407 Arbitration Protocol States ...................................................................... 18-20 ColdFire Bus Arbitration Signal Summary............................................................... 18-21 Cycles for Basic No-Wait-State External Master Access......................................... 18-23 Cycles for External Master Burst Line Access to 32-Bit Port .................................. 18-24 MCF5407 Two-Wire Bus Arbitration Protocol Transition Conditions.................... 18-28 Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32 Data Pin Configuration ............................................................................................. 18-35 JTAG Pin Descriptions ............................................................................................... 19-3 JTAG Instructions....................................................................................................... 19-5 IDCODE Bit Assignments.......................................................................................... 19-6 Boundary-Scan Bit Definitions................................................................................... 19-7 Absolute Maximum Ratings ....................................................................................... 20-1 Operating Temperatures.............................................................................................. 20-1 DC Electrical Specifications ....................................................................................... 20-2 Divide Ratio Encodings .............................................................................................. 20-4 Clock Timing Specification ........................................................................................ 20-5 Input AC Timing Specification................................................................................... 20-6 Tables xxxiii TABLES Table Number 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 xxxiv Title Page Number Output AC Timing Specification ................................................................................ 20-6 Reset Timing Specification....................................................................................... 20-15 Debug AC Timing Specification .............................................................................. 20-16 Timer Module AC Timing Specification.................................................................. 20-17 I2C Input Timing Specifications between SCL and SDA......................................... 20-18 I2C Output Timing Specifications between SCL and SDA ...................................... 20-18 UART Module AC Timing Specifications ............................................................... 20-19 General-Purpose I/O Port AC Timing Specifications............................................... 20-22 DMA AC Timing Specifications .............................................................................. 20-23 IEEE 1149.1 (JTAG) AC Timing Specifications ..................................................... 20-24 Differences between MCF5307 and MCF5407........................................................... A-1 MOVEC CPU Space Register Map ............................................................................. A-4 TM[2:1] Encoding for MCF5307 Internal DMA as Master (TT = 01) ....................... A-4 TM0 Encoding for MCF5307 Internal DMA as Master (TT = 01) ............................. A-5 Divide Ratio Encodings ............................................................................................... A-7 D[7:0] Multiplexing ..................................................................................................... A-8 D7/AA, Automatic Acknowledge of Boot CS0........................................................... A-9 D[6:5]/PS[1:0], Port Size of Boot CS0 ........................................................................ A-9 D4/ADDR_CONFIG, Address Pin Assignment.......................................................... A-9 D3/BE_CONFIG, BE[3:0] Boot Configuration .......................................................... A-9 Definition of DRc Encoding--Write ......................................................................... A-13 Debug C Exception Vector Assignments .................................................................. A-16 Version 4 Debug C Processor Status Encodings ....................................................... A-17 SIM Registers................................................................................................................B-1 Interrupt Controller Registers .......................................................................................B-1 Chip-Select Registers....................................................................................................B-2 DRAM Controller Registers .........................................................................................B-3 General-Purpose Timer Registers .................................................................................B-4 UART0 Control Registers.............................................................................................B-4 UART1 Control Registers.............................................................................................B-6 Parallel Port Memory Map............................................................................................B-7 I2C Interface Memory Map...........................................................................................B-8 DMA Controller Registers............................................................................................B-8 MCF5407 User's Manual About This Book The primary objective of this user's manual is to define the functionality of the MCF5407 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers' responsibility to be sure they are using the most recent version of the documentation. To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldfire. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MCF5407. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire architecture. Organization Following is a summary and a brief description of the major sections of this manual: * Chapter 1, "Overview," includes general descriptions of the modules and features incorporated in the MCF5407, focussing in particular on new features defined by the Version 4 (V4) programming model, such as the Harvard memory architecture implementation, new instructions, and new registers. * Part I is intended for system designers who need to understand the operation of the MCF5407 ColdFire core and its multiply/accumulate (MAC) execution unit. It describes the programming and exception models, Harvard memory implementation, and debug module. -- Chapter 2, "ColdFire Core," provides an overview of the microprocessor core of the MCF5407. The chapter begins with a description of enhancements from the V3 ColdFire core, and then fully describes the V4 programming model as it is implemented on the MCF5407. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. About This Book xxxv Organization -- Chapter 3, "Hardware Multiply/Accumulate (MAC) Unit," describes the MCF5407 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). * -- Chapter 4, "Local Memory." This chapter describes the MCF5407 implementation of the ColdFire V4 local memory specification. It consists of the two following major sections. - Section 4.2, "SRAM Overview," describes the MCF5407 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. - Section 4.7, "Cache Overview," describes the MCF5407 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. -- Chapter 5, "Debug Support," describes the Revision C enhanced hardware debug support in the MCF5407. This revision of the ColdFire debug architecture encompasses earlier revisions. Part II, "System Integration Module (SIM)," describes the system integration module, which provides overall control of the bus and serves as the interface between the ColdFire core processor complex and internal peripheral devices. It includes a general description of the SIM and individual chapters that describe components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt controller for peripherals, configuration and operation of chip selects, and the SDRAM controller. -- Chapter 6, "SIM Overview," describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5407. -- Chapter 7, "Phase-Locked Loop (PLL)," describes configuration and operation of the PLL module. It describes in detail the registers and signals that support the PLL implementation. -- Chapter 8, "I2C Module," describes the MCF5407 I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides extensive programming examples. -- Chapter 9, "Interrupt Controller," describes operation of the interrupt controller portion of the SIM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. -- Chapter 10, "Chip-Select Module," describes the MCF5407 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers. -- Chapter 11, "Synchronous/Asynchronous DRAM Controller Module," describes configuration and operation of the synchronous/asynchronous DRAM xxxvi MCF5407 User's Manual Organization controller component of the SIM. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. * * Part III, "Peripheral Module," describes the operation and configuration of the MCF5407 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II. -- Chapter 12, "DMA Controller Module," provides an overview of the DMA controller module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail, showing timing diagrams for various operations. -- Chapter 13, "Timer Module," describes configuration and operation of the two general-purpose timer modules, timer 0 and timer 1. It includes programming examples. -- Chapter 14, "UART Modules," describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5407 and includes programming examples. Particular attention is given to the UART1 implementation of a synchronous interface that provides a controller for an 8- or 16-bit CODEC interface and an audio CODEC `97 (AC '97) digital interface. -- Chapter 15, "Parallel Port (General-Purpose I/O)," describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. It includes a code example for setting up the parallel port. Part IV, "Hardware Interface," provides a pinout and both electrical and functional descriptions of the MCF5407 signals. It also describes how these signals interact to support the variety of bus operations shown in timing diagrams. -- Chapter 16, "Mechanical Data," provides a functional pin listing and package diagram for the MCF5407. -- Chapter 17, "Signal Descriptions," provides an alphabetical listing of MCF5407 signals. This chapter describes the MCF5407 signals. In particular, it shows which are inputs or outputs, how they are multiplexed, which signals require pull-up resistors, and the state of each signal at reset. -- Chapter 18, "Bus Operation," describes data transfers, error conditions, bus arbitration, and reset operations. It describes transfers initiated by the MCF5407 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. Note that Chapter 11, "Synchronous/Asynchronous DRAM Controller Module," describes DRAM cycles. -- Chapter 19, "IEEE 1149.1 Test Access Port (JTAG)," describes configuration and operation of the MCF5407 JTAG test implementation. It describes the use of JTAG instructions and how to disable JTAG functionality. About This Book xxxvii Suggested Reading -- Chapter 20, "Electrical Specifications," describes AC and DC electrical specifications and thermal characteristics for the MCF5407. Because additional speeds may have become available since the publication of this book, consult Motorola's ColdFire web page, http://www.motorola.com/coldfire, to confirm that this is the latest information. This manual includes the following two appendixes: * Appendix A, "Migrating from the ColdFire MCF5307 to the MCF5407," highlights the differences between the MCF5307B and MCF5407. Users of the MCF5307 and MCF5307A should use this document in conjunction with the MCF5307 User's Manual Mask Set Addendum. For additional information, see the MCF5407 Integrated ColdFire Microprocessor Product Brief. * Appendix B, "List of Memory Maps," lists the entire address-map for MCF5407 memory-mapped registers. This manual also includes a glossary and an index. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture. General Information The following documentation provides useful information about the ColdFire architecture and computer architecture in general: ColdFire Documentation The ColdFire documentation is available from the sources listed on the back cover of this manual. Document order numbers are included in parentheses for ease in ordering. * ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) * User's manuals--These books provide details about individual ColdFire implementations and are intended to be used in conjunction with The ColdFire Programmers Reference Manual. These include the following: -- ColdFire MCF5102 User's Manual (MCF5102UM/AD) -- ColdFire MCF5202 User's Manual (MCF5202UM/AD) * xxxviii -- ColdFire MCF5204 User's Manual (MCF5204UM/AD) -- ColdFire MCF5206 User's Manual (MCF5206EUM/AD) -- ColdFire MCF5206E User's Manual (MCF5206EUM/AD) -- ColdFire MCF5307 User's Manual (MCF5307UM/AD) ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) MCF5407 User's Manual Conventions * Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World Wide Web at http://www.motorola.com/ColdFire/. Conventions This document uses the following notational conventions: MNEMONICS In text, instruction mnemonics are shown in uppercase. mnemonics In code and tables, instruction mnemonics are shown in lowercase. italics 0x0 Italics indicate variable command parameters. Book titles in text are set in italics. Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register. nibble A 4-bit data unit byte An 8-bit data unit word A 16-bit data unit longword A 32-bit data unit x In some contexts, such as signal encodings, x indicates a don't care. n Used to express an undefined numerical value NOT logical operator & AND logical operator | OR logical operator Acronyms and Abbreviations Table i lists acronyms and abbreviations used in this document. Table i. Acronyms and Abbreviated Terms Term Meaning ADC Analog-to-digital conversion ALU Arithmetic logic unit AVEC Autovector About This Book xxxix Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Term xl Meaning BDM Background debug mode BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing EA Effective address EDO Extended data output (DRAM) FIFO First-in, first-out GPIO General-purpose I/O I2C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out LRU Least recently used LSB Least-significant byte lsb Least-significant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PCLK Processor clock PLL Phase-locked loop PLRU Pseudo least recently used MCF5407 User's Manual Terminology and Notational Conventions Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Terminology and Notational Conventions Table ii shows notational conventions used throughout this document. Table ii Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition (example: NE for not equal) Register Specifications An Ay,Ax Any address register n (example: A3 is address register 3) Source and destination address registers, respectively Dn Any data register n (example: D5 is data register 5) Dy,Dx Source and destination data registers, respectively Rc Any control register (example VBR is the vector base register) Rm MAC registers (ACC, MAC, MASK) Rn Any address or data register Rw Destination register w (used for MAC instructions only) Ry,Rx Xi Any source and destination registers, respectively index register i (can be an address or data register: Ai, Di) About This Book xli Terminology and Notational Conventions Table ii Notational Conventions (Continued) Instruction Operand Syntax Register Names ACC MAC accumulator register CCR Condition code register (lower byte of SR) MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name PSTDDATA Processor status/debug data port Miscellaneous Operands #<data> <ea> <ea>y,<ea>x <label> <list> <shift> <size> Immediate data following the 16-bit operation word of the instruction Effective address Source and destination effective addresses, respectively Assembly language program label List of registers for MOVEM instruction (example: D3-D0) Shift operation: shift left (<<), shift right (>>) Operand data size: byte (B), word (W), longword (L) bc Both instruction and data caches dc Data cache ic Instruction cache # <vector> <> <xxx> Identifies the 4-bit vector number for trap instructions identifies an indirect data address referencing memory identifies an absolute address referencing memory dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) Operations xlii + Arithmetic addition or postincrement indicator - Arithmetic subtraction or predecrement indicator x Arithmetic multiplication MCF5407 User's Manual Terminology and Notational Conventions Table ii Notational Conventions (Continued) Instruction Operand Syntax / Arithmetic division ~ Invert; operand is logically complemented & Logical AND | Logical OR ^ Logical exclusive OR << Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits) Source operand is moved to destination operand Two operands are exchanged sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion If <condition> then <operations> else <operations> Test the condition. If true, the operations after `then' are performed. If the condition is false and the optional `else' clause is present, the operations after `else' are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. Subfields and Qualifiers {} Optional operation () Identifies an indirect address dn Displacement value, n-bits wide (example: d16 is a 16-bit displacement) Address Calculated effective address (pointer) Bit Bit selection (example: Bit 3 of D0) lsb Least significant bit (example: lsb of D0) LSB Least significant byte LSW Least significant word msb Most significant bit MSB Most significant byte MSW Most significant word Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero About This Book xliii Terminology and Notational Conventions xliv MCF5407 User's Manual Chapter 1 Overview This chapter is an overview of the MCF5407 ColdFire(R) processor. It includes general descriptions of the modules and features incorporated in the MCF5407, focusing in particular on new features defined by the Version 4 (V4) programming model, such as the Harvard memory architecture implementation, new instructions, and new registers. 1.1 Features The MCF5407 integrated microprocessor combines a V4 ColdFire processor core with the following components, as shown in Figure 1-1: * * * * * * * * * Harvard architecture memory system with 16-Kbyte instruction cache and 8-Kbyte data cache Two, 2-Kbyte on-chip SRAMs Integer/fractional multiply-accumulate (MAC) unit Divide unit System debug interface DRAM controller for synchronous and asynchronous DRAM Four-channel DMA controller Two general-purpose timers Two UARTs, one that supports synchronous operations * * * I2CTM interface Parallel I/O interface System integration module (SIM) Designed for embedded control applications, the MCF5407 delivers 233 Dhrystone MIPS at 162 MHz while minimizing system costs. Chapter 1. Overview 1-1 Features V4 COLDFIRE PROCESSOR COMPLEX Instruction Unit 8-Entry Branch Cache .. . Instruction Fetch Pipeline (IFP) IAG IC1 IC2 IED Branch Logic JTAG LIFO Return Stack Ten-Instruction FIFO Buffer 128-Entry Prediction Table Operand Execution Pipeline (OEP) CCR DS AG OC1 OC2 EX MAC DA DIV Debug Module GeneralPurpose Registers A0-A7 D0-D7 31 0 31 0 Local Memory /2 SRAM Controller PSTCLK RAMBAR0 RAMBAR1 2-Kbyte SRAM0 CLKIN (to on-chip peripherals) CLKIN PLL Xn RSTI Local Memory Instruction Bus 2-Kbyte SRAM1 Local Memory Data Bus Harvard Cache Controller CACR PCLK RSTO ACR2 ACR3 ACR0 ACR1 16-Kbyte Instruction Cache 8-Kbyte Data Cache 31 0 4-Entry Store Buffer DMA SYSTEM INTEGRATION MODULE (SIM) PLL Control PLL System Control RSR SWIVR Base Address Bus Master Park Parallel Port MBAR MPARK PLL Software Watchdog SYPCR SWSR DRAM Controller Chip-Select Module DRAM Control DCR External Bus Interface Interrupt Controller I2C Module IRQPAR Two UARTs 10 ICRs 8 8 8 CSARs CSCRs CSMRs IPR Addr/Cntrl Mask DACR0/1 IMR DMR0/1 AVR 8 DRAM Controller Outputs CS[7:0] 32-Bit Address Bus 32-Bit Data Bus Control Signals 4 IRQ[1,3,5,7] Figure 1-1. MCF5407 Block Diagram 1-2 Four Channels MCF5407 User's Manual Two GeneralPurpose Timers Features Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated using advanced process technologies. The MCF5407 extends the legacy of Motorola's 68K family by providing a compatible path for 68K and ColdFire customers in which development tools and customer code can be leveraged. In fact, customers moving from 68K to ColdFire can use code translation and emulation tools that facilitate modifying 68K assembly code to the ColdFire architecture. The package, pinout, and integration mix of the MCF5407 create an especially simple upgrade for current MCF5307 designs with over triple the system performance. Based on the concept of variable-length RISC technology, the ColdFire family combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. In defining the ColdFire architecture for embedded processing applications, a 68K-code compatible core combines performance advantages of a RISC architecture with the optimum code density of a streamlined, variable-length M68000 instruction set. By using a variable-length instruction set architecture, embedded system designers using ColdFire RISC processors enjoy significant advantages over conventional fixed-length RISC architectures. The denser binary code for ColdFire processors consumes less memory than many fixed-length instruction set RISC processors available. This improved code density means more efficient system memory use for a given application and allows use of slower, less costly memory to help achieve a target performance level. The MCF5407 is the first standard product to implement the Version 4 ColdFire microprocessor core. The V4 microarchitecture implements a number of advanced techniques, including a Harvard memory architecture, branch cache acceleration logic, and limited superscalar support (dual-instruction issue), which contribute to the 233 Dhrystone MIPS performance level. Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. The processor complex frequency is an integer multiple, 3 to 6 times, of the external bus frequency. The core clock can be stopped to support a low-power mode. Serial communication channels are provided by an I2C interface module and two programmable full-duplex UARTs, one of which provides synchronous communications for soft-modem applications. Four channels of DMA allow for fast data transfer using a programmable burst mode independent of processor execution. The two 16-bit general-purpose multimode timers provide separate input and output signals. For system protection, the processor includes a programmable 16-bit software watchdog timer. In addition, common system functions such as chip selects, interrupt control, bus arbitration, and an IEEE 1149.1 JTAG module are included.A sophisticated debug interface supports background-debug mode plus real-time trace and debug with an expanded set of on-chip breakpoint registers. This interface is present in all ColdFire standard products and allows common emulator support across the entire family of microprocessors. Chapter 1. Overview 1-3 MCF5407 Features 1.2 MCF5407 Features The following list summarizes MCF5407 features: * * * * 1-4 ColdFire processor core -- Variable-length RISC, clock-multiplied Version 4 microprocessor core -- Implementation of Revision B of the ColdFire instruction set architecture (ISA), which leverages the 68K programming model -- Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) and five-stage operand execution pipeline (OEP) -- Ten-instruction FIFO buffer provides decoupling between the pipelines -- Limited superscalar design achieves performance levels close to dual-issue performance -- Programmable two-level branch acceleration mechanism with an 8-entry branch cache plus a 128-entry prediction table for increased performance -- 32-bit internal address bus supporting 4 Gbytes of linear address space -- 32-bit data bus -- 16 user-accessible, 32-bit-wide, general-purpose registers -- Supervisor/user modes for system protection -- Vector base register to relocate exception-vector table -- Optimized for high-level language constructs Multiply and accumulate unit (MAC) -- High-speed, complex arithmetic processing for DSP applications -- Tightly coupled to the OEP -- Three-stage execute pipeline with one clock issue rate for 16 x 16 operations -- 16 x 16 and 32 x 32 multiplies support, all with 32-bit accumulate -- Signed or unsigned integer support, plus signed fractional operands Hardware integer divide unit -- Unsigned and signed integer divide support -- Tightly coupled to the OEP -- 32/16 and 32/32 operation support producing quotient and/or remainder results 16-Kbyte instruction cache, 8-Kbyte data cache -- Four-way set-associative organization -- Operates at higher processor core frequency -- Provides pipelined, single-cycle access to critical code and data -- Data cache supports write-through and copyback modes -- Four-entry, 32-bit store buffer to improve performance of operand writes MCF5407 User's Manual MCF5407 Features * * * * * Two, 2-Kbyte SRAMs -- Programmable location anywhere within 4-Gbyte linear address space -- Higher core-frequency operation -- Pipelined, single-cycle access to critical code or data -- Each block mappable to either the instruction or data operand bus DMA controller -- Four fully programmable channels: two support external requests and external acknowledges -- Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability -- Source/destination address pointers that can increment or remain constant -- 24-bit transfer counter per channel -- Operand packing and unpacking supported -- Auto-alignment transfers supported for efficient block movement -- Bursting and cycle steal support -- Two-bus-clock internal access -- Automatic DMA transfers from on-chip UARTs using internal interrupts DRAM controller -- Synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, and fast page mode support -- Up to 512 Mbytes of DRAM -- Programmable timer provides CAS-before-RAS refresh for asynchronous DRAMs -- Support for two separate memory blocks Two UARTs -- One UART offers synchronous mode with expanded buffers for soft modem support -- Full-duplex operation -- Programmable clock -- Modem control signals available (CTS, RTS) -- Processor-interrupt capability Dual 16-bit general-purpose multiple-mode timers -- 8-bit prescaler -- Timer input and output pins -- Processor-interrupt capability -- Up to 18.5-nS resolution at 54 MHz Chapter 1. Overview 1-5 MCF5407 Features * * * * * * * 1-6 I2C module -- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads -- Fully compatible with industry-standard I2C bus -- Master or slave modes support multiple masters -- Automatic interrupt generation with programmable level System interface module (SIM) -- Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM, FLASH, and memory-mapped I/O devices -- Eight fully programmable chip selects, each with a base address register -- Programmable wait states and port sizes per chip select -- User-programmable processor clock/input clock frequency ratio -- Programmable interrupt controller -- Low interrupt latency -- Four external interrupt request inputs -- Programmable autovector generator -- Software watchdog timer 16-bit general-purpose I/O interface IEEE 1149.1 test (JTAG) module System debug support -- Real-time trace for determining dynamic execution path while in emulator mode -- Background debug mode (BDM) for debug features while halted -- Real-time debug support, including 13 user-visible hardware breakpoint registers supporting 8 separate breakpoints -- Supports servicing of critical, real-time interrupt requests while the BDM is in emulator mode -- Supports comprehensive emulator functions through trace and breakpoint logic On-chip PLL -- Accepts various clock input (CLKIN) frequencies between 25 and 54 MHz -- Supports core frequencies between 100 and 162 MHz -- Supports low-power mode Product offerings -- 233 Dhrystone MIPS at 162 MHz -- Implemented in 0.22 , quad-layer-metal process technology with 1.8-V operation (3.3-V compliant I/O pads) -- 208-pin plastic QFP package -- 0-70 C operating temperature MCF5407 User's Manual ColdFire Module Description 1.2.1 Process The MCF5407 is manufactured in a 0.22- CMOS process with quad-layer-metal routing technology. This process combines the high performance and low power needed for embedded system applications. Inputs are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with outputs operating from VDD + 0.5 V to GND - 0.5 V, with guaranteed TTL-level specifications. 1.3 ColdFire Module Description The following sections provide overviews of the various modules incorporated in the MCF5407. 1.3.1 ColdFire Core The Version 4 ColdFire core consists of two independent and decoupled pipelines to maximize performance--the instruction fetch pipeline (IFP) and the operand execution pipeline (OEP). 1.3.1.1 Instruction Fetch Pipeline (IFP) The four-stage instruction fetch pipeline (IFP) is designed to prefetch instructions for the operand execution pipeline (OEP). Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer, the fetch mechanism can prefetch instructions in advance of their use by the OEP, thereby minimizing the time stalled waiting for instructions. To maximize the performance of conditional branch instructions, the Version 4 IFP implements a sophisticated two-level acceleration mechanism. The first level is an 8-entry, direct-mapped branch cache with a 2-bit prediction state (strongly/weakly, taken/not-taken) for each entry. The branch cache implements instruction folding techniques. These allow conditional branch instructions that are predicted correctly as taken to execute in zero cycles. For those conditional branches with no information in the branch cache, a second-level, direct-mapped prediction table containing 128 entries is accessed. Again, each entry uses the same 2-bit prediction state definition as the branch cache. This branch prediction state is then used to predict the direction of prefetched conditional branch instructions. Other change-of-flow instructions, including unconditional branches, jumps, and subroutine calls, use a similar mechanism where the IFP calculates the target address. The performance of subroutine return instructions is improved through the use of a four-entry, LIFO return stack. In all cases, these mechanisms allow the IFP to redirect the fetch stream down the path predicted to be taken well in advance of the actual instruction execution. The result is significantly improved performance. Chapter 1. Overview 1-7 ColdFire Module Description 1.3.1.2 Operand Execution Pipeline (OEP) The prefetched instruction stream is gated from the FIFO buffer into the five-stage OEP. The OEP consists of two, traditional two-stage RISC compute engines with a register file access feeding an arithmetic/logic unit (ALU). The compute engine located at the top of the OEP is typically used for operand memory address calculations (the address ALU), while the compute engine located at the bottom of the pipeline is used for instruction execution (the execution ALU). The resulting structure provides 3.9 Gbytes/S data operand bandwidth at 162 MHz to the two compute engines and supports single-cycle execution speeds for most instructions, including all load, store, and most embedded-load operations. In response to users and developers' comments, the V4 design supports execution of the ColdFire Revision B instruction set, which adds a small number of new instructions to improve performance and code density. The OEP also implements two advanced performance features. It dynamically determines the appropriate location of instruction execution (either in the address ALU or the execution ALU) based on the pipeline state. The address compute engine, in conjunction with register renaming resources, can be used to execute a number of heavily-used opcodes and forward the results to subsequent instructions without any pipeline stalls. Additionally, the OEP implements instruction folding techniques involving MOVE instructions so that two instructions can be issued in a single machine cycle. The resulting microarchitecture approaches the performance of a full superscalar implementation, but at a much lower silicon cost. 1.3.1.3 MAC Module The MAC unit provides signal processing capabilities for the MCF5407 in a variety of applications including digital audio and servo control. Integrated as an execution unit in the processor's OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers, plus signed, fixed-point fractional input operands. 1.3.1.4 Integer Divide Module Integrated into the OEP, the divide module performs operations using signed and unsigned integers. The module supports word and longword divides producing quotients and/or remainders. 1.3.2 Harvard Architecture A Harvard memory architecture implements separate instruction and data buses to the processor-local memories, removing conflicts between instruction fetches and operand accesses. 1-8 MCF5407 User's Manual ColdFire Module Description 1.3.2.1 16-Kbyte Instruction Cache/8-Kbyte Data Cache The MCF5407 Harvard architecture includes a 16-Kbyte instruction cache and an 8-Kbyte data cache. These four-way, set-associative caches provide pipelined, single-cycle access on cached instructions and operands. As with all ColdFire caches, the cache controllers implement a non-lockup, streaming design. The use of processor-local memories decouples performance from external memory speeds and increases available bandwidth for external devices or the on-chip 4-channel DMA. Both caches implement line-fill buffers to optimize 16-byte line burst accesses. Additionally, the data cache supports copyback, write-through, or cache-inhibited modes. A 4-entry, 32-bit buffer is used for cache line push operations and can be configured for deferred write buffering in write-through or cache-inhibited modes. The INTOUCH instruction can be used to prefetch instructions that, when used with the cache locking feature, cannot be displaced from the instruction cache by instruction cache misses. This function may be desirable in systems where deterministic real-time performance is critical. 1.3.2.2 Internal 2-Kbyte SRAMs Two 2-Kbyte on-chip SRAM modules are also connected to the Harvard memory architecture and provide pipelined, single-cycle access to memory regions mapped to these devices. Each memory can be independently mapped to any 0-modulo-2K location in the 4-Gbyte address space and can be configured either for instruction or data accesses. Time-critical functions can be mapped onto the instruction memory bus, while the system stack or heavily-referenced data operands can be mapped onto the data bus. 1.3.3 DRAM Controller The MCF5407 DRAM controller provides a direct interface for up to two blocks of DRAM. The controller supports 8-, 16-, or 32-bit memory widths and can easily interface to PC-100 DIMMs. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. The controller operates in normal mode or in page mode and supports SDRAMs and EDO DRAMs. 1.3.4 DMA Controller The MCF5407 provides four fully programmable DMA channels for quick data transfer. Dual- and single-address modes support bursting and cycle steal. Data transfers are 32 bits long with packing and unpacking supported along with an auto-alignment option for efficient block transfers. Automatic block transfers from on-chip serial UARTs are also supported through the DMA channels. Chapter 1. Overview 1-9 ColdFire Module Description 1.3.5 UART Modules The MCF5407 contains two UARTs, which function independently. One UART has been enhanced to provide synchronous operation and a CODEC interface for soft modem support. Either UART can be clocked by the system bus clock, eliminating the need for an external crystal. Each UART module interfaces directly to the CPU, as shown in Figure 1-2. UART Internal Channel Control Logic CTS Serial Communications Channel RTS RxD TxD System Integration Module (SIM) Interrupt Controller Interrupt Control Logic Programmable Clock Generation CLKIN or External clock (TIN) Figure 1-2. UART Module Block Diagram Each UART module consists of the following major functional areas: * * * * Serial communication channel 16-bit divider for clock generation Internal channel control logic Interrupt control logic UART1 is enhanced to provide a CODEC interface for soft modem support. UART1 can be programmed to function like UART0 or in one of following modem modes: * * * An 8-bit CODEC interface A 16-bit CODEC interface An audio CODEC '97 (AC97) digital interface controller Each UART contains an programmable clock-rate generator. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. The UARTs include the following transmit and receive FIFO buffers: * * UART0 has a 4-byte FIFO receive buffer and a 2-byte FIFO transmit buffer. In UART1, the Tx and Rx FIFOs can hold the following: -- 32 1-byte samples when programmed as a UART or as an 8-bit CODEC interface -- 16 2-byte samples when programmed as a 16-bit CODEC interface -- 16 20-bit samples when programmed as a Digital AC '97 Controller The UART modules also provide several error-detection and maskable-interrupt capabilities. Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines. CLKIN provides the time base through a programmable prescaler. The UART time scale can also be sourced from a timer input. Full-duplex, auto-echo loopback, local loopback, 1-10 MCF5407 User's Manual ColdFire Module Description and remote loopback modes allow testing of UART connections. The programmable UARTs can interrupt the CPU on various normal or error-condition events. 1.3.6 Timer Module The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer for use in any of three modes. One mode captures the timer value with an external event. Another mode triggers an external signal or interrupts the CPU when the timer reaches a set value, while a third mode counts external events. The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system bus cycle or an external clock input pin (TIN). The programmable timer-output pin generates either an active-low pulse or toggles the output. 1.3.7 I2C Module The I2C interface is a two-wire, bidirectional serial bus used for quick data exchanges between devices. The I2C minimizes the interconnection between devices in the end system and is best suited for applications that need occasional bursts of rapid communication over short distances among several devices. The I2C can operate in master, slave, or multiple-master modes. 1.3.8 System Interface The MCF5407 processor provides a direct interface to 8-, 16-, and 32-bit FLASH, SRAM, ROM, and peripheral devices through the use of fully programmable chip selects and write enables. Support for burst ROMs is also included. Through the on-chip PLL, users can input a slower clock (25 to 54 MHz) that is internally multiplied to create the faster processor clock (100 to 162 MHz). 1.3.8.1 External Bus Interface The bus interface controller transfers information between the ColdFire core or DMA and memory, peripherals, or other devices on the external bus. The external bus interface provides up to 32 bits of address bus space, a 32-bit data bus, and all associated control signals. This interface implements an extended synchronous protocol that supports bursting operations. Simple two-wire request/acknowledge bus arbitration between the MCF5407 processor and another bus master, such as an external DMA device, is glueless with arbitration logic internal to the MCF5407 processor. Multiple-master arbitration is also available with some simple external arbitration logic. 1.3.8.2 Chip Selects Eight fully programmable chip select outputs support the use of external memory and peripheral circuits with user-defined wait-state insertion. These signals interface to 8-, 16-, Chapter 1. Overview 1-11 ColdFire Module Description or 32-bit ports. The base address, access permissions, and internal bus transfer terminations are programmable with configuration registers for each chip select. CS0 also provides global chip select functionality of boot ROM upon reset for initializing the MCF5407. 1.3.8.3 16-Bit Parallel Port Interface A 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin basis. 1.3.8.4 Interrupt Controller The interrupt controller provides user-programmable control of ten internal peripheral interrupts and implements four external fixed interrupt-request pins. Each internal interrupt can be programmed to any one of seven interrupt levels and four priority levels within each of these levels. Additionally, the external interrupt request pins can be mapped to levels 1, 3, 5, and 7 or levels 2, 4, 6, and 7. Autovector capability is available for both internal and external interrupts. 1.3.8.5 JTAG To help with system diagnostics and manufacturing testing, the MCF5407 processor includes dedicated user-accessible test logic that complies with the IEEE 1149.1a standard for boundary-scan testability, often referred to as the Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a standard. 1.3.9 System Debug Interface The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug unit in the MCF5407 is a compatible upgrade to the MCF52xx and MCF53xx debug modules with added breakpoint registers and support for I/O interrupt request servicing while in emulator mode. The on-chip breakpoint resources include a total of 13 programmable registers--two sets of address registers (each with two 32-bit registers), two sets of data registers (each with a 32-bit data register plus a 32-bit data mask register), one 32-bit PC register plus a 32-bit PC mask register and three additional 32-bit PC registers. These registers can be accessed through the dedicated debug serial communication channel or from the processor's supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF5407's new interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging. 1-12 MCF5407 User's Manual Programming Model, Addressing Modes, and Instruction Set To support program trace, the Version 4 debug module has combined the processor status and debug data outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at one-half the CPU's clock rate. 1.3.10 PLL Module The MCF5407 PLL module is shown in Figure 1-3. CLKIN (to on-chip peripherals) BCLKO PCLK (to core) CLKIN DIVIDE[2:0] RSTI Debug Module /2 PLL RSTO PSTCLK (= PCLK/2) Figure 1-3. PLL Module The PLL module's three modes of operation are described as follows. * * * Reset mode--When RSTI is asserted, the PLL enters reset mode. At reset, the PLL asserts RSTO from the MCF5407. The core:bus frequency ratio and other MCF5407 configuration information are sampled during reset. Normal mode--In normal mode, the input frequency programmed at reset is clock-multiplied to provide the processor clock (PCLK). Reduced-power mode--In reduced-power mode, the PCLK is disabled by executing a sequence that includes programming a control bit in the system configuration register (SCR) and then executing the STOP instruction. Register contents are retained in reduced-power mode, so the system can be reenabled quickly when an unmasked interrupt or reset is detected. 1.4 Programming Model, Addressing Modes, and Instruction Set The ColdFire programming model has two privilege levels--supervisor and user. The S bit in the status register (SR) indicates the privilege level. The processor identifies a logical address that differentiates between supervisor and user modes by accessing either the supervisor or user address space. Chapter 1. Overview 1-13 Programming Model, Addressing Modes, and Instruction Set * * 1-14 User mode--When the processor is in user mode (SR[S] = 0), only a subset of registers can be accessed, and privileged instructions cannot be executed. Typically, most application processing occurs in user mode. User mode is usually entered by executing a return from exception instruction (RTE, assuming the value of SR[S] saved on the stack is 0) or a MOVE, SR instruction (assuming SR[S] is 0). Supervisor mode--This mode protects system resources from uncontrolled access by users. In supervisor mode, complete access is provided to all registers and the entire ColdFire instruction set. Typically, system programmers use the supervisor programming model to implement operating system functions and provide I/O control. The supervisor programming model provides access to the same registers as the user model, plus additional registers for configuring on-chip system resources, as described in Section 1.4.3, "Supervisor Registers." Exceptions (including interrupts) are handled in supervisor mode. MCF5407 User's Manual Programming Model, Addressing Modes, and Instruction Set 1.4.1 Programming Model Figure 1-4 shows the MCF5407 programming model. 31 0 Data registers A0 A1 A2 A3 A4 A5 A6 A7 PC CCR Address registers MACSR ACC MASK MAC status register MAC accumulator MAC mask register SR VBR CACR ACR0 ACR1 ACR2 ACR3 RAMBAR0 RAMBAR1 MBAR Status register Vector base register Cache control register Access control register 0 (data) Access control register 1 (data) Access control register 2 (instruction) Access control register 3 (instruction) RAM 0 base address register RAM 1 base address register Module base address register 0 User Registers 31 D0 D1 D2 D3 D4 D5 D6 D7 31 Stack pointer Program counter Condition code register 0 15 19 Supervisor Registers 31 (CCR) Must be zeros Figure 1-4. ColdFire MCF5407 Programming Model 1.4.2 User Registers The user programming model is shown in Figure 1-4 and summarized in Table 1-1. Table 1-1. User-Level Registers Register Description Data registers (D0-D7) These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as index registers. Address registers (A0-A7) These 32-bit registers serve as software stack pointers, index registers, or base address registers. The base address registers can be used for word and longword operations. A7 functions as a hardware stack pointer during stacking for subroutine calls and exception handling. Chapter 1. Overview 1-15 Programming Model, Addressing Modes, and Instruction Set Table 1-1. User-Level Registers (Continued) Register Description Program counter (PC) Contains the address of the instruction currently being executed by the MCF5407 processor Condition code register (CCR) The CCR is the lower byte of the SR. It contains indicator flags that reflect the result of a previous operation and are used for conditional instruction execution. MAC status register (MACSR) Defines the operating configuration of the MAC unit and contains indicator flags from the results of MAC instructions. Accumulator (ACC) General-purpose register used to accumulate the results of MAC operations Mask register (MASK) General-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory. 1.4.3 Supervisor Registers Table 1-2 summarizes the MCF5407 supervisor-level registers. Table 1-2. Supervisor-Level Registers Register Description Status register (SR) The upper byte of the SR provides interrupt information in addition to a variety of mode indicators signaling the operating state of the ColdFire processor. The lower byte of the SR is the CCR, as shown in Figure 1-4. Vector base register (VBR) Defines the upper 12 bits of the base address of the exception vector table used during exception processing. The low-order 20 bits are forced to zero, locating the vector table on 0-modulo-1 Mbyte address. Cache configuration register (CACR) Defines the operating modes of the Version 4 cache memories. Control fields configuring the instruction, data, and branch cache are provided by this register, along with the default attributes for the 4-Gbyte address space. Access control registers (ACR0/1, ACR2/3) Define address ranges and attributes associated with various memory regions within the 4-Gbyte address space. Each ACR defines the location of a given memory region and assigns attributes such as write-protection and cache mode (copyback, write-through, cacheability). ACR0 and ACR1 support data memory; ACR2 and ACR3 support instruction memory. Additionally, CACR fields assign default attributes to the instruction and data memory spaces. RAM base address registers (RAMBAR0, RAMBAR1) Provide the logical base address for the two 2-Kbyte SRAM modules and define attributes and access types allowed for the corresponding SRAM. Module base address register (MBAR) Defines the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals. 1.4.4 Instruction Set The Version 4 ColdFire core implements Revision B of the instruction set, which adds opcodes to enhance support for byte- and word-sized operands and position-independent code. The ColdFire instruction set supports high-level languages and is optimized for those instructions most commonly generated by compilers in embedded applications. Table 2-8 provides an alphabetized listing of the ColdFire instruction set opcodes, supported 1-16 MCF5407 User's Manual Programming Model, Addressing Modes, and Instruction Set operation sizes, and assembler syntax. For two-operand instructions, the first operand is generally the source operand and the second is the destination. Because the ColdFire architecture provides an upgrade path for 68K customers, its instruction set supports most of the common 68K opcodes. A majority of the instructions are binary compatible or optimized 68K opcodes. This feature, when coupled with the code conversion tools from third-party developers, generally minimizes software porting issues for customers with 68K applications. The following list summarizes new and enhanced instructions of Revision B ISA: * * New instructions: -- INTOUCH loads blocks of instructions to be locked in the instruction cache. -- MOV3Q.L moves 3-bit immediate data to destination location. -- MVS.{B,W} sign-extends the source operand and moves it to destination register. -- MVZ.{B,W} zero-fills the source operand and moves it to destination register. -- SATS.L updates bit 31 of destination register depending on CCR overflow bit. -- TAS.B tests and set byte operand being addressed. Enhancements to existing Revision A instructions: -- Longword support for branch instructions (Bcc, BRA, BSR) -- Byte and word support for compare instructions (CMP, CMPI) -- Byte and longword support for MOVE.x where the source is of type #<data> and the destination is of type d16(Ax); that is, move.b #<data>, d16(Ax) Chapter 1. Overview 1-17 Programming Model, Addressing Modes, and Instruction Set 1-18 MCF5407 User's Manual Part I MCF5407 Processor Core Intended Audience Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5407. It also describes the operation of the MCF5407 ColdFire core and its multiply/accumulate (MAC) execution unit. It describes the programming and exception models, Harvard memory implementation, and debug module. Contents * * * Chapter 2, "ColdFire Core," provides an overview of the microprocessor core of the MCF5407. The chapter begins with a description of enhancements from the V3 ColdFire core, and then fully describes the V4 programming model as it is implemented on the MCF5407. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. Chapter 3, "Hardware Multiply/Accumulate (MAC) Unit," describes the MCF5407 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). Chapter 4, "Local Memory." This chapter describes the MCF5407 implementation of the ColdFire V4 local memory specification. It consists of the two following major sections. -- Section 4.2, "SRAM Overview," describes the MCF5407 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. -- Section 4.7, "Cache Overview," describes the MCF5407 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. Part I. MCF5407 Processor Core I-xix * Chapter 5, "Debug Support," describes the Revision C enhanced hardware debug support in the MCF5407. This revision of the ColdFire debug architecture encompasses earlier revisions. Suggested Reading The following literature may be helpful with respect to the topics in Part I: * * ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Acronyms and Abbreviations Table I-i contains acronyms and abbreviations are used in Part I. Table I-i. Acronyms and Abbreviated Terms Term Meaning ADC Analog-to-digital conversion ALU Arithmetic logic unit BDM Background debug mode BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing EA Effective address EDO Extended data output (DRAM) FIFO First-in, first-out GPIO General-purpose I/O I2C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out I-xx MCF5407 User's Manual Table I-i. Acronyms and Abbreviated Terms (Continued) Term Meaning LRU Least recently used LSB Least-significant byte lsb Least-significant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PCLK Processor clock PLL Phase-locked loop PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part I. MCF5407 Processor Core I-xxi I-xxii MCF5407 User's Manual Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5407. The chapter begins with a description of enhancements from the Version 3 (V3) ColdFire core, and then fully describes the V4 programming model as it is implemented on the MCF5407. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings. 2.1 Features and Enhancements The MCF5407 is the first standard product to contain a Version 4 ColdFire microprocessor core. To create this next-generation, high-performance core, many advanced microarchitectural techniques were implemented. Most notable are a Harvard memory architecture, branch cache acceleration logic, and limited superscalar dual-instruction issue capabilities, which together provide 233 (Dhrystone 2.1) MIPS performance at 162 MHz. The MCF5407 core design emphasizes performance and backward compatibility, and represents the next step on the ColdFire performance roadmap. The following list summarizes MCF5407 features: * * * * * * * * * * Variable-length RISC, clock-multiplied Version 4 microprocessor core Revision B of the ColdFire instruction set architecture provides new instructions to improve performance and code density Two independent, decoupled pipelines--four-stage instruction fetch pipeline (IFP) and five-stage operand execution pipeline (OEP) for increased performance of conditional branch instructions Ten-instruction FIFO buffer provides decoupling between the pipelines Limited superscalar design approaches dual-issue performance Sophisticated two-level branch acceleration mechanism with a branch cache plus a prediction table for increased performance of conditional Bcc instructions 32-bit internal address bus supporting 4 Gbytes of linear address space 32-bit data bus 16 user-accessible, 32-bit-wide, general-purpose registers Supervisor/user modes for system protection Chapter 2. ColdFire Core 2-1 Features and Enhancements * * Vector base register to relocate exception-vector table Optimized for high-level language constructs 2.1.1 Clock-Multiplied Microprocessor Core The MCF5407 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. The frequency of the processor complex is an integer multiple of the external bus speed. Chapter 20, "Electrical Specifications," lists the supported clock ratios. The processor, instruction and data caches, integrated SRAMs, and misalignment module operate at the higher speed clock (PCLK); other system integrated modules operate at the speed of the input clock (CLKIN). When combined with the enhanced pipeline structure of the Version 4 ColdFire core, the processor and its local memories provide a high level of performance for today's demanding embedded applications. PCLK can be disabled to minimize dissipation when a low-power mode is entered. This is described in Section 7.2.3, "Reduced-Power Mode." 2.1.2 Enhanced Pipelines The IFP prefetches instructions. The OEP decodes instructions, fetches required operands, then executes the specified function. The two independent, decoupled pipeline structures maximize performance while minimizing core size. Pipeline stages are shown in Figure 2-1 and are summarized as follows: * * 2-2 Four-stage IFP (plus optional instruction buffer stage) -- Instruction address generation (IAG) calculates the next prefetch address. -- Instruction fetch cycle 1 (IC1) initiates prefetch on the processor's local instruction bus. -- Instruction fetch cycle 2 (IC2) completes prefetch on the processor's instruction local bus. -- Instruction early decode (IED) generates time-critical decode signals needed for the OEP. -- Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of fetch latency. Five-stage OEP with two optional processor bus write cycles. -- Decode stage (DS/secDS) decodes and selects for two sequential instructions. -- Operand address generation (OAG) generates the address for the data operand. -- Operand fetch cycle 1 and 2 (OC1 and OC2) fetch data operands. -- Execute (EX) performs prescribed operations on previously fetched data operands. MCF5407 User's Manual Features and Enhancements -- Write data available (DA) makes data available for operand write operations only. -- Store data (ST) updates memory element for operand write operations only. Instruction Fetch Pipeline IAG Branch Cache Instruction Memory IC1 IC2 Branch Accel. IED IB Internal Bus Operand Execution Pipeline DS secDS OAG Data (Operand) Memory OC1 OC2 Misalignment Module EX DA Debug DSCLK DSI DSO DDATA PSTDDATA PSTCLK Figure 2-1. ColdFire Enhanced Pipeline Chapter 2. ColdFire Core 2-3 Features and Enhancements 2.1.2.1 Instruction Fetch Pipeline (IFP) Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls. 2.1.2.1.1 Branch Acceleration To maximize the performance of conditional branch instructions, the IFP implements a sophisticated two-level acceleration mechanism. The first level is an 8-entry, direct-mapped branch cache with 2 bits for indicating four prediction states (strongly/weakly taken/not-taken) for each entry. The branch cache also provides the association between instruction addresses and the corresponding target address. In the event of a branch cache hit, if the branch is predicted as taken, the branch cache sources the target address from the IC1 stage back into the IAG to redirect the prefetch stream to the new location. The branch cache implements instruction folding, so conditional branch instructions correctly predicted as taken can execute in zero cycles. For conditional branches with no information in the branch cache, a second-level, direct-mapped prediction table is accessed. Each of its 128 entries uses the same 2-bit prediction mechanism as the branch cache. If a branch is predicted as taken, branch acceleration logic in the IED stage generates the target address. Other change-of-flow instructions, including unconditional branches, jumps, and subroutine calls, use a similar mechanism where the IFP calculates the target address. The performance of subroutine return instruction (RTS) is improved through the use of a four-entry, LIFO hardware return stack. In all cases, these mechanisms allow the IFP to redirect the fetch stream down the predicted path well ahead of instruction execution. 2.1.2.2 Operand Execution Pipeline (OEP) The two instruction registers in the decode stage (DS) of the OEP are loaded from the FIFO instruction buffer or are bypassed directly from the instruction early decode (IED). The OEP consists of two, traditional two-stage RISC compute engines with a dual-ported register file access feeding an arithmetic logic unit (ALU). The compute engine at the top of the OEP (the address ALU) is used typically for operand address calculations; the execution ALU at the bottom is used for instruction execution. The resulting structure provides 4 Gbytes/S operand bandwidth (at 162 MHz) to the two compute engines and supports single-cycle execution speeds for most instructions, including all load and store operations and most embedded-load operations. The V4 OEP supports the ColdFire Revision B instruction set, which adds a few new instructions to improve performance and code density. The OEP also implements the following advanced performance features: * * 2-4 Stalls are minimized by dynamically basing the choice between the address ALU or execution ALU for instruction execution on the pipeline state. The address ALU and register renaming resources together can execute heavily used opcodes and forward results to subsequent instructions with no pipeline stalls. MCF5407 User's Manual Features and Enhancements * Instruction folding involving MOVE instructions allows two instructions to be issued in one cycle. The resulting microarchitecture approaches full superscalar performance at a much lower silicon cost. 2.1.2.2.1 Illegal Opcode Handling To aid in conversion from M68000 code, every 16-bit operation word is decoded to ensure that each instruction is valid. If the processor attempts execution of an illegal or unsupported instruction, an illegal instruction exception (vector 4) is taken. 2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit The MAC is an optional unit in Version 4 that provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family. The MAC features a three-stage execution pipeline, optimized for 16 x 16 multiplies. It is tightly coupled to the OEP, which can issue a 16 x 16 multiply with a 32-bit accumulation plus fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires three cycles before the next instruction can be issued. Figure 2-2 shows basic functionality of the MAC. A full set of instructions are provided for signed and unsigned integers plus signed, fixed-point fractional input operands. Operand Y Operand X X Shift 0,1,-1 +/- Accumulator Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, "Hardware Multiply/Accumulate (MAC) Unit." * * * Signed and unsigned integer multiplies Multiply-accumulate operations with signed and unsigned fractional operands Miscellaneous register operations Chapter 2. ColdFire Core 2-5 Features and Enhancements 2.1.2.2.3 Hardware Divide Unit The hardware divide unit performs the following integer division operations: * * * 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder 32-bit operand/32-bit operand producing a 32-bit quotient 32-bit operand/32-bit operand producing a 32-bit remainder 2.1.2.3 Harvard Memory Architecture A Harvard memory architecture supports the increased bandwidth requirements of the V4 processor pipelines by providing separate configuration, access control, and protection resources for data (operand) and instruction memory. The MCF5407 has separate instruction and data buses to processor-local memories, eliminating conflicts between instruction fetches and operand accesses. 2.1.3 Debug Module Enhancements The ColdFire processor core debug interface supports system integration in conjunction with low-cost development tools. Real-time trace and debug information can be accessed through a standard interface, which allows the processor and system to be debugged at full speed without costly in-circuit emulators. The MCF5407 debug unit is a compatible upgrade to MCF52xx and MCF53xx debug modules with added breakpoint registers and support for I/O interrupt request servicing while in emulator mode. On-chip breakpoint resources include the following: * Configuration/status register (CSR) * Background debug mode (BDM) address attributes register (BAAR) * Bus attributes and mask registers (AATR and AATR1) * Breakpoint registers. These can be used to define triggers combining address, data, and PC conditions in single- or dual-level definitions. They include the following: * -- Four PC breakpoint registers (PBR, PBR1, PBR2, and PBR3) -- PC breakpoint mask register (PBMR) -- Two pairs of data operand address breakpoint registers (ABHR/ABLR and ABLR1/ABHR1) -- Data breakpoint registers (DBR and DBR1) -- Data breakpoint mask registers (DBMR and DBMR1) Trigger event registers. These can be programmed to generate a processor halt or initiate a debug interrupt exception. They include the following: -- Trigger definition register (TDR) -- Extended trigger definition register (XTDR) 2-6 MCF5407 User's Manual Programming Model These registers can be accessed through the dedicated debug serial communication channel, or from the processor's supervisor programming model, using the WDEBUG instruction. The MCF5407's new interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging. To support program trace, the Version 4 debug module combines the processor status and debug data outputs into a single 8-bit bus, PSTDDATA[7:0]. This bus along with the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at one-half the CPU's clock rate. The enhancements of the Revision C debug specification are fully backward-compatible with the A and B revisions. For more information, see Chapter 5, "Debug Support." 2.2 Programming Model The MCF5407 programming model consists of three instruction and register groups--user, MAC (also user-mode), and supervisor, shown in Figure 2-2. User mode programs are restricted to user and MAC instructions and programming models. Supervisor-mode system software can reference all user-mode and MAC instructions and registers and additional supervisor instructions and control registers. The user or supervisor programming model is selected based on SR[S]. The following sections describe the registers in the user, MAC, and supervisor programming models. Chapter 2. ColdFire Core 2-7 Programming Model 31 0 Data registers A0 A1 A2 A3 A4 A5 A6 A7 PC CCR Address registers MACSR ACC MASK MAC status register MAC accumulator MAC mask register SR VBR CACR ACR0 ACR1 ACR2 ACR3 RAMBAR0 RAMBAR1 MBAR Status register Vector base register Cache control register Access control register 0 (data) Access control register 1 (data) Access control register 2 (instruction) Access control register 3 (instruction) RAM 0 base address register RAM 1 base address register Module base address register 0 User Registers 31 D0 D1 D2 D3 D4 D5 D6 D7 31 Stack pointer Program counter Condition code register 0 15 Supervisor Registers 31 19 (CCR) Must be zeros Figure 2-3. ColdFire Programming Model 2.2.1 User Programming Model As Figure 2-3 shows, the user programming model consists of the following registers: * * * 16 general-purpose 32-bit registers, D0-D7 and A0-A7 32-bit program counter 8-bit condition code register 2.2.1.1 Data Registers (D0-D7) Registers D0-D7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit) operations. They may also be used as index registers. 2-8 MCF5407 User's Manual Programming Model 2.2.1.2 Address Registers (A0-A6) The address registers (A0-A6) can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations. 2.2.1.3 Stack Pointer (A7, SP) The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register. The initial value of A7 is loaded from the reset exception vector, address 0x0000. The same register is used for user and supervisor modes, and may be used for word and longword operations. A subroutine call saves the program counter (PC) on the stack and the return restores the PC from the stack. The PC and the status register (SR) are saved on the stack during exception and interrupt processing. The return from exception instruction restores SR and PC values from the stack. 2.2.1.4 Program Counter (PC) The PC holds the address of the executing instruction. For sequential instructions, the processor automatically increments PC. When program flow changes, the PC is updated with the target instruction. For some instructions, the PC specifies the base address for PC-relative operand addressing modes. 2.2.1.5 Condition Code Register (CCR) The CCR, Figure 2-4, occupies SR[7-0], as shown in Figure 2-3. CCR[4-0] are indicator flags based on results generated by arithmetic operations. 7 Field 4 3 2 1 0 -- 6 5 X N Z V C R R/W R/W R/W R/W Reset R/W Undefined R/W Figure 2-4. Condition Code Register (CCR) Table 2-1 describes the CCR fields. Chapter 2. ColdFire Core 2-9 Programming Model Table 2-1. CCR Field Descriptions Bits Name Description 7-5 -- Reserved, should be cleared. 4 X Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic. 3 N Negative condition code bit. Set if the msb of the result is set; otherwise cleared. 2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared. 1 V Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand size; otherwise cleared. 0 C Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. 2.2.1.6 MAC Programming Model Figure 2-3 shows the registers in the MAC portion of the user programming model. These registers are described as follows: * * * Accumulator (ACC)--This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. Mask register (MASK)--This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory. MAC status register (MACSR)--This 8-bit register defines configuration of the MAC unit and contains indicator flags affected by MAC instructions. Unless noted otherwise, MACSR indicator flag settings are based on the final result, that is, the result of the final operation involving the product and accumulator. 2.2.2 Supervisor Programming Model The MCF5407 supervisor programming model is shown in Figure 2-3. Typically, system programmers use the supervisor programming model to implement operating system functions and provide memory and I/O control. The supervisor programming model provides access to the user registers and additional supervisor registers, which include the upper byte of the status register (SR), the vector base register (VBR), and registers for configuring attributes of the address space connected to the Version 4 processor core. Most supervisor-level registers are accessed by using the MOVEC instruction with the control register definitions in Table 2-2. 2-10 MCF5407 User's Manual Programming Model Table 2-2. MOVEC Register Map Rc[11-0] Register Definition 0x002 Cache control register (CACR) 0x004 Access control register 0 (ACR0) 0x005 Access control register 1 (ACR1) 0x006 Access control register 2 (ACR2) 0x007 Access control register 3 (ACR3) 0x801 Vector base register (VBR) 0xC04 RAM base address register 0 (RAMBAR0) 0xC05 RAM base address register 1 (RAMBAR1) 0xC0F Module base address register (MBAR) 2.2.2.1 Status Register (SR) The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software can read or write the entire SR; user software can read or write only SR[7-0], described in Section 2.2.1.5, "Condition Code Register (CCR)." The control bits indicate processor states--trace mode (T), supervisor or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset. 15 14 13 12 11 10 9 8 7 6 System byte 5 4 3 2 1 0 Condition code register (CCR) Field T -- S M -- I -- X N Z V C Reset 0 0 1 0 0 111 000 -- -- -- -- -- R R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W Figure 2-5. Status Register (SR) Table 2-3 describes SR fields. Table 2-3. Status Field Descriptions Bits Name Description 15 T Trace enable. When T is set, the processor performs a trace exception after every instruction. 13 S Supervisor/user state. Indicates whether the processor is in supervisor or user mode 0 User mode 1 Supervisor mode 12 M Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer. 10-8 I Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all priority levels less than or equal to the current priority, except the edge-sensitive level-7 request, which cannot be masked. 7-0 CCR Condition code register. See Table 2-1. Chapter 2. ColdFire Core 2-11 Programming Model 2.2.2.2 Vector Base Register (VBR) The VBR holds the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. VBR[19-0] are not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte boundary. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Field Reset Exception vector table base address 9 8 7 6 5 4 3 2 1 0 -- 0000_0000_0000_0000_0000_0000_0000_0000 R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined. Rc[11-0] 0x801 Figure 2-6. Vector Base Register (VBR) 2.2.2.3 Cache Control Register (CACR) The CACR controls operation of both the instruction and data cache memory. It includes bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and write-protect fields. See Section 4.10.1, "Cache Control Register (CACR)." 2.2.2.4 Access Control Registers (ACR0-ACR3) The access control registers (ACR0-ACR3) define attributes for four user-defined memory regions. ACR0 and ACR1 control data memory space and ACR2 and ACR3 control instruction memory space. Attributes include definition of cache mode, write protect and buffer write enables. See Section 4.10.2, "Access Control Registers (ACR0-ACR3)." 2.2.2.5 RAM Base Address Registers (RAMBAR0 and RAMBAR1) The RAMBAR registers determine the base address location of the internal SRAM modules and indicate the types of references mapped to each. Each RAMBAR includes a base address, write-protect bit, address space mask bits, and an enable. The RAM base address must be aligned on a 0-module-2-Kbyte boundary. See Section 4.4.1, "SRAM Base Address Registers (RAMBAR0/RAMBAR1)." 2.2.2.6 Module Base Address Register (MBAR) The module base address register (MBAR) defines the logical base address for the memory-mapped space containing the control registers for the on-chip peripherals. See Section 6.2.2, "Module Base Address Register (MBAR)." 2-12 MCF5407 User's Manual Integer Data Formats 2.3 Integer Data Formats Table 2-4 lists the integer operand data formats. Integer operands can reside in registers, memory, or instructions. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Table 2-4. Integer Data Formats Operand Data Format Size Bit 1 bit Byte integer 8 bits Word integer 16 bits Longword integer 32 bits 2.4 Organization of Data in Registers The following sections describe data organization within the data, address, and control registers. 2.4.1 Organization of Integer Data Formats in Registers Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. Longword operands occupy the entire 32 bits of integer data registers. A data register that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits in byte or word operations, respectively. The remaining high-order portion does not change. The least significant bit (lsb) of all integer sizes is zero, the most-significant bit (msb) of a longword integer is 31, the msb of a word integer is 15, and the msb of a byte integer is 7. 31 30 1 msb 31 7 Not used 31 msb Bit (0 bit number 31) 0 msb Low order byte lsb Lower order word lsb 15 Not used Byte (8 bits) 0 31 msb 0 lsb Word (16 bits) 0 Longword lsb Longword (32 bits) Figure 2-7. Organization of Integer Data Formats in Data Registers The instruction set encodings do not allow the use of address registers for byte-sized operands. When an address register is a source operand, either the low-order word or the entire longword operand is used, depending on the operation size. Word-length source Chapter 2. ColdFire Core 2-13 Organization of Data in Registers operands are sign-extended to 32 bits and then used in the operation with anaddress register destination. When an address register is a destination, the entire register is affected, regardless of the operation size. Figure 2-8 shows integer formats for address registers. 31 16 15 0 Sign-Extended 16-Bit Address Operand 31 0 Full 32-Bit Address Operand Figure 2-8. Organization of Integer Data Formats in Address Registers The size of control registers varies according to function. Some have undefined bits reserved for future definition by Motorola. Those particular bits read as zeros and must be written as zeros for future compatibility. All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege mode. 2.4.2 Organization of Integer Data Formats in Memory All ColdFire processors use a big-endian addressing scheme. The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address N of a longword data item corresponds to the address of the high-order word. The lower order word is located at address N + 2. The address N of a word data item corresponds to the address of the high-order byte. The lower order byte is located at address N + 1. This organization is shown in Figure 2-9. 31 23 15 7 0 Longword 0x0000_0000 Word 0x0000_0000 Byte 0x0000_0000 Word 0x0000_0002 Byte 0x0000_0001 Byte 0x0000_0002 Byte 0x0000_0003 Longword 0x0000_0004 Word 0x0000_0004 Byte 0x0000_0004 Word 0x0000_0006 Byte 0x0000_0005 Byte 0x0000_0006 Byte 0x0000_0007 . . . Longword 0xFFFF_FFFC Word 0xFFFF_FFFC Byte 0xFFFF_FFFC Word 0xFFFF_FFFE Byte 0xFFFF_FFFD Byte 0xFFFF_FFFE Byte 0xFFFF_FFFF Figure 2-9. Memory Operand Addressing 2-14 MCF5407 User's Manual Addressing Mode Summary 2.5 Addressing Mode Summary Addressing modes are categorized by how they are used. Data addressing modes refer to data operands. Memory addressing modes refer to memory operands. Alterable addressing modes refer to alterable (writable) data operands. Control addressing modes refer to memory operands without an associated size. These categories sometimes combine to form more restrictive categories. Two combined classifications are alterable memory (both alterable and memory) and data alterable (both alterable and data). Twelve of the most commonly used effective addressing modes from the M68000 Family are available on ColdFire microprocessors. Table 2-5 summarizes these modes and their categories. Table 2-5. ColdFire Effective Addressing Modes Addressing Modes Mode Field Reg. Field Dn An 000 001 (An) (An)+ -(An) (d16, An) Syntax Category Data Memory Control Alterable reg. no. reg. no. X -- -- -- -- -- X X 010 011 100 101 reg. no. reg. no. reg. no. reg. no. X X X X X X X X X -- -- X X X X X (d8, An, Xi*SF) 110 reg. no. X X X X Program counter indirect with displacement (d16, PC) 111 010 X X X -- Program counter indirect with scaled index 8-bit displacement (d8, PC, Xi*SF) 111 011 X X X -- Absolute data addressing Short Long (xxx).W (xxx).L 111 111 000 001 X X X X X X -- -- Immediate #<xxx> 111 100 X X -- -- Register direct Data Address Register indirect Address Address with Postincrement Address with Predecrement Address with Displacement Address register indirect with scaled index 8-bit displacement 2.6 Instruction Set Summary The ColdFire instruction set is a simplified version of the M68000 instruction set. The removed instructions include BCD, bit field, logical rotate, decrement and branch, and integer multiply with a 64-bit result. Nine new MAC instructions have been added. Table 2-6 lists notational conventions used throughout this manual. Chapter 2. ColdFire Core 2-15 Instruction Set Summary Table 2-6. Notational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition (example: NE for not equal) Register Specifications An Ay,Ax Any address register n (example: A3 is address register 3) Source and destination address registers, respectively Dn Any data register n (example: D5 is data register 5) Dy,Dx Source and destination data registers, respectively Rc Any control register (example VBR is the vector base register) Rm MAC registers (ACC, MAC, MASK) Rn Any address or data register Rw Destination register w (used for MAC instructions only) Ry,Rx Xi Any source and destination registers, respectively index register i (can be an address or data register: Ai, Di) Register Names ACC MAC accumulator register CCR Condition code register (lower byte of SR) MACSR MAC status register MASK MAC mask register PC Program counter SR Status register Port Name PSTDDATA Processor status/debug data port Miscellaneous Operands #<data> <ea> <ea>y,<ea>x <label> <list> Source and destination effective addresses, respectively Assembly language program label List of registers for MOVEM instruction (example: D3-D0) <shift> Shift operation: shift left (<<), shift right (>>) <size> Operand data size: byte (B), word (W), longword (L) bc Both instruction and data caches dc Data cache ic Instruction cache # <vector> <> 2-16 Immediate data following the 16-bit operation word of the instruction Effective address Identifies the 4-bit vector number for trap instructions identifies an indirect data address referencing memory MCF5407 User's Manual Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction <xxx> Operand Syntax identifies an absolute address referencing memory dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) Operations + Arithmetic addition or postincrement indicator - Arithmetic subtraction or predecrement indicator x Arithmetic multiplication / Arithmetic division ~ Invert; operand is logically complemented & Logical AND | Logical OR ^ Logical exclusive OR << Shift left (example: D0 << 3 is shift D0 left 3 bits) >> Shift right (example: D0 >> 3 is shift D0 right 3 bits) Source operand is moved to destination operand Two operands are exchanged sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion If <condition> then <operations> else <operations> Test the condition. If the condition is true, the operations in the then clause are performed. If the condition is false and the optional else clause is present, the operations in the else clause are performed. If the condition is false and the else clause is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. Subfields and Qualifiers {} Optional operation () Identifies an indirect address dn Displacement value, n-bits wide (example: d16 is a 16-bit displacement) Address Calculated effective address (pointer) Bit Bit selection (example: Bit 3 of D0) lsb Least significant bit (example: lsb of D0) LSB Least significant byte LSW Least significant word msb Most significant bit MSB Most significant byte MSW Most significant word Chapter 2. ColdFire Core 2-17 Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction Operand Syntax Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero 2.6.1 Additions to the Instruction Set Architecture The original ColdFire instruction set architecture (ISA) was derived from the M68000 Family opcodes based on extensive analysis of embedded application code. After the initial ColdFire compilers were created, developers identified ISA additions that would enhance both code density and overall performance. Additionally, as users implemented ColdFire-based designs into a wide range of embedded systems, they identified frequently used instruction sequences that could be improved by the creation of new instructions. This observation was especially prevalent in development environments that made use of substantial amounts of assembly language code. The original ISA definition minimized the support for instructions referencing byte and word operands. Full support for the MOVE.B and MOVEC.W instructions was provided, but clr (clear) and tst (test) are the only other opcodes supporting these data types. Based on input from compiler writers and system users, a set of instruction enhancements was proposed that address the two following areas: * * Enhanced support for byte and word-sized operands through new move operations Enhanced support for position-independent code The following list summarizes new and enhanced instructions of Revision_B ISA: * 2-18 New instructions: -- INTOUCH loads blocks of instructions to be locked in the instruction cache -- MOV3Q.L moves 3-bit immediate data to the destination location -- MVS.{B,W} sign-extends the source operand and moves it to the destination register -- MVZ.{B,W} zero-fills the source operand and moves it to the destination register -- SATS.L updates the destination register depending on CCR[V] and bit 31 of the register -- TAS.B performs an indivisible read-modify-write cycle to test and set the addressed memory byte. MCF5407 User's Manual Instruction Set Summary * Enhancements to existing Revision_A instructions: -- Longword support for branch instructions (Bcc, BRA, BSR) -- Byte and word support for compare instructions (CMP, CMPI) -- Word support for the compare address register instruction (CMPA) -- Byte and longword support for MOVE.x ,where the source is immediate data and the destination is specified by d16(Ax); that is, MOVE.{B,W} #<data>, d16(Ax) Table 2-7 shows the syntax for the new and enhanced instructions, which are fully described in Section 2.9, "ColdFire Instruction Set Architecture Enhancements." Table 2-7. ColdFire ISA_B Extension Summary Mnemonic1 Instruction Destination 68K Branch Always bra.l <label> Yes Branch Conditionally bcc.l <label> Yes Branch to Subroutine bsr.l <label> Yes Compare Compare Address Compare Immediate Source cmp.{b,w,l} <ea>y Dx Yes cmpa.w <ea>y Ax Yes cmpi.{b,w} #<data> Dx Yes Instruction Fetch Touch intouch <Ay> Move 3-Bit Data Quick mov3q.l #<data> <ea>x Move Data Source to Destination move.{b,w} #<data> d16(Ax) Move with Sign Extend mvs.{b,w} <ea>y Dx Move with Zero-Fill mvz.{b,w} <ea>y Dx Signed Saturate sats.l Dx Test and Set an Operand tas.b <ea>x 1 Yes Yes Operand sizes in this column reflect only newly supported operand sizes for existing instructions (Bcc, BRA, BSR, CMP, CMPA, CMPI, and MOVE) Some proposed opcodes were formerly present in the M68000 family, while other opcodes are new functions. 2.6.2 Instruction Set Summary Table 2-8 lists implemented user-level instructions by opcode. Table 2-8. User-Level Instruction Set Summary Instruction Operand Syntax Operand Size Operation ADD Dy,<ea>x <ea>y,Dx .L .L Source + destination destination ADDA <ea>y,Ax .L Source + destination destination Chapter 2. ColdFire Core 2-19 Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation ADDI #<data>,Dx .L Immediate data + destination destination ADDQ #<data>,<ea>x .L Immediate data + destination destination ADDX Dy,Dx .L Source + destination + X destination AND Dy,<ea>x <ea>y,Dx .L .L Source & destination destination ANDI #<data>,Dx .L Immediate data & destination destination ASL Dy,Dx #<data>,Dx .L .L X/C (Dx << Dy) 0 X/C (Dx << #<data>) 0 ASR Dy,Dx #<data>,Dx .L .L MSB (Dx >> Dy) X/C MSB (Dx >> #<data>) X/C Bcc <label> .B,.W,.L If condition true, then PC + 2 + dn PC BCHG Dy,<ea>x #<data>,<ea-1>x .B,.L .B,.L ~(<bit number> of destination) Z, Bit of destination BCLR Dy,<ea>x #<data>,<ea-1>x .B,.L .B,.L ~(<bit number> of destination) Z; 0 bit of destination BRA <label> .B,.W,.L PC + 2 + dn PC BSET Dy,<ea>x #<data>,<ea-1>x .B,.L .B,.L ~(<bit number> of destination) Z; 1 bit of destination BSR <label> .B,.W,.L SP - 4 SP; next sequential PC (SP); PC + 2 + dn PC BTST Dy,<ea>x #<data>,<ea-1>x .B,.L .B,.L ~(<bit number> of destination) Z CLR <ea>y,Dx .B,.W,.L 0 destination CMP <ea>y,Ax .B,.W,.L Destination - source CMPA <ea>y,Dx .W,.L Destination - source CMPI <ea>y,Dx .B,.W,.L Destination - immediate data DIVS <ea-1>y,Dx <ea>y,Dx .W .L Dx /<ea>y Dx {16-bit remainder; 16-bit quotient} Dx /<ea>y Dx {32-bit quotient} Signed operation DIVU <ea-1>y,Dx Dy,<ea>x .W .L Dx /<ea>y Dx {16-bit remainder; 16-bit quotient} Dx /<ea>y Dx {32-bit quotient} Unsigned operation EOR Dy,<ea>x .L Source ^ destination destination EORI #<data>,Dx .L Immediate data ^ destination destination EXT #<data>,Dx .B .W .W .L Sign-extended destination destination EXTB Dx .B .L Sign-extended destination destination HALT1 None Unsized Enter halted state JMP <ea-3>y Unsized Address of <ea> PC JSR <ea-3>y Unsized SP - 4 SP; next sequential PC (SP); <ea> PC LEA <ea-3>y,Ax .L <ea> Ax 2-20 MCF5407 User's Manual Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation LINK Ax,#<d16> .W SP - 4 SP; Ax (SP); SP Ax; SP + d16 SP LSL Dy,Dx #<data>,Dx .L .L X/C (Dx << Dy) 0 X/C (Dx << #<data>) 0 LSR Dy,Dx #<data>,Dx .L .L 0 (Dx >> Dy) X/C 0 (Dx >> #<data>) X/C MAC Ry,RxSF .L + (.W x .W) .L .L + (.L x .L) .L ACC + (Ry x Rx){<< 1 | >> 1} ACC ACC + (Ry x Rx){<< 1 | >> 1} ACC; (<ea>y{&MASK}) Rw MACL Ry,RxSF,<ea-1>y,Rw .L + (.W x .W) .L, .L .L + (.L x .L) .L, .L ACC + (Ry x Rx){<< 1 | >> 1} ACC ACC + (Ry x Rx){<< 1 | >> 1} ACC; (<ea-1>y{&MASK}) Rw MOV3Q #<data>,<ea>x .L 3-bit immediatedestination MOVE <ea>y,<ea>x .B,.W,.L <ea>y <ea>x MOVE from MAC MASK,Rx ACC,Rx MACSR,Rx .L Rm Rx MACSR,CCR .L MACSR CCR Ry,ACC Ry,MACSR Ry,MASK .L Ry Rm #<data>,ACC #<data>,MACSR #<data>,MASK .L #<data> Rm MOVE from CCR CCR,Dx .W CCR Dx MOVE to CCR Dy,CCR #<data>,CCR .B Dy CCR #<data> CCR MOVEA <ea>y,Ax .W,.L .L Source destination MOVEM #<list>,<ea-2>x <ea-2>y,#<list> .L .L Listed registers destination Source listed registers MOVE to MAC MOVEQ #<data>,Dx .B .L Sign-extended immediate data destination MSAC Ry,RxSF .L - (.W x .W) .L .L - (.L x .L) .L ACC - (Ry x Rx){<< 1 | >> 1} ACC MSACL Ry,RxSF,<ea-1>y,Rw .L - (.W x .W) .L, .L .L - (.L x .L) .L, .L ACC - (Ry x Rx){<< 1 | >> 1} ACC; (<ea-1>y{&MASK}) Rw MULS <ea>y,Dx .W X .W .L .L X .L .L Source x destination destination Signed operation MULU <ea>y,Dx .W X .W .L .L X .L .L Source x destination destination Unsigned operation MVS <ea>y,Dx .B,.W Sign-extended source destination MVZ <ea-1>y,Dx .B,.W Zero-filled source destination NEG Dx .L 0 - destination destination NEGX Dx .L 0 - destination - X destination Chapter 2. ColdFire Core 2-21 Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation NOP none Unsized Synchronize pipelines; PC + 2 PC NOT Dx .L ~ Destination destination OR <ea>y,Dx Dy,<ea>x .L Source | destination destination ORI #<data>,Dx .L Immediate data | destination destination PEA <ea-3>y .L SP - 4 SP; Address of <ea> (SP) PULSE none Unsized Set PST= 0x4 REMS <ea-1>,Dx .L Dx/<ea>y Dw {32-bit remainder} Signed operation REMU <ea-1>,Dx .L Dx/<ea>y Dw {32-bit remainder} Unsigned operation RTS none Unsized (SP) PC; SP + 4 SP SATS Dx .L If CCR.V=1, then if Dx[31] =0 then 0x80000000 Dx else 0x7FFFFFFF Dx else Dx is unchanged Scc Dx .B If condition true, then 1s destination; Else 0s destination SUB <ea>y,Dx Dy,<ea>x .L .L Destination - source destination SUBA <ea>y,Ax .L Destination - source destination SUBI #<data>,Dx .L Destination - immediate data destination SUBQ #<data>,<ea>x .L Destination - immediate data destination SUBX Dy,Dx .L Destination - source - X destination SWAP Dx .W MSW of Dx LSW of Dx TAS <ea>x .B Set CCR; 1 Bit 7 of <ea>x TRAP #<vector> Unsized SP - 4 SP;PC (SP); SP - 2 SP;SR (SP); SP - 2 SP; format (SP); Vector address PC TRAPF None #<data> Unsized .W .L PC + 2 PC PC + 4 PC PC + 6 PC TST <ea>y .B,.W,.L Set condition codes UNLK Ax Unsized Ax SP; (SP) Ax; SP + 4 SP WDDATA <ea>y .B,.W,.L <ea>y DDATA port 1 By default the HALT instruction is a supervisor-level instruction; however, it can be configured to allow user-mode execution by setting CSR[UHE]. Table 2-9 describes supervisor-level instructions. 2-22 MCF5407 User's Manual Execution Timings Table 2-9. Supervisor-Level Instruction Set Summary Instruction CPUSHL Operand Syntax Operand Size (An) Unsized Operation Invalidate instruction cache line Push and invalidate data cache line Push data cache line and invalidate (I,D)-cache lines HALT1 none Unsized Enter halted state INTOUCH (Ay) Unsized Touch instruction space at address Ay MOVE from SR SR, Dx .W SR Dx MOVE to SR Dy,SR .W Source SR #<data>,SR MOVEC Ry,Rc .L Ry Rc Rc Register Definition 0x002 0x004 0x005 0x006 0x007 0x801 0xC04 0xC05 Cache control register (CACR) Access control register 0 (ACR0) Access control register 1 (ACR1) Access control register 2 (ACR2) Access control register 3 (ACR3) Vector base register (VBR) RAM base address register 0 (RAMBAR0) RAM base address register 1 (RAMBAR1) RTE None Unsized (SP+2) SR; SP+4 SP; (SP) PC; SP + formatfield SP STOP #<data> .W Immediate data SR; enter stopped state WDEBUG <ea-2>y .L <ea-2>y debug module 1 The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE]. 2.7 Execution Timings The timing data presented in this section assumes the following: * * * Execution times are shown for individual instructions without assumptions regarding the OEP's ability to dispatch multiple instructions at a time. For sequences where instruction pairs are issued, the execution time of the two instructions is defined by the execution time of the first instruction; that is, the second instruction effectively executes in zero cycles. The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP spends no time waiting for the IFP to supply opwords and/or extension words. The OEP experiences no sequence-related pipeline stalls. For the MCF5407, the most common example of such a stall occurs when a register is modified in the EX compute engine and a subsequent instruction generating an address uses the previously modified register. The second instruction stalls in the OEP until the register is updated by the previous instruction. For example: muls.l move.l #<data>,d0 (a0,d0.l*4),d1 Chapter 2. ColdFire Core 2-23 Execution Timings In this sequence, the second instruction is held for three cycles stalling for the multiply instruction to update d0. If consecutive instructions update a register and use that register as a base of index value with a scale factor of 1 (Xi.l*1) in an address calculation, a two-cycle pipeline stall occurs. Using the destination register as an index register with any other scale factor (Xi.l*2, Xi.l*4) causes a three-cycle stall. Some instructions are optimized to ensure against causing such stalls on subsequent instructions. The destination register on the following instructions is always available for subsequent instructions: lea move.l mov.w moveq clr.l mov3q.l <op> <op> <op> <op> * * <ea>y,Ax #<data>,Rx #<data>,Ax #<data>,Dx Dx #<data>,Rx (Ay)+,Rx -(Ay),Rx Ry,(Ax)+ Ry,-(Ax) Note that the address register results from postincrement and predecrement modes are available to subsequent instructions without stalls. The OEP can complete all memory accesses without memory causing any stall conditions. Thus, timing details in this section assume an infinite zero-wait state memory attached to the core. Operand data accesses are assumed to be aligned on the same byte boundary as the operand size: -- 16-bit operands aligned on 0-modulo-2 addresses -- 32-bit operands aligned on 0-modulo-4 addresses Operands not meeting these guidelines are misaligned. Table 2-10 shows how the core decomposes a misaligned operand reference into a series of aligned accesses. Table 2-10. Misaligned Operand References Additional C(R/W) 1 A[1:0] 1 Size Bus Operations Read Write x1 Word Byte, Byte 2(1/0) 1(0/1) x1 Long Byte, Word, Byte 3(2/0) 2(0/2) 10 Long Word, Word 2(1/0) 1(0/1) Each timing entry is presented as C(R/W), described as follows: C is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all internal core cycles required to complete the instruction execution. R/W is the number of operand reads (r) and writes (w) required by the instruction. An operation performing a read-modify write function is denoted as (1/1). 2-24 MCF5407 User's Manual Execution Timings 2.7.1 MOVE Instruction Execution Timing Execution timing for the MOVE.{B,W,L} instructions are shown in the next tables. Table 2-13 shows the timing for the other generic move operations. NOTE: For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is equivalent to the time using comparable An-relative mode. ET with {<ea> = (d16,PC)} ET with {<ea> = (d8,PC,Xi*SF)} equals ET with {<ea> = (d16,An)} equals ET with {<ea> = (d8,An,Xi*SF)} The nomenclature "(xxx).wl" refers to both forms of absolute addressing, (xxx).w and (xxx).l. Table 2-11 lists execution times for MOVE.{B,W} instructions. Table 2-11. Move Byte and Word Execution Times Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (Ay)+ 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -(Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- (d8,Ay,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) -- -- -- (xxx).w 1(1/0) 2(1/1) 2(1/1) 2(1/1) -- -- -- (xxx).l 1(1/0) 2(1/1) 2(1/1) 2(1/1) -- -- -- (d16,PC) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- (d8,PC,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) -- -- -- #<xxx> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) -- -- Table 2-12 lists timings for MOVE.L. Table 2-12. Move Long Execution Times Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl Dy 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) Ay 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (Ay)+ 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) Chapter 2. ColdFire Core 2-25 Execution Timings Table 2-12. Move Long Execution Times (Continued) Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl -(Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) (d16,Ay) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- (d8,Ay,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) -- -- -- (xxx).w 1(1/0) 2(1/1) 2(1/1) 2(1/1) -- -- -- -- (xxx).l 1(1/0) 2(1/1) 2(1/1) 2(1/1) -- -- (d16,PC) 1(1/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- (d8,PC,Xi*SF) 2(1/0) 3(1/1) 3(1/1) 3(1/1) -- -- -- #<xxx> 1(0/0) 1(0/1) 1(0/1) 1(0/1) -- -- -- Table 2-13 gives execution times for MOVE.L instructions accessing program-visible registers of the MAC unit, along with other MOVE.L timings. Execution times for moving contents of the ACC or MACSR into a destination location represent the best-case scenario when the store instruction is executed and no load, MAC, or MSAC instructions are in the MAC execution pipeline. In general, these store operations require only one cycle for execution, but if they are preceded immediately by a load, MAC, or MSAC instruction, the MAC pipeline depth is exposed and execution time is 3 cycles. Table 2-13. Miscellaneous Move Execution Times Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> move.l <ea>,ACC 1(0/0) -- -- -- -- -- -- 1(0/0) move.l <ea>,MACSR 6(0/0) -- -- -- -- -- -- 6(0/0) move.l <ea>,MASK 5(0/0) -- -- -- -- -- -- 5(0/0) move.l ACC,Rx 1(0/0) -- -- -- -- -- -- -- move.l MACSR,CCR 1(0/0) -- -- -- -- -- -- -- move.l MACSR,Rx 1(0/0) -- -- -- -- -- -- -- move.l MASK,Rx 1(0/0) -- -- -- -- -- -- -- moveq #imm,Dx -- -- -- -- -- -- -- 1(0/0) mov3q #imm,<ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) -- mvs <ea>,Dx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) mvz <ea>,Dx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) 2.7.2 Execution Timings--One-Operand Instructions Table 2-14 shows standard timings for single-operand instructions. 2-26 MCF5407 User's Manual Execution Timings Table 2-14. One-Operand Instruction Execution Times Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #xxx clr.b <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) -- clr.w <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) -- clr.l <ea> 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) -- ext.w Dx 1(0/0) -- -- -- -- -- -- -- ext.l Dx 1(0/0) -- -- -- -- -- -- -- extb.l Dx 1(0/0) -- -- -- -- -- -- -- neg.l Dx 1(0/0) -- -- -- -- -- -- -- negx.l Dx 1(0/0) -- -- -- -- -- -- -- -- not.l Dx 1(0/0) -- -- -- -- -- -- sats.l Dx 1(0/0) -- -- -- -- -- -- -- scc Dx 1(0/0) -- -- -- -- -- -- -- swap Dx 1(0/0) -- -- -- -- -- -- -- tas <ea> 1(1/1) 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- tst.b <ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) tst.w <ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) tst.l <ea> 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) 2.7.3 Execution Timings--Two-Operand Instructions Table 2-15 shows standard timings for two-operand instructions. Table 2-15. Two-Operand Instruction Execution Times Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> 1(0/0) add.l <ea>,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) add.l Dy,<ea> -- 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- addi.l #imm,Dx 1(0/0) -- -- -- -- -- -- -- addq.l #imm,<ea> 1(0/0) 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- addx.l Dy,Dx 1(0/0) -- -- -- -- -- -- -- and.l <ea>,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) and.l Dy,<ea> -- 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- andi.l #imm,Dx 1(0/0) -- -- -- -- -- -- -- asl.l <ea>,Dx 1(0/0) -- -- -- -- -- -- 1(0/0) asr.l <ea>,Dx 1(0/0) -- -- -- -- -- -- 1(0/0) bchg Dy,<ea> 2(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -- Chapter 2. ColdFire Core 2-27 Execution Timings Table 2-15. Two-Operand Instruction Execution Times (Continued) Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> bchg #imm,<ea> 2(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- -- bclr Dy,<ea> 2(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -- bclr #imm,<ea> 2(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- -- bset Dy,<ea> 2(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -- bset #imm,<ea> 2(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- -- btst Dy,<ea> 2(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) -- btst #imm,<ea> 1(0/0) 2(1/1) 2(1/1) 2(1/1) 2(1/1) -- -- 1(0/0) cmp.b <ea>,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) cmp.w <ea>,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) 1(0/0) cmp.l <ea>,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) cmpi.b #imm,Dx 1(0/0) -- -- -- -- -- -- -- cmpi.w #imm,Dx 1(0/0) -- -- -- -- -- -- -- cmpi.l #imm,Dx 1(0/0) -- -- -- -- -- -- -- divs.w <ea>,Dx 20(0/0) 20(1/0) 20(1/0) 20(1/0) 20(1/0) 21(1/0) 20(1/0) 20(0/0) divu.w <ea>,Dx 20(0/0) 20(1/0) 20(1/0) 20(1/0) 20(1/0) 21(1/0) 20(1/0) 20(0/0) divs.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) -- -- -- divu.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) -- -- -- eor.l Dy,<ea> 1(0/0) 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- eori.l #imm,Dx 1(0/0) -- -- -- -- -- -- -- lea <ea>,Ax -- 1(0/0) -- -- 1(0/0) 2(0/0) 1(0/0) -- lsl.l <ea>,Dx 1(0/0) -- -- -- -- -- -- 1(0/0) lsr.l <ea>,Dx 1(0/0) -- -- -- -- -- -- 1(0/0) mac.w Ry,Rx 1(0/0) -- -- -- -- -- -- -- mac.l Ry,Rx 3(0/0) -- -- -- -- -- -- -- msac.w Ry,Rx 1(0/0) -- -- -- -- -- -- -- msac.l Ry,Rx 3(0/0) -- -- -- -- -- -- -- mac.w Ry,Rx,ea,Rw -- 1(1/0) 1(1/0) 1(1/0) 1(1/0) -- -- -- mac.l Ry,Rx,ea,Rw -- 3(1/0) 3(1/0) 3(1/0) 3(1/0) -- -- -- msac.w Ry,Rx,ea,Rw -- 1(1/0) 1(1/0) 1(1/0) 1(1/0) -- -- -- msac.l Ry,Rx,ea,Rw -- 3(1/0) 3(1/0) 3(1/0) 3(1/0) -- -- -- muls.w <ea>,Dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0) mulu.w <ea>,Dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0) muls.l <ea>,Dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) -- -- -- mulu.l <ea>,Dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) -- -- -- or.l <ea>,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) 2-28 MCF5407 User's Manual Execution Timings Table 2-15. Two-Operand Instruction Execution Times (Continued) Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> or.l Dy,<ea> -- 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- or.l #imm,Dx 1(0/0) -- -- -- -- -- -- -- rems.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) -- -- -- remu.l <ea>,Dx 35(0/0) 35(1/0) 35(1/0) 35(1/0) 35(1/0) -- -- -- sub.l <ea>,Rx 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(0/0) sub.l Dy,<ea> -- 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- subi.l #imm,Dx 1(0/0) -- -- -- -- -- -- -- subq.l #imm,<ea> 1(0/0) 1(1/1) 1(1/1) 1(1/1) 1(1/1) 2(1/1) 1(1/1) -- subx.l Dy,Dx 1(0/0) -- -- -- -- -- -- -- 2.7.4 Miscellaneous Instruction Execution Times Table 2-16 lists timings for miscellaneous instructions. Table 2-16. Miscellaneous Instruction Execution Times Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> -- -- -- -- -- -- -- cpushl (Ax) -- 9(0/1) intouch (Ay) -- 19(1/0) link.w Ay,#imm 2(0/1) -- -- -- -- -- -- move.w CCR,Dx 1(0/0) -- -- -- -- -- -- -- move.w <ea>,CCR 1(0/0) -- -- -- -- -- -- 1(0/0) move.w SR,Dx 1(0/0) -- -- -- -- -- -- -- move.w <ea>,SR 4(0/0) -- -- -- -- -- -- 4(0/0) movec Ry,Rc 20(0/1) -- -- -- -- -- -- -- 1 <ea>,&list -- n(n/0) -- -- n(n/0) -- -- -- movem.l 1 &list,<ea> -- n(0/n) -- -- n(0/n) -- -- -- 6(0/0) -- -- -- -- -- -- -- -- 1(0/1) -- -- 1(0/1) 2(0/1) 1(0/1) -- 1(0/0) -- -- -- -- -- -- -- movem.l nop pea <ea> pulse stop #imm -- -- -- -- -- -- -- 6(0/0)2 trap #imm -- -- -- -- -- -- -- 18(1/2) trapf 1(0/0) -- -- -- -- -- -- -- trapf.w 1(0/0) -- -- -- -- -- -- -- trapf.l 1(0/0) -- -- -- -- -- -- -- Chapter 2. ColdFire Core 2-29 Execution Timings Table 2-16. Miscellaneous Instruction Execution Times (Continued) Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> unlk Ax 1(1/0) -- -- -- -- -- -- -- wddata. {b,w,l} <ea> -- 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) -- wdebug.l <ea> -- 15(2/0) -- -- 15(2/0) -- -- -- 1 n is the number of registers moved by the MOVEM opcode 2 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts. 2.7.5 Branch Instruction Execution Times Table 2-17 shows general branch instruction timing. Table 2-17. Branch Instruction Execution Times Effective Address Opcode <ea> bra bsr jmp <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> -- -- -- -- 1(0/1)1 -- -- -- -- -- -- 6(0/0) 1(0/0)1 -- -- -- -- -- -- 1(0/1)1 -- 5(0/0) -- -- 5(0/0) -- 5(0/1) -- -- 5(0/1) 6(0/1) 1(0/1)1 rte -- -- 15(2/0) -- -- -- -- -- rts -- -- 2(1/0)2 9(1/0)3 8(1/0)4 -- -- -- -- -- jsr <ea> 1 Assumes branch acceleration. If predicted correctly by the hardware return stack. 3 If mispredicted by the hardware return stack. 4 If not predicted by the hardware return stack. 2 Table 2-18 shows timing for Bcc instructions. Table 2-18. Bcc Instruction Execution Times Opcode Branch Cache Correctly Predicts Taken Prediction Table Correctly Predicts Taken Predicted Correctly as Not Taken Predicted Incorrectly bcc 0(0/0) 1(0/0) 1(0/0) 8(0/0) 2-30 MCF5407 User's Manual Exception Processing Overview 2.8 Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance. Differences from previous M68000 Family processors include the following: * * * * A simplified exception vector table Reduced relocation capabilities using the vector base register A single exception stack frame format Use of a single, self-aligning system stack pointer ColdFire processors use an instruction restart exception model but require more software support to recover from certain access errors. See Table 2-19 for details. Exception processing can be defined as the time from the detection of the fault condition until the fetch of the first handler instruction has been initiated. It is comprised of the following four major steps: 1. The processor makes an internal copy of the SR and then enters supervisor mode by setting SR[S] and disabling trace mode by clearing SR[T]. The occurrence of an interrupt exception also forces SR[M] to be cleared and the interrupt priority mask to be set to the level of the current interrupt request. 2. The processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on the exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a peripheral device. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address. 3. The processor saves the current context by creating an exception stack frame on the system stack. ColdFire processors support a single stack pointer in the A7 address register; therefore, there is no notion of separate supervisor and user stack pointers. As a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a simplified fixed-length stack frame for all exceptions. The exception type determines whether the program counter in the exception stack frame defines the address of the faulting instruction (fault) or of the next instruction to be executed (next). 4. The processor acquires the address of the first instruction of the exception handler. The exception vector table is aligned on a 1-Mbyte boundary. This instruction address is obtained by fetching a value from the table at the address defined in the vector base register. The index into the exception table is calculated as 4 x vector_number. When the index value is generated, the vector table contents determine the address of the first instruction of the desired handler. After the fetch of the first opcode of the handler is initiated, exception processing terminates and normal instruction processing continues in the handler. ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address boundary; see Table 2-19. The table contains 256 exception vectors where the first 64 are Chapter 2. ColdFire Core 2-31 Exception Processing Overview defined by Motorola; the remaining 192 are user-defined interrupt vectors. Table 2-19. Exception Vector Assignments Vector Numbers Vector Offset (Hex) Stacked Program Counter 1 0 000 -- Initial stack pointer 1 004 -- Initial program counter 2 008 Fault Access error 3 00C Fault Address error 4 010 Fault Illegal instruction 5 014 Fault Divide by zero 6-7 018-01C -- 8 020 Fault Privilege violation 9 024 Next Trace 1 Assignment Reserved 10 028 Fault Unimplemented line-a opcode 11 02C Fault Unimplemented line-f opcode 12 030 Next Non-PC breakpoint debug interrupt 13 034 Next PC breakpoint debug interrupt 14 038 Fault Format error 15 03C Next Uninitialized interrupt 16-23 040-05C -- Reserved 24 060 Next Spurious interrupt 25-31 064-07C Next Level 1-7 autovectored interrupts 32-47 080-0BC Next Trap #0-15 instructions 48-60 0C0-0F0 -- 61 0F4 Fault 62-63 0F8-0FC -- 64-255 100-3FC Next Reserved Unsupported instruction Reserved User-defined interrupts The term `fault' refers to the PC of the instruction that caused the exception. The term `next' refers to the PC of the instruction that immediately follows the instruction that caused the fault. ColdFire processors inhibit sampling for interrupts during the first instruction of all exception handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register. 2.8.1 Exception Stack Frame Definition The exception stack frame is shown in Figure 2-1. The first longword of the exception stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second longword contains the 32-bit program counter address. 2-32 MCF5407 User's Manual Exception Processing Overview 31 A7 28 Format 27 26 25 FS[3-2] + 0x04 18 Vector[7-0] 17 16 15 0 FS[1-0] Status Register Program Counter [31-0] Figure 2-1. Exception Stack Frame Form The 16-bit format/vector word contains three unique fields: * Format field--This 4-bit field at the top of the system stack is always written with a value of {4,5,6,7} by the processor indicating a 2-longword frame format. See Table 2-20. This field records any longword misalignment of the stack pointer that may have existed when the exception occurred. Table 2-20. Format Field Encoding * Original A7 at Time of Exception, Bits 1-0 A7 at First Instruction of Handler Format Field Bits 31-28 00 Original A[7-8] 0100 01 Original A[7-9] 0101 10 Original A[7-10] 0110 11 Original A[7-11] 0111 Fault status field--The 4-bit field, FS[3-0], at the top of the system stack is defined for access and address errors along with interrupted debug service routines. See Table 2-21. Table 2-21. Fault Status Encodings FS[3-0] 0000 Not an access or address error nor an interrupted debug service routine 0001 Reserved 0010 Interrupt during a debug service routine 0011 Reserved 0100 Error on instruction fetch 0101-011x Reserved 1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read 1101-111x * Definition Reserved Vector number--This 8-bit field, vector[7-0], defines the exception type. It is calculated by the processor for internal faults and is supplied by the peripheral for interrupts. See Table 2-19. Chapter 2. ColdFire Core 2-33 Exception Processing Overview 2.8.2 Processor Exceptions Table 2-22 describes MCF5407 exceptions. Table 2-22. MCF5407 Exceptions Exception Description Access Error Access errors are reported only in conjunction with an attempted store to write-protected memory. Thus, access errors associated with instruction fetch or operand read accesses are not possible. The Version 4 processor, unlike the Version 2 and 3 processors, updates the condition code register if a write-protect error occurs during a CLR or MOV3Q operation to memory. Address Error Caused by an attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target address is set), an attempted use of a word-sized index register (Xi.w) or a scale factor of 8 on an indexed effective addressing mode, or attempted execution of an instruction with a full-format indexed addressing mode. If an address error occurs on a JSR instruction, the Version 4 processor first pushes the return address onto the stack and then calculates the target address. On Version 2 and 3 processors, these functions are reversed. If an address error occurs on an RTS instruction, the Version 4 processor preserves the original return PC and writes the exception stack frame above this value. On Version 2 and 3 processors, the faulting return PC is overwritten by the address error stack frame. Illegal Instruction On Version 2 ColdFire implementations, only some illegal opcodes were decoded and generated an illegal instruction exception. Version 3 and Version 4 processors decode the full 16-bit opcode and generate this exception if execution of an unsupported instruction is attempted. Additionally, attempting to execute an illegal line A or line F opcode generates unique exception types: vectors 10 and 11, respectively. ColdFire processors do not provide illegal instruction detection on extension words of any instruction, including MOVEC. Attempting to execute an instruction with an illegal extension word causes undefined results. Divide by Zero Attempted division by zero causes an exception (vector 5, offset = 0x014) except when the PC points to the faulting instruction (DIVU, DIVS, REMU, REMS). Privilege Violation Caused by attempted execution of a supervisor mode instruction while in user mode. The ColdFire Programmer's Reference Manual lists supervisor- and user-mode instructions. Trace Exception ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this definition is the STOP instruction. If the processor is in trace mode, the instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reflects the just-loaded value. If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets the trace bit in the SR, hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after STOP, and the SR reflects the just-loaded value. Because ColdFire processors do not support hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider a TRAP instruction executing in trace mode. The processor initiates the TRAP exception and passes control to the corresponding handler. If the system requires that a trace exception be processed, the TRAP exception handler must check for this condition (SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception. 2-34 MCF5407 User's Manual Exception Processing Overview Table 2-22. MCF5407 Exceptions (Continued) Exception Description Debug Interrupt Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the processor internally calculates the vector number (12 or 13, depending on the type of breakpoint trigger). Additionally, the M bit and the interrupt priority mask fields of the SR are unaffected by the interrupt. See Section 2.2.2.1, "Status Register (SR)." The debug interrupt exception vector is expanded from Version 3 such that PC breakpoints are distinguishable from other triggers. The two unique entries occur when a PC breakpoint generates the 0x034 vector. In case of a two-level trigger, the last breakpoint event determines the vector. The changes are described in more detail in Chapter 5, "Debug Support." RTE and Format Error Exceptions When an RTE instruction executes, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire processor, any attempted execution of an RTE where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original exception frame and the stacked PC points to RTE.The selection of the format value provides limited debug support for porting code from M68000 applications. On M68000 Family processors, the SR was at the top of the stack. Bit 30 of the longword addressed by the system stack pointer is typically zero; so, attempting an RTE using this old format generates a format error on a ColdFire processor. If the format field defines a valid type, the processor does the following: 1 Reloads the SR operand. 2 Fetches the second longword operand. 3 Adjusts the stack pointer by adding the format value to the auto-incremented address after the first longword fetch. 4 Transfers control to the instruction address defined by the second longword operand in the stack frame. TRAP Executing TRAP always forces an exception and is useful for implementing system calls. The trap instruction may be used to change from user to supervisor mode. Interrupt Exception Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. Autovectoring may optionally be configured through the system interface module (SIM). See Section 9.2.2, "Autovector Register (AVR)." Reset Exception Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception priority; it provides for system initialization and recovery from catastrophic failure. When assertion of RSTI is recognized, current processing is aborted and cannot be recovered. The reset exception places the processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T]. This exception also clears SR[M] and sets the processor's interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to 0x0000_0000. Configuration registers controlling the operation of all processor-local memories are invalidated, disabling the memories. Note: Other implementation-specific supervisor registers are also affected. Refer to each of the modules in this manual for details on these registers. After RSTI is negated, the processor waits 16 cycles before beginning the actual reset exception process. During this time, certain events are sampled, including the assertion of the debug breakpoint signal. If the processor is not halted, it initiates the reset exception by performing two longword read bus cycles. The longword at address 0 is loaded into the stack pointer and the longword at address 4 is loaded into the PC. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction executes, the processor enters the fault-on-fault halted state. Unsupported Instruction Exception If the MCF5407 attempts to execute a valid instruction but the required optional hardware module is not present in the OEP, a non-supported instruction exception is generated (vector 0x61). Control is then passed to an exception handler that can then process the opcode as required by the system. If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to force the processor to exit this halted state. Chapter 2. ColdFire Core 2-35 ColdFire Instruction Set Architecture Enhancements 2.9 ColdFire Instruction Set Architecture Enhancements This section describes the new opcodes implemented as part of the Revision B enhancements to the basic ColdFire ISA. In some cases, the opcodes represent minor enhancements to existing ColdFire functions, while in other cases, the functionality is new and not covered in the existing ISA. 2-36 MCF5407 User's Manual ColdFire Instruction Set Architecture Enhancements Bcc Bcc Branch Conditionally If Condition True Then PC + dn PC Operation: Assembler Syntax: Bcc <label> Attributes: Size = byte, word, long Description: If the condition is true, execution continues at (PC) + displacement. PC holds the address of the instruction word for the Bcc instruction, plus two. The displacement is a two's-complement integer that represents the relative distance in bytes from the current PC to the destination PC. If the 8-bit displacement field is 0, a 16-bit displacement (the word after the instruction) is used. If the 8-bit displacement field is 0xFF, the 32-bit displacement (longword after the instruction) is used. Condition code specifies one of the following tests: Code Condition Code Condition Code Condition Code Condition CC(HI) Carry clear GT Greater than LT Less than VC Overflow clear CS(LO) Carry set HI High MI Minus VS Overflow set EQ Equal LE Less or equal NE Not equal GE Greater or equal LS Low or same PL Plus Condition Codes: Instruction Format: Not affected 15 14 13 12 0 1 1 0 11 10 9 8 7 Condition 6 5 4 3 2 1 0 8-bit displacement 16-bit displacement if 8-bit displacement = 0x00 32-bit displacement if 8-bit displacement = 0xFF Instruction Fields: * Condition field--Binary code for one of the conditions listed in the table. * 8-bit displacement field--Two's complement integer specifying the number of bytes between the branch and the next instruction to be executed if the condition is met. * 16-bit displacement field--Used when the 8-bit displacement contains 0x00. * 32-bit displacement field--Used when the 8-bit displacement contains 0xFF. NOTE: A branch to the next immediate instruction uses 16-bit displacement because the 8-bit displacement field is 0x00. Bcc V2, V3 Core V4 Core Opcode present Yes Yes Operand sizes supported .b, .w .b, .w, .l Chapter 2. ColdFire Core 2-37 ColdFire Instruction Set Architecture Enhancements BRA BRA Branch Always Operation: PC + dn PC Assembler Syntax: BRA <label> Attributes: Size = byte, word, long Description: Program execution continues at location (PC) + displacement. The PC contains the address of the instruction word of the BRA instruction, plus two. The displacement is a two's complement integer that represents the relative distance in bytes from the current PC to the destination PC. If the 8-bit displacement field in the instruction word is 0, a 16-bit displacement (the word immediately following the instruction) is used. If the 8-bit displacement field in the instruction word is all ones (0xFF), the 32-bit displacement (longword immediately following the instruction) is used. Condition codes: Instruction Format: Not affected 15 14 13 12 11 10 9 8 0 1 1 0 0 0 0 0 7 6 5 4 3 2 1 0 8-bit displacement 16-bit displacement if 8-bit displacement = 0x00 32-bit displacement if 8-bit displacement = 0xFF Instruction Fields: * 8-bit displacement field--Two's complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed. * 16-bit displacement field--Used for displacement when the 8-bit displacement contains 0x00. * 32-bit displacement field--Used for displacement when the 8-bit displacement contains 0xFF. NOTE: A branch to the next immediate instruction automatically uses the 16-bit displacement format because the 8-bit displacement field contains 0x00 (zero offset). BRA 2-38 V2, V3 Core V4 Core Opcode present Yes Yes Operand sizes supported .b, .w .b, .w, .l MCF5407 User's Manual ColdFire Instruction Set Architecture Enhancements BSR BSR Branch to Subroutine Operation: SP - 4 SP; PC (SP); PC + dn PC Assembler Syntax: BSR <label> Attributes: Size = byte, word, long Description: Pushes the word address of the instruction immediately following the BSR instruction onto the system stack. The PC contains the address of the instruction word, plus two. Program execution then continues at location (PC) + displacement. The displacement is a two's complement integer that represents the relative distance in bytes from the current PC to the destination PC. If the 8-bit displacement field in the instruction word is 0, a 16-bit displacement (the word immediately following the instruction) is used. If the 8-bit displacement field in the instruction word is all ones (0xFF), the 32-bit displacement (longword immediately following the instruction) is used. Condition Codes: Instruction Format: Not affected 15 14 13 12 11 10 9 8 0 1 1 0 0 0 0 1 7 6 5 4 3 2 1 0 8-bit displacement 16-bit displacement if 8-bit displacement = 0x00 32-bit displacement if 8-bit displacement = 0xFF Instruction Fields: * 8-bit displacement field--Two's complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed. * 16-bit displacement field--Used for displacement when the 8-bit displacement contains 0x00. * 32-bit displacement field--Used for displacement when the 8-bit displacement contains 0xFF. NOTE: A branch to the next immediate instruction automatically uses the 16-bit displacement format because the 8-bit displacement field contains 0x00 (zero offset). BSR V2, V3 Core V4 Core Opcode present Yes Yes Operand sizes supported .b, .w .b, .w, .l Chapter 2. ColdFire Core 2-39 ColdFire Instruction Set Architecture Enhancements CMP CMP Compare Operation: Destination - Source cc Assembler Syntax: CMP <ea>y, Dx Attributes: Size = byte, word, long Description: Subtracts the source operand from the destination operand in the data register and sets condition codes according to the result; the data register is unchanged. The operation size may be a byte, word, or longword. CMPA is used when the destination is an address register; CMPI is used when the source is immediate data. Most assemblers automatically make this distinction. Condition Codes: X -- N Z V C X N Z V C 15 14 13 12 1 0 1 1 Instruction Format: Not affected Set if the result is negative; cleared otherwise Set if the result is zero; cleared otherwise Set if an overflow occurs; cleared otherwise Set if a borrow occurs; cleared otherwise 11 10 9 8 REGISTER 7 6 5 OPMODE 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields: * Register field--specifies the destination register. * Opmode field: * Byte Word Long Operation 000 001 010 Dx - <ea>y Effective address field specifies the source operand; use addressing modes in the following table: Addressing Mode Mode Register Addressing Mode Mode Register reg. number:Ay Dy 000 reg. number:Dy (d8,Ay,Xi) 110 Ay (word/longword operand only) 001 reg. number:Ay (xxx).W 111 000 (Ay) 010 reg. number:Ay (xxx).L 111 001 (Ay) + 011 reg. number:Ay #<data> 111 100 - (Ay) 100 reg. number:Ay (d16,PC) 111 010 (d16,Ay) 101 reg. number:Ay (d8,PC,Xi) 111 011 2-40 CMP V2, V3 Core Opcode present Yes Yes Operand sizes supported .l .b, .w, .l MCF5407 User's Manual V4 Core ColdFire Instruction Set Architecture Enhancements CMPA CMPA Compare Address Operation: Destination - Source cc Assembler Syntax: CMPA <ea>y, Ax Attributes: Size = word, long Description: Operates similarly to CMP, but is used when the destination register is an address register rather than a data register. The operation size can be word or longword. Word-length source operands are sign-extended to 32 bits for comparison. Condition Codes: X -- N Z V C X N Z V C 15 14 13 12 1 0 1 1 Instruction Format: Not affected Set if the result is negative; cleared otherwise Set if the result is zero; cleared otherwise Set if an overflow occurs; cleared otherwise Set if a borrow occurs; cleared otherwise 11 10 9 8 REGISTER 7 6 5 4 OPMODE 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields: * Register field--Specifies the destination register. * Opmode field: * Byte Word Long Operation -- 011 111 Ax - <ea>y Effective address field specifies the source operand; use addressing modes in the following table: Addressing Mode Mode Register Addressing Mode Mode Register reg. number:Ay Dy 000 reg. number:Dy (d8,Ay,Xi) 110 Ay (word/longword operand only) 001 reg. number:Ay (xxx).W 111 000 (Ay) 010 reg. number:Ay (xxx).L 111 001 (Ay) + 011 reg. number:Ay #<data> 111 100 - (Ay) 100 reg. number:Ay (d16,PC) 111 010 (d16,Ay) 101 reg. number:Ay (d8,PC,Xi) 111 011 CMPA V2, V3 Core Opcode present Yes Yes Operand sizes supported .l .w, .l Chapter 2. ColdFire Core V4 Core 2-41 ColdFire Instruction Set Architecture Enhancements CMPI CMPI Compare Immediate Operation: Destination - Immediate Data cc Assembler Syntax: CMPI #<data>, Dx Attributes: Size = byte, word, long Description: Operates similarly to CMP, but is used when the source operand is immediate data. The size of the operation may be specified as byte, word, or longword. The size of the immediate data matches the operation size. Condition Codes: X -- N Instruction Format: Z V C X N Z V C Not affected Set if the result is negative; cleared otherwise Set if the result is zero; cleared otherwise Set if an overflow occurs; cleared otherwise Set if a borrow occurs; cleared otherwise 15 14 13 12 11 10 9 8 0 0 0 0 1 1 0 0 7 6 SIZE 5 4 3 0 0 0 UPPER WORD LOWER WORD Instruction Fields: * Register field--Destination data register. * Size field: Byte Word Long Operation 00 01 10 Dx - #<data> Note that if size = byte, the immediate is contained in bits [7:0] of the single extension word. If size = word, the immediate is contained in bits[15:0] of the single extension word. If size = long, the immediate is contained in the two extension words. 2-42 CMPI V2, V3 Core Opcode present Yes Yes Operand sizes supported .l .b, .w, .l MCF5407 User's Manual V4 Core 2 1 0 REGISTER ColdFire Instruction Set Architecture Enhancements INTOUCH INTOUCH Instruction Fetch Touch Operation: If Supervisor State then Instruction Fetch Touch @ <Ay> else TRAP Assembler Syntax INTOUCH <Ay> Attributes: Unsized Description: Generates an instruction fetch reference at address (Ay). If the referenced address space is a cacheable region, this instruction can be used to prefetch a 16-byte packet into the processor's instruction cache. If the referenced instruction address is a non-cacheable space, the instruction effectively performs no operation. The INTOUCH instruction can be used to prefetch, and with the later setting of CACR[11], lock specific memory lines in the processor's instruction cache. This function may be desirable in systems where deterministic real-time performance is critical. Condition Codes: Instruction Format: Not affected. 15 14 13 12 11 10 9 8 7 6 5 4 3 1 1 1 1 0 1 0 0 0 0 1 0 1 2 1 0 REGISTER Instruction Fields: * Register field--Specifies the destination address register number. INTOUCH V2, V3 Core V4 Core Opcode present No Yes Operand sizes supported -- -- Chapter 2. ColdFire Core 2-43 ColdFire Instruction Set Architecture Enhancements MOVE MOVE Move Data from Source to Destination Operation: Source Destination Assembler Syntax: MOVE <ea>y, <ea>x Attributes: Size = byte, word, long Description: Moves the data at the source to the destination location and sets the condition codes according to the data. The size of the operation may be specified as byte, word, or longword. Condition Codes: X -- N Z Instruction Format: V 0 15 14 0 0 C 0 13 X N Z V C 12 Not affected Set if the result is negative; cleared otherwise Set if the result is zero; cleared otherwise Always cleared Always cleared 11 10 SIZE 9 8 7 6 5 4 DESTINATION REGISTER 3 2 1 0 SOURCE MODE MODE REGISTER Instruction fields: * Size field--Specifies the size of the operand to be moved: 01-- 11-- 10-- * * 2-44 byte operation word operation long operation Destination effective address field--Specifies destination location; the table below lists possible data alterable addressing modes. The restrictions on combinations of source and destination addressing modes are listed in the table at the bottom of the next page. Addressing Mode Mode Register Addressing Mode Mode Register Dx Ax (Ax) (Ax) + - (Ax) (d16,Ax) 000 -- 010 011 100 101 reg. number:Dx -- reg. number:Ax reg. number:Ax reg. number:Ax reg. number:Ax (d8,Ax,Xi) (xxx).W (xxx).L #<data> (d16,PC) (d8,PC,Xi) 110 111 111 -- -- -- reg. number:Ax 000 001 -- -- -- Source effective address field--Specifies source operand; the table below lists possible addressing modes. The ColdFire MOVE instruction has restrictions on combinations of source and destination addressing modes. The table at the end of this instruction description outlines the restrictions. MCF5407 User's Manual ColdFire Instruction Set Architecture Enhancements Addressing Mode Mode Register Addressing Mode Mode Register Dy Ay (Ay) (Ay) + - (Ay) (d16,Ay) 000 001 010 011 100 101 reg. number:Dy reg. number:Ay reg. number:Ay reg. number:Ay reg. number:Ay reg. number:Ay (d8,Ay,Xi) (xxx).W (xxx).L #<data> (d16,PC) (d8,PC,Xi) 110 111 111 111 111 111 reg. number:Ay 000 001 100 010 011 NOTE: Most assemblers use MOVEA when the destination is an address register. Use MOVEQ to move an immediate 8-bit value to a data register. Use MOV3Q to move a 3-bit immediate value to any effective destination address. Not all combinations of source/destination addressing modes are possible. The table below shows the possible combinations. Source Addressing Mode Destination Addressing Mode Dy, Ay, (Ay), (Ay)+,-(Ay) All possible (d16, Ay), (d16, PC) All possible except (d8, Ax, Xi), (xxx).W, (xxx).L (d8, Ay, Xi), (d8, PC, Xi), (xxx).W, (xxx).L, #<xxx> All possible except (d8, Ax, Xi), (xxx).W, (xxx).L Note: The combination of #<xxx>,d16(Ax) addressing modes can be used only on move byte and move word opcodes. Refer to the previous tables for valid source and destination addressing modes. MOVE V2, V3 Core V4 Core Opcode present Yes Yes Operand sizes supported .b, .w, .l except move.x #<data>, d16(Ax) .b, .w, .l including move.{b,w} #<data>, d16(Ax) Chapter 2. ColdFire Core 2-45 ColdFire Instruction Set Architecture Enhancements MOVEA MOVEA Move Address from Source to Destination Operation: Source Destination Assembler Syntax: MOVEA <ea>y, Ax Attributes: Size = word, long Description: Moves the address at the source to the destination location and sets the condition codes according to the data. The size of the operation may be specified as word or longword. Condition Codes: Instruction Format: Not affected 15 14 0 0 13 12 11 10 SIZE 9 8 7 6 5 4 DESTINATION REGISTER 3 2 1 0 SOURCE MODE MODE REGISTER Instruction fields: * Size field--specifies the size of the operand to be moved: 11--word operation 10--longword operation * Destination effective address field--Specifies the destination location; the table below lists possible addressing modes. * Addressing Mode Mode Register Addressing Mode Mode Register Dx Ax (Ax) (Ax) + - (Ax) (d16,Ax) -- 001 -- -- -- -- -- reg. number: Ax -- -- -- -- (d8,Ax,Xi) (xxx).W (xxx).L #<data> (d16,PC) (d8,PC,Xi) -- -- -- -- -- -- -- -- -- -- -- -- Source effective address field--Specifies the source operand; the table below lists possible modes. Addressing Mode Mode Register Addressing Mode Mode Register Dy Ay (Ay) (Ay) + - (Ay) (d16,Ay) 000 001 010 011 100 101 reg. number:Dy reg. number:Ay reg. number:Ay reg. number:Ay reg. number:Ay reg. number:Ay (d8,Ay,Xi) (xxx).W (xxx).L #<data> (d16,PC) (d8,PC,Xi) 110 111 111 111 111 111 reg. number:Ay 000 001 100 010 011 MOVEA V2, V3 Core V4 Core Opcode present Yes Yes Operand sizes supported 2-46 No differences MCF5407 User's Manual ColdFire Instruction Set Architecture Enhancements MOV3Q MOV3Q Move 3-Bit Data Quick Operation: Immediate Data Destination Assembler Syntax MOV3Q #<data>,<ea>x Attributes: Size = long Description: Move the immediate data to the operand at the destination location. The data range is from -1 to 7, excluding 0. The immediate data is zero-filled to a long operand and all 32 bits are transferred to the destination location. Condition Codes: X -- N Z Instruction Format: V 0 C 0 X N Z V C 15 14 13 12 1 0 1 0 Not affected Set if the result is negative; cleared otherwise Set if the result is zero; cleared otherwise Always cleared Always cleared 11 10 DATA 9 8 7 6 1 0 1 5 4 3 MODE 2 1 0 REGISTER Instruction Fields: * Data field--3 bits of data having a range {-1,1-7} where a data value of 0 represents -1. * Effective Address field--Specifies the destination operand; use only data addressing modes listed in the following table: Addressing Mode Mode Register Addressing Mode Mode Register Dx 000 reg. number:Dx (d8,Ax,Xi) 110 reg. number:Ax Ax 001 reg. number:Ax (xxx).W 111 000 (Ax) 010 reg. number:Ax (xxx).L 111 001 (Ax) + 011 reg. number:Ax #<data> -- -- - (Ax) 100 reg. number:Ax (d16,PC) -- -- (d16,Ax) 101 reg. number:Ax (d8,PC,Xi) -- -- MOV3Q V2, V3 Core V4 Core Opcode present No Yes Operand sizes supported -- .l Chapter 2. ColdFire Core 2-47 ColdFire Instruction Set Architecture Enhancements MVS MVS Move with Sign Extend Operation: (Source with sign extension) Destination Assembler Syntax: MVS <ea>y,Dx Attributes: Size = byte, word Description: Sign-extend the source operand and move to the destination register. For the byte operation, bit 7 of the source is copied to bits 31-8 of the destination. For the word operation, bit 15 of the source is copied to bits 31-16 of the destination. Condition Codes: X -- N Z V 0 C 0 X N Z V C 15 14 13 12 0 1 1 1 Instruction Format: Not affected Set if the result is negative; cleared otherwise Set if the result is zero; cleared otherwise Always cleared Always cleared 11 10 9 REGISTER 8 7 6 1 0 SIZ E 5 4 3 2 1 MODE REGISTER Instruction Fields: * Size field--specifies the size of the operation 0 byte operation 1 word operation * Register field--specifies a data register as the destination. * Effective address field--specifies the source operand; use only data addressing modes from the following table: Addressing Mode 2-48 Mode Register Addressing Mode Mode Register Dy 000 reg. number:Dy (d8,Ay,Xi) 110 reg. number:Ay Ay 001 reg. number:Ay (xxx).W 111 000 (Ay) 010 reg. number:Ay (xxx).L 111 001 (Ay) + 011 reg. number:Ay #<data> 111 100 - (Ay) 100 reg. number:Ay (d16,PC) 111 010 (d16,Ay) 101 reg. number:Ay (d8,PC,Xi) 111 011 MVS V2, V3 Core Opcode present No Yes Operand sizes supported -- .b, .w MCF5407 User's Manual 0 EFFECTIVE ADDRESS V4 Core ColdFire Instruction Set Architecture Enhancements MVZ MVZ Move with Zero-Fill Operation: (Source with zero fill) Destination Assembler Syntax MVZ <ea>y,Dx Attributes: Size = byte, word Description--Zero-fill the source operand and move to the destination register. For the byte operation, the source operand is moved to bits 7-0 of the destination and bits 31-8 are filled with zeros. For the word operation, the source operand is moved to bits 15-0 of the destination and bits 31-16 are filled with zeros. Condition Codes: X -- N 0 Instruction Format: Z V 0 C 0 X N Z V C 15 14 13 12 0 1 1 1 Not affected Always cleared Set if the result is zero; cleared otherwise Always cleared Always cleared 11 10 9 REGISTER 8 7 6 1 1 SIZ E 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields: * Size field--Specifies the size of the operation 0 byte operation 1 word operation * Register field--Specifies a data register as the destination. * Effective address field--Specifies the source operand; use the following data addressing modes: Addressing Mode Mode Register Addressing Mode Mode Register Dy 000 reg. number:Dy (d8,Ay,Xi) 110 reg. number:Ay Ay 001 reg. number:Ay (xxx).W 111 000 (Ay) 010 reg. number:Ay (xxx).L 111 001 (Ay) + 011 reg. number:Ay #<data> 111 100 - (Ay) 100 reg. number:Ay (d16,PC) 111 010 (d16,Ay) 101 reg. number:Ay (d8,PC,Xi) 111 011 MVZ V2, V3 Core Opcode present No Yes Operand sizes supported -- .b, .w Chapter 2. ColdFire Core V4 Core 2-49 ColdFire Instruction Set Architecture Enhancements SATS SATS Signed Saturate Operation: If CCR.V == 1, then if Dx[31] == 0, then Dx[31:0] = 0x80000000 else Dx[31:0] = 0x7FFFFFFF else Dx[31:0] is unchanged Assembler Syntax: SATS Dx Attributes: Size = long Description: Update the destination register only if the overflow bit of the CCR is set. If the operand is negative, then set the result to greatest positive number, otherwise set the result to the largest negative value. The condition codes are set according to the result. Condition Codes: X -- N Instruction Format: Z V 0 C 0 X N Z V C Not affected Set if the result is negative; cleared otherwise Set if the result is zero; cleared otherwise Always cleared Always cleared 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 1 1 0 0 1 0 0 0 0 Instruction Fields: * Register field--Specifies the destination data register. 2-50 SATS V2, V3 Core V4 Core Opcode present No Yes Operand sizes supported -- .l MCF5407 User's Manual 2 1 0 REGISTER ColdFire Instruction Set Architecture Enhancements TAS TAS Test and Set an Operand Operation: Destination Tested CCR; 1 bit 7 of Destination Assembler Syntax: TAS <ea>x Attributes: Size = byte Description: Tests and sets the byte operand addressed by the effective address field. The instruction tests the current value of the operand and sets the N and Z condition code bits appropriately. TAS also sets the high-order bit of the operand. The operand uses a read-modify-write memory cycle that completes the operation without interruption. This instruction supports use of a flag or semaphore to coordinate several processors. Condition Codes: X -- N Z Instruction Format: V 0 C 0 X N Z V C Not affected Set if the msb of the operand is currently set; cleared otherwise Set if the operand was zero; cleared otherwise Always cleared Always cleared 15 14 13 12 11 10 9 8 7 6 0 1 0 0 1 0 1 0 1 1 5 4 3 2 1 0 EFFECTIVE ADDRESS MODE REGISTER Instruction Fields: * Effective address field--specifies the destination location; the possible data alterable addressing modes are listed in the table below. Addressing Mode Mode Register Addressing Mode Mode Register Dx Ax (Ax) (Ax) + - (Ax) (d16,Ax) -- -- 010 011 100 101 -- -- reg. number:Ax reg. number:Ax reg. number:Ax reg. number:Ax (d8,Ax,Xi) (xxx).W (xxx).L #<data> (d16,PC) (d8,PC,Xi) 110 111 111 -- -- -- reg. number:Ax 000 001 -- -- -- TAS V2, V3 Core V4 Core Opcode present No Yes Operand sizes supported -- .b Chapter 2. ColdFire Core 2-51 ColdFire Instruction Set Architecture Enhancements 2-52 MCF5407 User's Manual Chapter 3 Hardware Multiply/Accumulate (MAC) Unit This chapter describes the MCF5407 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). 3.1 Overview The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family. The MAC unit provides signal processing capabilities for the MCF5407 in a variety of applications including digital audio and servo control. Integrated as an execution unit in the processor's OEP, the MAC unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit input operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed, fixed-point fractional input operands. The MAC unit provides functionality in three related areas: * * * Signed and unsigned integer multiplies Multiply-accumulate operations supporting signed, unsigned, and signed fractional operands Miscellaneous register operations Each of the three areas of support is addressed in detail in the succeeding sections. Logic that supports this functionality is contained in a MAC module, as shown in Figure 3-1. The MAC unit is tightly coupled to the OEP and features a three-stage execution pipeline. To minimize silicon costs, the ColdFire MAC is optimized for 16 x 16 multiply instructions. The OEP can issue a 16 x 16 multiply with a 32-bit accumulation and fetch a 32-bit operand in the same cycle. A 32 x 32 multiply with a 32-bit accumulation takes three cycles before the next instruction can be issued. Figure 3-1 shows the basic functionality of the ColdFire MAC. A full set of instructions is provided for signed and unsigned integers plus signed, fixed-point, fractional input operands. Chapter 3. Hardware Multiply/Accumulate (MAC) Unit 3-1 Overview Operand Y Operand X X Shift 0,1,-1 +/- Accumulator Figure 3-1. ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints. For example, small digital filters can tolerate some variance in the execution time of the algorithm; larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements exceeding the scope of any processor architecture and requiring a fully developed DSP implementation. The M68000 architecture was not designed for high-speed signal processing, and a large DSP engine would be excessive in an embedded environment. In striking a middle ground between speed, size, and functionality, the ColdFire MAC unit is optimized for a small set of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for single-cycle, 16 x 16 multiplies producing a 32-bit result, with a possible accumulation cycle following. This is common in a large portion of signal processing applications. In addition, the ColdFire core architecture has been modified to allow for an operand fetch in parallel with a multiply, increasing overall performance for certain DSP operations. 3.1.0.1 MAC Programming Model Figure 3-2 shows the registers in the MAC portion of the user programming model. 31 0 MACSR ACC MASK MAC status register MAC accumulator MAC mask register Figure 3-2. MAC Programming Model 3-2 MCF5407 User's Manual Overview These registers are described as follows: * * * Accumulator (ACC)--This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. Mask register (MASK)--This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory. MAC status register (MACSR)--This 8-bit register defines configuration of the MAC unit and contains indicator flags affected by MAC instructions. Unless noted otherwise, the setting of MACSR indicator flags is based on the final result, that is, the result of the final operation involving the product and accumulator. 3.1.0.2 General Operation The MAC unit supports the ColdFire integer multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of this number to or from the value contained in the accumulator. The product may be optionally shifted left or right one bit before the addition or subtraction takes place. Hardware support for saturation arithmetic may be enabled to minimize software overhead when dealing with potential overflow conditions using signed or unsigned operands. These MAC operations treat the operands as one of the following formats: * * * Signed integers Unsigned integers Signed, fixed-point, fractional numbers To maintain compactness, the MAC module is optimized for 16-bit multiplications. Two 16-bit operands produce a 32-bit product. Longword operations are performed by reusing the 16-bit multiplier array at the expense of a small amount of extra control logic. Again, the product of two 32-bit operands is a 32-bit result. For longword integer operations, only the least significant 32 bits of the product are calculated. For fractional operations, the entire 63-bit product is calculated and then either truncated or rounded to a 32-bit result using the round-to-nearest (even) method. Because the multiplier array is implemented in a 3-stage pipeline, MAC instructions can have an effective issue rate of one clock for word operations, three for longword integer operations, and four for 32-bit fractional operations. Arithmetic operations use register-based input operands, and summed values are stored internally in the accumulator. Thus, an additional MOVE instruction is necessary to store data in a general-purpose register. MAC instructions can choose the upper or lower word of a register as the input, which helps filtering operations in which one data register is loaded with input data and another is loaded with coefficient data. Two 16-bit MAC operations can be performed without fetching additional operands between instructions by alternating the word choice during the calculations. Chapter 3. Hardware Multiply/Accumulate (MAC) Unit 3-3 Overview The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efficiently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for filling registers quickly with input data, filter coefficients, and output data. Loading an operand from memory into a register during a MAC operation makes some DSP operations, especially filtering and convolution, more manageable. The MACSR has a 4-bit operational mode field and three condition flags. The operational mode bits control the overflow/saturation mode, whether operands are signed or unsigned, whether operands are treated as integers or fractions, and how rounding is performed. Negative, zero and overflow flags are also provided. The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask register (MASK), and MACSR, are described in Section 3.1.0.1, "MAC Programming Model." 3.1.0.3 MAC Instruction Set Summary The MAC unit supports the integer multiply operations defined by the baseline ColdFire architecture, as well as the new multiply-accumulate instructions. Table 3-1 summarizes the MAC unit instruction set. Table 3-1. MAC Instruction Summary Instruction Mnemonic Description Multiply Signed MULS <ea>y,Dx Multiplies two signed operands yielding a signed result Multiply Unsigned MULU <ea>y,Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate MAC Ry,RxSF MSAC Ry,RxSF Multiplies two operands, then adds or subtracts the product to/from the accumulator Multiply Accumulate with Load MAC Ry,RxSF,Rw MSAC Ry,RxSF,Rw Multiplies two operands, then adds or subtracts the product to/from the accumulator while loading a register with the memory operand Load Accumulator MOV.L {Ry,#imm},ACC Loads the accumulator with a 32-bit operand Store Accumulator MOV.L ACC,Rx Writes the contents of the accumulator to a register Load MACSR MOV.L {Ry,#imm},MACSR Writes a value to the MACSR Store MACSR MOV.L MACSR,Rx Store MACSR to CCR MOV.L MACSR,CCR Write the contents of MACSR to the processor's CCR register Load MASK MOV.L {Ry,#imm},MASK Writes a value to MASK Store MASK MOV.L MASK,Rx Writes the contents of MASK to a register Write the contents of MACSR to a register 3.1.0.4 Data Representation The MAC unit supports three basic operand types: * 3-4 Two's complement signed integer: In this format, an N-bit operand represents a number within the range -2(N-1) < operand < 2(N-1) - 1. The binary point is to the right of the least significant bit. MCF5407 User's Manual MAC Instruction Execution Timings * * Two's complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 < operand < 2N - 1. The binary point is to the right of the least significant bit. Two's complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number, aN-1aN-2aN-3... a2a1a0, its value is given by the following formula: N-2 + 2 (i + 1 - N) ai i=0 This format can represent numbers in the range -1 < operand < 1 - 2(N-1). For words and longwords, the greatest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x0x8000_0000, respectively. The most positive word is 0x7FFF or (1 - 2-15); the most positive longword is 0x7FFF_FFFF or (1 - 2-31). 3.2 MAC Instruction Execution Timings Table 3-2 shows standard timings for two-operand MAC instructions. Table 3-2. Two-Operand MAC Instruction Execution Times Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> mac.w Ry,Rx 1(0/0) -- -- -- -- -- -- -- mac.l Ry,Rx 3(0/0) -- -- -- -- -- -- -- msac.w Ry,Rx 1(0/0) -- -- -- -- -- -- -- msac.l Ry,Rx 3(0/0) -- -- -- -- -- -- -- mac.w Ry,Rx,ea,Rw -- 1(1/0) 1(1/0) 1(1/0) 1(1/0) -- -- -- mac.l Ry,Rx,ea,Rw -- 3(1/0) 3(1/0) 3(1/0) 3(1/0) -- -- -- msac.w Ry,Rx,ea,Rw -- 1(1/0) 1(1/0) 1(1/0) 1(1/0) -- -- -- msac.l Ry,Rx,ea,Rw -- 3(1/0) 3(1/0) 3(1/0) 3(1/0) -- -- -- muls.w <ea>,Dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0) mulu.w <ea>,Dx 3(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(0/0) muls.l <ea>,Dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) -- -- -- mulu.l <ea>,Dx 5(0/0) 5(1/0) 5(1/0) 5(1/0) 5(1/0) -- -- -- Table 3-3 shows standard timings for MAC move instructions. Chapter 3. Hardware Multiply/Accumulate (MAC) Unit 3-5 MAC Instruction Execution Timings Table 3-3. MAC Move Instruction Execution Times Effective Address Opcode <ea> Rn (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> move.l <ea>,ACC 1(0/0) -- -- -- -- -- -- 1(0/0) move.l <ea>,MACSR 6(0/0) -- -- -- -- -- -- 6(0/0) move.l <ea>,MASK 5(0/0) -- -- -- -- -- -- 5(0/0) move.l ACC,Rx 1(0/0) -- -- -- -- -- -- -- move.l MACSR,CCR 1(0/0) -- -- -- -- -- -- -- move.l MACSR,Rx 1(0/0) -- -- -- -- -- -- -- move.l MASK,Rx 1(0/0) -- -- -- -- -- -- -- 3-6 MCF5407 User's Manual Chapter 4 Local Memory This chapter describes the MCF5407 implementation of the ColdFire Version 4 local memory specification. It consists of two major sections. * * Section 4.2, "SRAM Overview," describes the MCF5407 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM. Section 4.7, "Cache Overview," describes the MCF5407 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interfaces with other memory structures. 4.1 Interactions between Local Memory Modules Depending on configuration information, instruction fetches and data read accesses may be sent simultaneously to the RAM and cache controllers. This approach is required because all three controllers are memory-mapped devices and the hit/miss determination is made concurrently with the read data access. Power dissipation can be minimized by configuring the RAMBARs to mask unused address spaces whenever possible. If the access address is mapped into the region defined by the RAM (and this region is not masked), the RAM provides the data back to the processor, and the cache data is discarded. Accesses from the RAM module are never cached. The complete definition of the processor's local bus priority scheme for read references is as follows: ) if (RAM "hits" RAM supplies data to the processor else if (data cache "hits") data cache supplies data to the processor else system memory reference to access data For data write references, the memory mapping into the local memories is resolved before the appropriate destination memory is accessed. Accordingly, only the targeted local memory is accessed for data write transfers. 4.2 SRAM Overview The two 2-Kbyte on-chip SRAM modules provide pipelined, single-cycle access to memory mapped to these modules. Memory can be independently mapped to any Chapter 4. Local Memory 4-1 SRAM Operation 0-modulo-2K location in the 4-Gbyte address space and configured to respond to either instruction or data accesses. Time-critical functions can be mapped into instruction memory and the system stack. Other heavily-referenced data can be mapped into data memory. The following summarizes features of the MCF5407 SRAM implementation: * * * * * * Two 2-Kbyte SRAMs, organized as 512 x 32 bits Single-cycle throughput. When the pipeline is full, one access can occur per clock cycle. Physical location on the processor's high-speed local bus with a user-programmed connection to the internal instruction or data bus Memory location programmable on any 0-modulo-2K address boundary Byte, word, and longword address capabilities The RAM base address registers (RAMBAR0 and RAMBAR1) define the logical base address, attributes, and access types for the two SRAM modules. 4.3 SRAM Operation Each SRAM module provides a general-purpose memory block that the ColdFire processor can access with single-cycle throughput. The location of the memory block can be specified to any word-aligned address in the 4-Gbyte address space by RAMBARn[BA], described in Section 4.4.1, "SRAM Base Address Registers (RAMBAR0/RAMBAR1)." The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module connects physically to the processor's high-speed local bus, it can service processor-initiated accesses or memory-referencing debug module commands. The Version 4 ColdFire processor core implements a Harvard memory architecture. Each SRAM module may be logically connected to either the processor's internal instruction or data bus. This logical connection is controlled by a configuration bit in the RAM base address registers (RAMBAR0 and RAMBAR1). If an instruction fetch is mapped into the region defined by the SRAM, the SRAM sources the data to the processor and any cache data is discarded. Likewise, if a data access is mapped into the region defined by the SRAM, the SRAM services the access and the cache is not affected. Accesses from SRAM modules are never cached, and debug-initiated references are treated as data accesses. Note also that the SRAMs cannot be accessed by the on-chip DMAs. The on-chip system configuration allows concurrent core and DMA execution, where the core can reference code or data from the internal SRAMs or caches while performing a DMA transfer. 4-2 MCF5407 User's Manual SRAM Programming Model Accesses are attempted in the following order: 1. SRAM 2. Cache (if space is defined as cacheable) 3. External access 4.4 SRAM Programming Model The SRAM programming model consists of RAMBAR0 and RAMBAR1. 4.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1) The SRAM modules are configured through the RAMBARs, shown in Figure 4-1. * * * * Each RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only access to this register from the processor. Each RAMBAR can be read or written from the debug module in a similar manner. All undefined RAMBAR bits are reserved. These bits are ignored during writes to the RAMBAR and return zeros when read from the debug module. The valid bits, RAMBARn[V], are cleared at reset, disabling the SRAM modules. All other bits are unaffected. 31 Field 11 BA 10 9 -- Reset 8 WP 7 6 5 4 3 2 1 0 D/I -- C/I SC SD UC UD V -- R/W 0 W for CPU; R/W for debug Address CPU space + 0xC04 (RAMBAR0), CPU space + 0xC05 (RAMBAR1) Figure 4-1. SRAM Base Address Registers (RAMBARn) RAMBARn fields are described in detail in Table 4-1. Table 4-1. RAMBARn Field Description Bits Name Description 31-11 BA Base address. Defines the SRAM module's word-aligned base address. Each SRAM module occupies a 2-Kbyte space defined by the contents of BA. SRAM may reside on any 2-Kbyte boundary in the 4-Gbyte address space. 10-9 -- Reserved, should be cleared. 8 WP Write protect. Controls read/write properties of the SRAM. 0 Allows read and write accesses to the SRAM module 1 Allows only read accesses to the SRAM module. Any attempted write reference generates an access error exception to the ColdFire processor core. 7 D/I Data/instruction bus. Indicates whether SRAM is connected to the internal data or instruction bus. 0 Data bus 1 Instruction bus Chapter 4. Local Memory 4-3 SRAM Initialization Table 4-1. RAMBARn Field Description (Continued) Bits Name Description 6 -- Reserved, should be cleared. 5-1 C/I, SC, SD, UC, UD Address space masks (ASn). These fields allow certain types of accesses to be masked, or inhibited from accessing the SRAM module. These bits are useful for power management as described in Section 4.6, "Power Management." In particular, C/I is typically set. The address space mask bits are follows: C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0. SC = Supervisor code address space mask SD = Supervisor data address space mask UC = User code address space mask UD = User data address space mask For each ASn bit: 0 An access to the SRAM module can occur for this address space 1 Disable this address space from the SRAM module. If a reference using this address space is made, it is inhibited from accessing the SRAM module and is processed like any other non-SRAM reference. 0 V Valid. Enables/disables the SRAM module. V is cleared at reset. 0 RAMBAR contents are not valid. 1 RAMBAR contents are valid. The mapping of a given access into the RAM uses the following algorithm to determine if the access hits in the memory: if (RAMBAR[0] = 1) if (((access = instructionFetch) & (RAMBAR[7] = 1)) | ((access = dataReference) & (RAMBAR[7] = 0))) if (requested address[31:10] = RAMBAR[31:10]) if (requested address[31:n] = RAMBAR[31:n] if (ASn of the requested type = 0) Access is mapped to the RAM module if (access = read) Read the RAM and return the data if (access = write) if (RAMBAR[8] = 0) Write the data into the RAM else Signal a write-protect access error ASn refers to the five address space mask bits: C/I, SC, SD, UC, and UD. 4.5 SRAM Initialization After a hardware reset, the contents of each SRAM module are undefined. The valid bits, RAMBARn[V], are cleared, disabling the SRAM modules. If the SRAM requires initialization with instructions or data, the following steps should be performed: 1. Load RAMBARn with bit 7 = 0, mapping the SRAM module to the desired location. Clearing RAMBARn[7] logically connects the SRAM module to the processor's data bus. 4-4 MCF5407 User's Manual SRAM Initialization 2. Read the source data and write it to the SRAM. Various instructions support this function, including memory-to-memory move instructions and the move multiple instruction (MOVEM). MOVEM is optimized to generate line-sized burst fetches on line-aligned addresses, so it generally provides maximum performance. 3. After the data is loaded into the SRAM, it may be appropriate to revise the RAMBAR attribute bits, including the write-protect and address space mask fields. If the SRAM contains instructions, RAMBAR[D/I] must be set to logically connect the memory to the processor's internal instruction bus. Remember that the SRAM cannot be accessed by the on-chip DMAs. The on-chip system configuration allows concurrent core and DMA execution where the core can execute code out of internal SRAM or cache during DMA access. The ColdFire processor or an external emulator using the debug module can perform these initialization functions. 4.5.1 SRAM Initialization Code The code segment below initializes the SRAM using RAMBAR0. The code sets the base address of the SRAM at 0x2000_0000 and then initializes the RAM to zeros. RAMBASE RAMVALID move.l movec.l EQU 0x20000000 EQU 0x00000035 #RAMBASE+RAMVALID,D0 D0, RAMBAR0 ;set this variable to 0x20000000 ;load RAMBASE + valid bit into D0 ;load RAMBAR0 and enable SRAM The following loop initializes the entire SRAM to zero: lea.l move.l RAMBASE,A0 #512,D0 ;load pointer to SRAM ;load loop counter into D0 (A0)+ #1,D0 SRAM_INIT_LOOP ;clear 4 bytes of SRAM ;decrement loop counter ;exit if done; else continue looping SRAM_INIT_LOOP: clr.l subq.l bne.b The following function copies the number of bytesToMove from the source (*src) to the processor's local RAM at an offset relative to the SRAM base address defined by destinationOffset. The bytesToMove must be a multiple of 16. For best performance, source and destination SRAM addresses should be line-aligned (0-modulo-16). ; copyToCpuRam (*src, destinationOffset, bytesToMove) RAMBASE RAMFLAGS lea.l movem.l EQU EQU 0x20000000 0x00000035 -12(a7),a7 #0x1c,(a7) ;SRAM base address ;RAMBAR valid + mask bits ;allocate temporary space ;store D2/D3/D4 registers ; stack arguments and locations Chapter 4. Local Memory 4-5 Power Management ; ; ; ; ; ; ; +0 +4 +8 +12 +16 +20 +24 loop: saved d2 saved d3 saved d4 returnPc pointer to source operand destinationOffset bytesToMove move.l movec.l RAMBASE+RAMFLAGS,a0 a0,rambar0 ;define RAMBAR0 contents ;load it move.l 16(a7),a0 ;load argument defining *src lea.l add.l RAMBASE,a1 20(a7),a1 ;memory pointer to RAM base ;include destinationOffset move.l asr.l 24(a7),d4 #4,d4 ;load byte count ;divide by 16 to convert to loop count .align movem.l movem.l lea.l lea.l subq.l bne.b 4 (a0),#0xf #0xf,(a1) 16(a0),a0 16(a1),a1 #1,d4 loop ;force loop on 0-mod-4 address ;read 16 bytes from source ;store into RAM destination ;increment source pointer ;increment destination pointer ;decrement loop counter ;if done, then exit, else continue movem.l lea.l rts (a7),#0x1c 12(a7),a7 ;restore d2/d3/d4 registers ;deallocate temporary space 4.6 Power Management Because processor memory references may be simultaneously sent to an SRAM module and cache, power can be minimized by configuring RAMBAR address space masks as precisely as possible. For example, if an SRAM is mapped to the internal instruction bus and contains instruction data, setting the ASn mask bits associated with operand references can decrease power dissipation. Similarly, if the SRAM contains data, setting ASn bits associated with instruction fetches minimizes power. Table 4-2 shows typical RAMBAR configurations. . Table 4-2. Examples of Typical RAMBAR Settings Data Contained in SRAM RAMBAR[5-0] Code only 0x2B Data only 0x35 Both code and data 0x21 4.7 Cache Overview This section describes the MCF5407 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. 4-6 MCF5407 User's Manual Cache Overview The MCF5407 implements a special branch instruction cache for accelerating branches, enabled by a bit in the cache access control register (CACR[BEC]). The branch cache is described in Section 2.1.2.1.1, "Branch Acceleration." The MCF5407 processor's Harvard memory structure includes an 8-Kbyte data cache and a 16-Kbyte instruction cache. Both are nonblocking and 4-way set-associative with a 16-byte line. The cache improves system performance by providing single-cycle access to the instruction and data pipelines. This decouples processor performance from system memory performance, increasing bus availability for on-chip DMA or external devices. Figure 4-2 shows the organization and integration of the data cache. Cache Control External Bus Control Control Logic Control Data Array ColdFire Processor Core System Integration Module (SIM) Directory Array Data Address Address/ Data Data Data Path Address Address Path Figure 4-2. Data Cache Organization Both caches implement line-fill buffers to optimize line-sized burst accesses. The data cache supports operation of copyback, write-through, or cache-inhibited modes. A four-entry, 32-bit buffer supports cache line-push operations, and can be configured to defer write buffering in write-through or cache-inhibited modes. The cache lock feature can be used to guarantee deterministic response for critical code or data areas. A nonblocking cache services read hits or write hits from the processor while a fill (caused by a cache allocation) is in progress. As Figure 4-2 shows, accesses use a single bus connected to the cache. All addresses from the processor to the cache are physical addresses. A cache hit occurs when an address matches a cache entry. For a read, the cache supplies data to the processor. For a write, which is permitted only to the data cache, the processor updates the cache. If an access does not match a cache entry (misses the cache) or if a write access must be written through to memory, the cache performs a bus cycle on the internal bus and correspondingly on the external bus by way of the system integration module (SIM). The SRAM module does not implement bus snooping; cache coherency with other possible bus masters must be maintained in software. Chapter 4. Local Memory 4-7 Cache Organization 4.8 Cache Organization A four-way set associative cache is organized as four ways (levels). There are 128 sets in the 8-Kbyte data cache with each line containing 16 bytes (4 longwords). The 16-Kbyte instruction cache has 256 sets. Entire cache lines are loaded from memory by burst-mode accesses that cache 4 longwords of data or instructions. All 4 longwords must be loaded for the cache line to be valid. Figure 4-3 shows data cache organization as well as terminology used. Way 0 Way 1 Way 2 Way 3 * * * * * * Line * * * * * * Set 0 Set 1 Set 126 Set 127 Cache Line Format TAG V M Longword 0 Longword 1 Longword 2 Longword 3 Where: TAG--21-bit address tag V--Valid bit for line M--Modified bit for line (data cache only) Figure 4-3. Data Cache Organization and Line Format A set is a group of four lines (one from each level, or way), corresponding to the same index into the cache array. 4.8.1 Cache Line States: Invalid, Valid-Unmodified, and Valid-Modified As shown in Table 4-3, a data cache line can be invalid, valid-unmodified (often called exclusive), or valid-modified. An instruction cache line can be valid or invalid. Table 4-3. Valid and Modified Bit Settings V M Description 0 x Invalid. Invalid lines are ignored during lookups. 1 0 Valid, unmodified. Cache line has valid data that matches system memory. 1 1 Valid, modified. Cache line contains most recent data, data at system memory location is stale. A valid line can be explicitly invalidated by executing a CPUSHL instruction. 4-8 MCF5407 User's Manual Cache Organization 4.8.2 The Cache at Start-Up As Figure 4-4 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines even though the cache may not contain the appropriate data for start up. Because reset and power-up do not invalidate cache lines automatically, the cache should be cleared explicitly by setting CACR[DCINVA,ICINVA] before the cache is enabled (B). After the entire cache is flushed, cacheable entries are loaded first in way 0. If way 0 is occupied, the cacheable entry is loaded into the same set in way 1, as shown in Figure 4-4 (D). This process is described in detail in Section 4.9, "Cache Operation." Chapter 4. Local Memory 4-9 Cache Organization Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A:Cache population at start-up B:Cache after invalidation, C:Cache after loads in before it is enabled Way 0 D:First load in Way 1 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 At reset, cache contents are indeterminate; V and M may be set. The cache should be cleared explicitly by setting CACR[DCINVA] before the cache is enabled. Setting CACR[DCINVA] invalidates the entire cache. Initial cacheable accesses to memory-fill positions in way 0. A line is loaded in way 1 only if that set is full in way 0. Set 0 Set 127 Figure 4-4. Data Cache--A: at Reset, B: after Invalidation, C and D: Loading Pattern 4-10 MCF5407 User's Manual Cache Operation 4.9 Cache Operation Figure 4-5 shows the general flow of a caching operation using the 8-Kbyte data cache as an example. The discussion in this chapter assumes a data cache. Instruction cache operations are similar except that there is no support for writing to the cache; therefore such notions of modified cache lines and write allocation do not apply. Address 31 11 10 Tag Data/Tag Reference 4 3 0 Way 3 Way 2 Way 1 Way 0 Index Set Select A[10:4] Set 0 TAG Set 1 * * * * * * Set 127 TAG STATUS LW0 LW1 LW2 LW3 * * * * * * * * * * * * * * * STATUS LW0 LW1 LW2 LW3 Data Address A[31:11] MUX 3 2 1 Comparator 0 Line Select Hit 3 Hit 2 Hit 1 Hit 0 Logical OR Hit Figure 4-5. Data Caching Operation The following steps determine if a data cache line is allocated for a given address: 1. The cache set index, A[10:4], selects one cache set. 2. A[31:11] and the cache set index are used as a tag reference or are used to update the cache line tag field. Note that A[31:11] can specify 21 possible addresses that can be mapped to one of the four ways. 3. The four tags from the selected cache set are compared with the tag reference. A cache hit occurs if a tag matches the tag reference and the V bit is set, indicating that the cache line contains valid data. If a cacheable write access hits in a valid cache line, the write can occur to the cache line without having to load it from memory. If the memory space is copyback, the updated cache line is marked modified (M = 1), because the new data has made the data in memory out of date. If the memory location is write-through, the write is passed on to system memory and the M bit is never used. Note that the tag does not have TT or TM bits. Chapter 4. Local Memory 4-11 Cache Operation To allocate a cache entry, the cache set index selects one of the cache's 128 sets. The cache control logic looks for an invalid cache line to use for the new entry. If none is available, the cache controller uses a pseudo-round-robin replacement algorithm to choose the line to be deallocated and replaced. First the cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to the next way. Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking. If CACR[DHLCK,IHLCK] = 1, the replacement pointer is restricted to way 2 or 3. As part of deallocation, a valid, unmodified cache line is invalidated. It is consistent with system memory, so memory does not need to be updated. To deallocate a modified cache line, data is placed in a push buffer (for an external cache line push) before being invalidated. After invalidation, the new entry can replace it. The old cache line may be written after the new line is read. When a cache line is selected to host a new cache entry, the following three things happen: 1. The new address tag bits A[31:11] are written to the tag. 2. The cache line is updated with the new memory data. 3. The cache line status changes to a valid state (V = 1). Read cycles that miss in the cache allocate normally as previously described. Write cycles that miss in the cache do not allocate on a cacheable write-through region, but do allocate for addresses in a cacheable copyback region. A copyback byte, word, longword, or line write miss causes the following: 1. 2. 3. 4. The cache initiates a line fill or flush. Space is allocated for a new line. V and M are both set to indicate valid and modified. Data is written in the allocated space. No write to memory occurs. Note the following: * * * * 4-12 Read hits cannot change the status bits and no deallocation or replacement occurs; the data or instructions are read from the cache. If the cache hits on a write access, data is written to the appropriate portion of the accessed cache line. Write hits in cacheable, write-through regions generate an external write cycle and the cache line is marked valid, but is never marked modified. Write hits in cacheable copyback regions do not perform an external write cycle; the cache line is marked valid and modified (V = 1 and M = 1). Misaligned accesses are broken into at least two cache accesses. Validity is provided only on a line basis. Unless a whole line is loaded on a cache miss, the cache controller does not validate data in the cache line. MCF5407 User's Manual Cache Operation Write accesses designated as cache-inhibited by the CACR or ACR bypass the cache and perform a corresponding external write. Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to this normal operation occurs when all of the following conditions are true during a cache-inhibited read: * * * The cache-inhibited fill buffer bit, CACR[DNFB], is set. The access is an instruction read. The access is normal (that is, transfer type (TT) equals 0). In this case, an entire line is fetched and stored in the fill buffer. It remains valid there, and the cache can service additional read accesses from this buffer until either another fill or a cache-invalidate-all operation occurs. Valid cache entries that match during cache-inhibited address accesses are neither pushed nor invalidated. Such a scenario suggests that the associated cache mode for this address space was changed. To avoid this, it is generally recommended to use the CPUSHL instruction to push or invalidate the cache entry or set CACR[DCINVA] to invalidate the data cache before switching cache modes. 4.9.1 Caching Modes For every memory reference generated by the processor or debug module, a set of effective attributes is determined based on the address and the ACRs. Caching modes determine how the cache handles an access. A data access can be cacheable in either write-through or copyback mode; it can be cache-inhibited in precise or imprecise modes. For normal accesses, the ACRn[CM] bit corresponding to the address of the access specifies the caching modes. If an address does not match an ACR, the default caching mode is defined by CACR[DDCM,IDCM]. The specific algorithm is as follows: if (address == ACR0-address including mask) effective attributes = ACR0 attributes else if (address == ACR1-address including mask) effective attributes = ACR1 attributes else effective attributes = CACR default attributes Addresses matching an ACR can also be write-protected using ACR[W]. Addresses that do not match either ACR can be write-protected using CACR[DW]. Reset disables the cache and clears all CACR bits. As shown in Figure 4-4, reset does not automatically invalidate cache entries; they must be invalidated through software. The ACRs allow the defaults selected in the CACR to be overridden. In addition, some instructions (for example, CPUSHL) and processor core operations perform accesses that have an implicit caching mode associated with them. The following sections discuss the different caching accesses and their associated cache modes. Chapter 4. Local Memory 4-13 Cache Operation 4.9.1.1 Cacheable Accesses If ACRn[CM] or the default field of the CACR indicates write-through or copyback, the access is cacheable. A read access to a write-through or copyback region is read from the cache if matching data is found. Otherwise, the data is read from memory and the cache is updated. When a line is being read from memory for either a write-through or copyback read miss, the longword within the line that contains the core-requested data is loaded first and the requested data is given immediately to the processor, without waiting for the three remaining longwords to reach the cache. The following sections describe write-through and copyback modes in detail. Note that some of this information applies to data caches only. 4.9.1.2 Write-Through Mode (Data Cache Only) Write accesses to regions specified as write-through are always passed on to the external bus, although the cycle can be buffered, depending on the state of CACR[DESB]. Writes in write-through mode are handled with a no-write-allocate policy--that is, writes that miss in the cache are written to the external bus but do not cause the corresponding line in memory to be loaded into the cache. Write accesses that hit always write through to memory and update matching cache lines. The cache supplies data to data-read accesses that hit in the cache; read misses cause a new cache line to be loaded into the cache. 4.9.1.3 Copyback Mode (Data Cache Only) Copyback regions are typically used for local data structures or stacks to minimize external bus use and reduce write-access latency. Write accesses to regions specified as copyback that hit in the cache update the cache line and set the corresponding M bit without an external bus access. Be sure to flush the cache using the CPUSHL instruction before invalidating the cache in copyback mode. Modified cache data is written to memory only if the line is replaced because of a miss or a CPUSHL instruction pushes the line. If a byte, word, longword, or line write access misses in the cache, the required cache line is read from memory, thereby updating the cache. When a miss selects a modified cache line for replacement, the modified cache data moves to the push buffer. The replacement line is read into the cache and the push buffer contents are then written to memory. 4.9.2 Cache-Inhibited Accesses Memory regions can be designated as cache-inhibited, which is useful for memory containing targets such as I/O devices and shared data structures in multiprocessing systems. It is also important to not cache the MCF5407 memory mapped registers. If the corresponding ACRn[CM] or CACR[DDCM] indicates cache-inhibited, precise or imprecise, the access is cache-inhibited. The caching operation is identical for both cache-inhibited modes, which differ only regarding recovery from an external bus error. 4-14 MCF5407 User's Manual Cache Operation In determining whether a memory location is cacheable or cache-inhibited, the CPU checks memory-control registers in the following order: 1. 2. 3. 4. RAMBARs ACR0 and ACR2 ACR1 and ACR3 If an access does not hit in the RAMBARs or the ACRs, the default is provided for all accesses in CACR. Cache-inhibited write accesses bypass the cache and a corresponding external write is performed. Cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the following conditions are true: * * * The cache-inhibited fill-buffer bit, CACR[DNFB], is set. The access is an instruction read. The access is normal (that is, TT = 0). In this case, a fetched line is stored in the fill buffer and remains valid there; the cache can service additional read accesses from this buffer until another fill occurs or a cache-invalidate-all operation occurs. If ACRn[CM] indicates cache-inhibited mode, precise or imprecise, the controller bypasses the cache and performs an external transfer. If a line in the cache matches the address and the mode is cache-inhibited, the cache does not automatically push the line if it is modified, nor does it invalidate the line if it is valid. Before switching cache mode, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] to invalidate the entire cache. If ACRn[CM] indicates precise mode, the sequence of read and write accesses to the region is guaranteed to match the instruction sequence. In imprecise mode, the processor core allows read accesses that hit in the cache to occur before completion of a pending write from a previous instruction. Writes are not deferred past data-read accesses that miss the cache (that is, that must be read from the bus). Precise operation forces data-read accesses for an instruction to occur only once by preventing the instruction from being interrupted after data is fetched. Otherwise, if the processor is not in precise mode, an exception aborts the instruction and the data may be accessed again when the instruction is restarted. These guarantees apply only when ACRn[CM] indicates precise mode and aligned accesses. CPU space-register accesses, such as MOVEC, are treated as cache-inhibited and precise. 4.9.3 Cache Protocol The following sections describe the cache protocol for processor accesses and assumes that the data is cacheable (that is, write-through or copyback). Note that the discussion of write operations applies to the data cache only. Chapter 4. Local Memory 4-15 Cache Operation 4.9.3.1 Read Miss A processor read that misses in the cache requests the cache controller to generate a bus transaction. This bus transaction reads the needed line from memory and supplies the required data to the processor core. The line is placed in the cache in the valid state. 4.9.3.2 Write Miss (Data Cache Only) The cache controller handles processor writes that miss in the data cache differently for write-through and copyback regions. Write misses to copyback regions cause the cache line to be read from system memory, as shown in Figure 4-6. 1. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line. Cache Line 0x0C 0x08 MCF5407 0x04 0x00 V=0 M=0 X 2. The cache line (characters A-P) is updated from system memory, and line is marked valid. 0x0C 0x08 0x04 0x00 V=1 ABCD EFGH IJKL MNOP M = 0 System Memory 3. After the cache line is filled, the write that initiated the write miss (the character X) completes to 0x0B. MCF5407 0x0C 0x08 0x04 0x00 V=1 ABCD EXGH IJKL MNOP M = 1 Figure 4-6. Write-Miss in Copyback Mode The new cache line is then updated with write data and the M bit is set for the line, leaving it in modified state. Write misses to write-through regions write directly to memory without loading the corresponding cache line into the cache. 4.9.3.3 Read Hit On a read hit, the cache provides the data to the processor core and the cache line state remains unchanged. If the cache mode changes for a specific region of address space, lines in the cache corresponding to that region that contain modified data are not pushed out to memory when a read hit occurs within that line. First execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching the cache mode. 4-16 MCF5407 User's Manual Cache Operation 4.9.3.4 Write Hit (Data Cache Only) The cache controller handles processor writes that hit in the data cache differently for write-through and copyback regions. For write hits to a write-through region, portions of cache lines corresponding to the size of the access are updated with the data. The data is also written to external memory. The cache line state is unchanged. For copyback accesses, the cache controller updates the cache line and sets the M bit for the line. An external write is not performed and the cache line state changes to (or remains in) the modified state. 4.9.4 Cache Coherency (Data Cache Only) The MCF5407 provides limited cache coherency support in multiple-master environments. Both write-through and copyback memory update techniques are supported to maintain coherency between the cache and memory. The cache does not support snooping (that is, cache coherency is not supported while external or DMA masters are using the bus). Therefore, on-chip DMAs of the MCF5407 cannot access local memory and do not maintain coherency with the data cache. 4.9.5 Memory Accesses for Cache Maintenance The cache controller performs all maintenance activities that supply data from the cache to the core, including requests to the SIM for reading new cache lines and writing modified lines to memory. The following sections describe memory accesses resulting from cache fill and push operations. Chapter 18, "Bus Operation," describes required bus cycles in detail. 4.9.5.1 Cache Filling When a new cache line is required, a line read is requested from the SIM, which generates a burst-read transfer by indicating a line access with the size signals, SIZ[1:0]. The responding device supplies 4 consecutive longwords of data. Burst operations can be inhibited or enabled through the burst read/write enable bits (BSTR/BSTW) in the chip-select control registers (CSCR0-CSCR7). SIM line accesses implicitly request burst-mode operations from memory. For more information regarding external bus burst-mode accesses, see Chapter 18, "Bus Operation." The first cycle of a cache-line read loads the longword entry corresponding to the requested address. Subsequent transfers load the remaining longword entries. A burst operation is aborted by an a write-protection fault, which is the only possible access error. Exception processing proceeds immediately. Note that unlike Version 2 and Version 3 access errors, the program counter stored on the exception stack frame points to the faulting instruction. See Section 2.8.2, "Processor Exceptions." Chapter 4. Local Memory 4-17 Cache Operation 4.9.5.2 Cache Pushes Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To reduce the requested data's latency in the new line, the modified line being replaced is temporarily placed in the push buffer while the new line is fetched from memory. After the bus transfer for the new line completes, the modified cache line is written back to memory and the push buffer is invalidated. 4.9.5.2.1 Push and Store Buffers The 16-byte push buffer reduces latency for requested new data on a cache miss by holding a displaced modified data cache line while the new data is read from memory. If a cache miss displaces a modified line, a miss read reference is immediately generated. While waiting for the response, the current contents of the cache location load into the push buffer. When the burst-read bus transaction completes, the cache controller can generate the appropriate line-write bus transaction to write the push buffer contents into memory. In imprecise mode, the FIFO store buffer can defer pending writes to maximize performance. The store buffer can support as many as four entries (16 bytes maximum) for this purpose. Data writes destined for the store buffer cannot stall the core. The store buffer effectively provides a measure of decoupling between the pipeline's ability to generate writes (one per cycle maximum) and the external bus's ability to retire those writes. In imprecise mode, writes stall only if the store buffer is full and a write operation is on the internal bus. The internal write cycle is held, stalling the data execution pipeline. If the store buffer is not used (that is, store buffer disabled or cache-inhibited precise mode), external bus cycles are generated directly for each pipeline write operation. The instruction is held in the pipeline until external bus transfer termination is received. Therefore, each write is stalled for 5 cycles, making the minimum write time equal to 6 cycles when the store buffer is not used. See Section 2.1.2.2, "Operand Execution Pipeline (OEP)." The data store buffer enable bit, CACR[DESB], controls the enabling of the data store buffer. This bit can be set and cleared by the MOVEC instruction. DESB is zero at reset and all writes are performed in order (precise mode). ACRn[CM] or CACR[DDCM] generates the mode used when DESB is set. Cacheable write-through and cache-inhibited imprecise modes use the store buffer. The store buffer can queue data as much as 4 bytes wide per entry. Each entry matches the corresponding bus cycle it generates; therefore, a misaligned longword write to a write-through region creates two entries if the address is to an odd-word boundary. It creates three entries if it is to an odd-byte boundary--one per bus cycle. 4.9.5.2.2 Push and Store Buffer Bus Operation As soon as the push or store buffer has valid data, the internal bus controller uses the next available external bus cycle to generate the appropriate write cycles. In the event that 4-18 MCF5407 User's Manual Cache Operation another cache fill is required (for example, cache miss to process) during the continued instruction execution by the processor pipeline, the pipeline stalls until the push and store buffers are empty, then generate the required external bus transaction. Supervisor instructions, the NOP instruction, and exception processing synchronize the processor core and guarantee the push and store buffers are empty before proceeding. Note that the NOP instruction should be used only to synchronize the pipeline. The preferred no-operation function is the TPF instruction. 4.9.6 Cache Locking Ways 0 and 1 of the data cache can be locked by setting CACR[DHLCK]; likewise, ways 0 and 1 of the instruction cache can be locked by setting CACR[IHLCK]. If a cache is locked, cache lines in ways 0 and 1 are not subject to being deallocated by normal cache operations. As Figure 4-7 (B and C) shows, the algorithm for updating the cache and for identifying cache lines to be deallocated is otherwise unchanged. If ways 2 and 3 are entirely invalid, cacheable accesses are first allocated in way 2. Way 3 is not used until the location in way 2 is occupied. Ways 0 and 1 are still updated on write hits (D in Figure 4-7) and may be pushed or cleared only explicitly by using specific cache push/invalidate instructions. However, new cache lines cannot be allocated in ways 0 and 1. Chapter 4. Local Memory 4-19 Cache Operation Invalid (V = 0) Valid, not modified (V = 1, M = 0) Valid, modified (V = 1, M = 1) A:Ways 0 and 1 are filled. Ways 2 and 3 are invalid. B:CACR[DHLCK] is set, locking ways 0 and 1. C:When a set in Way 2 is D:Write hits to ways 0 occupied, the set in way 3 and 1 update cache is used for a cacheable lines. access. Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 After CACR[DHLCK] is set, subsequent cache accesses go to ways 2 and 3. While the cache is locked and after a position in ways is full, the set in Way 3 is updated. While the cache is locked, ways 0 and 1 can be updated by write hits. In this example, memory is configured as copyback, so updated cache lines are marked modified. Set 0 Set 127 After reset, the cache is invalidated, ways 0 and 1 are then written with data that should not be deallocated. Ways 0 and 1 can be filled systematically by using the INTOUCH instruction. Figure 4-7. Data Cache Locking 4-20 MCF5407 User's Manual Cache Registers 4.10 Cache Registers This section describes the MCF5407 implementation of the Version 4 cache registers. 4.10.1 Cache Control Register (CACR) The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the MOVEC register instruction and can be read or written from the debug facility. A hardware reset clears CACR, which disables the cache; however, reset does not affect the tags, state information, or data in the cache. 31 30 29 28 27 26 Field DEC DW DESB DDPI DHLCK 25 DDCM Reset 24 23 DCINVA 20 19 18 BEC BCINVA -- 17 16 -- 0000_0000_0000_0000 R/W Write (R/W by debug module) 15 Field IEC 14 13 12 11 10 -- DNFB IDPI IHLCK IDCM Reset 9 8 -- ICINVA 7 0 -- 0000_0000_0000_0000 R/W Write (R/W by debug module) Rc 0x002 Figure 4-8. Cache Control Register (CACR) Table 4-4 describes CACR fields. Table 4-4. CACR Field Descriptions Bits Name Description 31 DEC Enable data cache. 0 Cache disabled. The data cache is not operational, but data and tags are preserved. 1 Cache enabled. 30 DW Data default write-protect. For normal operations that do not hit in the RAMBARs or ACRs, this field defines write-protection. See Section 4.9.1, "Caching Modes." 0 Not write protected. 1 Write protected. Write operations cause an access error exception. 29 DESB Enable data store buffer. Affects the precision of transfers. CACR[DESB] has precedence over CACR[9-8] and ACRn[9-8]; therefore, the store buffer must be disabled to use imprecise mode. 0 Imprecise-mode, write-through or cache-inhibited writes bypass the store buffer and generate bus cycles directly. Section 4.9.5.2.1, "Push and Store Buffers," describes the associated performance penalty. 1 The four-entry FIFO store buffer is enabled; to maximize performance, this buffer defers pending imprecise-mode, write-through or cache-inhibited writes. Precise-mode, cache-inhibited accesses always bypass the store buffer. Precise and imprecise modes are described in Section 4.9.2, "Cache-Inhibited Accesses." 28 DDPI Disable CPUSHL invalidation. 0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified and then invalidated. 1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified, then left valid. Chapter 4. Local Memory 4-21 Cache Registers Table 4-4. CACR Field Descriptions (Continued) Bits Name Description 27 DHLCK Half-data cache lock mode 0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache allocates the way pointed at by the counter and then increments this counter modulo-4. 1 Half-cache operation. The cache allocates to the lower invalid way of levels 2 and 3; if both are valid, the cache allocates to way 2 if the high-order bit of the round-robin counter is zero; otherwise, it allocates way 3 and increments the round-robin counter modulo-2. This locks the content of ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or cleared by specific cache push/invalidate instructions. This implementation allows maximum use of available cache memory and provides the flexibility of setting DHLCK before, during, or after allocations occur. 26-25 DDCM Default data cache mode. For normal operations that do not hit in the RAMBARs or ACRs, this field defines the effective cache mode. 00 Cacheable write-through imprecise 01 Cacheable copyback 10 Cache-inhibited precise 11 Cache-inhibited imprecise Precise and imprecise accesses are described in Section 4.9.2, "Cache-Inhibited Accesses." 24 23-20 DCINVA -- 19 BEC 18 BCINVA 17-16 -- 15 IEC 14 -- 13 DNFB 12 IDPI 4-22 Data cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. Once invalidation is complete, this bit automatically returns to 0; it is not necessary to clear it explicitly. Note the caches are not cleared on power-up or normal reset, as shown in Figure 4-4. 0 No invalidation is performed. 1 Initiate invalidation of the entire data cache. The cache controller sequentially clears V and M bits in all sets. Subsequent data accesses stall until the invalidation is finished, at which point, this bit is automatically cleared. In copyback mode, the cache should be flushed using a CPUSHL instruction before setting this bit. Reserved, should be cleared. Enable branch cache. The branch cache is described in Section 2.1.2.1.1, "Branch Acceleration." 0 Branch cache disabled. This may be useful if code is unlikely to be reused. 1 Branch cache enabled. Branch cache invalidate. Invalidation occurs when this bit is written as a 1. Note that branch caches are not cleared on power-up or normal reset. 0 No invalidation is performed. 1 Initiate an invalidation of the entire branch cache. Reserved. These bits must be cleared; otherwise performance may be affected. Enable instruction cache 0 Instruction cache disabled. All instructions and tags in the cache are preserved. 1 Instruction cache enabled. Reserved, should be cleared. Default cache-inhibited fill buffer 0 Fill buffer does not store cache-inhibited instruction accesses (16 or 32 bits). 1 Fill buffer can store cache-inhibited accesses. The buffer is used only for normal (TT = 0) instruction reads of a cache-inhibited region. Instructions are loaded into the buffer by a burst access (line fill). They stay in the buffer until they are displaced; subsequent accesses may not appear on the external bus. Setting DNFB can cause a coherency problem for self-modifying code. If a cache-inhibited access uses the buffer while DNFB = 1, instructions remain valid in the buffer until a cache-invalidate-all instruction, another cache-inhibited burst, or a miss that initiates a fill. A write to the line in the fill goes to the external bus without updating or invalidating the buffer. Subsequent reads of that written data are serviced by the fill buffer and receive stale information. Instruction CPUSHL invalidate disable. 0 Normal operation. A CPUSHL instruction causes the selected line to be invalidated. 1 No clear operation. A CPUSHL instruction causes the selected line to be left valid. MCF5407 User's Manual Cache Registers Table 4-4. CACR Field Descriptions (Continued) Bits Name Description 11 IHLCK Instruction cache half-lock. 0 Normal operation. The cache allocates to the lowest invalid way; if all ways are valid, the cache allocates to the way pointed at by the round-robin counter and then increments this counter modulo-4. 1 Half cache operation. The cache allocates to the lowest invalid way of ways 2 and 3; if both of these ways are valid, the cache allocates to way 2 if the high-order bit of the round-robin counter is zero; otherwise, it allocates way 3 and then increments the round-robin counter modulo-2. This locks the content of ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or cleared by specific cache push/invalidate instructions. This implementation allows maximum use of the available cache memory and also provides the flexibility of setting IHLCK before, during, or after the needed allocations occur. 10 IDCM Instruction default cache mode. For normal operations that do not hit in the RAMBARs or ACRs, this field defines the effective cache mode. 0 Cacheable 1 Cache-inhibited 9 -- Reserved, should be cleared. 8 ICINVA Instruction cache invalidate. Invalidation occurs when this bit is written as a 1. Note the caches are not cleared on power-up or normal reset. 0 No invalidation is performed. 1 Initiate invalidation of instruction cache. The cache controller sequentially clears all V bits. Subsequent local memory bus accesses stall until invalidation completes, at which point, ICINVA is cleared automatically without software intervention. For copyback mode, use CPUSHL before setting ICINVA. 7-0 -- Reserved. These bits must be cleared; otherwise, performance may be affected. 4.10.2 Access Control Registers (ACR0-ACR3) The ACRs, Figure 4-9, assign control attributes, such as cache mode and write protection, to specified memory regions. ACR0 and ACR1 control data attributes; ACR2 and ACR3 control instruction attributes. Registers are accessed with the MOVEC instruction with the Rc encodings in Figure 4-9. For overlapping data regions, ACR0 takes priority; ACR2 takes priority for overlapping instruction regions. Data transfers to and from these registers are longword transfers. Bits 12-7, 4, 3, 1, and 0 are always read as zeros. NOTE: The SIM MBAR region should be mapped as cache-inhibited through an ACR. Chapter 4. Local Memory 4-23 Cache Management 31 Field 24 23 Address Base Reset 16 15 14 13 12 Address Mask Uninitialized R/W E S 7 6 -- 0 5 CM 4 3 -- 2 W1 1 0 -- Uninitialized Write (R/W by debug module) Rc ACR0: 0x004; ACR1: 0x005; ACR2: 0x006; ACR3: 0x007 1 Reserved in ACR2 and ACR3. Figure 4-9. Access Control Register Format (ACRn) Table 4-5 describes ACRn fields. I Table 4-5. ACRn Field Descriptions Bits Name Description 31-24 Address base Address base. Compared with address bits A[31:24]. Eligible addresses that match are assigned the access control attributes of this register. 23-16 Address mask Address mask. Setting a mask bit causes the corresponding address base bit to be ignored. The low-order mask bits can be set to define contiguous regions larger than 16 Mbytes. The mask can define multiple noncontiguous regions of memory. 15 E Enable. Enables or disables the other ACRn bits. 0 Access control attributes disabled 1 Access control attributes enabled 14-13 S Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address range or if the type of access is a don't care. 00 Match addresses only in user mode 01 Match addresses only in supervisor mode 1x Execute cache matching on all accesses 12-7 -- Reserved; should be cleared. 6-5 CM Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are described in Section 4.9.2, "Cache-Inhibited Accesses." 00 Cacheable, write-through 01 Cacheable, copyback 10 Cache-inhibited, precise 11 Cache-inhibited, imprecise 4-3 -- Reserved, should be cleared. 2 W ACR0/ACR1 only. Write protect. Selects the write privilege of the memory region. ACR2[2] and ACR3[2] are reserved. 0 Read and write accesses permitted 1 Write accesses not permitted 1-0 -- Reserved, should be cleared. 4.11 Cache Management The cache can be enabled and configured by using a MOVEC instruction to access CACR. A hardware reset clears CACR, disabling the cache and removing all configuration information; however, reset does not affect the tags, state information, and data in the cache. Set CACR[DCINVA,ICINVA] to invalidate the caches before enabling them. 4-24 MCF5407 User's Manual Cache Management The privileged CPUSHL instruction supports cache management by selectively pushing and invalidating cache lines. The address register used with CPUSHL directly addresses the cache's directory array. The CPUSHL instruction flushes a cache line. The value of CACR[DDPI,IDPI] determines whether CPUSHL invalidates a cache line after it is pushed. To push the entire cache, implement a software loop to index through all sets and through each of the four lines within each set (a total of 512 lines for the data cache and 1024 lines for the instruction cache). The state of CACR[DEC,IEC] does not affect the operation of CPUSHL or CACR[DCINVA,ICINVA]. Disabling a cache by setting CACR[IEC] or CACR[DEC] makes the cache nonoperational without affecting tags, state information, or contents. The contents of An used with CPUSHL specify cache row and line indexes. This differs from the MC68040 where a physical address is specified. Figure 4-11 shows the An format for the data cache. 31 11 10 0 4 3 Set Index 0 Line Index Figure 4-10. An Format (Data Cache) Figure 4-11 shows the An format for the instruction cache. 31 12 11 0 4 Set Index 3 0 Line Index Figure 4-11. An Format (Instruction Cache) The following code example flushes the entire data cache: _cache_disable: nop move.w jsr clr.l movec movec move.l movec rts #0x2700,SR _cache_flush d0 d0,ACR0 d0,ACR1 #0x01000000,d0 d0,CACR ;mask off IRQs ;flush the cache completely ;ACR0 off ;ACR1 off ;Invalidate and disable cache _cache_flush: nop moveq.l moveq.l move.l #0,d0 #0,d1 d0,a0 ;synchronize--flush store buffer ;initialize way counter ;initialize set counter ;initialize cpushl pointer setloop: cpushl add.l addq.l cmpi.l bne dc,(a0) #0x0010,a0 #1,d1 #128,d1 setloop ;push cache line a0 ;increment set index by 1 ;increment set counter ;are sets for this way done? #0,d1 ;set counter to zero again moveq.l Chapter 4. Local Memory 4-25 Cache Management addq.l move.l cmpi.l bne rts #1,d0 d0,a0 #4,d0 setloop ;increment to next way ;set = 0, way = d0 ;flushed all the ways? The following CACR loads assume the instruction cache has been invalidated, the default instruction cache mode is cacheable, and the default data cache mode is copyback. dataCacheLoadAndLock: move.l movec #0xa3080800,d0; enable and invalidate data cache ... d0,cacr ; ... in the CACR The following code preloads half of the data cache (4 Kbytes). It assumes a contiguous block of data is to be mapped into the data cache, starting at a 0-modulo-4K address. move.l lea dataCacheLoop: tst.b lea subq.l bne.b #256,d0 data_,a0 ;256 16-byte lines in 4K space ; load pointer defining data area (a0) 16(a0),a0 #1,d0 dataCacheLoop ;touch location + load into data cache ;increment address to next line ;decrement loop counter ;if done, then exit, else continue ; A 4K region has been loaded into levels 0 and 1 of the 8K data cache. lock it! move.l movec rts #0xaa088000,d0 d0,cacr align 16 ;set the data cache lock bit ... ; ... in the CACR The following CACR loads assume the data cache has been invalidated, the default instruction cache mode is cacheable and the default operand cache mode is copyback. Note that this function must be mapped into a cache inhibited or SRAM space or these text lines will be prefetched into the instruction cache, which may displace some of the 8-Kbyte space being explicitly fetched. instructionCacheLoadAndLock: move.l movec #0xa2088100,d0 d0,cacr ;enable and invalidate the instruction ;cache in the CACR The following code segments preload half of the instruction cache (8 Kbytes). It assumes a contiguous block of data is to be mapped, starting at a 0-modulo-8K address move.l #512,d0 lea code_,a0 instCacheLoop: ; intouch (a0) ;512 16-byte lines in 8K space ;load pointer defining code area ;touch location + load into instruction cache ; Note in the assembler we use, there is no INTOUCH opcode. The following ; is used to produce the required binary representation cpushl 4-26 #nc,(a0) ;touch location + load into MCF5407 User's Manual Cache Operation Summary ;instruction cache lea 16(a0),a0 ;increment address to next line subq.l #1,d0 ;decrement loop counter bne.b instCacheLoop ;if done, then exit, else continue ; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. ; lock it! move.l movec rts #0xa2088800,d0 d0,cacr ;set the instruction cache lock bit ;in the CACR 4.12 Cache Operation Summary This section gives operational details for the cache and presents instruction and data cache-line state diagrams. 4.12.1 Instruction Cache State Transitions Because the instruction cache does not support writes, it supports fewer operations than the data cache. As Figure 4-12 shows, an instruction cache line can be in one of two states, valid or invalid. Modified state is not supported. Transitions are labeled with a capital letter indicating the previous state and with a number indicating the specific case listed in Table 4-6. These numbers correspond to the equivalent operations on data caches, described in Section 4.12.2, "Data Cache State Transitions." II5--ICINVA II6--CPUSHL & IDPI II7--CPUSHL & IDPI IV1--CPU read miss IV2--CPU read hit IV7--CPUSHL & IDPI II1--CPU read miss Invalid V=0 Valid V=1 IV5--ICINVA IV6--CPUSHL & IDPI Figure 4-12. Instruction Cache Line State Diagram Table 4-6 describes the instruction cache state transitions shown in Figure 4-12. Table 4-6. Instruction Cache Line State Transitions Current State Access Invalid (V = 0) Valid (V = 1) Read miss II1 Read line from memory and update cache; IV1 Read new line from memory and update cache; supply data to processor; stay in valid state. supply data to processor; go to valid state. Read hit II2 Not possible IV2 Supply data to processor; stay in valid state. Write miss II3 Not possible IV3 Not possible Write hit II4 Not possible IV4 Not possible Chapter 4. Local Memory 4-27 Cache Operation Summary Table 4-6. Instruction Cache Line State Transitions (Continued) Current State Access Invalid (V = 0) Valid (V = 1) Cache invalidate II5 No action; stay in invalid state. IV5 No action; go to invalid state. Cache push II6, No action; II7 stay in invalid state. IV6 No action; go to invalid state. IV7 No action; stay in valid state. 4.12.2 Data Cache State Transitions Using the V and M bits, the data cache supports a line-based protocol allowing individual cache lines to be invalid, valid, or modified. To maintain memory coherency, the data cache supports both write-through and copyback modes, specified by the corresponding ACR[CM], or CACR[DDCM] if no ACR matches. Read or write misses to copyback regions cause the cache controller to read a cache line from memory into the cache. If available, tag and data from memory update an invalid line in the selected set. The line state then changes from invalid to valid by setting the V bit. If all lines in the row are already valid or modified, the pseudo-round-robin replacement algorithm selects one of the four lines and replaces the tag and data. Before replacement, modified lines are temporarily buffered and later copied back to memory after the new line has been read from memory. Figure 4-13 shows the three possible data cache line states and possible processor-initiated transitions for memory configured as copyback. Transitions are labeled with a capital letter indicating the previous state and a number indicating the specific case listed in Table 4-7. CI5--DCINVA CI6--CPUSHL & DDPI CI7--CPUSHL & DDPI CV1--CPU read miss CV2--CPU read hit CV7--CPUSHL & DDPI CI1--CPU read miss Valid V=1 M=0 CV5--DCINVA CV6--CPUSHL & DDPI CI3--CPU write miss CD1--CPU read miss CD7--CPUSHL & DDPI CD5--DCINVA CV3--CPU write miss CD6--CPUSHL & DDPI CV4--CPU write hit Modified V=1 M=1 CD2--CPU read hit CD3--CPU write miss CD4--CPU write hit Invalid V=0 Figure 4-13. Data Cache Line State Diagram--Copyback Mode 4-28 MCF5407 User's Manual Cache Operation Summary Figure 4-14 shows the two possible states for a cache line in write-through mode. WV1--CPU read miss WV2--CPU read hit WV3--CPU write miss WV4--CPU write hit WV7--CPUSHL & DDPI WI3--CPU write miss WI5--DCINVA WI6--CPUSHL & DDPI WI7--CPUSHL & DDPI WI1--CPU read miss Invalid V=0 Valid V=1 WV5--DCINVA WV6--CPUSHL & DDPI Figure 4-14. Data Cache Line State Diagram--Write-Through Mode Table 4-7 describes data cache line transitions and the accesses that cause them. Table 4-7. Data Cache Line State Transitions Current State Access Invalid (V = 0) Valid (V = 1, M = 0) Modified (V = 1, M = 1) Read miss (C,W)I1 Read line from memory and update cache; supply data to processor; go to valid state. (C,W)V1 Read new line from memory and update cache; supply data to processor; stay in valid state. CD1 Push modified line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; go to valid state. Read hit (C,W)I2 Not possible. (C,W)V2 Supply data to processor; stay in valid state. CD2 Supply data to processor; stay in modified state. Write miss (copyback) CI3 Read line from memory and update cache; write data to cache; go to modified state. CV3 Read new line from memory and update cache; write data to cache; go to modified state. CD3 Push modified line to buffer; read new line from memory and update cache; write push buffer contents to memory; stay in modified state. Write miss (writethrough) WI3 Write data to memory; stay in invalid state. WV3 Write data to memory; stay in valid state. WD3 Write data to memory; stay in modified state. Cache mode changed for the region corresponding to this line. To avoid this state, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes. Write hit (copyback) CI4 Not possible. CV4 Write data to cache; go to modified state. CD4 Write data to cache; stay in modified state. Chapter 4. Local Memory 4-29 Cache Operation Summary Table 4-7. Data Cache Line State Transitions (Continued) Current State Access Invalid (V = 0) Write hit (writethrough) WI4 Not possible. Valid (V = 1, M = 0) WV4 Write data to memory and to cache; stay in valid state. Modified (V = 1, M = 1) WD4 Write data to memory and to cache; go to valid state. Cache mode changed for the region corresponding to this line. To avoid this state, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes. Cache (C,W)I5 No action; invalidate stay in invalid state. (C,W)V5 No action; go to invalid state. CD5 No action (modified data lost); go to invalid state. Cache push (C,W)V6 No action; go to invalid state. CD6 Push modified line to memory; go to invalid state. (C,W)V7 No action; stay in valid state. CD7 Push modified line to memory; go to valid state. (C,W)I6 No action; (C,W)I7 stay in invalid state. The following tables present the same information as Table 4-7, organized by the current state of the cache line. In Table 4-8 the current state is invalid. Table 4-8. Data Cache Line State Transitions (Current State Invalid) Access Response Read miss (C,W)I1 Read line from memory and update cache; supply data to processor; go to valid state. Read hit (C,W)I2 Not possible Write miss (copyback) CI3 Read line from memory and update cache; write data to cache; go to modified state. Write miss (write-through) WI3 Write data to memory; stay in invalid state. Write hit (copyback) CI4 Not possible Write hit (write-through) WI4 Not possible Cache invalidate (C,W)I5 No action; stay in invalid state. Cache push (C,W)I6 No action; stay in invalid state. Cache push (C,W)I7 No action; stay in invalid state. In Table 4-9 the current state is valid. 4-30 MCF5407 User's Manual Cache Operation Summary Table 4-9. Data Cache Line State Transitions (Current State Valid) Access Response Read miss (C,W)V1 Read new line from memory and update cache; supply data to processor; stay in valid state. Read hit (C,W)V2 Supply data to processor; stay in valid state. Write miss (copyback) CV3 Read new line from memory and update cache; write data to cache; go to modified state. Write miss (write-through) WV3 Write data to memory; stay in valid state. Write hit (copyback) CV4 Write data to cache; go to modified state. Write hit (write-through) WV4 Write data to memory and to cache; stay in valid state. Cache invalidate (C,W)V5 No action; go to invalid state. Cache push (C,W)V6 No action; go to invalid state. Cache push (C,W)V7 No action; stay in valid state. In Table 4-10 the current state is modified. Table 4-10. Data Cache Line State Transitions (Current State Modified) Access Response Read miss CD1 Push modified line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; go to valid state. Read hit CD2 Supply data to processor; stay in modified state. Write miss (copyback) CD3 Push modified line to buffer; read new line from memory and update cache; write push buffer contents to memory; stay in modified state. Write miss (write-through) WD3 Write data to memory; stay in modified state. Cache mode changed for the region corresponding to this line. To avoid this state, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes. Write hit (copyback) CD4 Write data to cache; stay in modified state. Write hit (write-through) WD4 Write data to memory and to cache; go to valid state. Cache mode changed for the region corresponding to this line. To avoid this state, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes. Chapter 4. Local Memory 4-31 Cache Initialization Code Table 4-10. Data Cache Line State Transitions (Current State Modified) (Continued) Access Response Cache invalidate CD5 No action (modified data lost); go to invalid state. Cache push CD6 Push modified line to memory; go to invalid state. Cache push CD7 Push modified line to memory; go to valid state. 4.13 Cache Initialization Code The following example sets up the cache for FLASH or ROM space only. move.l#0xA30C8100,D0 //enable cache, invalidate it, //default mode is cache-inhibited imprecise movecD0, CACR move.l #0xFF00C000,D0//cache FLASH space, enable, //ignore FC2, cacheable, writethrough movecD0,ACR0 4-32 MCF5407 User's Manual Chapter 5 Debug Support This chapter describes the Revision C enhanced hardware debug support in the MCF5407. This revision of the ColdFire debug architecture encompasses the two earlier revisions. 5.1 Overview The debug module is shown in Figure 5-1. High-speed local bus ColdFire CPU Core Debug Module Control BKPT Trace Port PSTDDATA[7:0] PSTCLK Communication Port DSCLK, DSI, DSO Figure 5-1. Processor/Debug Module Interface Debug support is divided into three areas: * * * Real-time trace support--The ability to determine the dynamic execution path through an application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel output bus that reports processor execution status and data to an external emulator system. See Section 5.3, "Real-Time Trace Support." Background debug mode (BDM)--Provides low-level debugging in the ColdFire processor complex. In BDM, the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers. The external emulator uses a three-pin, serial, full-duplex channel. See Section 5.5, "Background Debug Mode (BDM)," and Section 5.4, "Programming Model." Real-time debug support--BDM requires the processor to be halted, which many real-time embedded applications cannot do. Debug interrupts let real-time systems execute a unique service routine that can quickly save the contents of key registers and variables and return the system to normal operation. The emulator can access saved data because the hardware supports concurrent operation of the processor and BDM-initiated commands. See Section 5.6, "Real-Time Debug Support." Chapter 5. Debug Support 5-1 Signal Descriptions The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based on feedback from customers and third-party developers, enhancements have been added to succeeding generations of ColdFire cores. The Version 3 core implements the Revision B of the debug architecture, providing more flexibility for configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while hardware breakpoint registers are active. The MCF5407 core implements Revision C of the debug architecture, which more than doubles the on-chip breakpoint registers and provides an ability to interrupt debug service routines. For Revision C, the revision level bit, CSR[HRL], is 2. See Section 5.4.4, "Configuration/Status Register (CSR)." 5.2 Signal Descriptions Table 5-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor core's clock signal. The standard 26-pin debug connector is shown in Section 5.7, "Motorola-Recommended BDM Pinout." Table 5-1. Debug Module Signals Signal Description Development Serial Clock (DSCLK) Internally synchronized input that clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor CLK speed. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state. The logic level on DSCLK is validated if it has the same value on two consecutive rising CLKIN edges. Development Serial Input (DSI) Internally synchronized input that provides data input for the serial communication port to the debug module. Development Serial Output (DSO) Provides serial output communication for debug module responses. DSO is registered internally. Breakpoint (BKPT) Used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status/debug data signals (PSTDDATA[7:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. Processor Status Clock (PSTCLK) Half-speed version of the processor clock. Its rising edge appears in the center of the two processor-cycle window of valid PSTDDATA output. See Figure 5-2. Because debug trace port signals change on alternate processor cycles and are unrelated to external bus frequency, PSTCLK helps the development system sample PSTDDATA values. If real-time trace is not used, setting CSR[PCD] keeps PSTCLK and PSTDDATA outputs from toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing CSR[PCD], although the emulator must resynchronize with the PSTDDATA output. PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during system reset exception processing. Table 5-4 describes PST values. Chapter 7, "Phase-Locked Loop (PLL)," describes PSTCLK generation. Processor Status/Debug Data (PSTDDATA[7:0]) These outputs indicate both processor status and captured address and data values and are discussed more thoroughly in Section 5.2.1, "Processor Status/Debug Data (PSTDDATA[7:0]). 5-2 MCF5407 User's Manual Signal Descriptions Figure 5-2 shows PSTCLK timing. PSTCLK PSTDDATA Figure 5-2. PSTCLK Timing 5.2.1 Processor Status/Debug Data (PSTDDATA[7:0]) Processor status data outputs are used to indicate both processor status and captured address and data values. They operate at half the processor's frequency. Given that real-time trace information appears as a sequence of 4-bit data values, there are no alignment restrictions; that is, the processor status (PST) values and operands may appear on either nibble of PSTDDATA[7:0]. The upper nibble (PSTDDATA[7:4]) is the most significant. CSR controls capturing of data values. Executing the WDDATA instruction captures data displayed on PSTDDATA. These signals are updated each processor cycle and displayed two values at a time for two processor clock cycles. Table 5-2 shows the PSTDDATA output for the processor's sequential execution of single-cycle instructions (A, B, C, D...). Cycle counts are shown relative to processor frequency. These outputs indicate the current processor pipeline status and are not related to the current bus transfer. Table 5-2. PSTDDATA: Sequential Execution of Single-Cycle Instructions Cycle PSTDDATA[7:0] T {PST for A, PST for B} T+1 {PST for A, PST for B} T+2 {PST for C, PST for D} T+3 {PST for C, PST for D} T+4 {PST for E, PST for F} T+5 {PST for E, PST for F} The signal timing for the example in Table 5-2 is shown in Figure 5-3. PCLK PSTCLK PSTDDATA {A, B} {C, D} {E, F} Figure 5-3. PSTDDATA: Single-Cycle Instruction Timing Chapter 5. Debug Support 5-3 Real-Time Trace Support Table 5-3 shows the case where a PSTDDATA module captures a memory operand on a simple load instruction: mov.l <mem>,Rx. Table 5-3. PSTDDATA: Data Operand Captured Cycle T PSTDDATA[7:0] {PST for mov.l, PST marker for captured operand) = {0x1, 0xB} T+1 {0x1, 0xB} T+2 {Operand[3:0], Operand[7:4]} T+3 {Operand[3:0], Operand[7:4]} T+4 {Operand[11:8], Operand[15:12]} T+5 {Operand[11:8], Operand[15:12]} T+6 {Operand[19:16], Operand[23:20]} T+7 {Operand[19:16], Operand[23:20]} T+8 {Operand[27:24], Operand[31:28]} T+9 {Operand[27:24], Operand[31:28]} T+10 (PST for next instruction) T+11 (PST for next instruction,...) A PST marker and its data display are transmitted contiguously. Except for this transmission, the IDLE status (0x0) may appear any time. Again, given the real-time trace information appears as a sequence of 4-bit values, there are no alignment restrictions. That is, PST values and operands may appear on either nibble of PSTDDATA. 5.3 Real-Time Trace Support Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system. This 8-bit port is partitioned into two consecutive 4-bit nibbles. Each nibble can either transmit information concerning the processor's execution status (PST) or debug data (DDATA). The processor status may not be related to the current bus transfer. External development systems can use PSTDDATA outputs with an external image of the program to completely track the dynamic execution path. This tracking is complicated by any change in flow, especially when branch target address calculation is based on the contents of a program-visible register (variant addressing). PSTDDATA outputs can be configured to display the target address of such instructions in sequential nibble increments across multiple processor clock cycles, as described in Section 5.3.1, "Begin Execution of Taken Branch (PST = 0x5)." Four 32-bit storage elements form a FIFO buffer connecting the processor's high-speed local bus to the external development system through PSTDDATA[7:0]. The buffer captures branch target addresses and certain data values for eventual display on the PSTDDATA port, two nibbles at a time starting with the lsb. 5-4 MCF5407 User's Manual Real-Time Trace Support Execution speed is affected only when three storage elements have valid data to be dumped to the PSTDDATA port. This occurs only when two values are captured simultaneously in a read-modify-write operation; the core stalls until two FIFO entries are available. Table 5-4 shows the encoding of these signals. Table 5-4. Processor Status Encoding PST[3:0] Definition Hex Binary 0x0 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock cycles, subsequent clock cycles are indicated by driving PSTDDATA outputs with this encoding. 0x1 0001 Begin execution of one instruction. For most instructions, this encoding signals the first clock cycle of an instruction's execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions, generate different encodings. 0x2 0010 Begin execution of two instructions. For superscalar instruction dispatches, this encoding signals the first clock cycle of the simultaneous instructions' execution. 0x3 0011 Entry into user-mode. Signaled after execution of the instruction that caused the MCF5407 to enter user mode. 0x4 0100 Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the PSTDDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is signaled, followed by the appropriate marker, and then the data transfer on the PSTDDATA port. Transfer length depends on the WDDATA operand size. 0x5 0101 Begin execution of taken branch. For some opcodes, a branch target address may be displayed on PSTDDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins the data output. See Section 5.3.1, "Begin Execution of Taken Branch (PST = 0x5)." 0x6 0110 Begin execution of instruction plus a taken branch. The processor completes execution of a taken conditional branch instruction and simultaneously starts executing the target instruction. This is achieved through branch folding. 0x7 0111 Begin execution of return from exception (RTE) instruction. 0x8- 0xB 1000- 1011 Indicates the size of the next consecutive nibbles. The encoding is driven onto the PSTDDATA port one clock cycle before the data is displayed on PSTDDATA. 0x8 Begin 1-byte transfer on PSTDDATA. 0x9 Begin 2-byte transfer on PSTDDATA. 0xA Begin 3-byte transfer on PSTDDATA. 0xB Begin 4-byte transfer on PSTDDATA. 0xC 1100 Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace) generate a different encoding, 0xD. Because the 0xC encoding defines a multiple-cycle mode, PSTDDATA outputs are driven with 0xC until exception processing completes. 0xD 1101 Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace). Because this encoding defines a multiple-cycle mode, PSTDDATA outputs are driven with 0xD until exception processing completes. 0xE 1110 A breakpoint state change causes this encoding to assert for one cycle only followed by the trigger status value. If the processor stops waiting for an interrupt, the encoding is asserted for multiple cycles. See Section 5.3.2, "Processor Stopped or Breakpoint State Change (PST = 0xE)." 0xF 1111 Processor is halted. See Section 5.3.3, "Processor Halted (PST = 0xF)." Chapter 5. Debug Support 5-5 Real-Time Trace Support 5.3.1 Begin Execution of Taken Branch (PST = 0x5) PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on PSTDDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data output. Bytes are displayed in least-to-most-significant order. The processor captures only those target addresses associated with taken branches which use a variant addressing mode, that is, RTE and RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception vectors. The simplest example of a branch instruction using a variant address is the compiled code for a C language case statement. Typically, the evaluation of this statement uses the variable of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. For such change-of-flow operations, the MCF5407 uses the debug pins to output the following sequence of information on successive processor clock cycles: 1. Use PSTDDATA (0x5) to identify that a taken branch was executed. 2. Optionally signal the target address to be displayed sequentially on the PSTDDATA pins. Encodings 0x9-0xB identify the number of bytes displayed. 3. The new target address is optionally available on subsequent cycles using the PSTDDATA port. The number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes). Another example of a variant branch instruction would be a JMP (A0) instruction. Figure 5-4 shows when the PSTDDATA outputs that indicate when a JMP (A0) executed, assuming the CSR was programmed to display the lower 2 bytes of an address. PCLK PSTCLK PSTDDATA 0x59 A0[3-0,7-4] A0[11-8,15-12] Figure 5-4. Example JMP Instruction Output on PSTDDATA PSTDDATA is driven two nibbles at a time with a 0x59; 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the remaining 4 nibbles display the lower 2 bytes of address register A0 in least-to-most-significant nibble order. The PSTDDATA output after the JMP instruction continues with the next instruction. 5-6 MCF5407 User's Manual Real-Time Trace Support 5.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE) The 0xE encoding is generated either as a one- or multiple-cycle issue as follows: * * When the MCF5407 is stopped by a STOP instruction, this encoding appears in multiple-cycle format. The ColdFire processor remains stopped until an interrupt occurs, thus PSTDDATA outputs display 0xE until stopped mode is exited. When a breakpoint status change is to be output on PSTDDATA, 0xE is displayed for one cycle, followed immediately with the 4-bit value of the current trigger status, where the trigger status is left justified rather than in the CSR[BSTAT] description. Section 5.4.4, "Configuration/Status Register (CSR)," shows that status is right justified. That is, the displayed trigger status on PSTDDATA after a single 0xE is as follows: -- 0x0 = no breakpoints enabled -- 0x2 = waiting for level-1 breakpoint -- 0x4 = level-1 breakpoint triggered -- 0xA = waiting for level-2 breakpoint -- 0xC = level-2 breakpoint triggered Thus, 0xE can indicate multiple events, based on the next value, as Table 5-5 shows. Table 5-5. 0xE Status Posting PSTDDATA Stream Includes Result {0xE, 0x2} Breakpoint state changed to waiting for level-1 trigger {0xE, 0x4} Breakpoint state changed to level-1 breakpoint triggered {0xE, 0xA} Breakpoint state changed to waiting for level-2 trigger {0xE, 0xC} Breakpoint state changed to level-2 breakpoint triggered {0xE, 0xE} The MCF5407 is in stopped mode. 5.3.3 Processor Halted (PST = 0xF) PST is 0xF when the processor is halted (see Section 5.5.1, "CPU Halt"). Because this encoding defines a multiple-cycle mode, the PSTDDATA outputs display 0xF until the processor is restarted or reset. HALT can be distinguished from a data output 0xFF by counting 0xFF occurrences on PSTDDATA. Because data always follows a marker (0x8, 0x9, 0xA, or 0xB), the longest occurrence in PSTDDATA of 0xFF, in a data output, is four 0xFFs. Chapter 5. Debug Support 5-7 Programming Model Two scenarios exist for data--0xFFFF_FFFF * * A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xBF 0xFF 0xFF 0xFF 0xFX (X indicates that the next PST value is guaranteed to not be 0xF.) A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xYB 0xFF 0xFF 0xFF 0xFF 0xXY (X indicates the PST value is guaranteed not to be 0xF, and Y signifies a PSTDDATA value that doesn't affect the 0xFF count.) Thus, a count of either nine or more sequential single 0xF values or five or more sequential 0xFF values signifies the HALT condition. 5.4 Programming Model In addition to the existing BDM commands that provide access to the processor's registers and the memory subsystem, the debug module contains 19 registers to support the required functionality. These registers are also accessible from the processor's supervisor programming model by executing the WDEBUG instruction. Thus, the breakpoint hardware in the debug module can be accessed by the external development system using the debug serial interface or by the operating system running on the processor core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent. Hardware provides a locking mechanism in the CSR to allow the external development system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the MCF5407 is using the WDEBUG instruction to access debug module registers or the resulting behavior is undefined. These registers, shown in Figure 5-5, are treated as 32-bit quantities, regardless of the number of implemented bits. 5-8 MCF5407 User's Manual Programming Model 31 15 31 15 31 15 31 7 0 AATR Address attribute trigger register ABLR ABHR Address low breakpoint register Address high breakpoint register AATR1 Address 1 attribute register 0 7 15 0 0 ABLR1 Address low breakpoint 1 register ABHR1 Address high breakpoint 1 register 31 15 31 15 0 31 15 0 31 7 15 0 BAAR BDM address attribute register CSR Configuration/status register DBR DBMR Data breakpoint register Data breakpoint mask register 0 DBR1 Data breakpoint 1 register DBMR1 Data breakpoint mask 1 register 31 15 0 31 15 0 31 15 0 PBR PBR1 PBR2 PBR3 PBMR PC breakpoint register PC breakpoint 1 register PC breakpoint 2 register PC breakpoint 3 register PC breakpoint mask register TDR Trigger definition register XTDR Extended trigger definition register Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don't care). All debug control registers are writable from the external development system or the CPU via the WDEBUG instruction. CSR is write-only from the programming model as debug control register 0x00 using the supervisor-mode WDEBUG instruction. It can be read from and written through the BDM port using the RDMREG and WDMREG commands. Figure 5-5. Debug Programming Model These registers are accessed through the BDM port by new BDM commands, WDMREG and RDMREG, described in Section 5.5.3.3, "Command Set Descriptions." These commands contain a 5-bit field, DRc, that specifies the register, as shown in Table 5-6. Table 5-6. BDM/Breakpoint Registers DRc[4-0] 0x00 0x01-0x04 Register Name Configuration/status register Abbreviation Initial State Page CSR 0x0020_0000 p. 5-13 -- -- -- 0x05 BDM address attribute register Reserved BAAR 0x0000_0005 p. 5-12 0x06 Address attribute trigger register AATR 0x0000_0005 p. 5-10 Chapter 5. Debug Support 5-9 Programming Model Table 5-6. BDM/Breakpoint Registers (Continued) DRc[4-0] Register Name Abbreviation Initial State Page 0x07 Trigger definition register TDR 0x0000_0000 p. 5-18 0x08 Program counter breakpoint register PBR -- p. 5-16 0x09 Program counter breakpoint mask register PBMR -- p. 5-16 -- -- -- Address breakpoint high register ABHR -- p. 5-12 0x0D Address breakpoint low register ABLR -- p. 5-12 0x0E Data breakpoint register DBR -- p. 5-15 0x0F Data breakpoint mask register DBMR -- p. 5-15 -- -- -- 0x0A-0x0B Reserved 0x0C 0x10-0x15 Reserved 0x16 Address attribute trigger register 1 AATR1 0x0000_0005 p. 5-10 0x17 Extended trigger definition register XTDR 0x0000_0000 p. 5-19 0x18 Program counter breakpoint 1 register PBR1 0x0000_0000 p. 5-16 0x19 Reserved -- -- -- 0x1A Program counter breakpoint register 2 PBR2 0x0000_0000 p. 5-16 0x1B Program counter breakpoint register 3 PBR3 0x0000_0000 p. 5-16 0x1C Address high breakpoint register 1 ABHR1 -- p. 5-12 0x1D Address low breakpoint register 1 ABLR1 -- p. 5-12 0x1E Data breakpoint register 1 DBR1 -- p. 5-15 0x1F Data breakpoint mask register 1 DBMR1 -- p. 5-15 NOTE: Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction. CSR is write-only from the programming model as debug control register 0x00 using the supervisor-mode WDEBUG instruction. It can be read from and written through the BDM port using the RDMREG and WDMREG commands. 5.4.1 Address Attribute Trigger Registers (AATR, AATR1) The address attribute trigger registers (AATR, AATR1) define address attributes and a mask to be matched in the trigger. The register value is compared with address attribute signals from the processor's local high-speed bus, as defined by the setting of the trigger definition register (TDR) for AATR and the extended trigger definition register (XTDR) for AATR1. 5-10 MCF5407 User's Manual Programming Model 15 Field RM Reset 14 13 SZM 12 11 TTM 10 9 TMM 8 7 6 R 5 SZ 4 3 2 TT 1 0 TM 0000_0000_0000_0101 R/W AATR and AATR1 are accessible in supervisor mode as debug control register 0x06 and 0x16 respectively, and using the WDEBUG instruction and through the BDM port using the WDMREG command. DRc[4-0] 0x06 (AATR); 0x16 (AATR1) Figure 5-6. Address Attribute Trigger Registers (AATR, AATR1) Table 5-7 describes AATR and AATR1 fields. Table 5-7. AATR and AATR1 Field Descriptions Bits Name Description 15 RM Read/write mask. Setting RM masks R in address comparisons. 14-13 SZM Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons. 12-11 TTM Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons. 10-8 TMM Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address comparisons. 7 R Read/write. R is compared with the R/W signal of the processor's local bus. 6-5 SZ Size. Compared to the processor's local bus size signals. 00 Longword 01 Byte 10 Word 11 Reserved 4-3 TT Transfer type. Compared with the local bus transfer type signals. 00 Normal processor access 01 Reserved 10 Emulator mode access 11 Acknowledge/CPU space access These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates an external or DMA access (for backward compatibility). These bits affect the TM bits. 2-0 TM Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental information for each transfer type. TT = 00 (normal mode): 000 Data and instruction cache line push 001 User data access 010 User code access 011 Instruction cache invalidate 100 Data cache push 101 Supervisor data access 110 Supervisor code access 111 INTOUCH instruction access TT = 10 (emulator mode): 0xx-100 Reserved 101 Emulator mode data access 110 Emulator mode code access 111 Reserved TT = 11 (acknowledge/CPU space transfers): 000 CPU space access 001-111 Interrupt acknowledge levels 1-7 These bits also define the TM encoding for BDM memory commands (for backward compatibility). Chapter 5. Debug Support 5-11 Programming Model 5.4.2 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) The address breakpoint low and high registers (ABLR, ABLR1, ABHR, and ABHR1), Figure 5-7, define regions in the processor's data address space that can be used as part of the trigger. These register values are compared with the address for each transfer on the processor's high-speed local bus. TDR determines if the trigger is in the address in ABLR or either inside or outside of the range bound by ABLR and ABHR. XTDR determines the same for ABLR1 and ABHR1. 31 0 Field Address Reset -- R/W ABHR and ABHR1 are accessible in supervisor mode as debug control registers 0x0C and 0x1C, using the WDEBUG instruction and via the BDM port using the RDMREG and WDMREG commands. ABLR and ABLR1 are accessible in supervisor mode as debug control register 0x0D and 0x1D, using the WDEBUG instruction and via the BDM port using the WDMREG command. DRc[4-0] 0x0D (ABLR); 0x1D (ABLR1); 0x0C (ABHR); 0x1C (ABHR1) Figure 5-7. Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1) Table 5-8 describes ABLR and ABLR1 fields. Table 5-8. ABLR and ABLR1 Field Description Bits Name Description 31-0 Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for specific addresses are programmed into ABLR or ABLR1. Table 5-9 describes ABHR and ABHR1 fields. Table 5-9. ABHR and ABHR1 Field Description Bits Name Description 31-0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range. 5.4.3 BDM Address Attribute Register (BAAR) The BAAR defines the address space for memory-referencing BDM commands. See Figure 5-8. The reset value of 0x5 sets supervisor data as the default address space. 5-12 MCF5407 User's Manual Programming Model 7 Field 6 5 R 4 3 SZ 2 1 TT Reset 0 TM 0000_0101 R/W BAAR[R,SZ] are loaded directly from the BDM command; BAAR[TT,TM] can be programmed as debug control register 0x05 from the external development system. For compatibility with Rev. A, BAAR is loaded each time AATR is written. DRc[4-0] 0x05 Figure 5-8. BDM Address Attribute Register (BAAR) Table 5-10 describes BAAR fields. Table 5-10. BAAR Field Descriptions Bits Name Description 7 R Read/write 0 Write 1 Read 6-5 SZ Size 00 Longword 01 Byte 10 Word 11 Reserved 4-3 TT Transfer type. See the TT definition in Table 5-7. 2-0 TM Transfer modifier. See the TM definition in Table 5-7. 5.4.4 Configuration/Status Register (CSR) The configuration/status register (CSR) defines the debug configuration for the processor and memory subsystem and contains status information from the breakpoint logic. 31 30 29 28 27 26 25 24 23 22 20 19 18 17 16 Field BSTAT HRL -- Reset 0000 0 0 0 0 0010 -- -- -- 0 R/W1 R R R R R R -- -- -- R/W 10 9 3 2 1 0 15 14 13 Field MAP TRC EMU Reset 0 R/W R/W DRc[4-0] FOF TRG HALT BKPT 21 12 11 DDC UHE 8 BTB BKD PCD IPW 7 6 5 4 --2 NPL -- SSM -- 0 0 00 0 00 0 0 -- 0 -- R/W R/W R/W R/W R/W R R/W -- R/W -- 0x00 1 CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands. 2 Bit 7 is reserved for Motorola use and must be written as a zero. Figure 5-9. Configuration/Status Register (CSR) Chapter 5. Debug Support 5-13 Programming Model Table 5-11 describes CSR fields. Table 5-11. CSR Field Descriptions Bit 31-28 Name Description BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. Also output on PSTDDATA when it is not displaying PST or other processor data. BSTAT is cleared by a TDR or XTDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled. 0000 No breakpoints enabled 0001 Waiting for level-1 breakpoint 0010 Level-1 breakpoint triggered 0101 Waiting for level-2 breakpoint 0110 Level-2 breakpoint triggered 27 FOF Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. 26 TRG Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and forced entry into BDM. Reset and the debug GO command clear TRG. 25 HALT Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset and the debug GO command reset HALT. 24 BKPT Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset and the debug GO command clears this bit. HRL Hardware revision level. Indicates the level of debug module functionality. An emulator could use this information to identify the level of functionality supported. 0000 Initial debug functionality (Revision A) 0001 Revision B 0010 Revision C (this is the only valid value for the MCF5407) 19 -- Reserved, should be cleared. 18 BKD Breakpoint disable. Used to disable the normal BKPT input functionality and to allow the assertion of BKPT to generate a debug interrupt. 0 Normal operation 1 BKPT is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the processor. The processor makes this interrupt request pending until the next sample point, when the exception is initiated. In the ColdFire architecture, the interrupt sample point occurs once per instruction. There is no support for nesting debug interrupts. 17 PCD PSTCLK disable. Setting PCD disables generation of PSTCLK and PSTDDATA outputs and forces them to remain quiescent. 16 IPW Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module's programming model registers. IPW can be modified only by commands from the external development system. 15 MAP Force processor references in emulator mode. 0 All emulator-mode references are mapped into supervisor code and data spaces. 1 The processor maps all references while in emulator mode to a special address space, TT = 10, TM = 101 or 110. 14 TRC Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a trace exception occurs. 13 EMU Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See Section 5.6.1.1, "Emulator Mode." 23-20 5-14 MCF5407 User's Manual Programming Model Table 5-11. CSR Field Descriptions (Continued) Bit Name Description 12-11 DDC Debug data control. Controls operand data capture for PSTDDATA, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple clock cycles). See Table 5-4. 00 No operand data is displayed. 01 Capture all write data. 10 Capture all read data. 11 Capture all read and write data. 10 UHE User halt enable. Selects the CPU privilege level required to execute the HALT instruction. 0 HALT is a supervisor-only instruction. 1 HALT is a supervisor/user instruction. 9-8 BTB Branch target bytes. Defines the number of bytes of branch target address PSTDDATA displays. 00 0 bytes 01 Lower 2 bytes of the target address 10 Lower 3 bytes of the target address 11 Entire 4-byte target address See Section 5.3.1, "Begin Execution of Taken Branch (PST = 0x5)." 7 -- Reserved, should be cleared. 6 NPL Non-pipelined mode. Determines whether the core operates in pipelined or mode. 0 Pipelined mode 1 Nonpipelined mode. The processor effectively executes one instruction at a time with no overlap. This adds at least 5 cycles to the execution time of each instruction. Instruction folding is disabled. Given an average execution latency of 1.6, throughput in non-pipeline mode would be 6.6, approximately 25% or less compared to pipelined performance. Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction executes. In normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is imprecise. In non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise. An address or data breakpoint should always occur before the next instruction begins execution. Therefore the occurrence of the address/data breakpoints should be guaranteed. 5 -- Reserved, should be cleared. 4 SSM Single-step mode. Setting SSM puts the processor in single-step mode. 0 Normal mode. 1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the GO command, the processor executes the next instruction and halts again. This process continues until SSM is cleared. -- Reserved, should be cleared. 3-0 5.4.5 Data Breakpoint/Mask Registers (DBR/DBR1, DBMR/DBMR1) The data breakpoint registers (DBR/DBR1), Figure 5-10, specify data patterns used as part of the trigger into debug mode. Only DBRn bits not masked with a corresponding zero in DBMRn are compared with the data from the processor's local bus, as defined in TDR. Chapter 5. Debug Support 5-15 Programming Model 31 0 Field Data (DBR/DBR1); Mask (DBMR/DBMR1) Reset Uninitialized R/W DBR and DBR1 are accessible in supervisor mode as debug control register 0x0E and 0x1E, using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands. DBMR and DBMR1 are accessible in supervisor mode as debug control register 0x0F and 0x0F1 using the WDEBUG instruction and via the BDM port using the WDMREG command. DRc[4-0] 0x0E (DBR), 0x1E (DBR1); 0x0F (DBMR), 0x1F (DBMR1) Figure 5-10. Data Breakpoint/Mask Registers (DBR/DBR1 and DBMR/DBMR1) Table 5-12 describes DBRn fields. Table 5-12. DBRn Field Descriptions Bits Name 31-0 Data Description Data breakpoint value. Contains the value to be compared with the data value from the processor's local bus as a breakpoint trigger. Table 5-13 describes DBMRn fields. Table 5-13. DBMRn Field Descriptions Bits 31-0 Name Mask Description Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBRn bit allows the corresponding DBRn bit to be compared to the appropriate bit of the processor's local data bus. Setting a DBMRn bit causes that bit to be ignored. DBRs support both aligned and misaligned references. Table 5-14 shows relationships between processor address, access size, and location within the 32-bit data bus. Table 5-14. Access Size and Operand Data Location A[1:0] Access Size Operand Location 00 Byte D[31:24] 01 Byte D[23:16] 10 Byte D[15:8] 11 Byte D[7:0] 0x Word D[31:16] 1x Word D[15:0] xx Longword D[31:0] 5.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBR1, PBR2, PBR3, PBMR) Each PC breakpoint register (PBR, PBR1, PBR2, PBR3) defines an instruction address for use as part of the trigger. These registers' contents are compared with the processor's 5-16 MCF5407 User's Manual Programming Model program counter register when the appropriate valid bit is set and TDR and/or XTDR are configured appropriately. PBR bits are masked by clearing corresponding PBMR bits. Results are compared with the processor's program counter register, as defined in TDR and/or XTDR. PBR1-PBR3 are not masked. Figure 5-11 shows the PC breakpoint register. 31 1 0 Field Program Counter V1 Reset -- 0 R/W Write. PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in Section 5.5.3.3, "Command Set Descriptions." DRc[4-0] 1 PBR 0x08 (PBR); 0x18 (PBR1); 0x1A (PBR2); 0x1B (PBR3) does not have a valid bit. PBR[0] is read as 0 and should be cleared. Figure 5-11. Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3) Table 5-15 describes PBR, PBR1, PBR2, and PBR3 fields. Table 5-15. PBR, PBR1, PBR2, PBR3 Field Descriptions Bits Name Description 31-1 Address PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint trigger. PBR does not have a valid bit. 0 V Valid. Breakpoint registers are compared with the processor's program counter register when the appropriate valid bit is set and TDR and/or XTDR are configured appropriately. This bit is not implemented on PBR. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG instruction and via the BDM port using the WDMREG command. Figure 5-12 shows PBMR. 31 1 0 Field Mask -- Reset -- -- R/W Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG instruction and via the BDM port using the wdmreg command. DRc[4-0] 0x09 Figure 5-12. Program Counter Breakpoint Mask Register (PBMR) Table 5-16 describes PBMR fields. Table 5-16. PBMR Field Descriptions Bits Name 31-0 Mask Description PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored. Chapter 5. Debug Support 5-17 Programming Model 5.4.7 Trigger Definition Register (TDR) The TDR, shown in Table 5-13, configures the operation of the hardware breakpoint logic that corresponds with the ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module. In conjunction with the XTDR and its associated debug registers, TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as one- or two-level triggers. TDR[31-16] and/or XTDR[31-16] define second-level triggers and bits 15-0 define first-level triggers. NOTE: The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before defining triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. Section 5.4.9, "Resulting Set of Possible Trigger Combinations," describes how to handle multiple breakpoint conditions. Second-Level Triggers 31 Field 30 TRC 29 EBL 28 27 26 25 24 23 22 EDLW EDWL EDWU EDLL EDLM EDUM EDUU Reset 21 20 DI EAI 19 18 17 EAR EAL EPC 16 PCI 0000_0000_0000_0000 R/W Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command. First-Level Triggers 15 Field 14 -- 13 EBL 12 11 10 9 8 7 6 EDLW EDWL EDWU EDLL EDLM EDUM EDUU Reset 5 4 DI EAI 3 2 1 EAR EAL EPC 0 PCI 0000_0000_0000_0000 R/W Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command. DRc[4-0] 0x07 Figure 5-13. Trigger Definition Register (TDR) Table 5-17 describes TDR fields. 5-18 MCF5407 User's Manual Programming Model Table 5-17. TDR Field Descriptions Bits Name Description 31-30 TRC Trigger response control. Determines how the processor responds to a completed trigger condition. The trigger response is always displayed on PSTDDATA. 00 Display on PSTDDATA only 01 Processor halt 10 Debug interrupt 11 Reserved 29/13 EBL Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] or XTDR[EBL] enables a breakpoint trigger; clearing both disables all breakpoints. 28-22 12-6 EDx Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement on the processor's local data bus. Clearing all EDx bits disables data breakpoints. 28/12 EDLW Data longword. Entire processor's local data bus. 27/11 EDWL Lower data word. 26/10 EDWU Upper data word. 25/9 EDLL Lower lower data byte. Low-order byte of the low-order word. 24/8 EDLM Lower middle data byte. High-order byte of the low-order word. 23/7 EDUM Upper middle data byte. Low-order byte of the high-order word. 22/6 EDUU Upper upper data byte. High-order byte of the high-order word. 21/5 DI Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR contents. 20-18/ 4-2 EAx Enable address bits. Setting an EA bit enables the corresponding address breakpoint. Clearing all three bits disables the breakpoint. 20/4 EAI Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR. 19/3 EAR Enable address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR. EAL Enable address breakpoint low. The breakpoint is based on the address in the ABLR. 18/2 17/1 EPC Enable PC breakpoint. If set, this bit enables the PC breakpoint. 16/0 PCI Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR/PBR1/PBR2/PBR3 and PBMR to enable a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR/PBR1/PBR2/PBR3 and PBMR. 5.4.8 Extended Trigger Definition Register (XTDR) The XTDR configures the operation of the hardware breakpoint logic that corresponds with the ABHR1/ABLR1/AATR1 and DBR1/DBMR1 registers within the debug module and, in conjunction with the TDR and its associated debug registers, controls the actions taken under the defined conditions. The breakpoint logic may be configured as a one- or two-level trigger, where TDR[31-16] and/or XTDR[31-16] define the second-level trigger and bits 15-0 define the first-level trigger. The XTDR is accessible in supervisor mode as debug control register 0x17 using the WDEBUG instruction and via the BDM port using the WDMREG command. Chapter 5. Debug Support 5-19 Programming Model NOTE: The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before defining triggers. A write to the XTDR clears the trigger status bits, CSR[BSTAT]. Section 5.4.9, "Resulting Set of Possible Trigger Combinations," describes how to handle multiple breakpoint conditions. Second-Level Triggers 31 30 29 EBL 28 27 26 25 24 23 22 EDLW EDWL EDWU EDLL EDLM EDUM EDUU 21 20 19 18 17 16 DI EAI EAR EAL -- Field -- Reset -- 000_0000_0000_000 -- R/W -- Write -- First-Level Triggers 15 14 13 EBL 12 11 10 9 8 7 6 EDLW EDWL EDWU EDLL EDLM EDUM EDUU 5 4 3 2 DI EAI EAR EAL 1 0 Field -- Reset -- 000_0000_0000_000 -- R/W -- Write -- DRc[4-0] 0x17 Figure 5-14. Extended Trigger Definition Register (XTDR) Table 5-18 describes XTDR fields. Table 5-18. XTDR Field Descriptions Bits Name Description 29/13 EBL Enable breakpoint level. If set, EBL is the global enable for the breakpoint trigger; that is, if TDR[EBL] or XTDR[EBL] is set, a breakpoint trigger is enabled. Clearing both disables all breakpoints. 28-22 12-6 EDx Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement on the processor's local data bus. Clearing all EDx bits disables data breakpoints. 28/12 EDLW Data longword. Entire processor's local data bus. 27/11 EDWL Lower data word. 26/10 EDWU Upper data word. 25/9 EDLL Lower lower data byte. Low-order byte of the low-order word. 24/8 EDLM Lower middle data byte. High-order byte of the low-order word. 23/7 EDUM Upper middle data byte. Low-order byte of the high-order word. 22/6 EDUU Upper upper data byte. High-order byte of the high-order word. 5-20 MCF5407 User's Manual -- Programming Model Table 5-18. XTDR Field Descriptions (Continued) Bits Name Description 21/5 DI Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR1 contents. 20-18/ 4-2 EAx Enable address bits. Setting an EAx bit enables the corresponding address breakpoint. If all three bits are cleared, this breakpoint is disabled. 20/4 EAI Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR1 and ABHR1. 19/3 EAR Enable address breakpoint range. Breakpoint is based on the range defined between ABLR1 and ABHR1. 18/2 EAL Enable address breakpoint low. The breakpoint is based on the address in ABLR1. 17-16, 1-0 -- Reserved, should be cleared. 5.4.9 Resulting Set of Possible Trigger Combinations The resulting set of possible breakpoint trigger combinations consist of the following options where || denotes logical OR, && denotes logical AND, and {} denotes an optional additional trigger term: One-level triggers of the form: if if if (PC_breakpoint) (PC_breakpoint||Address_breakpoint{&& Data_breakpoint}) (PC_breakpoint||Address_breakpoint{&& Data_breakpoint} || Address1_breakpoint{&& Data1_breakpoint}) if if (Address_breakpoint {&& Data_breakpoint}) ((Address_breakpoint {&& Data_breakpoint}) || (Address1_breakpoint{&& Data1_breakpoint})) if (Address1_breakpoint {&& Data1_breakpoint}) Two-level triggers of the form: if (PC_breakpoint) then if (Address_breakpoint{&& Data_breakpoint}) if (PC_breakpoint) then if (Address_breakpoint{&& Data_breakpoint} || Address1_breakpoint{&& Data1_breakpoint}) if (PC_breakpoint) then if (Address1_breakpoint{&& Data1_breakpoint}) if (Address_breakpoint {&& Data_breakpoint}) then if (Address1_breakpoint{&& Data1_breakpoint}) if (Address1_breakpoint {&& Data1_breakpoint}) then if (Address_breakpoint{&& Data_breakpoint}) if (Address_breakpoint {&& Data_breakpoint}) then if (PC_breakpoint) if (Address1_breakpoint {&& Data1_breakpoint}) Chapter 5. Debug Support 5-21 Background Debug Mode (BDM) then if (PC_breakpoint) if (Address_breakpoint {&& Data_breakpoint}) then if (PC_breakpoint || Address1_breakpoint{&& Data1_breakpoint}) if (Address1_breakpoint {&& Data1_breakpoint}) then if (PC_breakpoint || Address_breakpoint{&& Data_breakpoint}) In this example, PC_breakpoint is the logical summation of the PBR/PBMR, PBR1, PBR2, and PBR3 breakpoint registers; Address_breakpoint is a function of ABHR, ABLR, and AATR; Data_breakpoint is a function of DBR and DBMR; Address1_breakpoint is a function of ABHR1, ABLR1, and AATR1; and Data1_breakpoint is a function of DBR1 and DBMR1. In all cases, the data breakpoints can be included with an address breakpoint to further qualify a trigger event as an option. 5.5 Background Debug Mode (BDM) The ColdFire Family implements a low-level system debugger in the microprocessor hardware. Communication with the development system is handled through a dedicated, high-speed serial command interface. The ColdFire architecture implements the BDM controller in a dedicated hardware module. Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM commands, such as memory accesses, can be executed while the processor is running. 5.5.1 CPU Halt Although many BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority: 1. A catastrophic fault-on-fault condition automatically halts the processor. 2. A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 5.6.1, "Theory of Operation." 3. The execution of a HALT instruction immediately suspends execution. Attempting to execute HALT in user mode while CSR[UHE] = 0 generates a privilege violation exception. If CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes, the processor can be restarted by serial shifting a GO command into the debug module. Execution continues at the instruction after HALT. 5-22 MCF5407 User's Manual Background Debug Mode (BDM) 4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution of each instruction. If there is a pending halt condition at the sample time, the processor suspends execution and enters the halted state. The assertion of BKPT should be considered in the following two special cases: * * After the system reset signal is negated, the processor waits for 16 clock cycles before beginning reset exception processing. If the BKPT input is asserted within eight cycles after RSTI is negated, the processor enters the halt state, signaling halt status (0xF) on the PSTDDATA outputs. While the processor is in this state, all resources accessible through the debug module can be referenced. This is the only chance to force the processor into emulation mode through CSR[EMU]. After system initialization, the processor's response to the GO command depends on the set of BDM commands performed while it is halted for a breakpoint. Specifically, if the PC register was loaded, the GO command causes the processor to exit halted state and pass control to the instruction address in the PC, bypassing normal reset exception processing. If the PC was not loaded, the GO command causes the processor to exit halted state and continue reset exception processing. The ColdFire architecture also handles a special case of BKPT being asserted while the processor is stopped by execution of the STOP instruction. For this case, the processor exits the stopped mode and enters the halted state, at which point, all BDM commands may be exercised. When restarted, the processor continues by executing the next sequential instruction, that is, the instruction following the STOP opcode. CSR[27-24] indicates the halt source, showing the highest priority source for multiple halt conditions. Debug module Revisions A and B clear CSR[27-24] upon a read of the CSR, but Revision C (in the MCF5407) does not. The debug GO command clears CSR[26-24]. HALT can be recognized by counting 0xFF occurrences on PSTDDATA. The count is necessary to determine between a possible data output value of 0xFF and the HALT condition. Because data always follows a marker (0x8, 0x9, 0xA, or 0xB), PSTDDATA can display no more than four data 0xFFs. Two such scenarios exist: * A B marker occurs on the left nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xBF 0xFF 0xFF 0xFF 0xFX (X indicates that the next PST value is guaranteed to not be 0xF) Chapter 5. Debug Support 5-23 Background Debug Mode (BDM) * A B marker occurs on the right nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xYB 0xFF 0xFF 0xFF 0xFF 0xXY (X indicates that the PST value is guaranteed to not be 0xF; and Y indicates a PSTDDATA value that doesn't affect the 0xFF count). Thus, a count of either nine or more sequential single 0xF values or five or more sequential 0xFF values signifies the HALT condition. 5.5.2 BDM Serial Interface When the CPU is halted and PSTDDATA reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSCLK and DSI must meet the required input setup and hold timings and the DSO is specified as a delay relative to the rising edge of the processor clock. See Table 5-1. The development system serves as the serial communication channel master and must generate DSCLK. The serial channel operates at a frequency from DC to 1/5 of the processor frequency. The channel uses full-duplex mode, where data is sent and received simultaneously by both master and slave devices. The transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown in Figure 5-15, all state transitions are enabled on a rising edge of the processor clock when DSCLK is high; that is, DSI is sampled and DSO is driven. C1 C2 C3 C4 CPU CLK PSTCLK DSCLK DSI BDM State Machine DSO Current Current State Past Next Next State Current Figure 5-15. BDM Serial Interface Timing 5-24 MCF5407 User's Manual Background Debug Mode (BDM) DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor CLK as well as the DSI. DSO is delayed from the DSCLK-enabled CLK rising edge (registered after a BDM state machine state change). All events in the debug module's serial state machine are based on the processor clock rising edge. DSCLK must also be sampled low (on a positive edge of CLK) between each bit exchange. The MSB is transferred first. Because DSO changes state based on an internally-recognized rising edge of DSCLK, DSDO cannot be used to indicate the start of a serial transfer. The development system must count clock cycles in a given transfer. C1-C4 are described as follows: * * * C1--First synchronization cycle for DSI (DSCLK is high). C2--Second synchronization cycle for DSI (DSCLK is high). C3--BDM state machine changes state depending upon DSI and whether the entire input data transfer has been transmitted. C4--DSO changes to next value. * NOTE: A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 5.5.2.1 Receive Packet Format The basic receive packet, Figure 5-16, consists of 16 data bits and 1 status bit. 16 15 S 0 Data Field [15:0] Figure 5-16. Receive BDM Packet Table 5-19 describes receive BDM packet fields. Table 5-19. Receive BDM Packet Field Description Bits Name 16 S 15-0 Data Description Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. S Data Message 0 xxxx Valid data transfer 0 0xFFFF Status OK 1 0x0000 Not ready with response; come again 1 0x0001 Error--Terminated bus cycle; data invalid 1 0xFFFF Illegal command Data. Contains the message to be sent from the debug module to the development system. The response message is always a single word, with the data field encoded as shown above. Chapter 5. Debug Support 5-25 Background Debug Mode (BDM) 5.5.2.2 Transmit Packet Format The basic transmit packet, Figure 5-17, consists of 16 data bits and 1 control bit. 16 15 0 C D[15:0] Figure 5-17. Transmit BDM Packet Table 5-20 describes transmit BDM packet fields. Table 5-20. Transmit BDM Packet Field Description Bits Name 16 C 15-0 Data Description Control. This bit is reserved. Command and data transfers initiated by the development system should clear C. Contains the data to be sent from the development system to the debug module. 5.5.3 BDM Command Set Table 5-21 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. Table 5-21. BDM Command Summary Command Mnemonic Read A/D register RAREG/ Write A/D register WAREG/ Read memory location Description CPU State1 Section Command (Hex) Read the selected address or data register and return the results through the serial interface. Halted 5.5.3.3.1 0x218 {A/D, Reg[2:0]} Write the data operand to the specified address or data register. Halted 5.5.3.3.2 0x208 {A/D, Reg[2:0]} READ Read the data at the memory location specified by the longword address. Steal 5.5.3.3.3 0x1900--byte 0x1940--word 0x1980--lword Write memory location WRITE Write the operand data to the memory location specified by the longword address. Steal 5.5.3.3.4 0x1800--byte 0x1840--word 0x1880--lword Dump memory block DUMP Used with READ to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. A DUMP command retrieves subsequent operands. Steal 5.5.3.3.5 0x1D00--byte 0x1D40--word 0x1D80--lword Fill memory block FILL Used with WRITE to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. A FILL command writes subsequent operands. Steal 5.5.3.3.6 0x1C00--byte 0x1C40--word 0x1C80--lword Resume execution GO The pipeline is flushed and refilled before resuming instruction execution at the current PC. Halted 5.5.3.3.7 0x0C00 Perform no operation; may be used as a null command. Parallel 5.5.3.3.8 0x0000 RDREG WDREG No operation NOP 5-26 MCF5407 User's Manual Background Debug Mode (BDM) Table 5-21. BDM Command Summary (Continued) CPU State1 Section Capture the current PC and display it on the PSTDDATA output pins. Parallel 5.5.3.3.9 0x0001 Read control RCREG register Read the system control register. Halted 5.5.3.3.10 0x2980 Write control WCREG register Write the operand data to the system control register. Halted 5.5.3.3.11 0x2880 Read debug module register RDMREG Read the debug module register. Parallel 5.5.3.3.12 0x2D {0x42 DRc[4:0]} Write debug module register WDMREG Write the operand data to the debug module register. Parallel 5.5.3.3.13 0x2C {0x42 Drc[4:0]} Command Output the current PC Mnemonic SYNC_PC Description Command (Hex) 1 General command effect and/or requirements on CPU operation: - Halted. The CPU must be halted to perform this command. - Steal. Command generates bus cycles that can be interleaved with bus accesses. - Parallel. Command is executed in parallel with CPU activity. 2 0x4 is a three-bit field. Unassigned command opcodes are reserved by Motorola. All unused command formats within any revision level perform a NOP and return the illegal command response. 5.5.3.1 ColdFire BDM Command Format All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in Figure 5-18. 15 10 Operation 9 8 0 R/W 7 6 5 4 3 Op Size 0 0 A/D 2 0 Register Extension Word(s) Figure 5-18. BDM Command Format Table 5-22 describes BDM fields. Table 5-22. BDM Field Descriptions Bit Name Description 15-10 Operation Specifies the command. These values are listed in Table 5-21. 9 0 Reserved 8 R/W Direction of operand transfer. 0 Data is written to the CPU or to memory from the development system. 1 The transfer is from the CPU to the development system. Chapter 5. Debug Support 5-27 Background Debug Mode (BDM) Table 5-22. BDM Field Descriptions (Continued) Bit 7-6 Name Description Operand Size Operand data size for sized operations. Addresses are expressed as 32-bit absolute values. Note that a command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined. Referenced data is returned in the lower 8 bits of the response. Operand Size Bit Values 00 Byte 8 bits 01 Word 16 bits 10 Longword 32 bits 11 Reserved -- 5-4 00 Reserved 3 A/D Address/data. Determines whether the register field specifies a data or address register. 0 Indicates a data register. 1 Indicates an address register. 2-0 Register Contains the register number in commands that operate on processor registers. 5.5.3.1.1 Extension Words as Required Some commands require extension words for addresses and/or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Longword accesses are forcibly longword-aligned and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long. Byte and word data each requires a single extension word and longword data requires two extension words. Operands and addresses are transferred most-significant word first. In the following descriptions of the BDM command set, the optional set of extension words is defined as address, data, or operand data. 5.5.3.2 Command Sequence Diagrams The command sequence diagram in Figure 5-19 shows serial bus traffic for commands. Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module's response to the previous development system commands. Command and result transactions overlap to minimize latency. 5-28 MCF5407 User's Manual Background Debug Mode (BDM) COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS LOW-ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL-RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS NOT COMPLETED READ (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION XXX "NOT READY" XXXXX XXX MS RESULT XXX BERR NEXT COMMAND CODE NEXT CMD LS RESULT NEXT CMD "NOT READY" DATA UNUSED FROM THIS TRANSFER SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY DEBUG MODULE RESULTS FROM PREVIOUS COMMAND SEQUENCE TAKEN IF BUS ERROR OCCURS ON MEMORY ACCESS HIGH- AND LOW-ORDER 16 BITS OF RESULT RESPONSES FROM THE DEBUG MODULE Figure 5-19. Command Sequence Diagram The sequence is as follows: * * In cycle 1, the development system command is issued (READ in this example). The debug module responds with either the low-order results of the previous command or a command complete status of the previous command, if no results are required. In cycle 2, the development system supplies the high-order 16 address bits. The debug module returns a not-ready response unless the received command is decoded as unimplemented, which is indicated by the illegal command encoding. If this occurs, the development system should retransmit the command. NOTE: A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. * * In cycle 3, the development system supplies the low-order 16 address bits. The debug module always returns a not-ready response. At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response. Chapter 5. Debug Support 5-29 Background Debug Mode (BDM) * Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command's opcode is sent to the debug module during the final transfer. If a memory or register access is terminated with a bus error, the error status (S = 1, DATA = 0x0001) is returned instead of result data. 5.5.3.3 Command Set Descriptions The following sections describe the commands summarized in Table 5-21. NOTE: The BDM status bit (S) is 0 for normally completed commands; S = 1 for illegal commands, not-ready responses, and transfers with bus-errors. Section 5.5.2, "BDM Serial Interface," describes the receive packet format. Motorola reserves unassigned command opcodes for future expansion. Unused command formats in any revision level perform a NOP and return an illegal command response. 5.5.3.3.1 Read A/D Register (RAREG/RDREG) Read the selected address or data register and return the 32-bit result. A bus error response is returned if the CPU core is not halted. Command/Result Formats: 15 Command 12 11 8 0x2 7 0x1 Result 4 0x8 3 A/D 2 0 Register D[31:16] D[15:0] Figure 5-20. RAREG/RDREG Command Format Command Sequence: RAREG/RDREG ??? XXX MS RESULT XXX BERR NEXT CMD LS RESULT NEXT CMD "NOT READY" Figure 5-21. RAREG/RDREG Command Sequence Operand Data: None Result Data: The contents of the selected register are returned as a longword value, most-significant word first. 5-30 MCF5407 User's Manual Background Debug Mode (BDM) 5.5.3.3.2 Write A/D Register (WAREG/WDREG) The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: 15 Command 12 0x2 11 8 7 0x0 Result 4 0x8 3 A/D 2 0 Register D[31:16] D[15:0] Figure 5-22. WAREG/WDREG Command Format Command Sequence WDREG/WAREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX BERR NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Figure 5-23. WAREG/WDREG Command Sequence Operand Data Longword data is written into the specified address or data register. The data is supplied most-significant word first. Result Data Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. Chapter 5. Debug Support 5-31 Background Debug Mode (BDM) 5.5.3.3.3 Read Memory Location (READ) Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command/Result Formats: 15 12 Byte 11 8 0x1 7 0x9 4 3 0x0 Command 0 0x0 A[31:16] A[15:0] Result Word X X Command X X X 0x1 X X X 0x9 D[7:0] 0x4 0x0 0x8 0x0 A[31:16] A[15:0] Result D[15:0] Longword Command 0x1 0x9 A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 5-24. READ Command/Result Formats Command Sequence: READ (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" READ MEMORY LOCATION XXX "NOT READY" XXXCMD NEXT RESULT XXX BERR READ (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" READ MEMORY LOCATION NEXT CMD "NOT READY" XXX "NOT READY" XXX XXX MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD "NOT READY" Figure 5-25. READ Command Sequence Operand Data The only operand is the longword address of the requested location. Result Data Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result, the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs. 5-32 MCF5407 User's Manual Background Debug Mode (BDM) 5.5.3.3.4 Write Memory Location (WRITE) Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command Formats: 15 12 Byte 11 8 0x1 7 0x8 4 0x0 3 1 0x0 A[31:16] A[15:0] X Word X X 0x1 X X X X X 0x8 D[7:0] 0x4 0x0 0x8 0x0 A[31:16] A[15:0] D[15:0] Longword 0x1 0x8 A[31:16] A[15:0] D[31:16] D[15:0] Figure 5-26. WRITE Command Format Chapter 5. Debug Support 5-33 Background Debug Mode (BDM) Command Sequence: WRITE (B/W) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" WRITE (LONG) ??? MS ADDR "NOT READY" LS ADDR "NOT READY" MS DATA "NOT READY" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Figure 5-27. WRITE Command Sequence Operand Data This two-operand instruction requires a longword absolute address that specifies a location to which the data operand is to be written. Byte data is sent as a 16-bit word, justified in the LSB; 16- and 32-bit operands are sent as 16 and 32 bits, respectively Result Data Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs. 5-34 MCF5407 User's Manual Background Debug Mode (BDM) 5.5.3.3.5 Dump Memory Block (DUMP) is used with the READ command to access large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. If an initial READ is not executed before the first DUMP, an illegal command response is returned. The DUMP command retrieves subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent DUMP commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register. DUMP NOTE: DUMP does not check for a valid address; it is a valid command only when preceded by NOP, READ, or another DUMP command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a DUMP command is processed, allowing the operand size to be dynamically altered. Command/Result Formats: 15 Byte Command Result Word Command 12 11 X X 8 0x1 X X 0xD X 0x1 X 4 3 0x0 X X 0xD Result Longword Command 7 0 0x0 D[7:0] 0x4 0x0 0x8 0x0 D[15:0] 0x1 0xD Result D[31:16] D[15:0] Figure 5-28. DUMP Command/Result Formats Chapter 5. Debug Support 5-35 Background Debug Mode (BDM) Command Sequence: READ MEMORY LOCATION DUMP (B/W) ??? XXX "NOT READY" NEXT CMD RESULT XXX "ILLEGAL" NEXT CMD "NOT READY" READ MEMORY LOCATION DUMP (LONG) ??? XXX "ILLEGAL" XXX BERR NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "NOT READY" NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD "NOT READY" Figure 5-29. DUMP Command Sequence Operand Data: None Result Data: Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if a bus error occurs. 5-36 MCF5407 User's Manual Background Debug Mode (BDM) 5.5.3.3.6 Fill Memory Block (FILL) A FILL command is used with the WRITE command to access large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. The FILL command writes subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register after the memory write. Subsequent FILL commands use this address, perform the write, increment it by the current operand size, and store the updated address in the temporary register. If an initial WRITE is not executed preceding the first FILL command, the illegal command response is returned. NOTE: The FILL command does not check for a valid address--FILL is a valid command only when preceded by another FILL, a NOP, or a WRITE command. Otherwise, an illegal command response is returned. The NOP command can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a FILL command is processed, allowing the operand size to be altered dynamically. Command Formats: 15 12 Byte X Word 11 8 0x1 X 7 0xC X X X 0x1 X 4 3 0x0 X X 0xC 0 0x0 D[7:0] 0x4 0x0 0x8 0x0 D[15:0] Longword 0x1 0xC D[31:16] D[15:0] Figure 5-30. FILL Command Format Chapter 5. Debug Support 5-37 Background Debug Mode (BDM) Command Sequence: FILL FILL(LONG) (B/W) ??? MS DATA "NOT READY" XXX "ILLEGAL" LS DATA "NOT READY" WRITE MEMORY LOCATION XXX "NOT READY" NEXT CMD "CMD COMPLETE" NEXT CMD "NOT READY" XXX BERR FILL(LONG) (B/W) FILL ??? DATA "NOT READY" WRITE MEMORY LOCATION XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "NOT READY" XXX "NOT READY" NEXT CMD "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Figure 5-31. FILL Command Sequence Operand Data: A single operand is data to be written to the memory location. Byte data is sent as a 16-bit word, justified in the least-significant byte; 16and 32-bit operands are sent as 16 and 32 bits, respectively. Result Data: Command complete status (0xFFFF) is returned when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs. 5-38 MCF5407 User's Manual Background Debug Mode (BDM) 5.5.3.3.7 Resume Execution (GO) The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes. If a GO command is issued and the CPU is not halted, the command is ignored. 15 12 11 8 0x0 0xC 7 4 0x0 3 0 0x0 Figure 5-32. GO Command Format Command Sequence: GO ??? NEXT CMD "CMD COMPLETE" Figure 5-33. GO Command Sequence Operand Data: None Result Data: The command-complete response (0xFFFF) is returned during the next shift operation. Chapter 5. Debug Support 5-39 Background Debug Mode (BDM) 5.5.3.3.8 No Operation (NOP) NOP performs no operation and may be used as a null command where required. Command Formats: 15 12 11 8 0x0 0x0 7 4 0x0 3 0 0x0 Figure 5-34. NOP Command Format Command Sequence: NOP ??? NEXT CMD "CMD COMPLETE" Figure 5-35. NOP Command Sequence Operand Data: None Result Data: The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation. 5-40 MCF5407 User's Manual Background Debug Mode (BDM) 5.5.3.3.9 Synchronize PC to the PSTDDATA Lines (SYNC_PC) The SYNC_PC command captures the current PC and displays it on the PSTDDATA outputs. After the debug module receives the command, it sends a signal to the ColdFire processor that the current PC must be displayed. The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of CSR[BTB]. The specific sequence of PSTDDATA values is as follows: 1. Debug signals a SYNC_PC command is pending. 2. CPU completes the current instruction. 3. CPU forces an instruction fetch to the next PC, generates a PST = 0x5 value indicating a taken branch and signals the capture of DDATA. 4. The instruction address corresponding to the PC is captured. 5. The PST marker (0x9-0xB) is generated and displayed as defined by CSR[BTB] followed by the captured PC address. The SYNC_PC command can be used to dynamically access the PC for performance monitoring. The execution of this command is considerably less obtrusive to the real-time operation of an application than a HALT-CPU/READ-PC/RESUME command sequence. Command Formats: 15 12 11 0x0 8 0x0 7 4 0x0 3 0 0x1 Figure 5-36. SYNC_PC Command Format Command Sequence: SYNC_PC NOP ??? NEXT CMD "CMD COMPLETE" Figure 5-37. SYNC_PC Command Sequence Operand Data: None Result Data: Command complete status (0xFFFF) is returned when the register write is complete. Chapter 5. Debug Support 5-41 Background Debug Mode (BDM) 5.5.3.3.10 Read Control Register (RCREG) Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same as that used by the MOVEC instruction. Command/Result Formats: 15 Command 12 11 8 7 4 3 0 0x2 0x9 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D[31:16] D[15:0] Figure 5-38. RCREG Command/Result Formats Rc encoding: Table 5-23. Control Register Map Rc Register Definition Rc Register Definition 0x002 Cache control register (CACR) 0x805 MAC mask register (MASK) 0x004 Access control register 0 (ACR0) 0x806 MAC accumulator (ACC) 0x005 Access control register 1 (ACR1) 0x80E Status register (SR) 0x006 Access control register 2 (ACR2) 0x80F Program register (PC) 0x007 Access control register 2 (ACR3) 0xC04 RAM base address register (RAMBAR0) 0x801 Vector base register (VBR) 0xC05 RAM base address register (RAMBAR1) 0x804 MAC status register (MACSR) 0xC0F Memory base address (MBAR) Command Sequence: RCREG ??? MS ADDR EXT WORD "NOT READY" MS ADDR EXT WORD "NOT READY" READ CONTROL MEMORY REGISTER LOCATION XXX "NOT READY" XXX MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD "NOT READY" Figure 5-39. RCREG Command Sequence Operand Data: The only operand is the 32-bit Rc control register select field. Result Data: Control register contents are returned as a longword, most-significant word first. The implemented portion of registers smaller than 32 bits is guaranteed correct; other bits are undefined. 5-42 MCF5407 User's Manual Background Debug Mode (BDM) 5.5.3.3.11 Write Control Register (WCREG) The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats: 15 Command 12 11 8 7 4 3 0 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D[31:16] D[15:0] Figure 5-40. WCREG Command/Result Formats Command Sequence: WCREG ??? MS ADDR EXT WORD "NOT READY" MS ADDR EXT WORD "NOT READY" MS DATA "NOT READY" LS DATA "NOT READY" WRITE WRITE CONTROL MEMORY REGISTER LOCATION XXX "NOT READY" XXX CMD NEXT "CMD COMPLETE" XXX BERR NEXT CMD "NOT READY" Figure 5-41. WCREG Command Sequence Operand Data: This instruction requires two longword operands. The first selects the register to which the operand data is to be written; the second contains the data. Result Data: Successful write operations return 0xFFFF. Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001. Chapter 5. Debug Support 5-43 Background Debug Mode (BDM) 5.5.3.3.12 Read Debug Module Register (RDMREG) Read the selected debug module register and return the 32-bit result. The only valid register selection for the RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR clears the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled. Command/Result Formats: 15 Command 12 11 8 0x2 7 5 4 0 0x41 0xD Result DRc D[31:16] D[15:0] Figure 5-42. 1 RDMREG BDM Command/Result Formats Note 0x4 is a 3-bit field Table 5-24 shows the definition of DRc encoding. Table 5-24. Definition of DRc Encoding--Read DRc[4:0] Debug Register Definition Mnemonic Initial State Page 0x00 Configuration/Status CSR 0x0 p. 5-13 0x01-0x1F Reserved -- -- -- Command Sequence: RDMREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX "ILLEGAL" NEXT CMD "NOT READY" Figure 5-43. RDMREG Command Sequence Operand Data: None Result Data: The contents of the selected debug register are returned as a longword value. The data is returned most-significant word first. 5-44 MCF5407 User's Manual Real-Time Debug Support 5.5.3.3.13 Write Debug Module Register (WDMREG) The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. Command Format: Figure 5-44. WDMREG BDM Command Format 15 12 11 0x2 8 7 5 4 0x41 0xC 0 DRc D[31:16] D[15:0] 1 Note: 0x4 is a three-bit field Table 5-6 shows the definition of the DRc write encoding. Command Sequence: WDMREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Figure 5-45. WDMREG Command Sequence Operand Data: Longword data is written into the specified debug register. The data is supplied most-significant word first. Result Data: Command complete status (0xFFFF) is returned when register write is complete. 5.6 Real-Time Debug Support The ColdFire Family provides support debugging real-time applications. For these types of embedded systems, the processor must continue to operate during debug. The foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can generally tolerate small intrusions into the real-time operation. The debug module provides three types of breakpoints--PC with mask, operand address range, and data with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger response also programmable. The debug module programming model can be written from either the external development system using the debug serial interface or from the processor's supervisor programming model using the WDEBUG instruction. Only CSR is readable using the external development system. Chapter 5. Debug Support 5-45 Real-Time Debug Support 5.6.1 Theory of Operation Breakpoint hardware can be configured to respond to triggers in several ways. The response desired is programmed into TDR. As shown in Table 5-25, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the PSTDDATA output port when it is not displaying captured processor status, operands, or branch addresses. See Section 5.3.2, "Processor Stopped or Breakpoint State Change (PST = 0xE)." Table 5-25. PSTDDATA Nibble/CSR[BSTAT] Breakpoint Response PSTDDATA Nibble/CSR[BSTAT] 1 1 Breakpoint Status 0000/0000 No breakpoints enabled 0010/0001 Waiting for level-1 breakpoint 0100/0010 Level-1 breakpoint triggered 1010/0101 Waiting for level-2 breakpoint 1100/0110 Level-2 breakpoint triggered Encodings not shown are reserved for future use. The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status is also cleared by writing to either TDR or XTDR. BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates, a breakpoint trigger generates the response defined in TDR. PC breakpoints are treated in a precise manner--exception recognition and processing are initiated before the excepting instruction is executed. All other breakpoint events are recognized on the processor's local bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these interrupts are imprecise. In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] = 01, a breakpoint trigger causes the core to halt (PST = 0xF). If the processor core cannot be halted, the debug interrupt can be used. With this configuration, TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC breakpoint to occur before the targeted instruction executes. This is possible because the PC breakpoint is enabled when interrupt sampling occurs. For address and data breakpoints, reporting is considered imprecise because several instructions may execute after the triggering address or data is detected. As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for multiple cycles. The core enters emulator mode when exception 5-46 MCF5407 User's Manual Real-Time Debug Support processing begins. After the standard 8-byte exception stack is created, the processor fetches a unique exception vector from the vector table. Table 5-26 describes the two unique entries that distinguish PC breakpoints from other trigger events. Table 5-26. Exception Vector Assignments Vector Number Vector Offset (Hex) Stacked Program Counter Assignment 12 0x030 Next Non-PC-breakpoint debug interrupt 13 0x034 Next PC-breakpoint debug interrupt In the case of a two-level trigger, the last breakpoint event determines the exception vector; however, if the second-level trigger is PC || Address {&& Data} (as shown in the last condition in the code example in Section 5.4.9, "Resulting Set of Possible Trigger Combinations"), the vector taken is determined by the first condition that occurs after the first-level trigger--vector 13 if PC occurs first or vector 12 if Address {&& Data} occurs first. If both occur simultaneously, the non-PC-breakpoint debug interrupt is taken (vector number 12). Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. The debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program-visible registers into a reserved memory area. During a debug interrupt service routine, all normal interrupt requests are evaluated and sampled once per instruction. If any exception occurs, the processor responds as follows: 1. It saves a copy of the current value of the emulator mode state bit and then exits emulator mode by clearing the actual state. 2. Bit 1 of the fault status field (FS1) in the next exception stack frame is set to indicate the processor was in emulator mode when the interrupt occurred. This corresponds to bit 17 of the longword at the top of the system stack. See Section 2.8.1, "Exception Stack Frame Definition." 3. It passed control to the appropriate exception handler. 4. It executes an RTE instruction when the exception handler finishes. During the processing of the RTE, FS1 is reloaded from the system stack. If this bit is set, the processor sets the emulator mode state and resumes execution of the original debug interrupt service routine. This is signaled externally by the generation of the PST value that originally identified the debug interrupt exception, that is, PST = 0xD. Fault status encodings are listed in Table 2-21. Implementation of this debug interrupt handling fully supports the servicing of a number of normal interrupt requests during a debug interrupt service routine. The emulator mode state bit is essentially changed to be a program-visible value, stored into memory during exception stack frame creation, and loaded from memory by the RTE instruction. When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator mode. After the debug interrupt handler completes execution, the external Chapter 5. Debug Support 5-47 Real-Time Debug Support development system can use BDM commands to read the reserved memory locations. The generation of another debug interrupt during the first instruction after the RTE exits emulator mode is inhibited. This behavior is consistent with the existing logic involving trace mode where the first instruction executes before another trace exception is generated. Thus, all hardware breakpoints are disabled until the first instruction after the RTE completes execution, regardless of the programmed trigger response. 5.6.1.1 Emulator Mode Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered in three different ways: * * * Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is negated and the processor begins reset exception processing. It can be set while the processor is halted before reset exception processing begins. See Section 5.5.1, "CPU Halt." A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins. Setting CSR[TRC] forces the processor into emulation mode when trace exception processing begins. While operating in emulation mode, the processor exhibits the following properties: * * Unmasked interrupt requests are serviced. The resulting interrupt exception stack frame has FS[1] set to indicate the interrupt occurred while in emulator mode. If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory accesses are forced into a specially mapped address space signaled by TT = 2, TM = 5 or 6. This includes stack frame writes and the vector fetch for the exception that forced entry into this mode. The return-from-exception (RTE) instruction exits emulation mode. The processor status output port provides a unique encoding for emulator mode entry (0xD) and exit (0x7). 5.6.2 Concurrent BDM and Processor Operation The debug module supports concurrent operation of both the processor and most BDM commands. BDM commands may be executed while the processor is running, except those following operations that access processor/memory registers: * * Read/write address and data registers Read/write control registers For BDM commands that access memory, the debug module requests the processor's local bus. The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus. 5-48 MCF5407 User's Manual Motorola-Recommended BDM Pinout Breakpoint registers must be carefully configured in a development system if the processor is executing. The debug module contains no hardware interlocks, so TDR and XTDR should be disabled while breakpoint registers are loaded, after which TDR and XTDR can be written to define the exact trigger. This prevents spurious breakpoint triggers. Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU is writing the debug's registers (DSCLK must be inactive). 5.7 Motorola-Recommended BDM Pinout The ColdFire BDM connector, Figure 5-46, is a 26-pin Berg connector arranged 2 x 13. Developer reserved 1 1 2 BKPT GND 3 4 DSCLK GND 5 6 Developer reserved1 RESET 7 8 DSI +3.3V2 9 10 DSO GND 11 12 PSTDDATA7 PSTDDATA6 13 14 PSTDDATA5 PSTDDATA4 15 16 PSTDDATA3 PSTDDATA2 17 18 PSTDDATA1 PSTDDATA0 19 20 GND Motorola reserved 21 22 Motorola reserved GND 23 24 PSTCLK VDD_CPU 25 26 TA 1 Pins reserved for BDM 2 Supplied by target. developer use. Figure 5-46. Recommended BDM Connector 5.8 Debug C Definition of PSTDDATA Outputs This section specifies the ColdFire processor and debug module's generation of the PSTDDATA output on an instruction basis. In general, the PSTDDATA output for an instruction is defined as PSTDDATA = 1, {[89B], operand} where the {...} definition is optional operand information defined by the setting of the CSR. The [89B] signifies a PST value that is a marker identifying the presence and size of valid data to follow. A PST value of 0x8 (1 byte of data), 0x9 (2 bytes), or 0xB (4 bytes) is displayed before the data output. The CSR allows operands to be displayed based on reference type (read, write, or both). A PST value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the PSTDDATA output {1, 2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions, CSR[9,8] provides the ability to display {0x2, 0x3, or 0x4} bytes of the target instruction address. A PST value {0x9, 0xA, or 0xB} provides the marker identifying the size and presence of a valid target address on the PSTDDATA output. Chapter 5. Debug Support 5-49 Debug C Definition of PSTDDATA Outputs 5.8.1 User Instruction Set Table 5-27 shows the PSTDDATA specification for user-mode instructions. Table 5-27. PSTDDATA Specification for User-Mode Instructions Instruction Syntax PSTDDATA add.l <ea>y,Rx PSTDDATA = 1, {B, source operand} add.l Dy,<ea>x PSTDDATA = 1, {B, source}, {B, destination} addi.l #imm,Dx PSTDDATA = 1 addq.l #imm,<ea>x PSTDDATA = 1, {B, source}, {B, destination} addx.l Dy,Dx PSTDDATA = 1 and.l <ea>y,Dx PSTDDATA = 1, {B, source operand} and.l Dy,<ea>x PSTDDATA = 1, {B, source}, {B, destination} andi.l #imm,Dx PSTDDATA = 1 asl.l {Dy,#imm},Dx PSTDDATA = 1 asr.l {Dy,#imm},Dx bcc.{b,w,l} PSTDDATA = 1 if taken, then PSTDDATA = 5, else PSTDDATA = 1 bchg Dy,<ea>x PSTDDATA = 1, {8, source}, {8, destination} bchg #imm,<ea>x PSTDDATA = 1, {8, source}, {8, destination} bclr Dy,<ea>x PSTDDATA = 1, {8, source}, {8, destination} bclr #imm,<ea>x bra.{b,w,l} PSTDDATA = 1, {8, source}, {8, destination} PSTDDATA = 5 bset Dy,<ea>x PSTDDATA = 1, {8, source}, {8, destination} bset #imm,<ea>x PSTDDATA = 1, {8, source}, {8, destination} btst Dy,<ea>x PSTDDATA = 1, {8, source operand} btst #imm,<ea>x PSTDDATA = 1, {8, source operand} clr.b <ea>x PSTDDATA = 1, {8, destination operand} clr.w <ea>x PSTDDATA = 1, {9, destination operand} clr.l <ea>x PSTDDATA = 1, {B, destination operand} cmp.b <ea>y,Rx PSTDDATA = 1, {8, source operand} cmp.w <ea>y,Rx PSTDDATA = 1, {9, source operand} cmp.l <ea>y,Rx PSTDDATA = 1, {B, source operand} cmpi.b #imm,Dx PSTDDATA = 1 cmpi.w #imm,Dx PSTDDATA = 1 cmpi.l #imm,Dx PSTDDATA = 1 divs.l <ea>y,Dx PSTDDATA = 1, {B, source operand} divs.w <ea>y,Dx PSTDDATA = 1, {9, source operand} divu.l <ea>y,Dx PSTDDATA = 1, {B, source operand} bsr.{b,w,l} 5-50 PSTDDATA = 5, {B, destination operand} MCF5407 User's Manual Debug C Definition of PSTDDATA Outputs Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Syntax PSTDDATA divu.w <ea>y,Dx PSTDDATA = 1, {9, source operand} eor.l Dy,<ea>x PSTDDATA = 1, {B, source}, {B, destination} eori.l #imm,Dx PSTDDATA = 1 ext.w Dx PSTDDATA = 1 ext.l Dx PSTDDATA = 1 extb.l Dx PSTDDATA = 1 jmp <ea>x PSTDDATA = 5, {[9AB], target address} 1 jsr <ea>x PSTDDATA = 5, {[9AB], target address},{B, destination operand} 1 lea <ea>y,Ax PSTDDATA = 1 link.w Ay,#imm PSTDDATA = 1, {B, destination operand} lsl.l {Dy,#imm},Dx PSTDDATA = 1 lsr.l {Dy,#imm},Dx PSTDDATA = 1 mac.l Ry,Rx PSTDDATA = 1 mac.l Ry,Rx,ea,Rw PSTDDATA = 1, {B, source operand} mac.w Ry,Rx PSTDDATA = 1 mac.w Ry,Rx,ea,Rw PSTDDATA = 1, {B, source operand} mov3q.l #imm,<ea>x PSTDDATA = 1, {B, destination operand} move.b <ea>y,<ea>x PSTDDATA = 1, {8, source}, {8, destination} move.w <ea>y,<ea>x PSTDDATA = 1, {9, source}, {9, destination} move.l <ea>y,<ea>x PSTDDATA = 1, {B, source}, {B, destination} move.l <ea>y,ACC PSTDDATA = 1 move.l <ea>y,MACSR PSTDDATA = 1 move.l <ea>y,MASK PSTDDATA = 1 move.l ACC,Rx PSTDDATA = 1 move.l MACSR,CCR PSTDDATA = 1 move.l MACSR,Rx PSTDDATA = 1 move.l MASK,Rx PSTDDATA = 1 move.w CCR,Dx PSTDDATA = 1 move.w {Dy,#imm},CCR PSTDDATA = 1 movem.l <ea>y,#list PSTDDATA = 1, {B, source},... 2 movem.l #list,<ea>x PSTDDATA = 1, {B, destination},...2 moveq #imm,Dx PSTDDATA = 1 msac.l Ry,Rx PSTDDATA = 1 msac.l Ry,Rx,ea,Rw PSTDDATA = 1, {B, source operand} msac.w Ry,Rx PSTDDATA = 1 msac.w Ry,Rx,ea,Rw PSTDDATA = 1, {B, source operand} Chapter 5. Debug Support 5-51 Debug C Definition of PSTDDATA Outputs Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Syntax PSTDDATA muls.w <ea>y,Dx PSTDDATA = 1, {9, source operand} mulu.w <ea>y,Dx PSTDDATA = 1, {9, source operand} muls.l <ea>y,Dx PSTDDATA = 1, {B, source operand} mulu.l <ea>y,Dx PSTDDATA = 1, {B, source operand} mvs.b <ea>y,Dx PSTDDATA = 1, {8, source operand} mvs.w <ea>y,Dx PSTDDATA = 1, {9, source operand} mvz.b <ea>y,Dx PSTDDATA = 1, {8, source operand} mvz.w <ea>y,Dx PSTDDATA = 1, {9, source operand} neg.l Dx PSTDDATA = 1 negx.l Dx PSTDDATA = 1 nop PSTDDATA = 1 not.l Dx PSTDDATA = 1 or.l <ea>y,Dx PSTDDATA = 1, {B, source operand} or.l Dy,<ea>x PSTDDATA = 1, {B, source}, {B, destination} ori.l #imm,Dx PSTDDATA = 1 pea <ea>y pulse PSTDDATA = 1, {B, destination operand} PSTDDATA = 4 rems.l <ea>y,Dx:Dw PSTDDATA = 1, {B, source operand} remu.l <ea>y,Dx:Dw PSTDDATA = 1, {B, source operand} rts (not predicted) PSTDDATA=1, {B, source operand}, PSTDDATA=5, {[9AB], target address} rts (predicted) 3 PSTDDATA=1, {B, source operand}, 5 sats.l Dx PSTDDATA = 1 scc Dx PSTDDATA = 1 sub.l <ea>y,Rx PSTDDATA = 1, {B, source operand} sub.l Dy,<ea>x PSTDDATA = 1, {B, source}, {B, destination} subi.l #imm,Dx PSTDDATA = 1 subq.l #imm,<ea>x PSTDDATA = 1, {B, source}, {B, destination} subx.l Dy,Dx PSTDDATA = 1 swap Dx PSTDDATA = 1 tas <ea>x PSTDDATA = 1, {8, source}, {8, destination} trap #imm PSTDDATA = 1 4 tpf PSTDDATA = 1 tpf.w PSTDDATA = 1 tpf.l PSTDDATA = 1 tst.b 5-52 <ea>x PSTDDATA = 1, {8, source operand} MCF5407 User's Manual Debug C Definition of PSTDDATA Outputs Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued) Instruction Syntax PSTDDATA tst.w <ea>x PSTDDATA = 1, {9, source operand} tst.l <ea>x PSTDDATA = 1, {B, source operand} unlk Ax PSTDDATA = 1, {B, destination operand} wddata.b <ea>y PSTDDATA = 4, 8, source operand wddata.w <ea>y PSTDDATA = 4, 9, source operand wddata.l <ea>y PSTDDATA = 4, B, source operand 1 For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi), (d8,PC,Xi). 2 For move multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the address reaches a cache line (0-modulo-16) boundary four or more registers are to be transferred. For these line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value. Automatic line-sized burst transfers maximize performance for these sequential memory accesses. 3 The source operand in predicted RTS is displayed if CSR[12] and/or (CSR[9] or CSR[8]) is set. 4 During normal exception processing, PSTDDATA outputs are driven to 0xC. The exception stack write operands and the vector read and target address of the exception handler may also be displayed. Rn represents any {Dn, An} register. In this definition, the `y' suffix generally denotes the source and `x' denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. Exception Processing PSTDDATA = C,{B, destination},// stack frame {B, destination},// stack frame {B, source},// vector read PSTDDATA = 5,{[9AB], target}// PC of handler The PSTDDATA specification for the reset exception is shown below: Exception Processing PSTDDATA = C, PSTDDATA = 5,{[9AB], target}// initial PC The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated as instruction fetches. For all types of exception processing, the PSTDDATA = 0xC value is driven at all times, unless the PSTDDATA output is needed for one of the optional marker values or for the taken branch indicator (0x5). 5.8.2 Supervisor Instruction Set The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below. Table 5-28 shows the PSTDDATA specification for these opcodes. Chapter 5. Debug Support 5-53 Debug C Definition of PSTDDATA Outputs Table 5-28. PSTDDATA Specification for Supervisor-Mode Instructions Instruction Syntax PSTDDATA cpushl PSTDDATA = 1 halt PSTDDATA = 1, PSTDDATA = F intouch PSTDDATA = 1 move.w SR,Dx move.w {Dy,#imm},SR PSTDDATA = 1, {3} movec Ry,Rc PSTDDATA = 1 rte PSTDDATA = 1 PSTDDATA = 7, {B, source operand}, {3},{B, source operand}, {DD}, PSTDDATA = 5, {[9AB], target address} stop #imm PSTDDATA = 1, PSTDDATA = E wdebug <ea>y PSTDDATA = 1, {B, source, B, source} The move-to-SR and RTE instructions include an optional PSTDDATA = 0x3 value, indicating an entry into user mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled. Similar to the exception processing mode, the stopped state (PSTDDATA = 0xE) and the halted state (PSTDDATA = 0xF) display this status throughout the entire time the ColdFire processor is in the given mode. 5-54 MCF5407 User's Manual Part II System Integration Module (SIM) Intended Audience Part II is intended for users who need to understand the interface between the ColdFire core processor complex, described in Part I, and internal peripheral devices, described in Part III. It includes a general description of the SIM and individual chapters that describe components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt controller for both on-chip and external peripherals, configuration and operation of chip selects, and the SDRAM controller. Contents Part II contains the following chapters: * * * * * * Chapter 6, "SIM Overview," describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5407. Chapter 7, "Phase-Locked Loop (PLL)," describes configuration and operation of the PLL module. It describes in detail the registers and signals that support the PLL implementation. Chapter 8, "I2C Module," describes the MCF5407 I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides extensive programming examples. Chapter 9, "Interrupt Controller," describes operation of the interrupt controller portion of the SIM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. Chapter 10, "Chip-Select Module," describes the MCF5407 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers. Chapter 11, "Synchronous/Asynchronous DRAM Controller Module," describes configuration and operation of the synchronous/asynchronous DRAM controller component of the SIM. It begins with a general description and brief glossary, and Part II. System Integration Module (SIM) II-i includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. Suggested Reading The following literature may be helpful with respect to the topics in Part II: The I2C Bus Specification, Version 2.1 (January 2000) * Acronyms and Abbreviations Table II-i contains acronyms and abbreviations are used in Part II. Table II-i. Acronyms and Abbreviated Terms Term Meaning ADC Analog-to-digital conversion BDM Background debug mode CODEC Code/decode DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing EDO Extended data output (DRAM) FIFO First-in, first-out GPIO General-purpose I/O I2C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council LIFO Last-in, first-out LRU Least recently used LSB Least-significant byte lsb Least-significant bit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex II-ii MCF5407 User's Manual Table II-i. Acronyms and Abbreviated Terms (Continued) Term Meaning NOP No operation PCLK Processor clock PLL Phase-locked loop POR Power-on reset Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part II. System Integration Module (SIM) II-iii II-iv MCF5407 User's Manual Chapter 6 SIM Overview This chapter provides detailed operation information regarding the system integration module (SIM). It describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5407. 6.1 Features The SIM, shown in Figure 6-1, provides overall control of the bus and serves as the interface between the ColdFire core processor complex and the internal peripheral devices. CLKIN (to on-chip peripherals) V4 COLDFIRE PROCESSOR COMPLEX CLKIN PLL Xn RSTI PCLK RSTO DMA SYSTEM INTEGRATION MODULE (SIM) PLL Control PLL System Control RSR SWIVR Base Address Bus Master Park Parallel Port MBAR MPARK PAR Software Watchdog SYPCR SWSR DRAM Controller Chip Select Module DRAM Control DCR External Bus Interface 8 8 8 CSARs CSCRs CSMRs Interrupt Controller I2C Module 10 ICRs Two UARTs IRQPAR IPR Addr/Cntrl Mask DACR0/1 IMR DMR0/1 AVR 8 DRAM Controller Outputs Four Channels CS[7:0] 32-Bit Data Bus 32-Bit Address Bus Two GeneralPurpose Timers 4 IRQ[1,3,5,7] Control Signals Figure 6-1. SIM Block Diagram Chapter 6. SIM Overview 6-1 Features The following is a list of the key SIM features: * * * * * * * 6-2 Module base address register (MBAR) -- Base address location of all internal peripherals and SIM resources -- Address space masking to internal peripherals and SIM resources Phase-locked loop (PLL) clock control register (PLLCR) for CPU STOP instruction -- Control for turning off clocks to core and interrupt levels that turn clocks back on Chapter 7, "Phase-Locked Loop (PLL)." Interrupt controller -- Programmable interrupt level (1-7) for internal peripheral interrupts -- Programmable priority level (0-3) within each interrupt level -- Four external interrupts; one set to interrupt level 7; three others programmable to two interrupt levels See Chapter 9, "Interrupt Controller." Chip select module -- Eight independent, user-programmable chip-select signals (CS[7:0]) that can interface with SRAM, PROM, EPROM, EEPROM, Flash, and peripherals -- Address masking for 64-Kbyte to 4-Gbyte memory block sizes -- Programmable wait states and port sizes -- External master access to chip selects See Chapter 10, "Chip-Select Module." System protection and reset status -- Reset status indicating the cause of last reset -- Software watchdog timer with programmable secondary bus monitor See Section 6.2.4, "Software Watchdog Timer." Pin assignment register (PAR) configures the parallel port. See Section 6.2.9, "Pin Assignment Register (PAR)." Bus arbitration -- Default bus master park register (MPARK) controls internal and external bus arbitration and enables display of internal accesses on the external bus for debugging -- Supports several arbitration algorithms See Section 6.2.10, "Bus Arbitration Control." MCF5407 User's Manual Programming Model 6.2 Programming Model The following sections describe the registers incorporated into the SIM. 6.2.1 SIM Register Memory Map Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM are memory-mapped registers offset from the MBAR address pointer defined in MBAR[BA]. This supervisor-level register is described in Section 6.2.2, "Module Base Address Register (MBAR)." Because SIM registers depend on the base address defined in MBAR[BA], MBAR must be programmed before SIM registers can be accessed. NOTE: Although external masters cannot access the MCF5407's on-chip memories or MBAR, they can access any of the SIM memory map and peripheral registers, such as those belonging to the interrupt controller, chip-select module, UARTs, timers, DMA, and I2C. Table 6-1. SIM Registers MBAR Offset 0x000 0x004 [31:24] [23:16] [15:8] [7:0] Reset status register (RSR) [p. 6-5] System protection control register (SYPCR) [p. 6-8] Software watchdog interrupt vector register (SWIVR) [p. 6-9] Software watchdog service register (SWSR) [p. 6-9] Interrupt port assignment register (IRQPAR) [p. 9-7] Reserved Pin assignment register (PAR) [p. 6-10] 0x008 PLL control (PLLCR) [p. 7-3] Reserved 0x00C Default bus master park register (MPARK) [p. 6-11] Reserved 0x010- 0x03C Reserved Interrupt Controller Registers [p. 9-2] 0x040 Interrupt pending register (IPR) [p. 9-6] 0x044 Interrupt mask register (IMR) [p. 9-6] 0x048 Reserved Autovector register (AVR) [p. 9-5] Interrupt Control Registers (ICRs) [p. 9-3] Chapter 6. SIM Overview 6-3 Programming Model Table 6-1. SIM Registers (Continued) MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x04C Software watchdog timer (ICR0) [p. 9-3] Timer0 (ICR1) [p. 9-3] Timer1 (ICR2) [p. 9-3] I2C (ICR3) [p. 9-3] 0x050 UART0 (ICR4) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA1 (ICR7) [p. 9-3] 0x054 DMA2 (ICR8) [p. 9-3] DMA3 (ICR9) [p. 9-3] Reserved 6.2.2 Module Base Address Register (MBAR) The supervisor-level MBAR, Figure 6-2, specifies the base address and allowable access types for all internal peripherals. It is written with a MOVEC instruction using the CPU address 0xC0F. (See the ColdFire Family Programmer's Reference Manual.) MBAR can be read or written through the debug module as a read/write register, as described in Chapter 5, "Debug Support." Only the debug module can read MBAR. The valid bit, MBAR[V], is cleared at system reset to prevent incorrect references before MBAR is written; other MBAR bits are uninitialized at reset. To access internal peripherals, write MBAR with the appropriate base address (BA) and set MBAR[V] after system reset. All internal peripheral registers occupy a single relocatable memory block along 4-Kbyte boundaries. If MBAR[V] is set, MBAR[BA] is compared to the upper 20 bits of the full 32-bit internal address to determine if an internal peripheral is being accessed. MBAR masks specific address spaces using the address space fields. Attempts to access a masked address space generate an external bus access. Addresses hitting overlapping memory spaces take the following priority: 1. MBAR 2. SRAM and caches 3. Chip select NOTE: The MBAR region must be mapped to non-cacheable space. Attribute Mask Bits 31 Field Reset R/W Address 12 11 10 9 BA -- 8 7 6 5 3 2 Undefined W (supervisor only); R/W through debug module (only the debug module can read MBAR) CPU + 0x0C0F Figure 6-2. Module Base Address Register (MBAR) 6-4 4 MCF5407 User's Manual 1 0 WP -- AM C/I SC SD UC UD V 0 Programming Model Table 6-2 describes MBAR fields. Table 6-2. MBAR Field Descriptions Bits Field 31-12 BA 11-9 -- 8 WP Description Base address. Defines the base address for a 4-Kbyte address range. Reserved, should be cleared. Write protect. Mask bit for write cycles in the MBAR-mapped register address range. 0 Module address range is read/write. 1 Module address range is read only. 7 -- Reserved, should be cleared. 6 AM Alternate master mask. When AM = 0 and an alternate master (external master or DMA) accesses MBAR-mapped registers, MBAR[SC,SD,UC,UD] are ignored in address decoding. These fields mask address space, placing the MBAR-mapped register in a specific address space or spaces. 5 C/I Mask CPU space and interrupt acknowledge cycles. 0 Activates the corresponding MBAR-mapped register 1 Regular external bus access 4 SC Setting masks supervisor code space in MBAR address range 3 SD Setting masks supervisor data space in MBAR address range 2 UC Setting masks user code space in MBAR address range 1 UD 0 V Setting masks user data space in MBAR address range Valid. Determines whether MBAR settings are valid. 0 MBAR contents are invalid. 1 MBAR contents are valid. The following example shows how to set the MBAR to location 0x1000_0000 using the D0 register. Setting MBAR[V] validates the MBAR location. This example assumes all accesses are valid: move.1 #0x10000001,DO movec DO,MBAR 6.2.3 Reset Status Register (RSR) The reset status register (RSR), Figure 6-3, contains two status bits, HRST and SWTR. Reset control logic sets one of the bits depending on whether the last reset was caused by an external device asserting RSTI (HRST = 1) or by the software watchdog timer (SWTR = 1). Only one RSR bit can be set at any time. If a reset occurs, reset control logic sets only the bit that indicates the cause of reset. 7 Field HRST Reset R/W Address 1/0 6 5 -- SWTR 4 -- 0 0 1/0 0_0000 Read/Write MBAR + 0x000 Figure 6-3. Reset Status Register (RSR) Chapter 6. SIM Overview 6-5 Programming Model Table 6-3 describes RSR fields. Table 6-3. RSR Field Descriptions Bits Name 7 HRST 6 -- 5 SWTR 4-0 -- Description Hardware or system reset 1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the core processor to take a reset exception. All registers in internal peripherals and the SIM are reset. Reserved, should be cleared. Software watchdog timer reset 1 The last reset was caused by the software watchdog timer. If SYPCR[SWRI] = 1 and the software watchdog timer times out, a hardware reset occurs. Reserved, should be cleared. 6.2.4 Software Watchdog Timer The software watchdog timer prevents system lockup should the software become trapped in loops with no controlled exit. The software watchdog timer can be enabled or disabled through SYPCR[SWE]. If enabled, the watchdog timer requires the periodic execution of a software watchdog servicing sequence. If this periodic servicing action does not occur, the timer times out, resulting in a watchdog timer IRQ or hardware reset with RSTO driven low, as programmed by SYPCR[SWRI]. If the timer times out and the software watchdog transfer acknowledge enable bit (SYPCR[SWTA]) is set, a watchdog timer IRQ is asserted. Note that the software watchdog timer IACK cycle cannot be autovectored. If a software watchdog timer IACK cycle has not occurred after another timeout, SWT TA is asserted in an attempt to terminate the bus cycle and allow the IACK cycle to proceed. The setting of SYPCR[SWTAVAL] indicates that the watchdog timer TA was asserted. Figure 6-4 shows termination of a locked bus. 6-6 MCF5407 User's Manual Programming Model Code in the watchdog timer interrupt handler polls SYPCR[SWTAVAL] to determine if SWT TA was needed. If so, execute code to identify bad address. Code enables software watchdog timer interrupt and SWTA functionality by writing SYPCR. Problem: 1. Watchdog timer times out due to unterminated bus NOTE: The watchdog timer IRQ should be set to the highest level in the system. Software watchdog timer IRQ Timeout 2. Watchdog timer interrupt cannot be serviced due to hung bus cycle. Wait for another timeout before setting SYPCR[SWTA]. 3. TA held until another bus cycle starts Software watchdog timer TA Timeout SYPCR[SWTAVAL] 1 1 SWTAVAL is set if watchdog timer TA is asserted. Watchdog timer IACK cycle Figure 6-4. MCF5407 Embedded System Recovery from Unterminated Access When the watchdog timer times out and SYPCR[SWRI] is programmed for a software reset, an internal reset is asserted and RSR[SWTR] is set. To prevent the watchdog timer from interrupting or resetting, the SWSR must be serviced by performing the following sequence: 1. Write 0x55 to SWSR. 2. Write 0xAA to the SWSR. Both writes must occur in order before the timeout, but any number of instructions or SWSR accesses can be executed between the two writes. This order allows interrupts and exceptions to occur, if necessary, between the two writes. Caution should be exercised when changing SYPCR values after the software watchdog timer has been enabled with the setting of SYPCR[SWE], because it is difficult to determine the state of the watchdog timer while it is running. The countdown value is constantly compared with the timeout period specified by SYPCR[SWP,SWT]. Therefore, altering SWP and SWT improperly causes unpredictable processor behavior. The following steps must be taken to change SWP or SWT: Chapter 6. SIM Overview 6-7 Programming Model 1. 2. 3. 4. Disable the software watchdog timer by clearing SYPCR[SWE]. Reset the counter by writing 0x55 and then 0xAA to SWSR. Update SYPCR[SWT,SWP]. Reenable the watchdog timer by setting SYPCR[SWE]. This can be done in step 3. 6.2.5 System Protection Control Register (SYPCR) The SYPCR, Figure 6-5, controls the software watchdog timer, timeout periods, and software watchdog timer transfer acknowledge. The SYPCR can be read at any time, but can be written only if a software watchdog timer IRQ is not pending. At system reset, the software watchdog timer is disabled. Field 7 6 5 SWE SWRI SWP 4 3 SWT Reset 2 1 0 SWTA SWTAVAL -- 0000_0000 R/W R/W Address MBAR + 0x01 Figure 6-5. System Protection Control Register (SYPCR) Table 6-4 describes SYPCR fields. Table 6-4. SYPCR Field Descriptions Bits Name 7 SWE Software watchdog timer enable 0 Software watchdog timer disabled 1 Software watchdog timer enabled Description 6 SWRI Software watchdog reset/interrupt select 0 If a timeout occurs, the watchdog timer generates an interrupt to the core processor at the level programmed into ICR0[IL]. 1 The software watchdog timer causes soft reset to be asserted for all modules of the part except for the PLL (reset mode selects, such as PP_RESET_SEL or chip-select settings, should not change). 5 SWP Software watchdog prescaler. This bit interacts with SYPCR[SWT]. 0 Software watchdog timer clock not prescaled. 1 Software watchdog timer clock prescaled by 8192. 4-3 SWT Software watchdog timing delay. SWT and SWP select the timeout period for the watchdog timer. At system reset, the software watchdog timer is set to the minimum timeout period. SWP = 0 00 29/system frequency 01 211/system frequency 10 213/system frequency 11 215/system frequency SWP = 1 00 222/system frequency 01 224/system frequency 10 226/system frequency 11 228/system frequency Note that if SWP and SWT are modified to select a new software timeout, the software service sequence must be performed (0x55 followed by 0xAA written to the SWSR) before the new timeout period takes effect. 6-8 MCF5407 User's Manual Programming Model Table 6-4. SYPCR Field Descriptions (Continued) Bits Name Description 2 SWTA Software watchdog transfer acknowledge enable 0 SWTA transfer acknowledge disabled 1 SWTA asserts transfer acknowledge enabled. After one timeout period of the unacknowledged assertion of the software watchdog timer interrupt, the software watchdog transfer acknowledge asserts, which allows the watchdog timer to terminate a bus cycle and allow the IACK to occur. 1 SWTAVAL Software watchdog transfer acknowledge valid 0 SWTA transfer acknowledge has not occurred. 1 SWTA transfer acknowledge has occurred. Write a 1 to clear this flag bit. 6.2.6 Software Watchdog Interrupt Vector Register (SWIVR) The SWIVR, shown in Figure 6-6, contains the 8-bit interrupt vector (SWIV) that the SIM returns during an interrupt-acknowledge cycle in response to a software watchdog timer-generated interrupt. SWIVR is set to the uninitialized vector 0x0F at system reset. 7 Field 0 SWIV Reset 0000_1111 R/W Supervisor write only Address MBAR + 0x002 Figure 6-6. Software Watchdog Interrupt Vector Register (SWIVR) Note that the software watchdog interrupt cannot be autovectored. 6.2.7 Software Watchdog Service Register (SWSR) The SWSR, shown in Figure 6-7, is where the software watchdog timer servicing sequence should be written. To prevent a watchdog timer timeout, the software service sequence must be performed (0x55 followed by 0xAA written to the SWSR). Both writes must be performed in order before the timeout, but any number of instructions or accesses to the SWSR can be executed between the two writes. If the timer has timed out, writing to SWSR does not cancel the interrupt (that is, IPR[SWT] remains set). The interrupt is cancelled (and SWT is cleared) automatically when the IACK cycle is run. 7 0 Field SWSR Reset Undetermined R/W Address Supervisor write only MBAR + 0x003 Figure 6-7. Software Watchdog Service Register (SWSR) Chapter 6. SIM Overview 6-9 Programming Model 6.2.8 PLL Clock Control for CPU STOP Instruction The SIM contains the PLL clock control register, which is described in detail in Section 7.2.4, "PLL Control Register (PLLCR)." PLLCR[ENBSTOP,PLLIPL] are significant to the operation of the SIM, and are described as follows: * * PLLCR[ENBSTOP] must be set for the ColdFire CPU STOP instruction to be acknowledged. This bit is cleared at reset and must be set for the MCF5407 to enter low-power modes. The CPU STOP instruction stops only clocks to the core processor. All internal modules remain clocked and can generate interrupts to restart the ColdFire core. For example, the on-chip timer can be used to interrupt the processor after a given timer countdown. PLLCR[PLLIPL] determines the minimum level at which an interrupt (decoded as an interrupt priority level or IPL) must occur to awaken the PLL. The PLL then turns clocks back on to the core processor and interrupt exception processing takes place. Table 6-5 describes PLLIPL settings to be compared against the interrupt ranges that awaken the core processor from a CPU STOP instruction. Table 6-5. PLLIPL Settings PLLIPL Description 000 Any interrupts can wake core 001 Interrupts 2-7 010 Interrupts 3-7 011 Interrupts 4-7 100 Interrupts 5-7 101 Interrupts 6-7 110 Interrupt 7 only 111 No interrupts can wake core 6.2.9 Pin Assignment Register (PAR) The pin assignment register (PAR), Figure 6-8, allows the selection of pin assignments. 15 14 13 12 11 10 9 8 7 6 Field PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 PAR6 5 4 TIP DREQ0 DREQ1 TM2 A27 A26 A25 PP6 0 PP2 PP7 A24 A28 1 PP5 PP8 PARn = 1 A31 A29 2 PAR2 PAR1 PAR0 PARn = 0 PP15 PP14 PP13 PP12 PP11 PP10 PP9 A30 3 PAR5 PAR4 PAR3 PP4 PP3 PP1 PP0 TM1/ TM0/ TT1 DACK1 DACK0 TT0 Reset Determined by driving D4/ADDR_CONFIG with a 1 or 0 when RSTI negates. The system is configured as PP[15:0] if D4 is low; otherwise alternate pin functions selected by PAR = 1 are used. R/W Address R/W Address MBAR + 0x004 Figure 6-8. Pin Assignment Register (PAR) 6-10 MCF5407 User's Manual Programming Model 6.2.10 Bus Arbitration Control This section describes the bus arbitration register and the four arbitration schemes. 6.2.10.1 Default Bus Master Park Register (MPARK) The MPARK, shown in Figure 6-9, determines the default bus master arbitration between internal transfers (core and DMA module) and between internal and external transfers to internal resources. This arbitration is needed because external masters can access internal registers within the MCF5407 peripherals. 7 Field 6 PARK 5 4 3 2 IARBCTRL EARBCTRL SHOWDATA Reset 0 -- 0000_0000 R/W R/W Address MBAR + 0x0C Figure 6-9. Default Bus Master Register (MPARK) Table 6-6 describes MPARK bits. Table 6-6. MPARK Field Descriptions Bits Name Description 7-6 PARK 5 IARBCTRL 4 EARBCTRL External bus arbitration control. Enables internal register memory space to external bus arbitration. Internal registers are those accessed at offsets to the MBAR. These include the SIM, DMA, chip selects, timers, UARTs, I2C, and parallel port registers. These registers do not include the MBAR; only the core can access the MBAR. 0 Arbitration disabled 1 Arbitration enabled The use of this field is described in detail in Section 6.2.10.1.2, "Arbitration between Internal and External Masters for Accessing Internal Resources." Park. Indicates the arbitration priority of internal transfers among MCF5407 resources. 00 Round-robin between DMA and ColdFire core 01 Park on master ColdFire core 10 Park on master DMA module 11 Park on current master Use of this field is described in detail in Section 6.2.10.1.1, "Arbitration for Internally Generated Transfers (MPARK[PARK])." Internal bus arbitration control. Controls external device access to the MCF5407 internal bus. 0 Arbitration disabled (single-master system) 1 Arbitration enabled. IARBCTRL must be set if external masters are using internal resources like the DRAM controller or chip selects. Use of this bit depends on whether the system has single or multiple masters, as follows: * In a single-master system, IARBCTRL should stay cleared, disabling internal arbitration by external masters. In this scenario, MPARK[PARK] applies only to priority of internal masters over one another. Note that the internal DMA (master 3) has priority over the ColdFire core (master 2), if internal DMA bandwidth is at its maximum (BWC = 000). * In multiple master systems that expect to use internal resources like the DRAM controller or chip selects, internal arbitration should be enabled. The external master defaults to the highest priority internal master anytime BG is negated. Chapter 6. SIM Overview 6-11 Programming Model Table 6-6. MPARK Field Descriptions (Continued) Bits 3 2-0 Name Description SHOWDATA Enable internal register data bus to be driven on external bus. EARBCTRL must be set for this function to work. Section 6.2.10.1.2, "Arbitration between Internal and External Masters for Accessing Internal Resources," describes the proper use of SHOWDATA. 0 Do not drive internal register data bus values to external bus. 1 Drive internal register data bus values to external bus. -- Reserved, should be cleared. 6.2.10.1.1 Arbitration for Internally Generated Transfers (MPARK[PARK]) MPARK[PARK] prioritizes internal transfers, which can be initiated by the core and the on-chip DMA module, which contains all four DMA channels. Priority among the four DMA channels in the module is determined by the BWC bits in their respective DMA control registers (see Chapter 12, "DMA Controller Module"). The four arbitration schemes for internally generated transfers are described as follows: * Round-robin scheme (PARK = 00)--Figure 6-10 shows round-robin arbitration between the core and DMA module. Bus mastership alternates between the core and DMA module. Internal Bus Mastership (Alternates between Core and DMA Module) DMA MODULE CORE 5th 3rd 1st 4th 2nd Channel 0 Channel 1 Channel 2 Channel 3 Figure 6-10. Round Robin Arbitration (PARK = 00) The DMA module presents only the highest-priority DMA request, and bus mastership alternates between the core and DMA channel as long as both are requesting bus mastership. Section 12.5.4.1, "External Request and Acknowledge Operation," includes a timing diagram showing a lower-priority DMA transfer. When the processor is initialized, the core has first priority. If DMA channels 0 and 1 (both set to BWC = 010) assert an internal bus request during a core-generated bus transfer, DMA channel 0 would gain bus mastership next. However, if the core requests the bus during this DMA transfer, bus mastership returns to the core rather than being granted to DMA channel 1. Note that the internal DMA has higher priority than the core if the internal DMA has its bandwidth BWC bits set to 000 (maximum bandwidth). 6-12 MCF5407 User's Manual Programming Model * Park on master core priority (PARK = 01)--The core retains bus mastership as long as it needs it. After it negates its internal bus request, the core does not have to rearbitrate for the bus unless the DMA module has requested the bus when it is idle. The DMA module can be granted bus mastership only when the core is not asserting its bus request. See Figure 6-11. Core BR negated DMA module BR asserted Core BR negated DMA module BR negated DMA Module Core Core BR asserted DMA module BR negated/asserted Figure 6-11. Park on Master Core Priority (PARK = 01) * Park on master DMA priority (PARK = 10)--The DMA module retains bus mastership as long as it needs it. After it negates its internal bus request, the DMA module does not have to rearbitrate for the bus unless the core has requested the bus when it is idle. The core can be granted bus mastership only when the DMA module is not asserting its bus request. See Figure 6-12. DMA module BR asserted Core BR negated/asserted Core DMA BR negated Core BR negated DMA Module Core BR asserted DMA module BR negated Figure 6-12. Park on DMA Module Priority (PARK = 10) Chapter 6. SIM Overview 6-13 Programming Model * Park on current master priority (PARK = 11)--The current bus master retains mastership as long as it needs the bus. The other device can become the bus master only when the bus is idle. For example, if the core is bus master out of reset, it retains mastership as long as it needs the bus. It loses mastership only when it negates its bus request signal and the DMA asserts its internal bus request signal. At this point the DMA module is the bus master, and retains bus mastership as long as it needs the bus. See Figure 6-13. DMA module BR asserted Core BR negated Core BR negated DMA module BR negated Core Core BR asserted DMA module BR asserted DMA module BR negated Core BR negated DMA Module Core BR asserted DMA module BR negated DMA module BR asserted Core BR asserted Figure 6-13. Park on Current Master Priority (PARK = 01) 6.2.10.1.2 Arbitration between Internal and External Masters for Accessing Internal Resources If an external device is programmed to access internal MCF5407 resources (EARBCTRL = 1), the external device can gain bus mastership only when BG is negated. This means neither the core nor the DMA controller can access the external bus until the external device asserts BG. After the external master finishes its bus transfer and asserts BG, the core has priority on the next available bus cycle regardless of the value of PARK. Thus if the core asserts its internal bus request on this first bus cycle, it executes a bus cycle even if PARK indicates the DMA should have priority. Then, after the bus transfer, the PARK scheme returns to programmed functioning and the DMA is given bus mastership. NOTE: In all arbitration modes, if BG is negated, the external master interface has highest priority. In this case, the ColdFire core has second-highest priority, until the internal bus grant is asserted. * 6-14 In a single-master system, the setting of EARBCTRL does not affect arbitration performance. Typically, BG is tied low and the MCF5407 always owns the external bus and internal register transfers are already shown on the external bus. In a system where MCF5407 is the only master, this bit may remain cleared. If the system needs external visibility of the data bus values during internal register transfers for system debugging, both EARBCTRL and SHOWDATA must be set. Note that when an internal register transfer is driven externally, TA becomes an output, which is asserted (normally an input) to prevent external devices and MCF5407 User's Manual Programming Model * memories from responding to internal register transfers that go to the external bus. The AS signal and all chip-select-related strobe signals are not asserted. Do not immediately follow a cycle in which SHOWDATA is set with a cycle using fast termination. In multiple-master systems, disabling arbitration with EARBCTRL allows performance improvement because internal register bus transfer cycles do not interfere with the external bus. Having internal transfers go external may affect performance in two ways: -- If the internal device does not control the bus immediately, the core stalls until it wins arbitration of the external bus. -- If the core wins arbitration instantly, it may kick the external master off of the external bus unnecessarily for a transfer that did not need the external bus. For debug, where this performance penalty is not a concern, setting EARBCTRL and SHOWDATA provides external visibility of the internal bus cycles. Chapter 6. SIM Overview 6-15 Programming Model 6-16 MCF5407 User's Manual Chapter 7 Phase-Locked Loop (PLL) This chapter describes configuration and operation of the phase-locked loop (PLL) module. It describes in detail the registers and signals that support the PLL implementation. 7.1 Overview The basic features of the MCF5407 PLL implementation are as follows: * * The MCF5407 PLL is enhanced to support faster processor clock (PCLK) frequencies than the MCF5307. It also offers a wider range of clock input ratios. A buffered processor status clock (PSTCLK) is half the PCLK frequency, as indicated in Figure 7-1. This signal is made available for system development. The PLL module has the following three modes of operation: * * * Reset mode--In reset mode, the core/bus frequency ratio and other configuration information is sampled. At reset, the PLL asserts the reset out signal, RSTO. Normal mode--During normal operations, the divide ratio is programmed at reset and is clock-multiplied to provide the processor clock frequency. These frequencies are described in the electrical specifications." Reduced-power mode--In reduced-power mode, the high-speed processor core clocks are turned off without losing the register contents so that the system can be reenabled by an unmasked interrupt or reset. Figure 7-1 shows the frequency relationships of PLL module clock signals. z CLKIN (to on-chip peripherals) BCLKO PCLK (to core) CLKIN DIVIDE[2:0] RSTI Debug Module /2 PLL RSTO PSTCLK (= PCLK/2) Figure 7-1. PLL Module Block Diagram Chapter 7. Phase-Locked Loop (PLL) 7-1 PLL Operation Motorola recommends using CLKIN for the system clock. BCLKO is provided only for compatibility with slower MCF5307 designs. Regardless of the CLKIN frequency driven at power-up, CLKIN (and BCLKO) have the same ratio value to the PCLK. Although either signal can be used as a clock reference, CLKIN leaves more room to meet the bus specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN. 7.1.1 PLL:PCLK Ratios The PLL for the MCF5407 is enhanced to support faster processor clock (PCLK) frequencies. While the MCF5307 supports various PCLK frequencies listed in the electrical specifications with a clock input (CLKIN) of 1/2 PCLK, the MCF5407 offers a wider range of clock input ratios and a higher performance processor clock. Like the MCF5307, the MCF5407 samples clock ratio encodings on the lower data bus bits at reset to determine the CLKIN-to-PCLK ratio. These bits are DIVIDE[1:0] on the MCF5307 and are multiplexed with data bits D[1:0]. Because the MCF5407 offers more divide ratio than the MCF5307, three bits, D[2:0]/DIVIDE[2:0], are provided to offer more programming options at reset. Also, note that only specific CLKIN ranges are allowed for each divide ratio on the MCF5407. Table 7-1 shows MCF5407 divide ratio encodings. Table 7-1. Divide Ratio Encodings D[2:0]/DIVIDE[2:0] Multiplier 00x-010 Reserved 011 3 100 4 101 5 110 6 111 Reserved 7.2 PLL Operation The following sections provide detailed information about the three PLL modes. 7.2.1 Reset/Initialization The PLL receives RSTI as an input directly from the pin. Additionally, signals are multiplexed with D[2:0]/DIVIDE[2:0] while RSTI is asserted. These signals are sampled during reset and registered by the PLL on the negation of RSTI to provide initialization information. DIVIDE[2:0] are used by the PLL to set the CLKIN/PCLK ratio. 7.2.2 Normal Mode CLKIN should be used as the system bus clock in 5407 systems. The CLKIN frequency is 7-2 MCF5407 User's Manual PLL Operation multiplied up as determined by the logic level of the multiplexed D[2:0]/DIVIDE[2:0] pins during reset to create PCLK. 7.2.3 Reduced-Power Mode The PCLK can be turned off in a predictable manner to conserve system power. To allow fast restart of the MCF5407 processor core, the PLL continues to operate at the frequency configured at reset. PCLK is disabled using the CPU STOP instruction and resumes normal operation on interrupt, as described in Section 7.2.4, "PLL Control Register (PLLCR)." 7.2.4 PLL Control Register (PLLCR) The PLL control register (PLLCR), Figure 7-2, provides control over the PLL. 7 6 Field ENBSTOP 5 PLLIPL Reset 4 3 2 DISBCLKO 1 0 -- 0000_0000 R/W R/W Address MBAR + 0x08 Figure 7-2. PLL Control Register (PLLCR) Table 7-2 describes PLLCR bits. Table 7-2. PLLCR Field Descriptions Bit Name Description 7 ENBSTOP Enable CPU STOP instruction. Must be set for the ColdFire CPU STOP instruction to be acknowledged. Cleared at reset and must be subsequently set for the processor to enter low-power modes. Only clocks to the core are turned off because of the CPU STOP instruction. Internal modules remain clocked and can generate interrupts to restart the ColdFire core. 0 Disable CPU STOP 1 Enable CPU STOP; STOP instruction turns off clocks to the ColdFire core. 6-4 PLLIPL PLL interrupt priority level to wake up from CPU STOP. Determines the minimum level an interrupt (decoded as an interrupt priority level) must be to waken the PLL. The PLL then turns clocks back on to the core processor and interrupt exception processing occurs. 000 Any interrupts can wake core 001 Interrupts 2-7 010 Interrupts 3-7 011 Interrupts 4-7 100 Interrupts 5-7 101 Interrupts 6-7 110 Interrupt 7 only 111 No interrupts can wake core. Any reset, including a watchdog reset, can wake the core. No PLL phase lock time is required. 3 2-0 DISBCLKO BCLKO disable. Determines whether BCLKO is driven. 0 BCLKO is driven. 1 BCLKO is three-stated. BCLKO can be reenabled only by a reset. -- Reserved, should be cleared. Chapter 7. Phase-Locked Loop (PLL) 7-3 PLL Port List 7.3 PLL Port List Table 7-3 describes PLL module inputs. Table 7-3. PLL Module Input SIgnals SIgnal Description CLKIN Input clock to the PLL. Input frequency must not be changed during operation. Changes are recognized only at reset. RSTI Active-low asynchronous input that, when asserted, indicates PLL is to enter reset mode. As long as RSTI is asserted, the PLL is held in reset and does not begin to lock. DIVIDE[2:0] TheMCF5407 samples clock ratio encodings on the lower data bits of the bus to determine the CLKIN-to-processor clock ratio. D[2:0]/DIVIDE[2:0] support the divide-ratio combinations. Note that only specific CLKIN ranges are allowed for each divide ratio on the MCF5407. See the electrical specifications for valid frequencies. Table 7-4 describes PLL module outputs. Table 7-4. PLL Module Output Signals Output Description BCLKO This bus clock output provides a divided version of the processor clock frequency, determined by DIVIDE[2:0]. BCLKO is provided for MCF5307 compatibility (slower-speed designs). PSTCLK Provides a buffered processor status clock. PSTCLK is half the frequency of PCLK. See Section 7.4.1, "PCLK, PSTCLK, and BCLKO," and Figure 7-1. RSTO This output provides an external reset for peripheral devices. 7.4 Timing Relationships The MCF5407 CLKIN frequency can be 1/3, 1/4, 1/5, or 1/6 the processor clock. In this document, bus timings are referenced from CLKIN. Regardless of the CLKIN frequency driven at power-up, CLKIN and BCLKO have the same ratio value to the PCLK. Although either signal can be used as a clock reference, CLKIN leaves more room to meet the bus specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN. Although the CLKIN duty cycle remains the same for the MCF5307 and MCF5407, caution should be used when interfacing signals on the falling edge of CLKIN with only a 4-nS window to work from at high frequencies. Also, note that the MCF5407 CLKIN rise time is reduced to 2 nS (5 nS in the MCF5307). If signals are referenced from CLKIN only, setting PLLCR[DISBCLKO] and disabling BCLKO reduces power consumption. See Section 7.2.4, "PLL Control Register (PLLCR)." 7.4.1 PCLK, PSTCLK, and BCLKO Figure 7-3 shows the frequency relationships between PCLK, PSTCLK, and the four 7-4 MCF5407 User's Manual Timing Relationships possible versions of CLKIN/BCLKO. This figure does not show the skew between CLKIN and PCLK, PSTCLK, and BCLKO. PSTCLK is half the frequency of PCLK. Similarly, the skew between PCLK and BCLKO is unspecified. PCLK PSTCLK CLKIN/BCLKO (/3) CLKIN/BCLKO (/4) CLKIN/BCLKO (/5) CLKIN/BCLKO (/6) NOTE: The clock signals are shown with edges aligned to show frequency relationships only. Actual signal edges have some skew between them. Figure 7-3. CLKIN, PCLK, PSTCLK, and BCLKO Timing 7.4.2 RSTI Timing Figure 7-4 shows PLL timing during reset. As shown, RSTI must be asserted for at least 16 CLKIN cycles to give the MCF5407 time to begin its initialization sequence. At this time, the configuration pins should be asserted (D[2:0] for DIVIDE[2:0]), meeting the minimum setup and hold times to RSTI given in Chapter 20, "Electrical Specifications." On the rising edge of CLKIN before the rising edge of RSTI, the data on D[7:0] is latched and the PLL begins ramping to its final operating frequency. During this ramp and lock time, BCLKO and PSTCLK are held low. The PLL locks in about 2 mS or less depending on the CLKIN frequency, at which time BCLKO begins normal operation in the specified mode. The PLL requires 50,000 CLKIN cycles to guarantee PLL lock. To allow for reset of external peripherals requiring a clock source, RSTO remains asserted for a number of CLKIN cycles, as shown in Figure 7-4. PSTCLK will begin oscillating a minimum of10 clock cycles after RSTO is negated. Chapter 7. Phase-Locked Loop (PLL) 7-5 PLL Power Supply Filter Circuit 50K CLKIN Cycle Lock Time >16 CLKS >10 CLKS CLKIN BCLKO PSTCLK RSTI D[7:0] D[7:0] latched on rising edge of CLKIN RSTO Figure 7-4. Reset and Initialization Timing 7.5 PLL Power Supply Filter Circuit To ensure PLL stability, the power supply to the PLL power pin should be filtered using a circuit similar to the one in Figure 7-5. The circuit should be placed as close as possible to the PLL power pin to ensure maximum noise filtering. 10 Vdd PLL power pin 10 F 0.1 F Figure 7-5. PLL Power Supply Filter Circuit 7-6 MCF5407 User's Manual Chapter 8 I2C Module This chapter describes the MCF5407 I2C module, including I2C protocol, clock synchronization, and the registers in the I2C programing model. It also provides extensive programming examples. 8.1 Overview I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development. The I2C system is a true multiple-master bus including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. Note that I2C is defined for 5-V operation and the MCF5407 is a 3.3-V device. Care must be taken to interface to 5-V peripherals. 8.2 Interface Features The I2C module has the following key features: * * * * * * * * Compatibility with I2C bus standard Support for 3.3-V tolerant devices Multiple-master operation Software-programmable for one of 64 different serial clock frequencies Software-selectable acknowledge bit Interrupt-driven, byte-by-byte data transfer Arbitration-lost interrupt with automatic mode switching from master to slave Calling address identification interrupt Chapter 8. I2C Module 8-1 Interface Features * * * * Start and stop signal generation/detection Repeated START signal generation Acknowledge bit generation/detection Bus-busy detection Figure 8-1 is a block diagram of the I2C module. Internal Bus IRQ Address Data Address Decode Data MUX I2C Data I/O Register (I2DR) I2C Address Register (IADR) Registers and ColdFire Interface I2C Frequency Divider Register (IFDR) I2C Control Register (I2CR) I2C Status Register (I2SR) Clock Control Start, Stop, and Arbitration Control Input Sync In/Out Data Shift Register Address Compare SCL SDA Figure 8-1. I2C Module Block Diagram Figure 8-1 shows the relationships of the I2C registers, listed below: * I2C address register (IADR) 8-2 * I2C frequency divider register (IFDR) * I2C control register (I2CR) * I2C status register (I2SR) * I2C data I/O register (I2DR) MCF5407 User's Manual I2C System Configuration These registers are described in Section 8.5, "Programming Model." 8.3 I2C System Configuration The I2C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. For I2C compliance, all devices connected to these two signals must have open drain or open collector outputs. (There is no such requirement for inputs.) The logic AND function is exercised on both lines with external pull-up resistors. Out of reset, the I2C default is as slave receiver. Thus, when not programmed to be a master or responding to a slave transmit address, the I2C module should return to the default slave receiver state. See Section 8.6.1, "Initialization Sequence," for exceptions. NOTE: The I2C module is designed to be compatible with the Philips I2C bus protocol. For information on system configuration, protocol, and restrictions, see The I2C Bus Specification, Version 2.1. 8.4 I2C Protocol Normally, a standard communication is composed of the following parts: 1. START signal--When no other device is bus master (both SCL and SDA lines are at logic high), a device can initiate communication by sending a START signal (see A in Figure 8-2). A START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves. msb SCL SDA A 1 lsb 2 3 4 5 6 7 8 msb 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START Signal Calling Address B R/W ACK Bit C D 1 XXX lsb 2 3 D7 D6 D5 E 4 5 6 7 8 9 D4 D3 D2 D1 D0 Data Byte No STOP ACK Signal Bit F Figure 8-2. I2C Standard Communication Protocol 2. Slave address transmission--The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave data transfer direction. Chapter 8. I2C Module 8-3 I2C Protocol Each slave must have a unique address. An I2C master must not transmit an address that is the same as its slave address; it cannot be master and slave at the same time. The slave whose address matches that sent by the master pulls SDA low at the ninth clock (D) to return an acknowledge bit. 3. Data transfer--When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master. Data can be changed only while SCL is low and must be held stable while SCL is high, as Figure 8-2 shows. SCL is pulsed once for each data bit, with the msb being sent first. The receiving device must acknowledge each byte by pulling SDA low at the ninth clock; therefore, a data byte transfer takes nine clock pulses. If it does not acknowledge the master, the slave receiver must leave SDA high. The master can then generate a STOP signal to abort the data transfer or generate a START signal (repeated start, shown in Figure 8-3) to start a new calling sequence. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave. The slave releases SDA for the master to generate a STOP or START signal. 4. STOP signal--The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is at logical high (F). Note that a master can generate a STOP even if the slave has made an acknowledgment, at which point the slave must release the bus. Instead of signalling a STOP, the master can repeat the START signal, followed by a calling command, (A in Figure 8-3). A repeated START occurs when a START signal is generated without first generating a STOP signal to end the communication. msb SCL SDA 1 lsb 2 3 4 5 6 7 8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START Signal Calling Address lsb msb 9 1 XX 2 3 4 5 6 7 8 9 AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W R/W ACK Repeated Bit START Signal A New Calling Address Stop R/W No ACK Bit STOP Signal Figure 8-3. Repeated START The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 8.4.1 Arbitration Procedure If multiple devices simultaneously request the bus, the bus clock is determined by a 8-4 MCF5407 User's Manual I2C Protocol synchronization procedure in which the low period equals the longest clock-low period among the devices and the high period equals the shortest. A data arbitration procedure determines the relative priority of competing devices. A device loses arbitration if it sends logic high while another sends logic low; it immediately switches to slave-receive mode and stops driving SDA. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. 8.4.2 Clock Synchronization Because wire-AND logic is used, a high-to-low transition on SCL affects devices connected to the bus. Devices start counting their low period when the master drives SCL low. When a device clock goes low, it holds SCL low until the clock high state is reached. However, the low-to-high change in this device clock may not change the state of SCL if another device clock is still in its low period. Therefore, the device with the longest low period holds the synchronized clock SCL low. Devices with shorter low periods enter a high wait state during this time (See Figure 8-4). When all devices involved have counted off their low period, the synchronized clock SCL is released and pulled high. There is then no difference between device clocks and the state of SCL, so all of the devices start counting their high periods. The first device to complete its high period pulls SCL low again. Wait Start counting high period SCL1 SCL2 SCL Internal Counter Reset Figure 8-4. Synchronized Clock SCL 8.4.3 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices can hold SCL low after completing one byte transfer (9 bits). In such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases SCL. 8.4.4 Clock Stretching Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave SCL low period is longer than the master SCL low period, Chapter 8. I2C Module 8-5 Programming Model the resulting SCL bus signal low period is stretched. 8.5 Programming Model Table 8-1 lists the configuration registers used in the I2C interface. Table 8-1. I2C Interface Memory Map MBAR Offset [31:24] [23:16] [15:8] 0x280 I2C address register (IADR) [p. 8-6] 0x284 I2C 0x288 I2C control register (I2CR) [p. 8-7] Reserved 0x28C I2C status register (I2SR) [p. 8-8] Reserved 0x290 I2C Reserved [7:0] Reserved frequency divider register (IFDR) [p. 8-6] Reserved data I/O register (I2DR) [p. 8-9] NOTE: External masters cannot access the MCF5407's on-chip memories or MBAR, but can access any I2C module register. 8.5.1 I2C Address Register (IADR) The IADR holds the address the I2C responds to when addressed as a slave. Note that it is not the address sent on the bus during the address transfer. 7 6 5 Field 4 3 2 1 ADR Reset 0000_0000 R/W Read/Write Address 0 -- MBAR + 0x280 Figure 8-5. I2C Address Register (IADR) Table 8-2 describes IADR fields. Table 8-2. I2C Address Register Field Descriptions Bits Name Description 7-1 ADR Slave address. Contains the specific slave address to be used by the I2C module. Slave mode is the default I2C mode for an address match on the bus. 0 -- Reserved, should be cleared. 8.5.2 I2C Frequency Divider Register (IFDR) The IFDR, Figure 8-6, provides a programmable prescaler to configure the clock for 8-6 MCF5407 User's Manual Programming Model bit-rate selection. 7 Field 6 5 4 3 2 -- 1 0 IC Reset 0000_0000 R/W Read/Write Address MBAR + 0x284 Figure 8-6. I2C Frequency Divider Register (IFDR) Table 8-3 describes IFDR[IC]. Table 8-3. IFDR Field Descriptions Bits Name 7-6 -- Reserved, should be cleared. Description 5-0 IC I2C clock rate. Prescales the clock for bit-rate selection. Due to potentially slow SCL and SDA rise and fall times, bus signals are sampled at the prescaler frequency. The serial bit clock frequency is equal to CLKIN divided by the divider shown below. Note that IC can be changed anywhere in a program. IC Divider IC Divider IC Divider IC Divider 0x00 28 0x10 288 0x20 20 0x30 160 0x01 30 0x11 320 0x21 22 0x31 192 0x02 34 0x12 384 0x22 24 0x32 224 0x03 40 0x13 480 0x23 26 0x33 256 0x04 44 0x14 576 0x24 28 0x34 320 0x05 48 0x15 640 0x25 32 0x35 384 0x06 56 0x16 768 0x26 36 0x36 448 0x07 68 0x17 960 0x27 40 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88 0x19 1280 0x29 56 0x39 768 0x0A 104 0x1A 1536 0x2A 64 0x3A 896 0x0B 128 0x1B 1920 0x2B 72 0x3B 1024 0x0C 144 0x1C 2304 0x2C 80 0x3C 1280 0x0D 160 0x1D 2560 0x2D 96 0x3D 1536 0x0E 192 0x1E 3072 0x2E 112 0x3E 1792 0x0F 240 0x1F 3840 0x2F 128 0x3F 2048 8.5.3 I2C Control Register (I2CR) The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern operation as a slave or a master. Chapter 8. I2C Module 8-7 Programming Model Field 7 6 5 4 3 2 IEN IIEN MSTA MTX TXAK RSTA Reset 1 0 -- 0000_0000 R/W Read/Write Address MBAR + 0x288 Figure 8-7. I2C Control Register (I2CR) Table 8-4 describes I2CR fields. Table 8-4. I2CR Field Descriptions Bits Name Description 7 IEN I2C enable. Controls the software reset of the entire I2C module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next start condition is detected. Master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the current master or the I2C module to lose arbitration, after which bus operation returns to normal. 0 The module is disabled, but registers can still be accessed. 1 The I2C module is enabled. This bit must be set before any other I2CR bits have any effect. 6 IIEN I2C interrupt enable. 0 I2C module interrupts are disabled, but currently pending interrupt condition are not cleared. 1 I2C module interrupts are enabled. An I2C interrupt occurs if I2SR[IIF] is also set. 5 MSTA Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal. 0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode. 1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode. 4 MTX Transmit/receive mode select bit. Selects the direction of master and slave transfers. 0 Receive 1 Transmit. When a slave is addressed, software should set MTX according to I2SR[SRW]. In master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1. 3 TXAK Transmit acknowledge enable. Specifies the value driven onto SDA during acknowledge cycles for both master and slave receivers. Note that writing TXAK applies only when the I2C bus is a receiver. 0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. 1 No acknowledge signal response is sent (that is, acknowledge bit = 1). 2 RSTA Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration. 0 No repeat start 1 Generates a repeated START condition. 1-0 -- Reserved, should be cleared. 8.5.4 I2C Status Register (I2SR) This I2SR contains bits that indicate transaction direction and status. 8-8 MCF5407 User's Manual Programming Model Field 7 6 5 4 3 2 1 0 ICF IAAS IBB IAL -- SRW IIF RXAK R/W R Reset R/W 1000_0001 R R R/W Address MBAR + 0x28C Figure 8-8. I2CR Status Register (I2SR) Table 8-5 describes I2SR fields. Table 8-5. I2SR Field Descriptions Bits Name Description 7 ICF Data transferring bit. While one byte of data is transferred, ICF is cleared. 0 Transfer in progress 1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer. 6 IAAS I2C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit. 0 Not addressed. 1 Addressed as a slave. Set when its own address (IADR) matches the calling address. 5 IBB I2C bus busy bit. Indicates the status of the bus. 0 Bus is idle. If a STOP signal is detected, IBB is cleared. 1 Bus is busy. When START is detected, IBB is set. 4 IAL Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing zero to it.) * SDA sampled low when the master drives high during an address or data-transmit cycle. * SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle. * A start cycle is attempted when the bus is busy. * A repeated start cycle is requested in slave mode. * A stop condition is detected when the master did not request it. 3 -- Reserved, should be cleared. 2 SRW Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address sent from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated, and the I2C module is a slave and has an address match. 0 Slave receive, master writing to slave. 1 Slave transmit, master reading from slave. 1 IIF I2C interrupt. Must be cleared by software by writing a zero to it in the interrupt routine. 0 No I2C interrupt pending 1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the following occurs: * Complete one byte transfer (set at the falling edge of the ninth clock) * Reception of a calling address that matches its own specific address in slave-receive mode * Arbitration lost 0 RXAK Received acknowledge. The value of SDA during the acknowledge bit of a bus cycle. 0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 No acknowledge signal was detected at the ninth clock. 8.5.5 I2C Data I/O Register (I2DR) In master-receive mode, reading the I2DR, Figure 8-9, allows a read to occur and initiates Chapter 8. I2C Module 8-9 I2C Programming Examples next byte data receiving. In slave mode, the same function is available after it is addressed. 7 6 5 4 3 Field D Reset 0000_0000 R/W 2 1 0 Read/Write Address MBAR + 0x290 Figure 8-9. I2C Data I/O Register (I2DR) 8.6 I2C Programming Examples The following examples show programming for initialization, signalling START, post-transfer software response, signalling STOP, and generating a repeated START. 8.6.1 Initialization Sequence Before the interface can transfer serial data, registers must be initialized, as follows: 1. Set IFDR[IC] to obtain SCL frequency from the system bus clock. See Section 8.5.2, "I2C Frequency Divider Register (IFDR)." 2. Update the IADR to define its slave address. 3. Set I2CR[IEN] to enable the I2C bus interface system. 4. Modify the I2CR to select master/slave mode, transmit/receive mode, and interrupt-enable or not. NOTE: If IBSR[IBB] when the I2C bus module is enabled, execute the following code sequence before proceeding with normal initialization code. This issues a STOP command to the slave device, placing it in idle state as if it were just power-cycled on. I2CR = 0x0 I2CR = 0xA dummy read of I2DR IBSR = 0x0 I2CR = 0x0 8.6.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. On a multiple-master bus system, IBSR[IBB] must be tested to determine whether the serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the slave address) can be sent. The data written to the data register comprises the address of the desired slave and the lsb indicates the transfer direction. 8-10 MCF5407 User's Manual I2C Programming Examples The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period, it may be necessary to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with the following instructions. The following example signals START and transmits the first byte of data (slave address): CHFLAG MOVE.B I2SR,-(A0);Check I2SR[MBB] BTST.B #5, (A0)+ BNE.S CHFLAG;If I2SR[MBB] = 1, wait until it is clear TXSTART MOVE.B I2CR,-(A0);Set transmit mode BSET.B #4,(A0) MOVE.B (A0)+, I2CR MOVE.B I2CR, -(A0);Set master mode BSET.B #5, (A0);Generate START condition MOVE.B (A0)+, I2CR MOVE.B CALLING,-(A0);Transmit the calling address, D0=R/W MOVE.B (A0)+, I2DR IFREE MOVE.B I2SR,-(A0);Check I2SR[MBB] ;If it is clear, wait until it is set. BTST.B #5, (A0)+; BEQ.S IFREE; 8.6.3 Post-Transfer Software Response Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is finished. I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during initialization by setting I2CR[IIEN]. Software must first clear IIF in the interrupt routine. ICF is cleared either by reading from I2DR in receive mode or by writing to I2DR in transmit mode. Software can service the I2C I/O in the main program by monitoring IIF if the interrupt function is disabled. Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost. When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent. If master receive mode is required (I2DR[R/W], I2CR[MTX] should be toggled. During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the direction of the next transfer. MTX is programmed accordingly. For slave-mode data cycles (IAAS = 0), SRW is invalid. MTX should be read to determine the current transfer direction. The following is an example of a software response by a master transmitter in the interrupt routine (see Figure 8-10). I2SR LEA.L I2SR,-(A7);Load effective address BCLR.B #1,(A7)+;Clear the IIF flag MOVE.B I2CR,-(A7);Push the address on stack, BTST.B #5,(A7)+;check the MSTA flag BEQ.S SLAVE;Branch if slave mode MOVE.B I2CR,-(A7);Push the address on stack BTST.B #4,(A7)+;check the mode flag Chapter 8. I2C Module 8-11 I2C Programming Examples BEQ.S RECEIVE;Branch if in receive mode MOVE.B I2SR,-(A7);Push the address on stack, BTST.B #0,(A7)+;check ACK from receiver BNE.B END;If no ACK, end of transmission TRANSMITMOVE.B DATABUF,-(A7);Stack data byte MOVE.B (A7)+, I2DR;Transmit next byte of data 8.6.4 Generation of STOP A data transfer ends when the master signals a STOP, which can occur after all data is sent, as in the following example. MASTX END MOVE.B I2SR, -(A7);If no ACK, branch to end BTST.B #0,(A7)+ BNE.B END MOVE.B TXCNT,D0;Get value from the transmitting counter BEQ.S END;If no more data, branch to end MOVE.B DATABUF,-(A7);Transmit next byte of data MOVE.B (A7)+,I2DR MOVE.B TXCNT,D0;Decrease the TXCNT SUBQ.L #1,D0 MOVE.B D0,TXCNT BRA.S EMASTX;Exit LEA.L I2CR,-(A7);Generate a STOP condition BCLR.B #5,(A7)+ EMASTX RTE;Return from interrupt For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following example. MASR MOVE.B RXCNT,D0;Decrease RXCNT SUBQ.L #1,D0 MOVE.B D0,RXCNT BEQ.S ENMASR;Last byte to be read MOVE.B RXCNT,D1;Check second-to-last byte to be read EXTB.L D1 SUBI.L #1,D1; BNE.S NXMAR;Not last one or second last LAMAR BSET.B #3,I2CR;Disable ACK BRA NXMAR ENMASR NXMAR BCLR.B #5,I2CR;Last one, generate STOP signal MOVE.B I2DR,RXBUF;Read data and store RTE 8.6.5 Generation of Repeated START After the data transfer, if the master still wants the bus, it can signal another START followed by another slave address without signalling a STOP, as in the following example. RESTART MOVE.B BSET.B MOVE.B MOVE.B MOVE.B MOVE.B 8-12 I2CR,-(A7);Repeat START (RESTART) #2, (A7) (A7)+, I2CR CALLING,-(A7);Transmit the calling address, D0=R/WCALLING,-(A7); (A7)+, I2DR MCF5407 User's Manual I2C Programming Examples 8.6.6 Slave Mode In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS automatically. The only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode releases SCL, allowing the master to send data. In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data. Setting RXAK means an end-of-data signal from the master receiver, after which software must switch it from transmitter to receiver mode. Reading I2DR then releases SCL so that the master can generate a STOP signal. 8.6.7 Arbitration Lost If several devices try to engage the bus at the same time, one becomes master. Hardware immediately switches devices that lose arbitration to slave receive mode. Data output to SDA stops, but SCL is still generated until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] = 1 and I2CR[MSTA] = 0. If a device that is not a master tries to transmit or do a START, hardware inhibits the transmission, clears MSTA without signalling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, the slave service routine should first test IAL and software should clear it if it is set. Chapter 8. I2C Module 8-13 I2C Programming Examples Clear IIF Y TX TX/Rx ? Master Mode? N Y RX Arbitration Lost? N Last Byte Transmitted ? N RXAK= 0 ? Clear IAL Y Last Byte to be Read ? N Y Y N End of ADDR Cycle (Master RX) ? N Write Next Byte to I2DR N Y Y (Read)Y N Data Cycle SRW=1 ? Generate STOP Signal Y Set TX Mode Switch to Rx Mode Generate STOP Signal Tx/Rx ? N (WRITE) N Write Data to I2DR Dummy Read from I2DR IAAS=1 ? Address Y Cycle 2nd Last Byte to be Read? Set TXAK =1 Y IAAS=1 ? Read Data from I2DR And Store TX ACK from Receiver ? N Read Data from I2DR and Store Tx Next Byte Set RX Mode Switch to Rx Mode Dummy Read from I2DR Dummy Read from I2DR RTE Figure 8-10. Flow-Chart of Typical I2C Interrupt Routine 8-14 MCF5407 User's Manual RX Chapter 9 Interrupt Controller This chapter describes the operation of the interrupt controller portion of the system integration module (SIM). It includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. 9.1 Overview The SIM provides a centralized interrupt controller for all MCF5407 interrupt sources, which consist of the following: * * * External interrupts Software watchdog timer Timer modules * * * I2C module UART modules DMA module Figure 9-1 is a block diagram of the interrupt controller. System Integration Module (SIM) DMA Four Channels Interrupt Controller 12 ICRs IRQPAR Software Watchdog I2C Module IPR IMR AVR 4 IRQ[1,3,5,7] Two UARTs Two GeneralPurpose Timers Figure 9-1. Interrupt Controller Block Diagram Chapter 9. Interrupt Controller 9-1 Interrupt Controller Registers The SIM provides the following registers for managing interrupts: * * * * * Each potential interrupt source is assigned one of the 10 interrupt control registers (ICR0-ICR9), which are used to prioritize the interrupt sources. The interrupt mask register (IMR) provides bits for masking individual interrupt sources. The interrupt pending register (IPR) provides bits for indicating when an interrupt request is being made (regardless of whether it is masked in the IMR). The autovector register (AVEC) controls whether the SIM supplies an autovector or executes an external interrupt acknowledge cycle for each IRQ. The interrupt port assignment register (IRQPAR) provides the level assignment of the primary external interrupt pins--IRQ5, IRQ3, and IRQ1. 9.2 Interrupt Controller Registers The interrupt controller register portion of the SIM memory map is shown in Table 9-2. Table 9-1. Interrupt Controller Registers MBAR Offset [31:24] [23:16] [15:8] 0x040 Interrupt pending register (IPR) [p. 9-6] 0x044 Interrupt mask register (IMR) [p. 9-6] 0x048 Reserved [7:0] Autovector register (AVR) [p. 9-5] Interrupt Control Registers (ICRs) [p. 9-3] 0x04C Software watchdog timer (ICR0) [p. 9-3] Timer0 (ICR1) [p. 9-3] Timer1 (ICR2) [p. 9-3] I2C (ICR3) [p. 9-3] 0x050 UART0 (ICR4) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA1 (ICR7) [p. 9-3] 0x054 DMA2 (ICR8) [p. 9-3] DMA3 (ICR9) [p. 9-3] Reserved Each internal interrupt source has its own interrupt control register (ICR0-ICR9), shown in Table 9-2 and described in Section 9.2.1, "Interrupt Control Registers (ICR0-ICR9)." Table 9-2. Interrupt Control Registers 9-2 MBAR Offset Register Name 0x04C ICR0 Software watchdog timer 0x04D ICR1 Timer0 0x04E ICR2 Timer1 0x04F ICR3 I2C 0x050 ICR4 UART0 0x051 ICR5 UART1 0x052 ICR6 DMA0 MCF5407 User's Manual Interrupt Controller Registers Table 9-2. Interrupt Control Registers (Continued) MBAR Offset Register Name 0x053 ICR7 DMA1 0x054 ICR8 DMA2 0x055 ICR9 DMA3 Internal interrupts are programmed to a level and priority. Each internal interrupt has a unique ICR. Each of the 7 interrupt levels has 5 priorities, for a total of 35 possible priority levels, encompassing internal and external interrupts. The four external interrupt pins offer seven possible settings at a fixed interrupt level and priority. The IRQPAR determines these settings for external interrupt request levels. External interrupts can be programmed to supply an autovector or execute an external interrupt acknowledge cycle. This is described in Section 9.2.2, "Autovector Register (AVR)." 9.2.1 Interrupt Control Registers (ICR0-ICR9) The interrupt control registers (ICR0-ICR9) provide bits for defining the interrupt level and priority for the interrupt source assigned to the ICR, shown in Table 9-2. 7 6 5 Field AVEC -- Reset 0 -- R/W Address 4 3 2 1 0 IL IP 0_00 00 R/W MBAR + 0x04C (ICR0); 0x04D (ICR1); 0x04E (ICR2); 0x04F (ICR3); 0x050 (ICR4); 0x051 (ICR5); 0x052 (ICR6); 0x053 (ICR7); 0x054 (ICR8); 0x055 (ICR9) Figure 9-2. Interrupt Control Registers (ICR0-ICR9) Table 9-3 describes ICR fields. Table 9-3. ICRn Field Descriptions Bits Field Description 7 AVEC Autovector enable. Determines whether the interrupt-acknowledge cycle input (for the internal interrupt level indicated in IL for each interrupt) requires an autovector response. 0 Interrupting source returns vector during interrupt-acknowledge cycle. 1 SIM generates autovector during interrupt acknowledge cycle. 6-5 -- Reserved, should be cleared. 4-2 IL Interrupt level. Indicates the interrupt level assigned to each interrupt input. See Table 9-4. 1-0 IP Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level assignment. See Table 9-4. 00 Lowest 01 Low 10 High 11 Highest Chapter 9. Interrupt Controller 9-3 Interrupt Controller Registers NOTE: Assigning the same interrupt level and priority to multiple ICRs causes unpredictable system behavior. Table 9-4 shows possible priority schemes for internal and external sources of the MCF5407. The internal module interrupt source in this table can be any internal interrupt source programmed to the given level and priority. This table shows how external interrupts are prioritized with respect to internal interrupt sources within the same level. For example, UART0 and UART1 sources are programmed to IL = 110; in this case, UART0 is given lower priority than UART1, so ICR4[IP] = 01 and the ICR5[IP] = 10. IRQ3 is programmed to level 6. If all three assert an interrupt request at the same time, they are serviced in the following order: 1. ICR5[IL] = 110 and ICR5[IP] = 10, so UART1 is serviced first (priority 7 in Table 9-4). 2. External interrupt IRQ3, set to level 6, is serviced next (priority 8). 3. ICR4[IL] = 110 and ICR5[IP] = 01, so UART0 is serviced last (priority 9). Table 9-4. Interrupt Priority Scheme Priority 1 Interrupt Level 7 2 Interrupt Source IL IRQPAR[IRQPAR] IP 111 11 111 10 Internal module xxx xxx 3 xxx xx External interrupt pin IRQ7 xxx 4 111 01 Internal module xxx 5 111 00 6 6 7 110 11 110 10 xxx Internal module xxx xx External interrupt pin IRQ3 (programmed as IRQ6) 9 110 01 Internal module 10 110 00 12 5 101 11 101 10 xxx xxx 8 11 9-4 ICR x1x xxx xxx Internal module xxx xxx 13 xxx xx External interrupt pin IRQ5 14 101 01 Internal module 15 101 00 0xx xxx xxx MCF5407 User's Manual Interrupt Controller Registers Table 9-4. Interrupt Priority Scheme (Continued) Priority ICR Interrupt Level 16 Interrupt Source IL 4 17 IRQPAR[IRQPAR] IP 100 11 100 10 Internal module xxx xxx 18 xxx xx External interrupt pin IRQ5 (programmed as IRQ4) 1xx 19 100 01 Internal module xxx 100 00 011 11 011 10 20 21 3 22 xxx Internal module xxx xxx 23 xxx xx External interrupt pin IRQ3 x0x 24 011 01 Internal module xxx 011 00 010 11 010 10 25 26 2 27 xxx Internal module xxx xxx 28 xxx xx External interrupt pin IRQ1 (programmed as IRQ2) xx1 29 010 01 Internal module xxx 010 00 001 11 001 10 30 31 1 32 xxx Internal module xxx xxx 33 xxx xx External interrupt pin IRQ1 xx0 34 001 01 Internal module xxx 35 001 00 xxx 9.2.2 Autovector Register (AVR) The autovector register (AVR), shown in Figure 9-3, enables external interrupt sources to be autovectored, using the vector offset defined in Table 2-19 in Section 2.8, "Exception Processing Overview." Note that the autovector enable for internal interrupt sources applies for respective ICRs. 7 6 5 Field 4 3 2 AVEC Reset 1 0 BLK 0000_0000 R/W R/W Address MBAR + 0x04B Figure 9-3. Autovector Register (AVR) Table 9-5 describes AVR fields. Chapter 9. Interrupt Controller 9-5 Interrupt Controller Registers . Table 9-5. AVR Field Descriptions Bit Name 7-1 AVEC Autovector control. Determines whether the external interrupt at that level is autovectored. 0 Interrupting source returns vector during interrupt-acknowledge cycle. 1 SIM generates autovector during interrupt-acknowledge cycle. 0 BLK Description Block address strobe (AS) for external AVEC access. Available for users who use AS as a global chip select for peripherals and do not want to enable them during an AVEC cycle. 0 Do not block address strobe. 1 Block address strobe from asserting. Table 9-6 shows the correlation between AVR[AVEC] and the external interrupts. Note that an AVECn bit is valid only when the corresponding external interrupt request level is enabled in the IRQPAR. Table 9-6. Autovector Register Bit Assignments Autovector Interrupt Source Autovector Register Bit Location Vector Offset External interrupt request 1 AVEC1 0x64 External interrupt request 2 AVEC2 0x68 External interrupt request 3 AVEC3 0x6C External interrupt request 4 AVEC4 0x70 External interrupt request 5 AVEC5 0x74 External interrupt request 6 AVEC6 0x78 External interrupt request 7 AVEC7 0x7C 9.2.3 Interrupt Pending and Mask Registers (IPR and IMR) The interrupt pending register (IPR), Figure 9-4, makes visible the interrupt sources that have an interrupt pending. The interrupt mask register (IMR), also shown in Figure 9-4, is used to mask the internal and external interrupt sources. NOTE: To mask interrupt sources, first set the core's status register interrupt mask level to that of the source being masked in the IMR. Then, the IMR bit can be masked. An interrupt is masked by setting, and enabled by clearing, the corresponding IMR bit. When a masked interrupt occurs, the corresponding IPR bit is still set, but no interrupt request is passed to the core. 9-6 MCF5407 User's Manual Interrupt Controller Registers 31 30 29 28 27 26 25 24 Field -- Reset -- R/W 23 22 21 20 19 18 17 16 DMA3 DMA2 1 1 Read-only (IPR); R/W (IMR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field DMA1 DMA0 UART1 UART0 I2C TIMER2 TIMER1 SWT EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1 Reset 1111 1111 1111 R/W Read-only (IPR); R/W (IMR) Addr MBAR + 0x040 (IPR); + 0x044 (IMR) 1 1 -- 1 -- Figure 9-4. Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR) Table 9-7 describes IPR and IMR fields. Table 9-7. IPR and IMR Field Descriptions Bits Name 31-18 -- 17-1 See Figure 9-4 Description Reserved, should be cleared. Interrupt pending/mask. Each bit corresponds to an interrupt source defined by the ICR. The corresponding IMR bit determines whether an interrupt condition can generate an interrupt. At every clock, the IPR samples the signal generated by the interrupting source. The corresponding IPR bit reflects the state of the interrupt signal even if the corresponding IMR bit is set. 0 The corresponding interrupt source is not masked (IMR) and has no interrupt pending (IPR). 1 The corresponding interrupt source is masked (IMR) and has an interrupt pending (IPR) 9.2.4 Interrupt Port Assignment Register (IRQPAR) The interrupt port assignment register (IRQPAR), shown in Figure 9-5, provides the level assignment of the primary external interrupt pins--IRQ5, IRQ3, and IRQ1. The setting of IRQPAR2-IRQPAR0 determines the interrupt level of these external interrupt pins. 7 Field IRQPAR2 6 5 IRQPAR1 IRQPAR0 Reset 4 3 -- 2 1 0 ENBDACK1 ENBDACK0 0000_0000 R/W R/W Address MBAR + 0x06 Figure 9-5. Interrupt Port Assignment Register (IRQPAR) Table 9-8 describes IRQPAR fields. Chapter 9. Interrupt Controller 9-7 Interrupt Controller Registers Table 9-8. IRQPAR Field Descriptions Bits Name Description 7-5 IRQPARn Configures the IRQ pin assignments and priorities IRQPARn External Pin IRQPARn = 0 IRQPARn = 1 IRQPAR2 IRQ5 Level 5 Level 4 IRQPAR1 IRQ3 Level 3 Level 6 IRQPAR0 IRQ1 Level 1 Level 2 4-2 -- Reserved, should be cleared. 1-0 ENBDACKn Enable DACK1 and DACK0. Determines the functionality of the respective TMn/DACKn pins. 0 TM1 and TM0 are driven instead of DACK1 and DACK0. 1 If the PAR register is programmed to enable TMn, the DACKn signal for DMA channel n is driven in place of TMn for DMA transfers. 9-8 MCF5407 User's Manual Chapter 10 Chip-Select Module This chapter describes the MCF5407 chip-select module, including the operation and programming model of the chip-select registers, which include the chip-select address, mask, and control registers. 10.1 Overview The following list summarizes the key chip-select features: * * * * Eight independent, user-programmable chip-select signals (CS[7:0]) that can interface with SRAM, PROM, EPROM, EEPROM, Flash, and peripherals Address masking for 64-Kbyte to 4-Gbyte memory block sizes Programmable wait states and port sizes External master access to chip selects 10.2 Chip-Select Module Signals Table 10-1 lists signals used by the chip-select module. Table 10-1. Chip-Select Module Signals Signal Description Chip Selects (CS[7:0]) Each CSn can be independently programmed for an address location as well as for masking, port size, read/write burst-capability, wait-state generation, and internal/external termination. Only CS0 is initialized at reset when it acts as a global chip select that allows boot ROM to be at any defined address space. Port size and termination (internal versus external) and byte enables for CS0 are configured by the logic levels of D[7:5] when RSTI negates. Output Enable (OE) Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the current address decode. Byte Enables/ Byte Write Enables (BE[3:0]/ BWE[3:0]) These multiplexed signals are individually programmed through the byte enable mode bit, CSCRn[BEM], described in Section 10.4.1.3, "Chip-Select Control Registers (CSCR0-CSCR7)." These generated signals provide byte data select signals, which are decoded from the transfer size, A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed, as Table 10-2 shows. Table 10-2 shows the interaction of the byte enable/byte-write enables with related signals. Chapter 10. Chip-Select Module 10-1 Chip-Select Operation Table 10-2. Byte Enables/Byte Write Enable Signal Settings BE0/BWE0 BE1/BWE1 BE2/BWE2 BE3/BWE3 D[31:24] D[23:16] D[15:8] D[7:0] 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 Transfer Size Port Size A1 A0 Byte 8-bit 0 0 0 16-bit 32-bit Word 8-bit 16-bit 32-bit Longword 8-bit 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 32-bit 0 0 0 0 0 0 8-bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 16-bit Line 0 1 16-bit 32-bit 10.3 Chip-Select Operation Each chip select has a dedicated set of the following registers for configuration and control. * 10-2 Chip-select address registers (CSARn) control the base address space of the chip select. See Section 10.4.1.1, "Chip-Select Address Registers (CSAR0-CSAR7)." MCF5407 User's Manual Chip-Select Operation * * Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See Section 10.4.1.2, "Chip-Select Mask Registers (CSMR0-CSMR7)." Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, and automatic acknowledge generation features. See Section 10.4.1.3, "Chip-Select Control Registers (CSCR0-CSCR7)." Each CSn can assert during specific CPU space accesses such as interrupt-acknowledge cycles and each can be accessed by an external master. CS0 is a global chip select after reset and provides relocatable boot ROM capability. 10.3.1 General Chip-Select Operation When a bus cycle is initiated, the MCF5407 first compares its address with the base address and mask configurations programmed for chip selects 0-7 (configured in CSCR0-CSCR7) and DRAM block 0 and 1 address and control registers (configured in DACR0 and DACR1). If the driven address matches a programmed chip select or DRAM block, the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed in the respective configuration register. Otherwise, the following occurs: * If the address and attributes do not match in CSCR or DACR, the MCF5407 runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. * Should an address and attribute match in multiple CSCRs, the matching chip-select signals are driven; however, the MCF5407 runs an external burst-inhibited bus cycle with external termination on a 32-bit port. * Should an address and attribute match both DACRs or a DACR and a CSCR, the operation is undefined. Table 10-3 shows the type of access as a function of match in the CSCRs and DACRs. Table 10-3. Accesses by Matches in CSCRs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSCR Multiple 0 External, burst-inhibited, 32-bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined Chapter 10. Chip-Select Module 10-3 Chip-Select Operation 10.3.1.1 8-, 16-, and 32-Bit Port Sizing Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 10.4.1.3, "Chip-Select Control Registers (CSCR0-CSCR7)." Figure 10-1 shows the correspondence between data byte lanes and the external chip-select memory. Note that all lanes are driven, although unused lines are undefined. BE0 BE1 BE2 BE3 D[31:24] D[23:16] D[15:8] D[7:0] 32-bit port memory Byte 0 Byte 1 Byte 2 Byte 3 16-bit port memory Byte 0 Byte 1 Byte 2 Byte 3 External data bus 8-bit port memory Byte 0 Byte 1 Byte 2 Byte 3 Driven, undefined Driven, undefined Figure 10-1. Connections for External Memory Port Sizes 10.3.1.2 Global Chip-Select Operation CS0, the global (boot) chip select, allows address decoding for boot ROM before system initialization. Its operation differs from other external chip-select outputs after system reset. After system reset, CS0 is asserted for every external access. No other chip-select can be used until the valid bit, CSMR0[V], is set, at which point CS0 functions as configured and CS[7:1] can be used. At reset, the port size, byte enable, and automatic acknowledge functions of the global chip-select are determined by the logic levels of the inputs on D[7:5,3]. Table 10-4 through Table 10-6 list the various reset encodings for the configuration signals multiplexed with D[7:5,3]. Table 10-4. D7/AA, Automatic Acknowledge of Boot CS0 D7/AA 10-4 Boot CS0 AA Configuration at Reset 0 Disabled 1 Enable with 15 wait states MCF5407 User's Manual Chip-Select Registers Table 10-5. D[6:5]/PS[1:0], Port Size of Boot CS0 D[6:5]/PS[1:0] Boot CS0 Port Size at Reset 00 32-bit port 01 8-bit port 1x 16-bit port Table 10-6. D3/BE_CONFIG0, BE[3:0] Boot Configuration D3/BE_CONFIG0 Configuration of Byte Enables for Boot CS0 0 BE[3:0] is enabled as byte write enables only. 1 BE[3:0] is enabled as byte enables for reads and writes. Provided the required address range is in the chip-select address register (CSAR0), CS0 can be programmed to continue decoding for a range of addresses after the CSMR0[V] is set, after which the global chip-select can be restored only by a system reset. 10.4 Chip-Select Registers Table 10-7 is the chip-select register memory map. Reading reserved locations returns zeros. Table 10-7. Chip-Select Registers MBAR Offset 0x080 0x084 [31:24] [23:16] [15:8] [7:0] Reserved1 Chip-select address register--bank 0 (CSAR0) [p. 10-6] Chip-select mask register--bank 0 (CSMR0) [p. 10-7] 0x088 Reserved1 Chip-select control register--bank 0 (CSCR0) [p. 10-8] 0x08C Chip-select address register--bank 1 (CSAR1) [p. 10-6] Reserved1 0x090 Chip-select mask register--bank 1 (CSMR1) [p. 10-7] 0x094 Reserved1 Chip-select control register--bank 1 (CSCR1) [p. 10-8] 0x098 Chip-select address register--bank 2 (CSAR2) [p. 10-6] Reserved1 0x09C Chip-select mask register--bank 2 (CSMR2) [p. 10-7] 0x0A0 Reserved1 Chip-select control register--bank 2 (CSCR2) [p. 10-8] 0x0A4 Chip-select address register--bank 3 (CSAR3) [p. 10-6] Reserved1 0x0A8 Chip-select mask register--bank 3 (CSMR3) [p. 10-7] 0x0AC Reserved1 Chip-select control register--bank 3 (CSCR3) [p. 10-8] 0x0B0 Chip-select address register--bank 4 (CSAR4) [p. 10-6] Reserved1 0x0B4 Chip-select mask register--bank 4 (CSMR4) [p. 10-7] Chapter 10. Chip-Select Module 10-5 Chip-Select Registers Table 10-7. Chip-Select Registers (Continued) MBAR Offset [31:24] [15:8] [7:0] 0x0B8 Reserved1 Chip-select control register--bank 4 (CSCR4) [p. 10-8] 0x0BC Chip-select address register--bank 5 (CSAR5) [p. 10-6] Reserved1 0x0C0 Chip-select mask register--bank 5 (CSMR5) [p. 10-7] 0x0C4 Reserved Chip-select control register--bank 5 (CSCR5) [p. 10-8] 0x0C8 Chip-select address register--bank 6 (CSAR6) [p. 10-6] Reserved1 0x0CC Chip-select mask register--bank 6 (CSMR6) [p. 10-7] 0x0D0 Reserved1 Chip-select control register--bank 6 (CSCR6) [p. 10-8] 0x0D4 Chip-select address register--bank 7 (CSAR7) [p. 10-6] Reserved1 0x0D8 Chip-select mask register--bank 7 (CSMR7) [p. 10-7] Reserved1 0x0DC 1 [23:16] Chip-select control register--bank 7 (CSCR7) [p. 10-8] Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. NOTE: External masters cannot access MCF5407 on-chip memories or MBAR, but can access any of the chip-select module registers. 10.4.1 Chip-Select Module Registers The chip-select module is programmed through the chip select address registers (CSAR0-CSAR7), chip select mask registers (CSMR0-CSMR7), and the chip select control registers (CSCR0-CSCR7). 10.4.1.1 Chip-Select Address Registers (CSAR0-CSAR7) Chip select address registers, Figure 10-2, specify the chip select base addresses. 15 0 Field BA Reset Uninitialized R/W R/W Addr 0x080 (CSAR0); 0x08C (CSAR1); 0x098 (CSAR2); 0x0A4 (CSAR3); 0x0B0 (CSAR4); 0x0BC (CSAR5); 0x0C8 (CSAR6); 0x0D4 (CSAR7) Figure 10-2. Chip Select Address Registers (CSAR0-CSAR7) Table 10-8 describes CSAR[BA]. 10-6 MCF5407 User's Manual Chip-Select Registers Table 10-8. CSARn Field Description Bits Name Description 15-0 BA Base address. Defines the base address for memory dedicated to chip select CS[7:0]. BA is compared to bits 31-16 on the internal address bus to determine if chip-select memory is being accessed. 10.4.1.2 Chip-Select Mask Registers (CSMR0-CSMR7) The chip select mask registers, Figure 10-3, are used to specify the address mask and allowable access types for the respective chip selects. . 31 16 15 Field 9 BAM -- Reset 8 7 6 5 4 3 2 1 0 WP -- AM C/I SC SD UC UD V Unitialized R/W R/W Addr 0x084 (CSMR0); 0x090 (CSMR1); 0x09C (CSMR2); 0x0A8 (CSMR3); 0x0B4 (CSMR4); 0x0C0 (CSMR5); 0x0CC (CSMR6); 0x0D8 (CSMR7) 0 Figure 10-3. Chip Select Mask Registers (CSMRn) Table 10-9 describes CSMR fields. Table 10-9. CSMRn Field Descriptions Bits Name Description 31-16 BAM Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode. 0 Corresponding address bit is used in chip-select decode. 1 Corresponding address bit is a don't care in chip-select decode. The block size for CS[7:0] is 2n; n = (number of bits set in respective CSMR[BAM]) + 16. So, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008, CS0 would address two discontinuous 64-Kbyte memory blocks: one from 0x0000-0xFFFF and one from 0x8_0000-0x8_FFFF. Likewise, for CS0 to access 32 Mbytes of address space starting at location 0x0, CS1 must begin at the next byte after CS0 for a 16-Mbyte address space. Then CSAR0 = 0x0000, CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and CSMR1[BAM] = 0x00FF. 8 WP Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate chip select not being selected. No exception occurs. 0 Both read and write accesses are allowed. 1 Only read accesses are allowed. 7 -- Reserved, should be cleared. 6 AM Alternate master. When AM = 0 during an external master or DMA access, SC, SD, UC, and UD are don't cares in the chip-select decode. Chapter 10. Chip-Select Module 10-7 Chip-Select Registers Table 10-9. CSMRn Field Descriptions (Continued) Bits Name 5-1 C/I, SC, SD, UC, UD Description Address space mask bits. These bits determine whether the specified accesses can occur to the address space defined by the BAM for this chip select. C/I SC SD UC UD CPU space and interrupt acknowledge cycle mask Supervisor code address space mask Supervisor data address space mask User code address space mask User data address space mask 0 The address space assigned to this chip select. is available to the specified access type. 1 The address space assigned to this chip select. is not available (masked) to the specified access type. If this address space is accessed, chip select is not activated and a regular external bus cycle occurs. Note that if if AM = 0, SC, SD, UC, and UD are ignored in the chip select decode on external master or DMA access. 0 V Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip selects do not assert until V is set (except for CS0, which acts as the global chip select). Reset clears each CSMRn[V]. 0 Chip select invalid 1 Chip select valid 10.4.1.3 Chip-Select Control Registers (CSCR0-CSCR7) Each chip-select control register, Figure 10-4, controls the auto acknowledge, external master support, port size, burst capability, and activation of each chip select. Note that to support the global chip select, CS0, the CSCR0 reset values differ from the other CSCRs. CS0 allows address decoding for boot ROM before system initialization. 15 14 13 10 9 8 7 6 5 4 3 2 Field -- WS -- AA PS1 PS0 BEM BSTR BSTW Reset: CSCR0 -- 11_11 -- D7 Reset: Other CSCRs D5 D3 -- Unitialized R/W Address D6 0 -- R/W 0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3); 0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6); 0x0DE (CSCR7) Figure 10-4. Chip-Select Control Registers (CSCR0-CSCR7) Table 10-10 describes CSCRn fields. Table 10-10. CSCRn Field Descriptions Bits Name 15-14 -- 13-10 WS 9 -- 10-8 Description Reserved, should be cleared. Wait states. The number of wait states inserted before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, TA must be asserted by the external system regardless of the number of wait states generated. In that case, the external transfer acknowledge ends the cycle. An external TA supersedes the generation of an internal TA. Reserved, should be cleared. MCF5407 User's Manual Chip-Select Registers Table 10-10. CSCRn Field Descriptions Bits Name Description 8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip-select address. 0 No internal TA is asserted. Cycle is terminated externally. 1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the external system asserts an external TA before the wait-state countdown asserts the internal TA, the cycle is terminated. Burst cycles increment the address bus between each internal termination. 7-6 PS Port size. Specifies the width of the data associated with each chip select. It determines where data is driven during write cycles and where data is sampled during read cycles. See Section 10.3.1.1, "8-, 16-, and 32-Bit Port Sizing." 00 32-bit port size. Valid data sampled and driven on D[31:0] 01 8-bit port size. Valid data sampled and driven on D[31:24] 1x 16-bit port size. Valid data sampled and driven on D[31:16] 5 BEM Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable in support of these SRAMs. 0 Neither BE nor BWE is asserted for read. BWE is generated for data write only. 1 BE is asserted for read; BWE is asserted for write. 4 BSTR Burst read enable. Specifies whether burst reads are used for memory associated with each CSn. 0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 3 BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CSn. 0 Break data larger than the specified port size into individual port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports. 2-0 -- Reserved, should be cleared. 10.4.1.4 Code Example The code below provides an example of how to initialize the chip-selects. Only chip selects 0, 1, 2, and 3 are programmed here; chip selects 4, 5, 6, and 7 are left invalid. MBARx defines the base of the module address space. CSAR0 EQU MBARx+0x080 CSMR0 EQU MBARx+0x084 CSCR0 EQU MBARx+0x08A ;Chip select 0 address register ;Chip select 0 mask register ;Chip select 0 control register CSAR1 EQU MBARx+0x08C CSMR1 EQU MBARx+0x090 CSCR1 EQU MBARx+0x096 ;Chip select 1 address register ;Chip select 1 mask register ;Chip select 1 control register CSAR2 EQU MBARx+0x098 CSMR2 EQU MBARx+0x09C CSCR2 EQU MBARx+0x0A2 ;Chip select 2 address register ;Chip select 2 mask register ;Chip select 2 control register CSAR3 EQU MBARx+0x0A4 CSMR3 EQU MBARx+0x0A8 CSCR3 EQU MBARx+0x0AE ;Chip select 3 address register ;Chip select 3 mask register ;Chip select 3 control register CSAR4 EQU MBARx+0x0B0 CSAR4 EQU MBARx+0x0B4 CSMR4 EQU MBARx+0x0BA ;Chip select 4 address register ;Chip select 4 mask register ;Chip select 4 control register Chapter 10. Chip-Select Module 10-9 Chip-Select Registers CSAR5 EQU MBARx+0x0BC CSMR5 EQU MBARx+0x0C0 CSCR5 EQU MBARx+0x0C6 ;Chip select 5 address register ;Chip select 5 mask register ;Chip select 5 control register CSAR6 EQU MBARx+0x0C8 CSMR6 EQU MBARx+0x0CC CSCR6 EQU MBARx+0x0D2 ;Chip select 6 address register ;Chip select 6 mask register ;Chip select 6 control register CSAR7 EQU MBARx+0x0D4 CSMR7 EQU MBARx+0x0D8 CSCR7 EQU MBARx+0x0DE ;Chip select 7 address register ;Chip select 7 mask register ;Chip select 7 control register ; All other chip selects should be programmed and made valid before global ; chip select is de-activated by validating CS0 ; Program Chip Select 3 Registers move.w #0x0040,D0 ;CSAR3 base address 0x00400000 move.w D0,CSAR3 move.w move.w #0x00A0,D0 D0,CSCR3 move.l #0x001F016B,D0 move.l D0,CSMR3 ;CSCR3 = no wait states, AA=0, PS=16-bit, BEM=1, ;BSTR=0, BSTW=0 ;Address range from 0x00400000 to 0x005FFFFF ;WP,EM,C/I,SD,UD,V=1; SC,UC=0 ; Program Chip Select 2 Registers move.w move.w #0x0020,D0 D0,CSAR2 ;CSAR2 base address 0x00200000 (to 0x003FFFFF) move.w move.w #0x0538,D0 D0,CSCR2 ;CSCR2 = 1 wait state, AA=1, PS=32-bit, BEM=1, ;BSTR=1, BSTW=1 move.l move.l #0x001F0001,D0 D0,CSMR2 ;Address range from 0x00200000 to 0x003FFFFF ;WP,EM,C/I,SC,SD,UC,UD=0; V=1 ; Program Chip Select 1 Registers move.w move.w #0x0000,D0 D0,CSAR1 ;CSAR1 base addresses 0x00000000 (to 0x001FFFFF) ;and 0x80000000 (to 0x801FFFFF) move.w move.w #0x09B0,D0 D0,CSCR1 ;CSCR1 = 2 wait states, AA=1, PS=16-bit, BEM=1, ;BSTR=1, BSTW=0 move.l move.l #0x801F0001,D0 D0,CSMR1 ;Address range from 0x00000000 to 0x001FFFFF and ;0x80000000 to 0x801FFFFF ;WP, EM, C/I, SC, SD, UC, UD=0, V=1 ; Program Chip Select 0 Registers move.w move.w #0x0080,D0 D0,CSAR0 ;CSAR0 base address 0x00800000 (to 0x009FFFFF) move.w move.w #0x0D80,D0 D0,CSCR0 ;CSCR0 = three wait states, AA=1, PS=16-bit, BEM=0, ;BSTR=0, BSTW=0 ; Program Chip Select 0 Mask Register (validate chip selects) move.l move.l 10-10 #0x001F0001,D0 D0,CSMR0 ;Address range from 0x00800000 to 0x009FFFFF ;WP,EM,C/I,SC,SD,UC,UD=0; V=1 MCF5407 User's Manual Chapter 11 Synchronous/Asynchronous DRAM Controller Module This chapter describes configuration and operation of the synchronous/asynchronous DRAM controller component of the system integration module (SIM). It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter consists of the two following parts: * * Section 11.3, "Asynchronous Operation," describes the programming model and signal timing for the four basic asynchronous modes. -- Non-page mode -- Burst page mode -- Continuous page mode -- Extended data-out mode Section 11.4, "Synchronous Operation," describes the programming model and signal timing, as well as the command set required for synchronous operations. This section also includes extensive examples the designer can follow to better understand how to configure the DRAM controller for synchronous operations. 11.1 Overview The DRAM controller module provides glueless integration of DRAM with the ColdFire product. The key features of the DRAM controller include the following: * * * * * * Support for two independent blocks of DRAM Interface to standard synchronous/asynchronous dynamic random access memory (ADRAM/SDRAM) components Programmable SRAS, SCAS, and refresh timing Support for page mode Support for 8-, 16-, and 32-bit wide DRAM blocks Support for synchronous and asynchronous DRAMs, including EDO DRAM, SDRAM, and fast page mode Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-1 Overview 11.1.1 Definitions The following terminology is used in this chapter: * * * A/SDRAM block--Any group of DRAM memories selected by one of the MCF5407 RAS[1:0] signals. Thus, the MCF5407 can support two independent memory blocks. The base address of each block is programmed in the DRAM address and control registers (DACR0 and DACR1). SDRAM--RAMs that operate like asynchronous DRAMs but with a synchronous clock, a pipelined, multiple-bank architecture, and faster speed. SDRAM bank--An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM component might be configured as four 512K x 32 banks. Banks are selected through the SDRAM component's bank select lines. 11.1.2 Block Diagram and Major Components The basic components of the DRAM controller are shown in Figure 11-1. DRAM Controller Module A[31:0] Address Multiplexing Internal Bus Page Hit Logic Control Logic and State Machine Memory Block 0 Hit Logic DRAM Address/Control Register 0 (DACR0) DRAM Control Register (DCR) Memory Block 1 Hit Logic DRAM Address/Control Register 1 (DACR1) A[31:0] RAS[1:0] CAS[3:0] DRAMW SCAS These signals are used for SRAS SDRAM only SCKE Refresh Counter Figure 11-1. Asynchronous/Synchronous DRAM Controller Block Diagram The DRAM controller's major components, shown in Figure 11-1, are described as follows: * 11-2 DRAM address and control registers (DACR0 and DACR1)--The DRAM controller consists of two configuration register units, one for each supported memory block. DACR0 is accessed at MBAR + 0x0108; DACR1 is accessed at 0x010. The register information is passed on to the hit logic. MCF5407 User's Manual DRAM Controller Operation * * * * Control logic and state machine--Generates all DRAM signals, taking bus cycle characteristic data from the block logic, along with hit information to generate DRAM accesses. Handles refresh requests from the refresh counter. -- DRAM control register (DCR)--Contains data to control refresh operation of the DRAM controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC]. -- Refresh counter--Determines when refresh should occur, determined by the value of DCR[RC]. It generates a refresh request to the control block. Hit logic--Compares address and attribute signals of a current DRAM bus cycle to both DACRs to determine if a DRAM block is being accessed. Hits are passed to the control logic along with characteristics of the bus cycle to be generated. Page hit logic--Determines if the next DRAM access is in the same DRAM page as the previous one. This information is passed on to the control logic. Address multiplexing--Multiplexes addresses to allow column and row addresses to share pins. This allows glueless interface to DRAMs. 11.2 DRAM Controller Operation The DRAM controller mode is programmed through DCR[SO]. Asynchronous mode (SO = 0) includes support for page mode and EDO DRAMs. Synchronous mode is designed to work with industry-standard SDRAMs. These modes act very differently from one another, especially regarding the use of DRAM registers and pins. Memory blocks cannot operate in different modes; both are either synchronous or asynchronous. 11.2.1 DRAM Controller Registers The DRAM controller registers memory map, Table 11-1, is the same regardless of whether asynchronous or synchronous DRAM is used, although bit configurations may vary. Table 11-1. DRAM Controller Registers MBAR Offset 0x100 [31:24] [23:16] [15:8] DRAM control register (DCR) [p. 11-4] [7:0] Reserved 0x104 Reserved 0x108 DRAM address and control register 0 (DACR0) [p. 11-5] 0x10C DRAM mask register block 0 (DMR0) [p. 11-7] 0x110 DRAM address and control register 1 (DACR1) [p. 11-5] 0x114 DRAM mask register block 1 (DMR1) [p. 11-7] NOTE: External masters cannot access MCF5407 on-chip memories or MBAR, but they can access DRAM controller registers. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-3 Asynchronous Operation 11.3 Asynchronous Operation The DRAM controller supports asynchronous DRAMs for cost-effective systems. Typical access times for the DRAM controller interfacing to ADRAM are 4-3-3-3. The DRAM controller supports the following four asynchronous modes: * * * * Non-page mode Burst page mode Continuous page mode Extended data-out mode In asynchronous mode, RAS and CAS always transition at the falling clock edge. As summarized previously, operation and timing of each ADRAM block is controlled by separate registers, but refresh is the same for both. All ADRAM accesses should be terminated by the DRAM controller. There is no priority encoding between memory blocks, so programming blocks to overlap with other blocks or with other internal resources causes undefined behavior. 11.3.1 DRAM Controller Signals in Asynchronous Mode Table 11-2 summarizes DRAM signals used in asynchronous mode. Table 11-2. SDRAM Signal Summary Signal Description RAS[1:0] Row address strobes. Interface to RAS inputs on industry-standard ADRAMs. When SDRAMs are used, these signals interface to the chip-select lines within an SDRAM's memory block. Thus, there is one RAS line for each of the two blocks. CAS[3:0] Column address strobes. Interface to CAS inputs on industry-standard DRAMs. These provide CAS for a given ADRAM block. When SDRAMs are used, CAS[3:0] control the byte enables (DQMx) for standard SDRAMs. CAS[3:0] strobes data in least-to-most significant byte order (CAS0 is MSB). DRAMW DRAM read/write. Asserted when a DRAM write cycle is underway. Negated for read bus cycles. 11.3.2 Asynchronous Register Set The following register configurations apply when DCR[SO] is 0, indicating the DRAM controller is interfacing to asynchronous DRAMs. 11.3.2.1 DRAM Control Register (DCR) in Asynchronous Mode The DCR provides programmable options for the refresh logic as well as the control bit to determine if the module is operating with synchronous or asynchronous DRAMs. The DCR is shown in Figure 11-2. 11-4 MCF5407 User's Manual Asynchronous Operation 15 Field SO Reset 14 13 -- NAM 12 11 10 RRA 0 9 8 0 RRP RC Uninitialized R/W R/W Address MBAR + 0x100 Figure 11-2. DRAM Control Register (DCR) (Asynchronous Mode) Table 11-3 describes DCR fields. Table 11-3. DCR Field Descriptions (Asynchronous Mode) Bits Name Description 15 SO Synchronous operation. Selects synchronous or asynchronous mode. A DRAM controller in synchronous mode can be switched to ADRAM mode only by resetting the MCF5407. 0 Asynchronous DRAMs. Default at reset. 1 Synchronous DRAMs 14 -- Reserved, should be cleared. 13 NAM No address multiplexing. Some implementations require external multiplexing. For example, when linear addressing is required, the DRAM should not multiplex addresses on DRAM accesses. 0 The DRAM controller multiplexes the external address bus to provide column addresses. 1 The DRAM controller does not multiplex the external address bus to provide column addresses. 12-11 RRA Refresh RAS asserted. Determines how long RAS is asserted during a refresh operation. 00 2 clocks 01 3 clocks 10 4 clocks 11 5 clocks 10-9 RRP Refresh RAS precharge. Controls how many clocks RAS is precharged after a refresh operation before accesses are allowed to DRAM. 00 1 clock 01 2 clocks 10 3 clocks 11 4 clocks 8-0 RC Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is (RC + 1) * 16. Refresh can range from 16-8192 bus clocks to accommodate both standard and low-power DRAMs with bus clock operation from less than 2 MHz to greater than 50 MHz. The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 mS of refresh every 15.625 s for each row (625 bus clocks at 40 MHz). # of bus clocks = 625 = (RC field + 1) * 16 RC = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, RC = 0x26. 11.3.2.2 DRAM Address and Control Registers (DACR0/DACR1) DACR0 and DACR1, Figure 11-3, contain the base address compare value and the control bits for memory blocks 0 and 1. Address and timing are also controlled by these registers. Memory areas defined for each block should not overlap; operation is undefined for accesses in overlapping regions. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-5 Asynchronous Operation 31 18 17 16 Field BA Reset -- Unitialized 15 14 13 12 11 10 RE -- CAS RP 9 RNCN 0 8 7 6 RCD -- EDO 5 4 PS 3 2 PM 1 0 -- Unitialized R/W R/W Addr MBAR + 0x10C (DACR0); 0x110 (DACR1) Figure 11-3. DRAM Address and Control Registers (DACR0/DACR1) Table 11-4 describes DACRn fields. Table 11-4. DACR0/DACR1 Field Description Bits Name Description 31-18 BA Base address. Used with DMR[BAM] to determine the address range in which the associated DRAM block is located. Each BA bit is compared with the corresponding address of the bus cycle in progress. If each bit matches, or if bits that do not match are masked in the BAM, the address selects the associated DRAM block. 17-16 -- Reserved, should be cleared. 15 RE Refresh enable. Determines whether the DRAM controller generates a refresh to the associated DRAM block. DRAM contents are not preserved during hard reset or software watchdog reset. 0 Do not refresh associated DRAM block. (Default at reset) 1 Refresh associated DRAM block. Reserved, should be cleared. 14 -- 13-12 CAS 11-10 RP 9 RAS precharge timing. Determines how long RAS is precharged between accesses. Note that RP is different from DCR[RRP]. 00 1 clock cycle 01 2 clock cycles 10 3 clock cycles 11 4 clock cycles RNCN RAS-negate-to-CAS-negate. Controls whether RAS and CAS negate concurrently or one clock apart. RNCN is ignored if CAS is asserted for only one clock and both RAS and CAS are negated. RNCN is used only for non-page-mode accesses and single accesses in page mode. 0 RAS negates concurrently with CAS. 1 RAS negates one clock before CAS. 8 RCD 7 -- 6 EDO 11-6 CAS timing. Determines how long CAS is asserted during a DRAM access. 00 1 clock cycle 01 2 clock cycles 10 3 clock cycles 11 4 clock cycles RAS-to-CAS delay. Determines the number of system clocks between assertions of RAS and CAS. 0 1 clock cycle 1 2 clock cycles Reserved, should be cleared. Extended data out. Determines whether the DRAM block operates in a mode to take advantage of industry-standard EDO DRAMs. Do not use EDO mode with non-EDO DRAM. 0 EDO operation disabled. 1 EDO operation enabled. MCF5407 User's Manual Asynchronous Operation Table 11-4. DACR0/DACR1 Field Description (Continued) Bits Name Description 5-4 PS Port size. Determines the port size of the associated DRAM block. For example, if two 16-bit wide DRAM components form one DRAM block, the port size is 32 bits. Programming PS allows the DRAM controller to execute dynamic bus sizing for associated accesses. 00 32-bit port 01 8-bit port 1x 16-bit port 3-2 PM Page mode. Configures page-mode operation for the memory block. 00 No page mode 01 Burst page mode (page mode for bursts only) 10 Reserved 11 Continuous page mode 1-0 -- Reserved, should be cleared. 11.3.2.3 DRAM Controller Mask Registers (DMR0/DMR1) The DRAM controller mask registers (DMR0 and DMR1), shown in Figure 11-4, include mask bits for the base address and for address attributes. 31 18 17 Field BAM 9 -- Reset 8 7 6 5 4 3 2 1 0 WP -- C/I AM SC SD UC UD V Uninitialized R/W R/W Addr MBAR + 0x10C (DMR0), 0x114 (DMR1) 0 Figure 11-4. DRAM Controller Mask Registers (DMR0 and DMR1) Table 11-5 describes DMRn fields. Table 11-5. DMR0/DMR1 Field Descriptions Bits Name Description 31-18 BAM Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various DRAM sizes. Mask bits need not be contiguous (see Section 11.5, "SDRAM Example.") 0 The associated address bit is used in decoding the DRAM hit to a memory block. 1 The associated address bit is not used in the DRAM hit decode. 17-9 -- 8 WP 7 -- Reserved, should be cleared. Write protect. Determines whether the associated block of DRAM is write protected. 0 Allow write accesses 1 Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs. Reserved, should be cleared. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-7 Asynchronous Operation Table 11-5. DMR0/DMR1 Field Descriptions (Continued) Bits Name 6-1 AMx Description Address modifier masks. Determine which accesses can occur in a given DRAM block. 0 Allow access type to hit in DRAM 1 Do not allow access type to hit in DRAM Bit 0 V Associated Access Type Access Definition C/I CPU space/interrupt acknowledge MOVEC instruction or interrupt acknowledge cycle AM Alternate master External or DMA master SC Supervisor code Any supervisor-only instruction access SD Supervisor data Any data fetched during the instruction access UC User code Any user instruction UD User data Any user data Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded. 0 Do not decode DRAM accesses. 1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded. 11.3.3 General Asynchronous Operation Guidelines The DRAM controller provides control for RAS, CAS, and DRAMW signals, as well as address multiplexing and bus cycle termination. Whether the mode is synchronous or asynchronous determines signal control and termination. To reduce complexity, multiplexing is the same for both modes. Table 11-6 shows the scheme for DRAM configurations. This scheme works for symmetric configurations (in which the number of rows equals the number of columns) as well as asymmetric configurations (in which the number of rows and columns are different). Table 11-6. Generic Address Multiplexing Scheme Address Pin Row Address Column Address 17 17 0 8-bit port only 16 16 1 8- and 16-bit ports only 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 11-8 Notes Relating to Port Sizes 9 9 8 17 17 16 32-bit port only 18 18 17 16-bit port only or 32-bit port with only 8 column address lines 19 19 18 16-bit port only when at least 9 column address lines are used MCF5407 User's Manual Asynchronous Operation Table 11-6. Generic Address Multiplexing Scheme (Continued) Address Pin Row Address Column Address 20 20 19 21 21 20 22 22 21 23 23 22 24 24 23 25 25 24 Notes Relating to Port Sizes Note the following: * * * * * Each MCF5407 address bit drives both a row address and a column address bit. As the user upgrades ADRAM, corresponding MCF5407 address bits must be connected. This multiplexing scheme allows various memory widths to be connected to the address bus. Some differences exist for each of the three possible port sizes. Note that only 8-bit ports use an A0 address from the MCF5407. Because 16- and 32-bit ports issue either words or longwords when accessed, they do not use the MCF5407 A0 signal. Likewise, the configuration for 32-bit ports uses neither A0 or A1. This presents a slight problem because DRAM address signal A0 is issued on physical pin A17 of the MCF5407 along with the ADRAM address signal A17. Although A0 is not used for larger ports, A17 is still needed. The MCF5407 DRAM controller provides for this by changing the column address that appears on physical pin A17 of the processor whenever an 8-bit port is not selected. This is determined by the DACRn[PS] settings. For 8-bit ports, MCF5407 physical pin A17 drives logical address A0 during the CAS cycle. When 16- or 32-bit port sizes are programmed, the CAS cycle pin A17 drives logical address A16, as indicated in the generic connection scheme. If a 32-bit port is used with only eight column address lines, A18 must drive DRAM address bit A18. Otherwise, in 32-bit port configurations, the MCF5407 physical address line is not connected with more than eight column address lines. All ADRAM blocks have a fixed page size of 512 bytes for page-mode operation. The addresses are connected differently for various width combinations. Table 11-7, Table 11-8, and Table 11-9 show how 8-, 16-, and 32-bit symmetrical ADRAM memories are connected to the address bus. The memory sizes show what DRAM size is accessed if the corresponding bits are connected to the memory. In each case, there is a base memory size. This limitation exists to allow simple page-mode multiplexing. Notice also that MCF5407 pin 17 is treated differently in byte-wide operations. In byte-wide operations, address bits 16 and 17 are driven on MCF5407 physical address pins 16 and 17, rather than the two bits being driven solely on A17, as they are for 32-wide memories. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-9 Asynchronous Operation Table 11-7. DRAM Addressing for Byte-Wide Memories MCF5407 Address Pin MCF5407 Address Bit Driven for RAS MCF5407 Address Bit Driven when CAS is Asserted 17 17 0 16 16 1 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 19 19 18 1 Mbyte 21 21 20 4 Mbytes 23 23 22 16 Mbytes 25 25 24 64 Mbytes Memory Size Base memory size of 256 Kbytes Note that in Table 11-8, MCF5407 pin A19 is not connected because DRAM address bit 18 is already provided on MCF5407 pin A18; thus, the next MCF5407 pin used should be A20. Table 11-8. DRAM Addressing for 16-Bit Wide Memories MCF5407 Address Pin MCF5407 Address Bit Driven for RAS MCF5407 Address Bit Driven when CAS is Asserted 16 16 1 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 18 18 17 512 Kbytes 20 20 19 2 Mbytes 22 22 21 8 Mbytes 24 24 23 32 Mbytes 11-10 MCF5407 User's Manual Memory Size Base memory size of 128 Kbytes Asynchronous Operation Table 11-9. DRAM Addressing for 32-Bit Wide Memories MCF5407 Address Pin MCF5407 Address Bit Driven for RAS MCF5407 Address Bit Driven when CAS is Asserted 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 9 9 8 17 17 16 19 19 18 1 Mbyte 21 21 20 4 Mbytes 23 23 22 16 Mbytes 25 25 24 64 Mbytes Memory Size Base Memory Size of 64 Kbytes 256 Kbytes 11.3.3.1 Non-Page-Mode Operation In non-page mode, the simplest mode, the DRAM controller provides termination and runs a separate bus cycle for each data transfer. Figure 11-5 shows a non-page-mode access in which a DRAM read is followed by a write. Addresses for a new bus cycle are driven at the rising clock edge. For a DRAM block hit, the associated RAS is driven at the next falling edge. Here DACRn[RCD] = 0, so the address is multiplexed at the next rising edge to provide the column address. The required CAS signals are then driven at the next falling edge and remain asserted for the period programmed in DACRn[CAS]. Here, DACRn[RNCN] = 1, so it is precharged one clock before CAS is negated. On a read, data is sampled on the last rising edge of the clock that CAS is valid. CLKIN A[31:0] Row Column RAS[1] or [0] DACRn[RCD] = 0 DACRn[RNCN] = 1 CAS[3:0] DACRn[CAS] = 01] DRAMW D[31:0] Figure 11-5. Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4) Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-11 Asynchronous Operation Figure 11-6 shows a variation of the basic cycle. In this case, RCD is 1, so there are two clocks between RAS and CAS. Note that the address is multiplexed on the rising clock immediately before CAS is asserted. Because RNCN = 0, RAS and CAS are negated together. The next bus cycle is initiated, but because DACRn[RP] requires RAS to be precharged for two clocks, RAS is delayed for a clock in the bus cycle. Note that this does not delay the address signals, only RAS. CLKIN A[31:0] Row Column RP = 01 RAS[1] or [0] RCD = 1 CAS[3:0] RNCN = 0 CAS = 01 DRAMW D[31:0] Figure 11-6. Basic Non-Page-Mode Operation RCD = 1, RNCN = 0 (5-5-5-5) 11.3.3.2 Burst Page-Mode Operation Burst page-mode operation (DACRn[PM] = 01) optimizes memory accesses in page mode by allowing a row address to remain registered in the DRAM while accessing data in different columns. This eliminates the setup and hold times associated with the need to precharge and assert RAS. Therefore, only the first bus cycle in the page takes the full access time; subsequent accesses are streamlined. Single accesses look the same as non-page-mode accesses. Burst page-mode accesses of any size--byte, word, longword, or line--are assumed to reside in the same page. In this mode, the DRAM controller generates a burst transfer only when the operand is larger than the DRAM block port size (such as, a line transfer to a 32-bit port or a longword transfer to an 8-bit port). The primary cycle asserts RAS and CAS; subsequent cycles assert only CAS. At the end of the access, RAS is precharged. The DRAM controller increments addresses between cycles. Figure 11-7 shows a read access in burst page mode. Four accesses take place, which could be a 32-bit access to an 8-bit port or a line access to a 32-bit port. Other burst page-mode operations may be from 2 to 16 accesses long, depending on the access and port sizes. In those cases, timing is similar with more or fewer accesses. 11-12 MCF5407 User's Manual Asynchronous Operation CLKIN A[31:0] Row Column Column Column Column RAS[1] or [0] RCD = 0 CAS[3:0] CAS = 01 DRAMW D[31:0] Figure 11-7. Burst Page-Mode Read Operation (4-3-3-3) Figure 11-8 shows the write operation with the same configuration. CLKIN A[31:0] Row Column Column Column Column RAS[1] or [0] RCD = 0 CAS[3:0] CAS = 01 DRAMW D[31:0] Figure 11-8. Burst Page-Mode Write Operation (4-3-3-3) 11.3.3.3 Continuous Page Mode Continuous page mode (DACRn[PM] = 11) is a type of page mode that balances performance, complexity, and size. In typical page-mode implementations, sequential addresses are checked for multiple hits in a DRAM block. On a hit, RAS remains asserted and CAS is asserted with the new column address. On a miss, RAS must be precharged again before the bus cycle begins. Continuous page mode supports page-mode operation without requiring an address holding register per memory block and eliminates the delay for a miss-to-precharge RAS for the upcoming bus cycle. Because the internal MCF5407 address bus is pipelined, addresses for Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-13 Asynchronous Operation the next bus cycle are often available before the current cycle completes. The two addresses are compared at the end of the cycle to determine if the next address hits the same page. If so, RAS remains asserted. If not, or if no access is pending, RAS is precharged before the next bus cycle is active on the external bus. As a result, a page miss suffers no penalty. Single accesses not followed by a hit in the page look like non-page-mode accesses. Figure 11-9 shows a write cycle followed by a read cycle in continuous page mode. The read hits in the same page as the write so RAS is not negated before the second cycle. Note that the row address does not appear on the pins for a bus cycle that hits in the page. Column addresses are immediately multiplexed onto the pins. The third bus cycle is a page miss, so RAS is precharged before the end of the bus cycle and no extra precharge delay is incurred. CLKIN A[31:0] Row Column Column Page Hit RAS[1] or [0] Row Column Page Miss RNCN=1 RCD=0 CAS[3:0] CAS=01 DRAMW D[31:0] Bus Cycle 1 Bus Cycle 2 Bus Cycle 3 Figure 11-9. Continuous Page-Mode Operation If a write cycle hits in the page, CAS must be delayed by one clock to allow data to become valid, as shown in Figure 11-10. 11-14 MCF5407 User's Manual Asynchronous Operation CLKIN A[31:0] Row Column Column Page Hit RAS[1] or [0] Page Miss RCD = 0 CAS[3:0] CAS = 01 DRAMW D[31:0] Bus Cycle 1 Bus Cycle 2 Figure 11-10. Write Hit in Continuous Page Mode 11.3.3.4 Extended Data Out (EDO) Operation EDO is a variation of page mode that allows the DRAM to continue driving data out of the device while CAS is precharging. To support EDO DRAMs, the DRAM controller delays internal termination of the cycle by one clock so data can continue to be captured as CAS is being precharged. For data to be driven by the DRAMs, RAS is held after CAS is negated. EDO operation does not affect write operations. EDO DRAMs can be used in continuous page or burst page modes. Single accesses not followed by a hit in the page look like non-page-mode accesses. Figure 11-11 shows four consecutive EDO accesses. Note that data is sampled after CAS is negated and that on the last page access, CAS is held until after data is sampled to assure that the data is driven. This allows RAS to be precharged before the end of the cycle. CLKIN A[31:0] RAS[1] or [0] RCD = 0 CAS[3:0] CAS = 00 DRAMW D[31:0] Figure 11-11. EDO Read Operation (3-2-2-2) Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-15 Synchronous Operation 11.3.3.5 Refresh Operation The DRAM controller supports CAS-before-RAS refresh operations that are not synchronized to bus activity. A special DRAMW pin is provided so refresh can occur regardless of the state of the processor bus. When the refresh counter rolls over, it sets an internal flag to indicate that a refresh is pending. If that happens during a continuous page-mode access, the page is closed (RAS precharged) when the data transfer completes to allow the refresh to occur. The flag is cleared when the refresh cycle is run. Both memory blocks are simultaneously refreshed as determined by the DCR. DRAM accesses are delayed during refresh. Only an active bus access to a DRAM block can delay refresh. Figure 11-12 shows a bus cycle delayed by a refresh operation. Notice that DRAMW is forced high during refresh. The row address is held until the pending DRAM access. CLKIN A[31:0] RAS[1] or [0] RRA = 01 RRP = 01 CAS[3:0] DRAMW Refresh Access Figure 11-12. DRAM Access Delayed by Refresh 11.4 Synchronous Operation By running synchronously with the system clock instead of responding to asynchronous control signals, SDRAM can (after an initial latency period) be accessed on every clock; 5-1-1-1 is a typical MCF5407 burst rate to SDRAM. Note that because the MCF5407 cannot have more than one page open at a time, it does not support interleaving. SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not only must they manage addresses and data, but they must send special commands for such functions as precharge, read, write, burst, auto-refresh, and various combinations of these functions. Table 11-10 lists common SDRAM commands. 11-16 MCF5407 User's Manual Synchronous Operation Table 11-10. SDRAM Commands Command Definition ACTV Activate. Executed before READ or WRITE executes; SDRAM registers and decodes row address. MRS Mode register set. NOP No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; RAS asserted. PALL Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is opened. READ Read access. SDRAM registers column address and decodes that a read access is occurring. REF Refresh. Refreshes internal bank rows of an SDRAM component. SELF Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode. SELFX Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared. WRITE Write access. SDRAM registers column address and decodes that a write access is occurring. SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data pipelines and commands to initiate special actions. Commands are issued to memory using specific encodings on address and control pins. Soon after system reset, a command must be sent to the SDRAM mode register to configure SDRAM operating parameters. Note that, after synchronous operation is selected by setting DCR[SO], DRAM controller registers reflect the synchronous operation and there is no way to return to asynchronous operation without resetting the processor. 11.4.1 DRAM Controller Signals in Synchronous Mode Table 11-11 shows the behavior of DRAM signals in synchronous mode. Table 11-11. Synchronous DRAM Signal Connections Signal Description SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SRAS should be connected to the corresponding SDRAM SRAS. Do not confuse SRAS with the DRAM controller's RAS[1:0], which should not be interfaced to the SDRAM SRAS signals. SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SCAS should be connected to the corresponding signal labeled SCAS on the SDRAM. Do not confuse SCAS with the DRAM controller's CAS[3:0] signals. DRAMW DRAM read/write. Asserted for write operations and negated for read operations. RAS[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF5407. One RAS signal selects one SDRAM block and connects to the corresponding CS signals. SCKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SCKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SCKE to provide command-bit functionality. CAS[3:0] Column address strobe. For synchronous operation, CAS[3:0] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-17 Synchronous Operation Table 11-11. Synchronous DRAM Signal Connections (Continued) Signal CLKIN Description Bus clock output. Connects to the CLK input of SDRAMs. EDGESEL Synchronous edge select. Provides additional output hold time for signals that interface to external SDRAMs. EDGESEL supports the three following modes for SDRAM interface signals: * Tied high. Signals change on the rising edge of CLKIN. * Tied low. Signals change on the falling edge of CLKIN. * Tied to buffered CLKIN. Signals change on the rising edge of the buffered clock. EDGESEL can provide additional output hold time for SDRAM interface signals, however the SDRAM clock and CLKIN frequencies must be the same. See Section 11.4.2, "Using Edge Select (EDGESEL)." Figure 11-13 shows a typical signal configuration for synchronous mode. MCF5407 A[31:0] D[31:0] CAS DRAMW SCAS SRAS SCKE SDRAM ADDRESS DATA DQM WE CAS RAS CKE 1 EDGESEL CLK CLKIN 1 Trace CLKIN length from buffer to CLK must equal length from buffer to EDGESEL. Figure 11-13. MCF5407 SDRAM Interface 11.4.2 Using Edge Select (EDGESEL) EDGESEL can ease system-level timings (note that the optional buffer in Figure 11-13 is for memories that need extra delay). The clock at the input to the SDRAM is monitored and data is held until the next edge of the bus clock, adding required output hold time to the address, data, and control signals. To generate SDRAM interface timing, address, data, and control signals are clocked through a two-stage shift register. The first stage is clocked on the rising edge of CLKIN; the second is clocked on the falling edge. This makes the signal available for up to an additional half bus clock cycle, of which only a small amount is needed for proper timing. Using the connection shown in Figure 11-13 ensures that data remains held for a longer time after the rising edge of the SDRAM clock input. This helps to match the MCF5407 output timing with the SDRAM clock. Figure 11-14 shows the output wave forms for the interface signals changing on the rising edge (A) and falling edge (B) of CLKIN as determined by whether EDGESEL is tied high or low. It also shows timing (C) with EDGESEL tied to buffered CLKIN. 11-18 MCF5407 User's Manual Synchronous Operation CLKIN CLKIN Address/ Data VALID VALID VALID Address/ Data VALID A: Address and Data Timing with EDGESEL Tied High VALID VALID VALID B: Address and Data Timing with EDGESEL Tied Low Buffer Delay CLKIN Buffered CLKIN Address/ Data VALID VALID VALID VALID C: Address and Data Timing with EDGESEL Tied to Buffered Clock Figure 11-14. Using EDGESEL to Change Signal Timing 11.4.3 Synchronous Register Set The memory map in Table 11-1 is the same for both synchronous and asynchronous operation. However, some bits are different, as noted in the following sections. 11.4.3.1 DRAM Control Register (DCR) in Synchronous Mode The DRAM control register (DCR), Figure 11-15, controls refresh logic. 15 14 Field SO -- Reset 0 13 12 NAM COC 11 10 IS 9 8 7 6 RTIM 5 4 3 2 1 0 RC Uninitialized R/W R/W Addr MBAR + 0x100 Figure 11-15. DRAM Control Register (DCR) (Synchronous Mode) Table 11-12 describes DCR fields. Table 11-12. DCR Field Descriptions (Synchronous Mode) Bits Name Description 15 SO Synchronous operation. Selects synchronous or asynchronous mode. When in synchronous mode, the DRAM controller can be switched to ADRAM mode only by resetting the MCF5407. 0 Asynchronous DRAMs. Default at reset. 1 Synchronous DRAMs 14 -- Reserved, should be cleared. 13 NAM No address multiplexing. Some implementations require external multiplexing. For example, when linear addressing is required, the DRAM should not multiplex addresses on DRAM accesses. 0 The DRAM controller multiplexes the external address bus to provide column addresses. 1 The DRAM controller does not multiplex the external address bus to provide column addresses. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-19 Synchronous Operation Table 11-12. DCR Field Descriptions (Synchronous Mode) (Continued) Bits Name Description 12 COC Command on SDRAM clock enable (SCKE). Implementations that use external multiplexing (NAM = 1) must support command information to be multiplexed onto the SDRAM address bus. 0 SCKE functions as a clock enable; self-refresh is initiated by the DRAM controller through DCR[IS]. 1 SCKE drives command information. Because SCKE is not a clock enable, self-refresh cannot be used (setting DCR[IS]). Thus, external logic must be used if this functionality is desired. External multiplexing is also responsible for putting the command information on the proper address bit. 11 IS Initiate self-refresh command. 0 Take no action or issue a SELFX command to exit self refresh. 1 If DCR[COC] = 0, the DRAM controller sends a SELF command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared, at which point the controller sends a SELFX command for the SDRAMs to exit self-refresh. The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period. 10-9 RTIM Refresh timing. Determines the timing operation of auto-refresh in the DRAM controller. Specifically, it determines the number of clocks inserted between a REF command and the next possible ACTV command. This same timing is used for both memory blocks controlled by the DRAM controller. This corresponds to tRC in the SDRAM specifications. 00 3 clocks 01 6 clocks 1x 9 clocks 8-0 RC Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is (RC + 1) * 16. Refresh can range from 16-8192 bus clocks to accommodate both standard and low-power DRAMs with bus clock operation from less than 2 MHz to greater than 50 MHz. The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 mS of refresh every 15.625 s for each row (625 bus clocks at 40 MHz). This operation is the same as in asynchronous mode. # of bus clocks = 625 = (RC field + 1) * 16 RC = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, RC = 0x26. 11.4.3.2 DRAM Address and Control Registers (DACR0/DACR1) in Synchronous Mode The DRAM address and control registers (DACR0 and DACR1), shown in Figure 11-16, contain the base address compare value and the control bits for both memory blocks 0 and 1 of the DRAM controller. Address and timing are also controlled by bits in DACRn. 31 Field Reset 18 BA Uninitialized 17 16 -- 15 14 13 RE -- CASL -- 0 12 11 10 9 CBM Uninitialized R/W R/W Addr MBAR+0x108 (DACR0); 0x110(DACR1) 8 7 6 -- IMRS 0 5 4 PS MCF5407 User's Manual 2 1 0 IP PM -- Uninitialized Figure 11-16. DACR0 and DACR1 Registers (Synchronous Mode) 11-20 3 Synchronous Operation Table 11-13 describes DACRn fields. Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode) Bit Name 31-18 BA Base address register. With DCMR[BAM], determines the address range in which the associated DRAM block is located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the same as in asynchronous operation. 17-16 -- Reserved, should be cleared. 15 RE Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM block. 0 Do not refresh associated DRAM block 1 Refresh associated DRAM block 14 -- Reserved, should be cleared. 13-12 Description CASL CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature: Number of Bus Clocks Parameter CASL= 00 CASL = 01 CASL= 10 CASL= 11 11 10-8 7 -- CBM -- tRCD--SRAS assertion to SCAS assertion 1 2 3 3 tCASL--SCAS assertion to data out 1 2 3 3 tRAS--ACTV command to precharge command 2 4 6 6 tRP--Precharge command to ACTV command 1 2 3 3 tRWL,tRDL--Last data input to precharge command 1 1 1 1 tEP--Last data out to precharge command) 1 1 1 1 Reserved, should be cleared. Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and bank select lines to correspond to different addresses, these resources are programmable. CBM determines the addresses onto which these functions are multiplexed. CBM Command Bit Bank Select Bits 000 17 18 and up 001 18 19 and up 010 19 20 and up 011 20 21 and up 100 21 22 and up 101 22 23 and up 110 23 24 and up 111 24 25 and up This encoding and the address multiplexing scheme handle common SDRAM organizations. Bank select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits. Reserved, should be cleared. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-21 Synchronous Operation Table 11-13. DACR0/DACR1 Field Descriptions (Synchronous Mode) (Continued) Bit Name Description IMRS Initiate mode register set (MRS) command. Setting IMRS generates a MRS command to the associated SDRAMs. In initialization, IMRS should be set only after all DRAM controller registers are initialized and PALL and REFRESH commands have been issued. After IMRS is set, the next access to an SDRAM block programs the SDRAM's mode register. Thus, the address of the access should be programmed to place the correct mode information on the SDRAM address pins. Because the SDRAM does not register this information, it doesn't matter if the IMRS access is a read or a write or what, if any, data is put onto the data bus. The DRAM controller clears IMRS after the MRS command finishes. 0 Take no action 1 Initiate MRS command 5-4 PS Port size. Indicates the port size of the associated block of SDRAM, which allows for dynamic sizing of associated SDRAM accesses. PS functions the same in asynchronous operation. 00 32-bit port 01 8-bit port 1x 16-bit port 3 IP Initiate precharge all (PALL) command. The DRAM controller clears IP after the PALL command is finished. Accesses via IP should be no wider than the port size programmed in PS. 0 Take no action. 1 A PALL command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the PALL command to the SDRAM block. 2 PM Page mode. Indicates how the associated SDRAM block supports page-mode operation. 0 Page mode on bursts only. The DRAM controller dynamically bursts the transfer if it falls within a single page and the transfer size exceeds the port size of the SDRAM block. After the burst, the page closes and a precharge is issued. 1 Continuous page mode. The page stays open and only SCAS needs to be asserted for sequential SDRAM accesses that hit in the same page, regardless of whether the access is a burst. 1-0 -- Reserved, should be cleared. 6 11.4.3.3 DRAM Controller Mask Registers (DMR0/DMR1) The DMRn, Figure 11-17, include mask bits for the base address and for address attributes. They are the same as in asynchronous operation. 31 Field 18 17 BAM 9 -- Reset 8 7 6 5 4 3 Uninitialized R/W R/W Addr MBAR + 0x10C (DMR0), 0x114 (DMR1) Figure 11-17. DRAM Controller Mask Registers (DMR0 and DMR1) Table 11-14 describes DMRn fields. 11-22 MCF5407 User's Manual 2 1 0 WP -- C/I AM SC SD UC UD V 0 Synchronous Operation Table 11-14. DMR0/DMR1 Field Descriptions Bits Name Description 31-18 BAM Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various DRAM sizes. Mask bits need not be contiguous (see Section 11.5, "SDRAM Example.") 0 The associated address bit is used in decoding the DRAM hit to a memory block. 1 The associated address bit is not used in the DRAM hit decode. 17-9 -- 8 WP 7 -- 6-1 AMx Reserved, should be cleared. Write protect. Determines whether the associated block of DRAM is write protected. 0 Allow write accesses 1 Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs. Reserved, should be cleared. Address modifier masks. Determine which accesses can occur in a given DRAM block. 0 Allow access type to hit in DRAM 1 Do not allow access type to hit in DRAM Bit C/I 0 V Associated Access Type CPU space/interrupt acknowledge Access Definition MOVEC instruction or interrupt acknowledge cycle AM Alternate master External or DMA master SC Supervisor code Any supervisor-only instruction access SD Supervisor data Any data fetched during the instruction access UC User code Any user instruction UD User data Any user data Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded. 0 Do not decode DRAM accesses. 1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded. 11.4.4 General Synchronous Operation Guidelines To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller provides SDRAM control signals as well as a multiplexed row address and column address to the SDRAM. When SDRAM blocks are accessed, the DRAM controller can operate in either burst or continuous page mode. The following sections describe the DRAM controller interface to SDRAM, the supported bus transfers, and initialization. 11.4.4.1 Address Multiplexing Table 11-6 shows the generic address multiplexing scheme for SDRAM configurations. All possible address connection configurations can be derived from this table. The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the MCF5407 to SDRAM. To use the Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-23 Synchronous Operation tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5407, which is not necessarily the SDRAM port size. For example, if two 1M x 16-bit SDRAMs together form a 2M x 32-bit memory, the port size is 32 bits. Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected. Table 11-15. MCF5407 to SDRAM Interface (8-Bit Port, 9-Column Address Lines) MCF5407 A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 14 13 12 11 10 9 Column 0 1 2 3 4 5 6 7 8 SDRAM Pins 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Table 11-16. MCF5407 to SDRAM Interface (8-Bit Port,10-Column Address Lines) MCF5407 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 14 13 12 11 10 9 19 Column 0 1 2 3 4 5 6 7 8 18 SDRAM Pins 20 21 22 23 24 25 26 27 28 29 30 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Table 11-17. MCF5407 to SDRAM Interface (8-Bit Port,11-Column Address Lines) MCF5407 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 14 13 12 11 10 9 19 21 Column 0 1 2 3 4 5 6 7 8 18 20 SDRAM Pins 22 23 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Table 11-18. MCF5407 to SDRAM Interface (8-Bit Port,12-Column Address Lines) MCF5407 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 14 13 12 11 10 9 19 21 23 Column 0 1 2 3 4 5 6 7 8 18 20 22 SDRAM Pins 11-24 31 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 MCF5407 User's Manual Synchronous Operation Table 11-19. MCF5407 to SDRAM Interface (8-Bit Port,13-Column Address Lines) MCF5407 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 16 15 14 13 12 11 10 9 19 21 23 25 0 1 2 3 4 5 6 7 8 18 20 22 24 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Table 11-20. MCF5407 to SDRAM Interface (16-Bit Port, 8-Column Address Lines) MCF5407 A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 Column 1 2 3 4 5 6 7 8 SDRAM Pins 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Table 11-21. MCF5407 to SDRAM Interface (16-Bit Port, 9-Column Address Lines) MCF5407 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 18 Column 1 2 3 4 5 6 7 8 17 SDRAM Pins 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Table 11-22. MCF5407 to SDRAM Interface (16-Bit Port, 10-Column Address Lines) MCF5407 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 18 20 21 22 23 24 25 26 27 28 29 30 31 Column 1 2 3 4 5 6 7 8 17 19 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Table 11-23. MCF5407 to SDRAM Interface (16-Bit Port, 11-Column Address Lines) MCF5407 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 16 15 14 13 12 11 10 9 18 20 22 Column 1 2 3 4 5 6 7 8 17 19 21 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 23 24 25 26 27 28 29 Chapter 11. Synchronous/Asynchronous DRAM Controller Module 30 31 11-25 Synchronous Operation Table 11-24. MCF5407 to SDRAM Interface (16-Bit Port, 12-Column Address Lines) MCF5407 A16 A15 A14 A13 A12 A11 A10 Pins A9 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31 Row 16 15 14 13 12 11 10 9 18 20 22 24 Column 1 2 3 4 5 6 7 8 17 19 21 23 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 25 26 27 28 29 30 31 A10 A11 A12 A13 A14 A15 A16 A17 A18 Table 11-25. MCF5407 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) MCF5407 A16 A15 A14 A13 A12 A11 A10 Pins Row 16 15 14 13 12 11 A9 10 A18 A20 A22 A24 A26 A27 A28 A29 A30 A31 9 18 20 Column 1 2 3 4 5 6 7 8 17 19 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 22 24 26 21 23 25 27 28 29 30 31 A10 A11 A12 A13 A14 A15 A16 A17 Table 11-26. MCF5407 to SDRAM Interface (32-Bit Port, 8-Column Address Lines) MCF5407 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 Column 2 3 4 5 6 7 8 16 SDRAM Pins 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Table 11-27. MCF5407 to SDRAM Interface (32-Bit Port, 9-Column Address Lines) MCF5407 A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 19 Column 2 3 4 5 6 7 8 16 18 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 20 21 22 23 24 25 26 27 28 29 30 31 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Table 11-28. MCF5407 to SDRAM Interface (32-Bit Port, 10-Column Address Lines) MCF5407 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 19 21 22 23 24 25 26 27 28 29 30 31 Column 2 3 4 5 6 7 8 16 18 20 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 11-26 MCF5407 User's Manual Synchronous Operation Table 11-29. MCF5407 to SDRAM Interface (32-Bit Port, 11-Column Address Lines) MCF5407 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 24 25 26 27 28 29 30 31 Table 11-30. MCF5407 to SDRAM Interface (32-Bit Port, 12-Column Address Lines) MCF5407 A15 A14 A13 A12 A11 A10 Pins A9 A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Row 15 14 13 12 11 10 9 17 19 21 23 25 Column 2 3 4 5 6 7 8 16 18 20 22 24 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 26 27 28 29 30 31 A10 A11 A12 A13 A14 A15 A16 A17 11.4.4.2 Interfacing Example The tables in the previous section can be used to configure the interface in the following example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the MCF5407, the connections would be as shown in Table 11-31. Table 11-31. SDRAM Hardware Connections SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1 MCF5407 Pins A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 11.4.4.3 Burst Page Mode SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SCAS is issued, the SDRAM accepts a new address and asserts SCAS every clock for as long as accesses are in that page. In burst page mode, there are multiple read or write operations for every ACTV command in the SDRAM if the requested transfer size exceeds the port size of the associated SDRAM. The primary cycle of the transfer generates the ACTV and READ or WRITE commands; secondary cycles generate only READ or WRITE commands. As soon as the transfer completes, the PALL command is generated to prepare for the next access. Note that in synchronous operation, burst mode and address incrementing during burst cycles are controlled by the MCF5407 DRAM controller. Thus, instead of the SDRAM enabling its internal burst incrementing capability, the MCF5407 controls this function. This means that the burst function that is enabled in the mode register of SDRAMs must be disabled when interfacing to the MCF5407. Figure 11-18 shows a burst read operation. In this example, DACR[CASL] = 01, for an SRAS-to-SCAS delay (tRCD) of 2 CLKIN cycles. Because tRCD is equal to the read CAS Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-27 Synchronous Operation latency (SCAS assertion to data out), this value is also 2 CLKIN cycles. Notice that NOPs are executed until the last data is read. A PALL command is executed one cycle after the last data transfer. CLKIN A[31:0] Row Column Column Column Column SRAS tRCD = 2 SCAS tEP DRAMW tCASL = 2 D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP READ NOP NOP PALL Figure 11-18. Burst Read SDRAM Access Figure 11-19 shows the burst write operation. In this example, DACR[CASL] = 01, which creates an SRAS-to-SCAS delay (tRCD) of 2 CLKIN cycles. Note that data is available upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read cycle with the same tRCD. The next bus cycle is initiated sooner, but cannot begin an SDRAM cycle until the precharge-to-ACTV delay completes. 11-28 MCF5407 User's Manual Synchronous Operation CLKIN A[31:0] Row Column Column Column Column SRAS tRP SCAS tCASL = 2 tRWL DRAMW D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP WRITE NOP PALL Figure 11-19. Burst Write SDRAM Access Accesses in synchronous burst page mode always cause the following sequence: 1. 2. 3. 4. 5. 6. command NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no NOP commands). Required number of READ or WRITE commands to service the transfer size with the given port size. Some transfers need more NOP commands to assure the ACTV-to-precharge delay. PALL command Required number of idle clocks inserted to assure precharge-to-ACTV delay. ACTV 11.4.4.4 Continuous Page Mode Continuous page mode is identical to burst page mode, except that it allows the processor core to handle successive bus cycles that hit the same page without having to close the page. When the current bus cycle finishes, the MCF5407 core internal pipelined bus can predict whether the upcoming cycle will hit in the same page. * If the next bus cycle is not pending or misses in the page, the PALL command is generated to the SDRAM. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-29 Synchronous Operation * If the next bus cycle is pending and hits in the page, the page is left open, and the next SDRAM access begins with a READ or WRITE command. Because of the nature of the internal CPU pipeline this condition does not occur often, however, the use of continuous page mode is recommended because it can provide a slight performance increase. Figure 11-20 shows two read accesses in continuous page mode. Note that there is no precharge between the two accesses. Also notice that the second cycle begins with a read operation with no ACTV command. CLKIN Row A[31:0] Column Column SRAS SCAS tEP tRCD = 2 DRAMW tCASL = 2 tCASL = 2 D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP READ NOP READ NOP NOP PALL Figure 11-20. Synchronous, Continuous Page-Mode Access--Consecutive Reads Figure 11-21 shows a write followed by a read in continuous page mode. Because the bus cycle is terminated with a WRITE command, the second cycle begins sooner after the write than after the read. A read requires data to be returned before the bus cycle can terminate. Note that in continuous page mode, secondary accesses output the column address only. 11-30 MCF5407 User's Manual Synchronous Operation CLKIN Row A[31:0] Column Column SRAS SCAS tEP tRCD = 3 DRAMW tCASL = 3 D[31:0] RAS[0] or [1] CAS[3:0] ACTV NOP WRITE NOP READ NOP NOP NOP PALL Figure 11-21. Synchronous, Continuous Page-Mode Access--Read after Write 11.4.4.5 Auto-Refresh Operation The DRAM controller is equipped with a refresh counter and control. This logic is responsible for providing timing and control to refresh the SDRAM. Once the refresh counter is set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh request flag is set and the counter begins counting down again. The DRAM controller completes any active burst operation and then performs a PALL operation. The DRAM controller then initiates a refresh cycle and clears the refresh request flag. This refresh cycle includes a delay from any precharge to the auto-refresh command, the auto-refresh command, and then a delay until any ACTV command is allowed. Any SDRAM access initiated during the auto-refresh cycle is delayed until the cycle is completed. Figure 11-22 shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh request becomes active. The request is delayed by the precharge to ACTV delay programmed into the active SDRAM bank by the CAS bits. The REF command is then generated and the delay required by DCR[RTIM] is inserted before the next ACTV command is generated. In this example, the next bus cycle is initiated, but does not generate an SDRAM access until TRC is finished. Because both chip selects are active during the REF command, it is passed to both blocks of external SDRAM. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-31 Synchronous Operation CLKIN A[31:0] SRAS tRC = 6 tRCD = 2 SCAS DRAMW RAS[0] or [1] PALL NOP REF NOP ACTV Figure 11-22. Auto-Refresh Operation 11.4.4.6 Self-Refresh Operation Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS]. When IS is set, the SELF command is sent to the SDRAM. When IS is cleared, the SELFX command is sent to the DRAM controller. Figure 11-23 shows the self-refresh operation. CLKIN SRAS tRCD = 2 SCAS tRC = 6 DRAMW RAS[0] or [1] SCKE (DCR[COC] = 0) PALL NOP SELF SelfRefresh Active SELFX NOP First Possible ACTV Figure 11-23. Self-Refresh Operation 11.4.5 Initialization Sequence Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller 11-32 MCF5407 User's Manual Synchronous Operation supports this sequence with the following procedure: 1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any action is taken on the SDRAMs. This is normally around 100 s. 2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable PALL or REF commands. 3. Issue a PALL command to the SDRAMs by setting DCR[IP] and accessing a SDRAM location. Wait the time (determined by tRP) before any other execution. 4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur. 5. Before issuing the MRS command, determine if the DMR mask bits need to be modified to allow the MRS to execute properly 6. Issue the MRS command by setting DACR[IMRS] and accessing a location in the SDRAM. Note that mode register settings are driven on the SDRAM address bus, so care must be taken to change DMR[BAM] if the mode register configuration does not fall in the address range determined by the address mask bits. After the mode register is set, DMR mask bits can be restored to their desired configuration. 11.4.5.1 Mode Register Settings It is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency, through the SDRAM component's mode register. CAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates at a CAS latency of 1, 2, or 3. Although the MCF5407 DRAM controller supports bursting operations, it does not use the bursting features of the SDRAMs. Because the MCF5407 can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a fixed burst length in the SDRAMs mode register becomes problematic. Therefore, the MCF5407 DRAM controller generates the burst cycles rather than the SDRAM device. Because the MCF5407 generates a new address and a READ or WRITE command for each transfer within the burst, the SDRAM mode register should be set either to a burst length of one or to not burst. This allows bursting to be controlled by the MCF5407 instead. The SDRAM mode register is written by setting the associated block's DACR[IMRS]. First, the base address and mask registers must be set to the appropriate configuration to allow the mode register to be set. Note that improperly set DMR mask bits may prevent access to the mode register address. Thus, the user should determine the mapping of the mode register address to the MCF5407 address bits to find out if an access is blocked. If the DMR setting prohibits mode register access, the DMR should be reconfigured to enable the access and then set to its necessary configuration after the MRS command executes. The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the SDRAM address space generates the MRS command to that SDRAM. The address of the access should be selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed for the MRS command. The MRS Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-33 SDRAM Example access can be a read or write. The important thing is that the address output of that access needs the correct mode programming information on the correct address bits. Figure 11-24 shows the MRS command, which occurs in the first clock of the bus cycle. CLKIN A[31:0] SRAS, SCAS DRAMW D[31:0] RAS[1] or [0] MRS Figure 11-24. Mode Register Set (MRS) Command 11.5 SDRAM Example This example interfaces a 2M x 32-bit x 4 bank SDRAM component to a MCF5407 operating at 40 MHz. Table 11-32 lists design specifications for this example. Table 11-32. SDRAM Example Specifications Parameter Speed grade (-8E) Specification 40 MHz (25-nS period) 10 rows, 8 columns Two bank-select lines to access four internal banks ACTV-to-read/write delay (tRCD) Period between auto refresh and ACTV command (tRC) ACTV command to precharge command (tRAS) Precharge command to ACTV command (tRP) 20 nS (min.) 70 nS 48 nS (min.) 20 nS (min.) Last data input to PALL command (tRWL) 1 bus clock (25 nS) Auto refresh period for 4096 rows (tREF) 64 mS 11.5.1 SDRAM Interface Configuration To interface this component to the MCF5407 DRAM controller, use the connection table that corresponds to a 32-bit port size with 8 columns (Table 11-26). Two pins select one of four banks when the part is functional. Table 11-33 shows the proper hardware hook-up. 11-34 MCF5407 User's Manual SDRAM Example Table 11-33. SDRAM Hardware Connections MCF5407 Pins A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1 11.5.2 DCR Initialization At power-up, the DCR has the following configuration if synchronous operation and SDRAM address multiplexing is desired. 15 Field SO Setting 1 14 13 res X 0 (hex) 12 NAM COC 0 11 IS 0 10 9 8 0 RTIM 0 8 0 RC 0 0 0 0 1 0 0 2 1 1 0 6 Figure 11-25. Initialization Values for DCR This configuration results in a value of 0x8026 for DCR, as shown in Table 11-34. Table 11-34. DCR Initialization Values Bits Name Setting Description 15 SO 1 Indicating synchronous operation 14 -- x Don't care (reserved) 13 NAM 0 Indicating SDRAM controller multiplexes address lines internally 12 COC 0 SCKE is used as clock enable instead of command bit because user is not multiplexing address lines externally and requires external command feed. 11 IS 0 At power-up, allowing power self-refresh state is not appropriate because registers are being set up. 10-9 RTIM 00 8-0 RC 0x26 Because tRC value is 70 nS, indicating a 3-clock refresh-to-ACTV timing. Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every 15.625 s for each row, or 625 bus clocks at 40 MHz. Because DCR[RC] is incremented by 1 and multiplied by 16, RC = (625 bus clocks/16) -1 = 38.06 = 0x38 11.5.3 DACR Initialization As shown in Figure 11-26, in this example the SDRAM is programmed to access only the second 512-Kbyte block of each 1-Mbyte partition in the SDRAM (each 16 Mbytes). The starting address of the SDRAM is 0xFF80_0000. Continuous page mode feature is used. Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-35 SDRAM Example Accessible Memory SDRAM Component Bank 0 Bank 1 512 Kbyte Bank 2 512 Kbyte 1 Mbyte Bank 3 512 Kbyte 1 Mbyte 512 Kbyte 1 Mbyte 512 Kbyte 1 Mbyte 512 Kbyte 512 Kbyte 512 Kbyte Figure 11-26. SDRAM Configuration The DACRs should be programmed as shown in Figure 11-27. 31 18 Field Setting (hex) Field Setting 15 14 -- 1111_1111_1000_10 xx 0 X (hex) 15 13 12 11 CASL -- 00 X 0 16 -- 15 RE 17 BA 8 10 8 8 7 6 3 2 CBM -- IMRS PS IP PM 011 X 0 00 0 1 3 5 4 0 1 0 -- xx 4 Figure 11-27. DACR Register Configuration This configuration results in a value of DACR0 = 0xFF88_0304, as described in Table 11-35. DACR1 initialization is not needed because there is only one block. Subsequently, DACR1[RE,IMRS,IP] should be cleared; everything else is a don't care. Table 11-35. DACR Initialization Values Bits Name Setting Description 31-18 BA Base address. So DACR0[31-16] = 0xFF88, which places the starting address of the SDRAM accessible memory at 0xFF88_0000. 17-16 -- Reserved. Don't care. 15 RE 14 -- 13-12 11 10-8 CASL 0 00 -- CBM 0, which keeps auto-refresh disabled because registers are being set up at this time. Reserved. Don't care. Indicates a delay of data 1 cycle after CAS is asserted Reserved. Don't care. 011 Command bit is pin 20 and bank selects are 21 and up. 7 -- 6 IMRS 0 Indicates MRS command has not been initiated. 5-4 PS 00 32-bit port. 3 IP 0 Indicates precharge has not been initiated. 11-36 Reserved. Don't care. MCF5407 User's Manual SDRAM Example Table 11-35. DACR Initialization Values Bits Name Setting 2 PM 1 1-0 -- Description Indicates continuous page mode Reserved. Don't care. 11.5.4 DMR Initialization In this example, again, only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank. In addition the SDRAM component is mapped only to readable and writable supervisor and user data. The DMRs have the following configuration. 31 Field Setting 17 1 X BAM 0 0 0 (hex) 0 0 0 0 0 15 9 X X X (hex) 0 1 X X 0 X 1 1 0 7 -- X 16 -- 0 0 Field Setting 18 X 4 8 7 6 5 4 3 2 1 0 WP -- C/I AM SC SD UC UD V 0 X 1 1 1 0 1 0 1 0 7 5 Figure 11-28. DMR0 Register With this configuration, the DMR0 = 0x0074_0075, as described in Table 11-36. Table 11-36. DMR0 Initialization Values Bits Name 31-16 BAM 15-9 -- Setting Description With bits 17 and 16 as don't cares, BAM = 0x0074, which leaves bank select bits and upper 512K select bits unmasked. Note that bits 22 and 21 are set because they are used as bank selects; bit 20 is set because it controls the 1-Mbyte boundary address. Reserved. Don't care. 8 WP 7 -- 0 Allow reads and writes 6 C/I 5 AM 1 Disable alternate master access 4 SC 1 Disable supervisor code accesses 3 SD 0 Enable supervisor data accesses 2 UC 1 Disable user code accesses 1 UD 0 Enable user data accesses 0 V 1 Enable accesses. Reserved 1 Disable CPU space access Chapter 11. Synchronous/Asynchronous DRAM Controller Module 11-37 SDRAM Example 11.5.5 Mode Register Initialization When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding MCF5407 address pins must be determined while being aware of masking requirements. Table 11-37 lists the desired initialization setting: Table 11-37. Mode Register Initialization MCF5407 Pins SDRAM Pins A20 A10 A19 A18 Mode Register Initialization Reserved X A9 WB 0 A8 Opmode 0 A17 A7 Opmode 0 A9 A6 CASL 0 A10 A5 CASL 0 A11 A4 CASL 1 A12 A3 BT 0 A13 A2 BL 0 A14 A1 BL 0 A15 A0 BL 0 Next, this information is mapped to an address to determine the hexadecimal value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X 0 0 0 X Field Setting (hex) 0 15 14 0 13 12 11 10 0 9 8 7 6 0 5 4 3 2 1 Field Setting (hex) 0 V 0 0 0 0 0 1 0 0 X X X 8 X X X X 0 X X 0 Figure 11-29. Mode Register Mapping to MCF5407 A[31:0] Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register bit is set, DMR0[19] must be set to enable masking. 11-38 MCF5407 User's Manual SDRAM Example 11.5.6 Initialization Code The following assembly code initializes the SDRAM example. Power-Up Sequence: move.w move.w move.l move.l move.l move.l #0x8026, d0 d0, DCR #0xFF880300, d0 d0, DACR0 #0x00740075, d0 d0, DMR0 //Initialize DCR //Initialize DACR0 //Initialize DMR0 Precharge Sequence: move.l move.l move.l move.l #0xFF880308, d0 d0, DACR0 #0xBEADDEED, d0 d0, 0xFF880000 //Set DACR0[IP] //Write to memory location to init. precharge Refresh Sequence: move.l move.l #0xFF888300, d0 d0, DACR0 //Enable refresh bit in DACR0 Mode Register Initialization Sequence: move.l #0x00600075, d0 move.l d0, DMR0 move.l #0xFF888340, d0 move.l d0, DACR0 move.l #0x00000000, d0 register move.l d0, 0xFF800800 //Mask bit 19 of address //Enable DACR0[IMRS]; DACR0[RE] remains set //Access SDRAM address to initialize Chapter 11. Synchronous/Asynchronous DRAM Controller Module mode 11-39 SDRAM Example 11-40 MCF5407 User's Manual Part III Peripheral Module Intended Audience Part III describes the operation and configuration of the MCF5407 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II. Contents It contains the following chapters: -- Chapter 12, "DMA Controller Module," provides an overview of the DMA controller module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail, showing timing diagrams for various operations. -- Chapter 13, "Timer Module," describes configuration and operation of the two general-purpose timer modules, timer 0 and timer 1. It includes programming examples. -- Chapter 14, "UART Modules," describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5407 and includes programming examples. Particular attention is given to the UART1 implementation of a synchronous interface that provides a controller for an 8- or 16-bit CODEC interface and an audio CODEC `97 (AC '97) digital interface. -- Chapter 15, "Parallel Port (General-Purpose I/O)," describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. It includes a code example for setting up the parallel port. Suggested Reading The following literature may be helpful with respect to the topics in Part III: Part III. Peripheral Module III-i Audio CODEC `97 Component Specification Acronyms and Abbreviations Table III-i describes acronyms and abbreviations used in Part III. Table III-i. Acronyms and Abbreviated Terms Term Meaning ADC Analog-to-digital conversion BIST Built-in self test CODEC Code/decode DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing EDO Extended data output (DRAM) FIFO First-in, first-out GPIO General-purpose I/O I2C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, first-out LRU Least recently used LSB Least-significant byte lsb Least-significant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter III-ii MCF5407 User's Manual Table III-i. Acronyms and Abbreviated Terms (Continued) Term Meaning PCLK Processor clock PLL Phase-locked loop PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part III. Peripheral Module III-iii III-iv MCF5407 User's Manual Chapter 12 DMA Controller Module This chapter describes the MCF5407 DMA controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. 12.1 Overview The direct memory access (DMA) controller module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module, shown in Figure 12-1, provides four channels that allow byte, word, or longword operand transfers. Each channel has a dedicated set of registers that define the source and destination addresses (SARn and DARn), byte count (BCRn), and control and status (DCRn and DSRn). Transfers can be dual or single address to off-chip devices or dual address to on-chip devices, such as UART, SDRAM controller, and parallel port. Channel 0 Channel 1 Channel 2 Channel 3 Internal Bus External Requests SAR0 SAR1 SAR2 SAR3 DAR0 DAR1 DAR2 DAR3 BCR0 BCR1 BCR2 BCR3 DCR0 DCR1 DCR2 DCR3 DSR0 DSR1 DSR2 DSR3 Channel Requests Interrupts Channel Attributes Channel Enables External Bus Address MUX MUX Control External Bus Size Current Master Attributes Arbitration/ Control Data Path Read Bus Data Data Path Control Write Bus Data Interface Bus Registered Bus Signals Figure 12-1. DMA Signal Diagram Chapter 12. DMA Controller Module 12-1 DMA Signal Description 12.1.1 DMA Module Features The DMA controller module features are as follows: * * * * * * * * * * * * Four fully independent, programmable DMA controller channels/bus modules Auto-alignment feature for source or destination accesses Dual- and single-address transfers Two external request pins (DREQ[1:0]) provided for channels 1 and 0 Two external acknowledge pins (DACK[1:0]) provided for channels 1 and 0 Channels 2 and 3 have request signals connected to the interrupt lines of UART0 and UART1, programmable through the channel select field MODCTL[DSL]. See Section 14.3.4, "Modem Control Register (MODCTL)." Channel arbitration on transfer boundaries Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer Continuous-mode and cycle-steal transfers Independent transfer widths for source and destination Independent source and destination address registers Data transfer can occur in as few as two clocks 12.2 DMA Signal Description Table 12-1 briefly describes the DMA module signals that provide handshake control for either a source or destination external device. Table 12-1. DMA Signals Signal I/O Description DREQ[1:0]/ PP[6:5] I External DMA request. DREQ[1:0] can serve as the DMA request inputs or as two parallel port bits. They are programmable individually through the PAR. A peripheral device asserts these inputs to request an operand transfer between it and memory. DREQ signals are asserted to initiate DMA accesses in the respective channels. The system should drive unused DREQ signals to logic high. Although each channel has an individual DREQ signal, in the MCF5407 only channels 0 and 1 connect to external DREQ pins. DREQ2 and DREQ3 are programmable for use with UART0 and UART1 through MODCTL[DSL]. See Section 14.3.4, "Modem Control Register (MODCTL)." TT[1:0]/ PP[1:0] O Transfer type. A DMA access is indicated by the transfer type pins, TT[1:0] = 01. The transfer modifier, TM[2:0], and DMA acknowledgement, DACK[1:0], configurations shown below are meaningful only if TT[1:0] = 01, indicating an external master or DMA access. 12-2 MCF5407 User's Manual DMA Signal Description Table 12-1. DMA Signals (Continued) Signal I/O Description TM[2:0]/ DACK[1:0] O Transfer modifier/DMA acknowledge. The MCF5407 TM[2:0] encodings are like the MCF5307, with functions shifted slightly, as Figure 12-2 shows. Dedicated DMA acknowledgement pins, DACK[1:0], are added and multiplexed as follows--TM[1:0]/DACK[1:0]/PP[3:2]. TM2 is still multiplexed only with PP4. Chapter 17, "Signal Descriptions," describes multiplexing. Although on the MCF5407, TM[2:0] can be programmed to be DMA acknowledge signals, bit positions of these encodings differ from the MCF5307. Single-address access indication is now encoded on TM2 when the PAR is set to enable the transfer modifier signal and an external or DMA transfer is occurring. This encoding is driven by TM0 on the MCF5307. In addition, DMA acknowledge signals are multiplexed with TM[1:0] on the MCF5407, as opposed to TM[2:1] providing DMA transfer information on the MCF5307. The MCF5407 encoding for TM[2:0], shown below describes when PAR is set to enable these signals and the IRQPAR is programmed to disable DACK[1:0]. Note that when DACK[1:0] are driven, TM2 is still driven if it is enabled through the PAR. To enable DACK[1:0], first enable TM[1:0] and then program the interrupt assignment register (IRQPAR) to enable bits 0-1. When IRQPAR[ENBDACK1] = 1 and TM1 is enabled, DACK1 for DMA channel 1 is driven in place of TM1 for DMA transfers. Clearing ENBDACK1 disables this function and only the TM1 encoding is driven. Likewise, setting ENBDACK0 enables DACK0 to be driven; clearing ENBDACK0 disables this function and drives the TM0 encoding. TM2 Encoding 0 Single-address access negated 1 Single-address access TM[1:0] Encoding 00 DMA acknowledge information not provided 01 DMA transfer, channel 0 10 DMA transfer, channel 1 11 Reserved The DMA transfer information on TM[1:0] can be provided on every DMA transfer or only on the last transfer by programming DCR[AT]. DACK[1:0] I/O DMA acknowledge. These signals provide an acknowledge of a DMA transfer. They can be programmed using DCR[AT] to assert on every transfer or only on the final transfer. Table 12-2 shows MCF5407 pin configurations based on PAR and IRQPAR configurations. Table 12-2. MCF5407 Signal Configurations for PP[4:2]/TM[2:0]/DACK[1:0] PAR Configuration 1 IRQPAR Configuration PP[4:2] TM[2:0] DACK[1:0] TM[2:0] disabled, PP[4:2] enabled ENBDACK[1-0] = 0 or 1 Driven Not driven Not driven TM[2:0] enabled ENBDACK[1-0] = 0 Not driven TM[2:0] driven Not driven TM[2:0] enabled ENBDACK[1-0] = 1 Not driven TM2 driven only Driven 1 Note that to enable DACK[1:0], PAR must first be programmed to enable TM[1:0]. Designers who used MCF5307 DMA channels should also note that the DMA byte count registers (BCR) for channels 0-3 exclusively support a 24-bit byte count. A 16-bit byte count register and MPARK[BCR24BIT] are no longer supported. As shown in Figure 12-2, when properly connected, TM[2:0] can be used in MCF5407 designs in the same manner as they were on MCF5307 designs or DACK[1:0] can be used for DMA transfers. Chapter 12. DMA Controller Module 12-3 DMA Transfer Overview MCF5307 Function Pin Pin MCF5407 Function Single/dual cycle access TM0 TM0 DMA 0 acknowledge DMA 0 acknowledge configuration TM1 TM1 DMA 1 acknowledge DMA 1 acknowledge configuration TM2 TM2 Single/dual cycle access Figure 12-2. MCF5307/MCF5407 TM[2:0] Pin Remapping 12.3 DMA Transfer Overview The DMA module usually transfers data faster than the ColdFire core can under software control. The term `direct memory access' refers to peripheral device's ability to access system memory directly, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four channels at once. The MCF5407 on-chip peripherals do not support single-address transfers. The processor generates DMA requests internally by setting DCR[START]; a device can generate a DMA request externally by using DREQ pins. The processor can program bus bandwidth for each channel. The channels support cycle-steal and continuous transfer modes; see Section 12.5.1, "Transfer Requests (Cycle-Steal and Continuous Modes)." The DMA controller supports dual- and single-address transfers as follows. In both, the DMA channel supports 32 address bits and 32 data bits. * Dual-address transfers--A dual-address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by an external device using DREQ. Two types of transfer can occur, a read from a source device or a write to a destination device; see Figure 12-3. Control and Data Memory/ Peripheral DMA Control and Data Memory/ Peripheral Figure 12-3. Dual-Address Transfer 12-4 MCF5407 User's Manual DMA Controller Module Programming Model * Single-address transfers--An external device can initiate a single-address transfer by asserting DREQ. The MCF5407 provides address and control signals for single-address transfers. The external device reads to or writes from the specified address, as Figure 12-4 shows. External logic is required. Write: Control Signals Memory DMA Data Control Signals Peripheral Read: Control Signals Memory DMA Data Control Signals Peripheral Figure 12-4. Single-Address Transfers Any operation involving the DMA module follows the same three steps: 1. Channel initialization--Channel registers are loaded with control information, address pointers, and a byte-transfer count. 2. Data transfer--The DMA accepts requests for operand transfers and provides addressing and bus control for the transfers. 3. Channel termination--Occurs after the operation is finished, either successfully or due to an error. The channel indicates the operation status in the channel's DSR, described in Section 12.4.5, "DMA Status Registers (DSR0-DSR3)." 12.4 DMA Controller Module Programming Model This section describes each internal register and its bit assignment. Note that there is no way to prevent a write to a control register during a DMA transfer. Table 12-3 shows the mapping of DMA controller registers. Chapter 12. DMA Controller Module 12-5 DMA Controller Module Programming Model Table 12-3. Memory Map for DMA Controller Module Registers DMA Channel MBAR Offset 0 0x300 Source address register 0 (SAR0) [p. 12-7] 0x304 Destination address register 0 (DAR0) [p. 12-7] 0x308 DMA control register 0 (DCR0) [p. 12-8] 1 2 3 [31:24] [23:16] [15:8] 0x30C Reserved Byte count register 0 (BCR0) [p. 12-7] 0x310 DMA status register 0 (DSR0) [p. 12-10] Reserved 0x314 DMA interrupt vector register 0 (DIVR0) [p. 12-11] Reserved 0x340 Source address register 1 (SAR1) [p. 12-7] 0x344 Destination address register 1 (DAR1) [p. 12-7] 0x348 DMA control register 1 (DCR1) [p. 12-8] 0x34C Reserved Byte count register 1 (BCR1) [p. 12-7] 0x350 DMA status register 1 (DSR1) [p. 12-10] Reserved 0x354 DMA interrupt vector register 1 (DIVR1) [p. 12-11] Reserved 0x380 Source address register 2 (SAR2) [p. 12-7] 0x384 Destination address register 2 (DAR2) [p. 12-7] 0x388 DMA control register 2 (DCR2) [p. 12-8] 0x38C Reserved Byte count register 2 (BCR2) [p. 12-7] 0x390 DMA status register 2 (DSR2) [p. 12-10] Reserved 0x394 DMA interrupt vector register 2 (DIVR2) [p. 12-11] Reserved 0x3C0 Source address register 3 (SAR3) [p. 12-7] 0x3C4 Destination address register 3 (DAR3) [p. 12-7] 0x3C8 DMA control register 3 (DCR3) [p. 12-8] 0x3CC Reserved Byte count register 3 (BCR3) [p. 12-7] 0x3D0 DMA status register 3 (DSR3) [p. 12-10] Reserved 0x3D4 DMA interrupt vector register 3 (DIVR3) [p. 12-11] Reserved NOTE: External masters cannot access MCF5407 on-chip memories or MBAR, but they can access DMA module registers. 12-6 MCF5407 User's Manual [7:0] DMA Controller Module Programming Model 12.4.1 Source Address Registers (SAR0-SAR3) SARn, Figure 12-5, contains the address from which the DMA controller requests data. In single-address mode, SARn provides the address regardless of the direction. 31 0 Field SAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W R/W Address MBAR + 0x300, 0x340, 0x380, 0x3C0 Figure 12-5. Source Address Registers (SARn) NOTE: SAR/DAR address ranges cannot be programmed to on-chip SRAM because it cannot be accessed by on-chip DMA. 12.4.2 Destination Address Registers (DAR0-DAR3) For dual-address transfers only, DARn, Figure 12-6, holds the address to which the DMA controller sends data. 31 0 Field DAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W Address R/W MBAR + 304, 0x344, 0x384, 0x3C4 Figure 12-6. Destination Address Registers (DARn) NOTE: On-chip DMAs do not maintain coherency with MCF5407 caches and so must not transfer data to cacheable memory. 12.4.3 Byte Count Registers (BCR0-BCR3) BCRn, Figure 12-7, holds the number of bytes yet to be transferred for a given block. BCRn decrements on the successful completion of the address transfer of either a write transfer in dual-address mode or any transfer in single-address mode. BCRn decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively. Chapter 12. DMA Controller Module 12-7 DMA Controller Module Programming Model 31 24 23 0 Field -- BCR Reset -- 0000_0000_0000_0000_0000_0000 R/W R/W Address MBAR + 0x30C, 0x34C, 0x38C, 0x3AC Figure 12-7. Byte Count Registers (BCRn) DSR[DONE], shown in Figure 12-9, is set when the block transfer is complete. When a transfer sequence is initiated and BCRn[BCR] is not divisible by 16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs. See Section 12.4.5, "DMA Status Registers (DSR0-DSR3)." 12.4.4 DMA Control Registers (DCR0-DCR3) DCRn, Figure 12-8, is used for configuring the DMA controller module. 31 30 Field INT EEXT 29 28 CS AA 27 25 BWC Reset 24 23 22 SAA S_RW SINC 21 20 SSIZE 19 DINC 18 17 DSIZE 16 START 0000_0000_0000_0000 R/W R/W 15 Field AT Reset 0 14 0 -- N/A R/W R/W Address MBAR + 0x308, 0x348, 0x388, 0x3A8 Figure 12-8. DMA Control Registers (DCRn) Table 12-4 describes DCR fields. Table 12-4. DCRn Field Descriptions Bits Name Description 31 INT Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition. 0 No interrupt is generated. 1 Internal interrupt signal is enabled. 30 EEXT Enable external request. Care should be taken because a collision can occur between the START bit and DREQ when EEXT = 1. 0 External request is ignored. 1 Enables external request to initiate transfer. Internal request is always enabled. It is initiated by writing a 1 to the START bit. 12-8 MCF5407 User's Manual DMA Controller Module Programming Model Table 12-4. DCRn Field Descriptions (Continued) Bits Name Description 29 CS Cycle steal. 0 DMA continuously makes read/write transfers until the BCR decrements to 0. 1 Forces a single read/write transfer per request. The request may be internal by setting the START bit, or external by asserting DREQ. 28 AA Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size. See Section 12.5.4.2, "Auto-Alignment." 0 Auto-align disabled 1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. 27-25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a multiple of the BWC value, the DMA releases the bus. 000 DMA has priority. It does not negate its request until its transfer completes. 001 16384 010 32768 011 65536 100 131072 101 262144 110 524288 111 1048576 24 SAA Single-address access. Determines whether the DMA channel is in dual- or single-address mode 0 Dual-address mode. 1 Single-address mode. The DMA provides an address from the SAR and directional control, bit S_RW, to allow two peripherals (one might be memory) to exchange data within a single access. Data is not stored by the DMA. 23 S_RW Single-address access read/write value. Valid only if SAA = 1. Specifies the value of the read signal during single-address accesses. This provides directional control to the bus controller. 0 Forces the read signal to 0. 1 Forces the read signal to 1. 22 SINC Source increment. Controls whether a source address increments after each successful transfer. 0 No change to SAR after a successful transfer. 1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size. 21-20 SSIZE Source size. Determines the data size of the source bus cycle for the DMA control module. 00 Longword 01 Byte 10 Word 11 Line 19 Destination increment. Controls whether a destination address increments after each successful transfer. 0 No change to the DAR after a successful transfer. 1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer. DINC 18-17 DSIZE Destination size. Determines the data size of the destination bus cycle for the DMA controller. 00 Longword 01 Byte 10 Word 11 Line 16 Start transfer. 0 DMA inactive 1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one clock and is always read as logic 0. START Chapter 12. DMA Controller Module 12-9 DMA Controller Module Programming Model Table 12-4. DCRn Field Descriptions (Continued) Bits Name Description 15 AT DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer or only the final transfer. 0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the result of an external request. 1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information is displayed for both the read and write cycles. 14-0 -- Reserved, should be cleared. 12.4.5 DMA Status Registers (DSR0-DSR3) In response to an event, the DMA controller writes to the appropriate DSRn bit, Figure 12-9. Only a write to DSRn[DONE] results in action. 7 6 5 4 3 2 1 0 Field -- CE BES BED -- REQ BSY DONE Reset -- 0 0 0 -- 0 0 0 R/W R/W Address MBAR + 0x310, 0x350, 0x390, 0x3D0 Figure 12-9. DMA Status Registers (DSRn) Table 12-5 describes DSRn fields. Table 12-5. DSRn Field Descriptions Bits Name Description 7 -- Reserved, should be cleared. 6 CE Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE]. 0 No configuration error exists. 1 A configuration error has occurred. 5 BES Bus error on source 0 No bus error occurred. 1 The DMA channel terminated with a bus error either during the read portion of a transfer or during an access in single-address mode (SAA = 1). 4 BED Bus error on destination 0 No bus error occurred. 1 The DMA channel terminated with a bus error during the write portion of a transfer. 3 -- Reserved, should be cleared. 2 REQ Request 0 No request is pending or the channel is currently active. Cleared when the channel is selected. 1 The DMA channel has a transfer remaining and the channel is not selected. 12-10 MCF5407 User's Manual DMA Controller Module Functional Description Table 12-5. DSRn Field Descriptions (Continued) Bits Name Description 1 BSY Busy 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. 1 BSY is set the first time the channel is enabled after a transfer is initiated. 0 DONE Transactions done. Set when all DMA controller transactions complete normally, as determined by transfer count and error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE before reprogramming the DMA. 0 Writing or reading a 0 has no effect. 1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used as an interrupt handler to clear the DMA interrupt and error bits. 12.4.6 DMA Interrupt Vector Registers (DIVR0-DIVR3) The contents of a DMA interrupt vector register (DIVRn), Figure 12-10, are driven onto the internal bus in response to an interrupt acknowledge cycle. 7 0 Field Interrupt Vector Bits Reset 0000_1111 R/W Address R/W MBAR + 0x314, 0x354, 0x394, 0x3D4 Figure 12-10. DMA Interrupt Vector Registers (DIVRn) 12.5 DMA Controller Module Functional Description In the following discussion, the term `DMA request' implies that DCR[START] or DCR[EEXT] is set, followed by assertion of DREQ. The START bit is cleared when the channel begins an internal access. Before initiating a dual-address access, the DMA module verifies that DCR[SSIZE,DSIZE] are consistent with the source and destination addresses. If the source and destination are not the same size, the configuration error bit, DSR[CE], is also set. If misalignment is detected, no transfer occurs, CE is set, and, depending on the DCR configuration, an interrupt event is issued. Note that if the auto-align bit, DCR[AA], is set, error checking is performed on appropriate registers. A read/write transfer reads bytes from the source address and writes them to the destination address. The number of bytes is the larger of the sizes specified by SSIZE and DSIZE. See Section 12.4.4, "DMA Control Registers (DCR0-DCR3)." Source and destination address registers (SAR and DAR) can be programmed in the DCR to increment at the completion of a successful transfer. BCR decrements when an address transfer write completes for a single-address access (DCR[SAA] = 0) or when SAA = 1. Chapter 12. DMA Controller Module 12-11 DMA Controller Module Functional Description 12.5.1 Transfer Requests (Cycle-Steal and Continuous Modes) The DMA channel supports internal and external requests. A request is issued by setting DCR[START] or by asserting DREQ. Setting DCR[EEXT] enables recognition of external interrupts. Internal interrupts are always recognized. Bus usage is minimized for either internal or external requests by selecting between cycle-steal and continuous modes. * * Cycle-steal mode (DCR[CS] = 1)--Only one complete transfer from source to destination occurs for each request. If DCR[EEXT] is set, a request can be either internal or external. Internal request is selected by setting DCR[START]. An external request is initiated by asserting DREQ while EEXT is set. Continuous mode (DCR[CS] = 0)--After an internal or external request, the DMA continuously transfers data until BCR reaches zero or a multiple of DCR[BWC] or DSR[DONE] is set. If BCR is a multiple of BWC, the DMA request signal is negated until the bus cycle terminates to allow the internal arbiter to switch masters. DCR[BWC] = 000 specifies the maximum transfer rate; other values specify a transfer rate limit. The DMA performs the specified number of transfers, then relinquishes bus control. The DMA negates its internal bus request on the last transfer before the BCR reaches a multiple of the boundary specified in BWC. On completion, the DMA reasserts its bus request to regain mastership at the earliest opportunity. The minimum time that the DMA loses bus control is one bus cycle. 12.5.2 Data Transfer Modes Each channel supports dual- and single-address transfers, described in the next sections. 12.5.2.1 Dual-Address Transfers Dual-address transfers consist of a source operand read and a destination operand write. The DMA controller module begins a dual-address transfer sequence when DCR[SAA] is cleared during a DMA request. If no error condition exists, DSR[REQ] is set. * * 12-12 Dual-address read--The DMA controller drives the SAR value onto the internal address bus. If DCR[SINC] is set, the SAR increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles complete (multiple reads if the destination size is wider than the source), the DMA initiates the write portion of the transfer. If a termination error occurs, DSR[BES,DONE] are set and DMA transactions stop. Dual-address write--The DMA controller drives the DAR value onto the address bus. If DCR[DINC] is set, DAR increments by the appropriate number of bytes at the completion of a successful write cycle. The BCR decrements by the appropriate number of bytes. DSR[DONE] is set when BCR reaches zero. If the BCR is greater MCF5407 User's Manual DMA Controller Module Functional Description than zero, another read/write transfer is initiated. If the BCR is a multiple of DCR[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. If a termination error occurs, DSR[BES,DONE] are set and DMA transactions stop. 12.5.2.2 Single-Address Transfers Single-address transfers consist of one DMA bus cycle, allowing either a read or a write cycle to occur. The DMA controller begins a single-address transfer sequence when DCR[SAA] is set during a DMA request. If no error condition exists, DSR[REQ] is set. When the channel is enabled, DSR[BSY] is set and REQ is cleared. SAR contents are then driven onto the address bus and the value of DCR[S_RW] is driven on R/W. The BCR decrements on each successful address access until it is zero, when DSR[DONE] is set. If a termination error occurs, DSR[BES,DONE] are set and DMA transactions stop. 12.5.3 Channel Initialization and Startup Before a block transfer starts, channel registers must be initialized with information describing configuration, request-generation method, and the data block. 12.5.3.1 Channel Prioritization The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel 3 having the lowest) or as determined by DCR[BWC]. If BWC for a DMA channel is 000, that channel has priority only over the channel immediately preceding it. For example, if DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming DCR2[BWC] 000) but not over DMA channel 1. If DCR1[BWC] = DCR2[BWC] = 000, DMA 1 has priority over DMA 0 and DMA 2. DCR2[BWC] = 000 in this case does not affect prioritization. Prioritization of simultaneous external requests is either ascending or as determined by each channel's BWC bits as described in the previous paragraphs. 12.5.3.2 Programming the DMA Controller Module Note the following general guidelines for programming the DMA: * * No mechanism exists to prevent writes to control registers during DMA accesses. If the BWC of sequential channels are equal, channel priority is in ascending order. The SAR is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to either a peripheral device or memory, the source address is the starting address of the data block. This can be any aligned byte address. In single-address mode, this data register is used regardless of transfer direction. Chapter 12. DMA Controller Module 12-13 DMA Controller Module Functional Description The DAR should contain the destination (write) address. If the transfer is from a peripheral device to memory, or memory to memory, the DAR is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, DAR is loaded with the address of the peripheral data register. This address can be any aligned byte address. DAR is not used in single-address mode. SAR and DAR change after each cycle depending on DCR[SSIZE,DSIZE,SINC,DINC] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword, or line transfers, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer. BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSR must be cleared for channel startup. As soon as the channel has been initialized, it is started by writing a one to DCR[START] or asserting DREQ, depending on the status of DCR[EEXT]. Programming the channel for internal request causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, DREQ must be asserted before the channel requests the bus. Changes to DCR are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSR[DONE] to stop the DMA channel. 12.5.4 Data Transfer This section includes timing diagrams that illustrate the interaction of signals in DMA data transfers. It also describes auto-alignment and bandwidth control. 12.5.4.1 External Request and Acknowledge Operation Channels 0 and 1 initiate transfers to an external module by means of DREQ[1:0]. The request for channels 2 and 3 are connected internally to the UART0 and UART1 interrupt signals, respectively. If DCR[EEXT] = 1 and the channel is idle, the DMA initiates a transfer when DREQ is asserted. Figure 12-11 shows the minimum 4-clock cycle delay from when DREQ is sampled asserted to when a DMA bus cycle begins. This delay may be longer, depending on DMA priority, bus arbitration, DRAM refresh operations, and other factors. 12-14 MCF5407 User's Manual DMA Controller Module Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 CLKIN DREQ0 TM0/DACK0 TT1 TT0 TS CS TA R/W A[31:0] Read Write Figure 12-11. DREQ Timing Constraints, Dual-Address DMA Transfer Although Figure 12-11 does not show TM0/DACK0 signaling a DMA acknowledgement, this signal can provide an external request acknowledge response, as shown in subsequent diagrams. To initiate a request, DREQ need only be asserted long enough to be sampled on one rising clock edge. However, note the following regarding the negation of DREQ: * * In cycle-steal mode (DCR[CS] = 1), the read/write transaction is limited to a single transfer. DREQ must be negated appropriately to avoid generating another request. -- For dual-address transfers, DREQ must be negated before TS is asserted for the write portion, as shown in Figure 12-11, clock cycle 7. -- For single-address transfers, DREQ must be negated before TS is asserted for the transfer, as shown in Figure 12-13, clock cycle 4. In burst mode, (DCR[CS] = 0), multiple read/write transfers can occur on the bus as programmed. DREQ need not be negated until DSR[DONE] is set, indicating the block transfer is complete. Another transfer cannot be initiated until the DMA registers are reprogrammed. Figure 12-12 shows a dual-address, peripheral-to-SDRAM DMA transfer. The DMA is not parked on the bus, so the diagram shows how the CPU can generate multiple bus cycles during DMA transfers. It also shows TM0/DACK0 timing. The TT signals indicate whether the CPU (0) or DMA (1) has bus mastership. TM2 indicates dual-address mode. If DCR[AT] is 1, TM/DACK is asserted during the final transfer. If DCR[AT] is 0, TM/DACK asserts during all DMA accesses. Chapter 12. DMA Controller Module 12-15 DMA Controller Module Functional Description CLKIN TS AS TIP A[31:0] R/W SIZ[1:0] D[31:0] CSx TA DRAMW Precharge SRAS SCAS RAS[1:0] CAS[3:0] TT[1:0] 0 1 0 1 0 TM2 TM0/DACK0 DREQ0 CPU DMA Read CPU DMA Write CPU Figure 12-12. Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer Figure 12-13 shows a single-address DMA transfer in which the peripheral is reading from memory. Note that TM2 is high, indicating a single-address transfer. Note that DREQ is negated in clock 4, before the assertion of TS in clock 6. 12-16 MCF5407 User's Manual DMA Controller Module Functional Description 0 1 2 3 4 5 6 7 8 9 10 11 CLKIN DREQ0 TM0/DACK0 TS A[31:0], SIZ[1:0] TIP R/W TM2 TT0 TT1 CSx, AS OE, BE/BWE TA D[31:0] Figure 12-13. Single-Address DMA Transfer 12.5.4.2 Auto-Alignment Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCR[AA] must be set. The source is auto-aligned if SSIZE indicates a transfer size larger than DSIZE. Source alignment takes precedence over the destination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. The address register chosen for alignment increments regardless of the increment value. Configuration error checking is performed on registers not chosen for alignment. If BCR is greater than 16, the address determines transfer size. Bytes, words, or longwords are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size. If BCR is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. For example, AA = 1, SAR = 0x0001, BCR = 0x00F0, SSIZE = 00 (longword), and DSIZE = 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers. The access sequence is as follows: 1. 2. 3. 4. Read byte from 0x0001--write 1 byte, increment SAR. Read word from 0x0002--write 2 bytes, increment SAR. Read longword from 0x0004--write 4 bytes, increment SAR. Repeat longwords until SAR = 0x00F0. Chapter 12. DMA Controller Module 12-17 DMA Controller Module Functional Description 5. Read byte from 0x00F0--write byte, increment SAR. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size. 12.5.4.3 Bandwidth Control Bandwidth control makes it possible to force the DMA off the bus to allow access to another device. DCR[BWC] provides seven levels of block transfer sizes. If the BCR decrements to a multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending, the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, DCR[AA] = 1, the BCR may skip over the programmed boundary, in which case, the DMA bus request is not negated. If BWC = 000, the request signal remains asserted until BCR reaches zero. DMA has priority over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus. See Section 6.2.10.1, "Default Bus Master Park Register (MPARK)." 12.5.5 Termination An unsuccessful transfer can terminate for one of the following reasons: * * 12-18 Error conditions--When the MCF5407 encounters a read or write cycle that terminates with an error condition, DSR[BES] is set for a read and DSR[BED] is set for a write before the transfer is halted. If the error occurred in a write cycle, data in the internal holding register is lost. Interrupts--If DCR[INT] is set, the DMA drives the appropriate internal interrupt signal. The processor can read DSR to determine whether the transfer terminated successfully or with an error. DSR[DONE] is then written with a one to clear the interrupt and the DONE and error bits. MCF5407 User's Manual Chapter 13 Timer Module This chapter describes the configuration and operation of the two general-purpose timer modules (timer 0 and timer 1). It includes programming examples. 13.1 Overview The timer module incorporates two independent, general-purpose 16-bit timers, timer 0 and timer 1. The output of an 8-bit prescaler clocks each timer. There are two sets of registers, one for each timer. The timers can operate from CLKIN or from an external clocking source using one of the TIN signals. If CLKIN is selected, it can be divided by 16 or 1. Figure 13-1 is a block diagram of one of the two identical ti5mer modules. GENERAL-PURPOSE TIMER CLKIN (/1 or /16) Timer Mode Register (TMRn) Prescaler Mode Bits Timer Clock Generator TIN clock Capture Detection 15 0 Timer Counter (TCNn) (contains incrementing value) 15 TOUT IRQn Divider 0 Timer Capture Register (TCRn) (latches TCN value when triggered by TIN) 15 0 Timer Reference Register (TRRn) (reference value for comparison with TCN) Timer Event Register (TERn) (indicates capture or when TCN = TRRn) Figure 13-1. Timer Block Diagram Chapter 13. Timer Module 13-1 General-Purpose Timer Units 13.1.1 Key Features Each general-purpose 16-bit timer unit has the following features: * * * * * * * Maximum period of 4.97 seconds at 54 MHz 18.5-nS resolution at 54 MHz Programmable sources for the clock input, including external clock Input-capture capability with programmable trigger edge on input pin Output-compare with programmable mode for the output pin Free run and restart modes Maskable interrupts on input capture or reference-compare 13.2 General-Purpose Timer Units The general-purpose timer units provide the following features: * * * * * * Each timer can be programmed to count and compare to a reference value stored in a register or capture the timer value at an edge detected on TIN. System bus clock can be divided by 16 or 1. This clock is input to the prescaler. TIN is fed directly into the 8-bit prescaler. The maximum value of TIN is 1/5 of CLKIN, as described in Chapter 20, "Electrical Specifications." The 8-bit prescaler clock divides the clocking source and is user-programmable from 1 to 256. Programmed events generate interrupts. The timer output signal (TOUT) can be configured to toggle or pulse on an event. 13.3 General-Purpose Timer Programming Model The following features are programmable through the timer registers, shown in Table 13-1: * * 13-2 Prescaler--The prescaler clock input is selected from CLKIN (divided by 1 or 16) or from the corresponding timer input, TIN. TIN is synchronized to CLKIN. The synchronization delay is between two and three CLKIN clocks. The corresponding TMRn[ICLK] selects the clock input source. A programmable prescaler divides the clock input by values from 1 to 256. The prescaler is an input to the 16-bit counter. Capture mode--Each timer has a 16-bit timer capture register (TCR0 and TCR1) that latches the counter value when the corresponding input capture edge detector senses a defined TIN transition. The capture edge bits (TMRn[CE]) select the type of transition that triggers the capture, sets the timer event register capture event bit, TERn[CAP], and issues a maskable interrupt. MCF5407 User's Manual General-Purpose Timer Programming Model * * Reference compare--A timer can be configured to count up to a reference value, at which point TERn[REF] is set. If TMRn[ORI] is one, an interrupt is issued. If the free run/restart bit TMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running. Output mode--When a timer reaches the reference value selected by TMRn[OM], it can send an output signal on TOUTn. TOUTn can be an active-low pulse or a toggle of the current output under program control. NOTE: Although external devices cannot access MCF5407 on-chip memories or MBAR, they can access timer module registers. The timer module registers, shown in Table 13-1, can be modified at any time. Table 13-1. General-Purpose Timer Module Memory Map MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x140 Timer 0 mode register (TMR0) [p. 13-3] 0x144 Timer 0 reference register (TRR0) [p. 13-4] Reserved 0x148 Timer 0 capture register (TCR0) [p. 13-4] Reserved 0x14C Timer 0 counter (TCN0) [p. 13-5] Reserved Reserved 0x150 Reserved Timer 0 event register (TER0) [p. 13-5] Reserved 0x180 Timer 1 mode register (TMR1) [p. 13-3] 0x184 Timer 1 reference register (TRR1) [p. 13-4] Reserved 0x188 Timer 1 capture register (TCR1) [p. 13-4] Reserved 0x18C Reserved Timer 1 counter (TCN1) [p. 13-5] Reserved 0x190 Reserved Timer 1 event register (TER1) [p. 13-5] Reserved 13.3.1 Timer Mode Registers (TMR0/TMR1) Timer mode registers (TMR0/TMR1), Figure 13-2, program the prescaler and various timer modes. 15 Field 8 6 CE Reset 5 4 3 OM ORI FRR 2 1 CLK 0 RST 0000_0000_0000_0000 R/W Address 7 PS R/W MBAR + 0x140 (TMR0); + 0x180 (TMR1) Figure 13-2. Timer Mode Registers (TMR0/TMR1) Table 13-2 describes TMRn fields. Chapter 13. Timer Module 13-3 General-Purpose Timer Programming Model Table 13-2. TMRn Field Descriptions Bits Name Description 15-8 PS Prescaler value. The prescaler is programmed to divide the clock input (CLKIN/(16 or 1) or clock on TIN) by values from 1 (PS = 0000_0000) to 256 (PS = 1111_1111). 7-6 CE Capture edge and enable interrupt 00 Disable interrupt on capture event 01 Capture on rising edge only and enable interrupt on capture event 10 Capture on falling edge only and enable interrupt on capture event 11 Capture on any edge and enable interrupt on capture event 5 OM Output mode 0 Active-low pulse for one CLKIN cycle (18.5 ns at 54 MHz). 1 Toggle output. 4 ORI Output reference interrupt enable. If ORI is set when TERn[REF] = 1, an interrupt occurs. 0 Disable interrupt for reference reached (does not affect interrupt on capture function). 1 Enable interrupt upon reaching the reference value. 3 FRR Free run/restart 0 Free run. Timer count continues to increment after reaching the reference value. 1 Restart. Timer count is reset immediately after reaching the reference value. 2-1 CLK Input clock source for the timer 00 Stop count 01 System bus clock divided by 1 10 System bus clock divided by 16. Note that this clock source is not synchronized to the timer; thus successive time-outs may vary slightly. 11 TIN pin (falling edge) 0 RST Reset timer. Performs a software timer reset similar to an external reset, although other register values can still be written while RST = 0. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless the timer is enabled. 0 Reset timer (software reset) 1 Enable timer 13.3.2 Timer Reference Registers (TRR0/TRR1) Each timer reference register (TRR0/TRR1), Figure 13-3, contains the reference value compared with the respective free-running timer counter (TCN0/TCN1) as part of the output-compare function. The reference value is not matched until TCNn equals TRRn. = 15 0 Field REF Reset 1111_1111_1111_1111 R/W Address R/W MBAR + 0x144 (TRR0),+ 0x184 (TRR1) Figure 13-3. Timer Reference Registers (TRR0/TRR1) 13.3.3 Timer Capture Registers (TCR0/TCR1) Each timer capture register (TCR0/TCR1), Figure 13-4, latches the corresponding TCNn value during a capture operation when an edge occurs on TIN, as programmed in TMRn. CLKIN is assumed to be the clock source. TIN cannot simultaneously function as a 13-4 MCF5407 User's Manual General-Purpose Timer Programming Model clocking source and as an input capture pin. 15 0 Field CAP (16-bit capture counter value) Reset 0000_0000_0000_0000 R/W Read only Address MBAR + 0x148 (TCR0); + 0x188 (TCR1) Figure 13-4. Timer Capture Register (TCR0/TCR1) 13.3.4 Timer Counters (TCN0/TCN1) The current value of the 16-bit, incrementing timer counters (TCN0/TCN1), Figure 13-5, can be read anytime without affecting counting. Writing to TCNn clears it. The timer counter decrements on the clock source rising edge (CLKIN / 1, CLKIN / 16, or TIN). 15 0 Field 16-bit timer counter value count Reset 0000_0000_0000_0000 R/W R/W (to reset) Address MBAR + 0x14C (TCN0); + 0x18C (TCN1) Figure 13-5. Timer Counters (TCN0/TCN1) 13.3.5 Timer Event Registers (TER0/TER1) Each timer event register (TER0/TER1), Figure 13-6, reports capture or reference events events the timer recognizes by setting TERn[CAP] or TERn[REF], which it does regardless of the corresponding interrupt-enable bit values, TMRn[ORI,CE]. Writing a 1 to either REF or CAP clears it (writing a 0 does not affect bit value); both bits can be cleared at the same time. REF and CAP must be cleared early in the exception handler, before the timer negates the IRQn to the interrupt controller. 7 Field Reset R/W Address 2 -- 1 0 REF CAP 0000_0000 R/W (ones clear/zeros have no effect) MBAR + 0x151 (TER0); + 0x191 (TER1) Figure 13-6. Timer Event Registers (TER0/TER1) Chapter 13. Timer Module 13-5 Code Example Table 13-3 describes TERn fields. Table 13-3. TERn Field Descriptions Bits Name Description 7-2 -- 1 REF Output reference event. The counter has reached the TRRn value. Setting TMRn[ORI] enables the interrupt request caused by this event. Writing a one to REF clears the event condition. 0 CAP Capture event. The counter value has been latched into TCRn. Setting TMRn[CE] enables the interrupt request caused by this event. Writing a 1 to CAP clears the event condition. Reserved 13.4 Code Example The following code provides an example of how to initialize timer 0 and how to use the timer for counting time-out periods. MBARx EQU 0x10000 ;Defines the module base address at 0x10000 TMR0 EQU MBARx+0x140;Timer 0 register TMR1 EQU MBARx+0x180 ;Timer 1 register TRR0 EQU MBARx+0x144 ;Timer 0 reference register TRR1 EQU MBARx+0x184 ;Timer 1 reference register TCR0 EQU MBARx+0x148 ;Timer 0 capture register TCR1 EQU MBARx+0x188 ;Timer 1 capture register TCN0 EQU MBARx+0x14C ;Timer 0 counter TCN1 EQU MBARx+0x18C ;Timer 1 counter TER0 EQU MBARx+0x151 ;Timer 0 event register TER1 EQU MBARx+0x191 ;Timer 1 event register * TMR0 is defined as: * *[PS]= 0xFF, divide clock by 256 *[CE] = 00disable interrupt *[OM] = 0 output=active-low pulse *[ORI] = 0, disable ref.interrupt *[FRR] = 1, restart mode enabled *[CLK] = 10, CLKIN/16 *[RST] = 0, timer 0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 move.w #0x0000,D0;writing to the timer counter with any move.w DO,TCN0 ;value resets it to zero move.w #AFAF,DO ;set the timer 0 reference to be move.w #D0,TRR0 ;defined as 0xAFAF The simple example below uses 0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached. timer0_ex clr.l DO clr.l D1 clt.l D2 move.w #0x0000,D0 move,w D0,TCN0;reset the counter to 0x0000 move.b #0x03,D0 ;writing ones to TER0[REF,CAP] move.b D0,TER0 ;clears the event flags 13-6 MCF5407 User's Manual Calculating Time-Out Values move.w TMR0,D0;save the contents of TMR0 while setting bset #0,D0 ;the 0 bit. This enables timer 0 and starts counting move.w D0, TMR0 ;load the value back into the register, setting TMR0[RST] T0_LOOP move.b TER0,D1 ;load TER0 and see if btst #1,D1 ;TER0[REF] has been set beq T0_LOOP addi.l #1,D2;Increment D2 cmp.l #5,D2;Did D2 reach 5? (i.e. timer ref has timed) beq T0_FINISH;If so, end timer0 example. Otherwise jump back. move.b #0x02,D0 ;writing one to TER0[REF] clears the event flag move.b D0,TER0 jmp T0_LOOP T0_FINISH HALT;End processing. Example is finished 13.5 Calculating Time-Out Values The formula below determines time-out periods for various reference values: Time-out period = (1/clock frequency) x (1 or 16) x (TMRn[PS] + 1) x (TRRn[REF]) When calculating time-out periods, add 1 to the prescaler to simplify calculating, because TMRn[PS] = 0x00 yields a prescaler of 1 and TMRn[PS] = 0xFF yields a prescaler of 256. For example, if a 54-MHz timer clock is divided by 16, TMRn[PS] = 0x7F, and the timer is referenced at 0xABCD (43,981 decimal), the time-out period is as follows: Time-out period = (1/54,000,000) x (16) x (127 + 1) x (43,981) = 1.67 S The time-out values in Table 13-4 represent the time it takes the counter value in TCNn value to go from 0x0000 to the default reference value, TRRn[REF] = 0xFFFF. Time-out values shown for CLKIN are divided by 1 and by 16 (TMRn[CLK] is 01 or 10, respectively). Any clock source (CLKIN / 1, CLKIN / 16, or TIN) can be prescaled using TMRn[PS]. Table 13-4. Time-Out Values (in Seconds)--TRR[REF] = 0xFFFF (162-MHz Processor Clock) CLK = 10 (/ 1) CLK = 01 (/ 16) TMR[PS] (Dec) CLKIN (MHz) 0 CLK = 10 (/ 1) CLK = 01 (/ 16) TMR[PS] (Dec) CLKIN (MHz) 0.019 0.026 0.032 0.001 0.002 0.002 128 2.505 3.340 4.175 0.157 0.209 0.261 1 0.039 0.052 0.065 0.002 0.003 0.004 129 2.524 3.366 4.207 0.158 0.210 0.263 2 0.058 0.078 0.097 0.004 0.005 0.006 130 2.544 3.392 4.240 0.159 0.212 0.265 3 0.078 0.104 0.129 0.005 0.006 0.008 131 2.563 3.418 4.272 0.160 0.214 0.267 4 0.097 0.129 0.162 0.006 0.008 0.010 132 2.583 3.443 4.304 0.161 0.215 0.269 5 0.117 0.155 0.194 0.007 0.010 0.012 133 2.602 3.469 4.337 0.163 0.217 0.271 54 40.5 32.4 54 40.5 32.4 54 Chapter 13. Timer Module 40.5 32.4 54 40.5 32.4 13-7 Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)--TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (/ 1) TMR[PS] (Dec) CLK = 01 (/ 16) 54 40.5 32.4 54 CLK = 10 (/ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (/ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 6 0.136 0.181 0.227 0.008 0.011 0.014 134 2.621 3.495 4.369 0.164 0.218 0.273 7 0.155 0.207 0.259 0.010 0.013 0.016 135 2.641 3.521 4.401 0.165 0.220 0.275 8 0.175 0.233 0.291 0.011 0.015 0.018 136 2.660 3.547 4.434 0.166 0.222 0.277 9 0.194 0.259 0.324 0.012 0.016 0.020 137 2.680 3.573 4.466 0.167 0.223 0.279 10 0.214 0.285 0.356 0.013 0.018 0.022 138 2.699 3.599 4.499 0.169 0.225 0.281 11 0.233 0.311 0.388 0.015 0.019 0.024 139 2.719 3.625 4.531 0.170 0.227 0.283 12 0.252 0.337 0.421 0.016 0.021 0.026 140 2.738 3.651 4.563 0.171 0.228 0.285 13 0.272 0.362 0.453 0.017 0.023 0.028 141 2.757 3.676 4.596 0.172 0.230 0.287 14 0.291 0.388 0.485 0.018 0.024 0.030 142 2.777 3.702 4.628 0.174 0.231 0.289 15 0.311 0.414 0.518 0.019 0.026 0.032 143 2.796 3.728 4.660 0.175 0.233 0.291 16 0.330 0.440 0.550 0.021 0.028 0.034 144 2.816 3.754 4.693 0.176 0.235 0.293 17 0.350 0.466 0.583 0.022 0.029 0.036 145 2.835 3.780 4.725 0.177 0.236 0.295 18 0.369 0.492 0.615 0.023 0.031 0.038 146 2.854 3.806 4.757 0.178 0.238 0.297 19 0.388 0.518 0.647 0.024 0.032 0.040 147 2.874 3.832 4.790 0.180 0.239 0.299 20 0.408 0.544 0.680 0.025 0.034 0.042 148 2.893 3.858 4.822 0.181 0.241 0.301 21 0.427 0.570 0.712 0.027 0.036 0.044 149 2.913 3.884 4.855 0.182 0.243 0.303 22 0.447 0.595 0.744 0.028 0.037 0.047 150 2.932 3.910 4.887 0.183 0.244 0.305 23 0.466 0.621 0.777 0.029 0.039 0.049 151 2.952 3.935 4.919 0.184 0.246 0.307 24 0.485 0.647 0.809 0.030 0.040 0.051 152 2.971 3.961 4.952 0.186 0.248 0.309 25 0.505 0.673 0.841 0.032 0.042 0.053 153 2.990 3.987 4.984 0.187 0.249 0.311 26 0.524 0.699 0.874 0.033 0.044 0.055 154 3.010 4.013 5.016 0.188 0.251 0.314 27 0.544 0.725 0.906 0.034 0.045 0.057 155 3.029 4.039 5.049 0.189 0.252 0.316 28 0.563 0.751 0.939 0.035 0.047 0.059 156 3.049 4.065 5.081 0.191 0.254 0.318 29 0.583 0.777 0.971 0.036 0.049 0.061 157 3.068 4.091 5.113 0.192 0.256 0.320 30 0.602 0.803 1.003 0.038 0.050 0.063 158 3.087 4.117 5.146 0.193 0.257 0.322 31 0.621 0.829 1.036 0.039 0.052 0.065 159 3.107 4.143 5.178 0.194 0.259 0.324 32 0.641 0.854 1.068 0.040 0.053 0.067 160 3.126 4.168 5.211 0.195 0.261 0.326 33 0.660 0.880 1.100 0.041 0.055 0.069 161 3.146 4.194 5.243 0.197 0.262 0.328 34 0.680 0.906 1.133 0.042 0.057 0.071 162 3.165 4.220 5.275 0.198 0.264 0.330 35 0.699 0.932 1.165 0.044 0.058 0.073 163 3.185 4.246 5.308 0.199 0.265 0.332 36 0.718 0.958 1.197 0.045 0.060 0.075 164 3.204 4.272 5.340 0.200 0.267 0.334 37 0.738 0.984 1.230 0.046 0.061 0.077 165 3.223 4.298 5.372 0.201 0.269 0.336 38 0.757 1.010 1.262 0.047 0.063 0.079 166 3.243 4.324 5.405 0.203 0.270 0.338 39 0.777 1.036 1.295 0.049 0.065 0.081 167 3.262 4.350 5.437 0.204 0.272 0.340 40 0.796 1.062 1.327 0.050 0.066 0.083 168 3.282 4.376 5.469 0.205 0.273 0.342 41 0.816 1.087 1.359 0.051 0.068 0.085 169 3.301 4.401 5.502 0.206 0.275 0.344 42 0.835 1.113 1.392 0.052 0.070 0.087 170 3.320 4.427 5.534 0.208 0.277 0.346 13-8 MCF5407 User's Manual Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)--TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (/ 1) TMR[PS] (Dec) CLK = 01 (/ 16) 54 40.5 32.4 54 CLK = 10 (/ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (/ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 43 0.854 1.139 1.424 0.053 0.071 0.089 171 3.340 4.453 5.567 0.209 0.278 0.348 44 0.874 1.165 1.456 0.055 0.073 0.091 172 3.359 4.479 5.599 0.210 0.280 0.350 45 0.893 1.191 1.489 0.056 0.074 0.093 173 3.379 4.505 5.631 0.211 0.282 0.352 46 0.913 1.217 1.521 0.057 0.076 0.095 174 3.398 4.531 5.664 0.212 0.283 0.354 47 0.932 1.243 1.553 0.058 0.078 0.097 175 3.418 4.557 5.696 0.214 0.285 0.356 48 0.951 1.269 1.586 0.059 0.079 0.099 176 3.437 4.583 5.728 0.215 0.286 0.358 49 0.971 1.295 1.618 0.061 0.081 0.101 177 3.456 4.609 5.761 0.216 0.288 0.360 50 0.990 1.320 1.651 0.062 0.083 0.103 178 3.476 4.634 5.793 0.217 0.290 0.362 51 1.010 1.346 1.683 0.063 0.084 0.105 179 3.495 4.660 5.825 0.218 0.291 0.364 52 1.029 1.372 1.715 0.064 0.086 0.107 180 3.515 4.686 5.858 0.220 0.293 0.366 53 1.049 1.398 1.748 0.066 0.087 0.109 181 3.534 4.712 5.890 0.221 0.295 0.368 54 1.068 1.424 1.780 0.067 0.089 0.111 182 3.554 4.738 5.923 0.222 0.296 0.370 55 1.087 1.450 1.812 0.068 0.091 0.113 183 3.573 4.764 5.955 0.223 0.298 0.372 56 1.107 1.476 1.845 0.069 0.092 0.115 184 3.592 4.790 5.987 0.225 0.299 0.374 57 1.126 1.502 1.877 0.070 0.094 0.117 185 3.612 4.816 6.020 0.226 0.301 0.376 58 1.146 1.528 1.909 0.072 0.095 0.119 186 3.631 4.842 6.052 0.227 0.303 0.378 59 1.165 1.553 1.942 0.073 0.097 0.121 187 3.651 4.867 6.084 0.228 0.304 0.380 60 1.185 1.579 1.974 0.074 0.099 0.123 188 3.670 4.893 6.117 0.229 0.306 0.382 61 1.204 1.605 2.007 0.075 0.100 0.125 189 3.689 4.919 6.149 0.231 0.307 0.384 62 1.223 1.631 2.039 0.076 0.102 0.127 190 3.709 4.945 6.181 0.232 0.309 0.386 63 1.243 1.657 2.071 0.078 0.104 0.129 191 3.728 4.971 6.214 0.233 0.311 0.388 64 1.262 1.683 2.104 0.079 0.105 0.131 192 3.748 4.997 6.246 0.234 0.312 0.390 65 1.282 1.709 2.136 0.080 0.107 0.133 193 3.767 5.023 6.279 0.235 0.314 0.392 66 1.301 1.735 2.168 0.081 0.108 0.136 194 3.787 5.049 6.311 0.237 0.316 0.394 67 1.320 1.761 2.201 0.083 0.110 0.138 195 3.806 5.075 6.343 0.238 0.317 0.396 68 1.340 1.786 2.233 0.084 0.112 0.140 196 3.825 5.100 6.376 0.239 0.319 0.398 69 1.359 1.812 2.265 0.085 0.113 0.142 197 3.845 5.126 6.408 0.240 0.320 0.400 70 1.379 1.838 2.298 0.086 0.115 0.144 198 3.864 5.152 6.440 0.242 0.322 0.403 71 1.398 1.864 2.330 0.087 0.117 0.146 199 3.884 5.178 6.473 0.243 0.324 0.405 72 1.418 1.890 2.363 0.089 0.118 0.148 200 3.903 5.204 6.505 0.244 0.325 0.407 73 1.437 1.916 2.395 0.090 0.120 0.150 201 3.922 5.230 6.537 0.245 0.327 0.409 74 1.456 1.942 2.427 0.091 0.121 0.152 202 3.942 5.256 6.570 0.246 0.328 0.411 75 1.476 1.968 2.460 0.092 0.123 0.154 203 3.961 5.282 6.602 0.248 0.330 0.413 76 1.495 1.994 2.492 0.093 0.125 0.156 204 3.981 5.308 6.635 0.249 0.332 0.415 77 1.515 2.019 2.524 0.095 0.126 0.158 205 4.000 5.333 6.667 0.250 0.333 0.417 78 1.534 2.045 2.557 0.096 0.128 0.160 206 4.020 5.359 6.699 0.251 0.335 0.419 79 1.553 2.071 2.589 0.097 0.129 0.162 207 4.039 5.385 6.732 0.252 0.337 0.421 Chapter 13. Timer Module 13-9 Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)--TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (/ 1) TMR[PS] (Dec) CLK = 01 (/ 16) 54 40.5 32.4 54 CLK = 10 (/ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (/ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 80 1.573 2.097 2.621 0.098 0.131 0.164 208 4.058 5.411 6.764 0.254 0.338 0.423 81 1.592 2.123 2.654 0.100 0.133 0.166 209 4.078 5.437 6.796 0.255 0.340 0.425 82 1.612 2.149 2.686 0.101 0.134 0.168 210 4.097 5.463 6.829 0.256 0.341 0.427 83 1.631 2.175 2.719 0.102 0.136 0.170 211 4.117 5.489 6.861 0.257 0.343 0.429 84 1.651 2.201 2.751 0.103 0.138 0.172 212 4.136 5.515 6.893 0.259 0.345 0.431 85 1.670 2.227 2.783 0.104 0.139 0.174 213 4.155 5.541 6.926 0.260 0.346 0.433 86 1.689 2.252 2.816 0.106 0.141 0.176 214 4.175 5.567 6.958 0.261 0.348 0.435 87 1.709 2.278 2.848 0.107 0.142 0.178 215 4.194 5.592 6.991 0.262 0.350 0.437 88 1.728 2.304 2.880 0.108 0.144 0.180 216 4.214 5.618 7.023 0.263 0.351 0.439 89 1.748 2.330 2.913 0.109 0.146 0.182 217 4.233 5.644 7.055 0.265 0.353 0.441 90 1.767 2.356 2.945 0.110 0.147 0.184 218 4.253 5.670 7.088 0.266 0.354 0.443 91 1.786 2.382 2.977 0.112 0.149 0.186 219 4.272 5.696 7.120 0.267 0.356 0.445 92 1.806 2.408 3.010 0.113 0.150 0.188 220 4.291 5.722 7.152 0.268 0.358 0.447 93 1.825 2.434 3.042 0.114 0.152 0.190 221 4.311 5.748 7.185 0.269 0.359 0.449 94 1.845 2.460 3.075 0.115 0.154 0.192 222 4.330 5.774 7.217 0.271 0.361 0.451 95 1.864 2.486 3.107 0.117 0.155 0.194 223 4.350 5.800 7.249 0.272 0.362 0.453 96 1.884 2.511 3.139 0.118 0.157 0.196 224 4.369 5.825 7.282 0.273 0.364 0.455 97 1.903 2.537 3.172 0.119 0.159 0.198 225 4.388 5.851 7.314 0.274 0.366 0.457 98 1.922 2.563 3.204 0.120 0.160 0.200 226 4.408 5.877 7.347 0.275 0.367 0.459 99 1.942 2.589 3.236 0.121 0.162 0.202 227 4.427 5.903 7.379 0.277 0.369 0.461 100 1.961 2.615 3.269 0.123 0.163 0.204 228 4.447 5.929 7.411 0.278 0.371 0.463 101 1.981 2.641 3.301 0.124 0.165 0.206 229 4.466 5.955 7.444 0.279 0.372 0.465 102 2.000 2.667 3.333 0.125 0.167 0.208 230 4.486 5.981 7.476 0.280 0.374 0.467 103 2.019 2.693 3.366 0.126 0.168 0.210 231 4.505 6.007 7.508 0.282 0.375 0.469 104 2.039 2.719 3.398 0.127 0.170 0.212 232 4.524 6.033 7.541 0.283 0.377 0.471 105 2.058 2.744 3.431 0.129 0.172 0.214 233 4.544 6.058 7.573 0.284 0.379 0.473 106 2.078 2.770 3.463 0.130 0.173 0.216 234 4.563 6.084 7.605 0.285 0.380 0.475 107 2.097 2.796 3.495 0.131 0.175 0.218 235 4.583 6.110 7.638 0.286 0.382 0.477 108 2.117 2.822 3.528 0.132 0.176 0.220 236 4.602 6.136 7.670 0.288 0.384 0.479 109 2.136 2.848 3.560 0.133 0.178 0.222 237 4.622 6.162 7.703 0.289 0.385 0.481 110 2.155 2.874 3.592 0.135 0.180 0.225 238 4.641 6.188 7.735 0.290 0.387 0.483 111 2.175 2.900 3.625 0.136 0.181 0.227 239 4.660 6.214 7.767 0.291 0.388 0.485 112 2.194 2.926 3.657 0.137 0.183 0.229 240 4.680 6.240 7.800 0.292 0.390 0.487 113 2.214 2.952 3.689 0.138 0.184 0.231 241 4.699 6.266 7.832 0.294 0.392 0.489 114 2.233 2.977 3.722 0.140 0.186 0.233 242 4.719 6.291 7.864 0.295 0.393 0.492 115 2.252 3.003 3.754 0.141 0.188 0.235 243 4.738 6.317 7.897 0.296 0.395 0.494 116 2.272 3.029 3.787 0.142 0.189 0.237 244 4.757 6.343 7.929 0.297 0.396 0.496 13-10 MCF5407 User's Manual Calculating Time-Out Values Table 13-4. Time-Out Values (in Seconds)--TRR[REF] = 0xFFFF (162-MHz Processor Clock) (Continued) CLK = 10 (/ 1) TMR[PS] (Dec) CLK = 01 (/ 16) 54 40.5 32.4 54 CLK = 10 (/ 1) TMR[PS] (Dec) CLKIN (MHz) 40.5 CLK = 01 (/ 16) CLKIN (MHz) 32.4 54 40.5 32.4 54 40.5 32.4 117 2.291 3.055 3.819 0.143 0.191 0.239 245 4.777 6.369 7.961 0.299 0.398 0.498 118 2.311 3.081 3.851 0.144 0.193 0.241 246 4.796 6.395 7.994 0.300 0.400 0.500 119 2.330 3.107 3.884 0.146 0.194 0.243 247 4.816 6.421 8.026 0.301 0.401 0.502 120 2.350 3.133 3.916 0.147 0.196 0.245 248 4.835 6.447 8.059 0.302 0.403 0.504 121 2.369 3.159 3.948 0.148 0.197 0.247 249 4.855 6.473 8.091 0.303 0.405 0.506 122 2.388 3.185 3.981 0.149 0.199 0.249 250 4.874 6.499 8.123 0.305 0.406 0.508 123 2.408 3.210 4.013 0.150 0.201 0.251 251 4.893 6.524 8.156 0.306 0.408 0.510 124 2.427 3.236 4.045 0.152 0.202 0.253 252 4.913 6.550 8.188 0.307 0.409 0.512 125 2.447 3.262 4.078 0.153 0.204 0.255 253 4.932 6.576 8.220 0.308 0.411 0.514 126 2.466 3.288 4.110 0.154 0.206 0.257 254 4.952 6.602 8.253 0.309 0.413 0.516 127 2.486 3.314 4.143 0.155 0.207 0.259 255 4.971 6.628 8.285 0.311 0.414 0.518 Chapter 13. Timer Module 13-11 Calculating Time-Out Values 13-12 MCF5407 User's Manual Chapter 14 UART Modules This chapter describes the use of the universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5407 and includes programming examples. All references to UART refer to one of these modules when in UART mode as opposed to modem mode. Particular attention is given to the UART1 implementation of a synchronous interface that provides a controller for an 8- or 16-bit CODEC interface and an audio CODEC `97 (AC '97) digital interface. 14.1 Overview The MCF5407 contains two independent UARTs. UART1 on the MCF5407 provides synchronous operation and a CODEC interface for soft modem support. Each UART can be clocked by CLKIN, eliminating the need for an external crystal. As Figure 14-1 shows, each UART module interfaces directly to the CPU and consists of the following: * * * * Serial communication channel Programmable transmitter and receiver clock generation Internal channel control logic Interrupt control logic UART Internal Channel Control Logic CTS Serial Communications Channel RTS RxD TxD System Integration Module (SIM) Interrupt Controller Interrupt Control Logic Programmable Clock Generation CLKIN or External clock (TIN) Figure 14-1. Simplified Block Diagram The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from CLKIN or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on Chapter 14. UART Modules 14-1 Serial Module Overview the channel transmitter serial data output (TxD). See Section 14.5.2.1, "Transmitting in UART Mode." The receiver converts serial data from the channel receiver serial data input (RxD) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. The receiver may be polledor interrupt-driven. See Section 14.5.2.3, "Receiver." UART1 can be programmed to function like original UART (identical to UART0) or in one of the following three modem modes: * * * An 8-bit CODEC interface A 16-bit CODEC interface An audio CODEC `97 (AC '97) digital interface controller A CODEC (code/decode) chip provides a data conversion interface for high-speed modem designs meeting a high range of standards, such as ITU-T V.34 and PCM. UART1 interfaces to the CODEC through a serial port consisting of Tx and Rx serial data and serial bit clock and frame inputs from the CODEC. UART1 transfers digital sample data to and from the CODEC through the serial port. AC '97 defines an architecture for audio-intensive personal computer applications such as gaming, authoring, and high-resolution music and video playback. An external AC '97 analog device performs mixing, analog processing, and sample-rate DAC and ADC. UART1 interfaces to the AC '97 device through a serial port consisting of Tx and Rx serial data, a serial bit clock, and a frame sync output generated by UART1 from the serial bit clock. An MCF5407 general-purpose I/O (GPIO) is used as a reset to the AC `97 device. UART1 transfers digital sample data as well as control/status information to and from the AC `97 device through the serial port. Unless otherwise specified, descriptions in this chapter refer to UART mode. 14.2 Serial Module Overview The MCF5407 contains two independent UART modules, whose features are as follows: * * * * * * 14-2 Each can be clocked by CLKIN, eliminating a need for an external crystal Full-duplex asynchronous/synchronous receiver/transmitter channel Quadruple-buffered receiver Double-buffered transmitter Independently programmable receiver and transmitter clock sources Programmable data format: -- 5-8 data bits plus parity -- Odd, even, no parity, or force parity -- One, one-and-a-half, or two stop bits MCF5407 User's Manual Register Descriptions * * * * * * * * * Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode Automatic wake-up mode for multidrop applications Four maskable interrupt conditions UART0 and UART1 have interrupt capability to DMA channels 2 and 3, respectively, when either the RxRDY or FFULL bit is set in the USR. Parity, framing, and overrun error detection False-start bit detection Line-break detection and generation Detection of breaks originating in the middle of a character Start/end break interrupt/status UART1 has the following additional features: * * * * * Programmable to interface to an 8- or 16-bit CODEC for soft modem support Programmable to function as a digital AC '97 controller Tx and Rx FIFOs can hold the following: -- 32 1-byte samples when programmed as a UART or as an 8-bit CODEC interface -- 16 2-byte samples when programmed as a 16-bit CODEC interface -- 16 20-bit samples when programmed as a digital AC '97 controller Both DMA channels associated with the UARTs can be programmed to service UART1 (one for the Tx channel and one for the Rx channel) No parity error, framing error, or line break detection in modem mode 14.3 Register Descriptions This section contains a detailed description of each register and its specific function. Flowcharts in Section 14.5.6, "Programming," describe basic UART module programming. The operation of the UART module is controlled by writing control bytes into the appropriate registers. Table 14-1 is a memory map for UART module registers. Chapter 14. UART Modules 14-3 Register Descriptions Table 14-1. UART Module Programming Model MBAR Offset [31:24] [23:16] [15:8] [7:0] UART0 UART1 0x1C0 0x200 UART mode registers1--(UMR1n) [p. 14-5], (UMR2n) [p. 14-7] Rx FIFO threshold register--(RXLVL) [p. 14-8] (UART1 only) Modem control Tx FIFO threshold register--(MODCTL) register--(TXLVL) [p. [p. 14-9] (UART1 only) 14-10] (UART1 only) 0x1C4 0x204 (Read) UART status registers--(USRn) [p. 14-10] -- (Read) Rx samples available register--(RSMP) [p. 14-12] (UART1 only) (Write) UART clock-select register1--(UCSRn) [p. 14-12] 0x1C8 0x1CC 0x208 0x20C (Read) Tx space available register--(TSPC) [p. 14-12] (UART1 only) (Read) Do not access2 -- (Write) UART command registers--(UCRn) [p. 14-13] -- (UART0/Read) UART receiver buffers--(URBn) [p. 14-15] -- (UART1/Read) UART receiver buffers--(URBn) [p. 14-15] (UART0/Write) UART transmitter buffers--(UTBn) [p. 14-16] -- (UART1/Write) UART transmitter buffers--(UTBn) [p. 14-16] 0x1D0 0x210 (Read) UART input port change registers--(UIPCRn) [p. 14-17] -- (Write) UART auxiliary -- control registers1--(UACRn) [p. 14-17] 0x1D4 0x214 (Read) UART interrupt -- status registers--(UISRn) [p. 14-18] (Write) UART interrupt -- mask registers--(UIMRn) [p. 14-18] 0x1D8 14-4 0x218 UART divider upper registers--(UDUn) [p. 14-19] -- MCF5407 User's Manual Register Descriptions Table 14-1. UART Module Programming Model (Continued) MBAR Offset [31:24] [23:16] UART0 UART1 0x1DC 0x21C 0x1E0- 0x1EC 0x220- Do not access2 0x22C -- 0x1F0 0x230 UART interrupt vector register--(UIVRn) [p. 14-20] -- 0x1F4 0x234 (Read) UART input port registers--(UIPn) [p. 14-20] -- UART divider lower registers--(UDLn) [p. 14-19] [15:8] [7:0] -- (Write) Do not access2 -- 0x1F8 0x238 (Read) Do not access2 -- (Write) UART output port bit set command registers--(UOP1n3) [p. 14-21] 0x1FC 0x23C -- (Read) Do not access2 -- (Write) UART output port bit reset command registers--(UOP0n3) [p. 14-21] -- 1 UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. 2 This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. 3 Address-triggered commands NOTE: UART registers are accessible only as bytes. Although external masters cannot access on-chip memories or MBAR, they can access any UART registers. 14.3.1 UART Mode Registers 1 (UMR1n) The UART mode registers 1 (UMR1n) control configuration. UMR1n can be read or written when the mode register pointer points to it, at RESET or after a RESET MODE REGISTER POINTER command using UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n. Chapter 14. UART Modules 14-5 Register Descriptions Field 7 6 5 RxRTS RxIRQ/FFULL ERR Reset 3 PM 2 1 PT 0 B/C 0000_0000 R/W Address 4 R/W MBAR + 0x1C0 (UART0), 0x200 (UART1). After UMR1n is read or written, the pointer points to UMR2n. Figure 14-2. UART Mode Registers 1 (UMR1n) Table 14-2 describes UMR1n fields. Table 14-2. UMR1n Field Descriptions Name Description 7 Bits RxRTS Receiver request-to-send. Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun. If both the receiver and transmitter are incorrectly programmed for RTS control, RTS control is disabled for both. Transmitter RTS control is configured in UMR2n[TxRTS]. Not used in modem mode. 0 The receiver has no effect on RTS. 1 When a valid start bit is received, RTS is negated if the UART's FIFO is full. RTS is reasserted when the FIFO has an empty position available. 6 RxIRQ/ FFULL Receiver interrupt select. This bit is used in UART and modem modes. 0 RxRDY is the source that generates IRQ. 1 FFULL is the source that generates IRQ. 5 ERR Error mode. Configures the FIFO status bits, USRn[RB,FE,PE]. This bit is not used in modem mode. 0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR must be 0 for correct A/D flag information when in multidrop mode. 1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the FIFO because the last RESET ERROR STATUS command for the channel was issued. See Section 14.3.10, "UART Command Registers (UCRn)." 4-3 PM Parity mode. Selects the parity or multidrop mode for the channel. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below. PM is not used in modem mode. 2 PT Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11). PT is not used in modem mode. PM 1-0 14-6 B/C Parity Mode Parity Type (PT= 0) 00 With parity Even parity 01 Force parity Low parity 10 No parity 11 Multidrop mode Parity Type (PT= 1) Odd parity High parity n/a Data character Address character Bits per character. Select the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits. B/C is not used in modem mode. 00 5 bits 01 6 bits 10 7 bits 11 8 bits MCF5407 User's Manual Register Descriptions 14.3.2 UART Mode Register 2 (UMR2n) UART mode registers 2 (UMR2n) control UART module configuration. UMR2n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do not update the pointer. 7 Field 6 CM 5 4 TxRTS TxCTS Reset 0 SB 0000_0000 R/W Address 3 R/W MBAR + 0x1C0, 0x200. After UMR1n is read or written, the pointer points to UMR2n. Figure 14-3. UART Mode Register 2 (UMR2n) Table 14-3 describes UMR2n fields. Table 14-3. UMR2n Field Descriptions Bits Name 7-6 CM Description Channel mode. Selects a channel mode. Section 14.5.3, "Looping Modes," describes individual modes. CM is used in both UART and modem modes. 00 Normal 01 Automatic echo 10 Local loop-back 11 Remote loop-back 5 TxRTS Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message transmission. Attempting to program a receiver and transmitter in the same channel for RTS control is not permitted and disables RTS control for both. TxRTS is not used in modem mode. 0 The transmitter has no effect on RTS. 1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically clears UOP[RTS] one bit time after any characters in the channel transmitter shift and holding registers are completely sent, including the programmed number of stop bits. 4 TxCTS Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter. TxCTS is not used in modem mode. 0 CTS has no effect on the transmitter. 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent; if it is negated, the channel TxD remains in the high state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. Chapter 14. UART Modules 14-7 Register Descriptions Table 14-3. UMR2n Field Descriptions (Continued) Bits Name Description 3-0 SB Stop-bit length control. Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths of 9/16th to 2 bits are programmable for 6-8 bit characters. Lengths of 1 1/16th to 2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high condition at the center of the first stop-bit position, that is, one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects 2 stop bits for transmission. Not used in modem mode. SB 5 Bits 6-8 Bits SB 5 Bits 6-8 Bits SB 5-8 Bits SB 5-8 Bits 0000 1.063 0.563 0100 1.313 0.813 1000 1.563 1100 1.813 0001 1.125 0.625 0101 1.375 0.875 1001 1.625 1101 1.875 0010 1.188 0.688 0110 1.438 0.938 1010 1.688 1110 1.938 0011 1.250 0.750 0111 1.500 1.000 1011 1.750 1111 2.000 14.3.3 Rx FIFO Threshold Register (RXLVL) The Rx FIFO threshold register (RXLVL) supports UART1 only and is used in both UART and modem modes. The threshold is one less than the value at which the Rx FIFO is considered to be full for purposes of alerting the CPU that the Rx FIFO needs to be read. 7 5 4 0 Field -- RXLVL Reset 000 0_0000 R/W R/W Address MBAR + 0x201 Figure 14-4. Rx FIFO Threshold Register (RXLVL) Table 14-4 describes RXLVL fields. Table 14-4. RXLVL Field Descriptions Bits Name 7-5 -- 4-0 RXLVL 14-8 Description Reserved, should be cleared. Rx FIFO full threshold level. Values of 0000-1111 specify 1-32 bytes. The Rx FIFO is full when the number of bytes in the FIFO equals or exceeds the Rx threshold. Although FIFO thresholds are in bytes, data is written into and read out of the FIFOs in numbers of samples, as follows: * 1 sample = 1 byte for 8-bit CODEC and UART modes, * 1 sample = 2 bytes for 16-bit CODEC and AC `97 modes For choosing threshold values, AC `97 samples should be thought of as 2-byte entities. The Rx threshold is RXLVL + 1, so RXLVL = [(# samples) * (# bytes per sample)] - 1. For example, for Rx FIFO to indicate full when 13 or more samples have arrived, calculate RXLVL as follows: * For 8-bit CODEC or UART mode, RXLVL = [(13 samples) * (1 byte per sample)] - 1 = 12 bytes * For 16-bit CODEC or AC `97 modes, RXLVL = [(13 samples) * (2 bytes per sample)] - 1 = 25 bytes MCF5407 User's Manual Register Descriptions 14.3.4 Modem Control Register (MODCTL) The modem control register (MODCTL), Figure 14-5, controls whether UART1 is in UART mode or in one of three modem modes. Field 7 6 ACRB AWR 5 4 DSL Reset 3 2 DTS1 SHDIR 1 0 MODE 1000_0000 R/W R/W Address MBAR + 0x202 Figure 14-5. Modem Control Register (MODCTL) Table 14-5 describes MODCTL fields. Table 14-5. Modem Control Register (MODCTL) Field Descriptions Bits Name Description 7 ACRB AC `97 cold reset (active low). 0 The genera-purpose I/O used as the AC `97 cold reset output pin is active 1 The genera-purpose I/O used as the AC `97 cold reset output pin is inactive 6 AWR AC `97 warm reset (active high) 0 Warm reset is inactive, letting UART1's RTS output to function normally as the AC `97 frame sync. 1 Forces a 1 on UART1's RTS output, which is used as the AC `97 frame sync. 5-4 DSL Channel select for DMA channels 2 and 3. The sources for the interrupt request lines that drive DMA DREQ[3:2] are selected by multiplexers in UART1, which are controlled by DSL. 00 DMA DREQ2 is driven by UART0 combined Tx/Rx interrupt DMA DREQ3 is driven by UART1 combined Tx/Rx interrupt 01 DMA DREQ2 is driven by UART1 Rx interrupt DMA DREQ3 is driven by UART1 Tx interrupt 10 same as 00 11 DMA DREQ2 is driven by UART1 Rx interrupt DMA DREQ3 is driven by UART1 combined Tx/Rx interrupt. This combination is a by-product of implementation and may not be useful. When UART1 uses both DREQ lines, DREQ3 and DREQ2 are driven by the Tx FIFO empty and Rx FIFO full conditions, respectively. The Rx FIFO not-empty condition can be used instead of Rx FIFO full by clearing UMR1n[6]. UART0 and UART1 have separate request lines to the interrupt controller. Each is sourced from the combined Tx/Rx interrupt from the associated UART. 3 DTS1 Delay of time slot 1. Determines the starting point of the first bit of the first time slot of a new frame. 0 The rising edge of frame sync 1 One bit-clock cycle after the rising edge of frame sync 2 SHDIR Shift direction. For AC `97 this bit must be 0. 0 Samples/time slots are transferred msb first 1 Samples/time slots are transferred lsb first 1-0 MODE Mode select for UART1. 00 UART mode (default mode after hard reset). Changing from modem mode back to UART mode by writing 00 to this field has the same effect on UART1 as a hard reset--all registers and control logic are reset and the Tx and Rx FIFO pointers are reinitialized, effectively emptying the FIFOs. 01 8-bit CODEC interface mode 10 16-bit CODEC interface mode 11 AC `97 mode Chapter 14. UART Modules 14-9 Register Descriptions 14.3.5 Tx FIFO Threshold Register (TXLVL) Tx FIFO threshold register (TXLVL) supports only UART1 in both UART and modem modes. TXLVL holds the Tx FIFO threshold, the value at which the Tx FIFO is considered to be empty for purposes of alerting the CPU that the Tx FIFO needs more data/samples. 7 5 4 0 Field -- TXLVL Reset -- 0_0000 R/W R/W Address MBAR + 0x203 Figure 14-6. Tx FIFO Threshold Register (TXLVL) Table 14-6 describes TXLVL fields. Table 14-6. TXLVL Field Descriptions Bits Name 7-5 -- 4-0 TXLVL Description Reserved, should be cleared. Tx FIFO empty threshold level. 0000-1111 selects values of 0-31 bytes, respectively. The Tx FIFO is empty when the number of bytes in the FIFO is less than or equal to the Tx threshold value. Although the FIFO thresholds are in numbers of bytes, data is written into and read out of the FIFOs in numbers of samples, as follows: 1 sample = 1 byte for 8-bit CODEC and UART modes 1 sample = 2 bytes for 16-bit CODEC and AC `97 modes For choosing threshold values, AC `97 samples should be thought of as 2-byte entities. Choose the Tx threshold register value using the following formula: TXLVL = (# samples) * (# bytes per sample) For example, to indicate empty when three or fewer samples remain, calculate TXLVL as follows: For 8-bit CODEC or UART mode, TXLVL = (3 samples) * (1 byte per sample) = 3 bytes For 16-bit CODEC or AC `97 modes, TXLVL = (3 samples) * (2 bytes per sample) = 6 bytes 14.3.6 UART Status Registers (USRn) The USRn, Figure 14-7, shows status of the transmitter, the receiver, and the FIFO. Field 7 6 5 4 3 2 1 0 RB FE PE OE TxEMP TxRDY FFULL RxRDY Reset 0000_0000 R/W Read only Address MBAR + 0x1C4 (USR0), 0x204 (USR1) Figure 14-7. UART Status Register (USRn) Table 14-7 describes USRn fields. 14-10 MCF5407 User's Manual Register Descriptions Table 14-7. USRn Field Descriptions Bits Name Description 7 RB Received break. The received break circuit detects breaks that originate in the middle of a received character. However, a break in the middle of a character must persist until the end of the next detected character time. RB is not used (and is always 0) in modem mode. 0 No break was received. 1 An all-zero character of the programmed length was received without a stop bit. RB is valid only when RxRDY = 1. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until RxD returns to the high state for at least one-half bit time, which is equal to two successive edges of the UART clock. 6 FE Framing error. FE is not used (and is always 0) in modem mode. 0 No framing error occurred. 1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1. 5 PE Parity error. Valid only if RxRDY = 1. PE is not used (and is always 0) in modem mode. 0 No parity error occurred. 1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received A/D bit. 4 OE Overrun error. Indicates whether an overrun occurs. OE also functions this way for UART1 in modem mode. (For purposes of overrun, FIFO full means all space in the FIFO is occupied; the Rx FIFO threshold is irrelevant to overrun.) 0 No overrun occurred. 1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. OE is cleared by the RESET ERROR STATUS command in UCRn. 3 TxEMP Transmitter empty. For UART1, the function of TxEMP depends on which mode is used. UART mode: 0 The transmitter buffer is not empty. Either a character is being shifted out, or the transmitter is disabled. The transmitter is enabled/disabled by programming UCRn[TC]. 1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. Modem mode: 0 The transmitter does not have underrun as described above. 1 The transmitter has underrun, which means the number of bytes in the Tx FIFO is zero, the Tx shift register is empty, and a frame sync occurs. In other words, the time has come to transmit a new sample but no sample is available in the Tx shift register. Unlike UART mode, TxEMP high indicates an error condition similar to the overrun condition (OE = 1), and as such it is now cleared the same way as OE, by a RESET ERROR STATUS command in the UCRn and not by a RESET TRANSMITTER command in the UCRn. 2 TxRDY Transmitter ready. UART0: 0 The CPU loaded the transmitter holding register or the transmitter is disabled. 1 The transmitter holding register is empty and ready for a character. TxRDY is set when a character is sent to the transmitter shift register and when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent. UART1 (in UART or modem modes): 0 The transmitter FIFO is not empty, or the transmitter is disabled. 1 The transmitter FIFO is empty, as defined by TXLVL. TxRDY is set when the number of bytes in the Tx FIFO falls to, or below, the TXLVL value, due to the transfer of a sample (1 or 2 bytes) from the Tx FIFO to the Tx shift register. Chapter 14. UART Modules 14-11 Register Descriptions Table 14-7. USRn Field Descriptions (Continued) Bits Name Description 1 FFULL FIFO full. UART0: 0 The FIFO is not full but may hold up to two unread characters. 1 A character was received and is waiting in the receiver buffer FIFO. UART1 (in UART or modem modes): 1 Rx FIFO is full, as defined by the RXLVL. FFULL is set as soon as the number of bytes in the Rx FIFO exceeds the RXLVL value, due to the transfer of a sample (1 or 2 bytes) from the Rx shift register to the Rx FIFO. 0 RxRDY Receiver ready (in UART or modem modes). 0 The CPU has read the receiver buffer and no characters remain in the FIFO after this read. 1 One or more characters were received and are waiting in the receiver buffer FIFO. 14.3.7 UART Clock-Select Registers (UCSRn) The UART clock-select registers (UCSRn) select an external clock on the TIN input (divided by 1 or 16) or a prescaled CLKIN as the clocking source for the transmitter and receiver. See Section 14.5.1, "Transmitter/Receiver Clock Source." UCSR1 is used in UART mode only. The transmitter and receiver can use different clock sources. To use CLKIN for both, set UCSRn to 0xDD. 7 Field 4 3 RCS Reset 0000_0000 R/W Write only Address 0 TCS MBAR + 0x1C4 (UCSR0), 0x204 (UCSR1) Figure 14-8. UART Clock-Select Register (UCSRn) Table 14-8 describes UCSRn fields. Table 14-8. UCSRn Field Descriptions Bits Name 7-4 RCS Receiver clock select. Selects the clock source for the receiver channel. 1101 Prescaled CLKIN 1110 TIN divided by 16 1111 TIN Description 3-0 TCS Transmitter clock select. Selects the clock source for the transmitter channel. 1101 Prescaled CLKIN 1110 TIN divided by 16 1111 TIN 14.3.8 Receive Samples Available Register (RSMP) The receive samples available register (RSMP), Figure 14-9, shows the current byte count for the Rx FIFO. It is in UART1 only and can be used in both UART and modem modes. 14-12 MCF5407 User's Manual Register Descriptions 7 5 4 0 Field -- RSMP Reset -- 0_0000 R/W Read only Address MBAR + 0x206 Figure 14-9. Receive Samples Available Register (RSMP) Table 14-9 describes RSMP fields. Table 14-9. RSMP Field Descriptions Bits Name 7-5 -- 4-0 RSMP Description Reserved, should be cleared. Number of bytes in the Rx FIFO. 14.3.9 Transmit Space Available Register (TSPC) The transmit space available register (TSPC), Figure 14-10, shows available bytes in Tx FIFO. TSPC supports UART1 only and can be used in UART and modem modes. 7 5 Field -- Reset -- 4 0 TSPC 0_0000 R/W Read only Address MBAR + 0x207 Figure 14-10. Tx Space Available Register (TSPC) Table 14-10 describes TSPC fields. Table 14-10. TSPC Field Descriptions Bits Name 7-5 -- 4-0 TSPC Description Reserved, should be cleared. Number of empty bytes in the Tx FIFO. 14.3.10 UART Command Registers (UCRn) The UART command registers (UCRn), Figure 14-11, supply commands to the UART in both UART and modem modes. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example, RESET TRANSMITTER and ENABLE TRANSMITTER cannot be specified in one command. Chapter 14. UART Modules 14-13 Register Descriptions 7 Field 6 4 -- 3 MISC Reset 2 1 TC 0 RC 0000_0000 R/W Write only Address MBAR + 0x1C8, 0x208 Figure 14-11. UART Command Register (UCRn) Table 14-11 describes UCRn fields and commands. Examples in Section 14.5.2, "Transmitter and Receiver Operating Modes," show how these commands are used. Table 14-11. UCRn Field Descriptions Bits 7 Value Command -- -- 6-4 Description Reserved, should be cleared. MISC Field (This field selects a single command.) 000 NO COMMAND -- 001 RESET MODE Causes the mode register pointer to point to UMR1n. REGISTER POINTER 010 RESET RECEIVER Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes the receiver FIFO pointer. No other registers are altered. Because it places the receiver in a known state, use this command instead of RECEIVER DISABLE when reconfiguring the receiver. 011 RESET In UART mode, immediately disables the transmitter and clears USRn[TxEMP,TxRDY]. No other registers are altered. Because it places the transmitter in a known state, use this command instead of TRANSMITTER DISABLE when reconfiguring the transmitter. When UART1 is in modem mode, TxEMP is not cleared by this soft reset. It is cleared the same way as the Rx overflow bit, by a RESET ERROR STATUS command. TRANSMITTER 100 RESET ERROR STATUS 101 RESET BREAK- CHANGE INTERRUPT 14-14 In UART mode, clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after a data block is received. When UART1 is in modem mode, this command also clears TxEMP. Clears the delta break bit, UISRn[DB]. This command has no effect in modem mode. 110 START BREAK Forces TxD low. If the transmitter is empty, the break may be delayed up to one bit time. If the transmitter is active, the break starts when character transmission completes. The break is delayed until any character in the transmitter shift register is sent. Any character in the transmitter holding register is sent after the break. The transmitter must be enabled for the command to be accepted. This command ignores the state of CTS and has no effect in modem mode. 111 STOP BREAK Causes TxD to go high (mark) within two bit times. Any characters in the transmitter buffer are sent. MCF5407 User's Manual Register Descriptions Table 14-11. UCRn Field Descriptions (Continued) Bits Value Command 3-2 Description TC Field (This field selects a single command) 00 NO ACTION TAKEN Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 TRANSMITTER Enables operation of the channel's transmitter. USRn[TxEMP,TxRDY] are set. If the transmitter is already enabled, this command has no effect. For UART1 in modem mode, Tx FIFO can be loaded while the transmitter is disabled, unlike in UART mode. Therefore, this command does not affect the behavior of TxRDY. It does not automatically set TxRDY and TxEMP; however, if no data is written to the Tx FIFO, TxEMP is set at the first frame sync after the transmitter is enabled. In AC `97 mode, TxEMP is set if Tx FIFO is empty, the transmitter is enabled, the receiver detects a coded ready condition, and a frame sync occurs before samples are written to the Tx FIFO. ENABLE 10 TRANSMITTER DISABLE 11 -- 1-0 Terminates transmitter operation and clears USRn[TxEMP,TxRDY]. If a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. If the transmitter is already disabled, the command has no effect. In modem mode, the transmitter does not clear USRn[TxRDY] unless UART1 is in remote loop-back or auto-echo mode. This is because in modem mode, unlike in UART mode, the Tx FIFO may be loaded while the Tx is disabled. Reserved, do not use. RC (This field selects a single command) 00 NO ACTION TAKEN Causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled. 01 RECEIVER ENABLE If the UART module is not in multidrop mode (UMR1n[PM] 11), RECEIVER ENABLE enables the channel's receiver and forces it into search-for-start-bit state. If the receiver is already enabled, this command has no effect. 10 RECEIVER DISABLE Disables the receiver immediately. Any character being received is lost. The command does not affect receiver status bits or other control registers. If the UART module is programmed for local loop-back or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, the command has no effect. When UART1 is in modem mode, if the receiver is disabled while a character is being received, reception completes before the receiver becomes inactive. 11 -- Reserved, do not use. 14.3.11 UART Receiver Buffers (URBn) The receiver buffer for UART0 contains one serial shift register and three receiver holding registers, which act as a FIFO. RxD is connected to the serial shift register. The CPU reads from the top of the stack while the receiver shifts and updates from the bottom when the shift register is full (see Figure 14-29). RB contains the character in the receiver. Chapter 14. UART Modules 14-15 Register Descriptions 7 0 Field RB Reset 0000_0000 R/W Read only Address MBAR + 0x1CC Figure 14-12. UART Receiver Buffer for UART0 (URB0) Figure 14-13 shows the configuration of URB1. 31 24 Field RB[31:24] Reset 23 16 15 RB[23:16] 8 7 RB[15:8] 0 RB[7:0] 0000_0000_0000_0000_0000_0000_0000_0000 R/W Read only Address MBAR + 0x20C Figure 14-13. UART Receiver Buffer for UART1 (URB1) 14.3.12 UART Transmitter Buffers (UTBn) The transmitter buffer for UART0 consists of the transmitter holding register and the transmitter shift register. The holding register accepts characters from the bus master if channel's USRn[TxRDY] is set. A write to the transmitter buffer clears TxRDY, inhibiting any more characters until the shift register can accept more data. When the shift register is empty, it checks if the holding register has a valid character to be sent (TxRDY = 0). If there is a valid character, the shift register loads it and sets USRn[TxRDY] again. Writes to the transmitter buffer when the channel's TxRDY = 0 and when the transmitter is disabled have no effect on the transmitter buffer. Figure 14-14 shows UTB0. TB contains the character in the transmitter buffer. 7 0 Field TB Reset 0000_0000 R/W Address Write only MBAR + 0x1CC Figure 14-14. UART Transmitter Buffer for UART0 (UTB0) The transmitter buffer in UART1 consists of the transmitter shift register and the Tx FIFO, as described in Section 14.5.2.6, "FIFOs in UART1." The Tx FIFO in UART1 accepts characters/samples from the bus master if there is room for them in the FIFO. A write to the transmitter buffer clears TxRDY if the number of bytes in the FIFO exceeds the threshold level in TXLVL. When the shift register is empty, it checks if the FIFO has a valid character/sample to be sent. Valid characters are loaded into the shift register. Unlike UART 14-16 MCF5407 User's Manual Register Descriptions mode, in modem mode the Tx FIFO in UART1 can be loaded while the Tx is disabled. For UART1, FIFOs can be accessed as longwords. Figure 14-15 shows the configuration of the UTB1. These bits contain the samples in the transmitter buffer for UART1. 31 24 Field 23 16 TB[31:24] 15 8 TB[23:16] Reset 7 0 TB[15:8] TB[7:0] 0000_0000_0000_0000_0000_0000_0000_0000 R/W Write only Address MBAR + 0x20C Figure 14-15. UART Transmitter Buffer for UART1 (UTB1) 14.3.13 UART Input Port Change Registers (UIPCRn) The input port change registers (UIPCRn), Figure 14-16, hold the current state and the change-of-state for CTS. 7 Field Reset 5 -- 3 1 111 0000 0 R/W Address 4 COS 0 CTS 11 CTS Read only MBAR + 0x1D0 (UIPCR0), 0x210 (UIPCR1) Figure 14-16. UART Input Port Change Register (UIPCRn) Table 14-12 describes UIPCRn fields. Table 14-12. UIPCRn Field Descriptions Bits Name 7-5 -- 4 COS 3-1 -- 0 CTS Description Reserved, should be cleared. Change of state (high-to-low or low-to-high transition). Not used in modem mode. 0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS]. 1 A change-of-state longer than 25-50 s occurred on the CTS input. UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected. Reserved, should be cleared. Current state. Starting two serial clock periods after reset, CTS reflects the state of CTS. If CTS is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled. This bit is not used in modem mode. 0 The current state of the CTS input is asserted. 1 The current state of the CTS input is negated. 14.3.14 UART Auxiliary Control Register (UACRn) The UART auxiliary control registers (UACRn), Figure 14-12, control the input enable. Chapter 14. UART Modules 14-17 Register Descriptions 7 1 Field -- Reset 0 IEC 0000_0000 R/W Write only Address MBAR + 0x1D0 (UACR0), 0x210 (UACR1) Figure 14-17. UART Auxiliary Control Register (UACRn) Table 14-13 describes UACRn fields. Table 14-13. UACRn Field Descriptions Bits Name 7-1 -- 0 IEC Description Reserved, should be cleared. Input enable control. This bit is not used in modem mode. 0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS]. 1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition on the CTS input (if UIMRn[COS] = 1). 14.3.15 UART Interrupt Status/Mask Registers (UISRn/UIMRn) The UART interrupt status registers (UISRn), Figure 14-18, provide status for all potential interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the internal interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding UISRn bit has no effect on the output. NOTE: True status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module is reset. 7 Field Reset R/W Address COS 6 3 -- 2 1 0 DB FFULL/RxRDY TxRDY 0000_0000 Read only MBAR + 0x1D4 (UISR0), 0x214 (UISR1); MBAR + 0x1D4 (UIMR0), 0x214 (UIMR1) Figure 14-18. UART Interrupt Status/Mask Registers (UISRn/UIMRn) Table 14-14 describes UISRn and UIMRn fields. 14-18 MCF5407 User's Manual Register Descriptions Table 14-14. UISRn/UIMRn Field Descriptions Bits 7 Name Description COS Change-of-state. Not used by UART1 in modem mode. 0 UIPCRn[COS] is not selected. 1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt. 6-3 -- Reserved, should be cleared. 2 DB Delta break. Not used by UART1 in modem mode. 0 No new break-change condition to report. Section 14.3.10, "UART Command Registers (UCRn)," describes the RESET BREAK-CHANGE INTERRUPT command. 1 The receiver detected the beginning or end of a received break. 1 FFULL/ RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if UMR1n[FFULL/RxRDY] RxRDY = 1. Duplicate of USRn[FFULL/RxRDY]. Used by UART1 in modem mode. If FFULL is enabled for UART0 or UART1, DMA channels 2 or 3 are respectively interrupted when the FIFO is full. 0 TxRDY Transmitter ready. This bit is the duplication of USRn[TxRDY]. Used by UART1 in modem mode. 0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TxRDY = 0 are not sent. 1 The transmitter holding register is empty and ready to be loaded with a character. 14.3.16 UART Divider Upper/Lower Registers (UDUn/UDLn) The UDUn registers (formerly called UBG1n) holds the MSB, and the UDLn registers (formerly UBG2n) hold the LSB of the preload value. UDUn and UDLn concatenate to provide a divider to CLKIN for transmitter/receiver operation, as described in Section 14.5.1.2.1, "CLKIN Baud Rates." 7 0 Field Divider MSB Reset 0000_0000 R/W R/W Address MBAR + 0x1D8 (UDU0), 0x218 (UDU1) Figure 14-19. UART Divider Upper Register (UDUn) 7 0 Field Divider LSB Reset 0000_0000 R/W Address R/W MBAR + 0x1DC (UDL0), 0x21C (UDL1) Figure 14-20. UART Divider Lower Register (UDLn) NOTE: The minimum value that can be loaded on the concatenation of UDUn with UDLn is 0x0002. Both UDUn and UDLn are write-only and cannot be read by the CPU. Chapter 14. UART Modules 14-19 Register Descriptions 14.3.17 UART Interrupt Vector Register (UIVRn) The UIVRn, Figure 14-21, contain the 8-bit internal interrupt vector number (IVR). 7 0 Field IVR Reset 0000_1111 R/W R/W Address MBAR + 0x1F0 (UIVR0), 0x230 (UIVR1) Figure 14-21. UART Interrupt Vector Register (UIVRn) Table 14-15 describes UIVRn fields. Table 14-15. UIVRn Field Descriptions Bits Name Description 7-0 IVR Interrupt vector. Indicates the vector number where the address of the exception handler for the specified interrupt is located. UIVRn is reset to 0x0F, indicating an uninitialized interrupt condition. 14.3.18 UART Input Port Register (UIPn) The UART input port registers (UIPn), Figure 14-22, show the current state of the CTS input when the processor is in UART mode. 7 1 Field -- Reset 1111_1111 R/W Read only Address 0 CTS MBAR + 0x1F4 (UIP0), 0x234 (UIP1) Figure 14-22. UART Input Port Register (UIPn) Table 14-16 describes UIPn fields. Table 14-16. UIPn Field Descriptions Bits Name 7-1 -- 0 CTS 14-20 Description Reserved, should be cleared. Current state. The CTS value is latched and reflects the state of the input pin when UIPn is read. Note: This bit has the same function and value as UIPCRn[RTS]. 0 The current state of the CTS input is logic 0. 1 The current state of the CTS input is logic 1. When UART1 is in modem mode, CTS toggles when a frame sync occurs. It is used during testing to synchronize test code running on the CPU with frames transferred on the serial interface. MCF5407 User's Manual UART Module Signal Definitions 14.3.19 UART Output Port Data Registers (UOP1n/UOP0n) In UART mode, the RTS output can be asserted by writing a 1 to UOP1n[RTS] and negated by writing a 1 to UOP0n[RTS]. UOP registers have no effect in modem mode. See Figure 14-23. 7 1 Field -- Reset 0 RTS 0000_0000 R/W Write only Addr UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0) Figure 14-23. UART Output Port Data 1 Register (UOP1/UOP0) Table 14-17 describes UOP1 fields. Table 14-17. UOP1/UOP0 Field Descriptions Bits Name Description 7-1 -- Reserved, should be cleared. 0 RTS Output port parallel output. Controls assertion (UOP1)/negation (UOP0) of RTS output. 0 Not affected. 1 Asserts RTS (UOP1). Negates RTS (UOP0). 14.4 UART Module Signal Definitions Figure 14-24 shows both the external and internal signal groups. CLKIN or External Clock (TIN) Clock Source Generator UART Module Internal Bus Output Port RTS Input Port CTS Four-Character Receive Buffer RxD Two-Character Transmit Buffer TxD Control Interface to CPU Address Bus Internal Control Logic Data To Interrupt Controller (SIM) External Interface Signals IRQ Figure 14-24. UART Block Diagram Showing External and Internal Interface Signals Chapter 14. UART Modules 14-21 UART Module Signal Definitions An internal interrupt request signal (IRQ) is provided to notify the interrupt controller of an interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt level of a UART module is programmed in the interrupt controller in the system integration module (SIM). The UART can use the autovector for the programmed interrupt level or supply the vector from the UIVRn when the UART interrupt is acknowledged. The interrupt level, priority, and auto-vectoring capability is programmed in SIM register ICR4 for UART0 and ICR5 for UART1. See Section 9.2.1, "Interrupt Control Registers (ICR0-ICR9)." Note that the UARTs can also automatically transfer data by using the DMA rather than interrupting the core. When UIMR[FFULL] is 1 and a receiver's FIFO is full, it can send an interrupt to a DMA channel so the FIFO data can be transferred to memory. Note also that UART0 and UART1's interrupt requests are connected to DMA channel 2 and channel 3, respectively. Table 14-18 briefly describes the UART module signals. NOTE: The terms `assertion' and `negation' are used to avoid confusion between active-low and active-high signals. `Asserted' indicates that a signal is active, independent of the voltage level; `negated' indicates that a signal is inactive. Table 14-18. UART Module Signals Signal Description Transmitter Serial Data Output (TxD) In UART mode, TxD is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loop-back mode. Data is shifted out on TxD on the falling edge of the clock source, with the least significant bit (lsb) sent first. For UART1 in modem mode, TxD is held low when the transmitter is disabled or idle. Data is shifted out on TxD on the rising edge of the clock signal driving UART1's CTS input. UART1 transfers can be specified as either lsb or msb first. Receiver Serial Data Input (RxD) Data received on RxD is sampled on the rising edge of the clock source, with the lsb received first. For UART1 in modem mode, data received on RxD is sampled on the falling edge of the clock signal driving UART1's CTS input. UART1 transfers can be specified as either lsb or msb first. Clear-toSend (CTS) This input can generate an interrupt on a change of state. For UART1 in modem mode, CTS must be driven by the serial bit clock from the external CODEC or AC `97 controller. Request-toSend (RTS) This output can be programmed to be negated or asserted automatically by either the receiver or the transmitter. When connected to a transmitter's CTS, RTS can control serial data flow. For UART1 in AC `97 mode, RTS serves as the frame sync or start-of-frame (SOF) output to the external AC `97 controller. When this mode is used, the AC `97 BIT_CLK, which is input on CTS, is divided by 256. Timer Input (TIN1) When UART1 in modem mode is used as an 8- or 16-bit CODEC interface, TIN1 must be driven by the frame sync or SOF output from the external CODEC. SOF is sampled on the falling edge of the bit clock driving CTS. TIN1 can still be used in all timer modes except capture mode when UART1 is being used as an 8- or 16-bit CODEC interface. See Table 14-26. Figure 14-25 shows a signal configuration for a UART/RS-232 interface. 14-22 MCF5407 User's Manual Operation UART RS-232 Transceiver RTS DI2 CTS DO2 TxD DI1 RxD DO1 Figure 14-25. UART/RS-232 Interface Figure 14-26 shows a signal configuration for a UART1/CODEC interface. UART1 MC143416 CODEC TIN1 SSYNC0 CTS SCLK0 TxD SRx0 RxD STx0 Figure 14-26. UART1/CODEC Interface Figure 14-27 shows a signal configuration for a UART1/CODEC interface. An MCF5407 general-purpose I/O (GPIO) is used as a reset to the AC `97 device. UART1 AC '97 RTS FRAME SYNC CTS BIT_CLK TxD SDATA_OUT RxD SDATA_IN GPIO RESET Figure 14-27. UART1/AC '97 Interface 14.5 Operation This section describes operation of the clock source generator, transmitter, and receiver. 14.5.1 Transmitter/Receiver Clock Source CLKIN serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to the UART. The clock generator cannot produce standard baud rates if CLKIN is used, so the 16-bit divider should be used. Chapter 14. UART Modules 14-23 Operation 14.5.1.1 Programmable Divider As Figure 14-28 shows, the UART transmitter and receiver can use the following clock sources: * * An external clock signal on the TIN pin that can be divided by 16. When not divided, TIN provides a synchronous clock mode; when divided by 16, it is asynchronous. CLKIN supplies an asynchronous clock source that is divided by 32 and then divided by the 16-bit value programmed in UDUn and UDLn. See Section 14.3.16, "UART Divider Upper/Lower Registers (UDUn/UDLn)." The choice of TIN or CLKIN is programmed in the UCSR. TOUT On-Chip Timer Module TIN UART Clocking sources programmed in UCSR TxD Tx Buffer x1 Prescaler TIN x16 Prescaler TIN Tx Rx Clock Generator RxD 16-Bit Divider x32 Prescaler Rx Buffer CLKIN Figure 14-28. Clocking Source Diagram NOTE: If TIN is a clocking source for either the timer or UART, as is the case for UART1 used as an 8- or 16-bit CODEC interface, the timer module cannot use TIN for timer capture. 14.5.1.2 Calculating Baud Rates The following sections describe how to calculate baud rates. 14.5.1.2.1 CLKIN Baud Rates When CLKIN is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UDUn and UDLn registers. Using a 54-MHz CLKIN, the baud-rate calculation is as follows: 14-24 MCF5407 User's Manual Operation 54MHz Baudrate = -----------------------------------[ 32 x divider ] Let baud rate = 9600; the divider can be calculated as follows: 54MHz Divider = ----------------------------- = 176 ( decimal ) = 0x00B0 [ 32 x 9600 ] Therefore UDUn = 0x00 and UDLn = 0xB0. 14.5.1.2.2 External Clock An external source clock (TIN) can be used as is or divided by 16. Externalclockfrequency Baudrate = --------------------------------------------------------------------16or1 14.5.2 Transmitter and Receiver Operating Modes Figure 14-29 is a functional block diagram of the transmitter and receiver showing the command and operating registers, which are described generally in the following sections and described in detail in Section 14.3, "Register Descriptions." UART0 UART Command Register (UCR0) UART Transmitter Buffer (UTB0) (2 Registers) W UART Mode Register 1 (UMR1) R/W UART Mode Register 2 (UMR2) R/W UART Status Register (USR0) R Transmitter Holding Register W External Interface TXD Transmitter Shift Register Receiver Holding Register 1 Receiver Holding Register 2 R FIFO (32-byte FIFOs on UART1) Receiver Holding Register 3 UART Receive Buffer (URB0) (4 Registers) Receiver Shift Register RXD Figure 14-29. Transmitter and Receiver Functional Diagram Chapter 14. UART Modules 14-25 Operation 14.5.2.1 Transmitting in UART Mode The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a character, the UART sets USRn[TxRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on TxD. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source. After the stop bits are sent, if no new character is in the transmitter holding register, the TxD output remains high (mark condition) and the transmitter empty bit, USRn[TxEMP], is set. Transmission resumes and TxEMP is cleared when the CPU loads a new character into the UART transmitter buffer (UTBn). If the transmitter receives a disable command, it continues until any character in the transmitter shift register is completely sent. If the transmitter is reset through a software command, operation stops immediately (see Section 14.3.10, "UART Command Registers (UCRn)"). The transmitter is reenabled through the UCRn to resume operation after a disable or software reset. If the clear-to-send operation is enabled, CTS must be asserted for the character to be transmitted. If CTS is negated in the middle of a transmission, the character in the shift register is sent and TxD remains in mark state until CTS is reasserted. If the transmitter is forced to send a continuous low condition by issuing a SEND BREAK command, the transmitter ignores the state of CTS. If the transmitter is programmed to automatically negate RTS when a message transmission completes, RTS must be asserted manually before a message is sent. In applications in which the transmitter is disabled after transmission is complete and RTS is appropriately programmed, RTS is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually reenabled by reasserting RTS before the next message is to be sent. Figure 14-30 shows the functional timing information for the transmitter. 14-26 MCF5407 User's Manual Operation C1 in transmission C11 TxD C2 C3 C4 Break C6 Transmitter Enabled USRn[TxRDY] internal module select W2 W W C11 C2 C3 Start break W W W C4 Stop break W W C5 not transmitted C6 CTS3 RTS4 Manually asserted by BIT-SET command Manually asserted 1 Cn = transmit characters 2 W = write 3 UMR2n[TxCTS] = 1 4 UMR2n[TxRTS] = 1 Figure 14-30. Transmitter Timing Diagram 14.5.2.2 Transmitter in Modem Mode (UART1) After a hardware reset, UART1 is in UART mode. UART1 can be put in one of the modem modes by writing the appropriate value for MODCTL[MODE], as described in Section 14.3.4, "Modem Control Register (MODCTL)." The other MODCTL fields should be initialized at the same time. Set the Tx FIFO threshold as described in Section 14.3.5, "Tx FIFO Threshold Register (TXLVL)." The serial bit clock is always an input to UART1 in modem mode (on CTS). For an 8- or 16-bit CODEC, the frame sync is also an input to UART1 (on TIN1). However for an AC `97 controller, UART1 provides the frame sync (on RTS). Figure 14-31 shows an example timing for UART1-CODEC interfaces (lsb first). CTS TIN1 Frame Sync TxD D0 D1 D2 D14 D15 RxD D0 D1 D2 D14 D15 Figure 14-31. 16-Bit CODEC Interface Timing (lsb First) Chapter 14. UART Modules 14-27 Operation Figure 14-32 is an example timing diagram for the UART1-CODEC interface (msb first). CTS TIN1 Frame Sync TxD D7 D6 D5 D1 D0 RxD D7 D6 D5 D1 D0 Figure 14-32. 8-Bit CODEC Interface Timing (msb First) Figure 14-33 shows an example timing diagram for the UART1-AC `97 interface. CTS RTS TxD Frame Sync bit1 bit2 Frame Sync bit13 bit14 bit15 bit16 20 bits Slot 2 RxD bit1 bit2 bit13 bit14 bit15 bit16 20 bits Slot 2 Slot 1 20 bits Slot 3 20 bits Slot 3 20 bits Slot 13 20 Slot 1 bits Slot 13 Slot 1 Frame Figure 14-33. AC `97 Interface Timing For more information about interfacing to an AC `97 controller, refer to the Audio CODEC `97 Component Specification. When interfaced to an 8- or 16-bit CODEC (MODCTL[MODE] = 01 or 10), UART1 starts to send a sample either during the 1-bit clock cycle after the rising edge of frame sync, according to the value of MODCTL[DTS1]. The width of the frame sync pulse makes no difference. MODCTL[SHDIR] controls whether bits are shifted out msb or lsb first. After the 8- or 16-bit sample is sent, zeros are sent until the next frame sync. When interfacing to an AC `97 controller (MODCTL[MODE] = 11), UART1 starts to transmit time slot 1 data one bit-clock cycle after the rising edge of frame sync, regardless of the value of MODCTL[DTS1]. However, MODCTL[SHDIR] must be 0, because the shift order must be msb first. UART1 divides the bit clock by 256 to generate a frame sync pulse that is high for 16-bit clock cycles. The transmitter sends zeros until the receiver detects the CODEC-ready condition (a 1 in the first bit of a new frame). Because Rx data is sampled on the falling edge of the bit clock, for transmit purposes, the frame has already started when the receiver detects a CODEC-ready condition. For this reason, transmission starts at the next frame sync after the CODEC-ready condition is detected. UART1 stops transmission at the end of the frame in which the first bit of the received frame is detected low (CODEC not ready). During transmission, UART1 fills each of the 13 time slots of the AC `97 frame with samples from the Tx FIFO. 14-28 MCF5407 User's Manual Operation 14.5.2.2.1 AC `97 Low-Power Mode A general-purpose I/O (GPIO) must be used as an AC `97 reset output pin. UART1 monitors the first three time slots of each Tx frame to detect the power-down condition for the AC `97 digital interface. The power-down condition is detected as follows: 1. The first 3 bits of slot 1 must be set, indicating that the Tx frame and slots 1 and 2 are valid. 2. Slot 2 holds the address of the power-down register (0x26) in the external AC `97 device. 3. Slot 3 contains a 1 in the fourth bit (bit 12/PR4 in power-down register 1), as defined in the AC '97 specification. Low-power mode can be left through either a warm or cold reset. The CPU performs a warm reset by setting MODCTL[AWR] for at least 1 s. This negates RTS, which is used as the frame sync output in AC `97 mode. The CPU performs a cold reset in two steps: 1. Writes a 0 to whichever GPIO is being used as the active low AC `97 reset pin for the minimum time specified in the AC `97 specification. 2. Writes a 0 to UART1's MODCTL[ACRB] (bit 7). The CPU sets this bit after writing a 1 to the GPIO used for the AC `97 reset pin. Step 2 is required so UART1 knows when an AC `97 cold reset is occurring. 14.5.2.3 Receiver The receiver is enabled through its UCRn, as described in Section 14.3.10, "UART Command Registers (UCRn)." Figure 14-34 shows receiver functional timing. Chapter 14. UART Modules 14-29 Operation TxD C1 C2 C3 C4 C5 C6 C7 C8 C6, C7, and C8 will be lost Receiver Enabled USRn[RxRDY] USRn[FFULL] internal module select Status Data C5 will be lost (C1) (C2) (C3) (C4) Reset by command Overrun USRn[OE] RTS4 Status Status Status Data Data Data Manually asserted first time, automatically negated if overrun occurs UOP0[RTS] = 1 Automatically asserted when ready to receive Figure 14-34. Receiver Timing When the receiver detects a high-to-low (mark-to-space) transition of the start bit on RxD, the state of RxD is sampled each 16x clock for eight clocks, starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If RxD is sampled high, the start bit is invalid and the search for the valid start bit begins again. If RxD is still low, a valid start bit is assumed and the receiver continues sampling the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the RxD input is sampled on the rising edge of the programmed clock source. The lsb is received first. The data is then transferred to a receiver holding register and USRn[RxRDY] is set. If the character is less than eight bits, the most significant unused bits in the receiver holding register are cleared. After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a non-zero character is received without a stop bit (framing error) and RxD remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit were detected. Parity error, framing error, overrun error, and received break conditions set the respective PE, FE, OE, RB error and break flags in the USRn at the received character boundary and are valid only if USRn[RxRDY] is set. If a break condition is detected (RxD is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register (RHR) and USRn[RB,RxRDY] are set. RxD must return to a high condition for at least one-half bit time before a search for the next start bit begins. 14-30 MCF5407 User's Manual Operation The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. If the break begins in the middle of a character, the receiver places the damaged character in the Rx FIFO stack and sets the corresponding USRn error bits and USRn[RxRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RxRDY]. 14.5.2.4 UART1 in UART Mode After a hardware reset, UART1 is in UART mode and differs from UART0 only with respect to receiver overrun, which is a function of Rx FIFO depth. UART0 has an effective depth of 4 bytes counting the Rx shift register, whereas UART1 has an effective depth of 33 bytes counting the Rx shift register. As a result, an overrun error won't occur in UART1 until 34 bytes are received without a CPU read from the Rx FIFO. In UART0, an overrun error would occur after 5 bytes are received without a CPU read from the Rx FIFO. In all other respects, UART1 in UART mode operates identically to UART0. 14.5.2.4.1 Receiver in Modem Mode (UART1) After a hardware reset, UART1 is in UART mode. Modem modes are chosen by setting MODCTL[MODE]. Other MODCTL fields should be initialized at the same time, as described in Section 14.3.4, "Modem Control Register (MODCTL)." Set the Rx FIFO threshold as described in Section 14.3.3, "Rx FIFO Threshold Register (RXLVL)." The serial bit clock is always an input to UART1 in modem mode (on CTS). When interfacing to an 8- or 16-bit CODEC, the frame sync is also an input to UART1 (on TIN1). However when an AC `97 controller is used, UART1 provides the frame sync (on RTS). Figure 14-31 on page 14-27 and Figure 14-32 on page 14-28 show timing diagrams for the UART1-CODEC interfaces. Figure 14-33 shows an example timing diagram for the UART1-AC `97 interface. When an 8- or 16-bit CODEC is specified (MODCTL[MODE] = 01 or 10), UART1 starts to receive a sample either at the rising edge of frame sync or 1 bit clock cycle after the rising edge of frame sync, according to the value of MODCTL[DTS1]. The width of the frame sync pulse makes no difference. MODCTL[SHDIR] controls whether the sample is shifted in msb or lsb first. After the 8- or 16-bit sample is received, the receiver shift register shuts off until the next frame sync occurs. When an AC `97 controller is specified (MODCTL[MODE] = 11), UART1 starts to receive time slot 1 data one bit-clock cycle after the rising edge of frame sync, regardless of the MODCTL[DTS1] value. However, MODCTL[SHDIR] must be 0 because the shift order must be msb first. Until the receiver detects the CODEC ready condition (a 1 in the first bit of a new frame), no data is put into the Rx FIFO for that frame. When a CODEC ready condition is detected, the receiver starts loading the Rx FIFO with the received time slot samples and continues to do so until a 0 is received in the first bit of a new frame. Chapter 14. UART Modules 14-31 Operation 14.5.2.5 FIFO Stack in UART0 The FIFO stack is used in the UART's receiver buffer logic. The stack consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the RxD (see Figure 14-29). Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple-buffered. In addition to the data byte, three status bits, parity error (PE), framing error (FE), and received break (RB), are appended to each data character in the FIFO; OE (overrun error) is not appended. By programming the ERR bit in the channel's mode register (UMR1n), status is provided in character or block modes. USRn[RxRDY] is set when at least one character is available to be read by the CPU. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are popped and the receiver shift register can add new data at the bottom of the stack. The FIFO-full status bit (FFULL) is set if all three stack positions are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt. The two error modes are selected by UMR1n[ERR] as follows: * * In character mode (UMR1n[ERR] = 0, status is given in the USRn for the character at the top of the FIFO. In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO stack since the last RESET ERROR STATUS command. Status is updated as characters reach the top of the FIFO stack. Block mode offers a data-reception speed advantage where the software overhead of error-checking each character cannot be tolerated. However, errors are not detected until the check is performed at the end of an entire message--the faulting character is not identified. In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when the receive buffer is read. The USRn should be read before reading the receive buffer. If all three receiver holding registers are full, a new character is held in the receiver shift register until space is available. However, if a second new character is received, the contents of the the character in the receiver shift register is lost, the FIFOs are unaffected, and USRn[OE] is set when the receiver detects the start bit of the new overrunning character. To support flow control, the receiver can be programmed to automatically negate and assert RTS, in which case the receiver automatically negates RTS when a valid start bit is detected and the FIFO stack is full. The receiver asserts RTS when a FIFO position becomes available; therefore, overrun errors can be prevented by connecting RTS to the CTS input of the transmitting device. 14-32 MCF5407 User's Manual Operation NOTE: The receiver can still read characters in the FIFO stack if the receiver is disabled. If the receiver is reset, the FIFO stack, RTS control, all receiver status bits, and interrupt requests are reset. No more characters are received until the receiver is reenabled. 14.5.2.6 FIFOs in UART1 For UART1, FIFOs can be accessed as longwords. Other properties are as follows: * * * 8-bit CODEC mode (MODCTL[MODE] = 01): -- Can access FIFOs either one, two, or four 1-byte samples at a time. -- For one-sample accesses, the sample occupies internal data bus bits 31-24. For two-sample accesses, the samples occupy internal data bus bits 31-16.16-bit CODEC mode (MODCTL[MODE] = 10): -- Can access FIFOs one or two 2-byte samples at a time. -- For one-sample accesses, the sample occupies internal data bus bits 31-16. AC `97 mode (MODCTL[MODE] = 11): -- Must access FIFOs one sample at a time -- Because time slot 1 has 16 bits, compared to 20 for all other time slots in a frame, time slot 1 data occupies internal data bus bits 31-16. -- All 20-bit time slots occupy internal data bus bits 31-12 for Tx and Rx FIFOs. -- In addition, when the Rx FIFO is being read, a 1 in internal data bus bit 11 marks this sample as the first time slot of a new frame. The Tx FIFO functions as follows: * * AC `97 mode--Tx FIFO is effectively a 16 x 20 dual-port RAM to hold sixteen 20-bit AC `97 time slots. One sample/time slot is written to Tx FIFO per internal bus cycle. For all other modes the Tx FIFO is effectively 8 x 32. -- 8-bit CODEC or as a UART--Tx FIFO can hold thirty-two 8-bit samples. One, two, or four bytes/samples can be written to Tx FIFO per internal bus cycle. -- 16-bit CODEC--Tx FIFO can hold sixteen 16-bit samples. Either one or two 16-bit samples can be written to Tx FIFO per internal bus cycle. The Rx FIFO functions as follows: * AC `97 mode--Rx FIFO is effectively a 16 x 21 dual-port RAM to hold sixteen 20-bit AC `97 time slots. The extra flag bit is set to indicate the first time slot of a new AC `97 frame. One sample/time slot is read from Rx FIFO per internal bus cycle. Chapter 14. UART Modules 14-33 Operation * For all other modes, the Rx FIFO is effectively 8 x 32. -- 8-bit CODEC or as a UART--Rx FIFO holds thirty-two 8-bit samples. One, two, or four bytes/samples can be read from the Rx FIFO per internal bus cycle. -- 16-bit CODEC--Rx FIFO holds sixteen 16-bit samples. Either one or two 16-bit samples can be read from the Rx FIFO per internal bus cycle. 14.5.3 Looping Modes The UART can be configured to operate in various looping modes as shown in Figure 14-34 on page 14-30. These modes are useful for local and remote system diagnostic functions and can be used by UART1 in modem mode as well as UART mode. The modes are described in the following paragraphs and in Section 14.3, "Register Descriptions." The UART's transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. 14.5.3.1 Automatic Echo Mode In automatic echo mode, shown in Figure 14-35, the UART automatically resends received data bit by bit. The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. In this mode, received data is clocked on the receiver clock and resent on TxD. The receiver must be enabled, but the transmitter need not be. RxD Input Rx CPU Disabled Tx Disabled TxD Input Figure 14-35. Automatic Echo Because the transmitter is inactive, USRn[TxEMP,TxRDY] are inactive and data is sent as it is received. Received parity is checked but is not recalculated for transmission. Character framing is also checked, but stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected. 14.5.3.2 Local Loop-Back Mode Figure 14-36 shows how TxD and RxD are internally connected in local loop-back mode. This mode is for testing the operation of a local UART module channel by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations. Rx Disabled RxD Input Disabled TxD Input CPU Tx Figure 14-36. Local Loop-Back 14-34 MCF5407 User's Manual Operation Features of this local loop-back mode are as follows: * * * * Transmitter and CPU-to-receiver communications continue normally in this mode. RxD input data is ignored TxD is held marking The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be. 14.5.3.3 Remote Loop-Back Mode In remote loop-back mode, shown in Figure 14-37, the channel automatically transmits received data bit by bit on the TxD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. For this mode, the transmitter uses the receiver clock. Because the receiver is not active, received data cannot be read by the CPU and error status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected. Disabled Rx Disabled RxD Input Disabled TxD Input CPU Disabled Tx Figure 14-37. Remote Loop-Back 14.5.4 Multidrop Mode Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations. Although slave stations have their channel receivers disabled, they continuously monitor the master's data stream. When the master sends an address character, the slave receiver channel notifies its respective CPU by setting USRn[RxRDY] and generating an interrupt (if programmed to do so). Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. Slave stations not addressed continue monitoring the data stream. Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Chapter 14. UART Modules 14-35 Operation Functional timing information for multidrop mode is shown in Figure 14-38. Master Station A/D TxD ADD1 1 A/D A/D C0 ADD2 1 Transmitter Enabled USRn[TxRDY] internal module select UMR1n[PM] = 11 UMR1n[PT] = 1 ADD 1 C0 UMR1n[PT] = 0 ADD 2 UMR1n[PT] = 2 Peripheral Station RxD A/D A/D 0 ADD1 1 A/D C0 A/D A/D ADD2 1 0 Receiver Enabled USRn[RxRDY] internal module select UMR1n[PM] = 11 UMR1n[PM] = 11 ADD 1 Status Data (C0) Status Data (ADD 2) Figure 14-38. Multidrop Mode Timing Diagram A character sent from the master station consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D = 1 indicates an address character; A/D = 0 indicates a data character. The polarity of A/D is selected through UMR1n[PT]. UMR1n should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer. In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the receiver holding register FIFO stack provided the received A/D bit is a one (address tag). The character is discarded if the received A/D bit is zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU through the receiver holding register stack during read operations. In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the status portion of the stack normally used for a parity error (USRn[PE]). Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still contain error detection and correction information. One way to provide error 14-36 MCF5407 User's Manual Operation detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. 14.5.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 14.5.5.1 Read Cycles The UART module responds to reads with byte data. Reserved registers return zeros. 14.5.5.2 Write Cycles The UART module accepts write data as bytes. Write cycles to read-only or reserved registers complete normally without exception processing, but data is ignored. NOTE: The UART module is accessed by the CPU with zero wait states, as CLKIN is used for the UART module. 14.5.5.3 Interrupt Acknowledge Cycles The UART module supplies the interrupt vector in response to a UART IACK cycle. If UIVRn is not initialized to provide a vector number, a spurious exception is taken if an interrupt is generated. This works in conjunction with the interrupt controller, which allows a programmable priority level. 14.5.6 Programming The software flowchart, Figure 14-39, consists of the following: * * UART module initialization--These routines consist of SINIT and CHCHK (sheets 1 and 2). Before SINIT is called at system initialization, the calling routine allocates 2 words on the system stack. On return to the calling routine, SINIT passes UART status data on the stack. If SINIT finds no errors, the transmitter and receiver are enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the UART in local loop-back mode and checks for the following errors: -- Transmitter never ready -- Receiver never ready -- Parity error -- Incorrect character received I/O driver routine--This routine (sheets 4 and 5) consists of INCH, the terminal input character routine which gets a character from the receiver, and OUTCH, which sends a character to the transmitter. Chapter 14. UART Modules 14-37 Operation * Interrupt handling--Consists of SIRQ (sheet 4), which is executed after the UART module generates an interrupt caused by a change-in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 14.5.6.1 UART Module Initialization Sequence NOTE: UART module registers can be accessed by word or byte operations, but only data byte D[7:0] is valid. Table 14-19 shows the UART module initialization sequence. Table 14-19. UART Module Initialization Sequence Register Setting UCRn Reset the receiver and transmitter--UART or modem modes. Reset the mode pointer (MISC[2-0] = 0b001)--UART or modem modes. UIVRn Program the vector number for a UART module interrupt--UART or modem modes. UIMRn Enable the preferred interrupt sources--UART or modem modes. UACRn Initialize the input enable control (IEC bit)--UART mode only. UCSRn Select the receiver and transmitter clock. Use timer as source if required--UART mode only. UMR1n If preferred, program operation of receiver ready-to-send (RxRTS bit)--UART mode only. Select receiver-ready or FIFO-full notification (RxRDY/FFULL bit)--UART or modem modes. Select character or block error mode (ERR bit)--UART mode only. Select parity mode and type (PM and PT bits)--UART mode only. Select number of bits per character (B/Cx bits)--UART mode only. UMR2n Select the mode of operation (CMx bits)--UART or modem modes. If preferred, program operation of transmitter ready-to-send (TxRTS)--UART mode only. If preferred, program operation of clear-to-send (TxCTS bit)--UART mode only. Select stop-bit length (SBx bits)--UART mode only. RXLVL UART1 only, UART or modem modes--Choose Rx FIFO full threshold level. TXLVL UART1 only, UART or modem modes--Choose Tx FIFO empty threshold level. MODCTL Modem mode only Choose the desired modem mode. Choose whether msb or lsb is to be transferred first. Choose 0- or 1-bit delay between rising edge of frame sync and first bit of time slot 1. Choose 1 or 2 DMA channels to service UART1. Activate/deactivate AC `97 warm and cold resets. UCRn Enable the receiver and transmitter--UART or modem modes. 14-38 MCF5407 User's Manual Operation ENABLE ENABLA SERIAL MODULE SINIT ANY ERRORS ? INITIATE: Y N CHANNEL INTERRUPTS ENABLE RECEIVER CHK1 CALL CHCHK SAVE CHANNEL STATUS ASSERT REQUEST TO SEND SINITR RETURN Figure 14-39. UART Mode Programming Flowchart (Sheet 1 of 5) Chapter 14. UART Modules 14-39 Operation CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE TRANSMITTER CLEAR STATUS WORD TxCHK N IS TRANSMITTER READY ? N Y WAITED TOO LONG ? Y SET TRANSMITTERNEVER-READY FLAG Y SET RECEIVERNEVER-READY FLAG N Y SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK N HAS CHARACTER BEEN RECEIVED ? N WAITED TOO LONG ? Y A B Figure 14-39. UART Mode Programming Flowchart (Sheet 2 of 5) 14-40 MCF5407 User's Manual Operation B A FRCHK RSTCHN HAVE FRAMING ERROR ? N Y DISABLE TRANSMITTER RESTORE TO ORIGINAL MODE SET FRAMING ERROR FLAG PRCHK RETURN HAVE PARITY ERROR ? N Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER ? Y N SET INCORRECT CHARACTER FLAG B Figure 14-39. UART Mode Programming Flowchart (Sheet 3 of 5) Chapter 14. UART Modules 14-41 Operation INCH SIRQ ABRKI WAS IRQ CAUSED BY BEGINNING OF A BREAK ? Y N DOES CHANNEL A RECEIVER HAVE A CHARACTER ? N Y PLACE CHARACTER IN D0 CLEAR CHANGE-INBREAK STATUS BIT ABRKI1 HAS END-OF-BREAK IRQ ARRIVED YET ? RETURN N Y CLEAR CHANGE-INBREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE Figure 14-39. UART Mode Programming Flowchart (Sheet 4 of 5) 14-42 MCF5407 User's Manual Operation OUTCH IS TRANSMITTER READY ? N Y SEND CHARACTER TO TRANSMITTER RETURN Figure 14-39. UART Mode Programming Flowchart (Sheet 5 of 5) Chapter 14. UART Modules 14-43 Operation 14-44 MCF5407 User's Manual Chapter 15 Parallel Port (General-Purpose I/O) This chapter describes the operation and programming model of the parallel port pin assignment, direction-control, and data registers. It includes a code example for setting up the parallel port. 15.1 Parallel Port Operation The MCF5407 parallel port module has 16 signals, which are programmed as follows: * * * The pin assignment register (PAR) selects the function of the 16 multiplexed pins. Port A data direction register (PADDR) determines whether pins configured as parallel port signals are inputs or outputs. The Port A data register (PADAT) shows the status of the parallel port signals. The operations of the PAR, PADDR, and PADAT are described in the following sections. 15.1.1 Pin Assignment Register (PAR) The pin assignment register (PAR), which is part of the system integration module (SIM), defines how each PAR bit determines each pin function, as shown in Figure 15-1. 15 14 13 12 11 10 9 8 7 Field PAR15 PAR14 PAR13 PAR12 PAR11 PAR10 PAR9 PAR8 PAR7 6 5 4 2 1 0 PAR5 PAR4 PAR3 PAR2 PAR1 PAR0 PP6 PP5 PP2 PAR[n] = 0 PP15 PP14 PP13 PP12 PP11 PP10 PP9 PP8 PP7 PAR[n] = 1 A30 A29 A28 A27 A26 A25 A24 TIP DREQ0 DREQ1 TM2 A31 3 PAR6 PP4 PP3 PP1 PP0 TM1/ TM0/ TT1 DACK1 DACK0 TT0 Reset Determined by driving D4/ADDR_CONFIG with a 1 or 0 when RSTI negates. The system is configured as PP[15:0] if D4 is low; otherwise alternate pin functions selected by PAR[n] = 1 are used. R/W Address R/W Address MBAR + 0x004 Figure 15-1. Parallel Port Pin Assignment Register (PAR) If PP[9:8]/A[25:24] are unavailable because A[25:0] are needed for external addressing, PP[15:10]/A[31:26] can be configured as general-purpose I/O. Table 15-1 summarizes MCF5407 parallel port pins, described in detail in Chapter 17, "Signal Descriptions." Chapter 15. Parallel Port (General-Purpose I/O) 15-1 Parallel Port Operation Table 15-1. Parallel Port Pin Descriptions Pin Description PP[15:8]/ A[31:24] MSB of the address bus/parallel port. Programmed through PAR[15-8]. If a PAR bit is 0, the associated pin functions as a parallel port signal. If a bit is 1, the pin functions as an address bus signal. If all pins are address signals, as much as 4 Gbytes of memory space are available. TIP/PP7 Transfer-in-progress output/parallel port bit 7. Programmed through PAR[7]. Assertion indicates a bus transfer is in progress; negation indicates an idle bus cycle if the bus is still granted to the processor. Note that TIP is held asserted on back-to-back bus cycles. DREQ[1:0]/ DMA request inputs/two bits of the parallel port. Programmed through PAR[6-5]. These inputs are PP[6:5] asserted by a peripheral device to request a DMA transfer. TM[2:0]/ PP[4:2]/ DACK[1:0] Transfer type outputs/parallel port bits 4-2. Programmed through PAR[4-2]. For DMA transfers, these signals provide acknowledge information or can be programmed to function as DMA acknowledge signals. For emulation transfers, TM[2:0] indicate user or data transfer types. For CPU space transfers, TM[2:0] are low. For interrupt acknowledge transfers, TM[2:0] carry the interrupt level being acknowledged. TT[1:0]/ PP[1:0] Transfer type outputs/parallel port bits 1-0. Programmed through PAR[1-0]. When the MCF5407 is bus master, it outputs these signals. They indicate the current bus access type. 15.1.2 Port A Data Direction Register (PADDR) The PADDR determines the signal direction of each parallel port pin programmed as a general-purpose I/O port in the PAR. 15 0 Field PADDR Reset 0000_0000_0000_0000 R/W R/W Address Address MBAR + 0x244 Figure 15-2. Port A Data Direction Register (PADDR) Table 15-2 describes PADDR fields. Table 15-2. PADDR Field Description Bits Name 15-0 PADDR Description Data direction bits. Each data direction bit selects the direction of the signal as follows: 0 Signal is defined as an input. 1 Signal is defined as an output. 15.1.3 Port A Data Register (PADAT) The PADAT value for inputs corresponds to the logic level at the pin; for outputs, the value corresponds to the logic level driven onto the pin. Note the following: * 15-2 PADAT has no effect on pins not configured for general-purpose I/O. MCF5407 User's Manual Parallel Port Operation * * PADAT settings do not affect inputs. PADAT bit values determine the corresponding logic levels of pins configured as outputs. PADAT can be written to anytime. A read from PADAT returns values of corresponding pins configured as general-purpose I/O in the PAR and designated as inputs by the PADDR. 15 0 Field PADAT Reset 0000_0000_0000_0000 R/W R/W Address Address MBAR+0x248 Figure 15-3. Port A Data Register (PADAT) Table 15-3 shows relationships between PADAT bits and parallel port pins when PADAT is accessed. The effect differs when the parallel port pin is an input or output. The following results occur when a parallel port pin is configured as an input: * * When the PADAT is read, the value returned is the logic value on the pin. When the PADAT is written, the register contents are updated without affecting the logic value on the pin. The following results occur when a parallel port pin is configured as an output: * * When the PADAT is read, the register contents are returned and the pin is the logic value of the register. When the PADAT is written, the register contents are updated and the pin is the logic value of the register. These relationships are also described in Table 15-3. Table 15-3. Relationship between PADAT Register and Parallel Port Pin (PP) PP Status PADAT R/W Read Effect on PADAT Effect on PP Register bit value is the pin's logic value No effect. Source of logic value Input Write Register contents updated No effect on the logic value at the pin Read Register contents are returned Pin is the logic value of the register bit Write Register contents updated Pin is the logic value of the register bit Output NOTE: Although external devices cannot access the MCF5407's on-chip memories or MBAR, they can access any parallel port module registers in the SIM. Chapter 15. Parallel Port (General-Purpose I/O) 15-3 Parallel Port Operation 15.1.4 Code Example The following code example shows how to set up the parallel port. Here, PP[7:0] are general-purpose I/O, PP[3:0] are inputs, and PP[7:4] are outputs. 15-4 MBARx PAR PADDR PADAT EQU EQU EQU EQU 0x00010000 MBARx+0x004 MBARx+0x244 MBARx+0x248 move.l movec move.w move.w move.w move.w move.b move.b #MBARx,D0 D0, MBAR #0x00FF,D0 D0,PAR #0x00F0,D0 D0,PADDR #0xA0,D0 D0,PADAT ;because MBAR is an internal register, MBARx is used as ;label for the memory map address ;set up the PAR. PP[7:0] set up as I/O ;set PP[7:4] as outputs; PP[3:0] as inputs ;0xA0 written into PADAT; PP[7:4] being outputs, ;PP[7:4] becomes 1010; i.e. PP7, PP5 = 1 and ;PP6, PP4 = 0 MCF5407 User's Manual Part IV Hardware Interface Intended Audience Part IV is intended for hardware designers who need to know the functions and electrical characteristics of the MCF5407 interface. It includes a pinout, and both electrical and functional descriptions of the MCF5407 signals. It also describes how these signals interact to support the variety of bus operations shown in timing diagrams. Contents Part IV contains the following chapters: * * * * * Chapter 16, "Mechanical Data," provides a functional pin listing and package diagram for the MCF5407. Chapter 17, "Signal Descriptions," provides an alphabetical listing of MCF5407 signals. This chapter describes the MCF5407 signals. In particular, it shows which are inputs or outputs, how they are multiplexed, which signals require pull-up resistors, and the state of each signal at reset. Chapter 18, "Bus Operation," describes data transfers, error conditions, bus arbitration, and reset operations. It describes transfers initiated by the MCF5407 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. Note that Chapter 11, "Synchronous/Asynchronous DRAM Controller Module," describes DRAM cycles. Chapter 19, "IEEE 1149.1 Test Access Port (JTAG)," describes configuration and operation of the MCF5407 JTAG test implementation. It describes the use of JTAG instructions and how to disable JTAG functionality. Chapter 20, "Electrical Specifications," describes AC and DC electrical specifications and thermal characteristics for the MCF5407. Because additional speeds may have become available since the publication of this book, consult Motorola's ColdFire web page, http://www.motorola.com/coldfire, to confirm that this is the latest information. Part IV. Hardware Interface IV-i Suggested Reading The following literature may be helpful with respect to the topics in Part IV: * * IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Supplement to Standard Test Access Port and Boundary-Scan Architecture (1149.1) Acronyms and Abbreviations Table IV-i describes acronyms and abbreviations used in Part IV. Table IV-i. Acronyms and Abbreviated Terms Term Meaning BDM Background debug mode BIST Built-in self test BSDL Boundary-scan description language DMA Direct memory access DSP Digital signal processing EDO Extended data output (DRAM) GPIO General-purpose I/O I2C Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LSB Least-significant byte lsb Least-significant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex PCLK Processor clock PLL Phase-locked loop POR Power-on reset PQFP Plastic quad flat pack IV-ii MCF5407 User's Manual Table IV-i. Acronyms and Abbreviated Terms (Continued) Term Meaning RISC Reduced instruction set computing Rx Receive SIM System integration module TAP Test access port TTL Transistor-to-transistor logic Tx Transmit Part IV. Hardware Interface IV-iii IV-iv MCF5407 User's Manual Chapter 16 Mechanical Data This chapter provides a function pin listing and package diagram for the MCF5407. See the website [http://www.motorola.com/coldfire] for any updated information. 16.1 Package The MCF5407 is assembled in a 208-pin, thermally enhanced plastic QFP package. 16.2 Pinout The MCF5407 pinout is detailed in the following tables, including the primary and secondary functions of multiplexed signals. Additional columns indicate the output drive capability of each pin, whether it is internally synchronized, and if the signal can change on a negative clock transition. Note that the pin names IVCC and EVCC indicate which pins require 1.8- and 3.3-V power inputs, respectively. These tables show MCF5407 pin numbers, including signal multiplexing. Additional columns indicate the direction, description, and output drive capability of each pin. Table 16-1. Pins 1-52 (Left, Top-to-Bottom) Pin Alternate Function I/O Description Drive (mA) No Name 1 IVCC -- -- 1.8-V power input -- 2 A0 -- I/O Address bus bit 8 3 A1 -- I/O Address bus bit 8 4 GND -- -- Ground pin -- 5 A2 -- I/O Address bus bit 8 6 A3 -- I/O Address bus bit 8 7 EVCC -- -- 3.3-V power input -- 8 A4 -- I/O Address bus bit 8 9 A5 -- I/O Address bus bit 8 10 GND -- -- Ground pin -- 11 A6 -- I/O Address bus bit 8 Chapter 16. Mechanical Data 16-1 Pinout Table 16-1. Pins 1-52 (Left, Top-to-Bottom) (Continued) Pin No 16-2 Name Alternate Function I/O Description Drive (mA) 12 A7 -- I/O Address bus bit 8 13 EVCC -- -- 3.3-V power input -- 14 A8 -- I/O Address bus bit 8 15 A9 -- I/O Address bus bit 8 16 A10 -- I/O Address bus bit 8 17 GND -- -- Ground pin -- 18 A11 -- I/O Address bus bit 8 19 A12 -- I/O Address bus bit 8 20 A13 -- I/O Address bus bit 8 21 EVCC -- -- 3.3-V power input -- 22 A14 -- I/O Address bus bit 8 23 A15 -- I/O Address bus bit 8 24 A16 -- I/O Address bus bit 8 25 GND -- -- Ground pin -- 26 A17 -- I/O Address bus bit 8 27 A18 -- I/O Address bus bit 8 28 A19 -- I/O Address bus bit 8 29 EVCC -- -- 3.3-V power input -- 30 A20 -- I/O Address bus bit 8 31 A21 -- I/O Address bus bit 8 32 A22 -- I/O Address bus bit 8 33 GND -- -- Ground pin -- 34 A23 -- I/O Address bus bit 8 35 PP8 A24 I/O Parallel port bit/Address bus bit 8 36 PP9 A25 I/O Parallel port bit/Address bus bit 8 37 EVCC -- -- 3.3-V power input -- 38 PP10 A26 I/O Parallel port bit/Address bus bit 8 39 PP11 A27 I/O Parallel port bit/Address bus bit 8 40 PP12 A28 I/O Parallel port bit/Address bus bit 8 -- 41 GND -- -- Ground pin 42 PP13 A29 I/O Parallel port bit/Address bus bit 8 43 PP14 A30 I/O Parallel port bit/Address bus bit 8 44 PP15 A31 I/O Parallel port bit/Address bus bit 8 45 EVCC -- -- 3.3-V power input -- 46 SIZ0 -- I/O Size attribute 8 MCF5407 User's Manual Pinout Table 16-1. Pins 1-52 (Left, Top-to-Bottom) (Continued) Pin No Name Alternate Function I/O Description Drive (mA) 47 SIZ1 -- I/O Size attribute 8 48 GND -- -- Ground pin -- 49 OE -- O Output enable for chip selects 8 50 CS0 -- O Chip select 8 51 CS1 -- O Chip select 8 52 EVCC -- -- 3.3-V power input -- Table 16-2. Pins 53-104 (Bottom, Left-to-Right) Pin Alternate Function I/O GND -- -- Ground pin -- 54 CS2 -- O Chip select 8 55 CS3 -- O Chip select 8 56 CS4 -- O Chip select 8 No Name 53 Description Drive (mA) 57 IVCC -- -- 1.8-V power input -- 58 CS5 -- O Chip select 8 59 CS6 -- O Chip select 8 60 CS7 -- O Chip select 8 61 GND -- -- Ground pin -- 62 AS -- I/O Address strobe 8 63 R/W -- I/O Read/Write 8 64 TA -- I/O Transfer acknowledge 8 65 EVCC -- -- 3.3-V power input -- 66 TS -- I/O Transfer start 8 67 RSTI -- I Reset -- 68 IRQ7 -- I Interrupt request -- 69 GND -- -- Ground pin -- 70 IRQ5 IRQ4 I Interrupt request -- 71 IRQ3 IRQ6 I Interrupt request -- 72 IRQ1 IRQ2 I Interrupt request -- 73 IVCC -- -- 1.8-V power input -- 74 BR -- O Bus request 8 75 BD -- O Bus driven 8 76 BG -- I Bus grant -- Chapter 16. Mechanical Data 16-3 Pinout Table 16-2. Pins 53-104 (Bottom, Left-to-Right) (Continued) Pin No 1 16-4 Name Alternate Function I/O Description Drive (mA) 77 GND -- -- Ground pin -- 78 TOUT1 -- O Timer output 8 79 TOUT0 -- O Timer output 8 80 TIN0 -- I Timer input -- 81 EVCC -- -- 3.3-V power input -- 82 TIN1 -- I Timer input -- 83 RAS0 -- O DRAM row address strobe 16 84 RAS1 -- O DRAM row address strobe 16 85 GND -- -- Ground pin -- 86 CAS0 -- O DRAM column address strobe 16 87 CAS1 -- O DRAM column address strobe 16 88 CAS2 -- O DRAM column address strobe 16 89 EVCC -- -- 3.3-V power input -- 90 CAS3 -- O DRAM column address strobe 16 91 DRAMW -- O DRAM write 16 92 SRAS -- O SDRAM row address strobe 16 93 GND -- -- Ground pin -- 94 SCAS -- O SDRAM column address strobe 16 95 SCKE -- O SDRAM clock enable 16 96 BE0 BWE0 O Byte enable/byte write enable 8 97 EVCC -- -- 3.3-V power input -- 98 BE1 BWE1 O Byte enable/byte write enable 8 99 BE2 BWE2 O Byte enable/byte write enable 8 100 BE3 BWE3 O Byte enable/byte write enable 8 101 GND -- -- Ground pin -- 102 SCL -- I/OD 1 Serial clock line 8 103 SDA -- I/OD 1 Serial data line 8 104 GND -- -- Ground pin OD: Open-drain output MCF5407 User's Manual -- Pinout Table 16-3. Pins 105-156 (Right, Bottom-to-Top) Pin No Name 105 IVCC Alternate Function I/O -- -- Description 1.8-V power input Drive (mA) -- 106 D31 -- I/O Data bus 8 107 D30 -- I/O Data bus 8 108 D29 -- I/O Data bus 8 109 GND -- -- Ground pin -- 110 D28 -- I/O Data bus 8 111 D27 -- I/O Data bus 8 112 D26 -- I/O Data bus 8 113 EVCC -- -- 3.3-V power input -- 114 D25 -- I/O Data bus 8 115 D24 -- I/O Data bus 8 116 D23 -- I/O Data bus 8 117 GND -- -- Ground pin -- 118 D22 -- I/O Data bus 8 119 D21 -- I/O Data bus 8 120 D20 -- I/O Data bus 8 121 EVCC -- -- 3.3-V power input -- 122 D19 -- I/O Data bus 8 123 D18 -- I/O Data bus 8 124 D17 -- I/O Data bus 8 125 GND -- -- Ground pin -- 126 D16 -- I/O Data bus 8 127 D15 -- I/O Data bus 8 128 D14 -- I/O Data bus 8 129 EVCC -- -- 3.3-V power input -- 130 D13 -- I/O Data bus 8 131 D12 -- I/O Data bus 8 132 D11 -- I/O Data bus 8 133 GND -- -- Ground pin -- 134 D10 -- I/O Data bus 8 135 D9 -- I/O Data bus 8 136 D8 -- I/O Data bus 8 137 EVCC -- -- 3.3-V power input -- 138 D7 CS_CONF2 I/O Data bus/Chip select configuration 8 Chapter 16. Mechanical Data 16-5 Pinout Table 16-3. Pins 105-156 (Right, Bottom-to-Top) (Continued) Pin No Name Alternate Function I/O Description Drive (mA) 139 D6 CS_CONF1 I/O Data bus/Chip select configuration 8 140 D5 CS_CONF0 I/O Data bus/Chip select configuration 8 141 GND -- -- Ground pin -- 142 D4 ADDR_CONF I/O Data bus/Address configuration 8 143 D3 BE_CONFIG0 I/O Data bus/Byte enable configuration 8 144 D2 DIVIDE2 I/O Data bus/Divide control PCLK:CLKIN 8 145 EVCC -- -- 3.3-V power input -- 146 D1 DIVIDE1 I/O Data bus/Divide control PCLK:CLKIN 8 147 D0 DIVIDE0 I/O Data bus/Divide control PCLK:CLKIN 8 Ground pin -- 148 GND -- -- 149 DSCLK TRST I Debug serial clock/JTAG Reset -- 150 TCK TCK I JTAG clock -- 151 DSO TDO O Debug serial out/JTAG data out 8 152 IVCC -- -- 1.8-V power input -- 153 DSI TDI I Debug serial input/JTAG data in -- 154 BKPT TMS I Debug breakpoint/JTAG mode select -- 155 HIZ -- I High impedance override -- 156 GND -- -- Ground pin -- Table 16-4. Pins 157-208 (Top, Right-to-Left) Pin 16-6 Alternate Function I/O IVCC -- -- 158 CTS1 -- 159 RTS1 -- 160 RXD1 -- I 161 TXD1 -- O UART1 transmit data 8 162 GND -- -- Ground pin -- -- No Name 157 Description Drive (mA) 1.8-V power input -- I UART1 clear-to-send -- O UART1 request-to-send 8 UART1 receive data -- 163 CTS0 -- I UART0 clear-to-send 164 RTS0 -- O UART0 request-to-send 8 165 RXD0 -- I UART0 receive data -- 166 TXD0 -- O UART0 transmit data 8 167 EVCC -- -- 3.3-V power input -- MCF5407 User's Manual Pinout Table 16-4. Pins 157-208 (Top, Right-to-Left) (Continued) Pin Alternate Function I/O No Name 168 EDGESEL -- I 169 GND -- -- Description Drive (mA) SDRAM bus clock edge select -- Ground pin -- 170 BCLKO -- O Bus clock output 16 171 IVCC -- -- 1.8-V power input -- 172 RSTO -- O Processor reset output 8 173 GND -- -- Ground pin -- 174 CLKIN -- I Clock input -- 175 IVCC -- -- 1.8-V power input -- 176 MTMOD0 -- I JTAG/BDM select (Tie high or low) -- 177 MTMOD1 -- I Tie high or low -- 178 PGND -- -- PLL ground pin -- 179 NC -- O 180 PVCC -- -- 181 MTMOD2 -- I 182 MTMOD3 -- I Tie high or low -- 183 GND -- -- Ground pin -- 184 PSTCLK -- O Processor status clock 8 -- 1.8-V filter supply for PLL -- Tie high or low -- 185 IVCC -- -- 1.8-V power input -- 186 PSTDDATA0 -- O Processor status/debug data 8 187 PSTDDATA1 -- O Processor status/debug data 8 188 GND -- -- Ground pin -- 189 PSTDDATA2 -- O Processor status/debug data 8 190 PSTDDATA3 -- O Processor status/debug data 8 191 EVCC -- -- 3.3-V power input -- 192 PSTDDATA4 -- O Processor status/debug data 8 193 PSTDDATA5 -- O Processor status/debug data 8 194 GND -- -- Ground pin -- 195 PSTDDATA6 -- O Processor status/debug data 8 196 PSTDDATA7 -- O Processor status/debug data 8 197 IVCC -- -- 1.8-V power input -- 198 PP7 TIP I/O Parallel port bit/transfer in progress 8 199 PP6 DREQ0 I/O Parallel port bit/DMA request 8 200 PP5 DREQ1 I/O Parallel port bit/DMA request 8 201 GND -- -- Ground pin -- 202 PP4 TM2 I/O Parallel port bit/Transfer modifier 8 Chapter 16. Mechanical Data 16-7 Mechanical Diagram Table 16-4. Pins 157-208 (Top, Right-to-Left) (Continued) Pin 1 Alternate Function I/O PP3 TM1/DACK11 I/O Parallel port bit/Transfer modifier/DMA acknowledge 8 204 PP2 TM0/DACK01 I/O Parallel port bit/Transfer modifier/DMA acknowledge 8 205 EVCC -- -- 3.3-V power input -- 206 PP1 TT1 I/O Parallel port bit/Transfer type 8 207 PP0 TT0 I/O Parallel port bit/Transfer type 8 208 GND -- -- Ground pin -- No Name 203 Description When the internal DMA is used, PP3 and PP2 (PP[3:2]/TM[1:0]) can be programmed to a third function, (DACK[1:0]), which indicates DMA acknowledge. 16.3 Mechanical Diagram Figure 16-1 is a mechanical diagram of the 208-pin QFP MCF5407. 16-8 MCF5407 User's Manual Drive (mA) GND PP0 PP1 EVCC PP2 PP3 PP4 GND PP5 PP6 PP7 IVCC PSTDDATA7 PSTDDATA6 GND PSTDDATA5 PSTDDATA4 EVCC PSTDDATA3 PSTDDATA2 GND PSTDDATA1 PSTDDATA0 IVCC PSTCLK GND MTMOD3 MTMOD2 PVCC NC PGND MTMOD1 MTMOD0 IVCC CLKIN GND RSTO IVCC BCLKO GND EDGESEL EVCC TXD0 RXD0 RTS0 CTS0 GND TXD1 RXD1 RTS1 CTS1 IVCC Case Drawing 156 160 165 170 175 180 185 190 205 1 IVCC A0 A1 GND A2 A3 EVCC A4 A5 GND A6 A7 EVCC A8 A9 A10 GND A11 A12 A13 EVCC A14 A15 A16 GND A17 A18 A19 EVCC A20 A21 A22 GND A23 PP8 PP9 EVCC PP10 PP11 PP12 GND PP13 PP14 PP15 EVCC SIZ0 SIZ1 GND OE CS0 CS1 EVCC 195 157 200 208 GND HIZ BKPT DSI IVCC DSO TCK DSCLK GND D0 D1 EVCC D2 D3 D4 GND D5 D6 D7 EVCC D8 D9 D10 GND D11 D12 D13 EVCC D14 D15 D16 GND D17 D18 D19 EVCC D20 D21 D22 GND D23 D24 D25 EVCC D26 D27 D28 GND D29 D30 D31 IVCC 155 5 150 10 145 15 140 20 135 25 130 30 125 35 120 40 115 45 110 100 95 90 85 80 75 70 65 52 60 55 50 105 104 GND CS2 CS3 CS4 IVCC CS5 CS6 CS7 GND AS R/W TA EVCC TS RSTI IRQ7 GND IRQ5 IRQ3 IRQ1 IVCC BR BD BG GND TOUT1 TOUT0 TIN0 EVCC TIN1 RAS0 RAS1 GND CAS0 CAS1 CAS2 EVCC CAS3 DRAMW SRAS GND SCAS SCKE BE0 EVCC BE1 BE2 BE3 GND SCL SDA GND 53 105 Figure 16-1. Mechanical Diagram 16.4 Case Drawing Figure 16-2 and Figure 16-3 show the MCF5407 case drawings. Chapter 16. Mechanical Data 16-9 Case Drawing Figure 16-2. MCF5407 Case Drawing (General View) 16-10 MCF5407 User's Manual Case Drawing View A: Three Places Section A-A: 160 Places Rotated 90 CW View B Figure 16-3. Case Drawing (Details) The dimensions in Figure 16-2 and Figure 16-3 are referenced in Table 16-5. Table 16-5. Dimensions Dimension (Millimeters) Reference Minimum Maximum A -- 4.10 A1 0.25 0.50 A2 3.20 3.60 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 30.60 BSC Chapter 16. Mechanical Data 16-11 Case Drawing Table 16-5. Dimensions (Continued) Dimension (Millimeters) Reference Minimum D1 28.00 BSC e 0.50 BSC E 30.60 BSC E1 28.00 BSC L 0.45 L1 R1 16-12 Maximum 0.75 1.30 REF 0.08 -- R2 0.08 0.25 S 0.20 -- 0* 8* 1 0* -- 2 5* 16* MCF5407 User's Manual Chapter 17 Signal Descriptions This chapter describes MCF5407 signals. It includes an alphabetical listing of signals, showing multiplexing, whether it is an input or output to the MCF5407, the state at reset, and whether a pull-up resistor should be used. The following chapter, Chapter 18, "Bus Operation," describes how these signals interact. NOTE: The terms `assertion' and `negation' are used to avoid confusion when dealing with a mixture of active-low and active-high signals. The term `asserted' indicates that a signal is active, independent of the voltage level. The term `negated' indicates that a signal is inactive. Active-low signals, such as SRAS and TA, are indicated with an overbar. 17.1 Overview Figure 17-1 shows the block diagram of the MCF5407 with the signal interface. Chapter 17. Signal Descriptions 17-1 Overview ColdFire V4 Core 2 2 Bus Interface Test Controller Debug Module PSTDDATA[7:0] 2 2-Kbyte SRAMs 32 DIV External to Internal Bus 8 2 8 4 Chip Selects 8 MAC 8-Kbyte 16-Kbyte D-Cache I-Cache Parallel Port1 Internal Bus Arbiter Interrupt Controller 1 Parallel 2 I2C port pins (PPn) are multiplexed with other bus functions as shown. is a Philips proprietary interface. Figure 17-1. MCF5407 Block Diagram with Signal Interfaces Table 17-1 lists the MCF5407 signals grouped by functionality. 17-2 MCF5407 User's Manual I2C Module 2 SDA SCL 2 2 Dual Timer Module TOUT[1:0] UART1 Serial I/O (synch) TxD0 RxD0 RTS0 CTS0 TxD1 RxD1 RTS1 CTS1 PLL UART0 Serial I/O TIN[1:0] DMA Module 2 DRAM Controller System Integration Module (SIM) 2 2 4 DREQ[1:0]/ PP[6:5] BCLKO CLKIN PSTCLK 4 TDI/DSI TRST/DSCLK A[23:0] CS[7:0] BE[3:0]/BWE[3:0] OE IRQ7 IRQ5 IRQ3 IRQ1 RAS[1:0] CAS[3:0] DRAMW SRAS SCAS SCKE EDGESEL JTAG Port TMS/BKPT 24 A[31:24]/PP[15:8] TM[2:0]/PP[4:2] MTMOD[3:0] HIZ TDO/DSO TCK DACK[1:0]/ PP[3:2] BR BG BD RSTI RSTO AS TA TS TT[1:0]]/PP[1:0] SIZ[1:0] R/W TIP/PP7 D[31:0] Overview Table 17-1. MCF5407 Signal Index Signal Name Abbreviation Function I/O Reset Pull-Up Page 17-7 Section 17.2, "MCF5407 Bus Signals" Address A[31:0] 32-bit address bus. A[4:2] indicate the interrupt level for external interrupts. I/O Three state 17-7 Data D[31:0] Data bus. D[7:0] are loaded at reset for bus configuration. I/O Three state 17-8 Read/Write R/W Identifies read and write transfers I/O Three state Size SIZ[1:0] Indicates the data transfer size I/O Three state 17-8 Transfer start TS Indicates the start of a bus transfer I/O Three state 17-9 Address strobe AS Indicates a bus cycle has been initiated and address is stable I/O Three state Up 17-9 Transfer acknowledge TA Assertion terminates transfer synchronously I/O Three state Up 17-9 Transfer in progress TIP/PP7 Indicates a bus cycle is in progress; multiplexed with PP7 O Parallel port 17-10 Transfer type TT[1:0] Indicates transfer type: normal, CPU space, emulator mode, or DMA; multiplexed with PP[1:0] O Parallel port 17-10 Transfer modifier TM[2:0] Provides transfer modifier information; multiplexed with TM2/PP4 and TM[1:0]/PP[3:2]/DACK[1:0] O Parallel port 17-10 Up 17-8 17-12 Section 17.3, "Interrupt Control Signals" Interrupt request IRQ7, IRQ5, IRQ3, IRQ1 Four external interrupts are set to default levels 1,3,5,7; user-alterable. I -- Up 17-12 17-12 Section 17.4, "Bus Arbitration Signals" Bus request BR Indicates processor needs bus O High Bus grant BG Arbiter asserts to grant mastership. I -- Bus driven BD Indicates processor is driving bus O High 17-12 Note 1 17-12 17-13 17-13 Section 17.5, "Clock and Reset Signals" Reset in RSTI Processor reset input I -- Clock input CLKIN Input used to clock internal logic I -- 17-13 Bus clock out BCLKO Bus clock reference output O -- 17-13 Reset out RSTO Processor reset output O Low 17-13 Auto-acknowledge configuration 2 AA_CONFIG Controls auto acknowledge timing for CS0 at reset I -- 17-14 Port size configuration 2 PS_CONFIG[1:0] Controls port size for CS0 at reset I -- User cfg 17-14 Chapter 17. Signal Descriptions Up 17-13 17-3 Overview Table 17-1. MCF5407 Signal Index (Continued) Signal Name Address configuration Abbreviation 2 Function I/O Reset Pull-Up Page ADDR_CONFIG Programs parallel I/O ports I -- User cfg 17-15 BE[3:0] configuration BE_CONFIG Programs byte enable pins I -- User cfg 17-15 Divide control PCLK to CLKIN 2 DIVIDE[2:0] Selects CLKIN/PCLK ratio I -- User cfg 17-15 17-15 Section 17.6, "Chip-Select Module Signals" Chip selects[7:0] CS[7:0] Enables peripherals at programmed addresses; CS0 provides boot ROM selection. O High 17-15 Byte enable[3:0]/ Byte write enable[3:0] BE[3:0]/ BWE[3:0] BE[3:0] select bytes in memory. Programmed at reset for CS0 O High 17-16 Output enable OE Output enable for chip select read cycles O High 17-16 17-16 Section 17.7, "DRAM Controller Signals" Row address strobe RAS[1:0] DRAM row address strobe O High Column address strobe CAS[3:0] DRAM column address strobe O High 17-16 DRAM write DRAMW Asserted for DRAM write; negated for DRAM read O High 17-16 Synchronous column address strobe SCAS SDRAM column address strobe O High 17-17 Synchronous row address strobe SRAS SDRAM row address strobe O High 17-17 Synchronous clock enable SCKE Clock enable for external SDRAM O Low 17-17 Synchronous edge select EDGESEL Timing select for external SDRAM I -- 17-16 User cfg 17-17 17-17 Section 17.8, "DMA Controller Module Signals" DMA request DREQ[1:0] External DMA transfer request; multiplexed with PP[6:5] I -- 17-17 DMA acknowledge DACK[1:0] Indicates DMA transfer terminated; multiplexed with TM[1:0]/PP[3:2] O Parallel port 17-18 17-18 Section 17.9, "Serial Module Signals" Receive data RxD[1:0] Receive serial data input for UART I -- 17-19 Transmit data TxD[1:0] Transmit serial data output for UART O High 17-18 Request-to-send RTS[1:0] UART asserts when ready to receive data query. O High 17-19 Clear-to-send CTS[1:0] Signals UART that data can be sent to peripheral I -- 17-19 17-19 Section 17.10, "Timer Module Signals" Timer input 17-4 TIN[1:0] Clock input to timer or trigger to timer value capture logic MCF5407 User's Manual I -- 17-19 Overview Table 17-1. MCF5407 Signal Index (Continued) Signal Name Timer outputs Abbreviation TOUT[1:0] Function Outputs waveform or pulse. I/O Reset O High Pull-Up Page 17-19 17-19 Section 17.11, "Parallel I/O Port (PP[15:0])" Parallel port PP[15:0] Interfaces with I/O; multiplexed with bus address and attribute signals. I/O Input 17-19 Section 17.12, "I2C Module Signals" I2C Serial clock line SCL Clock signal for Serial data line SDA Serial data port for I2C operation 17-20 operation I/O Open drain Up 17-20 I/O Open drain Up 17-20 17-20 Section 17.13, "Debug and Test Signals" Motorola test mode MTMOD0 Puts processor in functional or emulator mode I -- Motorola test mode MTMOD[3:1] Reserved I -- Down 17-20 High impedance HIZ Assertion three-states all outputs I -- Up 17-20 Processor clock out PSTCLK Output clock used for PSTDDATA O -- 17-21 Displays captured processor data and breakpoint status O Driven 17-21 Processor status/debug PSTDDATA[7:0] data User cfg 17-20 17-21 Section 17.14, "Debug Module/JTAG Signals" Test clock TCK Clock signal for IEEE 1149.1 JTAG I -- Low 17-22 Test reset/ Development serial clock TRST/DSCLK Asynchronous reset for JTAG; debug module clock input I -- Up 17-21 Test mode select/ Breakpoint TMS/BKPT TMS (JTAG)/hardware breakpoint (debug) I -- Up 17-21 Test data input/ Development serial input TDI/DSI Multiplexed serial input for the JTAG or background debug module I -- Up 17-22 Test data output/ Development serial output TDO/DSO Multiplexed serial output for the JTAG or background debug module O Driven 1 2 17-22 If there is no arbiter, BG should be tied low; otherwise, it should be negated. These data pins are sampled at reset for configuration. Table 17-2 lists signals in alphabetical order by abbreviated name. Table 17-2. MCF5407 Alphabetical Signal Index Abbreviation AA_CONFIG Signal Name Auto-acknowledge configuration Function Clock/reset ADDR_CONFIG Address configuration Clock/reset AS Address strobe Bus Chapter 17. Signal Descriptions I/O Page I 17-14 I 17-15 I/O 17-9 17-5 Overview Table 17-2. MCF5407 Alphabetical Signal Index (Continued) Abbreviation Signal Name Function I/O Page A[31:0] Address Bus I/O 17-7 BCLKO Bus clock out Clock/reset O 17-13 BD Bus driven Bus arbitration O 17-13 Chip select O 17-16 BE[3:0]/BWE[3:0] Byte enable[3:0]/Byte write enable[3:0] BG Bus grant Bus arbitration I 17-12 BR Bus request Bus arbitration O 17-12 CAS[3:0] Column address strobe DRAM O 17-16 CLKIN Clock input Clock/reset I 17-13 CS[7:0] Chip selects[7:0] UART O 17-15 CTS[1:0] Clear-to-send Serial module I 17-19 DACK[1:0] DMA acknowledge DMA O 17-18 DIVIDE[2:0] Divide control PCLK to CLKIN Clock/reset I 17-15 DRAMW DRAM write DRAM O 17-16 DREQ[1:0] DMA request DMA I 17-17 D[31:0] Data Bus I/O 17-8 EDGESEL Sync edge select DRAM I 17-17 HIZ High impedance Debug I 17-20 IRQ7, IRQ5, IRQ3, IRQ1 Interrupt request Interrupt control I 17-12 MTMOD[3:0] Motorola test mode Debug I 17-20 OE Output enable Chip select O 17-16 PP[15:0] Parallel port Parallel port I/O 17-19 PSTCLK Processor clock out Debug O 17-20 PSTDDATA[7:0] Processor status/debug data Debug O 17-20 Clock/reset I 17-14 PS_CONFIG[1:0] Port size configuration R/W Read/Write Bus I/O 17-8 RAS[1:0] Row address strobe DRAM O 17-16 RSTI Reset In Clock/reset I 17-13 RSTO Reset Out Clock/reset O 17-13 RTS[1:0] Request-to-send Serial module O 17-19 RxD[1:0] Receive data Serial module I 17-19 SCAS Synchronous column address strobe DRAM O 17-17 SCKE Synchronous clock enable DRAM O 17-17 SCL Serial clock line I2C I/O 17-20 SDA Serial data line I2C I/O 17-20 SIZ[1:0] Size Bus I/O 17-8 17-6 MCF5407 User's Manual MCF5407 Bus Signals Table 17-2. MCF5407 Alphabetical Signal Index (Continued) Abbreviation Signal Name Function I/O Page SRAS Synchronous row address strobe DRAM O 17-17 TA Transfer acknowledge Bus I/O 17-9 TCK Test clock JTAG I 17-22 TDI/DSI Test data input/Development serial input JTAG I 17-22 TDO/DSO Test data output/Development serial output JTAG O 17-22 TIN[1:0] Timer input Timer I 17-19 TIP Transfer in progress Bus O 17-10 TMS/BKPT Test mode select/Breakpoint JTAG I 17-21 TM[2:0] Transfer modifier Bus O 17-10 TOUT[1:0] Timer outputs Timer O 17-19 TRST/DSCLK Test reset/Development serial clock JTAG I 17-21 TS Transfer start Bus I/O 17-9 TT[1:0] Transfer type Bus O 17-10 TxD[1:0] Transmit data Serial module O 17-18 17.2 MCF5407 Bus Signals The bus signals provide the external bus interface to the MCF5407. 17.2.1 Address Bus The address bus provides the address of the byte or most-significant byte (MSB) of the word or longword being transferred. The address lines also serve as the DRAM addressing, providing multiplexed row and column address signals. When an external device has ownership of the MCF5407 bus, the device must drive the address bus and assert TS or AS to indicate the start of a bus cycle. During an interrupt acknowledge access, A[4:2] indicate the interrupt level being acknowledged. 17.2.1.1 Address Bus (A[23:0]) The lower 24 bits of the address bus become valid when TS is asserted. A[4:2] indicate the interrupt level during interrupt acknowledge cycles. 17.2.1.2 Address Bus (A[31:24]/PP[15:8]) These multiplexed pins can serve as the most-significant byte of the address bus, or as the most-significant byte of the parallel port. Programming the PAR in the system integration module (SIM) determines the function of each of these eight multiplexed pins. These pins are programmable on a bit-by-bit basis. Chapter 17. Signal Descriptions 17-7 MCF5407 Bus Signals * * A[31:24]--Pins are configured as address bits by setting corresponding PAR bits; they represent the most-significant address bus bits. As much as 4 Gbytes of memory are available when all of these pins are programmed as address signals. PP[15:8]--Pins are configured as parallel port signals by clearing corresponding PAR bits; these represent the most-significant parallel port bits. 17.2.2 Data Bus (D[31:0]) The data bus is bidirectional and non-multiplexed. Data is sampled by the MCF5407 on the rising CLKIN edge. The data bus port width, wait states, and internal termination are initially defined for the boot chip select by D[7:0] during reset. The port width for each chip select and DRAM bank are programmable. The data bus uses a default configuration if none of the chip selects or DRAM bank match the address decode. The default configuration is a 32-bit port with external termination and burst-inhibited transfers. The data bus can transfer byte, word, or longword data widths. All 32 data bus signals are driven during writes, regardless of port width and operand size. D[7:0] are used during reset initialization as inputs to configure the functions as described in Table 17-3. They are defined in Section 17.5.5, "Data/Configuration Pins (D[7:0])." Table 17-3. Data Pin Configuration Pin D7 Function Section Auto-acknowledge configuration (AA_CONFIG) Section 17.5.5.2, "D7--Auto Acknowledge Configuration (AA_CONFIG)" D[6:5] Port size configuration (PS_CONFIG[1:0]) Section 17.5.5.3, "D[6:5]--Port Size Configuration (PS_CONFIG[1:0])" D4 Address configuration (ADDR_CONFIG/D4) Section 17.5.6, "D4--Address Configuration (ADDR_CONFIG)" D3 Byte enable configuration (BE_CONFIG) D[2:0] Divide control (DIVIDE[2:0]) Section 17.5.5.4, "D3--Byte-Enable Configuration (BE_CONFIG)" Section 17.5.6.1, "D[2:0]--Divide Control (DIVIDE[2:0])" 17.2.3 Read/Write (R/W) When the MCF5407 is the bus master, it drives the R/W signal to indicate the direction of subsequent data transfers. It is driven high during read bus cycles and driven low during write bus cycles. This signal is an input during an external master access. 17.2.4 Size (SIZ[1:0]) When it is the bus master, the MCF5407 outputs these signals to indicate the requested data transfer size. Table 17-4 shows the definition of the bus request size encodings. When the MCF5407 device is not the bus master, these signals function as inputs. Note that for misaligned transfers, SIZ[1:0] indicate the size of each transfer. For example, 17-8 MCF5407 User's Manual MCF5407 Bus Signals if a longword access occurs at a misaligned offset of 0x1, a byte is transferred first (SIZ[1:0] = 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is transferred at offset 0x4 (SIZ[1:0] = 01). For aligned transfers larger than the port size, SIZ[1:0] behaves as follows: * * If bursting is used, SIZ[1:0] stays at the size of transfer. If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows the port size. Table 17-4. Bus Cycle Size Encoding SIZ[1:0] Port Size 00 Longword 01 Byte 10 Word 11 Line For burst-inhibited transfers, SIZ[1:0] changes with each TS assertion to reflect the next transfer size. For transfers to port sizes smaller than the transfer size, SIZ[1:0] indicates the size of the entire transfer on the first access and the size of the current port transfer on subsequent transfers. For example, for a longword write to an 8-bit port, SIZ[1:0] = 00 for the first byte transfer and 01 for the next three. 17.2.5 Transfer Start (TS) The MCF5407 asserts TS during the first clock cycle when address and attributes (TM, TT, TIP, R/W, and SIZ) are valid. TS is negated in the following clock cycle. When the MCF5407 is not the bus master, TS is an input. 17.2.6 Address Strobe (AS) Address strobe (AS) is asserted to indicate when the address is stable at the start of a bus cycle. The address and attributes are guaranteed to be valid during the entire period that AS is asserted. This signal is asserted and negated on the falling edge of the clock. When the MCF5407 is not the bus master, AS is an input. 17.2.7 Transfer Acknowledge (TA) When the MCF5407 is bus master, the external system drives this input to terminate the bus transfer. The bus continues to be driven until this synchronous signal is asserted. For write cycles, the processor continues to drive data one clock after TA is asserted. During read cycles, the peripheral must continue to drive data until TA is recognized. If all bus cycles support fast termination, TA can be tied low. However, note that TA cannot be tied low if potential external bus masters are present. The MCF5407 drives TA for an Chapter 17. Signal Descriptions 17-9 MCF5407 Bus Signals external master access. This condition is indicated by the AM bit in the chip-select mask register (CSMR) being cleared. See Chapter 10, "Chip-Select Module." 17.2.8 Transfer In Progress (TIP/PP7) The TIP/PP7 pin is programmed in the PAR to serve as the transfer-in-progress output or as a parallel port bits. The TIP output is asserted indicating a bus transfer is in progress. It is negated during idle bus cycles if the bus is still granted to the processor. It is three-stated for external master accesses. Note that TIP is held asserted on back-to-back bus cycles. 17.2.9 Transfer Type (TT[1:0]/PP[1:0]) The TT[1:0]/PP[1:0] pins are programmed in the PAR to serve as the transfer type outputs or as two parallel port bits. When the MCF5407 is bus master and TT[1:0] are enabled, these signals are driven as outputs only. If an external master owns the bus and TT[1:0] are enabled, these pins are three-stated by the MCF5407 and can be driven by the external master. Table 17-5 shows the definition of the encodings. Table 17-5. Bus Cycle Transfer Type Encoding TT[1:0] Transfer Type 00 Normal access 01 DMA access 10 Emulator access 11 CPU space or interrupt acknowledge 17.2.10 Transfer Modifier (TM[2:0]/PP[4:2]/DACK[1:0]) The TM[2:0]/PP[4:2] pins are programmed in the PAR to serve as the transfer modifier outputs or as three parallel port bits. These outputs provide supplemental information for each transfer type; see Table 17-6 through Table 17-10. When the MCF5407 is the bus master and TM[2:0] are enabled, these signals are driven as outputs only. If an external device is bus master and TM[2:0] are enabled, these pins are three-stated by the MCF5407 and can be driven by the external master. Table 17-6. TM[2:0] Encodings for TT = 00 (Normal Access) TM[2:0] 000 Cache push access 001 User data access 010 User code access 011-100 101 17-10 Transfer Modifier Reserved Supervisor data access MCF5407 User's Manual MCF5407 Bus Signals Table 17-6. TM[2:0] Encodings for TT = 00 (Normal Access) (Continued) TM[2:0] Transfer Modifier 110 Supervisor code access 111 Reserved As shown in Table 17-7, if the DMA is bus master (TT = 01), TM[2:0] indicate the type of DMA access and provide the DMA acknowledgement information for channels 0 and 1. In addition, TM[1:0] are multiplexed with DMA acknowledge signals for channels 0 and 1. NOTE: When TT= 01, the TM2 encoding is independent from TM[1:0] encoding. Table 17-7. TM2 Encoding for DMA as Master (TT = 01) TM2 Transfer Modifier Encoding 0 Single-address access negated 1 Single-address access Table 17-8. TM[1:0] Encoding for DMA as Master (TT = 01) TM[1:0] Transfer Modifier Encoding 00 DMA acknowledges negated 01 DMA acknowledge, channel 0 10 DMA acknowledge, channel 1 11 Reserved Table 17-9 shows TM[2:0] encodings for emulator mode accesses. Table 17-9. TM[2:0] Encodings for TT = 10 (Emulator Access) TM[2:0] 000-100 Transfer Modifier Reserved 101 Emulator mode data access 110 Emulator mode code access 111 Reserved The TM signals indicate user or data transfer types during emulation transfers, while for interrupt acknowledge transfers, the TM signals carry the interrupt level being acknowledged; see Table 17-10. Chapter 17. Signal Descriptions 17-11 Interrupt Control Signals Table 17-10. TM[2:0] Encodings for TT = 11 (Interrupt Level) TM[2:0] Transfer Modifier 000 CPU Space 001 Interrupt level 1 acknowledge 010 Interrupt level 2 acknowledge 011 Interrupt level 3 acknowledge 100 Interrupt level 4 acknowledge 101 Interrupt level 5 acknowledge 110 Interrupt level 6 acknowledge 111 Interrupt level 7 acknowledge 17.3 Interrupt Control Signals The interrupt control signals supply the external interrupt level to the MCF5407 device. 17.3.1 Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, and IRQ7) The IRQ1, IRQ3, IRQ5, and IRQ7 signals are the default interrupt request signals (IRQn). However, by setting the appropriate bit in the interrupt port assignment register (IRQPAR), IRQ1, IRQ3, and IRQ5 can be changed to function as IRQ2, IRQ6, and IRQ4, respectively. See Section 9.2.4, "Interrupt Port Assignment Register (IRQPAR)." 17.4 Bus Arbitration Signals The bus arbitration signals provide the external bus arbitration control for the MCF5407. 17.4.1 Bus Request (BR) The BR output indicates to an external arbiter that the processor is requesting to be bus master for one or more bus cycles. BR is negated when the MCF5407 begins an access to the external bus with no other internal accesses pending. BR remains negated until another internal request occurs. 17.4.2 Bus Grant (BG) An external arbiter asserts the BG input to indicate that the MCF5407 can take control of the bus on the next rising edge of CLKIN. When the arbiter negates BG, the MCF5407 will release the bus as soon as the current transfer completes. The external arbiter must not grant the bus to any other master until both BD and BG are negated. 17-12 MCF5407 User's Manual Clock and Reset Signals 17.4.3 Bus Driven (BD) The MCF5407 asserts BD to indicate that it is the current master and is driving the bus. The MCF5407 behaves as follows: * * * * If the MCF5407 is the bus master but is not using the bus, BD is asserted. If the MCF5407 loses mastership during a transfer, it completes the last transfer of the access, negates BD, and three-states all bus signals on the rising edge of CLKIN. If the MCF5407 loses bus mastership during an idle clock cycle, it three-states all bus signals on the rising edge of CLKIN. BD cannot be negated unless BG is negated. 17.5 Clock and Reset Signals The clock and reset signals configure the MCF5407 and provide interface signals to the external system. 17.5.1 Reset In (RSTI) Asserting RSTI causes the MCF5407 to enter reset exception processing. When RSTI is recognized, BR and BD are negated and the address bus, data bus, TT, SIZ, R/W, AS, and TS are three-stated. RSTO is asserted automatically when RSTI is asserted. 17.5.2 Clock Input (CLKIN) CLKIN is the MCF5407 input clock frequency to the on-board phase-locked-loop (PLL) clock generator. CLKIN is used to internally clock or sequence the MCF5407 internal bus interface at a selected multiple of the input frequency used for internal module logic. CLKIN should be used as the bus timing reference. 17.5.3 Bus Clock Output (BCLKO) The internal PLL generates BCLKO. It has the same frequency as CLKIN, which is used as the bus timing reference by the external devices. BCLKO is provided for compatibility with earlier devices. 17.5.4 Reset Out (RSTO) After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the PLL regains its lock, RSTO negates again. This signal can be used to reset external devices. Chapter 17. Signal Descriptions 17-13 Clock and Reset Signals 17.5.5 Data/Configuration Pins (D[7:0]) This section describes data pins, D[7:0], that are read at reset for configuration. Table 17-11 shows pin assignments. Table 17-11. Data Pin Configuration Pin Function D7 Auto-acknowledge configuration (AA_CONFIG) D[6:5] Port size configuration (PS_CONFIG[1:0]) D4 Address configuration (ADDR_CONFIG/D4) D3 Byte enable configuration (BE_CONFIG) D[2:0] Divide control (DIVIDE[2:0]) 17.5.5.1 D[7:5,3]--Boot Chip-Select (CS0) Configuration D[7:5,3] determine defaults for the global chip select (CS0), the only chip select valid at reset. These signals correspond to bits in chip-select configuration register 0 (CSCR0). 17.5.5.2 D7--Auto Acknowledge Configuration (AA_CONFIG) At reset, the enabling and disabling of auto acknowledge for boot CS0 is determined by the logic level driven on D7 at the rising edge of RSTI. AA_CONFIG is multiplexed with D7 and sampled only at reset. The D7 logic level is reflected as the reset value of CSCR[AA]. Table 17-12 shows how the D7 logic level corresponds to the auto acknowledge timing for CS0 at reset. Note that auto acknowledge can be disabled by driving a logic 0 on D7 at reset. Table 17-12. D7 Selection of CS0 Automatic Acknowledge D7 (CSCR0[AA]) Boot CS0 AA 0 Disabled 1 Enabled with 15 wait states 17.5.5.3 D[6:5]--Port Size Configuration (PS_CONFIG[1:0]) The default port size value of the boot CS0 is determined by the logic levels driven on D[6:5] at the rising edge of RSTI, which are reflected as the reset value of CSCR[PS]. Table 17-13 shows how the logic levels of D[6:5] correspond to the CS0 port size at reset. Table 17-13. D6 and D5 Selection of CS0 Port Size 17-14 D[6:5] (CSCR0[PS]) Boot CS0 Port Size 00 32-bit port 01 8-bit port 1x 16-bit port MCF5407 User's Manual Chip-Select Module Signals 17.5.5.4 D3--Byte-Enable Configuration (BE_CONFIG) The default byte-enable mode of the boot CS0 is determined by the logic level driven on D3 at the rising edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM]. Table 17-13 shows how the logic levels of D[6:5] correspond to the port size for CS0 at reset. Table 17-14. D3/BE_CONFIG, BE[3:0] Boot Configuration D3 (CSCR0[BEM]) Boot CS0 Byte Enable Configuration 0 Neither BE nor BWE is asserted for read. BWE is generated for data write only. 1 BE is asserted for read; BWE is asserted for write. 17.5.6 D4--Address Configuration (ADDR_CONFIG) The address configuration signal (ADDR_CONFIG) programs the PAR of the parallel I/O port to be either parallel I/O or to be the upper address bus bits along with various attribute and control signals at reset to give the user the option to access a broader addressing range of memory if desired. ADDR_CONFIG is multiplexed with D4 and its configuration is sampled at reset as shown in Table 17-15. Table 17-15. D4/ADDR_CONFIG, Address Pin Assignment D4/ADDR_CONFIG PAR Configuration at Reset 0 PP[15:0], defaulted to inputs upon reset 1 A[31:24]/TIP/DREQ[1:0]/TM[2:0]/TT[1:0] 17.5.6.1 D[2:0]--Divide Control (DIVIDE[2:0]) The divide control input bus, DIVIDE[2:0], indicates the CLKIN/PCLK ratio. These signals are sampled on the rising edge of RSTI to indicate the ratios described in Chapter 20, "Electrical Specifications." 17.6 Chip-Select Module Signals The MCF5407 device provides eight programmable chip-select signals that can directly interface with SRAM, EPROM, EEPROM, and peripherals. These signals are asserted and negated on the falling edge of the clock. 17.6.1 Chip-Select (CS[7:0]) Each chip select can be programmed for a base address location and for masking addresses, port size and burst-capability indication, wait-state generation, and internal/external termination. Reset clears all chip select programming; CS0 is the only chip select initialized out of reset. CS0 is also unique because it can function at reset as a global chip select that allows boot Chapter 17. Signal Descriptions 17-15 DRAM Controller Signals ROM to be selected at any defined address space. Port size and termination (internal vs. external) for boot CS0 are configured by the levels on D[7:5,3] on the rising edge of RSTI, as described in Section 17.5.5.1, "D[7:5,3]--Boot Chip-Select (CS0) Configuration." The chip-select implementation is described in Chapter 10, "Chip-Select Module." 17.6.2 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) The four byte enables are multiplexed with the MCF5407 byte-write-enable signals. Each pin can be individually programmed through the chip-select control registers (CSCRs). For each chip select, assertion of byte enables for reads and byte-write enables for write cycles can be programmed. Alternatively, users can program byte-write enables to assert on writes and no byte enable assertion for read transfers. 17.6.3 Output Enable (OE) The output enable (OE) signal is sent to the interfacing memory and/or peripheral to enable a read transfer. OE is asserted only when a chip select matches the current address decode. 17.7 DRAM Controller Signals The DRAM signals in the following sections interface to external DRAM. DRAM with widths of 8, 16, and 32 bits are supported and can access as much as 512 Mbytes of DRAM. 17.7.1 Row Address Strobes (RAS[1:0]) The row address strobes (RAS[1:0]) interface to RAS inputs on industry-standard ADRAMs. When SDRAMs are used, these signals interface to the chip-select lines of the SDRAMs within a memory block. Thus, there is one RAS line for each memory block (because the MCF5407 supports only two memory blocks). 17.7.2 Column Address Strobes (CAS[3:0]) The column address strobes (CAS[3:0]) interface to CAS inputs on industry-standard DRAMs. These provide CAS for a given ADRAM block. When SDRAMs are used, CAS signals control the byte enables for standard SDRAMs (referred to as DQMx). CAS3 accesses the LSB and CAS0 accesses the MSB of data. 17.7.3 DRAM Write (DRAMW) The DRAM write signal (DRAMW) is asserted to signify that a DRAM write cycle is underway. A read bus cycle is indicated by the negation of DRAMW. 17-16 MCF5407 User's Manual DMA Controller Module Signals 17.7.4 Synchronous DRAM Column Address Strobe (SCAS) The synchronous DRAM column address strobe (SCAS) is registered during synchronous mode to route directly to the SCAS signal of SDRAMs. 17.7.5 Synchronous DRAM Row Address Strobe (SRAS) The synchronous DRAM row address strobe output (SRAS) is registered during synchronous mode to route directly to the SRAS signal of external SDRAMs. 17.7.6 Synchronous DRAM Clock Enable (SCKE) The synchronous DRAM clock enable output (SCKE) is registered during synchronous mode to route directly to the SCKE signal of external SDRAMs. This signal provides the clock enable to the SDRAM. 17.7.7 Synchronous Edge Select (EDGESEL) The synchronous edge select input (EDGESEL) helps select additional output hold times for signals that interface to external SDRAMs. It provides the following three modes of operation for SDRAM control signals: * * * When EDGESEL is tied high, SDRAM control signals change on the rising edge of CLKIN. When EDGESEL is tied low, SDRAM control signals change on the falling edge of CLKIN. When EDGESEL is tied to the external clock (normally buffered CLKIN), which drives the SDRAM and other devices, SDRAM signals are generated within the MCF5407 make a transition on the rising edge of the SDRAM clock. See Figure 11-14 on page 11-19. This loop-back configuration provides additional output hold time for MCF5407 interface signals provided to the SDRAM. In this case, the SDRAM clock operates at the CLKIN frequency, with a possible slight phase delay. 17.8 DMA Controller Module Signals The DMA controller module uses the signals in the following subsections to provide external request for either a source or destination. 17.8.1 DMA Request (DREQ[1:0]/PP[6:5]) The DMA request pins (DREQ[1:0]/PP[6:5]) can serve as the DMA request inputs or as two bits of the parallel port, as determined by individually programmable bits in the PAR. These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and memory by either channel 0 or 1 of the on-chip DMA. Chapter 17. Signal Descriptions 17-17 Serial Module Signals 17.8.2 Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) Although the MCF5407 provides similar encodings on TM[2:0], DMA acknowledgement pins (DACK[1:0]) are now combined with PP[3:2]/TM[1:0], resulting in three-to-one multiplexed signals, PP[3:2]/TM[1:0]/DACK[1:0]. TM2 is still multiplexed only with PP4. When properly connected, TM[2:0] can be used in MCF5407 designs as on MCF5307 designs, or DACK[1:0] can be used for DMA transfers, as shown in Figure 17-2. MCF5307 Function Pin Pin MCF5407 Function Single/dual cycle access TM0 TM0 DMA 0 acknowledge DMA 0 acknowledge configuration TM1 TM1 DMA 1 acknowledge DMA 1 acknowledge configuration TM2 TM2 Single/dual cycle access Figure 17-2. MCF5307 to MCF5407 TM[2:0] Pin Remapping To enable DACK[1:0], first enable TM[1:0] through the PAR and then program the interrupt assignment register (IRQPAR) in the MCF5407 SIM module to enable bits 0-1. When IRQPAR[ENBDACK1] = 1 and PAR is programmed to enable TM1, DACK1 for DMA channel 1 is driven in place of TM1 for DMA transfers. Clearing ENBDACK1 disables this function and only the TM1 encoding is driven. Likewise, setting ENBDACK0 enables DACK0 to be driven; clearing ENBDACK0 disables this function and drives the TM0 encoding. Although the MCF5407 TM[2:0] signals can drive DMA access encoding, the bit positions of these encodings differ from the MCF5307. Single-address access indication is now encoded on TM2 when the PAR is set to enable the transfer modifier signal and an external master or DMA transfer is occurring. This encoding is driven by TM0 on the MCF5307. In addition, DMA acknowledge encodings are driven on TM[1:0] on the MCF5407, as opposed to TM[2:1] on the MCF5307. 17.9 Serial Module Signals The signals in the following sections are used to transfer serial data between the two UART modules and external peripherals. 17.9.1 Transmitter Serial Data Output (TxD) In UART mode, TxD is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loop-back mode. Data is shifted out least-significant bit (lsb) first on TxD on the falling edge of the clock source. For UART1 in modem mode, TxD is held low when the transmitter is disabled or idle. Data is shifted out on TxD on the rising edge of the clock signal driving UART1's CTS input. UART1 transfers can be specified as either lsb or msb first. 17-18 MCF5407 User's Manual Timer Module Signals 17.9.2 Receiver Serial Data Input (RxD) Data received on RxD is sampled on the rising edge of the clock source, with the lsb received first. For UART1 in modem mode, data received on RxD is sampled on the falling edge of the clock signal driving UART1's CTS input. UART1 transfers can be specified as either lsb or msb first. 17.9.3 Clear to Send (CTS) This input can generate an interrupt on a change of state. For UART1 in modem mode, CTS must be driven by the serial bit clock from the external CODEC or AC97 controller. 17.9.4 Request to Send (RTS) This output can be programmed to be negated or asserted automatically by either the receiver or the transmitter. When connected to a transmitter's CTS, RTS can control serial data flow. For UART1 in AC97 mode, RTS serves as the frame sync or start of frame (SOF), output to the external AC97 controller. When this mode is used, the AC97 BIT_CLK, which is input on CTS, is divided by 256. 17.10 Timer Module Signals The signals in the following sections are external interfaces to the two general-purpose MCF5407 timers. These 16-bit timers can capture timer values, trigger external events or internal interrupts, or count external events. 17.10.1 Timer Inputs (TIN[1:0]) TIN[1:0] can be programmed as clocks that cause events in the counter and prescalers. They can also cause captures on the rising edge, falling edge, or both edges. 17.10.2 Timer Outputs (TOUT1, TOUT0) The programmable timer outputs (TOUT1 and TOUT0) pulse or toggle on various timer events. 17.11 Parallel I/O Port (PP[15:0]) This 16-bit bus is dedicated for general-purpose I/O. The parallel port is multiplexed with the A[31:24], TT[1:0], TM[2:0], TIP, and DREQ[1:0]. These 16 bits are programmed for functionality with the PAR in the SIM. The system designer controls the reset value of this register by driving D4 with a 1 or 0 on the rising edge of RSTI (reset input to MCF5407 device). At reset, the system is configured as PP[15:0] if D4 is 0; otherwise alternate pin functions selected by PAR = 1 are used. Chapter 17. Signal Descriptions 17-19 I2C Module Signals Motorola recommends that D4 be driven during reset to a logic level. 17.12 I2C Module Signals The I2C module acts as a two-wire, bidirectional serial interface between the MCF5407 and peripherals with an I2C interface (such as LED controller, A-to-D converter, or D-to-A converter). Devices connected to the I2C must have open-drain or open-collector outputs. 17.12.1 I2C Serial Clock (SCL) The bidirectional, open-drain I2C serial clock signal (SCL) is the clock signal for I2C module operation. The I2C module controls this signal when the bus is in master mode; all I2C devices drive this signal to synchronize I2C timing. 17.12.2 I2C Serial Data (SDA) The bidirectional, open-drain I2C serial data signal (SDA) is the data input/output for the serial I2C interface. 17.13 Debug and Test Signals The signals in this section interface with external I/O to provide processor status signals. 17.13.1 Test Mode (MTMOD[3:0]) The test mode signals choose between multiplexed debug module and JTAG signals. If MTMOD0 is low, the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode. All other MTMOD values are reserved; MTMOD[3:1] should be tied to ground and MTMOD[3:0] should not be changed while RSTI is negated. 17.13.2 High Impedance (HIZ) The assertion of HIZ forces all output drivers to high-impedance state. The timing on HIZ is independent of the clock. Note that HIZ does not override the JTAG operation; TDO/DSO can be forced to high impedance by asserting TRST. 17.13.3 Processor Clock Output (PSTCLK) The internal PLL generates this output signal, and is the processor clock output that is used as the timing reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the same frequency as the core processor and cache memory. 17-20 MCF5407 User's Manual Debug Module/JTAG Signals 17.13.4 Processor Status Debug Data (PSTDDATA[7:0]) Processor status data outputs indicate both processor status and captured address and data values. They operate at half the processor's frequency, using PSTCLK. Given that real-time trace information appears as a sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant. See Chapter 5, "Debug Support." 17.14 Debug Module/JTAG Signals The MCF5407 complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are multiplexed with background debug pins. Except for TCK, these signals are selected by the value of MTMOD0. If MTMOD0 is high, JTAG signals are chosen; if it is low, debug module signals are chosen. MTMOD0 should be changed only while RSTI is asserted. 17.14.1 Test Reset/Development Serial Clock (TRST/DSCLK) If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG controller to the test logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this occurs, JTAG logic is benign and does not interfere with normal MCF5407 functionality. Although TRST is asynchronous, Motorola recommends that it makes an asserted-to-negated transition only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to a logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to VDD. Tying TRST to ground places the JTAG controller in test logic reset state immediately. Tying it to VDD causes the JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks. If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to the debug module. The maximum DSCLK frequency is 1/5 CLKIN. See Chapter 5, "Debug Support." 17.14.2 Test Mode Select/Breakpoint (TMS/BKPT) If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current state or advances to the next state. This directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up resistor so that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be tied to VDD. If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the Chapter 17. Signal Descriptions 17-21 Debug Module/JTAG Signals processor in debug mode. See Chapter 5, "Debug Support." 17.14.3 Test Data Input/Development Serial Input (TDI/DSI) If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG controller state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge. TDI has an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it should be tied to VDD. If MTMOD0 is low, DSI is selected. DSI provides the single-bit communication for debug module commands. See Chapter 5, "Debug Support." 17.14.4 Test Data Output/Development Serial Output (TDO/DSO) If MTMOD0 is high, TDO is selected. The TDO output provides the serial data port for outputting data from JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in the instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test data, it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices having JTAG. If MTMOD0 is low, DSO is selected. DSO provides single-bit communication for debug module responses. See Chapter 5, "Debug Support." 17.14.5 Test Clock (TCK) TCK is the dedicated JTAG test logic clock independent of the MCF5407 processor clock. Various JTAG operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground. 17-22 MCF5407 User's Manual Chapter 18 Bus Operation This chapter describes data-transfer operations, error conditions, bus arbitration, and reset operations. It describes transfers initiated by the MCF5407 and by an external bus master, and includes detailed timing diagrams showing the interaction of signals in supported bus operations. Chapter 11, "Synchronous/Asynchronous DRAM Controller Module," describes DRAM cycles. 18.1 Features The following list summarizes bus operation features: * * * * * * * Up to 32 bits of address and data 8-, 16-, and 32-bit port sizes Byte, word, longword, and line size transfers Bus arbitration for external devices Burst and burst-inhibited transfer support Internal termination for core and DMA bus cycles External termination of bus cycles controlled by an external bus master Note that, throughout this manual, an overbar indicates an active-low signal. 18.2 Bus and Control Signals Table 18-1 summarizes MCF5407 bus signals described in Chapter 17, "Signal Descriptions." Table 18-1. ColdFire Bus Signal Summary Signal Name AS A[31:0] BE/BWE 1 CS[7:0] 1 D[31:0] Description MCF5407 Master External Master Edge Address strobe O I Falling Address bus O I Rising Byte enable/Byte write enable O O Falling Chip selects O O Falling Data bus I/O I/O Rising Chapter 18. Bus Operation 18-1 Bus Characteristics Table 18-1. ColdFire Bus Signal Summary (Continued) Signal Name IRQ[7,5,3,1] MCF5407 Master External Master Edge Interrupt request I I Rising OE 1 Output enable O I Falling R/W Read/write O I Rising Transfer size O I Rising TA Transfer acknowledge I O Rising TIP Transfer in progress O Three-state Rising Transfer modifier O Three-state Rising TS Transfer start O I Rising TT[1:0] Transfer type O Three-state Rising SIZ[1:0] TM[2:0] 1 Description These signals change after the falling edge. In Chapter 20, "Electrical Specifications," these signals are specified off the rising edge because CLKIN is squared up internally. 18.3 Bus Characteristics The MCF5407 uses an input clock signal (CLKIN) to generate its internal clock and outputs BCLKO, which is provided for backwards compatibility for MCF5307 designs. CLKIN is the bus clock rate, where all bus operations are synchronous to the rising edge of CLKIN. Some of the bus control signals (BE/BWE, OE, CSx, and AS) are synchronous to the falling edge, shown in Figure 18-1. Bus characteristics may differ somewhat for interfacing with external DRAM. CLKIN tvo tho Rising-Edge Signals tvo tho Falling-Edge Signals tsi thi Inputs tvo=Propagation delay of signal relative to CLKIN edge tho=Output hold time relative to CLKIN edge tsi =Required input setup time relative to CLKIN edge thi=Required input hold time relative to CLKIN edge Figure 18-1. Signal Relationship to CLKIN for Non-DRAM Access 18.4 Data Transfer Operation Data transfers between the MCF5407 and other devices involve the following signals: 18-2 MCF5407 User's Manual Data Transfer Operation * * * * * Address bus (A[31:0]) Data bus (D[31:0]) Control signals (TS and TA) AS, CSx, OE, BE/BWE Attribute signals (R/W, SIZ, TT, TM, and TIP) The address bus, write data, TS, and all attribute signals change on the rising edge of CLKIN. Read data is latched into the MCF5407 on the rising edge of CLKIN. AS, CSx, OE, and BE/BWE change on the falling edge. The MCF5407 bus supports byte, word, and longword operand transfers and allows accesses to 8-, 16-, and 32-bit data ports. Transfer parameters such as port size, the number of wait states for the external slave being accessed, and whether internal transfer termination is enabled, can be programmed in the chip-select control registers (CSCRs) and DRAM control registers (DACRs). For aligned transfers larger than the port size, SIZ[1:0] behaves as follows: * * If bursting is used, SIZ[1:0] stays at the size of transfer. If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows the port size. Table 18-2 shows encoding for SIZ[1:0]. Table 18-2. Bus Cycle Size Encoding SIZ[1:0] Port Size 00 Longword 01 Byte 10 Word 11 Line Figure 18-2 shows the byte lanes that external memory should be connected to and the sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit memory should be connected to D[31:24] (BE0). A longword transfer takes four transfers on D[31:24], starting with the MSB and going to the LSB. Chapter 18. Bus Operation 18-3 Data Transfer Operation BE1 BE2 BE3 D[31:24] D[23:16] D[15:8] D[7:0] 32-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 16-Bit Port Memory Byte 0 Byte 1 Byte 2 Byte 3 Byte Enable Processor External Data Bus 8-Bit Port Memory BE0 Driven with indeterminate values Byte 0 Byte 1 Byte 2 Driven with indeterminate values Byte 3 Figure 18-2. Connections for External Memory Port Sizes The timing relationships between CLKIN and chip select (CS[7:0]), byte enable/byte write enables (BE/BWE[3:0]), and output enable (OE) are similar to their relationships with address strobe (AS) in that all transitions occur during the low phase of CLKIN. However, as shown in Figure 18-3, differences in on-chip signal routing and external loading may prevent signals from asserting simultaneously. CLKIN CS[7:0] BE/BWE[3:0] AS, OE Figure 18-3. Chip-Select Module Output Timing Diagram 18.4.1 Bus Cycle Execution When a bus cycle is initiated, the MCF5407 first compares its address with the base address and mask configurations programmed for chip selects 0-7 (CSCR0-CSCR7) and for DRAM blocks 0 and 1 address and control registers (DACR0 and DACR1). If the driven address matches a programmed chip select or DRAM block, the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed in the respective configuration register. Otherwise, the following occurs: * * * 18-4 If the address and attributes do not match in CSCR or DACR, the MCF5407 runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. If an address and attribute match in multiple CSCRs, the matching chip-select signals are driven; however, the MCF5407 runs an external burst-inhibited bus cycle with external termination on a 32-bit port. If an address and attribute match both DACRs or a DACR and a CSCR, the operation is undefined. MCF5407 User's Manual Data Transfer Operation Table 18-3 shows the type of access as a function of match in the CSCRs and DACRs. Table 18-3. Accesses by Matches in CSCRs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External Defined by CSCRs 1 0 Multiple 0 External, burst-inhibited, 32-bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined Basic bus operations occur in three clocks, as follows: 1. During the first clock, the address, attributes, and TS are driven. AS is asserted at the falling edge of the clock to indicate that address and attributes are valid and stable. 2. Data and TA are sampled during the second clock of a bus-read cycle. During a read, the external device provides data and is sampled at the rising edge at the end of the second bus clock. This data is concurrent with TA, which is also sampled at the rising clock edge. During a write, the MCF5407 drives data from the rising clock edge at the end of the first clock to the rising clock edge at the end of the bus cycle. Wait states can be added between the first and second clocks by delaying the assertion of TA. TA can be configured to be generated internally through the DACRs and CSCRs. If TA is not generated internally, the system must provide it externally. 3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data. Figure 18-6 and Figure 18-8 show the basic read and write operations. 18.4.2 Data Transfer Cycle States The data transfer operation in the MCF5407 is controlled by an on-chip state machine. Each bus clock cycle is divided into two states. Even states occur when CLKIN is high and odd states occur when CLKIN is low. The state transition diagram for basic and fast-termination read and write cycles is shown in Figure 18-4. Chapter 18. Bus Operation 18-5 Data Transfer Operation Next Cycle S0 S5 S1 Basic Read/Write Fast Termination S4 S2 Wait States S3 Figure 18-4. Data Transfer State Transition Diagram Table 18-4 describes the states as they appear in subsequent timing diagrams. Note that the TT[1:0], TM[2:0], and TIP functions are chosen in the PAR, as described in Section 15.1.1, "Pin Assignment Register (PAR)." Table 18-4. Bus Cycle States State Cycle CLKIN Description S0 All High The read or write cycle is initiated. On the rising edge of CLKIN, the MCF5407 places a valid address on the address bus, asserts TIP, and drives R/W high for a read and low for a write, if these signals are not already in the appropriate state. The MCF5407 asserts TT[1:0], TM[2:0], SIZ[1:0], and TS on the rising edge of CLKIN. S1 All Low AS asserts on the falling edge of CLKIN, indicating that the address and attributes are stable. The appropriate CSx, BE/BWE, and OE signals assert on the CLKIN falling edge. Fast termination S2 Read/write (skipped for fast termination) TA must be asserted during S1. Data is made available by the external device and is sampled on the rising edge of CLKIN with TA asserted. High Write S3 Read/write (skipped for fast termination) The data bus is driven out of high impedance as data is placed on the bus on the rising edge of CLKIN. Low Read S4 All Read (including fast termination) 18-6 TS is negated on the rising edge of CLKIN. The MCF5407 waits for TA assertion. If TA is not sampled as asserted before the rising edge of CLKIN at the end of the first clock cycle, the MCF5407 inserts wait states (full clock cycles) until TA is sampled as asserted. Data is made available by the external device on the falling edge of CLKIN and is sampled on the rising edge of CLKIN with TA asserted. High The external device should negate TA. The external device can stop driving data after the rising edge of CLKIN. However, data could be driven up to S5. MCF5407 User's Manual Data Transfer Operation Table 18-4. Bus Cycle States (Continued) State S5 Cycle CLKIN S5 Low Description AS, CS, BE/BWE, and OE are negated on the CLKIN falling edge. The MCF5407 stops driving address lines and R/W on the rising edge of CLKIN, terminating the read or write cycle. At the same time, the MCF5407 negates TT[1:0], TM[2:0], TIP, and SIZ[1:0] on the rising edge of CLKIN. Note that the rising edge of CLKIN may be the start of S0 for the next access cycle; in this case, TIP remains asserted and R/W may not transition, depending on the nature of the back-to-back cycles. Read The external device stops driving data between S4 and S5. Write The data bus returns to high impedance on the rising edge of CLKIN. The rising edge of CLKIN may be the start of S0 for the next access. NOTE: An external device has at most two CLKIN cycles after the start of S4 to three-state the data bus after data is sampled in S3. This applies to basic read cycles, fast-termination cycles, and the last transfer of a burst. 18.4.3 Read Cycle During a read cycle, the MCF5407 receives data from memory or from a peripheral device. Figure 18-5 is a read cycle flowchart. System MCF5407 1. Set R/W to read 2. Place address on A[31:0] 3. Assert TT[1:0], TM[2:0], TIP, and SIZ[1:0] 4. Assert TS 5. Assert AS 6. Negate TS 1. 1. 1. Decode address and select the appropriate slave device. 2. Drive data on D[31:0] 3. Assert TA 1. Negate TA. 2. Stop driving D[31:0] Sample TA low and latch data Start next cycle Figure 18-5. Read Cycle Flowchart The read cycle timing diagram is shown in Figure 18-6. NOTE: In the following timing diagrams, TA waveforms apply for chip selects programmed to enable either internal or external Chapter 18. Bus Operation 18-7 Data Transfer Operation termination. TA assertion should look the same in either case. S0 S1 S2 S3 S4 S5 CLKIN R/W TT[1:0], TM[2:0] SIZ[1:0], A[31:0] TIP TS AS, CSx BEx, OE Read D[31:0] TA Figure 18-6. Basic Read Bus Cycle Note the following characteristics of a basic read: * * * In S3, data is made available by the external device on the falling edge of CLKIN and is sampled on the rising edge of CLKIN with TA asserted. In S4, the external device can stop driving data after the rising edge of CLKIN. However, data could be driven up to S5. For a read cycle, the external device stops driving data between S4 and S5. States are described in Table 18-4. 18.4.4 Write Cycle During a write cycle, the MCF5407 sends data to memory or to a peripheral device. The write cycle flowchart is shown in Figure 18-7. 18-8 MCF5407 User's Manual Data Transfer Operation System MCF5407 1. Set R/W to write 2. Place address on A[31:0] 3. Assert TT[1:0], TM[2:0], TIP, and SIZ[1:0] 4. Assert TS 5. Assert AS 6. Place data on D[31:0] 7. Negate TS 1. Sample TA low 1. Tree-state D[31:0] 2. Start next cycle 1. Decode address 2. Store data on D[31:0] 3. Assert TA 1. Negate TA Figure 18-7. Write Cycle Flowchart The write cycle timing diagram is shown in Figure 18-8. S0 S1 S2 S3 S4 S5 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BWEx Write D[31:0] TA Figure 18-8. Basic Write Bus Cycle Table 18-4 describes the six states of a basic write cycle. 18.4.5 Fast-Termination Cycles Two clock-cycle transfers are supported on the MCF5407 bus. In most cases, this is impractical to use in a system because the termination must take place in the same half clock during which AS is asserted. Because this is atypical, it is not referred to as the zero-wait-state case but is called the fast-termination case. A fast-termination cycle is one in which an external device or memory asserts TA as soon as TS is detected. This means that the MCF5407 samples TA on the rising edge of the second cycle of the bus transfer. Figure 18-9 shows a read cycle with fast termination. Note that fast termination cannot be used with internal termination. Chapter 18. Bus Operation 18-9 Data Transfer Operation S0 S1 S4 S5 CLKIN A[31:0],TT[1:0] TM[2:0, SIZ[1:0]] R/W TIP TS AS, CSx BEx, OE Read D[31:0] TA Figure 18-9. Read Cycle with Fast Termination Figure 18-10 shows a write cycle with fast termination. S0 S1 S4 S5 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BWEx, OE D[31:0] Write TA Figure 18-10. Write Cycle with Fast Termination 18.4.6 Back-to-Back Bus Cycles The MCF5407 runs back-to-back bus cycles whenever possible. For example, when a longword read is started on a word-size bus, the processor performs two back-to-back word read accesses. Back-to-back accesses are distinguished by the continuous assertion of TIP throughout the cycle. Figure 18-11 shows a read back-to-back with a write. 18-10 MCF5407 User's Manual Data Transfer Operation S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx OE Read D[31:0] Write TA Figure 18-11. Back-to-Back Bus Cycles Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable. 18.4.7 Burst Cycles The MCF5407 can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to. For example, with bursting enabled, a word transfer to an 8-bit port would take a 2-byte burst cycle for which SIZ[1:0] = 10 throughout. A line transfer to a 32-bit port would take a 4-longword burst cycle, for which SIZ[1:0] = 11 throughout. The MCF5407 bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize DMA transfers. A user can add wait states by delaying termination of the cycle. The initiation of a burst cycle is encoded on the size pins. For burst transfers to smaller port sizes, SIZ[1:0] indicates the size of the entire transfer. For example, if the MCF5407 writes a longword to an 8-bit port, SIZ[1:0] = 00 for the first byte transfer and does not change. CSCRs are used to enable bursting for reads, writes, or both. MCF5407 memory space can be declared burst-inhibited for reads and writes by clearing the appropriate CSCRx[BSTR,BSTW]. A line access to a burst-inhibited region is broken into separate port-width accesses. Unlike a burst access, SIZ[1:0] = 11 only for the first port-width access; for the remaining accesses, SIZ[1:0] reflects the port width, with individual accesses separated by AS negations. The address changes if internal termination is used but does not change if external termination is used, as shown in Figure 18-12 and Figure 18-14. Chapter 18. Bus Operation 18-11 Data Transfer Operation 18.4.7.1 Line Transfers A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transfers on multiple address boundaries. Table 18-5 shows allowable patterns for line accesses. Table 18-5. Allowable Line Access Patterns A[3:2] Longword Accesses 00 0-4-8-C 01 4-8-C-0 10 8-C-0-4 11 C-0-4-8 18.4.7.2 Line Read Bus Cycles Figure 18-12 shows line read with zero wait states. The access starts like a basic read bus cycle with the first data transfer sampled on the rising edge of S4, but the next pipelined burst data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined data burst is single cycle until the last one, which can be held for up to 2 CLKIN cycles after TA is asserted. Note that AS and CSx are asserted throughout the burst transfer. This example shows the timing for external termination, which differs only from the internal termination example in Figure 18-13 in that the address lines change only at the beginning (assertion of TS and TIP) and end (negation of TIP) of the transfer. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx, OE D[31:0] Read Read Read Read TA Figure 18-12. Line Read Burst (2-1-1-1), External Termination Figure 18-13 shows timing when internal termination is used. 18-12 MCF5407 User's Manual Data Transfer Operation S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 CLKIN A[31:0] TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx, OE Read D[31:0] Read Read Read TA Figure 18-13. Line Read Burst (2-1-1-1), Internal Termination Figure 18-14 shows a line access read with one wait state programmed in CSCRx to give the peripheral or memory more time to return read data. This figure follows the same execution as a zero-wait state read burst with the exception of an added wait state. . S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10S11S12S13 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx, OE D[31:0] Read Read Read Read TA Figure 18-14. Line Read Burst (3-2-2-2), External Termination Figure 18-15 shows a burst-inhibited line read access with fast termination. The external device executes a basic read cycle while determining that a line is being transferred. The external device uses fast termination for subsequent transfers. Chapter 18. Bus Operation 18-13 Data Transfer Operation S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 S6 S7 CLKIN A[3:2] = 00 A[31:0] A[3:2] = 01 R/W TT[1:0] TM[2:0] TIP SIZ[1:0] Line Longword TS AS, CSx BE/BWEx, OE D[31:0] Read Read Read Read Fast Fast Fast TA Basic Figure 18-15. Line Read Burst-Inhibited, Fast, External Termination 18.4.7.3 Line Write Bus Cycles Figure 18-16 shows a line access write with zero wait states. It begins like a basic write bus cycle with data driven one clock after TS. The next pipelined burst data is driven a cycle after the write data is registered (on the rising edge of S6). Each subsequent burst takes a single cycle. Note that as with the line read example in Figure 18-12, AS and CSx remain asserted throughout the burst transfer. This example shows the behavior of the address lines for both internal and external termination. Note that with external termination, address lines, like SIZ, TT, and TM, hold the same value for the entire transfer. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 CLKIN A[31:0] Internal Termination A[31:0] External Termination SIZ[1:0] TM[1:0], TT[1:0] R/W, TIP TS AS, CSx OE, BE/BWE D[31:0] Write Write Write Write TA Figure 18-16. Line Write Burst (2-1-1-1), Internal/External Termination 18-14 MCF5407 User's Manual Data Transfer Operation Figure 18-17 shows a line burst write with one wait-state insertion. S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10S11 CLKIN A[31:0] R/W, TIP TM[2:0], TT[1:0] SIZ[1:0] TS AS, CSx OE, BWE Write D[31:0] Write Write Write TA Figure 18-17. Line Write Burst (3-2-2-2) with One Wait State, Internal Termination Figure 18-18 shows a burst-inhibited line write. The external device executes a basic write cycle while determining that a line is being transferred. The external device uses fast termination to end each subsequent transfer. S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 CLKIN A[31:0] A[3:2] = 00 A[3:2] = 01 R/W, TIP TT[1:0] TM[2:0] SIZ[1:0] Longword Line TS AS, CSx OE, BWE D[31:0] Write Write Write Write TA Basic Fast Fast Fast Figure 18-18. Line Write Burst-Inhibited, Internal Termination 18.4.7.4 Transfers Using Mixed Port Sizes Figure 18-19 shows timing for a longword read from an 8-bit port using external termination. Figure 18-20 shows the same transfer with internal termination. For both, SIZ[1:0] change only at the start of a new transfer because this burst is implemented as one Chapter 18. Bus Operation 18-15 Misaligned Operands transfer. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 CLKIN A[31:0], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx, OE Read Read D[31:0] Read Read TA Figure 18-19. Longword Read from an 8-Bit Port, External Termination Note that with external termination, address signals do not change. With internal termination, Figure 18-20, A[1:0] increment for the same longword transfer. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 CLKIN A[1:0] A[31:2], TT[1:0] TM[2:0], SIZ[1:0] R/W TIP TS AS, CSx BE/BWEx, OE D[31:0] Read Read Read Read TA Figure 18-20. Longword Read from an 8-Bit Port, Internal Termination 18.5 Misaligned Operands Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned. A byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a longword is misaligned at an address not a multiple of four. Although the MCF5407 enforces no alignment restrictions for data operands (including program counter (PC) relative data addressing), additional bus cycles are required for misaligned operands. 18-16 MCF5407 User's Manual Bus Errors Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address error exception. The MCF5407 converts misaligned, cache-inhibited operand accesses to multiple aligned accesses. Figure 18-21 shows the transfer of a longword operand from a byte address to a 32-bit port. In this example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device supplies the byte and acknowledges the data transfer. When the MCF5407 starts the second cycle, SIZ[1:0] specify a word transfer with a byte offset of 0x2. The next two bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the port supplies the final byte, and the operation is complete. 31 24 23 16 15 87 0 A[2:0] Transfer 1 -- Byte 0 -- -- 001 Transfer 2 -- -- Byte 1 Byte 2 010 Transfer 3 Byte 3 -- -- -- 100 Figure 18-21. Example of a Misaligned Longword Transfer (32-Bit Port) If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the cache. The example in Figure 18-22 differs from the one in Figure 18-21 in that the operand is word-sized and the transfer takes only two bus cycles. 31 24 23 16 15 87 0 A[2:0] Transfer 1 -- -- -- Byte 0 001 Transfer 2 Byte 0 -- -- -- 100 Figure 18-22. Example of a Misaligned Word Transfer (32-Bit Port) NOTE: External masters using internal MCF5407 chip selects and default memory control signals must initiate aligned transfers. 18.6 Bus Errors The MCF5407 has no bus monitor. If the auto-acknowledge feature is not enabled for the address that generates the error, the bus cycle can be terminated by asserting TA or by using the software watchdog timer. If it is required that the MCF5407 handle a bus error differently, an interrupt handler can be invoked by asserting an interrupt to the core along with TA when the bus error occurs. 18.7 Interrupt Exceptions A peripheral device uses the interrupt-request signals (IRQx) to signal the core to take an interrupt exception when it needs the MCF5407 or is ready to send information to it. The interrupt transfers control to an appropriate routine. Chapter 18. Bus Operation 18-17 Interrupt Exceptions The MCF5407 has the following two levels of interrupt masking: * * Interrupt mask registers in the SIM compare interrupt inputs with programmable interrupt mask levels. The SIM outputs only unmasked interrupts. The status register uses a 3-bit interrupt priority mask. The core recognizes only interrupt requests of higher priority than the value in the mask. See Section 2.2.2.1, "Status Register (SR)." NOTE: To mask a level 1-6 interrupt source, write a higher-level SR interrupt mask before setting IMR. Then restore the mask to its previous value. Do not mask a level 7 interrupt source. The MCF5407 continuously samples and synchronizes external interrupt inputs. An interrupt request must be held for at least two consecutive CLKIN periods to be considered valid. To guarantee that the interrupt is recognized, the request level must be maintained until the MCF5407 acknowledges the interrupt with an interrupt-acknowledge cycle. NOTE: Interrupt levels 1-7 are level-sensitive. Level 7 is also edge-triggered. See Section 18.7.1, "Level 7 Interrupts." The MCF5407 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any higher-priority pending exception. Thus, the MCF5407 executes at least one instruction in an interrupt exception handler before recognizing another interrupt request. If autovector generation is used for internal interrupts (ICRn[AVEC] = 1), the interrupt acknowledge vector is generated internally and no interrupt acknowledge cycle is generated on the external bus. If autovector generation is used for external interrupts, no interrupt acknowledge cycle is shown on the external bus (AS is not asserted) unless AVR[BLK] is 0. Consequently, the external interrupt must be cleared in the interrupt service routine. See Section 9.2.2, "Autovector Register (AVR)." 18.7.1 Level 7 Interrupts Level 7 interrupts are nonmaskable and are handled differently than other interrupts. Level 7 interrupts are edge triggered by a transition from a lower priority request to the level 7 request. Interrupts at all other levels are level sensitive. Therefore, if IRQ7 remains asserted, the MCF5407 recognizes only one level 7 interrupt because only one transition from a lower level request to a level 7evel 7 request occurred. For the processor to recognize two consecutive level 7 interrupts, one of the following must occur: 18-18 MCF5407 User's Manual Interrupt Exceptions * * The interrupt request on the interrupt control pins is raised to level 7 and stays there until an interrupt-acknowledge cycle begins. The level later drops but then returns to level 7, causing a second transition on the interrupt control lines. The interrupt request on the interrupt control pins is raised to level 7 and stays there. If the level 7 interrupt routine lowers the mask level, a second level 7 interrupt is recognized without a transition of the interrupt control pins. After the level 7 routine completes, the MCF5407 compares the mask level to the request level on the IRQx signals. Because the mask level is lower than the requested level, the interrupt mask is set back to level 7. To ensure it is recognized, the level 7 request on IRQ7 must be held until the second interrupt-acknowledge bus cycle begins. 18.7.2 Interrupt-Acknowledge Cycle When the MCF5407 processes an interrupt exception, it performs an interruptacknowledge bus cycle to obtain the vector number that contains the starting location of the interrupt exception handler. The interrupt-acknowledge bus cycle is a read transfer that differs from normal read cycles in the following respects: * * * * * TT[1:0] = 0x3 to indicate a CPU space or acknowledge bus cycle. TM[2:0] = the level of interrupt being acknowledged. A[31:5] = 0x7F_FFFF. A[4:2] = the interrupt request level being acknowledged (same as TM[2:0]). A[1:0] = 00. During the interrupt-acknowledge bus cycle (a read cycle), the responding device places the vector number on D[31:24] and the cycle is terminated normally with TA. Figure 18-23 is a flow diagram for an interrupt-acknowledge cycle terminated with TA. Chapter 18. Bus Operation 18-19 Bus Arbitration MCF5407 SYSTEM 1. Drive 0x7FFFFF on A[31:5] 2. Drive 0x0 on A[1:0] 3. Drive interrupt level on A[4:2] 4. Drive R/W to read (R/W = 1) 5. Drive SIZ[1:0] to indicate byte (SIZ[1:0] = 01) 6. Drive TT[1:0] and TM[2:0] to indicate interrupt acknowledge (TT[1:0] = 11; TM[2:0] = interrupt level) 7. Assert TS for one CLKIN cycle 1. Negate TS 2. Drive TM[2:0] to indicate interrupt acknowledge (TM[2:0] = interrupt level) 1. Decode address and select the appropriate slave device. 1. Read and store data (D[31:24]) 2. Drive data on D[31:24] 2. Recognize the transfer is done 3. Assert TA for one CLKIN cycle Figure 18-23. Interrupt-Acknowledge Cycle Flowchart 18.8 Bus Arbitration The MCF5407 bus protocol gives either the MCF5407 or an external device access to the external bus. If more than one external device uses the bus, an external arbiter can prioritize requests and determine which device is bus master. When the MCF5407 is bus master, it uses the bus to fetch instructions and transfer data to and from external memory. When an external device is bus master, the MCF5407 can monitor the external master's transfers and interact through its chip-select, DRAM control, and transfer termination signals. See Section 10.4.1.3, "Chip-Select Control Registers (CSCR0-CSCR7)," and Chapter 11, "Synchronous/Asynchronous DRAM Controller Module." Two-wire bus arbitration is used where the MCF5407 shares the bus with a single external device. This mode uses BG and BD. The external device can ignore BR. Three-wire mode is used where the MCF5407 shares the bus with multiple external devices. This requires an external bus arbiter and uses BG, BD, and BR. In either mode, the MCF5407 bus arbiter operates synchronously and transitions between states on the rising edge of CLKIN. Table 18-6 shows the four arbitration states the MCF5407 can be in during bus operation. Table 18-6. MCF5407 Arbitration Protocol States State Master Bus BD Reset None Not driven Negated The MCF5407 enters reset state from any other state when RSTI or software watchdog reset is asserted. If both are negated, the MCF5407 enters implicit or external device mastership state, depending on BG. Implicit master MCF5407 Not driven Negated The MCF5407 is bus master (BG input is asserted) but is not ready to begin a bus cycle. It continues to three-state the bus until an internal bus request. 18-20 Description MCF5407 User's Manual General Operation of External Master Transfers Table 18-6. MCF5407 Arbitration Protocol States (Continued) State Master Bus Explicit master MCF5407 External master External BD Description Driven Asserted The MCF5407 is explicit bus master when BG is asserted and at least one bus cycle has been initiated. It asserts BD and retains explicit mastership until BG is negated even if no active bus cycles are executed. It releases the bus at the end of the current bus cycle, then negates BD and three-states the bus signals. Not driven Negated An external device is bus master (BG negated to MCF5407). The MCF5407 can assert OE, CS[7:0], BE/BWE[3:0], TA, and all DRAM controller signals (RAS[1:0], CAS[3:0], SRAS, SCAS, DRAMW, SCKE). If the MCF5407 is the only possible master, BG can be tied to GND--no arbiter is needed. 18.8.1 Bus Arbitration Signals Bus arbitration signal timings in Table 18-7 are referenced to the system clock, which is not considered a bus signal. Clock routing is expected to meet application requirements. Table 18-7. ColdFire Bus Arbitration Signal Summary Signal I/O Description BR O Bus request. Indicates to an external arbiter that the processor needs to become bus master. BR is negated when the MCF5407 begins an access to the external bus with no other internal accesses pending. BR remains negated until another internal request occurs. BG I Bus grant. An external arbiter asserts BG to indicate that the MCF5407 can control the bus at the next rising edge of CLKIN. When the arbiter negates BG, the MCF5407 must release the bus as soon as the current transfer completes. The external arbiter must not grant the bus to any other device until both BD and BG are negated. BD O Bus driven. The MCF5407 asserts BD to indicate it is current master and is driving the bus. If it loses bus mastership during a transfer, it completes the last transfer of the current access, negates BD, and three-states all bus signals on the rising edge of CLKIN. If it loses mastership during an idle clock cycle, it three-states all bus signals on the rising edge of CLKIN. 18.9 General Operation of External Master Transfers An external master asserts its hold signal (such as HOLDREQ) when it executes a bus cycle, driving BG high and forcing the MCF5407 to hold all bus requests. During an external master cycle, the MCF5407 can provide memory control signals (OE, CS[7:0], BE/BWE[3:0], RAS[1:0], CAS[3:0]) and TA while the external master drives the address and data bus and other required bus control signals. When the external master asserts TS or AS to the MCF5407, the beginning of a bus cycle is identified and the MCF5407 starts decoding the address driven. Note the following regarding external master accesses: Chapter 18. Bus Operation 18-21 General Operation of External Master Transfers * For the MCF5407 to assert a CSx during external master accesses, CSMRn[AM] must be set. External master hits use the corresponding CSCRn settings for auto-acknowledge, byte enables, and wait states. See Section 10.4.1.3, "Chip-Select Control Registers (CSCR0-CSCR7)." To enable DRAM control signals during external master accesses, DCMRn[AM] must be set. During external master bus cycles, either TS or AS (but not both) should be driven to the MCF5407. Driving both during a bus cycle causes indeterminate results. * * External master transfers that use the MCF5407 to drive memory control signals and TA are like normal MCF5407 transfers. Figure 18-24 shows timing for basic back-to-back bus cycles during an external master transfer. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS CS 1 BE/BWE 1 D[31:0] TA 1 BR 2 BG, BD 2 HOLDREQ External Master 1 Depending on programming, these signals may or may not be driven 2 This signal is driven by the processor for an external master transfer. by the processor. Figure 18-24. Basic No-Wait-State External Master Access R/W is asserted high for reads and low for writes; otherwise, the transfers are the same. In Figure 18-24, the MCF5407 chip select's internal transfer acknowledge is enabled and the MCF5407 drives TA as an output after a programmed number of wait states. 18-22 MCF5407 User's Manual General Operation of External Master Transfers NOTE: Bus timing diagrams for external master transfers are not valid for on-chip internal four-channel DMA accesses on the MCF5407. Timing diagrams describe transactions in general terms of bus cycles (Cn) rather than the states (Sn) used in the bus diagrams. Table 18-8 defines the cycles for Figure 18-24. Table 18-8. Cycles for Basic No-Wait-State External Master Access Cycle C1 Definition The external master asserts HOLDREQ, signaling the MCF5407 to hold bus requests. BD should not be asserted. The external master drives address, TS, R/W, TT[1:0], TM[2:0], TIP, and SIZ[1:0] as MCF5407 inputs. C2-C3 The MCF5407 decodes the external master's address and control signals to identify the proper chip select and byte enable assertion. The external master negates TS in C2. C4 On the falling edge of CLKIN, the MCF5407 asserts the appropriate chip select for the external master access along with the appropriate byte enables. C5 On the rising edge of CLKIN, data is driven onto the bus by the device selected by CS. On the rising edge, the MCF5407 asserts TA to indicate the cycle is complete. C6 TA negates on the rising edge of CLKIN. On the falling edge, the MCF5407 negates the chip select and byte enables and the next cycle can begin. C7 The external master negates TIP on the rising edge of CLKIN. C8 The external device retains bus mastership and drives the address bus, TS, R/W, TT[1:0], TM[2:0], TIP, and SIZ[1:0] as inputs to the MCF5407. C9 The MCF5407 decodes the external master's address and control signals to identify the proper chip select and byte enable assertion. The external master negates TS. The MCF5407 asserts BR on the rising edge of CLKIN, signalling that it wants to arbitrate for the bus when the current cycle completes. C10 The MCF5407 continues to decode the external device's address and control signals to identify the proper chip select and byte enable assertion. C11 On the falling edge of CLKIN, the MCF5407 asserts the appropriate chip select for the external master access along with the appropriate byte enables. Figure 18-25 shows a burst line access for an external master transfer with the chip select set to no-wait states and with internal transfer-acknowledge assertion enabled. Chapter 18. Bus Operation 18-23 General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 CLKIN A[31:0] R/W TT[1:0], TM[2:0] SIZ[1:0] TIP TS AS, BR 2 CS 1 BE/BWE 1 D[31:0] TA 1 BG, BD 2 HOLDREQ External Master 1 Depending on programming, these signals may or may not be driven by the 2 These signals are driven by the processor for an external master transfer. processor. Figure 18-25. External Master Burst Line Access to 32-Bit Port Table 18-9 defines the cycles for Figure 18-25. Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port Cycle Definition C1 The external device is bus master and asserts HOLDREQ, indicating to the MCF5407 to hold all bus requests. In other words, BD should not be asserted. The external master drives address, TS, R/W, TT[1:0], TM[2:0], TIP, and SIZ[1:0] as inputs to the MCF5407. SIZ[1:0] inputs indicate a line transfer. The MCF5407 is not asserting BR. C2-C3 The MCF5407 decodes the external device's address and control signals to identify the proper chip-select and byte-enable assertion. The external device negates TS in C2. Address and R/W are latched in the MCF5407 on the rising edge of CLKIN in C2. After C2, the address and R/W are ignored for the rest of the burst transfer. C4 On the falling edge of CLKIN, the MCF5407 asserts the appropriate chip select for the external device access along with the appropriate byte enables. C5 On the rising edge of CLKIN, data is driven onto the bus by the device selected by CS. The MCF5407 asserts TA on the rising edge of CLKIN, indicating the first data transfer is complete. 18-24 MCF5407 User's Manual General Operation of External Master Transfers Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port (Continued) Cycle Definition C6-C8 No-wait state data transfers 2-4 occur on the rising edges of CLKIN. TA continues to be asserted indicating completion of each transfer. TIP, CSx, and BE/BWE[3:0] are driven. C9 TA negates on the rising edge of CLKIN along with external device's negation of TIP. On the falling edge, the MCF5407 negates chip select and byte enables, creating an opportunity for another cycle to begin. 18.9.1 Two-Device Bus Arbitration Protocol (Two-Wire Mode) Two-wire mode bus arbitration lets the MCF5407 share the external bus with a single external bus device without requiring an external bus arbiter. Figure 18-26 shows the MCF5407 connecting to an external device using the two-wire mode. The MCF5407 BG input is connected to the HOLDREQ output of the external device; the MCF5407 BD output is connected to the HOLDACK input of the external device. Because the external device controls the state of HOLDREQ, it controls when the MCF5407 is granted the bus, giving the MCF5407 lower priority. BG HOLDREQ HOLDACK BD BR A[31:0] A[31:0] D[31:0] TS R/W SIZ[1:0] TA D[31:0] TS R/W SIZ[1:0] TA External Bus Master MCF5407 To/from external memory and control Figure 18-26. MCF5407 Two-Wire Mode Bus Arbitration Interface When the external device is not using the bus, it negates HOLDREQ, driving BG low and granting the bus to the MCF5407. When the MCF5407 has an internal bus request pending and BG is low, the MCF5407 drives BD low, negating HOLDACK to the external device. When the external bus device needs the external bus, it asserts HOLDREQ, driving BG high, requesting the MCF5407 to release the bus. If BG is negated while a bus cycle is in progress, the MCF5407 releases the bus at the completion of the bus cycle. Note that the MCF5407 considers the individual transfers of a burst or burst-inhibited access to be a single bus cycle and does not release the bus until the last transfer of the series completes. When the bus has been granted to the MCF5407, one of two situations can occur. In the first case, if the MCF5407 has an internal bus request pending, the MCF5407 asserts BD to indicate explicit bus mastership and begins the pending bus cycle by asserting TS. As Chapter 18. Bus Operation 18-25 General Operation of External Master Transfers shown in Figure 18-25, the MCF5407 continues to assert BD until the completion of the bus cycle. If BG is negated by the end of the bus cycle, the MCF5407 negates BD. While BG is asserted, BD remains asserted to indicate the MCF5407 is master, and it continuously drives the address bus, attributes, and control signals. s C1 C2 C3 C4 C5 C6 C7 C8 C9 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS D[31:0] TA BG BD External Master MCF5407 Figure 18-27. Two-Wire Bus Arbitration with Bus Request Asserted In the second situation, the bus is granted to the MCF5407, but it does not have an internal bus request pending, so it takes implicit bus mastership. The MCF5407 does not drive the bus and does not assert BD if the bus has an implicit master. If an internal bus request is generated, the MCF5407 assumes explicit bus mastership. If explicit mastership was assumed because an internal request was generated, the MCF5407 immediately begins an access and asserts BD. In Figure 18-28, the external device is bus master during C1 and C2. During C3 the external device releases control of the bus by asserting BG to the MCF5407. At this point, there is an internal access pending so the MCF5407 asserts BD during C4 and begins the access. Thus, the MCF5407 becomes the explicit external bus master. Also during C4, the external device removes the grant from the MCF5407 by negating BG. As the current bus master, the MCF5407 continues to assert BD until the current transfer completes. Because BG is negated, the MCF5407 negates BD during C9 and three-states the external bus, thereby returning external bus mastership to the external device. 18-26 MCF5407 User's Manual General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS D[31:0] TA BG BD Implicit Mastership External Master Explicit Mastership MCF5407 Figure 18-28. Two-Wire Implicit and Explicit Bus Mastership In Figure 18-28, the external device is master during C1 and C2. It releases bus control in C3 by asserting BG to the MCF5407. During C4 and C5, the MCF5407 is implicit master because no internal access is pending. In C5, an internal bus request becomes pending, causing the MCF5407 to become explicit bus master in C6 by asserting BD. In C7, the external device removes the bus grant to the MCF5407. The MCF5407 does not release the bus (the MCF5407 continues to assert BD) until the transfer ends. NOTE: The MCF5407 can start a transfer in the clock cycle after BG is asserted. The external master must not assert BG to the MCF5407 while driving the bus or the part may be damaged. Figure 18-29 is a MCF5407 bus arbitration state diagram. States are described in Table 18-6. Chapter 18. Bus Operation 18-27 General Operation of External Master Transfers A1 A2 Reset A4 A3 B1 External Master D1 Implicit Master D3 D2 D4 B3 B2 B4 C3 C5 Explicit Master C1 C2 C4 Figure 18-29. MCF5407 Two-Wire Bus Arbitration Protocol State Diagram Table 18-10 describes the two-wire bus arbitration protocol transition conditions. Table 18-10. MCF5407 Two-Wire Bus Arbitration Protocol Transition Conditions Present State Condition Label RSTI Software Watchdog Reset BG Bus Request Transfer in Progress End of Cycle1 Next State A1 A2 -- -- -- -- -- Reset A2 N3 A -- -- -- -- Reset A3 N N N -- -- -- EM 4 A4 N N A -- -- -- Implicit mas B1 N N N -- -- -- EM B2 N N A -- -- -- Explicit mas B3 N N A N -- -- Implicit mas B4 N N A A -- -- Explicit mas C1 N N A -- -- -- Explicit mas C2 N N N -- -- -- Explicit mas C3 N N N -- N -- EM C4 N N N -- A N Explicit mas C5 N N N -- A A EM D1 N N N -- -- -- EM mas D2 N N A -- -- -- Explicit mas D3 N N A N -- -- Implicit mas D4 N N A A -- -- Explicit mas Reset Implicit Master Explicit Master External Master 18-28 MCF5407 User's Manual General Operation of External Master Transfers 1 Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from a burst-inhibited transfer are considered part of that original transfer. 2 A means asserted. 3 N means negated. 4 EM means external master. 18.9.2 Multiple External Bus Device Arbitration Protocol (Three-Wire Mode) Three-wire mode lets the MCF5407 share the external bus with multiple external devices. This mode requires an external arbiter to assign priorities to each potential master and to determine which device accesses the external bus. The arbiter uses the MCF5407 bus arbitration signals, BR, BD, and BG, to control use of the external bus by the MCF5407. The MCF5407 requests the bus from the external bus arbiter by asserting BR when the core requests an access. It continues to assert BR until after the transfer starts. It can negate BR at any time regardless of the BG status. If the MCF5407 is granted the bus when an internal bus request is generated, it asserts BD and the access begins immediately. The MCF5407 always drives BR and BD, which cannot be directly wire-ORed with other devices. The external arbiter asserts BG to grant the bus to MCF5407, which can begin a bus cycle after the next rising edge of CLKIN. If BG is negated during a bus cycle, the MCF5407 releases the bus when the cycle completes. To guarantee that the bus is released, BG must be negated before the rising edge of the CLKIN in which the last TA is asserted. Note that the MCF5407 treats any series of burst or a burst-inhibited transfers as a single bus cycle and does not release the bus until the last transfer of the series completes. When the MCF5407 is granted the bus after it asserts BR, one of two things can occur. If the MCF5407 has an internal bus request pending, it asserts BD, indicating explicit bus mastership, and begins the pending bus cycle by asserting TS. The MCF5407 continues to assert BD until the external bus arbiter negates BG, after which BD is negated at the completion of the bus cycle. As long as BG is asserted, BD remains asserted to indicate that the MCF5407 is bus master, and the MCF5407 continuously drives the address bus, attributes, and control signals. If no internal request is pending, the MCF5407 takes implicit bus mastership. It does not drive the bus and does not assert BD if the bus has an implicit master. If an internal bus request is generated, the MCF5407 assumes explicit bus mastership and immediately begins an access and asserts BD. Figure 18-30 shows implicit and explicit bus mastership due to generation of an internal bus request. Chapter 18. Bus Operation 18-29 General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS D[31:0] TA BR BG BD Implicit Mastership External Master Explicit Mastership MCF5407 Figure 18-30. Three-Wire Implicit and Explicit Bus Mastership In Figure 18-30, the external device is bus master during C1 and C2, releasing control in C3, at which time the external arbiter asserts BG to the MCF5407. During C4 and C5, the MCF5407 is implicit master because no internal access is pending. In C5, an internal bus request becomes pending, causing the MCF5407 to take explicit bus mastership in C6 by asserting BR and BD. In C7, the external device removes the bus grant to the MCF5407. The MCF5407 does not release the bus (the MCF5407 asserts BD) until the transfer ends. NOTE: The MCF5407 can start a transfer in the CLKIN cycle after BG is asserted. The external arbiter should not assert BG to the MCF5407 until the previous external master stops driving the bus. Asserting BG during another external master's transfer may damage the part. 18-30 MCF5407 User's Manual General Operation of External Master Transfers C1 C2 C3 C4 C5 C6 C7 C8 C9 CLKIN A[31:0], TT[1:0] SIZ[1:0], TM[2:0] R/W TIP TS AS D[31:0] TA BR BG BD External Master MCF5407 Figure 18-31. Three-Wire Bus Arbitration In Figure 18-31, the external device is bus master during C1 and C2. During C2, the MCF5407 requests the external bus because of a pending internal transfer. On C3, the external releases mastership and the external arbiter grants the bus to the MCF5407 by asserting BG. At this point, an internal is access pending so the MCF5407 asserts BD during C4 and begins the access. Thus, the MCF5407 becomes the explicit bus master. Also during C4, the external arbiter removes the grant from the MCF5407 by negating BG. Because the MCF5407 is bus master, it continues to assert BD until the current transfer completes. Because BG is negated, the MCF5407 negates BD during C9 and three-states the external bus, thereby passing mastership to an external device. The MCF5407 can assert BR to signal the external arbiter that it needs the bus. However, there is no guarantee that when the bus is granted to the MCF5407 that a bus cycle will be performed. At best, BR must be used as a status output that indicates when the MCF5407 needs the bus, but not as an indication that the MCF5407 is in a certain bus arbitration state. Figure 18-32 is a high-level state diagram for MCF5407 bus arbitration protocol. Table 18-6 describes the four states shown in Figure 18-32. Chapter 18. Bus Operation 18-31 General Operation of External Master Transfers A1 A2 Reset A4 A3 D1 B1 External Master Implicit Master D3 D2 D4 B3 B2 B4 C3 C5 Explicit Master C1 C2 C4 Figure 18-32. Three-Wire Bus Arbitration Protocol State Diagram Table 18-11 lists conditions that cause state transitions. Table 18-11. Three-Wire Bus Arbitration Protocol Transition Conditions Current State Reset Implicit master 18-32 Software Watchdog Reset BG Bus Request Transfer in Progress End of Cycle 1 Next State Asserted -- -- -- -- -- Reset Negated Asserted -- -- -- -- Reset Condition Label RSTI A1 A2 A3 Negated Negated Negated -- -- -- EM A4 Negated Negated Asserted -- -- -- Implicit master B1 Negated Negated Negated -- -- -- External device master B2 Negated Negated Asserted -- -- -- Explicit master B3 Negated Negated Asserted Negated -- -- Implicit master B4 Negated Negated Asserted Asserted -- -- Explicit master MCF5407 User's Manual Reset Operation Table 18-11. Three-Wire Bus Arbitration Protocol Transition Conditions (Continued) Current State Condition Label RSTI Software Watchdog Reset BG Bus Request Transfer in Progress End of Cycle 1 Explicit master C1 Negated Negated Asserted -- -- -- Explicit master C2 Negated Negated Negated -- -- -- Explicit master C3 Negated Negated Negated -- Negated -- External device master C4 Negated Negated Negated -- Yes Negated Explicit master C5 Negated Negated Negated -- Yes Yes External device master D1 Negated Negated Negated1 -- -- -- External device master D2 Negated Negated Asserted -- -- -- Explicit master D3 Negated Negated Asserted Negated -- -- Implicit master D4 Negated Negated Asserted Asserted -- -- Explicit master External master 1 Next State Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from a burst-inhibited transfer are considered part of that original transfer. The bus arbitration state diagram can be used for the MCF5407 three-wire bus arbitration protocol to approximate the high-level behavior of the MCF5407. It is assumed that all TS or AS signals in a system are tied together and each bus device's BD and BR signals are connected individually to the external arbiter. The external arbiter must ensure that any external masters will have released the bus after the next rising edge of CLKIN before asserting BG to the MCF5407. The MCF5407 does not monitor external bus master operation regarding bus arbitration. NOTE: The MCF5407 can start a transfer on the rising edge of CLKIN the cycle after BG is asserted. The external arbiter should not assert BG to the MCF5407 until the previous external master stops driving the bus or the part may be damaged. 18.10 Reset Operation The MCF5407 supports two types of reset. Asserting RSTI resets the entire MCF5407. A software watchdog reset resets everything but the internal PLL module. Chapter 18. Bus Operation 18-33 Reset Operation 18.10.1 Master Reset To perform a master reset, an external device asserts RSTI. When power is applied to the system, external circuitry should assert RSTI for a minimum of 16 CLKIN cycles after EVcc and IVcc are within tolerance. Figure 18-33 is a functional timing diagram of the master reset operation, showing relationships among E/IVcc, RSTI, mode selects, and bus signals. CLKIN must be stable by the time E/IVcc reach the minimum operating specification. See Section 20.1.1, "Supply Voltage Sequencing and Separation Cautions." CLKIN should start oscillating as E/IVcc are ramped up to clear out contention internal to the MCF5407 caused by the random states of internal flip-flops on power up. RSTI is internally synchronized for two CLKIN cycles before being used and must meet the specified setup and hold times in relationship to CLKIN to be recognized. >16 CLKIN cycles 50K CLKIN cycles PLL lock time CLKIN EVCC, IVCC RSTI RSTO D[7:0] Bus Signals BR BD Figure 18-33. Master Reset Timing During the master reset period, all signals capable of being three-stated are driven to a high-impedance; all others are negated. When RSTI negates, all bus signals remain in a high-impedance state until the MCF5407 is granted the bus and the core begins the first bus cycle for reset exception processing. A master reset causes any bus cycle (including DRAM refresh cycle) to terminate and initializes registers appropriately for a reset exception. Note that during reset D[7:0] are sampled on the negating edge of RSTI for initial MCF5407 configurations listed in Table 18-12. 18-34 MCF5407 User's Manual Reset Operation Table 18-12. Data Pin Configuration Pin D7 D[6:5] Function Auto-Acknowledge Configuration (AA_CONFIG) Port Size Configuration (PS_CONFIG[1:0]) D4 Address Configuration (ADDR_CONFIG/D4) D3 Byte Enable Configuration (BE_CONFIG) D[2:0] Divide Control (DIVIDE[2:0]) See Section 17.5.5, "Data/Configuration Pins (D[7:0])." Motorola recommends that the data pins be driven rather than using a weak pull-up or pull-down resistor. Table 17-1 lists the encoding of these pins sampled at reset. After RSTI is negated, 32 bits of CPU configuration information are loaded into data register D0 and 32 bits of internal memory information are loaded in D1. Because D0 and D1 are uninitialized on previous ColdFire devices, this feature allows users to identify the MCF5407 through software. Values D1 = 0x0630_0530 and D0 = 0xCF4x_C012 identify the MCF5407, where x identifies the core revision number (0x1 for the initial device). 18.10.2 Software Watchdog Reset A software watchdog reset is performed if the executing software does not provide the correct write data sequence with the enable-control bit set. This reset helps prevent runaway software or unterminated bus cycles. Figure 18-34 is a functional timing diagram of the software watchdog reset operation, showing RSTO and bus signal relationships. >16 CLKS 50K CLKIN Cycle Lock Time >10 CLKS CLKIN BCLKO PSTCLK RSTI D[7:0] D[7:0] latched on rising edge of CLKIN RSTO Figure 18-34. Software Watchdog Reset Timing Chapter 18. Bus Operation 18-35 Reset Operation During the software watchdog reset period, all signals that can be are driven to a high-impedance state; all those that cannot be are negated. When RSTO negates, bus signals remain in a high-impedance state until the MCF5407 is granted the bus and the ColdFire core begins the first bus cycle for reset exception processing. 18-36 MCF5407 User's Manual Chapter 19 IEEE 1149.1 Test Access Port (JTAG) This chapter describes configuration and operation of the MCF5407 JTAG test implementation. It describes the use of JTAG instructions and provides information on how to disable JTAG functionality. 19.1 Overview The MCF5407 dedicated user-accessible test logic is fully compliant with the publication Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1. Use the following description in conjunction with the supporting IEEE document listed above. This section includes the description of those chip-specific items that the IEEE standard requires as well as those items specific to the MCF5407 implementation. The MCF5407 JTAG test architecture supports circuit board test strategies based on the IEEE standard. This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST. Test logic design is static and is independent of the system logic except where the JTAG is subordinate to other complimentary test modes, as described in Chapter 5, "Debug Support." When in subordinate mode, JTAG test logic is placed in reset and the TAP pins can be used for other purposes, as described in Table 19-1. The MCF5407 JTAG implementation can do the following: * * * * * Perform boundary-scan operations to test circuit board electrical continuity Bypass the MCF5407 by reducing the shift register path to a single cell Set MCF5407 output drive pins to fixed logic values while reducing the shift register path to a single cell Sample MCF5407 system pins during operation and transparently shift out the result Protect MCF5407 system output and input pins from backdriving and random toggling (such as during in-circuit testing) by placing all system pins in highimpedance state NOTE: IEEE Standard 1149.1 may interfere with system designs that do not incorporate JTAG capability. Section 19.6, "Disabling IEEE Standard 1149.1 Operation," describes precautions for ensuring Chapter 19. IEEE 1149.1 Test Access Port (JTAG) 19-1 JTAG Signal Descriptions that this logic does not affect system or debug operation. Figure 19-1 is a block diagram of the MCF5407 implementation of the 1149.1 IEEE standard. The test logic includes several test data registers, an instruction register, instruction register control decode, and a 16-state dedicated TAP controller. Test Data Registers V+ TDI Boundary Scan Register M U X ID Code Bypass 3-Bit Instruction Decode 3-Bit Instruction Register M U X TDO V+ TMS TCK TAP V+ TRST Figure 19-1. JTAG Test Logic Block Diagram 19.2 JTAG Signal Descriptions JTAG operation on the MCF5407 is enabled when MTMOD0 is high (logic 1), as described in Table 19-1. Otherwise, JTAG TAP signals, TCK, TMS, TDI, TDO, and TRST, are interpreted as the debug port pins. MTMOD0 should not be changed while RSTI is asserted. 19-2 MCF5407 User's Manual TAP Controller Table 19-1. JTAG Pin Descriptions Pin Description TCK Test clock. The dedicated JTAG test logic clock is independent of the MCF5407 processor clock. Various JTAG operations occur on the rising or falling edge of TCK. Internal JTAG controller logic is designed such that holding TCK high or low indefinitely does cause the JTAG test logic to lose state information. If TCK is not used, it should be tied to ground. TMS/ BKPT Test mode select (MTMOD0 high)/breakpoint (MTMOD0 low). TMS provides the JTAG controller with information to determine the test operation mode. The states of TMS and of the internal 16-state JTAG controller state machine at the rising edge of TCK determine whether the JTAG controller holds its current state or advances to the next state. This directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up, so if it is not driven low, its value defaults to a logic level of 1. If TMS is not used, it should be tied to VDD. BKPT signals a hardware breakpoint to the processor in debug mode. See Chapter 5, "Debug Support." TDI/DSI Test data input (MTMOD0 high)/development serial input (MTMOD0 low). TDI provides the serial data port for loading the JTAG boundary-scan, bypass, and instruction registers. Shifting in of data depends on the state of the JTAG controller state machine and the instruction in the instruction register. This shift occurs on the rising edge of TCK. TDI has an internal pull-up so if it is not driven low its value defaults to a logical 1. If TDI is not used, it should be tied to VDD. DSI provides single-bit communication for debug module commands. See Chapter 5, "Debug Support." TDO/ DSO Test data output (MTMOD0 high)/development serial output (MTMOD0 low). TDO is the serial data port for outputting data from JTAG logic. Shifting data out depends on the state of the JTAG controller state machine and the instruction currently in the instruction register. This shift occurs on the falling edge of TCK. When not outputting test data, TDO is three-stated. It can also be placed in three-state mode to allow bussed or parallel connections to other devices having JTAG. DSO provides single-bit communication for debug module commands. See Chapter 5, "Debug Support." TRST/ Test reset (MTMOD0 high)/development serial clock (MTMOD0 low). As TRST, this pin asynchronously DSCLK resets the internal JTAG controller to the test logic reset state, causing the JTAG instruction register to choose the IDCODE instruction. When this occurs, all JTAG logic is benign and does not interfere with normal MCF5407 functionality. Although this signal is asynchronous, Motorola recommends that TRST make only an asserted-to-negated transition while TMS is held at a logic 1 value. TRST has an internal pull-up; if it is not driven low its value defaults to a logic level of 1. However, if TRST is not used, it can either be tied to ground or, if TCK is clocked, to VDD. The former connection places the JTAG controller in the test logic reset state immediately; the latter connection eventually puts the JTAG controller (if TMS is a logic 1) into the test logic reset state after 5 TCK cycles. DSCLK is the development serial clock for the serial interface to the debug module.The maximum DSCLK frequency is 1/2 the CLKIN frequency. See Chapter 5, "Debug Support." 19.3 TAP Controller The state of TMS at the rising edge of TCK determines the current state of the TAP controller. The TAP controller can follow two basic two paths, one for executing JTAG instructions and the other for manipulating JTAG data based on JTAG instructions. The various states of the TAP controller are shown in Figure 19-2. For more detail on each state, see the IEEE Standard 1149.1 JTAG document. Note that regardless of the TAP controller state, test-logic-reset can be entered if TMS is held high for at least five rising edges of TCK. Figure 19-2 shows the JTAG TAP controller state machine. Chapter 19. IEEE 1149.1 Test Access Port (JTAG) 19-3 JTAG Register Descriptions 1 Test-Logic-Reset TLR 0 Run-Test-Idle 0 <-- Value of TMS at rising edge of TCK 1 1 1 Select-IR-Scan SeIR Select-DR-Scan SeDR RTI 0 0 1 1 Capture-DR CaDR Capture-IR CaIR 0 0 Shift-IR Shift-DR ShDR 0 1 1 Exit1-DR Exit1-IR 1 E1DR 0 Pause-DR PaDR Pause-IR PaIR 0 1 0 1 0 Exit2-DR E2DR Exit2-IR E2IR 1 1 Update-DR UpDR 1 1 E1IR 0 0 0 ShIR 0 Update-IR UpIR 1 0 Figure 19-2. JTAG TAP Controller State Machine 19.4 JTAG Register Descriptions The following sections describe the JTAG registers implemented on the MCF5407. 19-4 MCF5407 User's Manual JTAG Register Descriptions 19.4.1 JTAG Instruction Shift Register The MCF5407 IEEE Standard 1149.1 implementation uses a 3-bit instruction-shift register (IR) without parity. This register transfers its value to a parallel hold register and applies one of six instructions on the falling edge of TCK when the TAP state machine is in Update-IR state. To load instructions into the shift portion of the register, place the serial data on TDI before each rising edge of TCK. The msb of the instruction shift register is the bit closest to the TDI pin, and the lsb is the bit closest to TDO. Table 19-2 describes customer-usable instructions. Table 19-2. JTAG Instructions Instruction Class IR Description EXTEST (EXT) Required 000 Selects the boundary-scan register. Forces all output pins and bidirectional pins configured as outputs to the preloaded fixed values (with the SAMPLE/PRELOAD instruction) and held in the boundary-scan update registers. EXTEST can also configure the direction of bidirectional pins and establish high-impedance states on some pins. EXTEST becomes active on the falling edge of TCK in the Update-IR state when the data held in the instruction-shift register is equivalent to octal 0. IDCODE (IDC) Optional 001 Selects the IDCODE register for connection as a shift path between TDI and TDO. Interrogates the MCF5407 for version number and other part identification. The IDCODE register is implemented in accordance with IEEE Standard 1149.1 so the lsb of the shift register stage is set to logic 1 on the rising edge of TCK following entry into the capture-DR state. Therefore, the first bit shifted out after selecting the IDCODE register is always a logic 1. The remaining 31-bits are also set to fixed values. See Section 19.4.2, "IDCODE Register." IDCODE is the default value in the IR when a JTAG reset occurs by either asserting TRST or holding TMS high while clocking TCK through at least five rising edges and the falling edge after the fifth rising edge. A JTAG reset causes the TAP state machine to enter test-logic-reset state (normal operation of the TAP state machine into the test-logic-reset state also places the default value of octal 1 into the instruction register). The shift register portion of the instruction register is loaded with the default value of octal 1 in Capture-IR state and a TCK rising edge occurs. SAMPLE/ PRELOAD (SMP) Required 100 Provides two separate functions. It obtains a sample of the system data and control signals at the MCF5407 input pins and before the boundary-scan cell at the output pins. This sampling occurs on the rising edge of TCK in the capture-DR state when an instruction encoding of octal 4 is in the instruction register. Sampled data is observed by shifting it through the boundary-scan register to TDO by using shift-DR state. The data capture and shift are transparent to system operation. The users must provide external synchronization to achieve meaningful results because there is no internal synchronization between TCK and CLK. SAMPLE/PRELOAD also initializes the boundary-scan register update cells before selecting EXTEST or CLAMP. This is done by ignoring data shifted out of TDO while shifting in initialization data. The Update-DR state in conjunction with the falling edge of TCK can then transfer this data to the update cells. This data is applied to external outputs when an instruction listed above is applied. HIGHZ (HIZ) Optional 101 Anticipates the need to backdrive outputs and protects inputs from random toggling during board testing. Selects the bypass register, forcing all output and bidirectional pins into high-impedance. HIGHZ goes active on the falling edge of TCK in the Update-IR state when instruction shift register data held is equivalent to octal 5. Chapter 19. IEEE 1149.1 Test Access Port (JTAG) 19-5 JTAG Register Descriptions Table 19-2. JTAG Instructions (Continued) Instruction Class IR Description CLAMP (CMP) Optional 110 Selects the bypass register and asserts functional reset while forcing all output and bidirectional pins configured as outputs to fixed, preloaded values in the boundary-scan update registers. Enhances test efficiency by reducing the overall shift path to one bit (the bypass register) while conducting an EXTEST type of instruction through the boundary-scan register. CLAMP becomes active on the falling edge of TCK in the Update-IR state when instruction-shift register data is equivalent to octal 6. BYPASS (BYP) Required 111 Selects the single-bit bypass register, creating a single-bit shift register path from TDI to the bypass register to TDO. Enhances test efficiency by reducing the overall shift path when a device other than the MCF5407 is under test on a board design with multiple chips on the overall 1149.1 defined boundary-scan chain. The bypass register is implemented in accordance with 1149.1 so the shift register stage is set to logic 0 on the rising edge of TCK following entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0 (to differentiate a part that supports an IDCODE register from a part that supports only the bypass register). BYPASS goes active on the falling edge of TCK in the Update-IR state when instruction shift register data is equivalent to octal 7. The IEEE Standard 1149.1 requires the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. IDCODE, CLAMP, and HIGHZ are optional standard instructions that the MCF5407 implementation supports and are described in the IEEE Standard 1149.1. 19.4.2 IDCODE Register The MCF5407 includes an IEEE Standard 1149.1-compliant JTAG identification register, IDCODE, which is read by the MCF5407 JTAG instruction encoded as octal 1. 31 30 29 28 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Version Number 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 (0000 for initial MCF5407 device) Figure 19-3. IDCODE Register Table 19-3 describes IDCODE bit assignments. Table 19-3. IDCODE Bit Assignments Bits Description 31-28 Version number. Indicates the revision number of the MCF5407 27-22 Design center. Indicates the ColdFire design center 21-12 Device number. Indicates an MCF5407 11-1 Indicates the reduced JEDEC ID for Motorola. Joint Electron Device Engineering Council (JEDEC) Publication 106-A and Chapter 11 of the IEEE Standard 1149.1 give more information on this field. 0 Identifies this as the JTAG IDCODE register (and not the bypass register) according to the IEEE Standard 1149.1 19-6 MCF5407 User's Manual JTAG Register Descriptions 19.4.3 JTAG Boundary-Scan Register The MCF5407 model includes an IEEE Standard 1149.1-compliant boundary-scan register connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. This register captures signal data on the input pins, forces fixed values on the output pins, and selects the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state pins. Table 19-4 shows MCF5407 boundary-scan register bits. Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type Pin Type Bit Cell Type 0 O.Ctl PP0 enable Pin Cell -- 120 O.Pin BE0 Pin Cell 1 O.Pin PP0 I/O 121 O.Pin SCKE O 2 I.Pin PP0 I/O 122 O.Pin SCAS O 3 IO.Ctl PP1 enable -- 123 O.Pin SRAS O 4 O.Pin PP1 I/O 124 O.Pin DRAMW O 5 I.Pin PP1 I/O 125 O.Pin CAS3 O 6 IO.Ctl PP2 enable -- 126 O.Pin CAS2 O 7 O.Pin PP2 I/O 127 O.Pin CAS1 O 8 I.Pin PP2 I/O 128 O.Pin CAS0 O 9 IO.Ctl PP3 enable -- 129 O.Pin RAS1 O 10 O.Pin PP3 I/O 130 O.Pin RAS0 O 11 I.Pin PP3 I/O 131 I.Pin TIN1 I 12 IO.Ctl PP4 enable -- 132 I.Pin TIN0 I 13 O.Pin PP4 I/O 133 O.Pin TOUT0 O 14 I.Pin PP4 I/O 134 O.Pin TOUT1 O 15 IO.Ctl PP5 enable -- 135 I.Pin BG I 16 O.Pin PP5 I/O 136 O.Pin BD O 17 I.Pin PP5 I/O 137 O.Pin BR O 18 IO.Ctl PP6 enable -- 138 I.Pin IRQ1 I 19 O.Pin PP6 I/O 139 I.Pin IRQ3 I 20 I.Pin PP6 I/O 140 I.Pin IRQ5 I 21 IO.Ctl PP7 enable -- 141 I.Pin IRQ7 I 22 O.Pin PP7 I/O 142 I.Pin RSTI I 23 I.Pin PP7 I/O 143 O.Pin TS I/O 24 O.Pin PSTDDATA7 O 144 I.Pin TS I/O 25 O.Pin PSTDDATA6 O 145 IO.Ctl TA enable -- 26 O.Pin PSTDDATA5 O 146 O.Pin TA I/O 27 O.Pin PSTDDATA4 O 147 I.Pin TA I/O 28 O.Pin PSTDDATA3 O 148 O.Pin R/W I/O Chapter 19. IEEE 1149.1 Test Access Port (JTAG) Pin Type O 19-7 JTAG Register Descriptions Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type 29 O.Pin 30 O.Pin 31 O.Pin PSTDDATA0 O 151 32 O.Pin PSTCLK O 152 33 I.Pin CLKIN I 153 O.Pin 34 IO.Ctl RSTO enable -- 154 35 O.Pin RSTO I/O 155 36 I.Pin RSTO I/O 156 37 O.Pin BCLKO O 157 38 I.Pin EDGESEL I 39 O.Pin TXD0 40 I.Pin RXD0 41 O.Pin RTS0 42 I.Pin CTS0 43 O.Pin TXD1 44 I.Pin 45 O.Pin 46 I.Pin CTS1 I 166 I.Pin PP15 I/O 47 I.Pin HIZ I 167 O.Pin PP15 I/O 48 IO.Ctl Data enable -- 168 IO.Ctl PP14 enable -- 49 O.Pin D0 I/O 169 I.Pin PP14 I/O 50 I.Pin D0 I/O 170 O.Pin PP14 I/O 51 O.Pin D1 I/O 171 IO.Ctl PP13 enable -- 52 I.Pin D1 I/O 172 I.Pin PP13 I/O 53 O.Pin D2 I/O 173 O.Pin PP13 I/O 54 I.Pin D2 I/O 174 IO.Ctl PP12 enable -- 55 O.Pin D3 I/O 175 I.Pin PP12 I/O 56 I.Pin D3 I/O 176 O.Pin PP12 I/O 57 O.Pin D4 I/O 177 IO.Ctl PP11 enable -- 58 I.Pin D4 I/O 178 I.Pin PP11 I/O 59 O.Pin D5 I/O 179 O.Pin PP11 I/O 60 I.Pin D5 I/O 180 IO.Ctl PP10 enable -- 61 O.Pin D6 I/O 181 I.Pin PP10 I/O 62 I.Pin D6 I/O 182 O.Pin PP10 I/O 63 O.Pin D7 I/O 183 IO.Ctl PP9 enable -- 64 I.Pin D7 I/O 184 I.Pin PP9 I/O 19-8 Pin Cell Pin Type Bit Cell Type PSTDDATA2 O 149 I.Pin R/W I/O PSTDDATA1 O 150 O.Pin AS I/O I.Pin AS I/O O.Pin CS7 O CS6 O O.Pin CS5 O O.Pin CS4 O O.Pin CS3 O O.Pin CS2 O 158 O.Pin CS1 O O 159 O.Pin CS0 O I 160 O.Pin OE O O 161 O.Pin SIZ1 I/O I 162 I.Pin SIZ1 I/O O 163 O.Pin SIZ0 I/O RXD1 I 164 I.Pin SIZ0 I/O RTS1 O 165 IO.Ctl PP15 enable -- MCF5407 User's Manual Pin Cell Pin Type JTAG Register Descriptions Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type Pin Cell Pin Type Bit Cell Type Pin Cell 65 O.Pin D8 I/O 185 O.Pin PP9 I/O 66 I.Pin D8 I/O 186 IO.Ctl PP8 enable -- 67 O.Pin D9 I/O 187 I.Pin PP8 I/O 68 I.Pin D9 I/O 188 O.Pin PP8 I/O 69 O.Pin D10 I/O 189 IO.Ctl TS/R/W/SIZ enable -- 70 I.Pin D10 I/O 190 IO.Ctl Address enable -- 71 O.Pin D11 I/O 191 O.Pin A23 I/O 72 I.Pin D11 I/O 192 I.Pin A23 I/O 73 O.Pin D12 I/O 193 O.Pin A22 I/O 74 I.Pin D12 I/O 194 I.Pin A22 I/O 75 O.Pin D13 I/O 195 O.Pin A21 I/O 76 I.Pin D13 I/O 196 I.Pin A21 I/O 77 O.Pin D14 I/O 197 O.Pin A20 I/O 78 I.Pin D14 I/O 198 I.Pin A20 I/O 79 O.Pin D15 I/O 199 O.Pin A19 I/O 80 I.Pin D15 I/O 200 I.Pin A19 I/O 81 O.Pin D16 I/O 201 O.Pin A18 I/O 82 I.Pin D16 I/O 202 I.Pin A18 I/O 83 O.Pin D17 I/O 203 O.Pin A17 I/O 84 I.Pin D17 I/O 204 I.Pin A17 I/O 85 O.Pin D18 I/O 205 O.Pin A16 I/O 86 I.Pin D18 I/O 206 I.Pin A16 I/O 87 O.Pin D19 I/O 207 O.Pin A15 I/O 88 I.Pin D19 I/O 208 I.Pin A15 I/O 89 O.Pin D20 I/O 209 O.Pin A14 I/O 90 I.Pin D20 I/O 210 I.Pin A14 I/O 91 O.Pin D21 I/O 211 O.Pin A13 I/O 92 I.Pin D21 I/O 212 I.Pin A13 I/O 93 O.Pin D22 I/O 213 O.Pin A12 I/O 94 I.Pin D22 I/O 214 I.Pin A12 I/O 95 O.Pin D23 I/O 215 O.Pin A11 I/O 96 I.Pin D23 I/O 216 I.Pin A11 I/O 97 O.Pin D24 I/O 217 O.Pin A10 I/O 98 I.Pin D24 I/O 218 I.Pin A10 I/O 99 O.Pin D25 I/O 219 O.Pin A9 I/O 100 I.Pin D25 I/O 220 I.Pin A9 I/O Chapter 19. IEEE 1149.1 Test Access Port (JTAG) Pin Type 19-9 Restrictions Table 19-4. Boundary-Scan Bit Definitions Bit Cell Type 101 O.Pin 102 I.Pin 103 104 105 Pin Cell Pin Type Bit Cell Type Pin Cell Pin Type D26 I/O 221 O.Pin A8 I/O D26 I/O 222 I.Pin A8 I/O O.Pin D27 I/O 223 O.Pin A7 I/O I.Pin D27 I/O 224 I.Pin A7 I/O O.Pin D28 I/O 225 O.Pin A6 I/O 106 I.Pin D28 I/O 226 I.Pin A6 I/O 107 O.Pin D29 I/O 227 O.Pin A5 I/O I/O 108 I.Pin D29 I/O 228 I.Pin A5 109 O.Pin D30 I/O 229 O.Pin A4 I/O 110 I.Pin D30 I/O 230 I.Pin A4 I/O 111 O.Pin D31 I/O 231 O.Pin A3 I/O 112 I.Pin D31 I/O 232 I.Pin A3 I/O 113 O.Pin SDA OD 233 O.Pin A2 I/O 114 I.Pin SDA I 234 I.Pin A2 I/O 115 O.Pin SCL OD 235 O.Pin A1 I/O 116 I.Pin SCL I 236 I.Pin A1 I/O 117 O.Pin BE3 O 237 O.Pin A0 I/O 118 O.Pin BE2 O 238 I.Pin A0 I/O 119 O.Pin BE1 O 19.4.4 JTAG Bypass Register The IEEE Standard 1149.1-compliant bypass register creates a single-bit shift register path from TDI to the bypass register to TDO when the BYPASS instruction is selected. 19.5 Restrictions Test logic design is static, so TCK can be stopped in high or low state with no data loss. However, system logic uses a different system clock not internally synchronized to TCK. Operation mixing 1149.1 test logic with system functional logic that uses both clocks must coordinate and synchronize these clocks externally to the MCF5407. 19.6 Disabling IEEE Standard 1149.1 Operation There are two ways to use the MCF5407 without IEEE Standard 1149.1 test logic being active: 19-10 MCF5407 User's Manual Obtaining the IEEE Standard 1149.1 * Nonuse of JTAG test logic by either nontermination (disconnection) or intentionally fixing TAP logic values. The following issues must be addressed if IEEE Standard 1149.1 logic is not to be used when the MCF5407 is assembled onto a board. -- IEEE Standard 1149.1 test logic must remain transparent and benign to the system logic during functional operation. To ensure that the part enters the test-logic-reset state requires either connecting TRST to logic 0 or connecting TCK to a source that supplies five rising edges and a falling edge after the fifth rising edge. The recommended solution is to connect TRST to logic 0. -- TCK has no internal pull-up as is required on TMS, TDI, and TRST; therefore, it must be terminated to preclude mid-level input values. Figure 19-4 shows pin values recommended for disabling JTAG with the MCF5407 in JTAG mode. VDD * TMS/BKPT TDI/DSI * TRST/DSCLK * TCK Note: MTMOD0 high allows JTAG mode. Figure 19-4. Disabling JTAG in JTAG Mode * Disabling JTAG test logic by holding MTMOD0 low during reset (debug mode). This allows the IEEE Standard 1149.1 test controller to enter test-logic-reset state when TRST is internally asserted to the controller. TAP pins function as debug mode pins. In JTAG mode, inputs TDI/DSI, TMS/BKPT, and TRST/DSCLK have internal pull-ups enabled. Figure 19-5 shows pin values recommended for disabling JTAG in debug mode. TDI/DSI Debug Interface TMS/BKPT TRST/DSCLK TCK Note: MTMOD0 low prohibits JTAG. Figure 19-5. Disabling JTAG in Debug Mode 19.7 Obtaining the IEEE Standard 1149.1 The IEEE Standard 1149.1 JTAG specification is a copyrighted document and must be Chapter 19. IEEE 1149.1 Test Access Port (JTAG) 19-11 Obtaining the IEEE Standard 1149.1 obtained directly from the IEEE: IEEE Standards Department 445 Hoes Lane P.O. Box 1331 Piscataway, NJ 08855-1331 USA http://stdsbbs.ieee.org/ FAX: 908-981-9667 Information: 908-981-0060 or 1-800-678-4333 19-12 MCF5407 User's Manual Chapter 20 Electrical Specifications This chapter describes the AC and DC electrical specifications and thermal characteristics for the MCF5407. Note that this information was correct at the time this book was published. As process technologies improve, there is a likelihood that this information may change. To confirm that this is the latest information, see Motorola's ColdFire webpage, http://www.motorola.com/coldfire. 20.1 General Parameters Table 20-1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of these ranges may cause erratic behavior or damage to the processor. Table 20-1. Absolute Maximum Ratings Rating Symbol Value Units External (I/O pads) supply voltage (3.3-V power pins) EVcc Internal logic supply voltage IVcc -0.3 to +4.0 -0.5 to +2.0 1, 2 V PLL supply voltage PVcc -0.5 to +2.0 2, 3 V Internal logic supply voltage, input voltage level Vin -0.5 to +3.6 4 V Storage temperature range Tstg -55 to +150 oC V 1 IVcc must not exceed EVcc IVcc and PVcc must not differ by more than 0.5 V 3 PV must not exceed EV cc cc 4 V must not exceed EV in cc 2 Table 20-2 lists junction and ambient operating temperatures. Table 20-2. Operating Temperatures Characteristic Maximum operating junction temperature Symbol Value Units Tj TBD oC 1 oC Maximum operating ambient temperature TAmax 70 Minimum operating ambient temperature TAmin 0 1 oC This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature lies within the specified range. Chapter 20. Electrical Specifications 20-1 General Parameters Table 20-3 lists DC electrical operating temperatures. This table is based on an operating voltage of EVcc = 3.3 Vdc 0.3 Vdc and IVcc of 1.8 0.15 Vdc. Table 20-3. DC Electrical Specifications Characteristic Symbol Min Max Units EVcc 3.0 3.6 V V External (I/O pads) operation voltage range 1 IVcc 1.65 1.95 PVcc 1.65 1.95 V Input high voltage VIH 2.0 3.6 V Internal logic operation voltage range PLL operation voltage range 1 Input low voltage VIL -0.5 0.8 V Input signal undershoot -- -- 0.8 V Input signal overshoot -- -- 0.8 V Input leakage current @ 0.5/2.4 V during normal operation Iin -- 20 A ITSI -- 20 A Signal low input current, VIL = 0.8 V 2 IIL 0 1 mA Signal high input current, VIH = 2.0 V 2 IIH 0 1 mA VOH 2.4 -- V VOL -- 0.5 V Load capacitance (all outputs) CL -- 50 pF Capacitance 5, Vin = 0 V, f = 1 MHz CIN -- TBD pF High impedance (three-state) leakage current @ 0.5/2.4 V during normal operation Output high voltage IOH = 8 mA 3, 16 mA 4 Output low voltage IOL = 8 mA 3, 16 mA 4 1 2 3 4 5 IVcc and PVcc should be at the same voltage. BKPT/TMS, DSI/TDI, DSCLK/TRST D[31:0], A[23:0], PP[15:0],TS, TA, SIZ[1:0], R/W, BR, BD, RSTO, AS, CS[7:0], BE[3:0], OE, PSTCLK, PSTDDATA[7:0], DSO, TOUT[1:0], SCL, SDA, RTS[1:0], TXD[1:0] BCLKO, RAS[1:0], CAS[3:0], DRAMW, SCKE, SRAS, SCAS Capacitance CIN is periodically sampled rather than 100% tested. 20-2 MCF5407 User's Manual General Parameters 20.1.1 Supply Voltage Sequencing and Separation Cautions DC Power Supply Voltage Figure 20-1 shows two situations to avoid in sequencing the IVcc and EVcc supplies. EVcc 3.3V 2 1.8V Supplies Stable IVcc, PVcc 1 0 Time Notes: 1 2 IVcc, PVcc rising before EVcc EVcc rising much faster than IVcc, PVcc Figure 20-1. Supply Voltage Sequencing and Separation Cautions IVcc should not be allowed to rise early (1). This is usually avoided by running the regulator for the IVcc supply (1.8 V) from the voltage generated by the 3.3-V EVcc supply (Figure 20-2). This keeps IVcc from rising faster than EVcc. IVcc should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies as shown in Figure 20-2. The series diodes forward bias when the difference between EVcc and IVcc reaches approximately 2.1V, causing IVcc to rise as EVcc ramps up. When the IVcc regulator begins proper operation, the difference between supplies should not exceed 1.5 V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: EVcc IVcc (EVcc - 2.1 V). The PLL Vdd (PVcc) supply should comply with these constraints just as IVcc does. In practice, PVcc is typically connected directly to IVcc with some filtering. Chapter 20. Electrical Specifications 20-3 Clock Timing Specifications 3.3 V Regulator Supply EVcc 1.8 V Regulator IVcc, PVcc Figure 20-2. Example Circuit to Control Supply Sequencing 20.2 Clock Timing Specifications Table 20-4 shows the MCF5407 PLL encodings. Note that they differ from the MCF5307 DIVIDE[1:0] encodings. Table 20-4. Divide Ratio Encodings D[2:0]/DIVIDE[2:0] Input Clock (MHz) Multiplier 011 40.0-54.0 3 120.0-162 60.0-81.0 100 25.0-40.5 4 100.0-162 50.0-81.0 101 25.0-32.4 5 125.0-162 67.5-81.0 110 25.0-27.0 6 150.0-162 75.0-81.0 00x-010 Core Clock (MHz) PSTCLK (MHz) Reserved 111 Reserved Figure 20-3 correlates CLKIN and core clock frequencies for the 3x-6x multipliers. CLKIN Core Clock 3x 40 54 120 162 4x 25 40.5 100 162 5x 25 32.4 125 162 6x 25 27 25 30 CLKIN (MHz) 150 35 40 45 50 55 100 110 120 Core Clock (MHz) 130 140 150 162 160 170 Figure 20-3. CLKIN-to-Core Clock Frequency Ranges Table 20-5 lists specifications for the clock timing parameters shown in Figure 20-4 and Figure 20-5. Motorola recommends that CLKIN be used for the system clock. BCLKO is provided only for compatibility with slower MCF5307 designs. Regardless of the CLKIN frequency driven at power-up, CLKIN (and BCLKO) have the same ratio value to the 20-4 MCF5407 User's Manual Clock Timing Specifications PCLK. Although either signal can be used as a clock reference, CLKIN leaves more room to meet the bus specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN. Table 20-5. Clock Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max 18.5 Note 1 nS C1 CLKIN cycle time C2 CLKIN rise time (0.5V to 2.4 V) -- 2 nS C3 CLKIN fall time (2.4V to 0.5 V) -- 2 nS C4 CLKIN duty cycle (at 1.5 V) C5 PSTCLK cycle time C6 PSTCLK duty cycle (at 1.5 V) C7 BCLKO cycle time C8 BCLKO duty cycle (at 1.5 V) C9 CLKIN to BCLKO 1 40 60 % 12.3 Note 1 nS 40 60 % 18.5 Note 1 nS 45 55 % -1.5 1.5 nS The PLL low-frequency limit depends on the clock divide ratio chosen. See Table 20-4. Figure 20-4 shows timings for the parameters listed in Table 20-5. C1 C3 C4 CLKIN C4 C2 C7 C9 BCLKO C8 C8 Note: Input and output AC timing specifications are measured to CLKIN with a 50-pF load capacitance (not including pin capacitance). Figure 20-4. Clock Timing Figure 20-5 shows PSTCLK timings for parameters listed in Table 20-5. Chapter 20. Electrical Specifications 20-5 Input/Output AC Timing Specifications C5 C6 PSTCLK C6 Figure 20-5. PSTCLK Timing 20.3 Input/Output AC Timing Specifications Table 20-6 lists specifications for parameters shown in Figure 20-6 and Figure 20-7. Note that inputs IRQ[7,5,3,1], BKPT, and AS are synchronized internally; that is, the logic level is validated if the value does not change for two consecutive rising CLKIN edges. Setup and hold times must be met only if recognition on a particular clock edge is required. Table 20-6. Input AC Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max B1 1 Valid to CLKIN rising (setup) 7.5 -- nS B2 1 CLKIN rising to invalid (hold) 1.0 -- nS 2 Valid to CLKIN rising (setup) 0 -- nS B4 2 CLKIN rising to invalid (hold) 0.5(C1) + 1.3 -- nS B5 3 CLKIN to input high impedance -- 2 Bus clock B6 CLKIN to EDGESEL delay 0 5.0 nS B3 1 Inputs: BG, TA, A[23:0], PP[15:0], SIZ[1:0], R/W, TS, EDGESEL, D[31:0], IRQ[7,5,3,1], and BKPT 2 Inputs: AS 3 Inputs: D[31:0] Table 20-7 lists specifications for timings in Figure 20-6, Figure 20-7, and Figure 20-13. Although output signals that share a specification number have approximately the same timing, due to loading differences, they do not necessarily change at the same time. However, they have similar timings; that is, minimum and maximum times are not mixed. Table 20-7. Output AC Timing Specification Num 54 MHz CLKIN Characteristic Min 20-6 B10 1,2,3 CLKIN rising to valid B11 3,4,5 CLKIN rising to invalid (hold) B12 6,7 CLKIN to high impedance (three-state) Units Max -- 84 nS -- 10 5 nS 1.0 5 -- nS -- 10 nS MCF5407 User's Manual Input/Output AC Timing Specifications Table 20-7. Output AC Timing Specification (Continued) Num 54 MHz CLKIN Characteristic Units Min Max -- 0.5(C1) +8.0 9 nS -- 0.5(C1) +10.0 10 nS 0.5(C1) + 1.0 -- nS -- 12 nS B13 8,2,3 CLKIN rising to valid B14 8,2,3 CLKIN rising to invalid (hold) B15 2,3 EDGESEL to valid B16 2,3 EDGESEL to invalid (hold) 2 -- nS H1 HIZ to high impedance -- 60 nS H2 HIZ to low Impedance -- 60 nS 1 2 3 4 5 6 7 8 9 10 Outputs that change only on rising edge of CLKIN: RSTO, TS, BR, BD, TA, R/W, SIZ[1:0], PP[7:0] (and PP[15:8] when configured as parallel port outputs). Outputs that can change on either CLKIN edge depending only on EDGESEL: D[31:0], A[23:0], SCKE, SRAS, SCAS, and DRAMW and on PP[15:8] when individually configured as A[31:24] outputs. Outputs that can change on either CLKIN edge depending upon EDGESEL and the interface operating mode (DRAM/SDRAM): RAS[1:0], CAS[3:0] SRAS, SCAS, DRAMW, RAS[1:0], CAS[3:0] D[31:0], A[23:0], TM[2:0], TT[1:0], SIZ[1:0], R/W, TIP, TS, BR, BD, and TA and PP[15:8] when individually configured as A[31:24] outputs. High impedance (three-state): D[31:0] Outputs that transition to high impedance due to bus arbitration: A[23:0], R/W, SIZ[1:0], TS, AS, and TA, and PP[15:8] when individually configured as A[31:24] outputs. Outputs that change only on falling edge of CLKIN: AS, CS[7:0], BE[3:0], OE SRAS, SCAS, DRAMW, RAS[1:0], CAS[3:0], AS, CS[7:0], BE[3:0], OE D[31:0], A[23:0], TM[2:0], TT[1:0], SIZ[1:0], R/W, TIP, and TS and on PP[15:8] when individually configured as A[31:24] outputs. Note that these figures show two representative bus operations and do not attempt to show all cases. For explanations of the states, S0-S5, see Section 18.4, "Data Transfer Operation." Note that Figure 20-7 does not show all signals that apply to each timing specification. See the previous tables for a complete listing. Figure 20-6 shows AC timings for normal read and write bus cycles. Chapter 20. Electrical Specifications 20-7 Input/Output AC Timing Specifications S0 CLKIN S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 B11 B10 A[31:0] TM[2:0] TT[1:0] SIZ[1:0] R/W B11 TS TIP B14 B13 AS, CS, OE BE/BWE[3:0] B12 B2 B10 D[31:0] B1 B5 TA Figure 20-6. AC Timings--Normal Read and Write Bus Cycles Figure 20-7 shows timings for a read cycle with EDGESEL tied to buffered CLKIN. 20-8 MCF5407 User's Manual Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLKIN B6 EDGESEL B15 Row A[31:0] Column TS B16 SRAS B15 SCAS 1 B16 DRAMW B1 D[31:0] B16 B2 RAS B16 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL NOP =2 Figure 20-7. SDRAM Read Cycle with EDGESEL Tied to Buffered CLKIN Figure 20-8 shows an SDRAM write cycle with EDGESEL tied to buffered CLKIN. Chapter 20. Electrical Specifications 20-9 Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKIN B6 EDGESEL B15 Row A[31:0] Column TS B16 SRAS B15 SCAS 1 B16 DRAMW B15 D[31:0] B16 RAS B16 CAS NOP ACTV 1 DACR[CASL] WRITE NOP PALL =2 Figure 20-8. SDRAM Write Cycle with EDGESEL Tied to Buffered CLKIN Figure 20-9 shows an SDRAM read cycle with EDGESEL tied high. 20-10 MCF5407 User's Manual Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLKIN B10 Row A[31:0] Column TS B11 SRAS B10 SCAS 1 B11 DRAMW B1 D[31:0] B11 B2 RAS B11 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL =2 Figure 20-9. SDRAM Read Cycle with EDGESEL Tied High Figure 20-10 shows an SDRAM write cycle with EDGESEL tied high. Chapter 20. Electrical Specifications 20-11 Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKIN B10 Row A[31:0] Column TS B11 SRAS B10 SCAS1 B11 DRAMW B10 D[31:0] B11 RAS B11 CAS ACTV 1 DACR[CASL] NOP WRITE NOP PALL =2 Figure 20-10. SDRAM Write Cycle with EDGESEL Tied High Figure 20-11 shows an SDRAM read cycle with EDGESEL tied low. 20-12 MCF5407 User's Manual Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLKIN B13 Row A[31:0] Column TS B14 SRAS B13 SCAS1 B14 DRAMW B1 D[31:0] B14 B2 RAS B14 CAS ACTV 1 DACR[CASL] NOP READ NOP NOP PALL =2 Figure 20-11. SDRAM Read Cycle with EDGESEL Tied Low Figure 20-12 shows an SDRAM write cycle with EDGESEL tied low. Chapter 20. Electrical Specifications 20-13 Input/Output AC Timing Specifications 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKIN B13 Row A[31:0] Column TS B14 SRAS B13 SCAS1 B14 DRAMW B13 D[31:0] B14 RAS B14 CAS ACTV 1 DACR[CASL] NOP WRITE NOP PALL =2 Figure 20-12. SDRAM Write Cycle with EDGESEL Tied Low Figure 20-13 shows AC timing showing high impedance. HIZ H1 OUTPUTS Figure 20-13. AC Output Timing--High Impedance 20-14 MCF5407 User's Manual H2 Reset Timing Specifications 20.4 Reset Timing Specifications Table 20-8 lists specifications for the reset timing parameters shown in Figure 20-14. Table 20-8. Reset Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max R1 1 Valid to CLKIN (setup) 7.5 -- nS R2 CLKIN to invalid (hold) 1.0 -- nS R3 RSTI to invalid (hold) 1.0 -- nS 1 RSTI and D[7:0] are synchronized internally. Setup and hold times must be met only if recognition on a particular clock is required. Figure 20-14 shows reset timing for the values in Table 20-8. CLKIN R1 RSTI R2 D[7:0] R1 R3 Note: Mode selects are registered on the rising CLKIN edge before the cycle in which RSTI is recognized as being negated. Figure 20-14. Reset Timing Chapter 20. Electrical Specifications 20-15 Debug AC Timing Specifications 20.5 Debug AC Timing Specifications Table 20-9 lists specifications for the debug AC timing parameters shown in Figure 20-16. Table 20-9. Debug AC Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max D1 PSTDDATA to PSTCLK setup 4.5 -- nS D2 PSTCLK to PSTDDATA hold 4.5 -- nS D3 DSI-to-DSCLK setup 1 -- PSTCLKs D4 1 DSCLK-to-DSO hold 4 -- PSTCLKs D5 DSCLK cycle time 5 -- PSTCLKs 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK. Figure 20-15 shows real-time trace timing for the values in Table 20-9. PSTCLK D1 D2 PSTDDATA[7:0] Figure 20-15. Real-Time Trace AC Timing Figure 20-16 shows BDM serial port AC timing for the values in Table 20-9. PSTCLK D5 DSCLK D3 DSI Current Next D4 DSO Past Figure 20-16. BDM Serial Port AC Timing 20-16 MCF5407 User's Manual Current Timer Module AC Timing Specifications 20.6 Timer Module AC Timing Specifications Table 20-10 lists specifications for timer module AC timing parameters shown in Figure 20-17. Table 20-10. Timer Module AC Timing Specification 54 MHz CLKIN Num Characteristic Units Min Max T1 TIN cycle time 3 -- Bus clocks T2 TIN valid to CLKIN (input setup) 7.5 -- nS T3 CLKIN to TIN invalid (input hold) 1.0 -- nS T4 CLKIN to TOUT valid (output valid) -- 10 nS T5 CLKIN to TOUT invalid (output hold) 1.0 -- nS T6 TIN pulse width 1 -- Bus clocks T7 TOUT pulse width 1 -- Bus clocks Figure 20-17 shows timings for Table 20-10. CLKIN T6 TIN T2 T3 TIN T1 T7 TOUT T4 T5 Figure 20-17. Timer Module AC Timing Chapter 20. Electrical Specifications 20-17 I2C Input/Output Timing Specifications 20.7 I2C Input/Output Timing Specifications Table 20-11 lists specifications for the I2C input timing parameters shown in Figure 20-18. Table 20-11. I2C Input Timing Specifications between SCL and SDA 54 MHz CLKIN Num Characteristic Units Min Max I1 Start condition hold time 2 -- Bus clocks I2 Clock low period 8 -- Bus clocks I3 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) -- 1 mS I4 Data hold time 0 -- nS I5 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) -- 1 mS I6 Clock high time 4 -- Bus clocks I7 Data setup time 0 -- nS I8 Start condition setup time (for repeated start condition only) 2 -- Bus clocks I9 Stop condition setup time 2 -- Bus clocks Table 20-12 lists specifications for the I2C output timing parameters shown in Figure 20-18. Table 20-12. I2C Output Timing Specifications between SCL and SDA 54 MHz CLKIN Num I11 Characteristic Start condition hold time I21 Clock low period I3 2 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Units Min Max 6 -- Bus clocks Bus clocks 10 -- Note 2 Note 2 I4 1 Data hold time 7 -- I5 3 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) -- 3 nS I6 1 Clock high time 10 -- Bus clocks Bus clocks I7 1 Data setup time 2 -- Bus clocks I8 1 Start condition setup time (for repeated start condition only) 20 -- Bus clocks Stop condition setup time 10 -- Bus clocks I9 1 1 Programming IFDR with the maximum frequency (IFDR = 0x20) results in the minimum output timings listed here. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 20-18 shows timing for the values in Table 20-11 and Table 20-12. 20-18 MCF5407 User's Manual UART Module AC Timing Specifications I2 I6 I5 SCL I1 I4 I3 I8 I9 I7 SDA Figure 20-18. I2C Input/Output Timings 20.8 UART Module AC Timing Specifications Table 20-13 lists specifications for UART module AC timing parameters in Figure 20-19. Table 20-13. UART Module AC Timing Specifications 54 MHz CLKIN Num Characteristic Units Min Max U1 RXD valid to CLKIN (input setup) 7.5 -- U2 CLKIN to RXD invalid (input hold) 1.0 -- nS nS U3 CTS valid to CLKIN (input setup) 7.5 -- nS U4 CLKIN to CTS invalid (input hold) 1.0 -- nS U5 CLKIN to TXD valid (output valid) -- 10 nS U6 CLKIN to TXD invalid (output hold) 1.0 -- nS U7 CLKIN to RTS valid (output valid) -- 10 nS U8 CLKIN to RTS invalid (output hold) 1.0 -- nS U9 CTS high time 38 -- nS U10 CTS low time 38 -- nS U11 CTS rising to TxD valid -- 20 nS U12 RxD setup to CTS falling 10 -- nS U13 RxD hold from CTS falling -- 5 nS U14 TxD to RxD (remote loop back) -- 15 nS U15 TIN1 setup to CTS falling 10 -- nS U16 TIN1 hold from CTS falling -- 5 nS U17 CTS rising to RTS asserted -- 20 nS Figure 20-19 shows UART0 and UART1 timing for the values in Table 20-13. Chapter 20. Electrical Specifications 20-19 UART Module AC Timing Specifications CLKIN U1 RXD U2 U3 CTS U4 U5 TXD U6 U7 RTS U8 Figure 20-19. UART0 and UART1 Module AC Timing--UART Mode Figure 20-19 shows timing for UART1 in 8- and 16-bit CODEC mode. 20-20 MCF5407 User's Manual UART Module AC Timing Specifications U9 U10 CTS/ Serial bit clock U11 TxD U14 U12 U13 RxD TIN1/ Frame sync U15 U16 Figure 20-20. UART1 in 8- and 16-bit CODEC Mode Figure 20-21 shows timing for UART1 in AC `97 mode. U9 U10 CTS/ Bit clock U17 RTS/ Frame sync Figure 20-21. UART1 in AC `97 Mode Chapter 20. Electrical Specifications 20-21 Parallel Port (General-Purpose I/O) Timing Specifications 20.9 Parallel Port (General-Purpose I/O) Timing Specifications Table 20-14 lists specifications for general-purpose I/O timing parameters in Figure 20-22. Table 20-14. General-Purpose I/O Port AC Timing Specifications 54 MHz CLKIN Num Characteristic Units Min Max P1 PP valid to CLKIN (input setup) 7.5 -- nS P2 CLKIN to PP invalid (input hold) 1.0 -- nS P3 CLKIN to PP valid (output valid) -- 10 nS P4 CLKIN to PP invalid (output hold) 1.0 -- nS Figure 20-22 shows general-purpose I/O timing. CLKIN P1 PP IN P2 P3 PP OUT P4 Figure 20-22. General-Purpose I/O Timing 20-22 MCF5407 User's Manual DMA Timing Specifications 20.10 DMA Timing Specifications Table 20-14 lists specifications for DMA timing parameters shown in Figure 20-22. Table 20-15. DMA AC Timing Specifications 54 MHz CLKIN Num Characteristic Units Min Max M1 DREQ valid to CLKIN (input setup) 7.5 -- nS M2 CLKIN to DREQ invalid (input hold) 1.0 -- nS M3 CLKIN to DACK valid (output valid) -- 10 nS M4 CLKIN to DACK invalid (output hold) 1.0 -- nS Figure 20-23 shows DMA AC timing. CLKIN M1 DREQ M4 M2 M3 DACK Figure 20-23. DMA Timing Chapter 20. Electrical Specifications 20-23 IEEE 1149.1 (JTAG) AC Timing Specifications 20.11 IEEE 1149.1 (JTAG) AC Timing Specifications Table 20-16 lists specifications for JTAG AC timing parameters shown in Figure 20-24. Table 20-16. IEEE 1149.1 (JTAG) AC Timing Specifications Num Characteristic -- TCK frequency of operation Units Min Max 0 10 MHz nS J1 TCK cycle time 100 -- J2a TCK clock pulse high width (measured at 1.5 V) 40 -- nS J2b TCK clock pulse low width (measured at 1.5 V) 40 -- nS J3a TCK fall time (VIH = 2.4 V to VIL = 0.5V) -- 5 nS J3b TCK rise time (VIL = 0.5v to VIH = 2.4V) -- 5 nS J4 TDI, TMS to TCK rising (input setup) 10 -- nS J5 TCK rising to TDI, TMS invalid (hold) 15 -- nS J6 Boundary scan data valid to TCK (setup) 10 -- nS J7 TCK to boundary-scan data invalid (hold) 15 -- nS J8 TRST pulse width (asynchronous to clock edges) 15 -- -- J9 TCK falling to TDO valid (signal from driven or three-state) -- 30 nS J10 TCK falling to TDO high impedance -- 30 nS J11 TCK falling to boundary scan data valid (signal from driven or three-state) -- 30 nS J12 TCK falling to boundary scan data high impedance -- 30 nS Figure 20-24 shows JTAG timing. 20-24 All Frequencies MCF5407 User's Manual IEEE 1149.1 (JTAG) AC Timing Specifications J3a J1 TCK J2b J2a J3b J4 TDI, TMS J5 J6 BOUNDARY SCAN DATA INPUT J7 TRST J8 J9 TDO J10 BOUNDARY SCAN DATA OUTPUT J11 J12 Figure 20-24. IEEE 1149.1 (JTAG) AC Timing Chapter 20. Electrical Specifications 20-25 IEEE 1149.1 (JTAG) AC Timing Specifications 20-26 MCF5407 User's Manual Appendix A Migrating from the ColdFire MCF5307 to the MCF5407 This appendix highlights the differences between the MCF5307B and MCF5407. Users of the MCF5307 and MCF5307A should use this document in conjunction with the MCF5307 User's Manual Mask Set Addendum. For additional information, see the MCF5407 Integrated ColdFire Microprocessor Product Brief. A.1 Overview Customers using the integrated peripherals of the MCF5307 can access the same features on the MCF5407 with the added advantage of increased cache and RAM memories as well as an enhanced instruction set architecture (ISA), DMA, synchronous UART, and debug functionality. Decreased voltage requirements allow designers to take advantage of other low-voltage components on the board for an integrated, low-power system. To migrate designs from the MCF5307 to the MCF5407, note the minor differences between these code-compatible processors in the initialization code, power supplies, and clock inputs. This document describes the differences between the processors and outlines the steps to upgrade the design. Table A-1 is a quick reference chart of these differences. Table A-1. Differences between MCF5307 and MCF5407 Feature MCF5307 MCF5407 Reference Version core ColdFire Version 3 (V3) ColdFire Version 4 -- MIPS 70 MIPS at 90-MHz core clock 233 MIPS at 162-MHz core clock -- Instruction set Baseline ColdFire ISA Rev A is used in Version 2 and Version 3 core. ColdFire ISA Rev B which includes certain instruction enhancements and some instruction additions; V2/V3 ISA Rev A is upward-compatible with ISA Rev B. Section A.2, "Instruction Set Additions" Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-1 Instruction Set Additions Table A-1. Differences between MCF5307 and MCF5407 Feature Caches MCF5307 MCF5407 Reference 8-Kbyte unified cache 16-Kbyte instruction cache 8-Kbyte data cache Two cache access control registers (ACR0/ACR1) ACR0/ACR1 configure data space; ACR2/ACR3 configure instruction space 4-Kbyte SRAM Two independently configurable 2-Kbyte SRAMs No cache locking Ability to lock all or half of the caches to prevent instructions or data from being cast out. This is useful for deterministic code. DMA acknowledge assertion is encoded on TM[2:0]. DACK[1:0] multiplexed on TM[1:0] can be programmed as separate DMA acknowledge signals. DMA TM[2:0] encodings are different from MCF5307 DMA TM[2:0] encodings. DMA byte count register (BCR) can be programmed to be 16 or 24 bits. BCR is 24 bits only. UART Both UARTs have identical functionality. No support for synchronous mode. UART0 is identical to the MCF5307 UARTs; UART1 has been enhanced to provide synchronous operation and a CODEC interface for soft modem support. Section A.5, "UART Enhancements" Timing relationships All signal timing with respect to BCLKO; CLKIN rise time = 5 nS. All signal timings with respect to CLKIN (BCLKO support provides compatibility with MCF5307 designs.) Tighter negative edge bus specifications due to duty cycle; CLKIN rise time = 2 nS. Section A.6.1, "Phase-Locked Loop (PLL)," and Section A.6, "Timing Differences" Reset initialization Need to drive D[7:0]/ AA, PS[1:0], ADDR_CONFIG, FREQ[1:0], DIVIDE[1:0] Need to drive D[7:0]/AA, PS[1:0], ADDR_CONFIG, BE_CONFIG, DIVIDE[2:0] Section A.7, "Reset Initialization Modifications" Debug module Debug Revision B. Separate PST[3:0] and DDATA[3:0] Debug Revision C--Adds breakpoint registers, normal interrupt request service during debug, and combines debug signals into PSTDDATA[7:0] Section A.8, "Revision C Debug" Voltage input changes Drives minimum 2.4 V; accepts 5-V input Drives minimum 2.4 V; accepts 3.3-V input Requires 3.3-V operating voltage Requires 1.8-V and 3.3-V operating voltages Section A.9, "Voltage Input Changes" Standard MCF5307 pinout Compatible with MCF5307 pinout except for power-pad input assignment DMA modifications Pin assignment Section A.3, "Enhanced Memories" Section A.4, "On-Chip DMA Modifications" Section A.11, "Pin-Assignment Compatibility" A.2 Instruction Set Additions The MCF5407 implements Revision B (Rev B) of the ColdFire instruction set, which adds instructions and enhances existing ISA Revision A (Rev A) opcodes to support byte- and A-2 MCF5407 User's Manual Enhanced Memories word-sized operands and position-independent code. Existing MCF5307 code is completely upward compatible with the MCF5407. However, designers may incorporate the instruction set additions and enhancements, especially when upgrading 68K code that references 8- and 16-bit short operands. The following list summarizes new and enhanced instructions of Rev B ISA: * * New instructions: -- INTOUCH loads instructions one cache block at a time for use with cache locking. -- MOV3Q.L moves 3-bit immediate data to the destination location. -- MVS.{B,W} moves the sign-extended source operand to the destination register. -- MVZ.{B,W} zero-fills the source operand and moves it to the destination register. -- SATS.L updates bit 31 of the destination register depending on the CCR overflow bit. -- TAS.B tests and sets byte operand being addressed. Enhancements to existing Revision A instructions: -- Longword support for branch instructions (Bcc, BRA, BSR) -- Byte and word support for compare instructions (CMP, CMPI) -- Byte and longword support for MOVE where the source is of type #<data> and the destination is of type d16(Ax); that is, move.b #<data>, d16(Ax) Refer to Section 2.9, "ColdFire Instruction Set Architecture Enhancements" for details of these additions and enhancements. A.3 Enhanced Memories With the introduction of a Harvard memory architecture in the Version 4 core design, the MCF5407 has separate instruction and data caches. The 16-Kbyte instruction cache and 8-Kbyte data cache greatly improve performance on existing systems. On-chip RAMs are also provided to work with the caches. For more details see, Chapter 4, "Local Memory". The MCF5307 configuration contains an 8-Kbyte unified cache with a 4-Kbyte SRAM. Configuration registers for these memories include one cache control register (CACR), two access control registers (ACR0 and ACR1), and one RAM base address register (RAMBAR). With the enhanced memory sizes of the MCF5407, more configuration registers have been provided. The new MOVEC register map for the MCF5407 memory configuration registers is given in Table A-2. Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-3 On-Chip DMA Modifications Table A-2. MOVEC CPU Space Register Map Rc[1:0] 1 Register Definition 0x002 Cache control register (CACR) 0x004 Cache access control register 0 (ACR0; data cache) 0x005 Cache access control register 1 (ACR1; data cache) 0x006 Cache access control register 2 (ACR2; instruction cache) 0x007 Cache access control register 3 (ACR3; instruction cache) 0xC04 RAM base address register 0 (RAMBAR0) 1 0xC05 RAM base address register 1 (RAMBAR1) 1 Either or both of the RAMBAR registers can be configured for instructions or data through an additional bit, RAMBARn[D/I]. Note that the existing functionality has not changed; new registers and new bits in existing registers have been added to support the enhanced memories and control for the new branch cache. One of the two 2-Kbyte SRAMs can be dedicated to support the instruction cache, and the other can support the data cache. Many designs use one SRAM block as a system stack and the other to hold important interrupt service routines. The SRAM can also function as a ROM by programming it as a data block while loading configuration information to it and then reprogramming it as a read-only instruction block. The two MCF5407 SRAM blocks can be programmed to provide a contiguous 4-Kbyte memory map similar to the MCF5307's single contiguous 4-Kbyte SRAM. A.4 On-Chip DMA Modifications The MCF5407 integrates the four-channel DMA used in the MCF5307 with changes to pin multiplexing, DMA byte transfer count, and the encoding of transfer acknowledgement. The MCF5307 provides DMA acknowledgement encodings for channels 0 and 1 through the transfer modifier pins, TM[2:1], which are multiplexed with PP[4:3]. For clarification on MCF5307 signal multiplexing, see the pinout tables in the mechanical specifications chapter of the MCF5307 User's Manual. The MCF5307 also indicates a DMA single address access through transfer modifier pin TM0, multiplexed with PP2. For more details see, Chapter 12, "DMA Controller Module". When the pin assignment register (PAR) is programmed to enable the TM signals, the encodings listed in Table A-3 and Table A-4 are driven during transfers by the internal DMA channels of the MCF5307. The condition TT[1:0] = 01 indicates an access by either an internal DMA or an external device. Table A-3. TM[2:1] Encoding for MCF5307 Internal DMA as Master (TT = 01) TM[2:1] A-4 Transfer Modifier Encoding 00 DMA acknowledges negated 01 DMA acknowledge, channel 0 MCF5407 User's Manual UART Enhancements Table A-3. TM[2:1] Encoding for MCF5307 Internal DMA as Master (TT = 01) (ConTM[2:1] Transfer Modifier Encoding 10 DMA acknowledge, channel 1 11 Reserved Table A-4. TM0 Encoding for MCF5307 Internal DMA as Master (TT = 01) TM0 Transfer Modifier Encoding 0 Dual address access 1 Single address access Although the MCF5407 provides similar encodings on TM[2:0], dedicated DMA acknowledgement pins (DACK[1:0]) have been added. Thus, DACK[1:0] are now combined with PP[3:2]/TM[1:0], resulting in a three-to-one multiplexed signal, PP[3:2]/TM[1:0]/DACK[1:0]. TM2 is still multiplexed only with PP4. For further clarification on the multiplexing, see the pinout tables in Section A.11, "Pin-Assignment Compatibility." When properly connected, TM[2:0] can be used in MCF5407 designs as on MCF5307 designs or DACK[1:0] can be used for DMA transfers, as shown in Figure A-1. MCF5307 Function Pin Pin MCF5407 Function Single/dual cycle access TM0 TM0 DMA 0 acknowledge DMA 0 acknowledge configuration TM1 TM1 DMA 1 acknowledge DMA 1 acknowledge configuration TM2 TM2 Single/dual cycle access Figure A-1. MCF5307 to MCF5407 TM[2:0] Pin Remapping For further details see Section 12.2, "DMA Signal Description". Although TM[2:0] can still drive DMA access encoding, the bit positions of these encodings are different from the MCF5307. The MCF5407 encodes single-address accesses on TM2 when the PAR is set to enable the transfer modifier signal and an external master or DMA transfer is occurring. This encoding is driven by TM0 on the MCF5307. Again, more details can be found in Section 12.2, "DMA Signal Description". Designers who use MCF5307 DMA channels should also note that the MCF5407 DMA byte count registers (BCRs) for channels 0-3 exclusively support a 24-bit byte count. A 16-bit byte count register is no longer supported; therefore, MPARK[BCR24BIT] has been removed. A.5 UART Enhancements The MCF5407 contains two UARTs that act independently. One of the UARTs on the MCF5407 has been enhanced to provide synchronous operation and a CODEC interface for soft modem support. Each UART can be clocked by the system bus clock, eliminating the need for an external crystal. For more details see, Chapter 14, "UART Modules". Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-5 Timing Differences The UART module interfaces directly to the CPU as shown in Figure A-2. The UART module consists of the following major functional areas: * * * * Serial communication channel 16-bit timer for baud-rate generation Internal channel control logic Interrupt control logic UART Internal Channel Control Logic CTS Serial Communications Channel RTS RxD TxD System Integration Module (SIM) Interrupt Controller Interrupt Control Logic 16-Bit Timer for Baud-Rate Generation CLKIN or External clock (TIN) Figure A-2. Simplified Block Diagram In addition, UART1 has been enhanced to provide a CODEC interface for soft modem support. UART1 can be programmed to provide any one of the following functions: * * The original UART (identical to UART0) Three modem modes, (see Section 14.5.2.2, "Transmitter in Modem Mode (UART1) for more details)": -- An 8-bit CODEC interface -- A 16-bit CODEC interface -- An audio CODEC 97 (AC97) digital interface controller A.6 Timing Differences This section explains timing relationships within phase-locked loop registers. A.6.1 Phase-Locked Loop (PLL) The PLL for the MCF5407 is enhanced to support faster processor clock (PCLK) frequencies. The MCF5307 supports PCLK frequencies of 66.7 and 90 MHz with a clock input (CLKIN) of 1/2 PCLK. The MCF5407 offers a larger range of clock input ratios and a higher performance processor clock. For more details see Section 7.1.1, "PLL:PCLK Ratios" and Chapter 20, "Electrical Specifications". The MCF5407 PLL module is shown in Figure A-3. A-6 MCF5407 User's Manual Timing Differences CLKIN (to on-chip peripherals) BCLKO PCLK (to core) CLKIN DIVIDE[2:0] Debug Module /2 PLL RSTI RSTO Figure A-3. PLL Module PSTCLK (= PCLK/2) Similar to the MCF5307 functionality, the MCF5407 samples clock ratio encodings on the lower data bits of the bus at reset to determine the CLKIN-to-PCLK ratio at which the device runs. These bits are DIVIDE[1:0] on the MCF5307 and are multiplexed with data bits D[1:0]. Because the MCF5407 offers more divide ratio combinations than the MCF5307, three input bits, D[2:0]/DIVIDE[2:0], have been provided to offer more programming options at reset. Also, note that only specific CLKIN ranges are allowed for each divide ratio on the MCF5407. Table A-5 shows the new encodings. Note that they differ from the MCF5307 DIVIDE[1:0] encodings. Table A-5. Divide Ratio Encodings D[2:0]/DIVIDE[2:0] Multiplier 00x-010 Reserved 011 3 100 4 101 5 110 6 111 Reserved A.6.2 Timing Relationships For both the MCF5307 and MCF5407, the user provides the clock input signal (CLKIN), which is also used for on-chip peripherals, as shown in Figure A-3. This signal is also the reference from which other clock frequencies are derived, including the bus clock output signal (BCLKO), which on the MCF5407 is provided for compatibility with MCF5307 designs. BCLKO is generated by the PLL and MCF5307 designs should use BCLKO as the bus timing reference for external devices; MCF5407 designs should use CLKIN. On the MCF5407, the CLKIN frequency can be 1/3, 1/4, 1/5, or 1/6 of the PCLK. Furthermore, depending on the MCF5307 configuration, the BCLKO-to-PCLK ratio may not be the same as the CLKIN-to-PCLK ratio. For more details see Section 20.2, "Clock Timing Specifications". On the MCF5407, the user-provided CLKIN should be used as the bus clock for the system. Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-7 Reset Initialization Modifications BCLKO runs at the same frequency as CLKIN and is offered as an optional timing reference for backwards compatibility for lower-speed MCF5307 designs. Regardless of the CLKIN frequency driven at power-up, CLKIN and BCLKO have the same ratio value to PCLK. Although designers can use either BCLKO or CLKIN as a clock reference, Motorola recommends using CLKIN because it leaves more room to meet bus specifications than BCLKO, which is generated as a phase-aligned signal to CLKIN. An MCF5307 user should consider switching to a CLKIN reference clock when upgrading to the MCF5407 if board frequencies exceed 50 MHz. Although the CLKIN duty cycle remains the same for the MCF5307 and MCF5407, use caution when interfacing signals on the falling edge of CLKIN with only a 4-nS window at high frequencies. Also, note that the MCF5407 input rise time is reduced to 2 nS (5 nS in the MCF5307). For designers who choose to reference signals from CLKIN only, BCLKO can be disabled to save power. For details see Section 7.2.3, "Reduced-Power Mode". A.7 Reset Initialization Modifications Like the MCF5307, the MCF5407 samples a group of eight input signals, D[7:0], on the rising edge of CLKIN before the rising edge of RSTI to determine the reset configuration of the global chip select, the address bus, and PLL. However, unlike the MCF5307, the frequency range encodings are not sampled on D[3:2], which are replaced by two other reset configuration inputs. First, the CLKIN-to-PCLK ratio allows more combinations. This extra bit is now sampled on D2 so that the clock ratio programming bits encompass D[2:0]/DIVIDE[2:0]. Second, a new reset configuration bit, BE_CONFIG, is now multiplexed with D3 in the MCF5407. This bit enables the four byte enables for the global chip select, CS0, for reads and writes or writes only, depending on the bit value sampled at reset, as shown in Table A-10. Table A-6 shows the multiplexing of D[7:0] for the MCF5307 and the MCF5407. Table A-6. D[7:0] Multiplexing Data Pins MCF5307 MCF5407 D7 AA D[6:5] PS[1:0] D4 ADDR_CONFIG D3 FREQ1 BE_CONFIG, BE[3:0] D2 FREQ0 DIVIDE2 D1 DIVIDE1 D0 DIVIDE0 Table A-7 through Table A-10 list the various reset encodings for the configuration signals A-8 MCF5407 User's Manual Reset Initialization Modifications multiplexed with D[7:3]. See for D[2:0]/DIVIDE[2:0] encodings sampled at reset. Note that Table A-7 and Table A-8 configure the global, or boot, CS0 that is used to access boot ROM out of reset. CS0 is the only chip select active out of reset until other chip selects become valid. Both the wait states and port size of boot memory accessed by boot CS0 are programmed through these bits. Table A-7. D7/AA, Automatic Acknowledge of Boot CS0 D7/AA Boot CS0 AA Configuration at Reset 0 Disabled 1 Enabled with 15 wait states Table A-8 shows configurations for D[6:5]/PS[1:0]. Table A-8. D[6:5]/PS[1:0], Port Size of Boot CS0 D[6:5]/PS[1:0] Boot CS0 Port Size at Reset 00 32-bit port 01 8-bit port 1x 16-bit port Table A-9 initializes the pin assignment register of the parallel I/O port to be either parallel I/O or to be the upper address bus bits along with various attribute and control signals at reset to give the user the option to access a broader addressing range of memory, if desired. Table A-9. D4/ADDR_CONFIG, Address Pin Assignment D4/ADDR_CONFIG Configuration Pin Assignment Register at Reset 0 PP[15:0], defaulted to inputs upon reset 1 ADDR[31:24]/TIP/DREQ[1:0]/TM[2:1] Table A-10 shows configurations for D3/BE_CONFIG. Because some boot memories require byte enables to be active only during writes, the functionality of byte enables, BE[3:0], can be programmed at reset. Table A-10. D3/BE_CONFIG, BE[3:0] Boot Configuration D3/BE_CONFIG Configuration of Byte Enables for Boot CS0 0 BE[3:0] are enabled as byte write enables only 1 BE[3:0] are enabled as byte enables for reads and writes D[2:0]/DIVIDE[2:0] configurations are shown in Table A-5. After RSTI is negated, 32 bits of CPU configuration information are loaded into data register D0 and 32 bits of internal memory information are loaded in D1. Because these registers are completely uninitialized on previous ColdFire devices, this feature allows users to identify the MCF5407 through software. Values D1 = 0x0630_0530 and D0 = Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-9 Revision C Debug 0xCF4x_C012 identify the MCF5407, where x identifies the core revision number (0x1 for the initial device). A.8 Revision C Debug A number of enhancements to the original ColdFire debug functions were requested by customers and third-party tool developers. As a result, an expanded set of debug functions was implemented in the Version 4 ColdFire and named Revision C, or simply Debug C. Most of the enhancements are included in the MCF5407 debug module and are primarily related to improvements in the real-time debug capabilities. A.8.1 Debug Interrupts and Interrupt Requests in Emulator Mode In the Debug B ColdFire implementation of the MCF5307, the response to a user-defined breakpoint trigger can be configured as one of three possibilities: * * * The breakpoint trigger can be displayed on the PSTDDATA bus with no internal reaction to the trigger. The trigger state information is displayed on PSTDDATA in all situations. The breakpoint trigger can force the processor to halt and allow BDM activities. The breakpoint trigger can generate a special debug interrupt to allow real-time systems to quickly process the interrupt and return to normal system executing as rapidly as possible. The occurrence of a debug interrupt exception is treated as a special type of interrupt. It is considered to be higher in priority than all normal interrupt requests and has special processor status values to indicate externally that this interrupt occurred. Additionally, the execution of the debug interrupt service routine is forced to be interrupt-inhibited by the processor hardware. Optionally, it is capable of mapping all instruction and data references while in this service routine into a separate address space, so that an emulator can define the routine dynamically. Current processor implementations include a state bit, invisible to software, that defines this emulator mode of operation. Note that the interrupt mask level is not modified during the processing of a debug interrupt. In response to customers with real-time embedded systems asking for the ability to service normal interrupt requests while processing the debug interrupt service routine, this feature has been incorporated in the Revision C debug. To provide this function and service any number of normal interrupt requests, including the possibility of nested interrupts, the processor state signaling emulator mode is now included as part of the exception stack A-10 MCF5407 User's Manual Revision C Debug frame, shown in Figure A-4. 31 A7 + 0x04 28 Format 27 26 FS[3-2] 25 18 Vector[7-0] 17 16 15 FS[1-0] 0 Status Register Program counter[31:0] Figure A-4. Exception Stack Frame Form As part of the Debug C enhancement, the operation of the debug interrupt is modified as follows: * * * 1. 2. 3. 4. The occurrence of the breakpoint trigger, configured to generate a debug interrupt, is treated exactly as before. The debug interrupt is treated as a higher priority exception relative to the normal interrupt requests encoded on the interrupt priority input signals. At the appropriate sample point, the processor initiates debug interrupt exception processing. This event is signaled externally by the generation of a unique PST value (PST = 0xD) asserted for multiple cycles. The processor sets the emulator mode state bit as part of this processing. All normal interrupt requests are evaluated and sampled once per instruction during the debug interrupt service routine. If an exception is detected, the processor takes the following steps: In response to the new exception, the processor saves a copy of the current value of the emulator mode state bit and then exits emulator mode by clearing the actual state. The new exception stack frame sets bit 1 of the fault status field, using the saved emulator mode bit, indicating that execution while the processor is in emulator mode was interrupted. This corresponds to bit [17] of the longword at the top of the system stack. Control is passed to the appropriate exception handler. When the exception handler is complete, a Return From Exception (RTE) instruction is executed. During the processing of the RTE, the FS1 bit is reloaded from the system stack. If FS1 = 1, the processor sets the emulator mode state and resumes execution of the original debug interrupt service routine. This is signaled externally by the generation of the PST value that originally identified the occurrence of a debug interrupt exception, that is, PST = 0xD. Implementation of this revised debug interrupt handling fully supports the servicing of any number of normal interrupt requests while in a debug interrupt service routine. The emulator mode state bit is essentially changed to a program-visible value, stored into memory when the exception stack frame is created, and loaded from memory by the RTE instruction. Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-11 Revision C Debug A.8.2 On-Chip Breakpoint Registers The Debug B core debug module included three basic types of on-chip breakpoint registers: * * * A 32-bit PC breakpoint register and a 32-bit PC breakpoint mask Two 32-bit address registers, which can be used to specify a single address or a range of addresses A 32-bit data breakpoint register and a 32-bit data breakpoint mask The mask registers can be used to "don't care" the equivalent bits in the breakpoint registers. Additions to the breakpoint implementation are as follows: * * * Three more 32-bit PC breakpoint registers Two more 32-bit address registers (ABLR1, ABHR1) plus an attribute register (AATR1) and mask register, which can be used to specify a single address or a range of addresses One more 32-bit data breakpoint register and a 32-bit data breakpoint mask The addition of these new breakpoint registers also requires the appropriate control and configuration functions be added to the debug programming model. The affected BDM command and new register formats are described below. The revised BDM command is write debug module register (WDMREG). A.8.2.1 Write Debug Module Register (WDMREG) The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write operation. The debug module's programming model can be accessed either from the serial BDM communication channel or from the processor's execution of the supervisor-mode WDEBUG instruction. DSCLK must be inactive while WDEBUG executes. Figure A-5 defines the operand data format. 15 14 13 0x2 12 11 10 9 8 7 0xC 6 0x4 5 4 3 2 DRc D[31:16] D[15:0] Figure A-5. Write Debug Module Register Command (WDMREG) A-12 MCF5407 User's Manual 1 0 Revision C Debug Table A-11 describes the DRc encoding for the debug registers. Table A-11. Definition of DRc Encoding--Write DRc (hex) 0x00 0x01-0x04 Debug Register Definition Abbreviation Initial State (hex) CSR 0x0000 Configuration/Status -- -- 0x05 BDM address attributes BAAR 0x0005 0x06 Bus attributes and mask AATR 0x0005 0x07 Trigger definition TDR 0x0000 0x08 PC breakpoint PBR -- 0x09 PC breakpoint mask 0x0A-0x0B Reserved PBMR -- -- -- Reserved 0x0C Operand address high breakpoint ABHR -- 0x0D Operand address low breakpoint ABLR -- 0x0E Data breakpoint DBR -- 0x0F Data breakpoint mask 0x10-0x15 DBMR -- -- -- Reserved 0x16 Bus attributes and mask 1 AATR1 0x0005 0x17 Extended trigger definition XTDR 0x0000 0x18 PC breakpoint 1 PBR1 0x0000 0x19 Reserved 0x1A PC breakpoint 2 -- -- PBR2 0x0000 PBR3 0x0000 0x1B PC breakpoint 3 0x1C Operand address high breakpoint 1 ABHR1 -- 0x1D Operand address low breakpoint 1 ABLR1 -- 0x1E Data breakpoint 1 DBR1 -- 0x1F Data breakpoint mask 1 DBMR1 -- Command Sequence: WDMREG ??? MS DATA "NOT READY" LS DATA "NOT READY" XXX "ILLEGAL" NEXT CMD "NOT READY" NEXT CMD "CMD COMPLETE" Figure A-6. WDMREG Command Sequence Operand Data: Longword data is written into the specified debug register. Data is supplied most significant word first. Result Data: Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-13 Revision C Debug Command complete status (0x0FFFF) is returned when register write is complete. A.8.3 Debug Programming Model In addition to existing BDM commands that provide access to the processor's registers and the memory subsystem, the debug module contains a number of registers to support the required functionality. These registers are treated as 32-bit quantities, regardless of the number of bits in the implementation. The debug control registers (DRc) are addressed using a 5-bit value as part of two new BDM commands (WDREG and RDREG). These values are shown in Table A-11. These registers are also accessible from the processor's supervisor programming model through the execution of the WDEBUG instruction. Thus, the breakpoint hardware within the debug module can be accessed by the external development system using the serial interface or by the operating system running on the processor core. It is the software's responsibility to guarantee that all accesses to these resources are serialized and are logically consistent. The hardware provides a locking mechanism in the CSR to allow the external development system to disable any attempted writes by the processor to the breakpoint registers (setting IPW). The following sections describe the newly added breakpoint registers in Debug C. A.8.3.1 Address Breakpoint 1 Registers (ABLR1, ABHR1) The 32-bit address breakpoint 1 registers define an upper (ABHR1) and a lower (ABLR1) boundary for a region in the operand logical address space of the processor that can be used as part of the trigger. The ABLR1 and ABHR1 values are compared with the ColdFire CPU core address signals, as defined by the setting of the trigger definition register (TDR) and the extended trigger definition register (XTDR). A.8.3.2 Address Attribute Breakpoint Register 1 (AATR1) The address attribute breakpoint register 1 (AATR1) defines the address attributes and a mask associated with ABLR1 and ABHR1 to be matched in the trigger. The AATR1 value is compared with the ColdFire CPU core address attribute signals, as defined by the setting of the TDR and XTDR. The format of the AATR1 is the same as the AATR register. For more details about these registers see Section 5.4.1, "Address Attribute Trigger Registers (AATR, AATR1)". A.8.3.3 Program Counter Breakpoint Registers 1-3 (PBR1-PBR3) Each of the program counter (PC) breakpoint registers (PBR, PBR1-PBR3) defines an instruction address that can be used as part of the trigger. PBRn registers are compared with the processor's program counter register when the appropriate valid bit is asserted and TDR is configured appropriately. For more details about these registers see Section 5.4.6, "Program Counter Breakpoint/Mask Registers (PBR, PBR1, PBR2, PBR3, PBMR)". A-14 MCF5407 User's Manual Revision C Debug The results of all PC breakpoint registers, PBR/PBMR, PBR1, PBR2, and PBR3, are logically summed to form a single PC breakpoint trigger signal. * * PBRn[31:1] = program counter breakpoint address PBRn[0] = valid bit A.8.3.4 Data Breakpoint Register 1 (DBR1, DBMR1) The data breakpoint register 1 (DBR1) defines a specific data pattern that can be used as part of a trigger. The DBR1 value is masked by DBMR1, allowing only those bits in DBR1 that have a corresponding zero in DBMR1 to be compared with the ColdFire CPU core data signals, as defined in the TDR and the XTDR. The data breakpoint registers support both aligned and misaligned operand references. The relationship between the processor core address, the access size, and the corresponding location within the 32-bit core data bus is defined in the DBR and DBMR description. A.8.3.5 Extended Trigger Definition Register (XTDR) The XTDR enables the operation as defined by the new breakpoint registers, ABHR1, ABLR1, AATR1, DBR1, and DBMR1, within the debug module and operates in conjunction with the trigger definition register (TDR). The added breakpoint logic can be included as a one- or two-level trigger; XTDR[29-18] define second-level triggers and XTDR[13-2] define first-level triggers. The definition of the XTDR register is exactly the same as the TDR for the control of the ABHR1, ABLR1, DBR1 and DBMR1 breakpoint registers. The XTDR is cleared on reset. For more details about this register see Section 5.4.8, "Extended Trigger Definition Register (XTDR)". A.8.4 Debug Interrupt Exception Vectors In the Debug B revision, if the occurrence of a hardware breakpoint is configured to generate a debug interrupt, this exception is mapped to vector number 12 (0x030). The actual debug interrupts can be broadly classified into two groups--PC breakpoints and all other types. A PC breakpoint is treated in a precise manner--exception recognition and processing are initiated before the instruction at the given address is executed. Conversely, all other breakpoint events are recognized on the given internal bus transaction, but are made pending to the processor and sampled like other interrupt conditions. As a result, these types of interrupts are imprecise by nature. In response to a customer request that PC breakpoints be distinguishable from other type of trigger events, the debug interrupt exception vector is expanded in Debug C of the MCF5407 to two unique entries, shown in Table A-12, where the occurrence of a PC breakpoint generates the 0x034 vector. In the case of a two-level trigger, the last breakpoint event determines the exception vector. Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-15 Revision C Debug Table A-12. Debug C Exception Vector Assignments Vector Vector Offset Stacked Program Counter Assignment 12 0x030 Next Non-PC-breakpoint debug interrupt 13 0x034 Next PC-breakpoint debug Interrupt A.8.5 Processor Status and Debug Data Output Signals The Debug B architecture defines processor status, PST[3:0] and debug data DDATA[3:0] signals, which provide information to support real-time trace. In the Debug B design, these signals are output at the processor frequency. For the Debug C definition, however, the PST and DDATA are combined and redefined to operate at half the processor's operating frequency (provided by PSTCLK). Therefore, PSTDDATA[7:0] are used to output both processor status and captured debug data values. For more details, including single-cycle instruction timing examples, see Section 5.2.1, "Processor Status/Debug Data (PSTDDATA[7:0])." A PST marker and its data display are transmitted contiguously. Except for this transmission, the IDLE status (0x0) may appear any time. Again, given the real-time trace information appears as a sequence of 4-bit values, there are no alignment restrictions. That is, PST values and operands may appear on either nibble of PSTDDATA. In Debug B, the DDATA outputs display the status of the internal breakpoint registers when they are not displaying captured data values. For the Debug C design, any change to this breakpoint state is identified by a PST marker and then the new state value. Specifically, the marker for this breakpoint state change is a single assertion of the value 0xD. Usually, the 0xD status is asserted for multiple cycles, indicating entry into emulator mode in response to a debug interrupt exception. For Debug C, the posting of the 0xD status can signal multiple events, based on the next value. if the PSTDDATA stream includes {0xD, 0x2} then Breakpoint state changed to Waiting for Level 1 Trigger if the PSTDDATA stream includes {0xD, 0x4} then Breakpoint state changed to Level 1 Breakpoint Triggered if the PSTDDATA stream includes {0xD, 0xA} then Breakpoint state changed to Waiting for Level 2 Trigger if the PSTDDATA stream includes {0xD, 0xC} then Breakpoint state changed to Level 2 Breakpoint Triggered if the PSTDDATA stream includes {0xD, 0xD} then Entry into Emulator Mode Table A-13 shows the revised definition of the processor status encodings, where the values of {0xC-0xF} are usually asserted for multiple cycles. The behavior of the 0xD value was described previously. The PSTDDATA values of 0x2 and 0x6 are formerly reserved values now needed to support the Version 4 operand execution pipeline. A-16 MCF5407 User's Manual Voltage Input Changes Table A-13. Version 4 Debug C Processor Status Encodings PSTDDATA Value Definition 0x0 Continue execution 0x1 Begin execution of one instruction 0x2 Begin execution of two instructions 0x3 Entry into user-mode 0x4 Begin execution of PULSE or WDDATA instruction 0x5 Begin execution of taken branch 0x6 Begin execution of an instruction plus a taken branch 0x7 Begin execution of RTE instruction 0x8 Begin 1-byte data transfer on PSTDDATA 0x9 Begin 2-byte data transfer on PSTDDATA 0xA Begin 3-byte data transfer on PSTDDATA 0xB Begin 4-byte data transfer on PSTDDATA 0xC Exception processing 0xD Breakpoint state change, or entry into emulator mode 0xE Processor is stopped, waiting for interrupt 0xF Processor is halted A.8.6 Debug C Summary The preceding section describes additional functionality requested by ColdFire customers and third-party developers. The Debug C enhancements are designed to retain backward compatibility with the previous definition. A.9 Voltage Input Changes Although the MCF5407 logic operates at 1.8 V, the device pads are standard TTL-compatible and therefore can drive a 2.4-V minimum output and accepts a 3.3-V input. Thus, the MCF5407 requires both 1.8- and 3.3-V power supplies. This specification differs from the MCF5307, which operates at 3.3 V with 5-V-tolerant I/O pads. Although the power and ground pin assignment are the same for both the MCF5307 and MCF5407, the power pin allocation of the MCF5407 is divided between 1.8- and 3.3-V supply levels. Thus, two power rails are necessary to supply power to the MCF5407. Note that the MCF5407 meets the EIA/JEDEC standard for 1.8-V power supply voltage and interface requirements. See the JEDEC standard (EIA/JESD8-7, February 1997). A.10 PLL Power Supply Filter Circuit To ensure PLL stability, the power supply to the PLL power pin should be filtered using a Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407 A-17 Pin-Assignment Compatibility circuit similar to the one shown in Figure A-7. The circuit should be as close as possible to the PLL power pin to ensure maximum noise filtering. This filter design can be used for both the MCF5307 and MCF5407. . Vdd 10 PLL power pin 10 F 0.1 F Figure A-7. PLL Power Supply Filter Circuit A.11 Pin-Assignment Compatibility The MCF5407 pinout is identical to the MCF5307 except for the power pin allocation and PSTDDATA[7:0], which make available the contents of processor status, PST[3:0], and debug data, DDATA[3:0]. Therefore, when designing-in the MCF5407, note which power pins require 1.8 V and which require 3.3 V. The MCF5407 footprint is the same as the MCF5307, which is a 208-pin plastic quad flat pack (QFP). A-18 MCF5407 User's Manual Appendix B List of Memory Maps Table B-1. SIM Registers MBAR Offset 0x000 0x004 [31:24] [23:16] [15:8] [7:0] Reset status register (RSR) [p. 6-5] System protection control register (SYPCR) [p. 6-8] Software watchdog interrupt vector register (SWIVR) [p. 6-9] Software watchdog service register (SWSR) [p. 6-9] Interrupt port assignment register (IRQPAR) [p. 9-7] Reserved Pin assignment register (PAR) [p. 6-10] 0x008 PLL control (PLLCR) [p. 7-3] Reserved 0x00C Default bus master park register (MPARK) [p. 6-11] Reserved 0x010- 0x03C Reserved Table B-2. Interrupt Controller Registers MBAR Offset [31:24] [23:16] [15:8] [7:0] Interrupt Registers [p. 9-3] 0x040 Interrupt pending register (IPR) [p. 9-6] 0x044 Interrupt mask register (IMR) [p. 9-6] 0x048 Reserved Autovector register (AVR) [p. 9-5] Interrupt Control Registers (ICRs) [p. 9-3] 0x04C Software watchdog timer (ICR0) [p. 6-6] Timer0 (ICR1) [p. 9-2] Timer1 (ICR2) [p. 9-3] I2C (ICR3) [p. 9-3] 0x050 UART0 (ICR4) [p. 9-3] UART1 (ICR5) [p. 9-3] DMA0 (ICR6) [p. 9-3] DMA1 (ICR7) [p. 9-3] 0x054 DMA2 (ICR8) [p. 9-3] DMA3 (ICR9) [p. 9-3] Appendix B. List of Memory Maps Reserved B-1 Table B-3. Chip-Select Registers MBAR Offset 0x080 0x084 [31:24] [23:16] [15:8] [7:0] Reserved1 Chip-select address register--bank 0 (CSAR0) [p. 10-6] Chip-select mask register--bank 0 (CSMR0) [p. 10-7] 0x088 Reserved1 Chip-select control register--bank 0 (CSCR0) [p. 10-8] 0x08C Chip-select address register--bank 1 (CSAR1) [p. 10-6] Reserved1 0x090 Chip-select mask register--bank 1 (CSMR1) [p. 10-7] 0x094 Reserved1 Chip-select control register--bank 1 (CSCR1) [p. 10-8] 0x098 Chip-select address register--bank 2 (CSAR2) [p. 10-6] Reserved1 0x09C Chip-select mask register--bank 2 (CSMR2) [p. 10-7] 0x0A0 Reserved1 Chip-select control register--bank 2 (CSCR2) [p. 10-8 0x0A4 Chip-select address register--bank 3 (CSAR3) [p. 10-6] Reserved1 0x0A8 Chip-select mask register--bank 3 (CSMR3) [p. 10-7] 0x0AC Reserved1 Chip-select control register--bank 3 (CSCR3) [p. 10-8] 0x0B0 Chip-select address register--bank 4 (CSAR4) [p. 10-6] Reserved1 0x0B4 Chip-select mask register--bank 4 (CSMR4) [p. 10-7] 0x0B8 Reserved1 Chip-select control register--bank 4 (CSCR4) [p. 10-8] 0x0BC Chip-select address register--bank 5 (CSAR5) [p. 10-6] Reserved1 0x0C0 Chip-select mask register--bank 5 (CSMR5) [p. 10-7] 0x0C4 Reserved Chip-select control register--bank 5 (CSCR5) [p. 10-8] 0x0C8 Chip-select address register--bank 6 (CSAR6) [p. 10-6] Reserved1 0x0CC Chip-select mask register--bank 6 (CSMR6) [p. 10-7] 0x0D0 Reserved1 Chip-select control register--bank 6 (CSCR6) [p. 10-8] 0x0D4 Chip-select address register--bank 7 (CSAR7) [p. 10-6] Reserved1 0x0D8 0x0DC B-2 Chip-select mask register--bank 7 (CSMR7) [p. 10-7] Reserved1 Chip-select control register--bank 7 (CSCR7) [p. 10-8 MCF5407 User's Manual Table B-3. Chip-Select Registers (Continued) MBAR Offset [31:24] [23:16] [15:8] [7:0] MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x080 0x084 Chip-select mask register--bank 0 (CSMR0) [p. 10-7] 0x088 Reserved1 Chip-select control register--bank 0 (CSCR0) [p. 10-8] 0x08C Chip-select address register--bank 1 (CSAR1) [p. 10-6] Reserved1 0x090 Chip-select mask register--bank 1 (CSMR1) [p. 10-7] 0x094 Reserved1 Chip-select control register--bank 1 (CSCR1) [p. 10-8] 0x098 Chip-select address register--bank 2 (CSAR2) [p. 10-6] Reserved1 0x09C Chip-select mask register--bank 2 (CSMR2) [p. 10-7] 0x0A0 Reserved1 Chip-select control register--bank 2 (CSCR2) [p. 10-8] 0x0A4 Chip-select address register--bank 3 (CSAR3) [p. 10-6] Reserved1 0x0A8 Chip-select mask register--bank 3 (CSMR3) [p. 10-7] 0x0AC Reserved1 Chip-select control register--bank 3 (CSCR3) [p. 10-8] 0x0B0 Chip-select address register--bank 4 (CSAR4) [p. 10-6] Reserved1 0x0B4 Chip-select mask register--bank 4 (CSMR4) [p. 10-7] Reserved1 0x0B8 1 Reserved1 Chip-select address register--bank 0 (CSAR0) [p. 10-6] Chip-select control register--bank 4 (CSCR4) [p. 10-8] Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect. Table B-4. DRAM Controller Registers MBAR Offset 0x100 [31:24] [23:16] [15:8] DRAM control register (DCR) [p. 11-3] [7:0] Reserved 0x104 Reserved 0x108 DRAM address and control register 0 (DACR0) [p. 11-3] 0x10C DRAM mask register block 0 (DMR0) [p. 11-3] 0x110 DRAM address and control register 1 (DACR1) [p. 11-3] 0x114 DRAM mask register block 1 (DMR1) [p. 11-3] Appendix B. List of Memory Maps B-3 Table B-5. General-Purpose Timer Registers MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x140 Timer 0 mode register (TMR0) [p. 13-3] 0x144 Timer 0 reference register (TRR0) [p. 13-4] Reserved 0x148 Timer 0 capture register (TCR0) [p. 13-4] Reserved 0x14C 0x150 Reserved Timer 0 counter (TCN0) [p. 13-5] Reserved Reserved Timer 0 event register (TER0) [p. 13-5] Reserved 0x180 Timer 1 mode register (TMR1) [p. 13-3] 0x184 Timer 1 reference register (TRR1) [p. 13-4] Reserved 0x188 Timer 1 capture register (TCR1) [p. 13-4] Reserved 0x18C 0x190 Reserved Timer 1 counter (TCN1) [p. 13-5] Reserved Reserved Timer 1 event register (TER1) [p. 13-5] Reserved Table B-6. UART0 Control Registers MBAR Offset [31:24] [23:16] UART0 Control Registers 0x1C0 UART mode registers1--(UMR1n) [p. 14-5], (UMR2n) [p. 14-7] -- 0x1C4 (Read) UART status registers--(USRn) [p. 14-10] -- (Write) UART clock-select register1--(UCSRn) [p. 14-12] -- (Read) Do not access2 -- 0x1C8 (Write) UART command -- registers--(UCRn) [p. 14-13] 0x1CC (Read) UART receiver buffers--(URBn) [p. 14-15] -- (Write) UART transmitter -- buffers--(UTBn) [p. 14-16] B-4 MCF5407 User's Manual [15:8] [7:0] Table B-6. UART0 Control Registers (Continued) MBAR Offset [31:24] [23:16] (Read) UART input port change registers--(UIPCRn) [p. 14-17] -- (Write) UART auxiliary control registers1--(UACRn) [p. 14-17] -- (Read) UART interrupt status registers--(UISRn) [p. 14-18] -- (Write) UART interrupt mask registers--(UIMRn) [p. 14-18] -- 0x1D8 UART divider upper registers--(UDUn) [p. 14-19] -- 0x1DC UART divider lower registers--(UDLn) [p. 14-19] -- 0x1E0- 0x1EC Do not access2 -- 0x1F0 UART interrupt vector register--(UIVRn) [p. 14-20] -- 0x1F4 (Read) UART input port registers--(UIPn) [p. 14-20] -- 0x1D0 0x1D4 2 -- 2 (Read) Do not access -- (Write) UART output port bit set command registers--(UOP1n3) [p. 14-21] -- (Write) Do not access 0x1F8 0x1FC (Read) Do not access 2 -- (Write) UART output port bit reset command registers--(UOP0n3) [p. 14-21] -- [15:8] [7:0] 1 UMR1n, UMR2n, UCSRn, and UACRn[BRG] should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. 2 This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. Appendix B. List of Memory Maps B-5 3 Address-triggered commands Table B-7. UART1 Control Registers MBAR Offset [31:24] [23:16] [15:8] [7:0] UART1 Control Registers 0x200 UART mode registers1--(UMR1n)[p. 14-5], (UMR2n) [p. 14-7 Rx FIFO threshold register--(RXLVL) [p. 14-8] Modem control register--(MODCTL) [p. 14-9] Tx FIFO threshold register--(TXLVL) [p. 14-10] 0x204 (Read) UART status registers--(USRn) [p. 14-10] -- (Read) Rx samples available register--(RSMP) [p. 14-12] (Read) Tx space available register--(TSPC) [p. 14-13] (Write) UART clock-select register1--(UCSRn) [p. 14-12] 0x208 (Read) Do not access2 -- (Write) UART command -- registers--(UCRn) [p. 14-13] 0x20C (Read) UART receiver buffers--(URBn) [p. 14-15] (Write) UART transmitter buffers--(UTBn) [p. 14-16] (Read) UART input port change registers--(UIPCRn) [p. 14-17] -- (Write) UART auxiliary control registers1--(UACRn) [p. 14-17] -- (Read) UART interrupt status registers--(UISRn) [p. 14-18] -- (Write) UART interrupt mask registers--(UIMRn) [p. 14-18] -- 0x218 UART divider upper registers--(UDUn) [p. 14-19] -- 0x21C UART divider lower registers--(UDLn) [p. 14-19] -- 0x220- 0x22C Do not access2 -- 0x210 0x214 B-6 MCF5407 User's Manual Table B-7. UART1 Control Registers (Continued) MBAR Offset [31:24] [23:16] 0x230 UART interrupt vector register--(UIVRn) [p. 14-20] -- 0x234 (Read) UART input port registers--(UIPn) [p. 14-20] -- 2 (Write) Do not access 0x238 2 [15:8] [7:0] -- (Read) Do not access -- (Write) UART output port bit set command registers--(UOP1n3) [p. 14-21] -- (Read) Do not access 2 -- (Write) UART output port bit reset command registers--(UOP0n3) [p. 14-21] -- 0x200 UART mode registers4--(UMR1n) [p. 14-5], (UMR2n) [p. 14-7] Rx FIFO threshold register--(RXLVL) [p. 14-10] (UART1 only) Modem control register--(MODCTL) [p. 14-9] (UART1 only) Tx FIFO threshold register--(TXLVL) [p. 14-10] (UART1 only) 0x204 (Read) UART status registers--(USRn) [p. 14-10] -- (Read) Rx samples available register--(RSMP) [p. 14-12] (UART1 only) (Read) Tx space available register--(TSPC) [p. 14-13] (UART1 only) 0x23C (Write) UART clock-select register1--(UCSRn) [p. 14-12] 1 UMR1n, UMR2n, UCSRn, and UACRn[BRG] should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. 2 This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed. 3 Address-triggered commands 4 UMR1n, UMR2n, UCSRn, and UACRn[BRG] should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. Table B-8. Parallel Port Memory Map MBAR Offset [31:24] [23:16] [15:8] [7:0] 0x244 Parallel port data direction register (PADDR) [p. 15-2] Reserved 0x248 Parallel port data register (PADAT) [p. 15-2] Reserved Appendix B. List of Memory Maps B-7 Table B-9. I2C Interface Memory Map MBAR Offset [31:24] [23:16] [15:8] 0x280 I2C address register (IADR) [p. 8-6] Reserved 0x284 I2C frequency divider register (IFDR) [p. 8-6] Reserved 0x288 I2C control register (I2CR) [p. 8-7] Reserved 0x28C I2C status register (I2SR) [p. 8-8] Reserved 0x290 I2C data I/O register (I2DR) [p. 8-9] Reserved [7:0] Table B-10. DMA Controller Registers MBAR Offset [31:24] [23:16] [15:8] 0x300 Source address register 0 (SAR0) [p. 12-7] 0x304 Destination address register 0 (DAR0) [p. 12-7] 0x308 DMA control register 0 (DCR0) [p. 12-8] 0x30C Reserved Byte count register 0 (BCR0) [p. 12-7] 0x310 DMA status register 0 (DSR0) [p. 12-10] Reserved 0x314 DMA interrupt vector register 0 (DIVR0) [p. 12-11] Reserved 0x340 Source address register 1 (SAR1) [p. 12-7] 0x344 Destination address register 1 (DAR1) [p. 12-7] 0x348 DMA control register 1 (DCR1) [p. 12-8] 0x34C Reserved Byte count register 1 (BCR1) [p. 12-7] 0x350 DMA status register 1 (DSR1) [p. 12-10] Reserved 0x354 DMA interrupt vector register 1 (DIVR1) [p. 12-11] Reserved 0x380 Source address register 2 (SAR2) [p. 12-7] 0x384 Destination address register 2 (DAR2) [p. 12-7] 0x388 DMA control register 2 (DCR2) [p. 12-8] 0x38C Reserved Byte count register 2 (BCR2) [p. 12-7] 0x390 DMA status register 2 (DSR2) [p. 12-10] Reserved B-8 MCF5407 User's Manual [7:0] Table B-10. DMA Controller Registers (Continued) MBAR Offset 0x394 [31:24] DMA interrupt vector register 2 (DIVR2) [p. 12-11] [23:16] [15:8] Reserved 0x3C0 Source address register 3 (SAR3) [p. 12-7] 0x3C4 Destination address register 3 (DAR3) [p. 12-7] 0x3C8 [7:0] DMA control register 3 (DCR3) [p. 12-8] 0x3CC Reserved Byte count register 3 (BCR3) [p. 12-7] 0x3D0 DMA status register 3 (DSR3) [p. 12-10] Reserved 0x3D4 DMA interrupt vector register 3 (DIVR3) [p. 12-11] Reserved Appendix B. List of Memory Maps B-9 B-10 MCF5407 User's Manual Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. A Architecture. A detailed specification of requirements for a processor or computer system. It does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible implementations. Autovector. A method of determining the starting address of the service routine by fetching the value from a lookup table internal to the processor instead of requesting the value from the system. B Branch folding. The replacement with target instructions of a branch instruction and any instructions along the not-taken path when a branch is either taken or predicted as taken. Branch prediction.The process of guessing whether a branch will be taken. Such predictions can be correct or incorrect; the term `predicted' as it is used here does not imply that the prediction is correct (successful). Branch resolution.The determination of whether a branch is taken or not taken. A branch is said to be resolved when the processor can determine which instruction path to take. If the branch is resolved as predicted, the instructions following the predicted branch that may have been speculatively executed can complete (see completion). If the branch is not resolved as predicted, instructions on the mispredicted path, and any results of speculative execution, are purged from the pipeline and fetching continues from the nonpredicted path. Burst. A multiple-beat data transfer. C Cache. High-speed memory containing recently accessed data and/or instructions (subset of main memory). Cache coherency. An attribute wherein an accurate and common view of memory is provided to all devices that share the same memory Glossary of Terms and Abbreviations Glossary-1 system. Caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor's cache. Cache flush. An operation that removes from a cache any data from a specified address range. This operation ensures that any modified data within the specified address range is written back to main memory. Cache line. The smallest unit of consecutive data or instructions that is stored in a cache. For ColdFire processors a line consists of 16 bytes. Caching-inhibited. A memory update policy in which the cache is bypassed and the load or store is performed to or from main memory. Cast outs. Cache lines that must be written to memory when a cache miss causes a cache line to be replaced. Clear. To cause a bit or bit field to register a value of zero. See also Set. Copyback. A cache memory update policy in which processor write cycles are directly written only to the cache. External memory is updated only indirectly, for example, when a modified cache line is cast out to make room for newer data. E Effective address (EA). The 32-bit address specified for an instruction. Exception. A condition encountered by the processor that requires special, supervisor-level processing. Exception handler. A software routine that executes when an exception is taken. Normally, the exception handler corrects the condition that caused the exception, or performs some other meaningful task (that may include aborting the program that caused the exception). The address for each exception handler is identified by an exception vector defined by the ColdFire architecture. F Fetch. The act of retrieving instructions from either the cache or main memory and making them available to the instruction unit. Flush. An operation that causes a modified cache line to be invalidated and the data to be written to memory. H Glossary-2 Harvard architecture. An architectural model featuring separate caches for instruction and data. MCF5407 User's Manual H I Illegal instructions. A class of instructions that are not implemented for a particular processor. These include instructions not defined by the ColdFire architecture. Implementation. A particular processor that conforms to the ColdFire architecture, but may differ from other architecture-compliant implementations for example in design, feature set, and implementation of optional features. The ColdFire architecture has many different implementations. Imprecise mode. A memory access mode that allows write accesses to a specified memory region to occur out of order. Instruction queue. A holding place for instructions fetched from the current instruction stream. Instruction latency. The total number of clock cycles necessary to execute an instruction and make the results of that instruction available. Interrupt. An asynchronous exception. On ColdFire processors, interrupts are a special case of exceptions. See also asynchronous exception. Invalid state. State of a cache entry that does not currently contain a valid copy of a cache line from memory. L L Least-significant bit (lsb). The bit of least value in an address, register, data element, or instruction encoding. Least-significant byte (LSB). The byte of least value in an address, register, data element, or instruction encoding. Longword. A 32-bit data element M Master. A device able to initiate data transfers on a bus. Bus mastering refers to a feature supported by some bus architectures that allow a controller connected to the bus to communicate directly with other devices on the bus without going through the CPU. Memory coherency. An aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory. Modified state. Cache state in which only one caching device has the valid data for that address. Glossary of Terms and Abbreviations Glossary-3 Most-significant bit (msb). The highest-order bit in an address, registers, data element, or instruction encoding. Most-significant byte (MSB). The highest-order byte in an address, registers, data element, or instruction encoding. N O P Nop. No-operation. A single-cycle operation that does not affect registers or generate bus activity. Overflow. An condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register(s). For example, if two 16-bit numbers are multiplied, the result may not be representable in 16 bits. Pipelining. A technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one completes. Precise mode. A memory access mode that ensures that all write accesses to a specified memory region occur in order. S Set (v) To write a nonzero value to a bit or bit field; the opposite of clear. The term `set' may also be used to generally describe the updating of a bit or bit field. Set (n). A subdivision of a cache. Cacheable data can be stored in a given location in any one of the sets, typically corresponding to its lowerorder address bits. Because several memory locations can map to the same location, cached data is typically placed in the set whose cache line corresponding to that address was used least recently. See Setassociativity. Set-associativity. Aspect of cache organization in which the cache space is divided into sections, called sets. The cache controller associates a particular main memory address with the contents of a particular set, or region, within the cache. Slave. The device addressed by a master device. The slave is identified in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure. Static branch prediction. Mechanism by which software (for example, compilers) can hint to the machine hardware about the direction a branch is likely to take. Glossary-4 MCF5407 User's Manual Superscalar machine. A machine that can issue multiple instructions concurrently from a conventional linear instruction stream. Supervisor mode. The privileged operation state of a processor. In supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. System memory. The physical memory available to a processor. T Tenure. A tenure consists of three phases: arbitration, transfer, termination. There can be separate address bus tenures and data bus tenures. Throughput. The measure of the number of instructions that are processed per clock cycle. Transfer termination. The successful or unsuccessful conclusion of a data transfer. U Underflow. A condition that occurs during arithmetic operations when the result cannot be represented accurately in the destination register. User mode. The operating state of a processor used typically by application software. In user mode, software can access only certain control registers and can access only user memory space. No privileged operations can be performed. V W Word. A 16-bit data element. Write-through. A cache memory update policy in which all processor write cycles are written to both the cache and memory. Glossary of Terms and Abbreviations Glossary-5 Glossary-6 MCF5407 User's Manual INDEX A C Addressing mode summary, 2-15 Arbitration between masters, 6-14 bus control, 6-11 for internal transfers, 6-12 Architecture Harvard memory, 2-6 instruction set additions, 2-18 enhancements, 2-36 Cache configuration register, 2-12 registers, access control, 2-12 Chip-select module 8-, 16-, and 32-bit port sizing, 10-4 enable signals, 17-15 operation, 10-2 general, 10-3 global, 10-4 overview, 10-1 registers, 10-5, 10-6, B-2 code example, 10-9 control, 10-8 mask, 10-7 signals, 10-1 Clock PLL control, 6-10 ColdFire core exception stack frame definition, A-11 features and enhancements, 2-1 Condition code register, 2-9 CPU STOP instruction, 6-10 B Branch acceleration, 2-4 Branch instruction execution timing, 2-30 Bus arbitration control, 6-11 Bus master park register, 6-11 Bus operation bus errors, 18-17 characteristics, 18-2 control signals, 18-1 data transfer back-to-back cycles, 18-10 burst cycles line read bus, 18-12 line transfers, 18-12 line write bus, 18-14 mixed port sizes, 18-15 overview, 18-11 cycle execution, 18-4 cycle states, 18-5 fast-termination cycles, 18-9 operation, 18-2 read cycle, 18-7 write cycle, 18-8 external master transfers general, 18-21 two-device arbitration protocol, 18-25 two-wire mode, 18-25 features, 18-1 interrupt exceptions, 18-17 misaligned operands, 18-16 reset operation master, 18-34 overview, 18-33 software watchdog, 18-35 D Data registers, A-13 Debug module enhancements, 2-6 system interface, 1-12 DMA controller module byte count registers, 12-7 programming model, 12-5 signal description, 12-2 source address registers, 12-7 transfer overview, 12-4 DRAM controller asynchronous mode signals, 11-4 asynchronous operation burst page mode, 11-12 continuous page mode, 11-13 extended data out, 11-15 general, 11-4 register set, 11-4 general guidelines, 11-8 non-page mode, 11-11 refresh operation, 11-16 registers, 11-3 Index Index-1 INDEX address and control, 11-5 mask, 11-7 signals, 17-16 synchronous operation, 11-16 address and control registers, 11-20 address multiplexing, 11-23 auto-refresh, 11-31 burst page mode, 11-27 continuous page mode, 11-29 controller signals, synchronous mode, 11-17 edge select, 11-18 general guidelines, 11-23 initialization, 11-32 interfacing, 11-27 mask registers, 11-22 mode register settings, 11-33 register set, 11-19 self-refresh, 11-32 E Electrical specifications cautions, 20-3 clock timing, 20-4 debug AC timing, 20-16 DMA timing, 20-23 general parameters, 20-1 I2C input/output timing, 20-18 input/output AC timing specifications, 20-6 JTAG AC timing, 20-24 parallel port timing, 20-22 reset timing, 20-15 timer module AC timing, 20-17 UART module AC timing, 20-19 Exception processing overview, 2-31 processor exceptions, 2-34 stack frame definition, 2-32 Execution timings miscellaneous, 2-29 one operand, 2-26 two operands, 2-27 F Features process, 1-7 summary, 1-4 H Harvard memory architecture, 2-6 I I2C Index-2 address register, 8-6 arbitration procedure, 8-4 clock stretching, 8-5 clock synchronization, 8-5 control register, 8-7 data I/O register, 8-9 features, 8-1 frequency divider register, 8-6 handshaking, 8-5 interface memory map, B-8 lost arbitration, 8-13 overview, 8-1 programming examples, 8-10 programming model, 8-6 protocol, 8-3 repeated START generation, 8-12 slave mode, 8-13 software response, 8-11 START generation, 8-10 status register, 8-8 STOP generation, 8-12 system configuration, 8-3 timing specifications, 20-18 IEEE Standard 1149.1 Test Access Port, see JTAG Instruction execution times, 2-29 Instruction set architecture additions, 2-18 architecture enhancements, 2-36 branch acceleration, 2-4 fetch pipeline, 2-4 MAC summary, 3-4 MAC unit execution times, 3-5 summary, 2-15, 2-19 Integer data formats, 2-13 Integer data formats in memory, 2-14 Integer data formats in registers, 2-13 Interrupt controller autovector register, 9-5 overview, 9-1 pending and mask registers, 9-6 port assignment register, 9-7 J JTAG AC timing, 20-24 obtaining IEEE Standard 1149.1, 19-11 overview, 19-1 registers boundary scan, 19-7 bypass, 19-10 descriptions, 19-4 IDCODE, 19-6 instruction shift, 19-5 restrictions, 19-10 MCF5407 User's Manual INDEX Pipelines, 2-2 instruction fetch, 2-4 operand execution, 2-4 PLL, 7-2 clock control for STOP, 6-10 clock frequency relationships, 7-4 clock-multiplied, 2-2 control register, 7-3 modes normal, 7-2 reduced power, 7-3 operation, 7-2 overview, 7-1 port list, 7-4 power supply filter circuit, 7-6 reset/initialization, 7-2 timing relationships, 7-4 Power supply filter circuit, 7-6 Program counter, 2-9 Programming models MAC, 2-10 overview, 2-7 registers, 1-15 SIM, 6-3 summary, B-1 supervisor, 2-10 user, 2-8 signal descriptions, 19-2 TAP controller, 19-3 test logic disabling, 19-10 M MAC data representation, 3-4 hardware support, 2-5 instruction execution timings, 3-5 instruction set summary, 3-4 operation, 3-3 programming model, 2-10, 3-2 Mask registers DRAM, 11-7, 11-22 MBAR, 6-4 Mechanical data, 16-1 case drawing, 16-9 diagram, 16-8 pinout, 16-1 Memory integer data formats, 2-14 SIM register, 6-3 Modules, 1-7 base address register, 2-12 core description, 1-7 debug, 2-6 DMA controller, 1-9 DRAM controller, 1-9 I2C, 1-11 PLL, 1-13 system interface, 1-11 16-bit parallel port, 1-12 chip selects, 1-11 debug, 1-12 external bus, 1-11 interrupt controller, 1-12 JTAG, 1-12 Timer, 1-11 UARTs, 1-10 MOVE instructions timing, 2-25 R RAM base address registers, 2-12 Registers A0-A6, 2-9 A7, 2-9 AATR, 5-10 access control, 2-12 address, 2-9 AVR, 9-5 BAAR, 5-12 bus master park, 6-11 cache configuration, 2-12 CACR, 2-12 CCR, 2-9 chip-select control, 10-8 mask, 10-7 module, 10-5 condition code, 2-9 CSR, 5-13 D0-D7, 2-8 data, 2-8, A-13 DMA byte count, 12-7 DMA source address, 12-7 DRAM O Opcodes illegal handling, 2-5 P Parallel port code example, 15-4 data direction register, 15-2 data register, 15-2 operation, 15-1 Pin assignment register, 6-10, 15-1 Index Index-3 INDEX asynchronous address and control, 11-5 DACR, 11-5 DCR, 11-4 DMR, 11-7 mode signals, 11-4 general operation, 11-3 synchronous DACR, 11-20 DCR, 11-19 DMR, 11-22 mode settings, 11-33 2 IC address, 8-6 control, 8-7 data I/O, 8-9 frequency divider, 8-6 status, 8-8 I2CR, 8-7 I2DR, 8-9 I2SR, 8-8 IADR, 8-6 IFDR, 8-6 integer data formats in, 2-13 interrupt controller autovector, 9-5 pending and mask, 9-6 port assignment, 9-7 IPR and IMR, 9-6 IRQPAR, 9-7 JTAG boundary scan, 19-7 bypass, 19-10 descriptions, 19-4 IDCODE, 19-6 instruction shift, 19-5 MBAR, 2-12, 6-4 MODCTL, 14-9 module base address, 2-12 MPARK, 6-11 PADAT, 15-2 PADDR, 15-2 PAR, 6-10, 15-1 parallel port data, 15-2 pin assignment, 15-1 PBR, 5-16 pin assignment, 6-10 PLL control, 7-3 PLLCR, 7-3 programming model, 1-15 RAM base address, 2-12 RAMBAR, 2-12 RAREG/RDREG, 5-30 Index-4 RCREG, 5-42 RDMREG, 5-44 reset status, 6-5 RSMP, 14-12 RSR, 6-5 RXLVL, 14-8 SDRAM mode initialization, 11-38 SIM base address, 6-4 memory map, 6-3 software watchdog interrupt, 6-9 SR, 2-11 status, 2-11 supervisor, 1-16, 1-16 SWIVR, 6-9 SWSR, 6-9 SYPCR, 6-8 system protection control, 6-8 TCR, 13-4 TDR, 5-18 TER, 13-5 timer module capture, 13-4 event, 13-5 mode, 13-3 reference, 13-4 TMR, 13-3 TSPC, 14-13 TXLVL, 14-10 UACR, 14-17 UART modules, 14-3-14-21 UCR, 14-13 UCSR, 14-12 UDU/UDL, 14-19 UIP, 14-20 UIPCR, 14-17 UISR, 14-18 UIVR, 14-20 user, 1-15 VB, 2-12 vector base, 2-12 WAREG/WDREG, 5-31 WCREG, 5-43 WDMREG, 5-45 XTDR, 5-19 RSTI timing, 7-5 S SDRAM block diagram and major components, 11-2 controller registers, B-3 DACR initialization, 11-35 DCR initialization, 11-35 definitions, 11-2 MCF5407 User's Manual INDEX interrupt request, 17-12 JTAG, 19-2 parallel I/O port, 17-19 read/write, 17-8 reset in, out, 17-13 serial module clear to Send, 17-19 general, 17-18 receiver serial data input, 17-19 request to send, 17-19 transmitter serial data output, 17-18 size, 17-8 timer module, 17-19 transfer acknowledge, 17-9 in progress, 17-10 modifier, 17-10 start, 17-9 Signals overview, 17-1 SIM features, 6-1 programming model, 6-3 register memory map, 6-3 Software watchdog interrupt vector register, 6-9 service register, 6-9 timer, 6-6 Stack pointer, 2-9, 2-9 Status register, 2-11 Supervisor programming model, 2-10 registers, 1-16 System protection control register, 6-8 DMR initialization, 11-37 example, 11-34 initialization code, 11-39 interface configuration, 11-34 mode register initialization, 11-38 overview, 11-1 Signal descriptions, 17-1 address bus, 17-7 address configuration, 17-15 address strobe, 17-9 bus arbitration, 17-12 clock output, 17-13 data, 17-8 driven, 17-13 grant, 17-12 request, 17-12 chip-select module, 17-15 clock and reset, 17-13 clock input, 17-13 data bus, 17-8 data/configuration pins, 17-14 debug high impedance, 17-20 JTAG, 17-21 processor clock output, 17-20 processor status debug data, 17-21 test clock, 17-22 mode, 17-20 overview, 17-20 debug module/JTAG test data input/development serial input, 17-22 test data output/development serial output, 17-22 test mode select/breakpoint, 17-21 test reset/development serial clock, 17-21 divide control, 17-15 DMA controller module general, 17-17 transfer modifier/acknowledge, 17-18 DRAM controller address strobes, 17-16 overview, 17-16 synchronous clock enable, 17-17 column address strobe, 17-17 edge select, 17-17 row address strobe, 17-17 synchronous edge select, 17-17 write, 17-16 I2C module general, 17-20 serial clock, 17-20 serial data, 17-20 interrupt control signals, 17-12 T Timer module calculating time-out values, 13-7 capture registers, 13-4 code example, 13-6 counters, 13-5 event registers, 13-5 general-purpose programming model, 13-2 general-purpose units, 13-2 mode registers, 13-3 reference registers, 13-4 Timing branch instruction execution, 2-30 MAC unit instructions, 3-5 MOVE instructions, 2-25 one operand, 2-26 PLL, 7-4 RSTI, 7-5 two operands, 2-27 Index Index-5 INDEX Transfers internally generated, 6-12 U UART Modules register description and programming register description UART module programming model (table 14-1), B-4 UART modules bus operation, 14-37 interrupt acknowledge cycles, 14-37 read cycles, 14-37 write cycles, 14-37 clock source baud rates, 14-24 controm registers, B-6 external clock, 14-25 FIFO stack in UART0, 14-32 initialization sequence, 14-38 looping modes, 14-34 automatic echo, 14-34 local loop-back, 14-34 remote loop-back mode, 14-35 mode registers, 14-5 multidrop mode, 14-35 programming, 14-37 receiver, 14-29 receiver in modem mode, 14-31 register descriptions, 14-3 serial overview, 14-2 signal definitions, 14-21 simplified block diagram, A-6 transmitter and receiver modes, 14-25 transmitter in modem mode, 14-27 transmitter/receiver clock source, 14-23 transmitting in UART mode, 14-26 UART1 in UART mode, 14-31 User registers, 1-15 V Vector base register, 2-12 Index-6 MCF5407 User's Manual Overview Part I: MCF5407 Processor Core 1 Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Part II SIM Overview 6 Phase-Locked Loop (PLL) 7 I2C Module 8 Interrupt Controller 9 Chip-Select Module 10 Synchronous/Asynchronous DRAM Controller Module 11 Part III: Peripheral Module Part III DMA Controller Module 12 Timer Module 13 UART Modules 14 Parallel Port (General-Purpose I/O) 15 Part IV: Hardware Interface Part IV Mechanical Data 16 Signal Descriptions 17 Bus Operation 18 IEEE 1149.1 Test Access Port (JTAG) 19 Electrical Specifications 20 Appendix A: Migration A Appendix B: Memory Map B Glossary of Terms and Abbreviations GLO Index IND IND B GLO IND 1 Part I Overview Part I: MCF5407 Processor Core 2 ColdFire Core 3 Hardware Multiply/Accumulate (MAC) Unit 4 Local Memory 5 Debug Support Part II Part II: System Integration Module (SIM) 6 SIM Overview 7 Phase-Locked Loop (PLL) 8 I2C Module 9 Interrupt Controller 10 Chip-Select Module 11 Synchronous/Asynchronous DRAM Controller Module Part III Part III: Peripheral Module 12 DMA Controller Module 13 Timer Module 14 UART Modules 15 Parallel Port (General-Purpose I/O) Part IV Part IV: Hardware Interface 16 Mechanical Data 17 Signal Descriptions 18 Bus Operation 19 IEEE 1149.1 Test Access Port (JTAG) 20 Electrical Specifications A Appendix A: Migration B Appendix B: Memory Map GLO Glossary of Terms and Abbreviations IND Index