SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
D
3-State Bus-Driving Outputs
D
Full Parallel Access for Loading
D
Buffered Control Inputs
D
Clock-Enable Input Has Hysteresis to
Improve Noise Rejection (’S373 and ’S374)
D
P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
description
These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The
high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . J OR W PACKAGE
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
SN74LS374 . . . DB, DW, N, OR NS PACKAGE
SN74S373 . . . DW OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OC
5Q
5D 8Q
4Q
GND
CVCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
C†
†C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
†C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
†
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
Tube SN74LS373N SN74LS373N
PDIP N
Tube SN74LS374N SN74LS374N
PDIP
–
N
Tube SN74S373N SN74S373N
Tube SN74S374N SN74S374N
Tube SN74LS373DW
LS373
Tape and reel SN74LS373DWR
LS373
Tube SN74LS374DW
LS374
0
°
Cto70
°
C
SOIC DW
Tape and reel SN74LS374DWR
LS374
0°C
to
70°C
SOIC
–
DW
Tube SN74S373DW
S373
Tape and reel SN74S373DWR
S373
Tube SN74S374DW
S374
Tape and reel SN74S374DWR
S374
Tape and reel SN74LS373NSR 74LS373
SOP – NS Tape and reel SN74LS374NSR 74LS374
Tape and reel SN74S374NSR 74S374
SSOP – DB Tape and reel SN74LS374DBR LS374A
Tube SN54LS373J SN54LS373J
Tube SNJ54LS373J SNJ54LS373J
Tube SN54LS374J SN54LS374J
CDIP J
Tube SNJ54LS374J SNJ54LS374J
CDIP
–
J
Tube SN54S373J SN54S373J
Tube SNJ54S373J SNJ54S373J
Tube SN54S374J SN54S374J
–55°C to 125°CTube SNJ54S374J SNJ54S374J
Tube SNJ54LS373W SNJ54LS373W
CFP – W Tube SNJ54LS374W SNJ54LS374W
Tube SNJ54S374W SNJ54S374W
Tube SNJ54LS373FK SNJ54LS373FK
LCCC FK
Tube SNJ54LS374FK SNJ54LS374FK
LCCC
–
FK
Tube SNJ54S373FK SNJ54S373FK
Tube SNJ54S374FK SNJ54S374FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
’LS373, ’S373
(each latch)
INPUTS OUTPUT
OC C D Q
L H H H
LHL L
LLX Q
0
H X X Z
’LS374, ’S374
(each latch)
INPUTS OUTPUT
OC CLK D Q
L↑H H
L↑LL
LLX Q
0
H X X Z
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagrams (positive logic)
OC
for ’S373 Only
1
11
32
C
1D
C1
1D 1Q
45
2D
C1
1D 2Q
76
3D
C1
1D 3Q
89
4D
C1
1D 4Q
13 12
5D
C1
1D 5Q
14 15
6D
C1
1D 6Q
17 16
7D
C1
1D 7Q
18 19
8D
C1
1D 8Q
Pin numbers shown are for DB, DW, J, N, NS, and W packages.
OC
for ’S374 Only
1
11
32
CLK
1D
C1
1D 1Q
45
2D 1D 2Q
76
3D 1D 3Q
89
4D 1D 4Q
13 12
5D 1D 5Q
14 15
6D 1D 6Q
17 16
7D 1D 7Q
18 19
8D 1D 8Q
’LS373, ’S373
T ransparent Latches ’LS374, ’S374
Positive-Edge-Triggered Flip-Flops
C1
C1
C1
C1
C1
C1
C1
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
Output
TYPICAL OF ALL OUTPUTS
VCC
100 Ω NOM
VCC
Req = 20 kΩ NOM
Input
Input
VCC
17 kΩ NOM
’LS373
EQUIVALENT OF DATA INPUTS EQUIVALENT OF ENABLE- AND
OUTPUT-CONTROL INPUTS
EQUIVALENT OF CLOCK- AND
OUTPUT-CONTROL INPUTS
’LS374
EQUIVALENT OF DATA INPUTS
30 kΩ NOM
Input
VCC
17 kΩ NOM
VCC
Input
Output
TYPICAL OF ALL OUTPUTS
VCC
100 Ω NOM
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
(’LS devices)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54LS’SN74LS’
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5 4.75 5 5.25 V
VOH High-level output voltage 5.5 5.5 V
IOH High-level output current –1–2.6 mA
IOL Low-level output current 12 24 mA
t
Pulse duration
CLK high 15 15
ns
t
w
Pulse
duration
CLK low 15 15
ns
t
Data setu
p
time
’LS373 5↓5↓
ns
t
su
Data
setup
time
’LS374 20↑20↑
ns
th
Data hold time
’LS373 20↓20↓
ns
t
h
Data
hold
time
’LS374‡5↑0↑
ns
TAOperating free-air temperature –55 125 0 70 °C
‡The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS’SN74LS’
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V
VOH
p
V
CC
= MIN, V
IH
= 2 V,
24
34
24
31
V
V
OH
-
CC ,
VIL = VIL max,
IH ,
IOH = MAX
2
.
4
3
.
4
2
.
4
3
.
1
V
VOL
p
V
CC
= MIN, V
IH
= 2 V, IOL = 12 mA 0.25 0.4 0.25 0.4
V
V
OL
-
CC ,
VIL = VIL max
IH ,
IOL = 24 mA 0.35 0.5
V
IOZH
Off-state output current, V
CC
= MAX, V
IH
= 2 V,
20
20
m
A
I
OZH
high-level voltage applied
CC ,
VO = 2.7 V
IH ,
20
20
m
A
IOZL
Off-state output current, V
CC
= MAX, V
IH
= 2 V,
20
20
m
A
I
OZL
low-level voltage applied
CC ,
VO = 0.4 V
IH ,
–
20
–
20
m
A
II
Input current at maximum
VCC = MAX
VI=7V
01
01
mA
I
Iinput voltage
V
CC =
MAX
,
V
I =
7
V
0
.
1
0
.
1
mA
IIH High-level input current VCC = MAX, VI = 2.7 V 20 20
m
A
IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA
IOS Short-circuit output current§VCC = MAX –30 –130 –30 –130 mA
ICC
pp
V
CC
= MAX, ’LS373 24 40 24 40
mA
I
CC
CC ,
Output control at 4.5 V ’LS374 27 40 27 40
mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER
FROM TO
TEST CONDITIONS
’LS373 ’LS374
UNIT
PARAMETER
(INPUT) (OUTPUT)
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
fmax RL = 667 Ω
,
CL = 45 pF,
See Note 3 35 50 MHz
tPLH
Data
Any Q
R
L
= 667 Ω
,
C
L
= 45 pF, 12 18
ns
tPHL
Data
Any
Q
L
,
L,
See Note 3 12 18
ns
tPLH
CorCLK
Any Q
R
L
= 667 Ω
,
C
L
= 45 pF, 20 30 15 28
ns
tPHL
C
or
CLK
Any
Q
L
,
L,
See Note 3 18 30 19 28
ns
tPZH
OC
Any Q
R
L
= 667 Ω
,
C
L
= 45 pF, 15 28 20 26
ns
tPZL
OC
Any
Q
L
,
L,
See Note 3 25 36 21 28
ns
tPHZ
15
25
15
28
t
PHZ
OC
Any Q
RL667 ΩCL5
p
F
15
25
15
28
ns
tPLZ
OC
An
y
Q
R
L =
667
Ω
,
C
L =
5
pF
12
20
12
20
ns
t
PLZ
12
20
12
20
NOTE 3: Maximum clock frequency is tested with all outputs loaded.
fmax = maximum clock frequency
tPLH = propagation delay time, low-to-high-level output
tPHL = propagation delay time, high-to-low-level output
tPZH = output enable time to high level
tPZL = output enable time to low level
tPHZ = output disable time from high level
tPLZ = output disable time from low level
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
Input
2.8 kΩ NOM
Output
TYPICAL OF ALL OUTPUTS
VCC
50 Ω NOM
’S373 and ’S374 ’S373 and ’S374
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
(’S devices)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54S’SN74S’
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VOH High-level output voltage 5.5 5.5 V
IOH High-level output current –2–6.5 mA
t
Pulse duration clock/enable
High 6 6
ns
t
w
Pulse
duration
,
clock/enable
Low 7.3 7.3
ns
t
Data setu
p
time
’S373 0↓0↓
ns
t
su
Data
setup
time
’S374 5↑5↑
ns
th
Data hold time
’S373 10↓10↓
ns
t
h
Data
hold
time
’S374 2↑2↑
ns
TAOperating free-air temperature –55 125 0 70 °C
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
VIH 2 V
VIL 0.8 V
VIK VCC = MIN, II = –18 mA –1.2 V
VOH
SN54S’
VCC = MIN
VIH =2V
VIL =08V
IOH = MAX
2.4 3.4
V
V
OH SN74S’
V
CC =
MIN
,
V
IH =
2
V
,
V
IL =
0
.
8
V
,
I
OH =
MAX
2.4 3.1
V
VOL VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.5 V
IOZH VCC = MAX, VIH = 2 V, VO = 2.4 V 50
m
A
IOZL VCC = MAX, VIH = 2 V, VO = 0.5 V –50
m
A
IIVCC = MAX, VI = 5.5 V 1 mA
IIH VCC = MAX, VI = 2.7 V 50
m
A
IIL VCC = MAX, VI = 0.5 V –250
m
A
IOS§VCC = MAX –40 –100 mA
Outputs high 160
’S373 Outputs low 160
Outputs disabled 190
ICC VCC = MAX Outputs high 110 mA
’
S374
Outputs low 140
’S374
Outputs disabled 160
CLK and OC at 4 V, D inputs at 0 V 180
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC= 5 V, TA = 25°C.
§Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)
PARAMETER
FROM TO
TEST CONDITIONS
’S373 ’S374
UNIT
PARAMETER
(INPUT) (OUTPUT)
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
fmax RL = 280 Ω
,
CL = 15 pF,
See Note 3 75 100 MHz
tPLH
Data
Any Q
R
L
= 280 Ω
,
C
L
= 15 pF, 7 12
ns
tPHL
Data
Any
Q
L
,
L,
See Note 3 7 12
ns
tPLH
CorCLK
Any Q
R
L
= 280 Ω
,
C
L
= 15 pF, 7 14 8 15
ns
tPHL
C
or
CLK
Any
Q
L
,
L,
See Note 3 12 18 11 17
ns
tPZH
OC
Any Q
R
L
= 280 Ω
,
C
L
= 15 pF, 8 15 8 15
ns
tPZL
OC
Any
Q
L
,
L,
See Note 3 11 18 11 18
ns
tPHZ
OC
Any Q
RL= 280 ΩCL=5
p
F
6 9 5 9
ns
tPLZ
OC
Any
Q
R
L =
280
Ω
,
C
L =
5
pF
8 12 7 12
ns
NOTE 3. Maximum clock frequency is tested with all outputs loaded.
fmax = maximum clock frequency
tPLH = propagation delay time, low-to-high-level output
tPHL = propagation delay time, high-to-low-level output
tPZH = output enable time to high level
tPZL = output enable time to low level
tPHZ = output disable time from high level
tPLZ = output disable time from low level
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
H. All parameters and waveforms are not applicable to all devices .
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tw
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOL
VOH
Figure 1. Load Circuits and Voltage Waveforms
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54S/74S DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
G. All parameters and waveforms are not applicable to all devices .
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
tw
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOH
VOL
Figure 2. Load Circuits and Voltage Waveforms
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL APPLICATION DATA
Bidirectional
Data Bus 2
Output
Control 2
Clock 2
Clock 1
Bidirectional
Data Bus 1
Output
Control 1
Clock 1
Clock 2
H
Bus
Exchange
Clock H
Clock Circuit for Bus Exchange
A
B
Expandable 4-W ord by 8-Bit General Register File
Enable Select
1/2 SN74LS139
or SN74S139
’LS374 or ’S374
’LS374 or ’S374
’LS374 or ’S374
’LS374 or ’S374
1/2 SN74LS139
or SN74S139
Y0
Y1
Y2
Y3
Y0 Y1 Y2 Y3
AB G
Clock
Select Clock
’LS374
or
’S374
’LS374
or
’S374
G
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C
C
Bidirectional Bus Driver
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-7801102VRA ACTIVE CDIP J 20 20 TBD A42 N / A for Pkg Type
5962-7801102VSA ACTIVE CFP W 20 25 TBD Call TI N / A for Pkg Type
78011022A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
7801102RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
7801102SA ACTIVE CFP W 20 1 TBD Call TI Call TI
JM38510/32502B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/32502BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
JM38510/32502BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
JM38510/32502SRA ACTIVE CDIP J 20 20 TBD A42 N / A for Pkg Type
JM38510/32502SSA ACTIVE CFP W 20 25 TBD Call TI N / A for Pkg Type
JM38510/32503B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/32503BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
JM38510/32503BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
M38510/32502B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
M38510/32502BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
M38510/32502BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
M38510/32502SRA ACTIVE CDIP J 20 20 TBD A42 N / A for Pkg Type
M38510/32502SSA ACTIVE CFP W 20 25 TBD Call TI N / A for Pkg Type
M38510/32503B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
M38510/32503BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
M38510/32503BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
SN54LS373J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN54LS374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN54S373J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN54S374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN74LS373DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS373DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LS373DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS373DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS373DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS373DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS373N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS373N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74LS373NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS373NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS373NSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS373NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374J OBSOLETE CDIP J 20 TBD Call TI Call TI
SN74LS374N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS374N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74LS374NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LS374NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374NSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS374NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74S373DW NRND SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74S373DWE4 NRND SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74S373DWG4 NRND SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74S373J OBSOLETE CDIP J 20 TBD Call TI Call TI
SN74S373N NRND PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74S373N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74S373NE4 NRND PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74S374J OBSOLETE CDIP J 20 TBD Call TI Call TI
SN74S374N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74S374N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74S374NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ54LS373FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LS373J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54LS373W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
SNJ54LS374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LS374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54LS374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
SNJ54S373FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54S373J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54S374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54S374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54S374W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 4
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LS373, SN54LS373-SP, SN54LS374, SN54LS374-SP, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373,
SN74S374 :
•Catalog: SN74LS373, SN54LS373, SN74LS374, SN54LS374, SN74S373, SN74S374
•Military: SN54LS373, SN54LS374, SN54S373, SN54S374
•Space: SN54LS373-SP, SN54LS374-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 5
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LS373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74LS373NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74LS374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LS374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74LS374NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS373DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LS373NSR SO NS 20 2000 367.0 367.0 45.0
SN74LS374DBR SSOP DB 20 2000 367.0 367.0 38.0
SN74LS374DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LS374NSR SO NS 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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