W3HG2128M64EEU-D4
January 2008
Rev. 7 1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
2GB – 2x128Mx64 DDR2 SDRAM SO-DIMM UNBUFFERED
DESCRIPTION
The W3HG2128M64EEU is a 2x128Mx64 Double Data
Rate DDR2 SDRAM high density SO-DIMM. This memory
module consists of sixteen 128Mx8 bit with 8 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
* This product is subject to change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
FEATURES
Unbuffered 200-pin, dual in-line memory module
(SO-DIMM). Raw card "E".
Fast data transfer rates: PC2-6400, PC2-5300,
PC2-4200 and PC2-3200
V
CC = 1.8V
V
CCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3, 4 and 5
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Dual Rank
RoHS compliant
JEDEC Package option
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-3200 PC2-4200 PC2-5300 PC2-6400 PC2-6400
Clock Speed 200MHz 266MHz 333MHz 400MHz 400MHz
CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 6-6-6 5-5-5
W3HG2128M64EEU-D4
January 2008
Rev. 7 2White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PIN CONFIGURATION
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
1V
REF 51 DQS2 101 A1 151 DQ42
2V
SS 52 DM2 102 A0 152 DQ46
3V
SS 53 VSS 103 VCC 153 DQ43
4 DQ4 54 VSS 104 VCC 154 DQ47
5 DQ0 55 DQ18 105 A10/AP 155 VSS
6 DQ5 56 DQ22 106 BA1 156 VSS
7 DQ1 57 DQ19 107 BA0 157 DQ48
8V
SS 58 DQ23 108 RAS# 158 DQ52
9V
SS 59 VSS 109 WE# 159 DQ49
10 DM0 60 VSS 110 CS0# 160 DQ53
11 DQS0# 61 DQ24 111 VCC 161 VSS
12 VSS 62 DQ28 112 VCC 162 VSS
13 DQS0 63 DQ25 113 CAS# 163 NC
14 DQ6 64 DQ29 114 ODT0 164 CK1
15 VSS 65 VSS 115 CS1# 165 VSS
16 DQ7 66 VSS 116 A13 166 CK1#
17 DQ2 67 DM3 117 VCC 167 DQS6#
18 VSS 68 DQS3# 118 VCC 168 VSS
19 DQ3 69 NC 119 ODT1 169 DQS6
20 DQ12 70 DQS3 120 NC 170 DM6
21 VSS 71 VSS 121 VSS 171 VSS
22 DQ13 72 VSS 122 VSS 172 VSS
23 DQ8 73 DQ26 123 DQ32 173 DQ50
24 VSS 74 DQ30 124 DQ36 174 DQ54
25 DQ9 75 DQ27 125 DQ33 175 DQ51
26 DM1 76 DQ31 126 DQ37 176 DQ55
27 VSS 77 VSS 127 VSS 177 VSS
28 VSS 78 VSS 128 VSS 178 VSS
29 DQS1# 79 CKE0 129 DQS4# 179 DQ56
30 CK0 80 CKE1 130 DM4 180 DQ60
31 DQS1 81 VCC 131 DQS4 181 DQ57
32 CK0# 82 VCC 132 VSS 182 DQ61
33 VSS 83 NC 133 VSS 183 VSS
34 VSS 84 NC 134 DQ38 184 VSS
35 DQ10 85 BA2 135 DQ34 185 DM7
36 DQ14 86 NC 136 DQ39 186 DQS7#
37 DQ11 87 VCC 137 DQ35 187 VSS
38 DQ15 88 VCC 138 VSS 188 DQS7
39 VSS 89 A12 139 VSS 189 DQ58
40 VSS 90 A11 140 DQ44 190 VSS
41 VSS 91 A9 141 DQ40 191 DQ59
42 VSS 92 A7 142 DQ45 192 DQ62
43 DQ16 93 A8 143 DQ41 193 VSS
44 DQ20 94 A6 144 VSS 194 DQ63
45 DQ17 95 VCC 145 VSS 195 SDA
46 DQ21 96 VCC 146 DQS5# 196 VSS
47 VSS 97 A5 147 DM5 197 SCL
48 VSS 98 A4 148 DQS5 198 SA0
49 DQS2# 99 A3 149 VSS 199 VCCSPD
50 NC 100 A2 150 VSS 200 SA1
PIN NAMES
Pin Name Function
CK0,CK1 Clock Inputs
CK0#, CK1# Clock Inputs Complement
CKE0, CKE1 Clock Enables
RAS# Row Address Strobe
CAS# Column Address Strobe
WE# Write Enable
CS0#, CS1# Chip Selects
A0-A13 Address Inputs
BA0 - BA2 Bank Address Inputs
ODT0,ODT1 On-die termination controls
DQ0-DQ63 Data Input/Output
DM0-DM7 Data Masks
DQS0-DQS7 Data strobes
DQS0#-DQS7# Data strobes complement
VCC Core and I/O Power
SDA SPD Data Input/Output
SCL (SPD) Clock Input
SA0, SA1 SPD address
VSS Ground
VREF Input/Output Reference voltage
VCCSPD SPD Power
NC Spare pins, No connect
W3HG2128M64EEU-D4
January 2008
Rev. 7 3White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
ODT0
CKE0
CS1#
ODT1
CKE1
SPD
SA0
SCL
SDA
V
SS
DDR2 SDRAMs, SPD
V
REF
DDR2 SDRAMs
DDR2 SDRAMs, V
CC,
V
CCQ
and V
CCL
V
CC
V
CC
SPD Serial PD
WP
SA1
SCL
A0
A1
A2
A0 - A13
RAS# DDR2 SDRAMs
CAS# DDR2 SDRAMs
WE# DDR2 SDRAMs
DDR2 SDRAMs
BA0 - BA2 DDR2 SDRAMs
3Ω ±5%
CS0#
DQS1
DQS1#
DM1
CS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS DQS5
DQS5#
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DM
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DQS#
DQS7
DQS7#
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DQS#
DM
O
D
T
C
K
E
CS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS
DQS#
O
D
T
C
K
E
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS#
DM
DQS
DQS#
DM
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
O
D
T
C
K
E
0
O
D
T
C
K
E
Notes :
1. All resistor values are 22 ohms unless otherwise specified
* Wire per Clock Loading
Table/Wiring Diagrams
* Clock Wiring
Clock Input DDR2 SDRAMs
CK0/CK0#
CK1/CK1#
8 DDR2 SDRAMs
8 DDR2 SDRAMs
10Ω ±5%
CS# CS#
CS#
DQS# DQS#
CS#
DQS# DQS#
CS# CS#
CS# CS# CS# CS#
CS# CS# CS# CS#
W3HG2128M64EEU-D4
January 2008
Rev. 7 4White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter Symbol
Rating
Units NotesMin. Typ. Max.
Supply Voltage VCC 1.7 1.8 1.9 V
I/O Reference Voltage VREF 0.49 x VCC 0.50 x VCC 0.51 x VCC V1
I/O Termination Voltage VTT VREF-0.04 VREF VREF+0.04 V 2
Notes:
1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Units
VCC Voltage on VCC pin relative to VSS -0.5 2.3 V
VIN, VOUT Voltage on any pin relative to VSS -0.5 2.3 V
TSTG Storage Temperature -55 100 ˚C
ILInput leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
Command/Address,
RAS#, CAS#, WE# -80 80 μA
CS#, CKE -40 40 μA
CK, CK# -40 40 μA
DM -10 10 μA
IOZ Output leakage current; 0V<VIN<VCC; DQs and ODT are
disable DQ, DQS, DQS# -10 10 μA
IVREF VREF leakage current; VREF = Valid VREF level -32 32 μA
W3HG2128M64EEU-D4
January 2008
Rev. 7 5White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
OPERATING TEMPERATURE CONDITION
Parameter Symbol Rating Unit Note
Operating temperature (Industrial) TOPER -40 to 85 °C 1
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter Symbol Min Max Units
Input High (Logic 1) Voltage VIH(DC) VREF + 0.125 VCC + 0.300 V
Input Low (Logic 0) Voltage VIL(DC) -0.300 VREF - 0.125 V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter Symbol Min Max Units
Input High (Logic 1) Voltage DDR2-400 & DDR2-533 VIH(AC) VREF + 0.250 - V
Input Low (Logic 1) Voltage DDR2-667 & DDR2-800 VIH(AC) VREF + 0.200 - V
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 VIL(AC) - VREF - 0.250 V
Input Low (Logic 0) Voltage DDR2-667 & DDR2-800 VIL(AC) - VREF - 0.200 V
W3HG2128M64EEU-D4
January 2008
Rev. 7 6White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DDR2 ICC SPECIFICATION
Symbol Proposed Conditions 805 806 665 534 403 Units
ICC0*
Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Normal 840 840 800 760 720
mA
Low Power 784 784 744 704 664
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS =
tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
Normal 920 920 880 840 800
mA
Low Power 864 864 824 784 744
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
Normal 240 240 240 240 240
mA
Low Power 128 128 128 128 128
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
640 640 640 640 560 mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
800 800 720 720 640 mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit
MRS(12) = 0 640 640 640 560 560 mA
Slow PDN Exit
MRS(12) = 1 288 288 288 288 288 mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
1,040 1,040 960 960 880 mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK =
tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Normal 1,280 1,280 1,160 1,080 960
mA
Low Power 1,224 1,224 1,104 1,024 904
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL =
0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as ICC4W
Normal 1,360 1,360 1,240 1,160 1,040
mA
Low Power 1,304 1,304 1,184 1,104 984
ICC5*
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,480 2,480 2,400 2,400 2,320 mA
ICC6**
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal 240 240 240 240 240
mA
Low Power 96 96 96 96 96
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-
1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data bus inputs are SWITCHING.
Normal 2,240 2,200 2,040 2,040 1,920
mA
Low Power 2,184 2,144 1,984 1,984 1,864
ICC specifi cation is based on SAMSUNG 1G (D-die revision) components. Other DRAM manufactures specifi cation may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated refl ects all module ranks in this operating condition.
W3HG2128M64EEU-D4
January 2008
Rev. 7 7White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DDR2 ICC SPECIFICATION
Symbol Proposed Conditions 805 806 665 534 Units
ICC0*
Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Normal 720 720 680 TBD
mA
Low Power 664 664 624 TBD
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS =
tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
Normal 800 800 760 TBD
mA
Low Power 744 744 704 TBD
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
Normal 240 240 240 TBD
mA
Low Power 128 128 128 TBD
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
480 480 480 TBD mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
560 560 560 TBD mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit
MRS(12) = 0 560 560 560 TBD mA
Slow PDN Exit
MRS(12) = 1 288 288 288 TBD mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
880 880 880 TBD mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK =
tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Normal 1,040 1,040 960 TBD
mA
Low Power 984 984 904 TBD
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL =
0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as ICC4W
Normal 1,200 1,200 1,080 TBD
mA
Low Power 1,144 1,144 1,024 TBD
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,230 2,230 2,240 TBD mA
ICC6**
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal 240 24 240 TBD
mA
Low Power 96 96 96 TBD
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-
1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data bus inputs are SWITCHING.
Normal 2,120 2,120 1,960 TBD
mA
Low Power 2,064 2,064 1,904 TBD
ICC specifi cation is based on SAMSUNG 1G (Q-die revision) components. Other DRAM manufactures specifi cation may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated refl ects all module ranks in this operating condition.
W3HG2128M64EEU-D4
January 2008
Rev. 7 8White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DDR2 ICC SPECIFICATION
Symbol Proposed Conditions 805 806 665 534 403 Units
ICC0*
Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
776 776 736 616 616 mA
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as ICC4W
936 936 856 816 776 mA
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
112 112 112 112 112 mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
800 800 640 640 560 mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
800 800 640 640 560 mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit
MRS(12) = 0 800 800 480 480 480 mA
Slow PDN Exit
MRS(12) = 1 160 160 160 160 160 mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
960 960 880 720 640 mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
1,336 1,336 1,136 1,056 896 mA
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
1,336 1,336 1,136 1,056 896 mA
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
3,760 3,760 3,440 3,360 3,280 mA
ICC6**
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal 112 112 112 112 112
mA
Low Power 80 80 80 80 80
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
2,736 2,736 2,296 2,216 2,136 mA
ICC specifi cation is based on MICRON (1G E-die revision) components. Other DRAM manufactures specifi cation may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated refl ects all module ranks in this operating condition.
W3HG2128M64EEU-D4
January 2008
Rev. 7 9White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS SYMBOL 805 806 665 534 403 UNIT
PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Clock
Clock cycle time
CL = 6 tCK (6) 2,500 8,000 2,500 8,000 3,000 8,000
CL = 5 tCK (5) 2,500 8,000 3,000 8,000 3,000 8,000 3,750 8,000 ps
CL = 4 tCK (4) 3,750 8,000 3,750 8,000 3,750 8,000 3,750 8,000 5,000 8,000 ps
CL = 3 tCK (3) 5,000 8,000 5,000 8,000 5,000 8,000 5,000 8,000 5,000 8,000 ps
CK high-level width tCH 0.48 0.52 0.48 0.52 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CK low-level width tCL 0.48 0.52 0.48 0.52 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Half clock period tHP MIN (tCH,
tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)ps
Data
DQ output access time from CK/CK# tAC -400 +400 -400 +400 -450 +450 -500 +500 -600 +600 ps
Data-out high-impedance window from
CK/CK# tHZ tAC MAX tAC MAX tAC MAX tAC MAX tAC MAX ps
Data-out low-impedance window from
CK/CK# tLZ 2x
tAC MIN tAC MAX 2x
tAC MIN tAC MAX 2x
tAC MIN tAC MAX 2x
tAC MIN tAC MAX 2x
tAC MIN tAC MAX ps
DQ and DM input setup time relative to DQS tDS 50 50 100 100 150 ps
DQ and DM input hold time relative to DQS tDH 125 125 175 225 275 ps
DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 0.35 0.35 0.35 tCK
Data hold skew factor tQHS 300 300 340 400 450 ps
DQ - DQS hold, DQS to fi rst DQ to go
nonvalid, per access tQH tHP - tQHS tHP - tQHS tHP - tQHS tHP - tQHS tHP - tQHS ps
Data Strobe
DQS input high pulse width tDQSH 0.35 0.35 0.35 0.35 0.35 tCK
DQS input low pulse width tDQSL 0.35 0.35 0.35 0.35 0.35 tCK
DQS output access time from CK/CK# tDQSCK -350 +350 -350 +350 -400 +400 -450 +450 -500 +500 ps
DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 0.2 0.2 tCK
DQS falling edge from CK rising - hold time tDSH 0.2 0.2 0.2 0.2 0.2 tCK
DQS - DQ skew, DQS to last DQ valid, per
group, per access tDQSQ 200 200 240 300 350 ps
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK
DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS write preamble tWPRE 0.35 0.35 0.35 0.35 0.35 tCK
DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Write command to fi rst DQS latching transition tDQSS WL
- 0.25
WL +
0.25
WL
-0.25
WL
+0.25
WL
-0.25
WL
+0.25
WL
-0.25
WL
+0.25
WL
-0.25
WL
+0.25 tCK
Address and control input pulse width for
each input tIPW 0.6 0.6 0.6 0.6 0.6 tCK
Address and control input setup time tIS 175 175 200 250 350 ps
Address and control input hold time tIH 250 250 275 375 475 ps
Address and control input hold time tCCD 22222t
CK
AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
Continued on next page
W3HG2128M64EEU-D4
January 2008
Rev. 7 10 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS SYMBOL 805 806 665 534 403 UNIT
PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Command and Address
ACTIVE to ACTIVE (same bank) command tRC 57.5 60 60 60 55 ns
ACTIVE bank a to ACTIVE bank b command tRRD 7.5 7.5 7.5 7.5 7.5 ns
ACTIVE to READ or WRITE delay tRCD 12.5 15 15 15 15 ns
ACTIVE to PRECHARGE command tRAS 45 70,000 45 70,000 45 70,000 45 70,000 40 70,000 ns
Internal READ to precharge command delay tRTP 7.5 7.5 7.5 7.5 7.5 ns
Write recovery time tWR 15 15 15 15 15 ns
Auto precharge write recovery + precharge
time tDAL tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP ns
Internal WRITE to READ command delay tWTR 7.5 7.5 7.5 7.5 10 ns
PRECHARGE command period tRP 12.5 15 15 15 15 ns
LOAD MODE command cycle time tMRD 22222t
CK
CKE low to CK,CK# uncertainty tDELAY tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH ns
Self Refresh
REFRESH to Active of Refresh to Refresh
command interval tRFC 105 105 105 105 105 ns
Average periodic refresh interval tREFI 7.8 7.8 7.8 7.8 7.8 μs
Exit self refresh to non-READ command tXSNR tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10 ns
Exit self refresh to READ command tXSRD 200 200 200 200 200 tCK
ODT
ODT turn-on delay tAOND 2222222222t
CK
ODT turn-on tAON tAC
(MIN)
tAC
(MAX)
+ 700
tAC
(MIN)
tAC
(MAX)
+ 700
tAC
(MIN)
tAC
(MAX)
+ 700
tAC
(MIN)
tAC
(MAX)
+ 1000
tAC
(MIN)
tAC
(MAX)
+ 1000
ps
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tCK
ODT turn-off tAOF tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
ps
ODT turn-on (power-down mode) tAONPD
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
ps
ODT turn-off (power-down mode) tAOFPD
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
ps
ODT to power-down entry latency tANPD 33333t
CK
ODT power-down exit latency tAXPD 88888t
CK
Power-Down
Exit active power-down to READ command,
MR[bit12=0] tXARD 22222t
CK
Exit active power-down to READ command,
MR[bit12=1] tXARDS 8-AL 8 - AL 7 - AL 6 - AL 6 - AL tCK
A Exit precharge power-down to any non-
READ command. tXP 22222t
CK
CKE minimum high/low time tCKE 33333t
CK
AC specifi cation is based on SAMSUNG components. Other DRAM manufactures specifi cation may be different.
W3HG2128M64EEU-D4
January 2008
Rev. 7 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
3.80 (0.150)
MAX
1.10 (0.043)
0.90 (0.035)
PIN 1
67.75 (2.667)
67.45 (2.656)
20.00 (0.787)
TYP
1.80 (0.071)
(2X)
0.60 (0.024)
TYP
0.45 (0.018)
TYP
PIN 199
PIN 200 PIN 2
2.15 (0.085)
6.00 (0.236)
63.60 (2.504)
2.55 (0.100)
1.00 (0.039)
TYP
TYP
BACK VIEW
FRONT VIEW
30.15 (1.187)
29.85 (1.175)
47.40 (1.866)
TYP 11.40 (0.449)
TYP
4.2 (0.165)
TYP
4.10(0.161) (2X)
3.90(0.154)
PACKAGE DIMENSIONS FOR D4
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
ORDERING INFORMATION FOR D4
Part Number Clock Speed/Data Rate CAS Latency tRCD tRP Height*
W3HG2128M64EEU805xD4xxG 400MHz/800Mb/s 5 5 5 30.00mm (1.181") TYP
W3HG2128M64EEU806xD4xxG 400MHz/800Mb/s 6 6 6 30.00mm (1.181") TYP
W3HG2128M64EEU665xD4xxG 333MHz/667Mb/s 5 5 5 30.00mm (1.181") TYP
W3HG2128M64EEU534xD4xxG 266MHz/533Mb/s 4 4 4 30.00mm (1.181") TYP
W3HG2128M64EEU403xD4xxG 200MHz/400Mb/s 3 3 3 30.00mm (1.181") TYP
NOTES:
• Industrial grade product is tested from -40°C to +85°C
• For part numbering interpretation, please see "part numbering guide" on page 10
W3HG2128M64EEU-D4
January 2008
Rev. 7 12 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PART NUMBERING GUIDE
W 3 H G 2 128M 64 E E U xxx x D4 x x G
WEDC
MEMOR Y (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
SPEED (Mb/s)
DIE REV OPTION
PACKAGE 200 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank" for industrial add "I")
(Industrial Temp: -40°C to +85°C)
COMPONENT VENDOR NAME
(S = Samsung)
(M = Micron)
Note: Consult factory for other vendor options
G = RoHS COMPLIANT
W3HG2128M64EEU-D4
January 2008
Rev. 7 13 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
Document Title
2GB – 2x128Mx64 DDR2 SDRAM SO-DIMM UNBUFFERED
Revision History
Rev # History Release Date Status
Rev 0 Created December 2006 Concept
Rev 1 1.0 Moved to advanced
1.1 Updated power specifi cation
1.2 Corrected part numbering guide
March 2007 Advanced
Rev 2 2.0 Corrected pin names
2.1 Updated block diagram
2.2 Corrected ICC specs
2.3 Updated AC timing specs
May 2007 Advanced
Rev 3 3.0 Added 800Mb/s specs (AC's and ICC), based on Samsung
D-Die
3.1 Updated ordering information to indicate 800Mb/s part
number for both CL = 5-5-5 and 6-6-6
June 2007 Advanced
Rev 4 4.0 Updated specifi cations June 2007 Advanced
Rev 5 5.0 Added industrial temp clarifi cation to ordering information
and part numbering guide June 2007 Advanced
Rev 6 6.0 Added low power specs for Samsung based components
6.1 Added Micron power specs August 2007 Advanced
Rev 7 7.0 Added Samsung Q-die ICC table January 2008 Final
