ii Altera Corporation
Viterbi Compiler MegaCore Function User Guide
Altera, ACEX, APEX, APEX 20K, FLEX, FLEX 10KE, MAX+PLUS II, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II
are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera Corporation
acknowledges the trademarks of other organizations for their respective products or services mentioned in this document,
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Copyright 2001 Altera Corporation. All rights reserved.
Altera Corporation iii
User Guide
About this User Guide
This user guide provides comprehensive information about the Altera®
Viterbi compiler MegaCore® function.
Table 1 shows the user guide revision history.
How to Find
Information
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Table 1. Revision History
Revision Date Description
1.0 Sep 2000 Initial release.
2.0 Mar 2001 Version 2.0 updates incorporated.
2.1 June 2001 Version 2.1 updates incorporated.
iv Altera Corporation
About this User Guide Viterbi Compiler MegaCore Function User Guide
How to Contact
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Note:
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Altera Corporation v
Viterbi Compiler MegaCore Function User Guide About this User Guide
Typographic
Conventions
The Viterbi Compiler MegaCore Function User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \QuartusII directory, d: drive, chiptrip.gdf file.
Bold italic type Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title” References to sections within a document and titles of Quartus II and MAX+PLUS II
Help topics are shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX
8000 Device with the BitBlaster™ Download Cable.”
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\quartusII\qdesigns\tutorial\chiptrip.gdf. Also, sections
of an actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
The hand points to information that requires special attention.
The angled arrow indicates you should press the Enter key.
The feet direct you to more information on a particular topic.
Notes:
Altera Corporation vii
Contents
User Guide
About this User Guide ..............................................................................iii
How to Find Information ............................................................................................................iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ............................................................................................................. v
Specifications ........................................................................................9
Features .............................................................................................................................................9
General Description .........................................................................................................................9
Product Options .....................................................................................................................11
Functional Description ..................................................................................................................12
Parallel Architecture ..............................................................................................................20
Soft Symbol Inputs .................................................................................................................20
Puncturing Scheme ................................................................................................................21
MegaWizard Plug-In Manager ....................................................................................................23
Performance ....................................................................................................................................24
Core Verification ............................................................................................................................25
Getting Started ..................................................................................... 27
Downloading & Installing the Function ....................................................................................28
Obtaining MegaCore Functions ...........................................................................................28
Installing the MegaCore Files ...............................................................................................28
Generating a Custom Viterbi Core ..............................................................................................29
Selecting the Viterbi Compiler Core ....................................................................................29
Architecture and Options .....................................................................................................30
Parameters ...............................................................................................................................31
Code Set Information (hybrid architecture only) ..............................................................35
Integrated Depuncturing Option .........................................................................................36
Test Data Settings ...................................................................................................................37
Completing the Custom Function .......................................................................................39
Simulating in the ModelSim Simulation Tool ...........................................................................41
Simulating using the Visual IP Model in the ModelSim Software .................................42
Configuring a Device .....................................................................................................................44
Notes:
Altera Corporation 9
User Guide
1
Specifications
Specifications
Features ■High-performance, area-optimized, soft-decision Viterbi decoders
for error correction
■ High-speed parallel architecture with:
–Pure logic implementation or memory based traceback
–Performance exceeding 100 Mbps
–Fully parallel operation
–Integral configurable depuncturing rate
■Low to medium-speed, hybrid architecture
–Configurable number of add compare and select (ACS) units
–Memory based architecture
–Wide range of performance from 0.5 to 12 Mbps
–Wide range of logic area
■Fully parameterized Viterbi core, including:
–Number of coded bits
–Constraint length
–Number of soft bits
–Precision of branch metric accumulation
–Traceback depth or maximum block length
–Polynomial for each coded bit
■Efficient RTL model for use in VHDL and Verilog HDL simulations
■VHDL testbenches to verify the decoder using the Model Technology
ModelSim simulation tool
■Optimized for Altera APEX™ 20K, APEX 20KC, APEX 20KE, ACEX™
1K, FLEX®6000, FLEX 8000, FLEX 10K, and FLEX 10KE devices
■Flexible licensing— use only the features you require
■Easy-to-use MegaWizard® Plug-In Manager
General
Description
Viterbi decoding (also known as maximum likelihood decoding or
forward dynamic programming) is the most common way of decoding
convolutional codes by using an asymptotically optimum decoding
technique.
In its basic form, Viterbi decoding is an efficient, recursive algorithm that
performs an optimal exhaustive search.
A convolutional encoder and Viterbi decoder can be used together to
provide error correction over a noisy channel, e.g., a communications
channel. A convolutional encoder adds redundancy (i.e., extra bits) to a
data stream before transmission.
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Specifications Viterbi Compiler MegaCore Function User Guide
The rate and the generating polynomials describe the encoder. The rate is
the number of extra bits per input bit, e.g., a rate 1/2 encodes 1 bit and
produces 2 bits for transmission. Similarly, a rate 2/3 encodes 2 bits and
produces 3 bits for transmission. A code can be punctured to increase its
rate, by deleting some of the encoded bits according to a deterministic
pattern.
The generating polynomials are bit patterns that denote the bits of the
input data stream, which are mathematically combined to produce an
encoded bit. There is one generating polynomial per encoded bit. The
length in bits of the generating polynomial is called the constraint length;
systems with higher constraint lengths are generally more robust.
However, the complexity of the Viterbi decoder increases exponentially
with the constraint length, so it is unusual to find constraint lengths
greater than nine.
Bit errors can occur at the receiver if the transmission channel is noisy. The
Viterbi algorithm is efficient at decoding the data stream and correcting
errors. The Viterbi decoder uses the redundancy, which the convolutional
encoder imparted, to decode the bit stream and remove the errors.
When encoded with the generating polynomials, the Viterbi algorithm
finds the most likely sequence of bits that is closest to the actual received
sequence. The decoding is highly mathematical, and uses a state machine
to describe how the received sequence could have resulted from all
possible sequences of bits. While processing bits the decoder retains
information on the likelihood of the possible sequences, which are stored
as ‘accumulated branch metrics’.
The receiver can deliver either hard or soft symbols to the Viterbi decoder.
A hard symbol is equivalent to a binary ±1. A soft symbol is multi-leveled
to represent the confidence in the bit being positive or negative. For
instance, if the channel is non-fading and Gaussian, the output of a
matched filter quantized to a given number of bits is a suitable soft input.
In both cases 0 is used to represent a punctured bit. The Viterbi algorithm
has better performance with soft input symbols.
The Viterbi decoder works on blocks of data, or continuous streams. It
takes in n symbols at a time for processing, where n is the number of
encoded symbols. The traceback length is the delay before the decoder
makes a decision on a bit. For blocks of data, the best performance is
achieved if decoding decisions are delayed until all input symbols have
been processed. For continuous streams this is not possible, and for
practical purposes the traceback length should be limited to several times
the constraint length.
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Viterbi Compiler MegaCore Function User Guide Specifications
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Specifications
You can parameterize the Altera® high-performance, soft-decision Viterbi
compiler MegaCore® function to implement any number of standard
Viterbi decoders, or to create a custom application. The function is capable
of a throughput (decoded bits output) exceeding 100 Mbps, even for
relatively large constraint lengths, such as 7. The function can support
many different puncturing rates, based on a mother code of 1/2.
The function also supports hard decision decoding, when the number of
soft bits is set to two.
Product Options
There are two Viterbi decoder functions within the Viterbi compiler
MegaCore function; for each you can specify a number of options. With
Altera flexible licensing, you only need to license the product that you
require. Table 1 shows the product options.
Note:
(1) Available with the continuous decoding option, not with the block decoding
option.
The bit error rate (BER) estimator option uses a re-encode and compare
approach for estimating errors. In cases where the signal-to-noise ratio is
sufficiently high to allow the decoder to decode an error-free output, the
BER estimation is very close to the actual channel BER. When the decoder
is not decoding an error-free output, the estimated BER is slightly higher
than the actual channel BER.
The multiple code set option allows up to five code sets, where a code set
comprises a code rate and associated generating polynomials.
Table 1. Product Options
Options Architecture
Hybrid Parallel
BER Estimator
Multiple Code set
Node Synchronization (1)
Integrated Depuncturing
Continuous Decoding
Block Decoding
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Specifications Viterbi Compiler MegaCore Function User Guide
When the Viterbi decoder is used as a continuous decoder, it processes
bits from a continuous data stream. The block decoding option allows the
decoder to start and end in a given run-time state, allowing optimum
decoding of a data block framed with tail bits.
The block decoding option comprises:
■Run-time selection of start state in a block
■Run-time selection of either an end state that you specify, or the state
with the best metric (from this state the traceback starts its operation
for the block)
■Run-time selection of block length (up to the value of the traceback
parameter)
■An output providing the best metric per decoded block
Table 2 shows the product order codes.
Functional
Description
Table 3 shows the function’s parameters, which can only be set in the
MegaWizard Plug-In and are described in detail in “Generating a Custom
Viterbi Core” on page 29.
Table 2. Ordering Codes
Product Order Code
Parallel architecture PLSM-HC-VITERBI/HS
Hybrid architecture PLSM-HC-VITERBI/SS
Table 3. Parameters (Part 1 of 2)
Parameter Description
niThe number of coded bits. For every bit to be encoded, ni bits are output. With the
multiple code set option there are up to 5 different ni parameters, which can be in
any order.
acs_units The number of ACS units, which adds a degree of parallelism (hybrid architecture
only).
constraint_length The constraint length. Selecting less than 9 limits the acs_units range.
softbits The number of soft decision bits per symbol. When softbits is set to 2 bits, the
decoder acts as a hard decision decoder, and still allows for erased symbols to be
entered as binary ‘00’.
norm_divisor When normalization occurs, the metrics are divided by norm_divisor, except for
norm_divisor = 1 where a constant is subtracted from the metric. Normalization
is necessary when overflow occurs.
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Viterbi Compiler MegaCore Function User Guide Specifications
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Specifications
Note:
(1) Traceback length can have a large impact on logic elements (LEs) used.
Table 4 shows the input signals.
bmgwide The precision of the branch metric accumulation. For certain combinations of n and
constraint_length, a larger number for bmgwide must be specified. When the
decoder is reset, all metrics are set to zero. When any metric reaches a value where
overflow can occur, all metrics are normalized (see norm_divisor).
vTraceback length, which is typically set to 5 × constraint_length for
unpunctured codes, and up to 15 × constraint_length for highly punctured
codes. (1)
Table 3. Parameters (Part 2 of 2)
Parameter Description
Table 4. Input Signals (Part 1 of 3)
Signal Name Description
sysclk sysclk is the main system clock. n symbols are read
in at each rising edge of the clock—the whole core
operates on the rising edge of sysclk. With the
parallel architecture and when internal depuncturing is
in operation, only one symbol is read in at each clock
cycle.
reset The entire decoder is asynchronously reset when
reset is asserted high.
enable The decoder is enabled, when enable is asserted
high. When it is low, no symbols are latched into the
core and all internal registers stop loading data at the
rising edge of sysclk.
load When high, load latches the rr[] bus into the
decoder on the rising edge of sysclk. load must be
asserted after the core asserts the output ready
(assuming input data is ready), otherwise enable must
be asserted low. (1)
rr[(n_max*softbits):1]
rr[(softbits):1] (2)
This takes in n symbols, each softbits wide per
clock. The first symbol received occupies the most
significant bits of rr[], and the last symbol received
occupies the least significant bits of rr[]. Erased
(depunctured) symbols are equal to zero. An encoded
‘1’ is negative (i.e., ‘1XX:’) and an encoded ‘0’ is
positive (i.e. ‘0XX:’). n_max is max(n).
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Specifications Viterbi Compiler MegaCore Function User Guide
sync_rot When asserted high for one clock cycle, a state
transition occurs where the n incoming signals are
rotated. Metrics and traceback register values are
synchronously cleared also.
sel_code[log2(ncodes):1] Selects the codeword—’0’ selects the first codeword,
‘1’ selects the second, etc. The bus size increases
according to the number of codes specified.
tb_length[] Specifies the block size. After the number of symbol
sets set by tb_length[]is received, further inputs to
the decoder are ignored and the traceback starts. The
width of tb_length[]is automatically set to handle
the maximum value of v. tb_length[]must remain
stable before the decoder is reset and until the
traceback starts. (6), (7)
tb_type When tb_type is low, the decoder uses the state
containing the best metric state to start the traceback
from. When tb_type is high, the decoder uses the
state specified in
tr_init_state[(constraint_length – 1):1].
(6), (7)
tr_init_state[(constraint_length – 1):1] Specifies the state to start the traceback from, when
tb_type is asserted high.
period_ber[24:1] Specifies the number of decoded symbols over which
the BER measurement is made. After the specified
number of symbols is reached, the bererr[16:1]
output bus is latched with the number of errors
estimated during the previous measurement period,
and the numerr[16:1] bus is reset to zero. A new
measurement period then begins. (3)
period_ns[8:1] Specifies the number of decoded symbols over which
the BER measurement is made, to decide whether the
decoder has achieved node synchronization or not.
Output signals in_sync and out_sync are flagged,
and the numerr_ns[8:1] bus is reset to zero. A new
measurement period then begins. (4)
threshold_ns[8:1] Specifies the number of errors’ threshold over the
period period_ns, to decide whether the decoder is in
node synchronization or not. (4)
Table 4. Input Signals (Part 2 of 3)
Signal Name Description
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Viterbi Compiler MegaCore Function User Guide Specifications
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Specifications
Notes:
(1) Not used with parallel architectures.
(2) Used only when internal depuncturing is enabled.
(3) Valid only when you select the BER option.
(4) Valid only when you select the node synchronization option.
(5) Used only when you select the multiple code set option.
(6) Used only when you select the block decoding option.
(7) Hybrid architecture only.
bm_init_state[(constraint_length–1):1] Specifies which state to initialize the metric from the
bm_init_value[] bus. All other branch metrics are
set to zero.
bm_init_state[(constraint_length–1):1]
must be stable before reset, and remain stable until
after the third symbol set is read in. (6), (7)
bm_init_value[(constraint_length–1):1] Specifies the value of the metric that initializes the start
state. All other metrics are set to 0.
bm_init_value[(constraint_length–
1):1]must be larger than
(constraint_length × 2(softbits – 1)). (6), (7)
Table 4. Input Signals (Part 3 of 3)
Signal Name Description
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Specifications Viterbi Compiler MegaCore Function User Guide
Table 5 shows the output signals.
Table 5. Output Signals (Part 1 of 2)
Signal Description
ready ready is asserted when the decoder requires another n symbols
on the rr[] bus on the next rising edge. If the input symbols are
not available, the decoder must be disabled until they are
available (using the enable signal). (1)
valid valid is an internal enable signal that is applied to the decoder.
valid indicates when internal depuncturing is used and indicates
when the core is enabled or not enabled.
decbits[bitsout:1] (1), (3)
decbit (2)
The decbits[] bus or the decbit signal contains output bits
when outvalid is asserted.
outvalid outvalid is asserted high, whenever there is a valid output on
the decbits[] bus, or decbit signal.
normalize normalize is asserted high for one clock cycle, whenever the
branch metrics are normalized.
in_sync in_sync is asserted high when the number of errors are less
than threshold_ns, after monitoring the BER output for
period_ns symbols.
out_sync out_sync is asserted high when the number of errors are equal
or higher than threshold_ns, after monitoring the BER output
for period_ns symbols.
numerr[] The numerr[] bus contains the number of errors detected during
the current measurement period. It is updated each time an error
is detected, making it possible to see the location of individual
errors. It is reset at the end of each measurement period. The
width of this bus is automatically set to handle the maximum value
of v. (3), (5)
numerr_ber[] The numerr_ber[] bus contains the number of errors detected
during the current measurement period. It is updated each time an
error is detected, making it possible to see the location of
individual errors (hybrid and parallel continuous architecture
only).
numerr_ns[] The numerr_ns[] contains the number of errors detected during
the current period_ns. This value is then compared against
threshold_ns to decide whether the decoder is in node
synchronization or not. (6)
bererr[16:1] The bererr[16:1] contains the number of errors detected
during the previous measurement period. It is updated at the end
of each measurement period. (3), (4)
bestmet[bmgwide:1] The best metric. (5)
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Viterbi Compiler MegaCore Function User Guide Specifications
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Specifications
Notes:
(1) Hybrid architectures only.
(2) Parallel architectures only.
(3) The MegaWizard Plug-In sets the width of this bus.
(4) Valid only when you select the BER estimator option.
(5) Valid only when you select the block decoding option.
(6) Valid only when you select the node synchronization option.
Figure 1 is a timing diagram for hybrid continuous decoding, and shows
the relationship between ready and load. Figure 2 shows a timing
diagram for hybrid block decoding.
Figure 1. Continuous Decoding (Hybrid Architecture)
bestadd[(constraint_length–1):1] The best address state. (5)
bitnum[] bitnum[] contains the decoded bit position within the block,
starting with position ‘0’ and ending with position
tb_length[] –1. The width of this bus is automatically set to
handle the maximum value of v. (5)
Table 5. Output Signals (Part 2 of 2)
Signal Description
sysclk
reset
enable
ready
load
rr[20..1] 76747 7667576747
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Specifications Viterbi Compiler MegaCore Function User Guide
Figure 2. Block Decoding (Hybrid Architecture)
For hybrid continuous decoding, the output bus is decbits[bitsout
.. 1], where bitsout is a parameter that depends upon the
constraint_length , acs_units and v. This is shown in the following
equations:
log2cc = constraint_length – 1 – log2(acs_units)
bitsout = ceil ( (v + 1) / (2log2cc ) )
For example, when
constraint_length = 5,
acs_units = 2,
v = 29,
therefore bitsout = 4.
sysclk
enable
reset
rr[66..1]
load
ready
normalize
sel_code
bm_init_state
bm_init_value
tr_init_state
outvalid
tb_type
tb_length[9..1]
bitnum[9..1]
decbits
numerr[12..1]
bestadd[23..1]
bestmet[23..1]
00000000122600400 000000000FFEE0052D00000000122600400
1
0
0
0
300
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0
3
1820686
Altera Corporation 19
Viterbi Compiler MegaCore Function User Guide Specifications
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Specifications
Another parameter dictates, on the first outvalid pulse, how many bits
have to be skipped and is given by:
skipbit = (v + 2) mod bitsout.
Figure 3 shows hybrid continuous decoding and illustrates skipbit. For
the given parameters, skipbit = 3. On the first outvalid pulse, the first
three bits are not valid or have to be skipped. The first three bits are
decbits (1) = 0, decbits (2) = 0, and decbits (3) = 0; decbits (4) = 1
is the first valid bit. The following valid bit is decbits (1) = 1 at the next
outvalid pulse.
Figure 3. Hybrid Continuous Decoding—Illustrating Skipbit
You may want to select values of v that force skipbit to be zero
(constraint_length and, to some degree, acs_units are dictated by
the application and the required throughput). When skipbit is zero,
after a reset, the first outvalid pulse indicates a set of decbits that are
all valid, which makes the core easier to use in your system.
87 88 77 87 77 78 77 7878
0
0000 0000 0000
17408
1
1
sysclk
First Outvalid Pulse
reset
enable
load
rr
sel_code
outvalid
normalize
ready
decbits[0]
decbits[4]
decbits[3]
decbits[2]
decbits[1]
period_ber
bererr
numerr_ber
78 88 A5 87 77 78 87 77
0000 0000 0000
17408
0
0
20 Altera Corporation
Specifications Viterbi Compiler MegaCore Function User Guide
Parallel Architecture
You can specify traceback type (parallel architecture only) as memory-
based or logic-based. Memory-based traceback implements the traceback
mechanism using RAM to store the survivors information; logic-based
traceback uses logic (flip-flops) to store the survivors information.
Memory-based requires more LEs, but no ESBs are deployed on the
traceback operation. Logic-based requires less LEs, but it uses a number of
ESBs.
For the parallel architecture with memory-based traceback, the parameter
norm_divisor has a great impact on performance and size depending
on whether the subtract option is selected, or the option of dividing by 2,
4, or 8 is chosen. Subtracting a value from the metrics yields better BER
performance, although the size is slightly higher and the frequency is
slightly lower than that achieved by the division configuration (see
Table 10 on page 25 for some examples).
Soft Symbol Inputs
Table 6 shows an example of the soft symbol input representation, for
softbits = 4.
Table 6. Soft Symbol Input Representation
Soft Symbol Meaning
0111 Strongest ‘0’
0110 Stronger ‘0’
0101 Strong ‘0’
0100 Medium ‘0’
0011 Weak ‘0’
0010 Weaker ‘0’
0001 Weakest ‘0’
0000 Erased Symbol
1111 Weakest ‘1’
1110 Weaker ‘1’
1101 Weak ‘1’
1100 Medium ‘1’
1011 Strong ‘1’
1010 Stronger ‘1’
1001 Strongest ‘1’
1000 Stronger ‘1’ (input normally clipped to 1001 for maximum ‘1’)
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Viterbi Compiler MegaCore Function User Guide Specifications
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Specifications
Puncturing Scheme
All architectures support external puncturing. All punctured codes
shown are based on a mother code of rate 1/2. For external depuncturing
you must depuncture the received data stream external to the decoder,
and input the data into the decoder n symbols at a time. If you are using
a parallel decoder with an externally punctured code, you need two clocks
in the system—a faster received-bits clock and a slower decoder clock. If
you use one clock, you must operate the enable signal. Even if the code
is unpunctured, you must still combine n symbols into a parallel symbol
vector and present the symbol vector data samples to the decoder with
every decoder clock. When testing this decoder with a depunctured code,
erased symbols are entered as zero.
Only the parallel architectures (with n = 2) support internal depuncturing.
The decoder receives input symbols one at a time and depunctures the
data internally. The punctured rates supported are given by:
Punctured rate = ‘x/y’ or ‘unpunctured’
where x<y, x/y>1/2
(x = information symbols, y – x = parity symbols).
Puncturing rate = mother code rate/punctured rate,
i.e., 1/2
punctured rate
22 Altera Corporation
Specifications Viterbi Compiler MegaCore Function User Guide
Table 7 shows some possible puncturing schemes, which can be defined,
and their rate.
Note:
(1) CA refers to the most significant (first transmitted bit, first received symbol); CB
refers to the least significant (last transmitted bit, last received symbol).
Table 7. Some Puncturing Schemes
Punctured Rate Puncturing
Rate
Puncturing Scheme
Bit (1) Multiplier
2/3 3/4 CA 1 0
CB 1 1
3/4 4/6 CA 101
CB 110
4/5 5/8 CA 1000
CB 1111
5/6 6/10 CA 10101
CB 11010
6/7 7/12 CA 100101
CB 111010
7/8 8/14 CA 1000101
CB 1111010
Altera Corporation 23
Viterbi Compiler MegaCore Function User Guide Specifications
1
Specifications
MegaWizard
Plug-In
Manager
The Viterbi compiler MegaCore function has an interactive wizard-driven
interface that allows you to create custom Viterbi functions easily. You can
launch the MegaWizard Plug-In Manager from within the Quartus II or
MAX+PLUS II software. The wizard allows you to input your choice of
parameters, verifies that all choices are valid, and generates a custom
MegaCore function in VHDL, AHDL, or Verilog HDL, which you can
integrate into your system design.
When you finish going through the wizard it generates several files:
■One of the following files (depending on your selection), which are
used to used to instantiate an instance of the function in your design:
–An AHDL Text Design File (.tdf)
–A VHDL Design File (.vhd)
–Verilog Design File (.v)
■Symbol Files (.bsf for the Quartus software, .sym for the
MAX+PLUS II software) used to instantiate the function into a
schematic design
■An encrypted wrapper <variation name> _enc.vhd, which instantiates
and sets the parameters at synthesis
■<variation name>.inc file (Verilog HDL and AHDL only)
■An example of the instantiation of the core <variation name> _inst
■A blackbox Verilog HDL model, <variation name>_bb (Verilog HDL
only)
■A component declaration file <variation name>.cmp (VHDL only);
■transbit.txt, which contains the bits that have been used to generate
the test data
■a_txsym.txt, which contains the encoded bits
■a_rcvsym.txt, which contains the received bits that are corrupted
with a signal to noise ratio you specify in the MegaWizard Plug-In.
a_rcvsym.txt is input to the bench when testing the core
■BER_report.txt, which contains the number of errors, the BERs and
their location for the test data
■<variation name>_leo_script.tcl, which is used by the
LeonardoSpectrum-Altera synthesis tool to synthesize the core with
your parameters
■A VHDL testbench <variation name>__testbench.vhd), which is used
in the ModelSim software to simulate the core
■<variation name>__vsim_script.tcl, which is used in the ModelSim
software to start the core simulation
<variation name> is the variation name you choose for the core.
24 Altera Corporation
Specifications Viterbi Compiler MegaCore Function User Guide
Performance Tables 8, 9, and 10 show typical expected performance for different
architectures and constraint_length combinations, and acs_units,
for APEX 20KE-1 devices. Performance largely depends on
constraint_length. Results were generated using the Quartus II
software, version 1.0 and the LeonardoSpectrum-Altera simulation tool.
The hybrid continuous architectures parameters used were:
v = 5 × constraint_length,
softbits = 4,
bmgwide = 12,
norm_divisor = 1,
n= 2.
Note:
(1) Performance for the hybrid block architecture is comparable to these figures.
Table 8. Performance & Area Utilization for Hybrid Continuous Architectures with acs_units = 1, 2, or 4
Note (1)
constraint
_length
acs_units = 1 acs_units = 2 acs_units = 4
LEs ESBs MHz LEs ESBs MHz LEs ESBs MHz
4 691 4 96 Not Possible Not Possible
5 698 4 93 1,147 6 86 Not Possible
6 770 5 92 1,183 7 87 2,033 9 76
7 934 7 96 1,365 9 86 2,180 11 84
8 1,206 11 84 1,617 13 85 2,471 15 78
9 1,784 21 77 2,200 21 80 3,022 23 78
Altera Corporation 25
Viterbi Compiler MegaCore Function User Guide Specifications
1
Specifications
Note:
(1) Performance for the hybrid block architecture is comparable to these figures.
Note:
(1) APEX 20KC device
Core
Verification
The core’s verification strategy included an automated regression test
suite, which is described in the following paragraphs.
TCL scripts drove the simulation at RTL level. Data was randomly
generated and encoded. The original transmited bits were stored in a file
transbit.txt. Optionally, Gaussian noise was added as a channel model
and the data was formated for use by the decoder’s testbench. The file that
fed the testbench was a_rcvsym.txt. The testbench collected the decoder’s
decoded bits and stored them in decoded.txt. Those bits were compared
with the original in transbit.txt.
The test script defined sets of tests that covered a comprehensive set of
parameters on RTL VHDL simulation.
Table 9. Performance & Area Utilization for Hybrid Continuous Architectures with acs_units = 8, 16, or 32
Note (1)
constraint
_length
acs_units = 8 acs_units = 16 acs_units = 32
LEs ESBs MHz LEs ESBs MHz LEs ESBs MHz
4 Not Possible Not Possible Not Possible
5 Not Possible Not Possible Not Possible
6 Not Possible Not Possible Not Possible
7 3,781 17 69 Not Possible Not Possible
8 4,080 21 72 7,406 33 63 Not Possible
9 4,650 29 69 7,814 41 65 13,955 65 59
Table 10. Performance & Area Utilization for Parallel Architecture
constraint
_length
Logic-based Traceback
norm_divisor = 2
Memory-based Traceback
norm_divisor = 2
Memory-based Traceback
norm_divisor = 1
LEs ESBs MHz LEs ESBs MHz LEs ESBs MHz
3 533 1 88 629 4 93 821 4 63
5 1,824 1 85 1,496 4 83 1,767 4 63
7 7,540 1 72 4,745 18 70 5,283 18 57
7 (1) 7,529 1 79 4,732 18 83 5,283 18 71
26 Altera Corporation
Specifications Viterbi Compiler MegaCore Function User Guide
The first tests were carried out with noiseless data. Then tests using a
subset of parameters, which used data with noise and performing
hundreds of thousand of bits at different signal-to-noise ratios, were
carried out to evaluate the BER performance. Another subset of
parameters was tested with noiseless data using post-synthesis Vital
VHDL netlist.
The set of test parameters that were chosen were comprehensive and
should detect any malfunction in any of the features or parameter sets of
the three core architectures.
Altera Corporation 27
User Guide
2
Getting Started
Getting Started
This section describes how to obtain the Viterbi compiler MegaCore
function, explains how to install it on your PC, and walks you through the
process of implementing the function in a design. You can test-drive
MegaCore functions using the Altera OpenCore feature to simulate the
functions within your custom logic. When you are ready to generate
programming or configuration files, you should license the function
through the Altera web site or through your local Altera sales
representative.
This walk-through involves the following steps:
1. Downloading and installing the Viterbi compiler MegaCore
function.
2. Generating a custom MegaCore function.
3. Implementing your system using AHDL, VHDL, or Verilog HDL.
4. Compiling your design.
5. Simulating your design to confirm the operation of your system.
6. Licensing the Viterbi compiler MegaCore function and configuring
the devices.
The instructions assume that:
■You are using a PC.
■You are familiar with either the Quartus II or MAX+PLUS II
software.
■Quartus II version 1.1 (or higher) is installed in the default location
(c:\quartus), or MAX+PLUS II version 10.1 (or higher) is installed in
the default location (c:\maxplus2).
■You are using the OpenCore feature to test-drive the Viterbi compiler
MegaCore function or you have licensed the function.
28 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Downloading &
Installing the
Function
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Obtaining MegaCore Functions
If you have Internet access, you can download the Viterbi compiler
MegaCore function from the Altera web site at http://www.altera.com.
Follow the instructions below to obtain the Viterbi compiler MegaCore
function via the Internet. If you do not have Internet access, you can obtain
the Viterbi compiler MegaCore function from your local Altera
representative.
1. Point your web browser at
http://www.altera.com/products/ip/ipm-index.html.
2. In the IP MegaSearch keyword field, type Viterbi.
3. Click the appropriate link for your desired MegaCore function.
4. Click the link for the download icon.
5. Follow the online instructions to download the function and save it
to your hard disk.
Installing the MegaCore Files
For Windows, follow the instructions below:
1. Click Run (Start menu).
2. Type <path name>\<filename>, where <path name> is the location of
the downloaded MegaCore function and <filename> is the file name
of the core. Click OK.
3. The MegaCore Installer dialog box appears. Follow the online
instructions to finish installation.
4. After you have finished installing the MegaCore files, you must
specify the MegaCore function’s library folder (\viterbicompiler-
v2.0.0\lib) as a user library in the Quartus II and MAX+PLUS II
software. Search for “User Libraries” in Quartus II or MAX+PLUS II
Help for instructions on how to add a library.
Altera Corporation 29
Viterbi Compiler MegaCore Function User Guide GettingGetting Started
2
Getting Started
Generating a
Custom Viterbi
Core
This section describes the design flow using the Altera Viterbi compiler
MegaCore function and the Quartus II or MAX+PLUS II development
system. Altera provides a MegaWizard Plug-In Manager with the Viterbi
compiler MegaCore function. The MegaWizard Plug-In Manager, which
you can use within the Quartus II or MAX+PLUS II software, lets you
create or modify design files to meet the needs of your application. You
can then instantiate the custom megafunction in your design file.
You can use the Altera OpenCore feature to compile and simulate the
MegaCore functions in the Quartus II or MAX+PLUS II software,
allowing you to evaluate the functions before deciding to license them.
If you are using the MAX+PLUS II software, use version 10.0 or
higher when designing with this MegaCore function. The
function relies on library files that exist only in these versions of
software.
Selecting the Viterbi Compiler Core
To select the Viterbi compiler MegaCore function, perform the following
steps:
1. Start the MegaWizard Plug-In Manager by choosing the
MegaWizard Plug-In Manager command (Tools menu in the
Quartus II software, File menu in any MAX+PLUS II application).
The MegaWizard Plug-In Manager dialog box is displayed.
Refer to the Quartus II or MAX+PLUS II Help for more
information on how to use the MegaWizard Plug-In Manager.
2. Specify that you want to create a new custom megafunction and
click Next.
3. Select Viterbi v2.1.0 in the Communications folder (see
Figure 1).
30 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Figure 1. Selecting the Megafunction
4. Choose the language for the output file(s)—either AHDL, VHDL, or
Veri log H DL—and specify a folder, <folder name> and name for the
output file, <variation name>. Click Next.
<variation name> and <folder name> must be the same name and
the same folder that your Quartus II or MAX+PLUS II project
use.
Architecture and Options
Select the architecture and options that you require (see Figure 2). Click
Next.
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Viterbi Compiler MegaCore Function User Guide GettingGetting Started
2
Getting Started
Figure 2. Selecting the Architecture
You can select a hybrid block, hybrid continuous, or parallel continuous
architecture. You can select the BER, multiple code set, or node
synchronization options; if the option is greyed out, it is not available for
your architecture.
Parameters
The MegaWizard Plug-In only allows you to select legal
combinations of parameters, and warns you of any invalid
configurations. Press F1 at anytime for on-line help.
Hybrid Architecture
Select the parameters that define the specific Viterbi code you wish to
implement (see Figure 3). Click Next.
The throughput calculator calculates throughput for specified frequencies
and block size.
32 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Figure 3. Selecting the Parameters—Hybrid Architecture
Constraint Length
The constraint length, constraint_length, which can take any integer
value from 4 to 9; selecting less than 9 limits the acs_units range.
ACS Units
The number of ACS units, which adds a degree of parallelism and can take
the values of 1, 2, 4, 8, 16, or 32 depending on the value of
constraint_length.
Traceback
Traceback length, which is typically set to 5 × constraint_length for
unpunctured codes, up to 15 × constraint_length for highly punctured
codes, and is >10. Traceback length can have a large impact on the number
of logic elements (LEs) used.
Softbits
The number of soft decision bits per symbol, softbits. When softbits
is set to 2 bits, the decoder acts as a hard decision decoder and still allows
for erased symbols to be entered as binary ‘00’. softbits can take any
integer value from 2 to 16.
Normalization
When normalization occurs, the metrics are divided by 2, 4, or 8, except
for normalization = 1 where a constant is subtracted from the metric.
Normalization is necessary when overflow occurs.
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Viterbi Compiler MegaCore Function User Guide GettingGetting Started
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Getting Started
BMGWIDE
The precision of the branch metric accumulation, bmgwide. For certain
combinations of n and constraint_length, a larger number for
bmgwide must be specified. When the decoder is reset, all metrics are set
to zero. When any metric reaches a value where overflow can occur, all
metrics are normalized (see normalization).bmgwide must be greater
than (softbits + 7 bits).
Parallel Architecture
Select the parameters that define the specific Viterbi code you wish to
implement (see Figure 4). Click Next.
34 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Figure 4. Selecting the Parameters—Parallel Architecture
Constraint Length
The constraint length, constraint_length, which can take any integer
value from 3 to 7.
Softbits
The number of soft decision bits per symbol, softbits. When softbits
is set to 2 bits, the decoder acts as a hard decision decoder, and still allows
for erased symbols to be entered as binary ‘00’. softbits can take any
integer value from 2 to 16.
Traceback
Traceback length, which is typically set to 5 × constraint_length for
unpunctured codes, up to 15 × constraint_length for highly punctured
codes, and is >10. Traceback length can have a large impact on the number
of logic elements (LEs) used.
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Viterbi Compiler MegaCore Function User Guide GettingGetting Started
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Getting Started
Normalization
When normalization occurs, the metrics are divided by 2, 4, or 8, except
for normalisation = 1 where a constant is subtracted from the metric.
Normalization is necessary when overflow occurs.
BMGWIDE
The precision of the branch metric accumulation. For certain
combinations of n and constraint_length, a larger number for
bmgwide must be specified. When the decoder is reset, all metrics are set
to zero. When any metric reaches a value where overflow can occur, all
metrics are normalized (see normalization).bmgwide must be greater
than (softbits + 7 bits).
N
The number of coded bits, n. For every bit to be encoded, ni bits are
output. If you have specified the multiple code set option, there are up to
5 different ni parameters, which can be in any order. n can take any
integer value from 2 to 4.
Traceback Type
Traceback type—logic- or memory-based.
Code Set Information (hybrid architecture only)
You can select the code set information that you require (see Figure 7).
Click Next.
36 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Figure 5. Code Set Configuration (Hybrid Architecture)
GA, GB, GC, GD, GE, GF, GG
The generator polynomials. If the multiple code set option is used, a
different set of polynomials is entered in the respective gi group. The
MegaWizard Plug-In provides default values that can be overwritten by
any valid polynomial. The wizard writes them as decimal base, but you
have the option of entering in either decimal or octal base.
N
The number of coded bits, n. For every bit to be encoded, ni bits are
output. If you have specified the multiple code set option, there are up to
5 different ni parameters, which can be in any order. n can take any
integer value from 2 to 7.
Integrated Depuncturing Option
The parallel architecture offers you the option of integrated depuncturing.
Select the number of rates and the puncturing rate that you require (see
Figure 6).
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Viterbi Compiler MegaCore Function User Guide GettingGetting Started
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Getting Started
Figure 6. Puncturing (Parallel Architecture)
Number of Rates
This is set to 1.
Punctured Rate
You can select no puncturing or a value ‘x/y’, where x<y and x/y>1/2.
Puncturing Pattern
The pattern for the selected puncturing rate. A 1 marks the puncturing
position. You can change the MegaWizard specified value.
Test Data Settings
The MegaWizard Plug-In Manager creates a TCL script for the ModelSim
software (see “Simulating in the ModelSim Simulation Tool” on page 41).
This script maps the ModelSim libraries provided (Viterbi and Lpm), and
compiles the testbench provided, the wrapper, and wizard-produced
testbench. You can use the script to initialize a simulation with your
parameters. Enter the test data settings for the script (see Figure 7). Click
Next.
38 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Figure 7. Test Data Settings
Number of Test Bits
The number of test bits, minimum value constraint_length.
Noise Ratio dB
The signal to noise ratio.
Block Size to Simulate (Hybrid Block Architecture only)
The size of the block, which must be less than the traceback length.
Code Set to Simulate (Multiple Code Set Option only)
Specify which code set you want to simulate.
Puncturing Pattern
For the hybrid architecture you can specify punctured data for testing. For
the parallel architecture the wizard takes the previously specified
puncturing pattern.
Test Target
Select either test BER or test node sync (node synchronization option
only), to test the BER or node synchronization feature.
Altera Corporation 39
Viterbi Compiler MegaCore Function User Guide GettingGetting Started
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Getting Started
Completing the Custom Function
To complete your custom function, perform the following steps.
1. The wizard selects the product order code for your chosen Viterbi
core (see Figure 8). Click Next.
Figure 8. Product Order Code
2. The final screen lists the design files that the wizard creates (see
Figure 9). Click Finish.
40 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Figure 9. Design Files
3. When you click Finish, the wizard asks if you want to execute the
synthesis TCL script. Select OK to start synthesis. If you select No,
you must run the MegaWizard Plug-In again to start synthesis.
4. Select your targeted device options for synthesis in the
LeonardoSpectrum-Altera synthesis tool (see Figure 10). Click Run.
Altera Corporation 41
Viterbi Compiler MegaCore Function User Guide GettingGetting Started
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Getting Started
Figure 10. Selecting Options for Synthesis in the LeonardoSpectrum-Altera
Synthesis Tool
When you have created your custom megafunction, you can integrate it
into your system design and compile.
Simulating in
the ModelSim
Simulation Tool
The following steps explain how to simulate the VHDL model of your
design in the ModelSim simulation tool.
1. Open the ModelSim simulation tool. Select Change Directory (File
menu) and change the folder to <folder name>.
2. Select Execute Macro (Macro menu). Select the file <variation
name>_vsim_script.tcl (see Figure 11) and click Open.
42 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
Figure 11. Selecting wizard_vsim.tcl
This TCL script performs the following functions:
■Maps the provided Viterbi and Lpm libraries
■Compiles your design wrapper, the provided bench and the top-level
testbench with your parameters
■Executes vsim and opens a wave window with the bench signals
If you selected the BER option, when the simulation is finished the
decoded bits are output to the file decoded.txt. The bits originally
transmitted are in the file tranbits.txt.
If you selected node synchronization option, the wave form display
shows how the core regains node synchronization.
Simulating using the Visual IP Model in the ModelSim Software
Altera provides a Visual IP model, which you can use with an alternative
simulator.
This section describes how to simulate the model using the ModelSim
software on Windows NT. For other simulators or operating systems,
refer to the Installing the Visual IP Software Application Note
(vip_installug.pdf), which covers a range of simulators.
Altera Corporation 43
Viterbi Compiler MegaCore Function User Guide GettingGetting Started
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Getting Started
Follow the instructions below to obtain the Visual IP software via the
Internet. If you do not have Internet access, you can obtain the Visual IP
software from your local Altera representative.
1. Point your web browser at
http://www.altera.com/products/ip/ipm-index.html.
2. In the IP MegaSearch keyword field type Functional
Simulation.
3. Click the link for the download icon.
4. Follow the online instructions to download the function and save it
to your hard disk.
Follow the instructions below to use the Visual IP software.
1. Ensure the appropriate ModelSim and Visual IP bin directories are in
the path, e.g.,:
c:\modeltech\win32pe;c:\progra~1\visualIP\bin;
2. Extract your Visual IP model to a suitable location, e.g.,
c:\Megacore\viterbi_compiler\. Set an environment variable to
point to the appropriate directory into which the Visual IP model has
been extracted, e.g.,:
set VIP_MODELS_DIR =
C:\Megacore\viterbi_compiler\sim_lib\visualIP\
3. Start the ModelSim software, select Change Directory (File menu),
and change the directory to your working directory for the
simulator.
4. Create a new working library in this directory by selecting Create a
New Library (Design menu). Select a new library and a logical
mapping to it and type work in the Library field. Click OK.
44 Altera Corporation
Getting Started Viterbi Compiler MegaCore Function User Guide
5. The ModelSim software creates a settings file, modelsim.ini, in the
working directory. Open this file in a text editor and search for the
string veriuser. You should find the following line:
; Veriuser = veriuser.sl
Remove the semi-colon (otherwise the line is treated as a comment
and ignored) and change the directory name to where you Visual IP
is installed, e.g.,:
Veriuser = c:\progra~1\visualIP\bin\libplimtivip
Save the modelsim.ini file and return to the ModelSim software.
6. Compile the wrapper for the model. The Verilog version of the
wrapper is found in the
$VIP_MODELS_DIR\<model_name>\interface\pli directory; the
corresponding VHDL version is in the $VIP_MODELS_DIR
\<model_name>\interface\mti directory. For example, to compile
the Verilog wrapper from the ModelSim command line, enter the
following command:
vlog
{$VIP_MODELS_DIR/<model_name>/interface/pli/<model
_name>.v}
where <model_name> is aukv_hyb_top_cnt, aukv_hyb_top_blk or
aukv_par_top_cnt.
The Visual IP model is now ready for use in your simulator.
Configuring a
Device
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera device. If you are evaluating the MegaCore
function with the OpenCore feature, you must license the function before
you can generate configuration files.
