Brochure - Altera Corporation

Signal Processing Solutions for System-on-a

Programmable-Chip Designs

Signal Processing IP

Megafunctions

May 2001

Altera Corporation

Signal Processing IP: Proven

Performance in One Portfolio

Wireless and digital signal processing (DSP)

engineers face a difficult challenge: to

design communications infrastructure

systems with increasing performance requirements, and

rapid technology changes. Altera® signal processing

intellectual property (IP) megafunctions are a complete

portfolio of proven, high-performance standard functions

created to help engineers meet these design challenges

and implement a solution using a single Altera

programmable logic device (PLD). Each function in the

portfolio—including MegaCore® and Altera Megafunction

Partners Program (AMPPSM) functions—has been rigorously

tested and meets the exacting requirements of IEEE and

world wide communications standards. Today, millions of

business users and consumers are powered by Altera’s

signal processing IP.

You can download signal processing IP functions

from the IP MegaStore™ web site at

http://www.altera.com/IPmegastore. The functions have

a user-friendly, wizard-driven graphical user interface

(GUI) that provides an intuitive, flexible environment to

customize the IP to meet any system’s requirements

(see Figure 1).

A Complete High-Performance

Solution for the DSP Market

Altera provides an extensive portfolio of drop-in DSP

and wireless IP functions. The signal processing

portfolio includes everything you need to build system-

on-a-programmable-chip (SOPC) solutions using high-

performance, high-throughput signal coding schemes,

modulation functions, and traditional signal

processing algorithms.

You can choose blocks of IP from the comprehensive

signal processing portfolio of standard functions to create

an entire SOPC. Alternatively, you can use individual

signal processing IP functions in systems that need

focused performance enhancements. All signal processing

IP is reusable; you can instantiate each function multiple

times in different designs.

Hardware Acceleration for Existing Designs

Signal processing IP can be integrated easily into the

datapath as a pre- and post-processor to implement

computationally rigorous routines, leaving the DSP

processor at the center of the original design. Adding a

high-performance PLD to attack bottlenecks at both ends

of existing processes allows DSP software engineers to

leverage existing software code while enjoying the PLD

benefits of hardware acceleration (see Figure 2).

Signal Coding

Altera provides a variety of signal coding functions for

encryption, forward error correction (FEC), and cyclic

redundancy code (CRC) checking (see Figure 3).

Encryption

Altera’s data encryption standard (DES) cores are certified

by the National Institute of Standards and Technology

(NIST) and can be used in applications requiring

electronic code book (ECB) or triple-DES encryption.

Using a PLD for encryption makes it easy to implement

DES in any operating mode or to add proprietary pre-

processing to the encryption stream. In addition to the

DES core, Altera has Rijndael, SHA-1, and MD5 cores.

Signal Processing IP Solution Signal Processing IP

Solution

Convolutional

Encoder Reed-

Solomon

Encoder

Processor &

Memory FIR Filter

Figure 2. Hardware Acceleration for DSP Processor Systems

Hardware Acceleration Existing Software Hardware Acceleration

Figure 1. Intuitive GUI for IP Customization

Altera Corporation 3

FEC

When starting a new design, communications systems

engineers must weigh the trade-off between data

reliability and throughput. Using modern FEC techniques,

receivers can correct the data that was corrupted during

signal transmission, thereby increasing the effective data

bandwidth, as shown in Figure 4.

Reed-Solomon: Reed-Solomon is an advanced error

correction technique that is widely used in data

communication, storage, and mobile computing. The

efficient Reed-Solomon algorithm uses polynomials to add

redundancy to the transmitted data. Implementing Reed-

Solomon functionality using DSP processors is expensive

and unsuitable for high-performance applications. The

signal processing IP portfolio provides a wide range of

Reed-Solomon encoders and decoders, including discrete,

streaming, continuous, and erasures-support. Implemented

in an Altera PLD, the parameterized Reed-Solomon

solution can provide 10-Mbps throughput at a cost of less

than $2, or high-performance Reed-Solomon decoding at

up to 900 Mbps for less than $80 (using an EP20K100E

device operating at 92 MHz).

Viterbi: High-performance, area-optimized 100-Mbps

Viterbi decoding (or convolutional decoding) with flexible

constraint lengths, soft bits, and traceback length can be

implemented in an Altera PLD for less than $20 per

device. As with all signal processing functions,

performance is not compromised; the maximum data

throughput is increased from a typical DSP processor rate

of 1 Mbps to over 100 Mbps.

Turbo: Specified by the third-generation partnership

project (3GPP) for third-generation wireless infrastructure,

turbo convolutional codes are complex and

difficult to easily implement on any DSP

processors. However, Altera’s signal processing

solution allows designers to easily implement

turbo convolutional codes. Supporting data rates

in excess of 2 Mbps, the turbo decoder features a

max-logMAP algorithm for maximum error

correction and includes a 3GPP-compliant

interleaver. Altera is the first PLD vendor to offer

3GPP-compliant turbo encoders and decoders as off-the-

shelf mainstream products.

CRC & Other Coding Techniques

Altera provides general-purpose functions such as cyclic

redundancy code (CRC) checkers and specialized

application-specific coding techniques such as color

space converters.

Hardware DSP Blocks

Signal processing hardware DSP blocks include filter

transform functions and basic building blocks, as shown

in Figure 5.

Filters

Digital filters such as finite impulse response (FIR) and

infinite impulse response (IIR) filters offer more than 10

times the performance of DSP processors when

implemented in PLDs. Altera’s FIR compiler and IIR

Figure 4. Signal Coding Block Diagram

Outer

Encoding

Encryption/

CRC/FEC

Data

In Inner

Encoding

FEC

Inner

Decoding

FEC

Outer

Decoding

Decryption/

CRC/FEC

Data

Out

Noisy

Channel

Forward

Error

Correction

Encryption

Cyclic

Redundancy

Code Check

Mappers Numerically

Controlled

Oscillator

QPSK &

QAM

Basic Math

Functions Filters

Transforms

Signal Coding Hardware DSP Blocks

Comparator &

Shift

Registers

Modulation Antenna

Figure 3. Typical Transmitter Using Signal Processing IP

compiler signal processing functions reduce the design

time from weeks to hours.

Fast Fourier Transform Functions

Traditionally performed by DSP processors, complex

functions can be performed in PLDs using parallel

instantiations to take advantage of hardware acceleration.

The Altera signal processing portfolio contains several

parameterizable functions to integrate your design on

one PLD.

Basic Building Blocks

Basic building blocks such as adders, multipliers,

counters, comparators, and dividers are available through

the standard library of parameterized modules (LPM).

Parameterizable LPM functions can be instantiated easily

using the MegaWizard® Plug-In manager.

Modulation & Demodulation

Designing modulators and demodulators such as

quadrature amplitude modulation (QAM), m-ary phase

shift keying (MPSK), and differential phase shift keying

(DPSK) are easy using Altera’s FIR compiler, constellation

mapper/demapper, and numerically-controlled oscillator

(NCO) functions. Altera provides reference designs for

direct digital synthesis (DDS) and QAM, that can be easily

modify to meet customized specifications. Using

programmable logic to implement your modulation

scheme lets you test your design in hardware the day

you build the design.

Using the power of digital logic, signals can be cleanly

modulated to an intermediate frequency (IF), digitally

filtered, and readied for transmission. Single-chip

integration of the modulator and the ability to integrate

signal coding techniques and customized logic onto the

same PLD provide faster design cycles and higher

performance, as well as power and board space savings.

Integrated Design Environment

Altera provides an integrated design environment to

streamline your design flow.

Set Parameters with MegaWizard Plug-Ins

Altera MegaWizard Plug-Ins provide a GUI

for customizing IP and integrating it into

your design flow using any EDA tool. The

plug-ins graphically demonstrate the

functionality of the IP and allow easy customization of

new designs or easy modification of existing designs, as

shown in figure 6. With MegaWizard Plug-Ins, you can

efficiently customize functions in your own design

environment, saving time and money.

Both Altera and AMPP partners offer parameterized

functions with MegaWizard Plug-Ins. For a demonstration

of various MegaWizard Plug-Ins, visit the signal

processing page on the IP MegaStore web site.

Third-Party System-Level DSP Tools

Signal processing IP integrates easily into any EDA or

third-party system-level DSP design tool flow. The

Mega Wizard Plug-Ins output graphical symbols or Altera

Hardware Description Language (AHDL), VHDL, or Verilog

HDL files for easy integration into custom designs. They

also generate high-level simulation output files for the

MATLAB and Simulink software as well as and VHDL or

Verilog HDL simulation models.

Altera Corporation

I-Input

Q-Input

xin

phi_inc

cosine

sine

yout

xin yout

Altera FIR Raised Cosine Filter

Altera FIR Raised Cosine Filter1

Cosine_mult

SIne_mult

QAM Signal

NCO

Carrier Phase

Increment

Figure 5. QAM Reference Design Using Altera FIR & NCO IP

Figure 6. IIR Compiler MegaWizard Plug-Ins

Altera Corporation 5

Easy Verification

As with all advanced designs, the verification process is

essential. To verify the functionality of any IP, the Altera

Quartus® II and MAX+PLUS® II software tools generate

post place-and-route VHDL or Verilog HDL netlist files

that can be imported into any simulation tool.

Altera also provides functional simulation models,

allowing you to test the IP prior to synthesis. You can

download the functional simulation models from the

IP MegaStore site.

To facilitate the verification process, system simulation

models for MATLAB and Simulink are provided with

many of the cores. These models, which reflect the

parameters you set, can be run in these popular DSP

design tools with a few simple keystrokes (see Figure 7).

Test-Drive Functions Risk-Free

Altera offers a no-risk MegaCore function

evaluation through the OpenCore®

feature. The OpenCore feature lets you

compile and simulate IP using the

Quartus II or MAX+PLUS II software. You can verify the

functionality of the IP quickly and easily, as well as

evaluate the size and speed of the IP before making a

purchase decision. After licensing the IP, you can output

EDIF, VHDL, and Verilog HDL netlist files, and create

programming or configuration files for Altera PLDs.

You can download all IP functions from the IP MegaStore

site for evaluation. Simply search for the desired IP and

follow the download instructions.

Development Boards

Board-level verification is essential to successful IP

design. To support the development and verification of

SOPC designs, Altera and its partners provide a variety

of development and prototyping boards that speed

system design by allowing application software

development to begin concurrently with hardware

development. Additionally, hardware designers can

verify IP functionality quickly and effectively. A

complete listing of development boards can be found

on the IP MegaStore web site.

Signal Processing IP Applications

Signal processing IP functions are ideal for high-

performance, high-throughput applications. These

applications, which would normally require several DSP

processors, can be placed into a single highly flexible,

high-performance PLD.

Wired

Signal processing IP are ideal for communications

applications requiring high throughput such as DSL

access multiplexers (DSLAMs), or those requiring flexible

modulation schemes such as cable broadcasting. Media

storage applications, such as mass storage (magnetic or

optical), digital video disc, and digital tape applications

require robust FEC algorithms.

Wireless & Broadband

The signal processing communications solution is ideal for

the rigorous high-throughput requirements of wireless and

broadband applications. The performance advantages of

parallel processing coupled with the traditional flexibility

of programmable logic make signal processing IP ideal for

emerging areas such as third-generation wireless, digital

audio and video broadcasting, multi-channel multipoint

distribution services (MMDS), and orthogonal frequency

division multiplexing (OFDM) systems.

Using IP, designers can quickly adapt to changing

standards such as the Wireless 802.11a, Wireless Broadband

Working Group 802.16, and HiperLAN/2. The building

blocks for these applications require FEC, modulation,

OpenCore

Figure 7. MATLAB/Simulink Interface

filtering, and encryption—all areas addressed by Altera’s

signal processing portfolio.

10-Gbps Solution for ITU-T G.709

ITU-T G.709 defines the network node interface for the

optical transport network operating at 2.5, 10, and

40 Gbps, and specifies the use of a Reed-Solomon

FEC section.

Altera has a 10-Gbps single-chip solution available today.

The Altera continuous Reed-Solomon decoder runs at over

96 MHz, yielding 760-Mbps throughput. Altera’s signal

processing Reed-Solomon decoder is able to achieve

2.5 Gbps by using Reed-Solomon decoder cores in

parallel—each decoder is positioned to process every

fourth code word.

The Reed-Solomon continuous decoder requires 2,460 logic

elements (LEs) and 2 embedded system blocks (ESBs). With

the addition of buffer memory and minimal control logic,

Altera’s Reed-Solomon core enables 2.7-Gbps throughput

for 10,500 LEs and 36 ESBs. This solution easily fits into

an APEX™ EP20K300E device.

Further leveraging the advantages of dedicated hardware,

Altera’s signal processing Reed-Solomon decoder can

implement 10-Gbps throughput in only 80% of a single

APEX EP20K1500E.

OFDM

OFDM has recently surged in popularity for wireless

systems. Broadcast applications such as terrestrial digital

video broadcast, digital audio broadcast (DAB), and

“last-mile” connectivity applications such as MMDS

and wireless local area networks have all adopted and

standardized behind OFDM as the modulation method

of choice.

With a high-performance, parameterizable fast Fourier

transform (FFT), as well as Reed-Solomon and Viterbi

functions, Altera’s signal processing IP portfolio contains

all the major blocks required to implement an OFDM

system, as shown in Figure 8.

Proven Solutions

Examples of complete systems using IP from the signal

processing portfolio include:

■Third-generation wireless CDMA basestations

■Digital video basestations

■Wireless broadband modems

■Global system for mobile communication (GSM)-Edge

basestations

■DSP prototyping platforms

■MMDS basestations

■Professional DVD recorders

■Multimedia satellite ground stations

■VDSL modems

■Video processing systems

■Local multipoint distribution service (LMDS)

basestations

Performance Advantages over DSP Processors

Programmable logic offers compelling performance

advantages over DSP processors. Programmable logic can

be thought of as an array of elements, each of which can

be configured as a complex processor routine. These

processor routines can then be linked together in serial

(the same way a DSP processor would execute them), or

they can be connected in parallel. In parallel, they offer

many times the performance of a DSP processor by

executing hundreds of instructions at once. Algorithms

that benefit from this type of performance increase

include FEC, modulation/demodulation, and encryption

(see Figure 9).

Time-to-Market Advantages over ASICs & ASSPs

A company with a new product typically makes 50% of

its profit in the first six months of production, before

competition enters and drives down prices. ASIC

Altera Corporation

Forward

Error

Correction

Coder

Buffer DAC

Cyclic

Prefix

Insertion

Shaper

FIR

Filter

Constellation

Mapper

Inverse

Fast

Fourier

Transform

Parallel

Serial

Interleaver

OFDM Modulator

Data In

Figure 8. Complete System Solution For a Typical OFDM Transmitter

= Altera IP Solution = Altera PLD Solution = Non-PLD Solution

Altera Corporation 7

implementations provide the same performance as

functions implemented in programmable logic, but

development lead times can stretch out up to one year

from design start. This programmable logic solution

shortens development time, improving time-to-market.

Flexibility

System specification changes, bug

fixes, or additional customer

requirements can obsolete an

expensive ASIC. With programmable

logic, systems can be upgraded in

the field, eliminating costly recalls

and lost sales.

IP MegaStore

Altera’s IP MegaStore web site

(http://www.altera.com/IPmegastore)

features information on IP

technology and system overviews and

provides a searchable list of IP

available from Altera and its AMPP

partners. Literature, board-level

demonstrations, simulation models, and IP evaluation

tools are available on the site (see Table 1).

Traditional DSP Processor

Serial Operation

Programmable Logic Device

Parallel Operation

Sequential (Serial) Operation Parallel Operation

1 ClockN Clocks

DSP Engine

Memory

Figure 9. Signal Processing IP Advantage

FUNCTION SOURCE PRODUCT FAMILY

Color Space Converter (PLSM-CSC) Altera Corporation APEX, APEX II, FLEX®, ACEX™, Mercury™

FIR Filter Compiler (PLSM-FIR) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Numerically Controlled Oscillator Compiler (PLSM-NCO) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Cyclic Redundancy Code Checker (PLSM-CRC) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Symbol Interleaver/Deinterleaver (PLSM-INLV) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Reed-Solomon Compiler, Encoder (PLSM-RSENC) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Reed-Solomon Compiler, Decoder (PLSM-RSDEC2) Altera Corporation APEX, APEX II, FLEX 10K, ACEX, Mercury

Turbo Encoder Function (PLSM-TURBO/ENC) Altera Corporation APEX, APEX II, Mercury

Turbo Decoder Function (PLSM-TURBO/DEC) Altera Corporation APEX, APEX II, APEX II, Mercury

Viterbi Compiler, High-Speed Parallel Decoder (PLSM-HC-VITERBI/HS) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Viterbi Compiler, Low-Speed/Hybrid Serial Decoder (PLSM-HC-VITERBI/SS) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Table 1. Signal Processing IP Functions

FFT/IFFT Processor (PLSM-HC-FFT) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

IIR Compiler (PLSM-IIR) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

Constellation Mapper/Demapper (PLSM-SYMMAP) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

8b10b Encoder & Decoder (PLSM-ED8BIOB) Altera Corporation APEX, APEX II, FLEX, ACEX, Mercury

ARCTAN HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

Hadamard Transform Processor (PLSM-HADAMARD) HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

Reed-Solomon Decoder Minicore (PLSM-RSDEC/MINI) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury

High-Speed Rijndael Encryption/Decryption (PLSM-RIJNDAEL/HS) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury

Low-Speed Rijndael Encryption/Decryption (PLSM-RIJNDAEL/LS) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury

Secure Hash Algorithm (PLSM-SHA1) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury

Message Digest Algorithm (PLSM-MD5) HammerCores by Altera APEX, APEX II, FLEX 10K, ACEX, Mercury

Adaptive Equalizer (PLSM-HC-EQUALIZER) HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

Altera Offices

Altera Corporation Altera European Headquarters Altera Japan Ltd. Altera International Ltd.

101 Innovation Drive Holmers Farm Way Shinjuku i-Land Tower 32F 2102 Tower 6

San Jose, CA 95134 High Wycombe 5-1, Nishi-Shinjuku, 6-Chome The Gateway, Harbour City

USA Buckinghamshire Shinjuku-ku, Tokyo 163-1332 9 Canton Road,

Telephone: (408) 544-7000 HP12 4XF Japan Tsimshatsui Kowloon

http://www.altera.com United Kingdom Telephone: (81) 3 3340 9480 Hong Kong

Telephone: (44) 1 494 602 000 http://www.altera.com/japan Telephone: (852) 2945 7000

MegaWizard, OpenCore, Quartus, Quartus II, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries.

FUNCTION SOURCE PRODUCT FAMILY

CORDIC HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

U-Law and A-Law Companders HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

Logarithm Function HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

Square Root Function HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

DES Encryption Processor (PLSM-HC-DES) HammerCores by Altera APEX, APEX II, FLEX, ACEX, Mercury

Discrete Cosine Transform Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

FFT/IFFT High Performance 64-Point Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

FFT/IFFT Low Latency 64-Point Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Floating-Point Operator Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Image Processing Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Laplacian Edge Detector Amphion Semiconductor Ltd. APEX, APEX II, FLEX 10KA, Mercury

Rank Order Filter Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

JPEG Encoder & Decoder Functions Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Adaptive Filters Amphion Semiconductor Ltd. APEX, APEX II, FLEX 10K, Mercury

FIR Filter, Cascadable, Adaptive Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Convolutional Encoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX 6000, Mercury

DVB FEC Codec Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

FIR Filter Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

IIR Filter Library Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Multi-Standard ADPCM Encoder/Decoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

QPSK Equalizer Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Reed-Solomon Decoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Reed-Solomon Encoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Viterbi Decoder Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Convolutional Interleaver Ktech Telecommunications, Inc. APEX, APEX II, FLEX, MAX®, Mercury

Complex Multiplier/Mixer Nova Engineering, Inc. APEX, APEX II, FLEX, Mercury

Linear Feedback Shift Register Nova Engineering, Inc. APEX, APEX II, FLEX, MAX, Mercury

Binary Pattern Correlator Nova Engineering, Inc. APEX, APEX II, FLEX, Mercury

Digital Modulator Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury

Digital IF Receiver Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury

Early-Late-Gate Symbol Synchronizer Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury

Numerically Controlled Oscillator Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury

Viterbi Decoder (Dual Constraint Length) Nova Engineering, Inc. APEX, APEX II, FLEX, ACEX, Mercury

TC1000 Turbo Decoder TurboConcept APEX, APEX II, FLEX, ACEX, Mercury

Turbo Product Code TurboConcept APEX, APEX II, FLEX, ACEX, Mercury

Table 1. Signal Processing IP Functions (continued from page 7)

VCO BIST Jitter Measurement Function Fluence Technology APEX, APEX II, FLEX, ACEX, Mercury

DES (X_DES) Digital Encryption Function CAST Inc. APEX, APEX II, FLEX, ACEX, Mercury

DES Encryption Core Sciworx APEX, APEX II, FLEX, ACEX, Mercury

FFT 256-Point Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Convolutional Interleaver Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Adaptive Equalizer Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Sync Detector Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury

Trellis-Coded Modulator Amphion Semiconductor Ltd. APEX, APEX II, FLEX, ACEX, Mercury