MT41K128M16JT-125 IT:K TR - MICRON TECHNOLOGY

DDR3L SDRAM

MT41K512M4 – 64 Meg x 4 x 8 banks

MT41K256M8 – 32 Meg x 8 x 8 banks

MT41K128M16 – 16 Meg x 16 x 8 banks

Description

The 1.35V DDR3L SDRAM device is a low-voltage ver-

sion of the 1.5V DDR3 SDRAM device. Refer to the

DDR3 (1.5V) SDRAM data sheet specifications when

running in 1.5V compatible mode.

Features

• VDD = VDDQ = 1.35V (1.283–1.45V)

• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• TC of 95°C

– 64ms, 8192-cycle refresh up to 85°C

– 32ms, 8192-cycle refresh at >85°C to 95°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multipurpose register

• Output driver calibration

Options Marking

• Configuration

– 512 Meg x 4 512M4

– 256 Meg x 8 256M8

– 128 Meg x 16 128M16

• FBGA package (Pb-free) – x4, x8

– 78-ball (8mm x 10.5mm x 1.2mm)

Rev. K DA

• FBGA package (Pb-free) – x16

– 96-ball (8mm x 14mm x 1.2mm)

Rev. K

• Timing – cycle time

– 1.07ns @ CL = 13 (DDR3-1866) -107

– 1.25ns @ CL = 11 (DDR3-1600) -125

– 1.5ns @ CL = 9 (DDR3-1333) -15E

– 1.875ns @ CL = 7 (DDR3-1066) -187E

• Operating temperature

– Commercial (0°C ≤ TC ≤ +95°C) None

– Industrial (–40°C ≤ TC ≤ +95°C) IT

• Revision :K

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)

-1071, 2, 3 1866 13-13-13 13.91 13.91 13.91

-1251, 2 1600 11-11-11 13.75 13.75 13.75

-15E11333 9-9-9 13.5 13.5 13.5

-187E 1066 7-7-7 13.1 13.1 13.1

Notes: 1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16

Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks

Refresh count 8K 8K 8K

Row address 32K A[14:0] 32K A[14:0] 16K A[13:0]

Bank address 8 BA[2:0] 8 BA[2:0] 8 BA[2:0]

Column address 2K A[11, 9:0] 1K A[9:0] 1K A[9:0]

Figure 1: DDR3L Part Numbers

Package

78-ball 8mm x 10.5mm FBGA

Example Part Number: MT41K256M8DA-107:K

96-ball 8mm x 14mm FBGA

Configuration

512 Meg x 4

256 Meg x 8

128 Meg x 16

512M4

256M8

128M16

Speed Grade

tCK = 1.071ns, CL = 13

tCK = 1.25ns, CL = 11

tCK = 1.5ns, CL = 9

tCK = 1.87ns, CL = 7

-107

-125

-15E

-187E

ConfigurationMT41K Package Speed

Revision

Temperature

Commercial

Industrial temperature

{

None

Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:

http://www.micron.com.

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.

Contents

Important Notes and Warnings ....................................................................................................................... 12

State Diagram ................................................................................................................................................ 13

Functional Description ................................................................................................................................... 14

Industrial Temperature ............................................................................................................................... 14

General Notes ............................................................................................................................................ 14

Functional Block Diagrams ............................................................................................................................. 16

Ball Assignments and Descriptions ................................................................................................................. 18

Package Dimensions ....................................................................................................................................... 24

Electrical Specifications .................................................................................................................................. 26

Thermal Characteristics .................................................................................................................................. 38

Electrical Specifications – IDD Specifications and Conditions ............................................................................ 40

Electrical Characteristics – IDD Specifications .................................................................................................. 51

Electrical Specifications – DC and AC .............................................................................................................. 52

DC Operating Conditions ........................................................................................................................... 52

Input Operating Conditions ........................................................................................................................ 53

DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 57

DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 61

DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 63

ODT Characteristics ....................................................................................................................................... 64

1.35V ODT Resistors ................................................................................................................................... 65

ODT Sensitivity .......................................................................................................................................... 66

ODT Timing Definitions ............................................................................................................................. 66

Output Driver Impedance ............................................................................................................................... 70

34 Ohm Output Driver Impedance .............................................................................................................. 71

DDR3L 34 Ohm Driver ................................................................................................................................ 72

DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 73

DDR3L Alternative 40 Ohm Driver ............................................................................................................... 74

DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 74

Output Characteristics and Operating Conditions ............................................................................................ 76

Reference Output Load ............................................................................................................................... 79

Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 79

Slew Rate Definitions for Differential Output Signals .................................................................................... 81

Speed Bin Tables ............................................................................................................................................ 82

Electrical Characteristics and AC Operating Conditions ................................................................................... 86

Command and Address Setup, Hold, and Derating .......................................................................................... 104

Data Setup, Hold, and Derating ...................................................................................................................... 111

Commands – Truth Tables ............................................................................................................................. 120

Commands ................................................................................................................................................... 123

DESELECT ................................................................................................................................................ 123

NO OPERATION ........................................................................................................................................ 123

ZQ CALIBRATION LONG ........................................................................................................................... 123

ZQ CALIBRATION SHORT .......................................................................................................................... 123

ACTIVATE ................................................................................................................................................. 123

READ ........................................................................................................................................................ 123

WRITE ...................................................................................................................................................... 124

PRECHARGE ............................................................................................................................................. 125

REFRESH .................................................................................................................................................. 125

SELF REFRESH .......................................................................................................................................... 126

DLL Disable Mode ..................................................................................................................................... 127

Input Clock Frequency Change ...................................................................................................................... 131

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Write Leveling ............................................................................................................................................... 133

Write Leveling Procedure ........................................................................................................................... 135

Write Leveling Mode Exit Procedure ........................................................................................................... 137

Initialization ................................................................................................................................................. 138

Voltage Initialization/Change ........................................................................................................................ 140

VDD Voltage Switching ............................................................................................................................... 141

Mode Registers .............................................................................................................................................. 142

Mode Register 0 (MR0) ................................................................................................................................... 143

Burst Length ............................................................................................................................................. 143

Burst Type ................................................................................................................................................. 144

DLL RESET ................................................................................................................................................ 145

Write Recovery .......................................................................................................................................... 146

Precharge Power-Down (Precharge PD) ...................................................................................................... 146

CAS Latency (CL) ....................................................................................................................................... 146

Mode Register 1 (MR1) ................................................................................................................................... 148

DLL ENABLE/DISABLE .............................................................................................................................. 148

Output Drive Strength ............................................................................................................................... 149

OUTPUT ENABLE/DISABLE ...................................................................................................................... 149

TDQS ENABLE .......................................................................................................................................... 149

On-Die Termination (ODT) ........................................................................................................................ 150

WRITE LEVELING ..................................................................................................................................... 150

Posted CAS Additive Latency (AL) ............................................................................................................... 150

Mode Register 2 (MR2) ................................................................................................................................... 152

CAS WRITE Latency (CWL) ........................................................................................................................ 152

AUTO SELF REFRESH (ASR) ....................................................................................................................... 153

SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 153

SRT versus ASR .......................................................................................................................................... 154

Dynamic On-Die Termination (ODT) ......................................................................................................... 154

Mode Register 3 (MR3) ................................................................................................................................... 155

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 155

MPR Functional Description ...................................................................................................................... 156

MPR Address Definitions and Bursting Order .............................................................................................. 157

MPR Read Predefined Pattern .................................................................................................................... 162

MODE REGISTER SET (MRS) Command ........................................................................................................ 162

ZQ CALIBRATION Operation ......................................................................................................................... 163

ACTIVATE Operation ..................................................................................................................................... 164

READ Operation ............................................................................................................................................ 166

WRITE Operation .......................................................................................................................................... 177

DQ Input Timing ....................................................................................................................................... 185

PRECHARGE Operation ................................................................................................................................. 187

SELF REFRESH Operation .............................................................................................................................. 187

Extended Temperature Usage ........................................................................................................................ 189

Power-Down Mode ........................................................................................................................................ 190

RESET Operation ........................................................................................................................................... 198

On-Die Termination (ODT) ............................................................................................................................ 200

Functional Representation of ODT ............................................................................................................. 200

Nominal ODT ............................................................................................................................................ 200

Dynamic ODT ............................................................................................................................................... 202

Dynamic ODT Special Use Case ................................................................................................................. 202

Functional Description .............................................................................................................................. 202

Synchronous ODT Mode ................................................................................................................................ 208

ODT Latency and Posted ODT .................................................................................................................... 208

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.

Timing Parameters .................................................................................................................................... 208

ODT Off During READs .............................................................................................................................. 211

Asynchronous ODT Mode .............................................................................................................................. 213

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 215

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 217

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 219

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Figures

Figure 1: DDR3L Part Numbers ........................................................................................................................ 2

Figure 2: Simplified State Diagram ................................................................................................................. 13

Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 16

Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 17

Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 17

Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 18

Figure 7: 96-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 19

Figure 8: 78-Ball FBGA – x4, x8 (DA) ............................................................................................................... 24

Figure 9: 96-Ball FBGA – x16 (JT) ................................................................................................................... 25

Figure 10: Thermal Measurement Point ......................................................................................................... 39

Figure 11: DDR3L 1.35V Input Signal .............................................................................................................. 56

Figure 12: Overshoot ..................................................................................................................................... 57

Figure 13: Undershoot ................................................................................................................................... 58

Figure 14: VIX for Differential Signals .............................................................................................................. 59

Figure 15: Single-Ended Requirements for Differential Signals ........................................................................ 59

Figure 16: Definition of Differential AC-Swing and tDVAC ............................................................................... 60

Figure 17: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 62

Figure 18: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .............. 63

Figure 19: ODT Levels and I-V Characteristics ................................................................................................ 64

Figure 20: ODT Timing Reference Load .......................................................................................................... 67

Figure 21: tAON and tAOF Definitions ............................................................................................................ 68

Figure 22: tAONPD and tAOFPD Definitions ................................................................................................... 68

Figure 23: tADC Definition ............................................................................................................................. 69

Figure 24: Output Driver ................................................................................................................................ 70

Figure 25: DQ Output Signal .......................................................................................................................... 77

Figure 26: Differential Output Signal .............................................................................................................. 78

Figure 27: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 79

Figure 28: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 80

Figure 29: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 81

Figure 30: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 107

Figure 31: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 108

Figure 32: Tangent Line for tIS (Command and Address – Clock) .................................................................... 109

Figure 33: Tangent Line for tIH (Command and Address – Clock) .................................................................... 110

Figure 34: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 116

Figure 35: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 117

Figure 36: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 118

Figure 37: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 119

Figure 38: Refresh Mode ............................................................................................................................... 126

Figure 39: DLL Enable Mode to DLL Disable Mode ........................................................................................ 128

Figure 40: DLL Disable Mode to DLL Enable Mode ........................................................................................ 129

Figure 41: DLL Disable tDQSCK .................................................................................................................... 130

Figure 42: Change Frequency During Precharge Power-Down ........................................................................ 132

Figure 43: Write Leveling Concept ................................................................................................................. 133

Figure 44: Write Leveling Sequence ............................................................................................................... 136

Figure 45: Write Leveling Exit Procedure ....................................................................................................... 137

Figure 46: Initialization Sequence ................................................................................................................. 139

Figure 47: VDD Voltage Switching .................................................................................................................. 141

Figure 48: MRS to MRS Command Timing (tMRD) ......................................................................................... 142

Figure 49: MRS to nonMRS Command Timing (tMOD) .................................................................................. 143

Figure 50: Mode Register 0 (MR0) Definitions ................................................................................................ 144

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 51: READ Latency .............................................................................................................................. 147

Figure 52: Mode Register 1 (MR1) Definition ................................................................................................. 148

Figure 53: READ Latency (AL = 5, CL = 6) ....................................................................................................... 151

Figure 54: Mode Register 2 (MR2) Definition ................................................................................................. 152

Figure 55: CAS WRITE Latency ...................................................................................................................... 153

Figure 56: Mode Register 3 (MR3) Definition ................................................................................................. 155

Figure 57: MPR Block Diagram ...................................................................................................................... 156

Figure 58: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 158

Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 159

Figure 60: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 160

Figure 61: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 161

Figure 62: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 163

Figure 63: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 164

Figure 64: Example: tFAW ............................................................................................................................. 165

Figure 65: READ Latency .............................................................................................................................. 166

Figure 66: Consecutive READ Bursts (BL8) .................................................................................................... 168

Figure 67: Consecutive READ Bursts (BC4) .................................................................................................... 168

Figure 68: Nonconsecutive READ Bursts ....................................................................................................... 169

Figure 69: READ (BL8) to WRITE (BL8) .......................................................................................................... 169

Figure 70: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 170

Figure 71: READ to PRECHARGE (BL8) .......................................................................................................... 170

Figure 72: READ to PRECHARGE (BC4) ......................................................................................................... 171

Figure 73: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 171

Figure 74: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 171

Figure 75: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 173

Figure 76: Data Strobe Timing – READs ......................................................................................................... 174

Figure 77: Method for Calculating tLZ and tHZ ............................................................................................... 175

Figure 78: tRPRE Timing ............................................................................................................................... 175

Figure 79: tRPST Timing ............................................................................................................................... 176

Figure 80: tWPRE Timing .............................................................................................................................. 178

Figure 81: tWPST Timing .............................................................................................................................. 178

Figure 82: WRITE Burst ................................................................................................................................ 179

Figure 83: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 180

Figure 84: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 180

Figure 85: Nonconsecutive WRITE to WRITE ................................................................................................. 181

Figure 86: WRITE (BL8) to READ (BL8) .......................................................................................................... 181

Figure 87: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 182

Figure 88: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 183

Figure 89: WRITE (BL8) to PRECHARGE ........................................................................................................ 184

Figure 90: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 184

Figure 91: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 185

Figure 92: Data Input Timing ........................................................................................................................ 186

Figure 93: Self Refresh Entry/Exit Timing ...................................................................................................... 188

Figure 94: Active Power-Down Entry and Exit ................................................................................................ 192

Figure 95: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 192

Figure 96: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 193

Figure 97: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 193

Figure 98: Power-Down Entry After WRITE .................................................................................................... 194

Figure 99: Power-Down Entry After WRITE with Auto Precharge (WRAP) ........................................................ 194

Figure 100: REFRESH to Power-Down Entry .................................................................................................. 195

Figure 101: ACTIVATE to Power-Down Entry ................................................................................................. 195

Figure 102: PRECHARGE to Power-Down Entry ............................................................................................. 196

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 103: MRS Command to Power-Down Entry ......................................................................................... 196

Figure 104: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 197

Figure 105: RESET Sequence ......................................................................................................................... 199

Figure 106: On-Die Termination ................................................................................................................... 200

Figure 107: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 205

Figure 108: Dynamic ODT: Without WRITE Command .................................................................................. 205

Figure 109: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 206

Figure 110: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 207

Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 207

Figure 112: Synchronous ODT ...................................................................................................................... 209

Figure 113: Synchronous ODT (BC4) ............................................................................................................. 210

Figure 114: ODT During READs .................................................................................................................... 212

Figure 115: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 214

Figure 116: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 216

Figure 117: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 218

Figure 118: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 220

Figure 119: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 220

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 1

Table 2: Addressing ......................................................................................................................................... 2

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 20

Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 22

Table 5: Input/Output Capacitance ................................................................................................................ 26

Table 6: DC Electrical Characteristics and Operating Conditions – 1.35V Operation ......................................... 26

Table 7: DC Electrical Characteristics and Operating Conditions – 1.5V Operation ........................................... 26

Table 8: Input Switching Conditions – Command and Address ........................................................................ 27

Table 9: Input Switching Conditions – DQ and DM ......................................................................................... 27

Table 10: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 28

Table 11: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ...................... 28

Table 12: RTT Effective Impedance ................................................................................................................. 29

Table 13: Reference Settings for ODT Timing Measurements ........................................................................... 30

Table 14: 34Ω Driver Impedance Characteristics ............................................................................................. 30

Table 15: 40Ω Driver Impedance Characteristics ............................................................................................. 30

Table 16: Single-Ended Output Driver Characteristics ..................................................................................... 31

Table 17: Differential Output Driver Characteristics ........................................................................................ 31

Table 18: Electrical Characteristics and AC Operating Conditions .................................................................... 31

Table 19: Derating Values for tIS/tIH – AC160/DC90-Based .............................................................................. 32

Table 20: Derating Values for tIS/tIH – AC135/DC90-Based .............................................................................. 33

Table 21: Derating Values for tIS/tIH – AC125/DC90-Based .............................................................................. 33

Table 22: Minimum Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition .............. 34

Table 23: Derating Values for tDS/tDH – AC160/DC90-Based ........................................................................... 34

Table 24: Derating Values for tDS/tDH – AC135/DC90-Based ........................................................................... 35

Table 25: Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns ............................................................ 36

Table 26: Minimum Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition .......................... 37

Table 27: Thermal Characteristics .................................................................................................................. 38

Table 28: Thermal Impedance ........................................................................................................................ 39

Table 29: DDR3L Timing Parameters Used for IDD Measurements – Clock Units ............................................... 40

Table 30: DDR3L IDD0 Measurement Loop ...................................................................................................... 41

Table 31: DDR3L IDD1 Measurement Loop ...................................................................................................... 42

Table 32: DDR3L IDD Measurement Conditions for Power-Down Currents ....................................................... 43

Table 33: DDR3L IDD2N and IDD3N Measurement Loop .................................................................................... 44

Table 34: DDR3L IDD2NT Measurement Loop .................................................................................................. 44

Table 35: DDR3L IDD4R Measurement Loop .................................................................................................... 45

Table 36: DDR3L IDD4W Measurement Loop .................................................................................................... 46

Table 37: DDR3L IDD5B Measurement Loop .................................................................................................... 47

Table 38: DDR3L IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 ........................................................ 48

Table 39: DDR3L IDD7 Measurement Loop ...................................................................................................... 49

Table 40: IDD Maximum Limits – Die Rev. K .................................................................................................... 51

Table 41: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions .............................................. 52

Table 42: DDR3L 1.35V DC Electrical Characteristics and Input Conditions ..................................................... 53

Table 43: DDR3L 1.35V Input Switching Conditions - Command and Address .................................................. 54

Table 44: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .............................. 55

Table 45: DDR3L Control and Address Pins ..................................................................................................... 57

Table 46: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins ............................................................................. 57

Table 47: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ... 60

Table 48: Single-Ended Input Slew Rate Definition .......................................................................................... 61

Table 49: DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................ 63

Table 50: On-Die Termination DC Electrical Characteristics ............................................................................ 64

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 51: 1.35V RTT Effective Impedance ........................................................................................................ 65

Table 52: ODT Sensitivity Definition .............................................................................................................. 66

Table 53: ODT Temperature and Voltage Sensitivity ........................................................................................ 66

Table 54: ODT Timing Definitions .................................................................................................................. 67

Table 55: DDR3L(1.35V) Reference Settings for ODT Timing Measurements .................................................... 67

Table 56: DDR3L 34 Ohm Driver Impedance Characteristics ........................................................................... 71

Table 57: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ........................................... 72

Table 58: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.35V ..................................... 72

Table 59: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.45V ..................................... 72

Table 60: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.283 ..................................... 73

Table 61: DDR3L 34 Ohm Output Driver Sensitivity Definition ........................................................................ 73

Table 62: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity .................................................. 73

Table 63: DDR3L 40 Ohm Driver Impedance Characteristics ........................................................................... 74

Table 64: DDR3L 40 Ohm Output Driver Sensitivity Definition ........................................................................ 74

Table 65: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 75

Table 66: DDR3L Single-Ended Output Driver Characteristics ......................................................................... 76

Table 67: DDR3L Differential Output Driver Characteristics ............................................................................ 77

Table 68: DDR3L Differential Output Driver Characteristics VOX(AC) ................................................................. 78

Table 69: Single-Ended Output Slew Rate Definition ....................................................................................... 79

Table 70: Differential Output Slew Rate Definition .......................................................................................... 81

Table 71: DDR3L-1066 Speed Bins .................................................................................................................. 82

Table 72: DDR3L-1333 Speed Bins .................................................................................................................. 83

Table 73: DDR3L-1600 Speed Bins .................................................................................................................. 84

Table 74: DDR3L-1866 Speed Bins .................................................................................................................. 85

Table 75: Electrical Characteristics and AC Operating Conditions .................................................................... 86

Table 76: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 96

Table 77: DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based ............... 105

Table 78: DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC160/DC90-Based ................................ 105

Table 79: DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC135/DC90-Based ................................ 105

Table 80: DDR3L-1866 Derating Values for tIS/tIH – AC125/DC90-Based ........................................................ 106

Table 81: DDR3L Minimum Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition . 106

Table 82: DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ....................... 112

Table 83: DDR3L Derating Values for tDS/tDH – AC160/DC90-Based .............................................................. 112

Table 84: DDR3L Derating Values for tDS/tDH – AC135/DC100-Based ............................................................ 112

Table 85: DDR3L Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns ............................................... 114

Table 86: DDR3L Minimum Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition ............. 115

Table 87: Truth Table – Command ................................................................................................................. 120

Table 88: Truth Table – CKE .......................................................................................................................... 122

Table 89: READ Command Summary ............................................................................................................ 124

Table 90: WRITE Command Summary .......................................................................................................... 124

Table 91: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 130

Table 92: Write Leveling Matrix ..................................................................................................................... 134

Table 93: Burst Order .................................................................................................................................... 145

Table 94: MPR Functional Description of MR3 Bits ........................................................................................ 156

Table 95: MPR Readouts and Burst Order Bit Mapping ................................................................................... 157

Table 96: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 189

Table 97: Self Refresh Mode Summary ........................................................................................................... 189

Table 98: Command to Power-Down Entry Parameters .................................................................................. 190

Table 99: Power-Down Modes ....................................................................................................................... 191

Table 100: Truth Table – ODT (Nominal) ........................................................................................................ 201

Table 101: ODT Parameters .......................................................................................................................... 201

Table 102: Write Leveling with Dynamic ODT Special Case ............................................................................. 202

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

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Table 103: Dynamic ODT Specific Parameters ............................................................................................... 203

Table 104: Mode Registers for RTT,nom ............................................................................................................ 203

Table 105: Mode Registers for RTT(WR) ............................................................................................................ 204

Table 106: Timing Diagrams for Dynamic ODT .............................................................................................. 204

Table 107: Synchronous ODT Parameters ...................................................................................................... 209

Table 108: Asynchronous ODT Timing Parameters for All Speed Bins .............................................................. 214

Table 109: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................. 216

2Gb: x4, x8, x16 DDR3L SDRAM

Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

2Gb: x4, x8, x16 DDR3L SDRAM

Important Notes and Warnings

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.

State Diagram

Figure 2: Simplified State Diagram

SRX = Self refresh exit

WRITE = WR, WRS4, WRS8

WRITE AP = WRAP, WRAPS4, WRAPS8

ZQCL = ZQ LONG CALIBRATION

ZQCS = ZQ SHORT CALIBRATION

Bank

active

ReadingWriting

Activating

Refreshing

Self

refresh

Idle

Active

power-

down

calibration

From any

state

Power

applied Reset

procedure

Power

Initial-

ization

MRS, MPR,

write

leveling

Precharge

power-

down

Writing Reading

Automatic

sequence

Command

sequence

Precharging

READ

READ READ

READ AP

PRE, PREA

PRE, PREA PRE, PREA

WRITE

CKE L CKE L

CKE L

WRITE

WRITE AP

PDE

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

ACT = ACTIVATE

MPR = Multipurpose register

MRS = Mode register set

PDE = Power-down entry

PDX = Power-down exit

PRE = PRECHARGE

PREA = PRECHARGE ALL

READ = RD, RDS4, RDS8

READ AP = RDAP, RDAPS4, RDAPS8

REF = REFRESH

RESET = START RESET PROCEDURE

SRE = Self refresh entry

2Gb: x4, x8, x16 DDR3L SDRAM

State Diagram

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is an 8n-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write

operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-

cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data

for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the

data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK

going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-

mand, and address signals are registered at every positive edge of CK. Input data is reg-

istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-

erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-

lected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVATE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVATE command are used to select the bank and row to be accessed. The ad-

dress bits registered coincident with the READ or WRITE commands are used to select

the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM

allows for concurrent operation, thereby providing high bandwidth by hiding row pre-

charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed

–40°C or 95°C. JEDEC specifications require the refresh rate to double when TC exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when TC is < 0°C or

>95°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation).

• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be

interpreted as any and all DQ collectively, unless specifically stated otherwise.

• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as

DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,

x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer

to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1kΩ* resistor.

– Connect UDQS# to VDD via 1kΩ* resistor.

– Connect UDM to VDD via 1kΩ* resistor.

– Connect DQ[15:8] individually to either VSS, VDD, or VREF via 1kΩ resistors,* or float

DQ[15:8].

*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Description

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally

configured as an 8-bank DRAM.

Figure 3: 512 Meg x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

Address

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To pullup/pulldown

networks

READ

drivers DQ[3:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

CK,CK#

DQS, DQS#

ODT

control

ZQ CAL

WE#

RZQ

CK, CK#

RAS#

CAS#

CS#

ODT

CKE

RESET#

CK,CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

BC4

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

A12

VSSQ

OTF

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 4: 256 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

Memory

array

(32,768 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

Read

drivers DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS/DQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

SW1 SW2

VDDQ/2

RTT(WR)

RTT,nom

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

BC4 (burst chop)

BC4

Write

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

Address

A12

VSSQ

OTF

Figure 5: 128 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

SW1 SW2

VDDQ/2

BC4

SW1 SW2

VDDQ/2

RTT,nom RTT(WR)

SW1 SW2

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

VSSQ A12

OTF

VDDQ/2

RTT,nom RTT(WR)

RTT(WR)

RTT,nom

2Gb: x4, x8, x16 DDR3L SDRAM

Functional Block Diagrams

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)

1 2 3 4 6 7 8 95

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

VDD

VSSQ

DQ2

NF, DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

VDD

NF, DQ7

CK#

A10/AP

A12/BC#

A11

A14

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

VSSQ

DQ3

VSS

NF, DQ5

VSS

VDD

VREFCA

BA1

Notes: 1. Ball descriptions listed in Table 3 (page 20) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 7: 96-Ball FBGA – x16 Ball Assignments (Top View)

1 2 3 4 6 7 8 95

VDDQ

VSSQ

VDDQ

VSSQ

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

DQ13

VDD

DQ11

VDDQ

VSSQ

DQ2

DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ15

VSS

DQ9

UDM

DQ0

LDQS

LDQS#

DQ4

RAS#

CAS#

WE#

BA2

A13

DQ12

UDQS#

UDQS

DQ8

LDM

DQ1

VDD

DQ7

CK#

A10/AP

A12/BC#

A11

VDDQ

DQ14

DQ10

VSSQ

DQ3

VSS

DQ5

VSS

VDD

VREFCA

BA1

VSS

VSSQ

VDDQ

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

Notes: 1. Ball descriptions listed in Table 4 (page 22) are listed as “x16.”

2. A comma separates the configuration; a slash defines a selectable function.

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

VREFCA.

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

VREFCA.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to VREFCA.

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to VREFDQ. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to VREFCA.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to VREFCA.

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤

0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to VREFDQ.

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol Type Description

DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are refer-

enced to VREFDQ.

DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write da-

ta. Center-aligned to write data.

TDQS, TDQS# I/O Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled,

DM is disabled, and the TDQS and TDQS# balls provide termination resistance.

VDD Supply Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.

VDDQ Supply DQ power supply: 1.35V, 1.283–1.45V operational; compatible with 1.5V operation.

VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained

at all times (including self refresh) for proper device operation.

VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self re-

fresh) for proper device operation.

VSS Supply Ground.

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

ZQ Reference External reference ball for output drive calibration: This ball is tied to an external

240Ω resistor (RZQ), which is tied to VSSQ.

NC – No connect: These balls should be left unconnected (the ball has no connection to the

DRAM or to other balls).

NF – No function: When configured as a x4 device, these balls are NF. When configured as a

x8 device, these balls are defined as TDQS#, DQ[7:4].

2Gb: x4, x8, x16 DDR3L SDRAM

Ball Assignments and Descriptions

CCMTD-1725822587-7895

2Gb_DDR3L.pdf - Rev. O 09/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A13, A12/BC#,

A11, A10/AP,