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LM124A/LM124JAN Low Power Quad Operational Amplifiers
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1FEATURES DESCRIPTION
The LM124/124A consists of four independent, high
2 Internally Frequency Compensated for Unity gain, internally frequency compensated operational
Gain amplifiers which were designed specifically to operate
Large DC Voltage Gain 100 dB from a single power supply over a wide range of
Wide Bandwidth (Unity Gain)1 MHz voltages. Operation from split power supplies is also
possible and the low power supply current drain is
(Temperature Compensated) independent of the magnitude of the power supply
Wide Power Supply Range: voltage.
Single Supply 3V to 32V Application areas include transducer amplifiers, DC
or Dual Supplies ±1.5V to ±16V gain blocks and all the conventional op amp circuits
Very Low Supply Current Drain (700 which now can be more easily implemented in single
μA)—Essentially Independent of Supply power supply systems. For example, the LM124/124A
Voltage can be directly operated off of the standard +5Vdc
power supply voltage which is used in digital systems
Low Input Biasing Current 45 nA (Temperature and will easily provide the required interface
Compensated) electronics without requiring the additional +15Vdc
Low Input Offset Voltage 2 mV and Offset power supplies.
Current: 5 nA
Input Common-Mode Voltage Range Includes
Ground
Differential Input Voltage Range Equal to the
Power Supply Voltage
Large Output Voltage Swing 0V to V+1.5V
UNIQUE CHARACTERISTICS
In the Linear Mode the Input Common-Mode
Voltage Range Includes Ground and the
Output Voltage can also Swing to Ground,
even though Operated from Only a Single
Power Supply Voltage
The Unity Gain Cross Frequency is
Temperature Compensated
The Input Bias Current is also Temperature
Compensated
ADVANTAGES
Eliminates Need for Dual Supplies
Four Internally Compensated Op Amps in a
Single Package
Allows Directly Sensing Near GND and VOUT
also goes to GND
Compatible with all Forms of Logic
Power Drain Suitable for Battery Operation
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Connection Diagrams
Dual-In-Line CDIP Package
Top View
See Package Number J
CLGA Package
See Package Number NAC or NAD
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Schematic Diagram
(Each Amplifier)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)
Power Dissipation(2) CDIP 400mW
CLGA 350mW
Ceramic SOIC 350mW
Supply Voltage, V+36VDC or ±18VDC
Input Voltage Differential 30VDC
Input Voltage 0.3VDC to +32VDC
Input Current (VIN <0.3VDC)(3) 10 to 0.1mA
Output Short-Circuit to GND(4) V+15VDC and TA= 25°C (One Amplifier) Continuous
Operating Temperature Range 55°C TA+125°C
Maximum Junction Temperature(2) 175°C
Storage Temperature Range 65°C TA+150°C
Lead Temperature (Soldering, 10 seconds) 260°C
Thermal Resistance θJA CDIP (Still Air) 120°C/W
(500LF/Min Air flow) 51°C/W
CLGA (Still Air) 140°C/W
(500LF/Min Air flow) 116°C/W
Ceramic SOIC (Still Air) 140°C/W
(500LF/Min Air flow) 116°C/W
θJC CDIP 35°C/W
CLGA 60°C/W
Ceramic SOIC 60°C/W
Package Weight (Typical) CDIP 2200mg
CLGA 460mg
Ceramic SOIC 410mg
ESD Tolerance(5) 250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
(3) This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of
the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is
also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the op amps to go to
the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and
normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than -0.3VDC (at
25°C).
(4) Short circuits from the output to V+can cause excessive heating and eventual destruction. When considering short circuits to ground,
the maximum output current is approximately 40mA independent of the magnitude of V+. At values of supply voltage in excess of
+15VDC, continuous short-circuits can exceed the power dissipation ratings and cause eventual destruction. Destructive dissipation can
result from simultaneous shorts on all amplifiers.
(5) Human body model, 1.5 kΩin series with 100 pF.
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Table 1. QUALITY CONFORMANCE INSPECTION(1)
Subgroup Description Temp (°C)
1 Static tests at 25
2 Static tests at 125
3 Static tests at -55
4 Dynamic tests at 25
5 Dynamic tests at 125
6 Dynamic tests at -55
7 Functional tests at 25
8A Functional tests at 125
8B Functional tests at -55
9 Switching tests at 25
10 Switching tests at 125
11 Switching tests at -55
(1) MIL-STD-883, Method 5005 Group A
LM124 JAN DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
VIO Input Offset Voltage VCC+= 30V, VCC-= Gnd, -5.0 5.0 mV 1
VCM = +15V -7.0 7.0 mV 2, 3
VCC+= 2V, VCC-= -28V, -5.0 5.0 mV 1
VCM = -13V -7.0 7.0 mV 2, 3
VCC+= 5V, VCC-= Gnd, -5.0 5.0 mV 1
VCM = +1.4V -7.0 7.0 mV 2, 3
VCC+= 2.5V, VCC-= -2.5V, VCM = -1.1V -5.0 5.0 mV 1
-7.0 7.0 mV 2, 3
IIO Input Offset Current VCC+= 30V, VCC-= Gnd, -30 30 nA 1, 2
VCM = +15V -75 75 nA 3
VCC+= 2V, VCC-= -28V, -30 30 nA 1, 2
VCM = -13V -75 75 nA 3
VCC+= 5V, VCC-= Gnd, -30 30 nA 1, 2
VCM = +1.4V -75 75 nA 3
VCC+= 2.5V, VCC-= -2.5V, VCM = -1.1V -30 30 nA 1, 2
-75 75 nA 3
±IIB Input Bias Current VCC+= 30V, VCC-= Gnd, -150 +0.1 nA 1, 2
VCM = +15V -300 +0.1 nA 3
VCC+= 2V, VCC-= -28V, -150 +0.1 nA 1, 2
VCM = -13V -300 +0.1 nA 3
VCC+= 5V, VCC-= Gnd, -150 +0.1 nA 1, 2
VCM = +1.4V -300 +0.1 nA 3
VCC+= 2.5V, VCC-= -2.5V, VCM = -1.1V -150 +0.1 nA 1, 2
-300 +0.1 nA 3
+PSRR Power Supply Rejection Ratio VCC-= Gnd, VCM = -1.4V, -100 100 µV/V 1, 2, 3
5V VCC 30V
CMRR Common Mode Rejection Ratio See(1) 76 dB 1, 2, 3
IOS+Output Short Circuit Current VCC+= 30V, VCC -= Gnd, -70 mA 1, 2, 3
Vo = +25V
(1) The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V (at 25°C). The
upper end of the common-mode voltage range is V+1.5V (at 25°C), but either or both inputs can go to +32V without damage
independent of the magnitude of V+.
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LM124 JAN DC ELECTRICAL CHARACTERISTICS (continued)
SYMBOL PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
ICC Power Supply Current VCC+= 30V, VCC -= Gnd 3 mA 1, 2
4 mA 3
Delta VIO / Input Offset Voltage Temperature +25°C TA+125°C, -30 30 µV/°C 2
Delta T Sensitivity VCC+= 5V, VCC-= 0V,
VCM = +1.4V
-55°C TA+25°C, -30 30 µV/°C 3
VCC+= 5V, VCC-= 0V,
VCM = +1.4V
Delta IIO / Input Offset Current Temperature +25°C TA+125°C, -400 400 pA/°C 2
Delta T Sensitivity VCC+= 5V, VCC-= 0V,
VCM = +1.4V
-55°C TA+25°C, -700 700 pA/°C 3
VCC+= 5V, VCC-= 0V,
VCM = +1.4V
VOL Logical "0" Output Voltage VCC+= 30V, VCC-= Gnd, 35 mV 4, 5, 6
RL= 10K
VCC+= 30V, VCC-= Gnd, 1.5 V 4, 5 ,6
IOL = 5mA
VCC+= 4.5V, VCC-= Gnd, 0.4 V 4, 5, 6
IOL = 2µA
VOH Logical "1" Output Voltage VCC+= 30V, VCC-= Gnd, 27 V 4, 5, 6
IOH = -10mA
VCC+= 4.5V, VCC-= Gnd, 2.4 V 4, 5
IOH = -10mA 2.3 V 6
AVS+Voltage Gain VCC+= 30V, VCC-= Gnd, 50 V/mV 4
1V VO26V, 25 V/mV 5, 6
RL= 10K
VCC+= 30V, VCC-= Gnd, 50 V/mV 4
5V VO20V, 25 V/mV 5, 6
RL= 2K
AVS Gain Voltage VCC+= 5V, VCC-= Gnd, 10 V/mV 4, 5, 6
1V VO2.5V,
RL= 10K
VCC+= 5V, VCC-= Gnd, 10 V/mV 4, 5, 6
1V VO2.5V,
RL= 2K
+VOP Maximum Output Voltage Swing VCC+= 30V, VCC-= Gnd, 27 V 4, 5, 6
VO= +30V, RL= 10K
VCC+= 30V, VCC-= Gnd, 26 V 4, 5, 6
Vo = +30V, RL= 2K
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LM124 JAN AC ELECTRICAL CHARACTERISTICS
The following conditions apply to all the following parameters, unless otherwise specified.
AC: +VCC = 30V, VCC = 0V.
SYMBOL PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
TRTR Transient Response: Rise Time VCC+= 30V, VCC-= Gnd 1.0 µS 7, 8A, 8B
TROS Transient Response: Overshoot VCC+= 30V, VCC-= Gnd 50 % 7, 8A, 8B
±SRSlew Rate: Rise/Fall VCC+= 30V, VCC-= Gnd 0.1 V/µS 7, 8A, 8B
NIBB Noise Broadband VCC+= 15V, VCC-= -15V, 15 µV/rms 7
BW = 10Hz to 5KHz
NIPC Noise Popcorn VCC+= 15V, VCC-= -15V, 50 µV/pK 7
Rs = 20K
CSChannel Separation VCC+= 30V, VCC-= Gnd, 80 dB 7
VIN = 1V and 16V,
RL= 2K
LM124 JAN DC DRIFT VALUES
“Delta calculations performed on JAN S and QMLV devices at group B, subgroup 5 only”
SYMBOL PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
VIO Input Offset Voltage VCC+= 30V, VCC-= Gnd, -1.0 1.0 mV 1
VCM = +15V
±IIB Input Bias Current VCC+= 30V, VCC-= Gnd, -15 15 nA 1
VCM = +15V
LM124A JAN DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
VIO Input Offset Voltage VCC+= 30V, VCC-= Gnd, -2.0 2.0 mV 1
VCM = +15V -4.0 4.0 mV 2, 3
VCC+= 2V, VCC-= -28V, -2.0 2.0 mV 1
VCM =13V -4.0 4.0 mV 2, 3
VCC+= 5V, VCC-= Gnd, -2.0 2.0 mV 1
VCM = +1.4V -4.0 4.0 mV 2, 3
VCC+= 2.5V, VCC-= -2.5V, VCM =1.1V -2.0 2.0 mV 1
-4.0 4.0 mV 2, 3
IIO Input Offset Current VCC+= 30V, VCC-= Gnd, -10 10 nA 1, 2
VCM = +15V -30 30 nA 3
VCC+= 2V, VCC-= -28V, -10 10 nA 1, 2
VCM =13V -30 30 nA 3
VCC+= 5V, VCC-= Gnd, -10 10 nA 1, 2
VCM = +1.4V -30 30 nA 3
VCC+= 2.5V, VCC-= -2.5V, VCM =1.1V -10 10 nA 1, 2
-30 30 nA 3
±IIB Input Bias Current VCC+= 30V, VCC-= Gnd, -50 +0.1 nA 1, 2
VCM = +15V -100 +0.1 nA 3
VCC+= 2V, VCC-= -28V, -50 +0.1 nA 1, 2
VCM =13V -100 +0.1 nA 3
VCC+= 5V, VCC-= Gnd, -50 +0.1 nA 1, 2
VCM = +1.4V -100 +0.1 nA 3
VCC+= 2.5V, VCC-= -2.5V, VCM =1.1V -50 +0.1 nA 1, 2
-100 +0.1 nA 3
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LM124A JAN DC ELECTRICAL CHARACTERISTICS (continued)
SYMBOL PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
+PSRR Power Supply Rejection Ratio VCC-= Gnd, VCM = -1.4V, -100 100 µV/V 1, 2, 3
5V VCC 30V
CMRR Common Mode Rejection Ratio See(1) 76 dB 1, 2, 3
IOS+ Output Short Circuit Current VCC+= 30V, VCC - = Gnd, -70 mA 1, 2, 3
VO= +25V
ICC Power Supply Current VCC+= 30V, VCC - = Gnd 3.0 mA 1, 2
4.0 mA 3
Delta VIO/ Input Offset Voltage +25°C TA+125°C, -30 30 µV/°C 2
Delta T Temperature Sensitivity VCC+= 5V, VCC-= 0V,
VCM = +1.4V
-55°C TA+25°C, -30 30 µV/°C 3
VCC+= 5V, VCC-= 0V,
VCM = +1.4V
Delta IIO / Input Offset Current +25°C TA+125°C, -400 400 pA/°C 2
Delta T Temperature Sensitivity VCC+= 5V, VCC-= 0V,
VCM = +1.4V
-55°C TA+25°C, -700 700 pA/°C 3
VCC+= 5V, VCC-= 0V,
VCM = +1.4V
VOL Logical "0" Output Voltage VCC+= 30V, VCC-= Gnd, 35 mV 4, 5, 6
RL= 10K
VCC+= 30V, VCC-= Gnd, 1.5 V 4, 5, 6
IOL = 5mA
VCC+= 4.5V, VCC-= Gnd, 0.4 V 4, 5, 6
IOL = 2µA
VOH Logical "1" Output Voltage VCC+= 30V, VCC-= Gnd, 27 V 4, 5, 6
IOH = -10mA
VCC+ = 4.5V, VCC- = Gnd, 2.4 V 4, 5
IOH = -10mA 2.3 V 6
AVS+Voltage Gain VCC+= 30V, VCC-= Gnd, 50 V/mV 4
1V VO26V, 25 V/mV 5, 6
RL= 10K
VCC+= 30V, VCC-= Gnd, 50 V/mV 4
5V VO20V, 25 V/mV 5, 6
RL= 2K
AVS Gain Voltage VCC+= 5V, VCC-= Gnd, 10 V/mV 4, 5, 6
1V VO2.5V,
RL= 10K
VCC+= 5V, VCC-= Gnd, 10 V/mV 4, 5, 6
1V VO2.5V,
RL= 2K
+VOP Maximum Output Voltage Swing VCC+= 30V, VCC-= Gnd, 27 V 4, 5, 6
VO= +30V, RL= 10K
VCC+= 30V, VCC-= Gnd, 26 V 4, 5, 6
VO= +30V, RL= 2K
(1) The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V (at 25°C). The
upper end of the common-mode voltage range is V+1.5V (at 25°C), but either or both inputs can go to +32V without damage
independent of the magnitude of V+.
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LM124A JAN AC ELECTRICAL CHARACTERISTICS
The following conditions apply to all the following parameters, unless otherwise specified.
AC: +VCC = 30V, VCC = 0V
SYMBOL PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
TRTR Transient Response: Rise Time VCC+= 30V, VCC-= Gnd 1.0 µS 7, 8A, 8B
TROS Transient Response: Overshoot VCC+= 30V, VCC-= Gnd 50 % 7, 8A, 8B
±SRSlew Rate: Rise/Fall VCC+= 30V, VCC-= Gnd 0.1 V/µS 7, 8A, 8B
NIBB Noise Broadband VCC+= 15V, VCC-= -15V, 15 µV/rms 7
BW = 10Hz to 5KHz
NIPC Noise Popcorn VCC+= 15V, VCC-= -15V, 50 µV/pK 7
Rs = 20K
BW = 10Hz to 5KHz
CSChannel Separation VCC+= 30V, VCC-= Gnd 80 dB 7
RL= 2K
VCC+= 30V, VCC-= Gnd, 80 dB 7
VIN = 1V and 16V,
RL= 2K
LM124A JAN DC DRIFT VALUES
“Delta calculations performed on JAN S and QMLV devices at group B, subgroup 5 only”
Symbol PARAMETER CONDITIONS NOTES MIN MAX UNIT SUB
GROUPS
Vio Input Offset Voltage Vcc+= 30V, Vcc-= Gnd, -0.5 0.5 mV 1
Vcm = +15V
±iib Input Bias Current Vcc+= 30V, Vcc-= Gnd, -10 10 nA 1
Vcm = +15V
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TYPICAL PERFORMANCE CHARACTERISTICS
Input Voltage Range Input Current
Figure 1. Figure 2.
Supply Current Voltage Gain
Figure 3. Figure 4.
Open Loop Frequency Common Mode Rejection
Response Ratio
Figure 5. Figure 6.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Voltage Follower Pulse Voltage Follower Pulse
Response Response (Small Signal)
Figure 7. Figure 8.
Large Signal Frequency Output Characteristics
Response Current Sourcing
Figure 9. Figure 10.
Output Characteristics
Current Sinking Current Limiting
Figure 11. Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Input Current (LM2902 only) Voltage Gain (LM2902 only)
Figure 13. Figure 14.
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APPLICATION HINTS
The LM124MIL series are op amps which operate with only a single power supply voltage, have true-differential
inputs, and remain in the linear mode with an input common-mode voltage of 0 VDC. These amplifiers operate
over a wide range of power supply voltage with little change in performance characteristics. At 25°C amplifier
operation is possible down to a minimum supply voltage of 2.3 VDC.
The pinouts of the package have been designed to simplify PC board layouts. Inverting inputs are adjacent to
outputs for all of the amplifiers and the outputs have also been placed at the corners of the package (pins 1, 7, 8,
and 14).
Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in
polarity or that the unit is not inadvertently installed backwards in a test socket as an unlimited current surge
through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a
destroyed unit.
Large differential input voltages can be easily accommodated and, as input differential voltage protection diodes
are not needed, no large input currents result from large differential input voltages. The differential input voltage
may be larger than V+without damaging the device. Protection should be provided to prevent the input voltages
from going negative more than 0.3 VDC (at 25°C). An input clamp diode with a resistor to the IC input terminal
can be used.
To reduce the power supply drain, the amplifiers have a class A output stage for small signal levels which
converts to class B in a large signal mode. This allows the amplifiers to both source and sink large output
currents. Therefore both NPN and PNP external current boost transistors can be used to extend the power
capability of the basic amplifiers. The output voltage needs to raise approximately 1 diode drop above ground to
bias the on-chip vertical PNP transistor for output current sinking applications.
For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor should be
used, from the output of the amplifier to ground to increase the class A bias current and prevent crossover
distortion.
Where the load is directly coupled, as in dc applications, there is no crossover distortion.
Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values
of 50 pF can be accommodated using the worst-case non-inverting unity gain connection. Large closed loop
gains or resistive isolation should be used if larger load capacitance must be driven by the amplifier.
The bias network of the LM124MIL establishes a drain current which is independent of the magnitude of the
power supply voltage over the range of from 3 VDC to 30 VDC.
Output short circuits either to ground or to the positive power supply should be of short time duration. Units can
be destroyed, not as a result of the short circuit current causing metal fusing, but rather due to the large increase
in IC chip dissipation which will cause eventual failure due to excessive junction temperatures. Putting direct
short-circuits on more than one amplifier at a time will increase the total IC power dissipation to destructive
levels, if not properly protected with external dissipation limiting resistors in series with the output leads of the
amplifiers. The larger value of output source current which is available at 25°C provides a larger output current
capability at elevated temperatures (see TYPICAL PERFORMANCE CHARACTERISTICS) than a standard IC
op amp.
The circuits presented in the section on typical applications emphasize operation on only a single power supply
voltage. If complementary power supplies are available, all of the standard op amp circuits can be used. In
general, introducing a pseudo-ground (a bias voltage reference of V+/2) will allow operation above and below this
value in single power supply systems. Many application circuits are shown which take advantage of the wide
input common-mode voltage range which includes ground. In most cases, input biasing is not required and input
voltages which range to ground can easily be accommodated.
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Typical Single-Supply Applications
(V+= 5.0 VDC)
*R not needed due to temperature independent IIN
Figure 15. Non-Inverting DC Gain (0V Input = 0V Output)
Where: V0= V1+ V2V3V4
(V1+ V2)(V3+ V4) to keep VO> 0 VDC
Figure 16. DC Summing Amplifier
(VIN'S 0 VDC and VOVDC)
V0= 0 VDC for VIN = 0 VDC
AV= 10
Figure 17. Power Amplifier
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Figure 18. LED Driver
fo= 1 kHz
Q = 50
AV= 100 (40 dB)
Figure 19. “BI-QUAD” RC Active Bandpass Filter
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Figure 20. Fixed Current Sources
Figure 21. Lamp Driver
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*(Increase R1 for ILsmall)
Figure 22. Current Monitor
Figure 23. Driving TTL
Figure 24. Voltage Follower
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Figure 25. Pulse Generator
Figure 26. Squarewave Oscillator
Figure 27. Pulse Generator
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IO= 1 amp/volt VIN
(Increase REfor Iosmall)
Figure 28. High Compliance Current Sink
Figure 29. Low Drift Peak Detector
Figure 30. Comparator with Hysteresis
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VO= VR
Figure 31. Ground Referencing a Differential Input Signal
*Wide control voltage range: 0 VDC VC2 (V+1.5 VDC)
Figure 32. Voltage Controlled Oscillator Circuit
Figure 33. Photo Voltaic-Cell Amplifier
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Figure 34. AC Coupled Inverting Amplifier
Figure 35. AC Coupled Non-Inverting Amplifier
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fO= 1 kHz
Q = 1
AV= 2
Figure 36. DC Coupled Low-Pass RC Active Filter
Figure 37.
Figure 38. High Input Z, DC Differential Amplifier
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Figure 39. High Input Z Adjustable-Gain
DC Instrumentation Amplifier
Figure 40. Using Symmetrical Amplifiers to
Reduce Input Current (General Concept)
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Figure 41. Bridge Current Amplifier
fO= 1 kHz
Q = 25
Figure 42. Bandpass Active Filter
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REVISION HISTORY
Date Released Revision Section Changes
01/27/05 A New Released, Corporate format 2 MDS data sheets converted into one Corp. data
sheet format. MJLM124–X, Rev. 1B1 and MJLM124A-
X, Rev. 2A1. MDS data sheets will be archived.
04/18/05 B Update Absolute Maximum Ratings Section Corrected typo for Supply Voltage limit From: 32Vdc
or +18Vdc TO: 32Vdc or ±18Vdc. Added Cerdip
package weight.
09/27/2010 C Obsolete Data Sheet End Of Life on Product/NSID Dec. 2008/2009
Changes from Revision E (April 2013) to Revision F Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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