M45PE80-VMP6TG - STMicroelectronics

1/36May 2004

M45PE80

8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory

With Byte-Alterability and a 25 MHz SPI Bus Interface

FEATURES SUMMAR Y

■8Mbit of Page-Erasable Flash Memory

■Page Write (up t o 256 Bytes) in 11ms (typical)

■Page Program (up to 256 Bytes) in 1.2ms

(typical)

■Page Erase (256 Bytes) in 10ms (typical)

■Sector Erase (512 Kb it)

■2.7 to 3.6V Single Supply Vo ltage

■SPI Bus Compatible Serial Interface

■25MH z Clock Rate (maximum)

■D eep Power-down Mod e 1µA (typical)

■Ele ctronic Signature

– JEDEC Standard Two-Byte Signature

(4014h)

■More than 100, 000 Write Cycles

■More than 20 Yea r Data Retention

Figure 1. Packages

VDFPN8 (MP)

6x5mm (MLP8)

SO16 (MF)

300 mil width

M45PE80

2/36

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. VDFPN Connect ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

R eset (Reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Po lling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

R eset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Active Power, Stand-by Power and Deep Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 7. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

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M45PE80

Figure 9. Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Read Identification (RDID) Data-Out Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.Read I dentification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 14

Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Figure 11.Read S tatus Register (RDSR) Instruction Sequence and Data-O ut Sequen ce . . . . . . . 15

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Read Dat a Bytes (READ) Instruction Sequen ce and Data-Out Sequence . . . . . . . . . . . 16

Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13.Read Data Bytes at Higher Speed (FAST_READ ) Instruction Sequenc e and Data-Out Se-

quence 17

Page Write (PW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14.P age Write (PW) Instruction Sequenc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Figure 15.P age Pro gram (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Pag e Erase (PE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16.P age Era se (PE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Sec tor Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Figure 17.S ector Eras e (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18.Deep P ower-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Release from Deep Power-down (RDP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 19.Release from Deep Power-down (RDP) Instruction Sequence. . . . . . . . . . . . . . . . . . . . 23

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 20.Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4

Table 6. Power-Up Timing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. Operating C onditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9. A C Measurem ent Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8

Table 12. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9

Figure 22.S erial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 23.Write Protect Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 25.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

M45PE80

4/36

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 26.M LP 8, 8-lead Very thin Dual Flat Package No lead, 6x 5mm, Package Outli ne . . . . . . . 32

Table 13. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Mechanical Data32

Figure 27.S O16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline. . . . 33

Table 14. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data. . . . 33

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 16. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5/36

M45PE80

SUMMA RY DESCRIPTION

The M45PE80 is a 8M bit (1M x 8 bit) Serial Paged

Flash Memory accessed by a high speed SPI-

comp atible bu s .

The memory can be written or programmed 1 to

256 bytes at a time, using the Page Write or Page

Program instruction. The Page Write instruction

consists of an integrated Page Erase cycle fol-

lowe d by a Page Program cycle.

The memory is organized as 16 sectors, each con-

taining 256 p ages. Each page is 256 bytes wide.

Thus, the whole memory can be viewed as con-

sisting of 4096 pages, or 1,048,576 bytes.

The memory can be erased a page at a time, using

the Page Erase instruction, or a sector at a time,

using the Sector Erase instruction.

Figure 2. Logic Diagram

Table 1. Signal Names

Figu re 3. V DFPN Connec tion s

Note : 1. There is an expo sed die pa ddle on the underside of the

MLP8 package. This is pulled, internally, to VSS, and

must not be allowed to be connected to any other voltage

or si gnal line on t he PCB.

2. See PACKAGE MECHANICAL section for package di-

mens i ons, and how to ident i fy pin-1.

Figu re 4. S O Conne ct i on s

N ot e: 1. D U = Do n’t Use

2. See PACKAGE MECHANICAL section for package di-

mens i ons, and how to ident i fy pin-1.

C Serial Clock

D Serial Data Input

Q Serial Data Outp ut

SChip Select

W Write Protect

Reset Reset

VCC Supply Voltage

VSS Ground

Reset

AI06810B

VCC

M45PE80

VSS

AI06811B

5WS VCC

VSS

Reset

M45PE80

AI09031B

DU DU

VSS

DUDU

M45PE80

9RESET

QVCC

M45PE80

6/36

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This input signal is used to

transfer data serially into the device. It receives in-

structions, addresses, and the data to be pro-

grammed. Values are latched on the rising edge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the serial interface. Instructions, address-

es, or data present at Serial Data Input (D) are

latched on the rising edge of Serial Clock (C). Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) i s at high impedance. Unless an internal Read,

Program, Erase or Write cycle is in progress, the

device will be in the Stan dby mo de (this is not the

Deep Power-down mode). Driving Chip Select (S)

Low enables the device, placing it in the active

power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Reset (R eset). T he Reset (Reset) input provides

a hardware reset for the memory. In this mode, the

outputs are high impedan ce.

When Reset (Reset) is driven High, the memory is

in the normal operating mode. When Reset (Re-

set) is driven Low, the memory will enter t he Reset

mode, provided that no internal operation is cur-

rently in progress. Driving Reset (Reset) Low while

an internal operation is in progress has no effect

on that internal operation (a write cycle, program

cycle, or erase cycle).

Write Protect (W). This input signal puts the de-

vice in the Hardware Protected mode, when Write

Protect (W ) is c onnected to VSS, causing the first

256 pages of memory to become read-only by pro-

tecting them fro m write, program and erase oper-

ations. When Write Protect (W) is connected to

VCC, the first 256 pages of memory behave like

the other pages of memory.

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M45PE80

SPI MODES

These dev ices can be drive n by a microcont roller

with its SPI peripheral running in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 6., is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. Bus Master and Memo ry Devices on the SPI Bus

Note: The Write Protect (W) signal shoul d be dri ven, Hi gh or Low as appropriate.

Figure 6 . SPI Mo de s S upport ed

AI04043B

Bus Master

(ST6, ST7, ST9,

ST10, Others) SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WRP WRP WRP

AI01438B

MSB

CPHA

CPOL

MSB

M45PE80

8/36

OPERA TING FE AT URES

Sharing the Overhead of Modifying Data

To write or program one (or more) data bytes, two

instructions are required: Write Enable (WREN),

which is one byte, and a Page Write (PW) or Page

Program (PP) sequence, which consists of four

bytes plus data. This is followed by the internal cy-

cle (of duration tPW or t PP).

To share this overhead, the Page Write (PW) or

Page Program (PP) instruction allows up to 256

bytes to be p rogrammed (changing bits from 1 t o

0) or wri tten (changing bits to 0 or 1) at a time, pro-

vided that they lie in consecutive addresses on the

same page of memory.

An Easy Way to Modify Data

The Page Write (PW) instruction provides a con-

venient w ay of modi fying data (up to 256 c ontigu-

ous bytes at a t ime), a nd sim ply requ ires the s tart

address, and the new data in the instruction se-

quence.

The Page Write (PW) instruction is entered by

driving Chip Select (S) Low , and then transmit ting

the instruction byte, three address bytes (A23-A0)

and at least one data byte, and then driving Chip

Select (S) High. While Chip Select (S) is being

held Low, the data bytes are written to the data

buffer, starting at the address given in the third ad-

dress byte (A7-A0). When Chip Select (S) is driven

High, the Write cycle starts. The remaining, un-

changed, bytes of the data buffer are automatically

loaded with the values of the correspondin g bytes

of the addressed memory page. The addressed

memory page then automatically put into an Erase

cycle. Finally, the addressed memory page is pro-

grammed with the contents of the data buffer.

All of this buffer management is handled internally,

and is transparent to the user. The user is given

the facility of being able to alter the contents of the

memory on a byte-by-byte basis.

A Fast Way to Modify Data

The Page Program (PP) instruction provides a f ast

way of modifying data (up to 256 contiguous bytes

at a time), provided that it only involves resetting

bits to 0 that had previously been set to 1.

This might be:

– when the designer is programming the device

fo r th e first tim e

– w hen the designer know s that the page has

already been erased by an earlier Page Erase

(PE) or Sect o r Erase (SE) i n str u ction . This is

use ful, for example, when storing a fast

stream of data, having first performed the

erase cycle when time was available

– w hen the designer know s that the only

changes involve resetting bits to 0 that are still

set to 1. When this method is possible, it has

the addi tional advantage of minimisin g the

number of unnecessary erase operations, and

the extra stress incurred by each page.

Polling During a Write, Program or Erase Cycle

A further improvement in the write, program or

erase time can be achieved by not waiting for the

worst case delay (tPW, tPP, tPE, or tSE). T he Write

In Progress (WIP) bit is provided in the Status

itor its value, polling it to establish when the previ-

ous cycl e is complet e .

Reset

An internal Power-On Reset circuit helps protect

against inadvertant data writes. Addition protec-

tion is provided by driving Re set (Reset) Low dur-

ing the Power-on process, and only driving it High

when VCC has reached the correct voltage level,

VCC(min).

Active Power, Sta nd - b y Po wer an d De ep

Power-Down Modes

When Chip Select (S) is Low, the device is en-

abled, and in the Active Power mode.

When Chip Select (S) is High, the device is dis-

abled, but could remain in the Active Powe r mode

until all internal cycles have completed (Program,

Erase, Write). The device then goes in to the

Stand-by Power mode. The device consumption

drops to ICC1.

The Deep Power-down mode is entered when the

specific instruction (the Enter Deep Power-down

Mode (DP) instruction) is executed. The device

consump tion drops further to ICC2. T he de vic e re-

mains in this mode until another specific instruc-

tion (the Release from Deep Power-down Mode

and Read Elect ronic Sig nature (RES ) instruction)

is executed.

All other instructions are igno red while the device

is in the Deep Power-down mode. This can be

used as an ext ra softw are protection mecha nism,

when the device is not in active use, to protect the

device from inadvertant Write, Program or Erase

instructions.

9/36

M45PE80

Status Register

The Status Register contains two status bits that

can be read by the Read Status Register (RDSR)

instruction.

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write, Program

or Erase cycle.

WE L bi t. The W rite Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

Table 2. Status Register Format

Note: 1. WE L and WIP are vo l atil e read-only bits ( WEL is set and

reset by specific instructions; WIP is automatically set

and reset by the internal logic of the device).

P rot e ct i on Modes

The environments where non-volatile memory de-

vices are used can be very noisy. No SPI device

can operate correctly in the presence of excessive

noise. To help com bat this, the M45PE80 boasts

the following data protection mechanisms:

■Powe r-On Reset and an internal timer (tPUW)

can provide protection against inadvertant

changes while the power suppl y is outside the

operat ing specificatio n.

■Program , Erase and Write instructions are

checked that they consist of a number of clock

pulses that is a multiple of eight, before they

are accepted for execut ion.

■All instructions that modify data must be

prece ded by a Write Enable (WREN)

instruction to set the Write Enable Latch

(WEL) bit . This bit is returned to its reset state

by the following events:

– Power-up

– Reset (RESET) driven Low

– Write Disable (WRDI) instruction

completion

– Page Write (PW) instruction completion

– Page Program (PP) instruction completion

– Page Erase (PE) instruction completion

– Sector Erase (SE) instruction completion

■The Hardware P rotected mo de is entered

when Write Protect (W) is driven Low, causing

the first 256 pages of memory to become

read-only. When Write Protect (W) is driven

High, the first 256 pages of memory behave

like the other pages of memo ry

■The Reset (Reset) signal can be driven Low to

protect the contents of the memory during any

critical time, not just during Power-up and

Power-down.

■In addition to the low power consumption

feature, the Deep Power-down mode offers

extra software protection from inad vertant

W rite, Program and Erase instructions while

the device is not in active use.

b7 b0

0 0 0 0 0 0 WEL WIP

M45PE80

10/36

ME M ORY ORGANIZATION

The memory is organized as:

■4096 pages (256 bytes each).

■1,048,576 bytes (8 bits each)

■16 sectors (512 Kbits, 65536 bytes each)

Each page can be individually:

– programmed (bits are programmed from 1 to

– erased (bits are erased from 0 to 1)

– w ritten (bits are changed to either 0 or 1)

The device is Page or Sector Erasable (bits are

erased from 0 to 1).

Table 3. Memory Organization

Sector Address Range

15 F0000h FFFFFh

14 E0000h EFFFFh

13 D0000h DFFFFh

12 C0000h CFFFFh

11 B0000h BFFFFh

10 A0000h AFFFFh

9 90000h 9FFFFh

8 80000h 8FFFFh

7 70000h 7FFFFh

6 60000h 6FFFFh

5 50000h 5FFFFh

4 40000h 4FFFFh

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

11/36

M45PE80

Figu re 7. Blo ck Diagram

AI06812

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Status

00000h

FFFFFh

000FFh

Reset

10000h

First 256 Pages can

be made read-only

M45PE80

12/36

INSTRUCTIONS

All instructions, addresses and data are shifted in

and out of the device, most significant bit first.

Serial Data Input (D) is sampled on the first rising

edge of Serial Clock (C) after Chip Select (S) is

driven Low. Then, the one-byte instruction code

must be shifted in to the device, most significant bit

first, on Serial Data Input (D), each bit being

latched on the rising edges of Serial Clock (C).

The instruction set is listed in Table 4..

Every instruction sequence s tarts with a one-byte

instruction code. Depending on the instruction,

this might be f ollowed by address bytes, or by data

bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read

Data Bytes at Higher Speed (Fast_Read) or Read

Status Register (RDSR) instruction, the shifted-in

instruction sequenc e is follo wed by a data-ou t se-

quence. Chip Select ( S) can be driven High after

any bit of the data-out sequence is being shifted

out.

In the cas e of a Page Write (PW), Page P rogram

(PP), Page Erase (PE), Sector Erase (SE), Write

Enable (WREN), Write Disable (WRDI), Deep

Power-down (DP) or Release from Deep Power-

down (RDP) instruction, Chip Select (S) must be

driven H igh e xactly a t a by te boundary , ot herwise

the instruction is rejected, and is not executed.

That is, Chip Select (S) must driven High when the

number of clock pulses after Chip Select (S) being

driven Low is an exact multiple of eight.

All attempts to access the mem ory array du ring a

Write cycle, Program cycle or Erase cycle are ig-

nored , and th e int e rn al Wri te cycl e, Program cycl e

or Erase cycle continues unaffected.

Table 4. Instruction Set

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞

PW Page Write 0000 1010 0Ah 3 0 1 to 256

PP Page Program 0000 0010 02h 3 0 1 to 256

PE Page Erase 1101 1011 DBh 3 0 0

SE Sector Erase 1101 1000 D8h 3 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RDP Release from Deep Power-down 1010 1011 ABh 0 0 0

13/36

M45PE80

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8.)

sets the Write Enable Latc h (WEL) bit.

The Write Enable Latch (WEL) bit must be set pri-

or to every Page Write (PW), Page Program (PP),

Page Erase (PE), and Sector Erase (SE) instruc-

tion.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 8. Write Enable (WREN) Instruction Sequence

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9.)

resets the Write Enable Latch (WEL ) bit.

The Write Disable (WRDI) instruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

–Power-up

– Write Disable (WRDI) instruction completion

– Page Write (PW) instruction completion

– Page Program (PP) instruction completion

– Pag e Erase (PE) instruction completion

– Sector Erase (SE) instruction completion

Figure 9. Write Disable (WRDI) Instruction Sequence

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

M45PE80

14/36

Read Identification (RDID)

The Read Identification (RDID) instruction allows

the 8-bit manufacturer identification to be read, fol-

lowed by two bytes of device identification. The

manufacturer identification is assigned by JEDEC,

and has the value 20h for STMicroelectronics. The

device identification is assigned by the device

manufacturer, and indicates the memory type in

the first byte (40h), and the memory capacity of the

device in the second byte (14h).

Any Read Identification (RDID) instruction while

an Erase or Program cycle is in progress, is not

decoded, and has no ef fect on the cycle that is in

progress.

The device is first selected by driving Chip Sele ct

(S) Low. Then, the 8-bit i nst ruction code for the in-

struction is shifted in. This is followed by the 24-bit

device identification, stored in the memory, being

shifted out on Serial Data Output (Q), each bit be-

ing shifted out during the falling edge of Serial

Clock (C).

The instruction sequence is shown in Figure 10..

The Read Identification (RDID) instruction is termi-

nated b y driving Chip Select ( S) High at any time

during data output.

When Chip Select (S) is driven High, the dev ice is

put in the Stand-by Power mode. Once in the

Stand-by Power mode, the device waits to be se-

lected, so that it can receive, decode and execute

instructions.

Table 5. Read Identification (RDID) Data-Out Sequence

Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

Manufacturer Identification Device Identification

Memory Type Memory Capacity

20h 40h 14h

21 3456789101112131415

Instruction

AI06809

Manufacturer Identification

High Impedance

MSB

15 1413 3210

Device Identification

MSB

16 16 18 28 29 30 31

15/36

M45PE80

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Program, Erase or Write cycle is in progress.

When one of these cycles is in progress, it is rec-

ommended to che ck the Write In Progress (WIP)

bit before sending a new instruction to the device.

It is also possible to read the Status Register con-

tinuously, as shown in Figure 11..

The status bits of the Status Register are as fol-

lows:

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write, Program

or Erase cycle. When set to 1, such a cycle is in

progress, when reset to 0 no such cycle is in

progress.

WE L bi t. The W rite Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, when s et to 0 t he i ntern al W rite E nabl e Latch

is reset and no Write, Program or Erase instruction

is accepted.

Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

M45PE80

16/36

Read Data Bytes (READ)

The device is first selected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte

address (A23-A0), each bit being latched-in during

the rising edge of Serial Clock (C). Then the mem-

ory contents, at that address, is shifted out on Se-

rial Data Output (Q), each bit bein g shif ted out, at

a maximum frequency fR, during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 12..

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, therefore, be read

with a singl e Read Data Bytes (READ) in st ruction.

When the highest address is reached, the address

counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is termi-

nated by driving Chip Select (S) High. Chip Select

(S) can be driven High at any time during data out-

put. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in

progress, is rej ected without having any ef fects on

th e cycle tha t is in pro gr es s.

Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

Note: Add ress bi ts A23 to A 20 are Don’t Car e.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

17/36

M45PE80

Read Data Bytes at Hig her Speed

(FAST_READ)

The device is first selected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the

rising edge of S erial Clock (C). Then the memory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, durin g the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 13..

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, therefore, be read

with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to

000000h, allowing the read sequence to be contin-

ued indefinitely.

The Read Data Bytes at Higher Speed

(FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driv-

en High at any time during data output. Any Read

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an Erase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Ou t

Sequence

Note: Add ress bi ts A23 to A 20 are Don’t Car e.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

M45PE80

18/36

Page Write (PW)

The Page Write (PW) instruction allows bytes to

be written in the memory. Before it can be accept-

ed, a Write Enable (WREN) instruction must previ-

ously have been exec uted. After the Write Enable

(WREN) instruction has been decoded, the device

sets the Write Enable Latc h (WEL).

The Page Write (PW) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). The rest of

the page remains unchanged if no power failure

occurs during this write cycle.

The Page Write (P W) instruc tion performs a p age

erase cycle even if only one byte is updated.

If the 8 least significant address bits (A7-A0) are

not all zero, all transmitted data exceeding the ad-

dressed page boundary roll over, and are written

from the start address of the same pa ge (the one

whose 8 least significant address bits (A7-A0) are

all zero). Chip Select (S) must be driven Low for

the entire duration of the sequenc e.

The instruction sequence is shown in Figure 14..

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be written correctly

within the same page. If le ss than 256 Data bytes

are sent to device, they are correctly written at the

requested addresses without having any effects

on the other bytes of the same page.

Chip Select (S) must be driven High after the

eighth bit of the last data byte has been latched in,

otherwise the Page Write (PW) instruction is not

executed.

As soon as Chip Select (S) is dr iv en Hi gh , t he se lf-

timed Page Write cycle (whose duration is t PW) is

initiated. While the Page Write cycle is in progress,

the Status Register may be read to che ck the val-

ue of the Write In Progress (WIP) bit. The Write In

Progress (WIP) bit is 1 during the self-timed Page

Write cycle, and is 0 when it is completed. At some

unspecified time before the cycle is complete, the

Write Enable Latch (WEL) bit is reset.

A Page Write (PW) instruction applied to a page

that is Hardware Protected is not executed.

An y Pag e Writ e (P W) in str uctio n, wh ile an Era se,

Prog ram or Write cycle is in progre ss, is rejected

without having any effects on the cycle that is in

progress.

Figu re 14 . P age W rite ( PW) Inst ru c tio n S e qu e nce

Note: 1. Address bits A23 to A20 are Don’t Care

2. 1 ≤ n ≤ 256

AI04045

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte n

765432 0

MSB MSB

MSB MSB MSB

19/36

M45PE80

Page Program (PP)

The Page Program (PP) instruction allows bytes to

be programmed in the memory (changing bits from

1 to 0, only). Before it can be accepted, a Write En-

able (WREN) instruction must previously have

been executed. After the Write E nable (WREN) in-

struction has been decoded, the device sets the

Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted data exceeding the ad-

dressed page boundary roll over, and are pro-

grammed from the start address of the same page

(the one whose 8 least significant address bits

(A7-A0) are all zero). Chip Select (S) must be driv-

en Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15..

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be programmed cor-

rectly within the sam e page. If less t han 2 56 Dat a

bytes are sent to device, they are correctly pro-

grammed at the requested addresses without hav-

ing any effects on the other bytes of the same

page.

Chip Select (S) must be driven High after the

eighth bit of the last data byte has been latched in,

otherwise the Page Program (PP) instruction is not

executed.

As soon as Chip Select (S) is dr iv en Hi gh , t he se lf-

timed Page Program cycl e (wh ose dur ation is tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress (WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL)

bit is reset.

A Page Program (PP) instruction applied to a

page that is Hardware Protected is not executed.

Any Page Program (PP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without havi n g any effects o n the cycl e th a t

is in progress.

Figu re 15 . P age Prog ra m (P P) Instruction Seq uenc e

Note: 1. Address bits A23 to A20 are Don’t Care

2. 1 ≤ n ≤ 256

AI04044

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte n

765432 0

MSB MSB

MSB MSB MSB

M45PE80

20/36

Page Erase (PE)

The Page Erase (PE) instruction sets to 1 (FFh) all

bits inside the chosen p age. Before it can b e ac-

cepted, a Write Enable (WREN) instruction must

previously have been executed. After the Write

Enable (WREN) instruction has been decoded,

the device sets the Write Enable Latch (WEL).

The Page Erase (PE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address by tes on Serial

Data Input (D). Any a ddress inside the Page is a

valid address for the P age Eras e (P E) instru ction.

Chip Select ( S) must be driven Low for the entire

duration of the seq uence.

The instruction sequence is shown in Figure 16..

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Page Erase (PE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-timed Pag e E rase cycle (w hose du-

ration is tPE) is initiated. While the Page Erase cy-

cle is in progress, the Status Register may be read

to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the

self-timed Page Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL)

bit is reset.

A Page Erase (PE) instruction applied to a page

that is Hardware Protected is not executed.

Any Page Erase (PE) instruction, while an Erase,

Prog ram or Write cycle is in progre ss, is rejected

without having any effects on the cycle that is in

progress.

Fig ur e 16. Page Erase (PE) Instruction Sequence

Note: Add ress bi ts A23 to A 20 are Don’t Car e.

24 Bit Address

AI04046

21 3456789 293031

Instruction

23 22 2 0

MSB

21/36

M45PE80

Sector Erase (SE)

The Sector E rase (SE) instruction sets t o 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address by tes on Serial

Data Input (D). Any address inside the Sector (see

Table 3.) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 17..

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-ti med Sector E rase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Status Register may be read

to check the value of the Write In Progress (WIP)

bit. The Write In Progress (WIP) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is complete, the Write Enable Latch (WEL)

bit is reset.

A Sector Erase (SE) instruction applied to a sector

that contains a page that is Hardware Protected is

not executed.

Any Sector Erase (SE) instruction, while an Erase,

Prog ram or Write cycle is in progre ss, is rejected

without having any effects on the cycle that is in

progress.

Figure 17. Sector Erase (SE) Instruction S equ ence

Note: Add ress bi ts A23 to A 20 are Don’t Car e.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

M45PE80

22/36

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction

is the only way to put the device in t he lowest con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism, while the device is not in active use,

since in this mode, the device ignores all Write,

Program and Eras e instructions.

Driving Chip Select (S) High deselects the device,

and puts the dev ice in the S tandby m ode (if there

is no internal cycle currently in progress). But this

mode is not the Deep Power-down mode. The

Deep Power-down mode can only be entered by

executing the Deep P ower-down (DP ) instruction,

to reduce the standby current (from ICC1 to I CC2,

as specified in T able 11.).

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down (RDP) instruc-

tion. This releas es the device from this mode.

The Deep P ower-down m ode automaticall y stops

at Power-down, and the device always Powers-up

in the Standby mode.

The Deep Power-down (DP) instruction is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Input (D). Chip Se-

lect (S) m ust be d riven Low for the entire duration

of the seq uence.

The instruction sequence is shown in Figure 18..

Chip Select (S) must be driven High after the

eighth bit of the instruction code has been latched

in, otherwise t he Deep Power-down (DP) instruc-

tion is not executed. As soon as Chip Select (S) is

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without havi n g any effects o n the cycl e th a t

is in progress.

Figure 18. Deep Power-down (DP) Instruction Sequence

AI03753D

21 345670tDP

Deep Power-down Mode

Stand-by Mode

Instruction

23/36

M45PE80

Release from Deep Power-do wn (RDP)

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down (RDP) instruc-

tion. Executing this instruction takes the device out

of the Deep Pow er-down mode.

The Release from Deep Power-down (RDP) in-

struction is entered by driving Chip Select (S) Low,

followed by the instruction code on Serial Data In-

put (D). Chip Sel ect (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 19..

The Release from Deep Power-down (RDP) in-

struction is terminated by driving Chip Select (S)

High. Sending additional clock cycles on Serial

Clock (C), while Chip Select (S) is driven Low,

cause the instruction to be rejected, and not exe-

cuted.

After Chip Select (S) has been driven High, fol-

lowed by a delay, tRDP, the device is put in the

Standby m ode. Chip S elect (S) must remain H igh

at least until this period is over. The device wai ts

to be selected, so that it can receive, decode and

execute instructions.

Any Release from Deep Power-down (RDP) in-

struction, while an Erase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 19. Rel ease from Deep Power-d ow n (RDP) Instruction Seque nce

AI06807

21 345670tRDP

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

M45PE80

24/36

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selected (that is Chip Select (S) must follow

the voltage applied on VCC) unti l VCC reache s the

correct value:

–V

CC(min) at Power-up, and then for a further

delay of tVSL

–V

SS at Power-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to insure safe and proper Power-up

and Power-down.

To avoid data corruption and inadvertent write op-

erations during power up, a Power On Reset

(POR) circuit i s included. Th e logic i nside the de-

vice is held reset w hile V CC is less than the POR

threshold value, VWI – all operations are disabled,

and the device does not respond to any instruc-

tion.

Moreover, the device ignores all Write Enable

(WREN), Page Write (PW), Page Program (PP),

Page Erase (PE) and Sector Erase (SE) instruc-

tions until a time de lay of t PUW has elapsed after

the moment that VCC rises above t he VWI thresh-

old. However, the correct operation of the device

is not guaranteed if, by this time, VCC is still below

VCC(min). No Write, Program or Erase instructions

should be sent until the later of:

–t

PUW after VCC passed the VWI threshold

–t

VSL after VCC passed the VCC(min) level

These values are specified in Table 6..

If the delay, tVSL, has elapsed, after VCC has risen

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not yet

fully elapsed.

As an extra protection, the Reset (Reset) signal

could be d riven L ow for the whole duration of the

Power-up and Power-down phases.

At Power-up, the dev ice is in the following state:

– The device is in the Standby mode (not the

D eep Power-down mod e).

– The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail

decoupling, to stabl ise the V CC fe ed. Each device

in a syst em should have the VCC r ail decoupled by

a suitable capacitor close to the package pins.

(Generally, this capacitor is of the order of 0.1µF).

At Power-down, when VCC drops from the operat-

ing voltage, to below the POR threshold value,

VWI, all operations are disabled and the device

does not respond to any instruction. (The designer

needs to be aware that if a Power-down occurs

while a Write, Program or Erase cycle is in

progress, some data corruption can result.)

Figure 20. Power-up Timing

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

25/36

M45PE80

Table 6. Power-Up Timing and VWI Th res h ol d

Note: 1. T hese pa ram eters are characterized onl y, over th e temperat ure range –40°C to +85°C .

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh). All usable Status Register bits are 0.

Symbol Parameter Min. Max. Unit

tVSL1VCC(min) to S low 30 µs

tPUW1Time delay before the first Write, Program or Erase instruction 1 10 ms

VWI1Write Inhibit Voltage 1.5 2.5 V

M45PE80

26/36

MAXI MUM RA T ING

Stressing the device above the rating l isted in t he

Absolute Maxi mum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at t hese or

any other con ditions ab ove those i ndicated in t he

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 7. Absolute Maximum Ratings

Note : 1. Comp liant wit h JEDEC Std J- STD- 020 B (for sm all bod y, Sn -Pb or Pb as sem bly ), the ST EC OPA CK ® 7191395 spec i ficat i on, and

the Eu ropean di recti ve on Res tr i ct i ons on Haz ardous Subst ances (RoHS ) 2002/ 95/E U

2. JED EC St d J ESD22-A11 4A (C 1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note 1°C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V

27/36

M45PE80

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement condition s, and the DC and AC charac-

teristics o f the de vice. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions in t heir circuit matc h the measurem ent

conditions when relying on the quoted parame-

ters.

Table 8. Operating Conditions

Table 9. AC Measu remen t Conditions

Note: Out put Hi-Z is defined as the poi nt wh ere dat a out is no l onger driven.

Figu re 21. AC Mea surem ent I/O W av eform

Table 10. Capacitanc e

Note: Sampled onl y, not 10 0% te st ed, at TA=25° C and a freq uency of 20 MHz.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmb ient Operati ng Temperature –40 85 °C

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V

Symbol Parameter Test Condition Min.Max.Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

M45PE80

28/36

Table 11. DC Characteristics

Symbol Parameter Test Condition

(in addition to those in Table 8.)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current

(Stand by and Reset modes) S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 10 µA

ICC3 Operating Current (FAST_READ) C = 0.1VCC / 0.9.VCC at 25 MHz,

Q = open 6mA

ICC4 Operating Current (PW) S = VCC 15 mA

ICC5 Operating Current (SE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Volta ge 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6 mA 0.4 V

VOH Output High Voltage IOH = –100 µAV

CC–0.2 V

29/36

M45PE80

Table 12. AC Characteristics

Note: 1. tCH + tCL mus t be gr eater than or equ al to 1/ fC

2. Value guarant eed by cha racteri zatio n, not 100% tes ted in producti on.

Test conditions specified in Table 8. and Table 9 .

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock Fre quen cy for the fo llowing

instructions: FAST_READ, PW, PP,

PE, SE, DP, RDP, WREN, WRDI,

RDSR

D.C. 25 MHz

fRClock Fre quen cy for READ

instructions D.C. 20 MHz

tCH 1tCLH Clock High Time 18 ns

tCL 1tCLL Cl ock Low Time 18 ns

Clock Slew Rate 2 (peak to peak) 0.03 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 10 ns

tSHCH S Not Active Setup Time (relative to C) 10 ns

tSHSL tCSH S Dese lect Time 200 ns

tSHQZ 2tDIS Output Disable Time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO O utput Hold Time 0 ns

tRLRH 2tRST Reset Pulse Width 10 µs

tRHSL tREC Reset Recovery Time 3 µs

tSHRH Chip should have been deselected

before Reset is de-asserted 10 ns

tWHSL Write Protect Setup Time 50 ns

tSHWL Write Protect Hold Time 100 ns

tDP 2S to Deep Power-down 3 µs

tRDP 2S High to Standby Mode 30 µs

tPW Page Write Cycle Time 11 25 ms

tPP Page Program Cycle Time 1.2 5 ms

tPE Page Erase Cycle Time 10 20 ms

tSE Sector Erase Cycle Time 1 5 s

M45PE80

30/36

Figu re 22 . Seri a l Input Timi ng

Figu re 23 . Wri t e Pr ote ct Se tu p and H ol d Ti m in g

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

31/36

M45PE80

Figu re 24. Ou t pu t Tim i ng

Figure 25. Reset AC Wavefo rms

AI01449D

LSB OUT

ADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

AI06808

Reset tRLRH

tRHSLtSHRH

M45PE80

32/36

P ACKAG E MECHANI CAL

Figure 26. MLP8, 8-lead Very thin Dual Flat Pack age No lead, 6x5mm , Package Ou tline

No te : Drawi ng is not to scale.

Table 13. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5m m , Packag e Mechanical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.20 0.1575 0.1496 0.1654

e 1.27 0.0500

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

θ12° 12°

VDFPN-01

A3A1

eE2

33/36

M45PE80

Figure 27. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline

No te : Drawi ng is not to scale.

Table 14. SO16 wide – 16-lead Plastic Small Ou tline, 300 mils body width, Mec han ica l Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 10.10 10.50 0.398 0.413

E 7.40 7.60 0.291 0.299

e1.27––0.050––

H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016 0.050

q0808

ddd 0.10 0.004

SO-H

LA1

ddd

h x 45˚

M45PE80

34/36

PART NUMBERING

Table 15. Ordering Information Scheme

Note: 1. Avai l abl e f or SO16 pac kage onl y

2. Availabl e for MLP pa ckag e onl y

For a list of available options (speed, package,

etc.) or for further i nformation on any aspect of this device, please contact y our nearest ST Sales O f-

fice.

Example: M45PE80 – V MP 6 T P

Device Type

M45PE = Page-Erasable Serial Flash Memory

Device Function

80 = 8Mbit (1M x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MF = SO16 (300 mil width)

MP = VDFPN8 6x5mm (MLP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape & Reel Packing

Plating Technology

blank = Standard SnPb plating

P1 = Lead-Free and RoHS compliant

G2 = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

35/36

M45PE80

REVISION HISTORY

Table 16. Document Revi sion History

Date Version Description of Revision

10-Feb-2003 1.0 Document written

02-Apr-2003 1.1 VFQFPN8 (MLP) package added

08-Apr-2003 1.2 Document promoted to Product Preview

05-May-2003 1.3 Document promoted to Preliminary Data

04-Jun-2003 1.4 Description corrected of entering Hardware Protected mode (W must be driven, and

cannot be left unconnected). Document Revision History for 05-May-2003 corrected.

26-Nov-2003 2.0 VIO(min) extended to –0.6V, and tPP(typ) improved to 1.2ms. Table of contents, SO16

package, warning about exposed paddle on MLP8, and Pb-free options added.

Change of naming for VDFPN8 package. Document promoted to full datasheet

23-Jan-2004 3.0 SO16 pin-out corrected

28-May-2004 4.0 Soldering temperature information clarified for RoHS compliant devices. Device Grade

clarified

M45PE80

36/36

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