74HC74DB - NXP SEMICONDUCTORS

1. General description

The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have

individual data (nD), clock (nCP), set (nSD) an d reset (nRD) inputs, and complementary

nQ and nQ o ut pu ts. Data at the nD-input, th at meets the set-up and hold time

requirement s on the LOW-to-HIGH clock transiti on, is stored in the flip-flop and appears at

the nQ output. Schmitt-trigge r a ction in th e clock input, makes the circuit highly tolerant to

slower clock rise and fall times. Inputs include clamp diodes tha t enable the use of curr ent

limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

Input levels:

For 74HC74: CMOS level

For 74HCT74: TTL level

Symmetrical output impedance

Low power dissipation

High noise immunity

Balanced propagation delays

Specified in compliance with JEDEC standard no. 7A

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Specified from 40 Cto+85C and from 40 Cto+125C

3. Ordering information

74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Rev. 4 — 27 August 2012 Product data sheet

Tabl e 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC74N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT74N

74HC74D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm SOT108-1

74HCT74D

74HC74DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm SOT337-1

74HCT74DB

Product data sheet Rev. 4 — 27 August 2012 2 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

4. Functional diagram

74HC74PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 lead s;

body width 4.4 mm SOT402-1

74HCT74PW

74HC74BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 30.85 mm

SOT762-1

74HCT74BQ

Tabl e 1. Ordering information …continued

Type number Package

Temperature range Name Description Version

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram

mna418

410

Q1Q

11 6

1SD

2CP

1CP

1D D

2SD

113

1RD 2RD

mna419

2C1

12 C1

10 S

13 R

Q1Q

1SD

1CP

1D D

11RD

mna420

Q2Q

2SD

2CP

2D D

13 2RD

Fig 4. Logic diagram for one flip-flop

mna421

Product data sheet Rev. 4 — 27 August 2012 3 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

5. Pinning information

5.1 Pinning

5.2 Pin description

(1) This is not a supply pin. The substrate is att ached to

this pad using conductive die attach material. There

is no electrical or mechanical requirement to solder

this pad. However, if it is soldered, the solder land

should remain floating or be connected to GND.

Fig 5. Pin configuration for DIP14, SO14 and (T)SSOP14 Fig 6. Pin configuration for DHVQFN14

+&

+&7

5' 9



5'

&3 '

6' &3



6'



4

*1' 4

DDD



























DDD

+&

+&7

7UDQVSDUHQWWRSYLHZ

4 4

4 6'

6' &3

&3 '

' 5'

*1'



*1'

4

5'

 

















WHUPLQDO

LQGH[DUHD

Table 2. Pin description

Symbol Pin Description

1RD 1 asynchronous reset-direct input (active LOW)

1D 2 data input

1CP 3 clock input (LOW-to-HIGH, edge-triggered)

1SD 4 asynchronous set-direct input (active LOW)

1Q 5 output

1Q 6 complement outp ut

GND 7 ground (0 V)

2Q 8 complement outp ut

2Q 9 output

2SD 10 asynchronous set-direct input (active LOW)

2CP 11 clock input (LOW-to-HIGH, edge-triggered)

2D 12 data input

2RD 13 asynchronous reset-direct input (active LOW)

VCC 14 supply voltage

Product data sheet Rev. 4 — 27 August 2012 4 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.

[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;

X = don’t care.

7. Limiting values

[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.

For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

Table 3. Function table[1]

Input Output

nSDnRDnCP nD nQ nQ

LHXXHL

HLXXLH

LLXXHH

Table 4. Function table[1]

Input Output

nSDnRDnCP nD nQn+1 nQn+1

HHLLH

HHHHL

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +7 V

IIK input clamping current VI < 0.5 V or VI>V

CC +0.5 V - 20 mA

IOK output clamping current VO<0.5 V or VO>V

CC +0.5V - 20 mA

IOoutput current VO = 0.5 V to (VCC +0.5V) - 25 mA

ICC supply current - +100 mA

IGND ground current 100 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation DIP14 package [1] - 750 mW

SO14, (T)SSOP14 and DHVQFN14

packages [1] - 500 mW

Product data sheet Rev. 4 — 27 August 2012 5 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

8. Recommended operating conditions

9. Static characteristics

Table 6. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC74 74HCT74 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0-V

CC V

VOoutput voltage 0 - VCC 0-V

CC V

Tamb ambient temperature 40 +25 +125 40 +25 +125 C

t/V i nput transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

VCC = 6.0 V - - 83 - - - ns/V

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit

Min Typ[1] Max Min Max

74HC74

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 V

VOH HIGH-level

output voltage VI=V

IH or VIL

IO=4.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V

IO=5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V

VOL LOW-level

output voltage VI=V

IH or VIL

IO=4.0mA; V

CC = 4.5 V - 0.15 0.33 - 0.4 V

IO=5.2mA; V

CC = 6.0 V - 0.16 0.33 - 0.4 V

IIinput leakage

current VI=V

CC or GND;

VCC =6.0V --1.0 - 1.0 A

ICC supply current VI=V

CC or GND; IO=0A;

VCC =6.0V --40 - 80A

CIinput

capacitance 3.5 pF

74HCT74

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V

Product data sheet Rev. 4 — 27 August 2012 6 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

[1] All typical values are measured at Tamb =25C.

VOH HIGH-level

output voltage VI=V

IH or VIL; VCC =4.5V

IO=4 mA 3.84 4.32 - 3.7 - V

VOL LOW-level

output voltage VI=V

IH or VIL; VCC =4.5V

IO= 4.0 mA - 0.15 0.33 - 0.4 V

IIinput leakage

current VI=V

CC or GND;

VCC =5.5V --1.0 - 1.0 A

ICC supply current VI=V

CC or GND; IO=0A;

VCC =5.5V --40 - 80A

ICC additional

supply current VI=V

CC 2.1 V;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V;

IO=0A

per input pin; nD, nRD

inputs - 70 315 - 343 A

per input pin; nSD, nCP

input - 80 360 - 392 A

CIinput

capacitance 3.5 pF

Table 7. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit

Min Typ[1] Max Min Max

Product data sheet Rev. 4 — 27 August 2012 7 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

10. Dynamic characteristics

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.

Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit

Min Typ[1] Max Min Max

74HC74

tpd propagation

delay nCP to nQ, nQ; see

Figure 7 [2]

VCC = 2.0 V - 47 220 - 265 ns

VCC = 4.5 V - 17 44 - 53 ns

VCC =5V; C

L=15pF - 14 - - - ns

VCC = 6.0 V - 14 37 - 45 ns

nSD to nQ, nQ; see

Figure 8 [2]

VCC = 2.0 V - 50 250 - 300 ns

VCC = 4.5 V - 18 50 - 60 ns

VCC =5V; C

L=15pF - 15 - - - ns

VCC = 6.0 V - 14 43 - 51 ns

nRD to nQ, nQ; see

Figure 8 [2]

VCC = 2.0 V - 52 250 - 300 ns

VCC = 4.5 V - 19 50 - 60 ns

VCC =5V; C

L=15pF - 16 - - - ns

VCC = 6.0 V - 15 43 - 51 ns

tttransition

time nQ, nQ; see Figure 7 [3]

VCC = 2.0 V - 19 95 - 110 ns

VCC = 4.5 V - 7 19 - 22 ns

VCC = 6.0 V - 6 16 - 19 ns

tWpulse width nCP HIGH or LOW;

see Figure 7

VCC = 2.0 V 100 19 - 120 - ns

VCC = 4.5 V 20 7 - 24 - ns

VCC = 6.0 V 17 6 - 20 - ns

nSD, nRD LOW;

see Figure 8

VCC = 2.0 V 100 19 - 120 - ns

VCC = 4.5 V 20 7 - 24 - ns

VCC = 6.0 V 17 6 - 20 - ns

trec recovery

time nSD, nRD; see Figure 8

VCC = 2.0 V 40 3 - 45 - ns

VCC = 4.5 V 8 1 - 9 - ns

VCC = 6.0 V 7 1 - 8 - ns

Product data sheet Rev. 4 — 27 August 2012 8 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

tsu set-up time n D to nCP; see Figure 7

VCC = 2.0 V 75 6 - 90 - ns

VCC = 4.5 V 15 2 - 18 - ns

VCC = 6.0 V 13 2 - 15 - ns

thhold time nD to nCP; see Figure 7

VCC = 2.0 V 3 6- 3 -ns

VCC = 4.5 V 3 2- 3 -ns

VCC = 6.0 V 3 2- 3 -ns

fmax maximum

frequency nCP; see Figure 7

VCC = 2.0 V 4.8 23 - 4.0 - MHz

VCC = 4.5 V 24 69 - 20 - MHz

VCC =5V; C

L=15pF - 76 - - - MHz

VCC = 6.0 V 28 82 - 24 - MHz

CPD power

dissipation

capacitance

CL=50pF;f=1 MHz;

VI=GNDtoV

[4] -24 - - -pF

74HCT74

tpd propagation

delay nCP to nQ, nQ; see

Figure 7 [2]

VCC = 4.5 V - 18 44 - 53 ns

VCC =5V; C

L=15pF - 15 - - - ns

nSD to nQ, nQ; see

Figure 8 [2]

VCC = 4.5 V - 23 50 - 60 ns

VCC =5V; C

L=15pF - 18 - - - ns

nRD to nQ, nQ; see

Figure 8 [2]

VCC = 4.5 V - 24 50 - 60 ns

VCC =5V; C

L=15pF - 18 - - - ns

tttransition

time nQ, nQ; see Figure 7 [3]

VCC = 4.5 V - 7 19 - 22 ns

tWpulse width nCP HIGH or LOW;

see Figure 7

VCC = 4.5 V 23 9 - 27 - ns

nSD, nRD LOW;

see Figure 8

VCC = 4.5 V 20 9 - 24 - ns

trec recovery

time nSD, nRD; see Figure 8

VCC = 4.5 V 8 1 - 9 - ns

tsu set-up time n D to nCP; see Figure 7

VCC = 4.5 V 15 5 - 18 - ns

Table 8. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.

Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit

Min Typ[1] Max Min Max

Product data sheet Rev. 4 — 27 August 2012 9 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

[1] All typical values are measured at Tamb =25C.

[2] tpd is the same as tPLH and tPHL.

[3] tt is the same as tTHL and tTLH.

[4] CPD is used to determine the dynamic power dissipation (PD in W).

PD=C

PD VCC2fiN+(CLVCC2fo) where:

fi = input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of outputs.

thhold time nD to nCP; see Figure 7

VCC = 4.5 V 3 3- 3 -ns

fmax maximum

frequency nCP; see Figure 7

VCC = 4.5 V 22 54 - 18 - MHz

VCC =5V; C

L=15pF - 59 - - - MHz

CPD power

dissipation

capacitance

CL=50pF;f=1 MHz;

VI=GNDtoV

CC - 1.5 V [4] -29 - - -pF

Table 8. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.

Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit

Min Typ[1] Max Min Max

Product data sheet Rev. 4 — 27 August 2012 10 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

11. Waveforms

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Input to output propagation delay, output transition time , cl oc k in pu t puls e width and maximum

frequency

WVX WVX

W3+/

W3/+

3/+

IPD[

92+

92/

*1'

Q'LQSXW

Q&3

LQSXW

Q4RXWSXW

DDD

Q4RXWSXW

7+/

W7/+











Product data sheet Rev. 4 — 27 August 2012 11 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. Set and res et pro pogation delays, pulse widths and recovery time

mna423

trec

tPHL

tPLH

GND

nSD input

GND

nRD input

nCP input

VOH

VOL

nQ output

VOH

VOL

nQ output

Table 9. Measurement points

Type Input Output

VMVM

74HC74 0.5VCC 0.5VCC

74HCT74 1.3 V 1.3 V

Product data sheet Rev. 4 — 27 August 2012 12 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Test data is given in Table 10.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig 9. Test circuit for measuring switching times

001aah768

negative

pulse

GND

positive

pulse

GND

10 %

90 %

10 % VMVM

VCC

DUT

VIVO

Table 10. Test data

Type Input Load Test

VItr, tfCLRL

74HC74 VCC 6ns 15pF, 50 pF 1ktPLH, tPHL

74HCT74 3V 6ns 15pF, 50 pF 1ktPLH, tPHL

Product data sheet Rev. 4 — 27 August 2012 13 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

12. Package outline

Fig 10. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 4 — 27 August 2012 14 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Fig 11. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 4 — 27 August 2012 15 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Fig 12. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 4 — 27 August 2012 16 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Fig 13. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 4 — 27 August 2012 17 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Fig 14. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 4 — 27 August 2012 18 of 21

NXP Semiconductors 74HC74; 74HCT74

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13. Abbreviations

14. Revision history

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT74 v.4 20120827 Product data sheet - 74HC_HCT74 v.3

Modifications: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

74HC_HCT74 v.3 20030710 Product data sheet - 74HC_HCT74_CNV v.2

74HC_HCT74_CNV v.2 19980223 Product specification - -

Product data sheet Rev. 4 — 27 August 2012 19 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or comple teness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cu stomer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification fo r product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 27 August 2012 20 of 21

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automoti ve qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74HC74; 74HCT74

Dual D-type flip-flop with set and reset; positive edge-trigger

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 August 2012

Document identifier: 74HC_HCT74

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16 Contact information. . . . . . . . . . . . . . . . . . . . . 20

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21