© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 5 1Publication Order Number:
TL594/D
TL594
Precision Switchmode
Pulse Width Modulation
Control Circuit
The TL594 is a fixed frequency, pulse width modulation control
circuit designed primarily for Switchmode power supply control.
Features
•Complete Pulse Width Modulation Control Circuitry
•On−Chip Oscillator with Master or Slave Operation
•On−Chip Error Amplifiers
•On−Chip 5.0 V Reference, 1.5% Accuracy
•Adjustable Deadtime Control
•Uncommitted Output Transistors Rated to 500 mA Source or Sink
•Output Control for Push−Pull or Single−Ended Operation
•Undervoltage Lockout
•Pb−Free Packages are Available*
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 42 V
Collector Output Voltage VC1,
VC2 42 V
Collector Output Current
(Each Transistor) (Note 1) IC1, IC2 500 mA
Amplifier Input Voltage Range VIR −0.3 to +42 V
Power Dissipation @ TA ≤ 45°C PD1000 mW
Thermal Resistance
Junction−to−Ambient (PDIP)
Junction−to−Air (TSSOP)
Junction−to−Ambient (SOIC)
RqJA 80
140
135
°C/W
Operating Junction Temperature TJ125 °C
Storage Temperature Range Tstg −55 to +125 °C
Operating Ambient Temperature Range
TL594CD, CN, CDTB TA−40 to 85 °C
Derating Ambient Temperature TA45 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Maximum thermal limits must be observed.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
SO−16
D SUFFIX
CASE 751B
TSSOP−16
DTB SUFFIX
CASE 948F
1
PDIP−16
N SUFFIX
CASE 648
1
1
MARKING
DIAGRAMS
1
16
TL594CDG
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
TL59
4DTB
ALYWG
G
See detailed ordering and shipping information in the packag
e
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
PIN CONNECTIONS
CT
RT
Ground
C1
1
Inv
Input
C2
Q2
E2
E1
1
≈0.1 V
Oscillator
VCC
5.0 V
REF
(Top View)
Noninv
Input
Inv
Input
Vref
Output
Control
VCC
Noninv
Input
Compen/PWN
Comp Input
Deadtime
Control
Error
Amp
+
−
2
3
4
5
6
7
89
10
11
12
13
14
15
16
2Error
Amp
+
−
Q1
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16
1
TL594CN
AWLYYWWG
1
16
(Note: Microdot may be in either location)
TL594
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2
RECOMMENDED OPERATING CONDITIONS
Characteristics Symbol Min Typ Max Unit
Power Supply Voltage VCC 7.0 15 40 V
Collector Output Voltage VC1, VC2 − 30 40 V
Collector Output Current (Each transistor) IC1, IC2 − − 200 mA
Amplified Input Voltage Vin 0.3 − VCC − 2.0 V
Current Into Feedback Terminal lfb − − 0.3 mA
Reference Output Current lref − − 10 mA
Timing Resistor RT1.8 30 500 kW
Timing Capacitor CT0.0047 0.001 10 mF
Oscillator Frequency fosc 1.0 40 300 kHz
PWM Input Voltage (Pins 3, 4, 13) − 0.3 − 5.3 V
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.)
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Voltage
(IO = 1.0 mA, TA = 25°C)
(IO = 1.0 mA)
Vref 4.925
4.9 5.0
−5.075
5.1
V
Line Regulation (VCC = 7.0 V to 40 V) Regline − 2.0 25 mV
Load Regulation (IO = 1.0 mA to 10 mA) Regload − 2.0 15 mV
Short Circuit Output Current (Vref = 0 V) ISC 15 40 75 mA
OUTPUT SECTION
Collector Off−State Current (VCC = 40 V, VCE = 40 V) IC(off) − 2.0 100 mA
Emitter Off−State Current (VCC = 40 V, VC = 40 V, VE = 0 V) IE(off) − − −100 mA
Collector−Emitter Saturation Voltage (Note 1)
Common−Emitter (VE = 0 V, IC = 200 mA)
Emitter−Follower (VC = 15 V, IE = −200 mA) VSAT(C)
VSAT(E) −
−1.1
1.5 1.3
2.5
V
Output Control Pin Current
Low State (VOC ≤ 0.4 V)
High State (VOC = Vref)IOCL
IOCH −
−0.1
2.0 −
20
mA
Output Voltage Rise Time
Common−Emitter (See Figure 13)
Emitter−Follower (See Figure 14)
tr−
−100
100 200
200
ns
Output Voltage Fall Time
Common−Emitter (See Figure 13)
Emitter−Follower (See Figure 14)
tf−
−40
40 100
100
ns
ERROR AMPLIFIER SECTION
Input Offset Voltage (VO (Pin 3) = 2.5 V) VIO − 2.0 10 mV
Input Offset Current (VO (Pin 3) = 2.5 V) IIO − 5.0 250 nA
Input Bias Current (VO (Pin 3) = 2.5 V) IIB − −0.1 −1.0 mA
Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C) VICR 0 to VCC−2.0 V
Inverting Input Voltage Range VIR(INV) −0.3 to VCC−2.0 V
Open Loop Voltage Gain (DVO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kW)AVOL 70 95 − dB
Unity−Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 kW)fC− 700 − kHz
Phase Margin at Unity−Gain (VO = 0.5 V to 3.5 V, RL = 2.0 kW)φm − 65 − deg.
Common Mode Rejection Ratio (VCC = 40 V) CMRR 65 90 − dB
Power Supply Rejection Ratio (DVCC = 33 V, VO = 2.5 V, RL = 2.0 kW)PSRR − 100 − dB
Output Sink Current (VO (Pin 3) = 0.7 V) IO− 0.3 0.7 − mA
Output Source Current (VO (Pin 3) = 3.5 V) IO+ −2.0 −4.0 − mA
1. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
TL594
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3
ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.)
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.
Characteristics Symbol Min Typ Max Unit
PWM COMPARATOR SECTION (Test Circuit Figure 11)
Input Threshold Voltage (Zero Duty Cycle) VTH − 3.6 4.5 V
Input Sink Current (VPin 3 = 0.7 V) II− 0.3 0.7 − mA
DEADTIME CONTROL SECTION (Test Circuit Figure 11)
Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V) IIB (DT) − −2.0 −10 mA
Maximum Duty Cycle, Each Output, Push−Pull Mode
(VPin 4 = 0 V, CT = 0.01 mF, RT = 12 kW)
(VPin 4 = 0 V, CT = 0.001 mF, RT = 30 kW)
DCmax 45
−48
45 50
−
%
Input Threshold Voltage (Pin 4)
(Zero Duty Cycle)
(Maximum Duty Cycle)
VTH −
02.8
−3.3
−
V
OSCILLATOR SECTION
Frequency
(CT = 0.001 mF, RT = 30 kW)
(CT = 0.01 mF, RT = 12 kW, TA = 25°C)
(CT = 0.01 mF, RT = 12 kW, TA = Tlow to Thigh)
fosc −
9.2
9.0
40
10
−
−
10.8
12
kHz
Standard Deviation of Frequency* (CT = 0.001 mF, RT = 30 kW)σfosc − 1.5 − %
Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C) Dfosc (DV) − 0.2 1.0 %
Frequency Change with Temperature
(DTA = Tlow to Thigh, CT = 0.01 mF, RT = 12 kW)Dfosc (DT) − 4.0 − %
UNDERVOLTAGE LOCKOUT SECTION
Turn−On Threshold (VCC Increasing, Iref = 1.0 mA)
TA = 25°C
TA = Tlow to Thigh
Vth 4.0
3.5 5.2
−6.0
6.5
V
Hysteresis
TL594C,I
TL594M
VH100
50 150
150 300
300
mV
TOTAL DEVICE
Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open)
(VCC = 15 V)
(VCC = 40 V)
ICC −
−8.0
8.0 15
18
mA
Average Supply Current (VPin 4 = 2.0 V, CT = 0.01 mF, RT = 12 kW,
VCC = 15 V, See Figure 11) −11 −mA
*Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, σ
N
n = 1
Σ (Xn − X)2
N − 1
TL594
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4
Figure 1. Representative Block Diagram
Figure 2. Timing Diagram
Capacitor CT
Feedback/PWM Comp.
Deadtime Control
Flip−Flop
Clock Input
Flip−Flop
Q
Flip−Flop
Q
Output Q1
Emitter
Output Q2
Emitter
Output
Control
6
RTCT
5
4
Deadtime
Control
Oscillator
≈0.12V
≈0.7V
0.7mA
+
1
−
−
+
−
+
+
2−
DQ
Ck
−
+
+
−
3.5V
4.9V
13
Reference
Regulator
Q1
Q2
8
9
11
10
12
VCC
VCC
12 3 1516 14 7
Error Amp
1
Feedback PWM
Comparator Input
Ref.
Output
Gnd
UV
Lockout
Flip−
Flop
Output Control
Error Amp
2
Deadtime
Comparator
PWM
Comparator
Q
This device contains 46 active transistors.
TL594
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5
APPLICATIONS INFORMATION
Description
The TL594 is a fixed−frequency pulse width modulation
control circuit, incorporating the primary building blocks
required for the control of a switching power supply. (See
Figure 1) A n i nternal− linear s awtooth o scillator i s f requency−
programmable by t wo e xternal components, RT and CT. The
approximate oscillator freq u enc y is determined by:
fosc ≈
1.1
RT • CT
For more information refer to Figure 3.
Output pulse width modulation is accomplished by
comparison of the positive sawtooth waveform across
capacitor C T to either of two control signals. The NOR gates,
which drive output transistors Q1 and Q2, are enabled only
when the flip−flop clock−input line is in its low state. This
happens only during that portion of time when the sawtooth
voltage is greater than the control signals. Therefore, an
increase i n control−signal amplitude causes a corresponding
linear decrease of output pulse width. (Refer to the Timing
Diagram shown in Figure 2.)
The control signals are external inputs that can be fed into
the deadtime control, the error amplifier inputs, or the
feedback input. The deadtime control comparator has an
effective 120 mV input offset which limits the minimum
output deadtime to approximately the first 4% of the
sawtooth−cycle time. This would result in a maximum duty
cycle on a given output of 96% with the output control
grounded, and 48% with it connected to the reference line.
Additional deadtime may be imposed on the output by
setting the deadtime−control input to a fixed voltage,
ranging between 0 V to 3.3 V.
The pulse width modulator comparator provides a means
for the error amplifiers to adjust the output pulse width from
the maximum percent on−time, established by the deadtime
control input, down to zero, as the voltage at the feedback
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
common−mode input range from −0.3 V to (VCC − 2 V), and
may be used to sense power−supply output voltage and
current. The error−amplifier outputs are active high and are
ORed together at the noninverting input of the pulse−width
modulator comparator. With this configuration, the
amplifier that demands minimum output on time, dominates
control of the loop.
Functional Table
Input/Output
Controls Output Function fout
fosc =
Grounded Single−ended PWM @ Q1 and Q2 1.0
@ Vref Push−pull Operation 0.5
When capacitor CT is discharged, a positive pulse is
generated on the output of the deadtime comparator, which
clocks the pulse−steering flip−flop and inhibits the output
transistors, Q1 and Q2. With the output−control connected
to the reference line, the pulse−steering flip−flop directs the
modulated pulses to each of the two output transistors
alternately for push−pull operation. The output frequency is
equal to half that of the oscillator. Output drive can also be
taken from Q1 or Q2, when single−ended operation with a
maximum on−time of less than 50% is required. This is
desirable when the output transformer has a ringback
winding with a catch diode used for snubbing. When higher
output−drive currents are required for single−ended
operation, Q1 and Q2 may be connected in parallel, and the
output−mode pin must be tied to ground to disable the
flip−flop. The output frequency will now be equal to that of
the oscillator.
The TL594 has an internal 5.0 V reference capable of
sourcing up to 10 mA of load current for external bias
circuits. The reference has an internal accuracy of ±1.5%
with a typical thermal drift of less than 50 mV over an
operating temperature range of 0° to 70°C.
Figure 3. Oscillator Frequency versus
Timing Resistance
1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
RT, TIMING RESISTANCE (W)
, OSCILLATOR FREQUENCY (Hz)fOSC
CT = 0.001 mFVCC = 15 V
0.01 mF
0.1 mF
Figure 4. Open Loop Voltage Gain and
Phase versus Frequency
1.0 10 100 1.0 k 10 k 100 k 1.0 M
, OPEN LOOP VOLTAGE GAIN (dB)
VOL
f, FREQUENCY (Hz)
AVOL
0
20
40
60
80
100
120
140
160
180
, EXCESS PHASE (DEGREES)φ
φ
VCC = 15 V
DVO = 3.0 V
RL = 2.0 kW
A
500 k
100 k
10 k
1.0 k
500
120
110
100
90
80
70
60
50
40
30
20
10
0
TL594
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Figure 5. Percent Deadtime versus
Oscillator Frequency Figure 6. Percent Duty Cycle versus
Deadtime Control Voltage
Figure 7. Emitter−Follower Configuration
Output Saturation Voltage versus
Emitter Current
20
18
16
14
12
10
8.0
6.0
4.0
2.0
0
500 k 1.0 k 10 k 100 k 500 k
fosc, OSCILLATOR FREQUENCY (Hz)
% DT, PERCENT DEADTIME (EACH OUTPUT
)
CT = 0.001 mF
0.01 mF
50
40
30
20
10
00 1.0 2.0 3.0 3.5
VDT, DEADTIME CONTROL VOLTAGE (IV)
% DC, PERCENT DUTY CYCLE (EACH OUTPU
T
VCC = 15 V
VOC = Vref
1.CT = 0.01 mF
1.RT = 10 kW
2.CT = 0.001 mF
1.RT = 30 kW
2
1
Figure 8. Common−Emitter Configuration
Output Saturation Voltage versus
Collector Current
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1 0 100 200 300 400
IE, EMITTER CURRENT (mA)
, SATURATION VOLTAGE (V)
CE(sat)
V
0 100 200 300 400
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
IC, COLLECTOR CURRENT (mA)
, SATURATION VOLTAGE (V)
CE(sat)
V
Figure 9. Standby Supply Current
versus Supply Voltage
10
9.8
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
00 5.0 10 15 20 25 30 35 40
CC, SUPPLY CURRENT (mA)
VCC, SUPPLY VOLTAGE (V)
I
Figure 10. Undervoltage Lockout Thresholds
versus Reference Load Current
6.0
5.5
5.0
4.5
4.0 0 5.0 10 15 20 25 30 35 40
TH, UNDERVOLTAGE LOCKOUT THRESHOLD (V)
IL, REFERENCE LOAD CURRENT (mA)
V
Turn On
Turn Off
TL594
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7
Figure 11. Error−Amplifier Characteristics Figure 12. Deadtime and Feedback Control Circuit
Figure 13. Common−Emitter Configuration
Test Circuit and Waveform
+
+
Vin
Error Amplifier
Under Test
Feedback
Terminal
(Pin 3)
Other Error
Amplifier
Vref
VCC = 15V
150
2W
Output 1
Output 2
C1
E1
C2
E2
Ref
Out
Gnd
Output
Control
(+)
(+)
(−)
(−)
Feedback
Deadtime
Error
VCC
Test
Inputs
50k
RT
CT
150
2W
Figure 14. Emitter−Follower Configuration
Test Circuit and Waveform
RL
68
VC
CL
15pF
C
E
Q
Each
Output
Transistor
15V
90%
VCC
10%
90%
10%
trtf
RL
68
VEE
CL
15pF
C
E
Q
Each
Output
Transistor
15V
90%
VEE
10%
90%
10%
trtf
−
−
Gnd
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8
Figure 15. Error−Amplifier Sensing Techniques
Figure 16. Deadtime Control Circuit Figure 17. Soft−Start Circuit
Figure 18. Output Connections for Single−Ended and Push−Pull Configurations
VOTo Output
Voltage of
System
R1
1
2
Vref
R2
+
Error
Amp
Positive Output Voltage
VO = Vref 1 + R1
3
+1
2
Vref
R2
VO
R1
Negative Output Voltage
−
To Output
Voltage of
System
Error
Amp −
VO = Vref
R1
R1
R2
Output
Control
Output
Q
RTCT
DT
Vref 4
5
6
0.001
30k
R1
R2
Max. % on Time, each output ≈ 45 −
80
1 +
Output
Q
Vref
4
DT
CS
RS
Output
Control
Single−Ended
Q1
Q2
QC
1.0 mA to
500 mA
QE
2.4 V ≤ VOC ≤ Vref
Push−Pull
Q1
Q2
C1
E1
C2
E2
1.0 mA to 250 mA
1.0 mA to 250 mA
Output
Control
0 ≤ VOC ≤ 0.4 V
C1
E1
C2
E2
R2
R2
3
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Figure 19. Slaving Two or More Control Circuits Figure 20. Operation with Vin > 40 V Using
External Zener
RT
CT
6
5
Vref
RT
CT
Master
Vref
Slave
(Additional
Circuits)
RT
CT
5
6
Vin > 40V
RS
VZ = 39V
1N975A
VCC
5.0V
Ref
12
270 Gnd
7
+Vin = 8.0V to 20V
1
2
3
15
16
+
−
−
+
Comp
OC VREF DT CTRTGnd E1E2
13144567910
1.0M
33k
0.01 0.01
VCC
C1
C2
8
11
47
47
10
+
10k
4.7k
4.7k 15k
Tip
32
+
T1
1N4934
L1
1N4934
240
+50
35V
4.7k
1.0
22
k
+
+VO = 28V
IO = 0.2A
12
All capacitors in mF
TL594
0.001
50
35V
50
25V
Tip
32
Figure 21. Pulse Width Modulated Push−Pull Converter
Test Conditions Results L1 − 3.5 mH @ 0.3 A
T1 − Primary: 20T C.T. #28 AWG
T1 − Secondary: 12OT C.T. #36 AWG
T1 − Core: Ferroxcube 1408P−L00−3CB
Line Regulation Vin = 10 V to 40 V 14 mV 0.28%
Load Regulation Vin = 28 V, IO = 1.0 mA to 1.0 A 3.0 mV 0.06%
Output Ripple Vin = 28 V, IO = 1.0 A 65 mVpp P.A.R.D.
Short Circuit Current Vin = 28 V, RL = 0.1 W1.6 A
Efficiency Vin = 28 V, IO = 1.0 A 71%
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+Vin = 10V to 40V Tip 32A
1.0mH @ 2.0A
+VO = 5.0V
IO = 1.0A
50
10V
+
5.1k
MR850
0.1
150
5.1k 5.1k
47k
1.0M
0.1
3
2
1
14
15
16
Comp
−
+
−
Vref
+
VCC C1C2
50
50V
0.001
56 4137910
CTRTD.T. O.C. Gnd E1E2
+
47k
+
500
10V
150
47
11
12 8
TL594
Figure 22. Pulse Width Modulated Step−Down Converter
Test Conditions Results
Line Regulation Vin = 8.0 V to 40 V 3.0 mV 0.01%
Load Regulation Vin = 12.6 V, IO = 0.2 mA to 200 mA 5.0 mV 0.02%
Output Ripple Vin = 12.6 V, IO = 200 mA 40 mVpp P.A.R.D.
Short Circuit Current Vin = 12.6 V, RL = 0.1 W250 mA
Efficiency Vin = 12.6 V, IO = 200 mA 72%
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping†
TL594CD −40 to 85°C SOIC−16 48 Units/Rail
TL594CDG −40 to 85°CSOIC−16
(Pb−Free) 48 Units/Rail
TL594CDR2 −40 to 85°C SOIC−16 2400 Tape & Reel
TL594CDR2G −40 to 85°CSOIC−16
(Pb−Free) 2400 Tape & Reel
TL594CN −40 to 85°C PDIP−16 25 Units/Rail
TL594CNG −40 to 85°CPDIP−16
(Pb−Free) 25 Units/Rail
TL594CDTBG* −40 to 85°C TSSOP−16* 96 Units/Rail
TL594CDTBR2G −40 to 85°C TSSOP−16* 2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
TL594
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11
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
TL594
http://onsemi.com
12
PACKAGE DIMENSIONS
TSSOP−16
DTB SUFFIX
CASE 948F−01
ISSUE A
ÇÇÇ
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
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