Machine Insertable Very low profile TTL input and outputs loads/package 2Le D Precise and stable delays Reliable hybrid construction No external components required Fan out 10TTL loads/tap, 20TTL e Operating temperature 0 to 70C e Storage temperature -55 to +125C Electrical Characteristics: VIH_ (Highlevelinputvoltage)........ tH = (Highlevelinputcurrent) ....... VIL (Lowlevelinput voltage)........ IIL (Lowtevelinput current)........ VOH (High level output voltage) ...... VOL (Low level output voltage) ...... vcc (Supply voltage)............... icc (Supplycurrent)............... Mechancial Specifications: Case: Transfer molded epoxy Leads: Phosphor bronze or equiv. solder coated Marking: White epoxy ink Also Available: Intermediate delays Non-symmetrical tap delays Tighter delay tolerances Falling edge delay specifications Non-tapped modules eee eee -2 ma Max. Senet 2.5 V Min. Sete eee eee eee 0.5 V Max. Lee eee eee eee 5.0V+0.25 VDC eee ee eee 75 ma Max. Lecce eee eee eee 2.0 To 5.0V Lecce eee eee 50 A Max. . 0.8 V Max. Input & test conditions are not limiting parameters. All digital delay modules can be operated at conditions other than specified. Since accuracies may be slightly affected, we suggest that the module be evaluated under specific operating conditions. Specifications subject to change without notice. Nominal Delays (In NS) +2 NS or 5% Whichever Is Greater Automatic Coll PIN 12 PIN 4 PIN 10 PIN 6 PIN 8 CD571A-101 5 10 15 20 25 CD571A-102 6 12 18 24 30 CD571A-103 7 14 21 28 35 CD571A-104 8 16 2A 32 a0 CD571A-105 9 18 27 36 45 CD571A-106 40 20 30 a0 50 CD571A-107 45 30 45 60 75 CD571A-108 20 40 60 80 700 D571A-109 25 50 75 100 125 CD571A-110 30 60 90 120 150 CD571A-111 40 80 120 160 200 CD571A-112 50 100 150 200 250 CD571A-113 60 120 180 240 300 CD571A-114 70 140 210 280 350 CD571A-115 80 160 240 320 400 CD571A-116 90 180 270 360 450 CDS71A-117 100 200 300 400 500 Output rise times (TPLH) 4.0 NS max. (0.75 to 2.4 V level). = 2773566 0000380 3 = 30 t- 150.030 | | 14 PIN DIP Pin numbers for reference only .800 Max. fae 8 | o>, Zs AUTO colt w @ COSTIAXXX w Qa 9 20 7 No, 1 Pin Index ye Max. Th wore 018 TYP, yp ARAL | DELAY NETWORK GND 7 oT vec 14 O- > 00 TYP, Test Conditions: 4) All measurements are made @ 5C 2) VCC is maintained @ 5.0 VDC 3) All measurements are made with no loads on outputs 4) Delays are measured @ 1.5V level 5) Delays & tolerances for leading edges only (TPLH) - falling edges (TPHL) closely matched to TPLH Input Conditions: 4) Pulse amplitude: 3.20V 2) Input rise time: 3.0 NS (10 to 90%) 3) Pulse width: 2 x total delay 4) Duty cycle: < 25%